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S6C0657
written permission of LCD Driver IC Team.
263 / 256 CHANNEL TFT-LCD GATE DRIVER
November. 1999.
Ver. 0.1
Prepared by: Jae il Byeon
Contents in this document are subject to change without notice. No part of this document may be reproduced
or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express
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S6C0657 263 / 256 CHANNEL TFT-LCD GATE DRIVER
S6C0657 Specification Revision History
Version Content Date
0.0 Original Aug.1999
0.1 The contents of page 9, 10 and 13 have been modified Nov.1999
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263 / 256 CHANNEL TFT-LCD GATE DRIVER S6C0657
CONTENTS
INTRODUCTION ....................................................................................................4
FEATURES............................................................................................................. 4
BLOCK DIAGRAM.................................................................................................5
PIN ASSIGNMENTS .............................................................................................6
PIN DESCRIPTIONS..............................................................................................7
ABSOLUTE MAXIMUM RATINGS........................................................................8
RECOMMENDED OPERATION RATINGS...........................................................8
DC CHARACTERISTICS .......................................................................................9
AC CHARACTERISTICS .....................................................................................10
AC TIMING DIAGRAM.........................................................................................11
OPERATION DESCRIPTION...............................................................................12
OPERATION METHOD.........................................................................................................12
OUTPUT PIN.........................................................................................................................12
VOLTAGE BIASING..............................................................................................................13
RECOMMENDED TIMING ....................................................................................................14
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S6C0657 263 / 256 CHANNEL TFT-LCD GATE DRIVER
INTRODUCTION
The S6C0657 is a TFT-LCD gate driver having 263 / 256 outputs. It can drive TFT panel gate ON voltage up
to 38 V. It can operate within the logic voltage 2.7 to 5.5 V.
FEATURES
• 263 / 256 outputs
• Maximum TFT panel gate ON voltage = 38 V
• Bi - directional shift register
• Logic supply voltage = 2.7 to 5.5 V
• COF (Chip On Film) available
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263 / 256 CHANNEL TFT-LCD GATE DRIVER S6C0657
BLOCK DIAGRAM
VDD
VLO
VOFF
SEL
U/D
CPV
S / R
DI/O
001
S / R
002
263 Shift Register
S / R
262
S / R
263
DO/I
OE
VGG
VOFF
Level Shifter
263 Ouput Buffer
G001 G002 G262 G263
Figure 1. Block Diagram
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S6C0657 263 / 256 CHANNEL TFT-LCD GATE DRIVER
PIN ASSIGNMENTS
G263
G262
G261
G260
G004
G003
G002
G001
S6C0657
(Top View)
VGG
VOFF
DMY1
DMY2
DMY3
DMY4
DOI
VDD
U/D
VLO
CPV
OE
CPV
VLO
SEL
VDD
DIO
DMY4
DMY3
DMY2
DMY1
VOFF
VGG
Figure 2. Pin Assignments
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263 / 256 CHANNEL TFT-LCD GATE DRIVER S6C0657
PIN DESCRIPTIONS
Symbol
DI/O
DO/I
U/D Shift direction control input I
CPV Shift clock input I
SEL
OE
G001
to
G263
VOFF
VLO Logic input low voltage I
VGG Driver positive power supply I
VDD Logic positive power supply
Pin Name I / O
Start pulse input/output I / O
Output selection input I
Output enable input I
Driver output O
Negative power supply I
Description
When these inputs operate as the input, the start pulse data is
read at the rising edge of shift clock, CPV.
When these inputs operate as the output, the start pulse output
is the next chip’ s start pulse input. The output pulse is
generated
at the falling edge of the 263th shift clock, CPV.
When U/D = H, the shift register does right shifting operation.
(Input = DI/O and output = DO/I)
When U/D = L, the shift register does left shifting operation.
(Input = DO/I and output = DI/O)
When U/D = H, DI/O → G001 →……→ G263 → DO/I
When U/D = L, DO/I → G263 →……→ G001 → DI/O
The shift register operates in synchronization with the rising
edge of this input
This input selects the number of available outputs
When SEL = H, 263 output mode
When SEL = L, 256 output mode(G129 - G135 are disabled)
This input controls the state of the driver outputs.
When OE = H, the driver output is fixed to VOFF.
When OE = L, the driver output is VGG or VOFF corresponding
to the data.
The output signals change in synchronization with the rising
edge of shift clock input, CPV.
The amplitude of the driver output is VGG - VOFF.
This input is logic and driver ground.
Always, has negative potential.
This input operates as the reference to the level conversion of
the other input.
The other logic input range: VDD - VLO
6 to 33 V
The TFT gate ON voltage is VGG - VOFF.
I 2.7 to 5.5 V
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S6C0657 263 / 256 CHANNEL TFT-LCD GATE DRIVER
ABSOLUTE MAXIMUM RATINGS (VOFF = 0 V)
Table 1. Absolute Maximum Ratings
Parameter Symbol Ratings Unit
Logic positive power supply VDD - 0.3 to 21.0 V
Driver positive power supply VGG - 0.3 to 42.0 V
Logic input low voltage VLO - 0.3 to VDD + 0.3 V
Input voltage VIN - 0.3 to VDD + 0.3 V
Operation temperature Top - 20 to 75
Storage temperature Tstg - 55 to 150
CAUTIONS
If the absolute maximum rating is exceeded momentarily, the quality of this product may be degraded.
It is desirable to use this product within the range of the absolute maximum ratings.
The power supplying order is as follows.
ON: VLO → VDD → VOFF → Control Input → VGG
OFF: VGG → Control Input → VOFF → VDD → VLO
°C
°C
RECOMMENDED OPERATION RATINGS (VLO = 0 V)
Table 2. Recommended Operation Ratings
Parameter Symbol Min. Typ. Max. Unit
Logic positive power supply VDD 2.7 - 5.5 V
Driver positive power supply VGG 6 - 33 V
Negative power supply VOFF - 15 - - 5 V
Power supply voltage VGG - VOFF 21 - 38 V
Operation frequency fCPV - - 100 kHz
Output load CL - - 1000 pF
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263 / 256 CHANNEL TFT-LCD GATE DRIVER S6C0657
DC CHARACTERISTICS (VLO = 0V)
Table 3. DC Characteristics
(Ta = - 20 to 75 °C, VGG - VOFF = 21 to 38 V, VLO - VOFF = 15 to 5 V, VDD - VLO = 2.7 to 5.5 V)
Parameter Symbol
High input voltage VIH VLO + 0.9VX
Condition Min. Max. Unit Pin used
VX = VDD - VLO
Low input voltage VIL
High output voltage
Low output voltage
LCD driver output
VOH
VOL
ROH
ON resistance
ROL
High output current
IGG Without output load - 400
IOH = - 40 µA
IOL = 40 µA
VOUT = VGG - 0.5 V,
VGG = 38 V, VOFF = 0 V
VOUT = 0.5 V,
VGG = 38 V, VOFF = 0 V
VOFF
VDD - 0.4 VDD V
VOFF VOFF + 0.4
-
-
VDD - VOFF = 3.3 V - 400
Low output current
IDD
VDD - VOFF = 19 V - 1000
Input leak current ILK - - 5 5
NOTES:
1. DI/O, DO/I, CPV, OE, U/D, SEL used.
2. When U/D = H, DO/I used, and when U/D = L, DI/O used.
3. Input swing voltage = VDD to VDD - 3.3 V
VDD V
VLO +
0.1VX
500
500
Ω
Ω
µA
µA
µA
µA
V
V
(1)
(2)
G001 to
G263
G001 to
G263
VGG
(1)
(3)
(1)
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S6C0657 263 / 256 CHANNEL TFT-LCD GATE DRIVER
AC CHARACTERISTICS (VLO = 0 V)
Table 4. AC Characteristics
(Ta = - 20 to 75 °C, VGG - VOFF = 21 to 38 V, VLO - VOFF = 15 to 5 V, VDD - VLO = 2.7 to 5.5 V)
Parameter Symbol Condition Min. Max. Unit
Clock period tCPV - 10 -
Clock pulse width tCPVH, tCPVL
Output enable input width twOE - 0.8 -
Data setup time tsDI - 0.8 -
Data hold time thDI - 0.8 Output delay time (1) tpdDO CL = 30 pF - 0.8
Output delay time (2) tpdG - 0.8
Output delay time (3) tpdOE
Duty = 50 % 4 -
CL = 300 pF
- 0.8
µs
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263 / 256 CHANNEL TFT-LCD GATE DRIVER S6C0657
DI/O (U/D=H)
DO/I (U/D=L)
CPV
OE
DO/I (U/D=H)
DI/O (U/D=L)
G1 (U/D=H)
G263 (U/D=L)
G263 (U/D=H)
G1 (U/D=L)
G2 to G262
50 %50 %
AC TIMING DIAGRAM
50 %50 %
tCPV
tpdDO tpdDO
tCPVH
50 %
50 %
50 %
tCPVL
tsDI thDI
50 % 50 %
tpdG
50 % 50 %
tpdOE
twOE
50 %
50 %50 %
tpdOE
Figure 3. AC Timing Diagram
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S6C0657 263 / 256 CHANNEL TFT-LCD GATE DRIVER
OPERATION DESCRIPTION
OPERATION METHOD
The start pulse input, DI/O (when U/D is “H” ) or DO/I (when U/D = “L”), is synchronized with the rising edge of
CPV and stored in the first shift register. While stored pulse is transferred to the next register at the next rising
edge of CPV, a new pulse is stored simultaneously. Output pin (G1 to G263) supplies VGG voltage or VOFF
voltage to the TFT-LCD panel depending on the pulse of the shift register.
The start pulse output, DO/I (when U/D is “H” ) or DI/O (when U/D = “L”), is synchronized with the falling edge of
CPV and the pulse of the last register (G1 or G263) is transferred to the next IC. The voltage level of the start
pulse output is VDD with “H” data, VOFF with “L” data
The relationship between U/D and shift data input / out pin is as follows:
Table 5. The Relationship between U/D and the Start Pulse Input / Output
output
output
Mode
263
256
U/D
state
“H” DI/O DO/I
“L” DO/I DI/O
“H” DI/O DO/I
“L” DO/I DI/O
Shift data Output level
Input Output
G1 → G2 → G3 → G4 → G5 →……→ G263
G263 → G262 → G261 → G260 →……→ G1
G1 → G2 →……→ G128 → G136 →……→ G262 → G263
G263 → G262 →……→ G136 → G128 →……→ G2 → G1
Data transfer direction
OE = L OE = H
Normal
(VGG /
VOFF)
Disable
(VOFF)
OUTPUT PIN (G1 TO G263)
If the data of the shift register to an output drive pin is “H” , the voltage level of the output is VGG and if the data
is “L” , the level of the output is VOFF. But, when OE is “H”, the voltage level of the output is VOFF irrespective of
the data of the shift register.
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263 / 256 CHANNEL TFT-LCD GATE DRIVER S6C0657
VOLTAGE BIASING
The driver negative power supply, VOFF, can be any value between VLO - 5V and VLO - 15V.
G1 to G263
VGG (31 V)
VDD (3.0V)
VLO (0 V)
VOFF (-7 V)
Input
signal
Logic
Output
Figure 4. Example of Voltage Biasing
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S6C0657 263 / 256 CHANNEL TFT-LCD GATE DRIVER
RECOMMENDED TIMING
- 263 Output mode (When SEL = "H")
When U/D = "H"
Input
DI/O
CPV
OE
G1
G2
G3
G4
G263
Output
DO/I
When U/D = "L"
Input
DO/I
CPV
OE
G263
G262
G261
G260
G1
VGG
VGG
VDD
VOFF
VOFF
VOFF
Output
DI/O
VDD
Figure 5. Recommended Timing
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VOFF
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263 / 256 CHANNEL TFT-LCD GATE DRIVER S6C0657
DI/O
- 256 Output mode (When SEL = "L")
When U/D = "H"
Input
DI/O
CPV
OE
G1
G2
G3
G4
G129 to
G135
G263
VGG
VOFF
VOFF
Output
DO/I
When U/D = "L"
Input
DO/I
CPV
OE
G263
G262
G261
G260
G135 to
G129
G1
Output
VGG
VDD
VDD
VOFF
VOFF
VOFF
VOFF
Figure 5. Recommended Timing (Continued)
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