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S71PL129JC0/S71PL129JB0/S71PL129JA0
Stacked Multi-Chip Product (MCP) Flash Memory and
pSRAM 128 Megabit (8M x 16-bit) CMOS 3.0 Volt-only
Simultaneous Operation, Page Mode Flash Memory with
64/32/16 Megabit (4M/2M/1M x 16-bit) Pseudo-Static RAM
Distinctive Characteristics
MCP Features
Power supply voltage of 2.7 to 3.1 volt
High performance
— 65ns (65ns Flash, 70ns pSRAM)
General Description
The S71PL129J series is a product line of stacked Multi-Chip Product (MCP) packages and consists of:
One S29PL129J Flash memory die
One 16M, 32M, or 64M pSRAM
The products covered by this document are listed in the table below. For details
about their specifications, please refer to the individual constituent datasheets for
further details.
Package
— 8 x 11.6 x 1.2 mm 64 ball FBGA
Operating Temperature
— –25°C to +85°C (Wireless)
— –40°C to +85°C (Industrial)
Dual CE# Flash memory
ADVANCE
INFORMATION
pSRAM
Density
Flash Memory Density
128Mb
64Mb S71PL129JC0
32Mb S71PL129JB0
16Mb S71PL129JA0
Publication Number S71PL129Jxx_00 Revision A Amendment 5 Issue Date December 23, 2004
This document contains information on a product under development at Spansion, LLC. The information is intended to help you evaluate this product. Do not design in
this product without contacting the factory. Spansion reserves the right to change or discontinue work on this proposed product without notice.
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Product Selector Guide
128 Mb Flash Memory
Device-Model# pSRAM density Flash Access time (ns) (p)SRAM Access time (ns) pSRAM type Package
S71PL129JA0-9P 16M pSRAM 65 70 Type 7 TLA064
S71PL129JB0-9Z 32M pSRAM 65 70 Type 7 TLA064
S71PL129JB0-9B 32M pSRAM 65 70 Type 2 TLA064
S71PL129JB0-9U 32M pSRAM 65 70 Type 6 TLA064
S71PL129JC0-9Z 64M pSRAM 65 70 Type 7 TLA064
S71PL129JC0-9U 64M pSRAM 65 70 Type 6 TLA064
Advance Information
2 S71PL129JC0/S71PL129JB0/S71PL129JA0 S71PL129Jxx_00_A5_E December 23, 2004
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Advance Information
S71PL129JC0/S71PL129JB0/S71PL129JA0
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . 1
MCP Features ........................................................................................................ 1
General Description . . . . . . . . . . . . . . . . . . . . . . . . 1
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .2
128 Mb Flash Memory ..........................................................................................2
MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .6
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . .7
Input/Output Description . . . . . . . . . . . . . . . . . . . 8
Pin Description ......................................................................................................8
Logic Symbol ...........................................................................................................8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . .9
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 11
TLA064—64-ball Fine-Pitch Ball Grid Array (FBGA)
8 x 11.6 mm Package ............................................................................................ 11
S29PL129J for MCP
General Description . . . . . . . . . . . . . . . . . . . . . . . . 14
Simultaneous Read/Write Operation with Zero Latency ...................... 14
Page Mode Features ........................................................................................... 14
Standard Flash Memory Features ................................................................... 14
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 19
Table 1. PL129J Device Bus Operations ................................ 19
Requirements for Reading Array Data ......................................................... 19
Random Read (Non-Page Read) ............................................................... 20
Page Mode Read .............................................................................................20
Table 2. Page Select .......................................................... 20
Simultaneous Read/Write Operation .......................................................... 20
Writing Commands/Command Sequences ................................................. 21
Accelerated Program Operation ............................................................... 21
Autoselect Functions ..................................................................................... 21
Standby Mode ........................................................................................................21
Automatic Sleep Mode ..................................................................................... 22
RESET#: Hardware Reset Pin ........................................................................ 22
Output Disable Mode ....................................................................................... 22
Table 3. S29PL129J Sector Architecture ............................... 23
Table 4. Secured Silicon Sect or A dd re sse s ............................ 29
Autoselect Mode ................................................................................................ 29
Table 5. Autoselect Codes for PL129J ................................... 30
Table 6. PL129J Boot Sector/Sector Block Addresses for Protection/
Unprotection ..................................................................... 31
Selecting a Sector Protection Mode ..............................................................32
Table 7. Sector Protection Schemes ..................................... 32
Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . 32
Persistent Sector Protection ...........................................................................32
Password Sector Protection ............................................................................32
WP# Hardware Protection .............................................................................32
Selecting a Sector Protection Mode ..............................................................32
Persistent Sector Protection . . . . . . . . . . . . . . . . 33
Persistent Protection Bit (PPB) .......................................................................33
Persistent Protection Bit Lock (PPB Lock) .................................................33
Dynamic Protection Bit (DYB) .......................................................................33
Persistent Sector Protection Mode Locking Bit ........................................35
Password Protection Mode . . . . . . . . . . . . . . . . . 35
Password and Password Mode Locking Bit ................................................36
64-bit Password ...................................................................................................36
Write Protect (WP#) .......................................................................................36
Persistent Protection Bit Lock ................................................................... 37
High Voltage Sector Protection ..................................................................... 37
Figure 1. In-System Sector Protection/Sector Unprotection
Algorithms.......................................................... .............. 38
Temporary Sector Unprotect ........................................................................39
Figure 2. Temporary Sector Unprotect Operation................... 39
Secured Silicon Sector Flash Memory Region ........................................... 39
Factory-Locked Area (64 words) ..............................................................40
Customer-Lockable Area (64 words) ......................................................40
Secured Silicon Sector Protection Bits ....................................................40
Figure 3. Secured Silic on Sector Protect Verify ...................... 41
Hardware Data Protection ..............................................................................41
Low VCC Write Inhibit .................................................................................41
Write Pulse “Glitch” Protection ................................................................41
Logical Inhibit ....................................................................................................41
Power-Up Write Inhibit ................................................................................41
Common Flash Memory Interface (CFI) . . . . . . 42
Table 8. CFI Query Identification String ................................42
Table 9. System Interface String .........................................43
Table 10. Device Geometry Definition ........................ ... ....... .43
Table 11. Primary Vendor-Specific Extend ed Que ry ................ 43
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 45
Reading Array Data ...........................................................................................45
Reset Command .................................................................................................45
Autoselect Command Sequence ....................................................................46
Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Se-
quence ....................................................................................................................46
Word Program Command Sequence ...........................................................46
Unlock Bypass Command Sequence ........................................................47
Figure 4. Program Operation............................................... 48
Chip Erase Command Sequence ...................................................................48
Sector Erase Command Sequence ................................................................49
Figure 5. Erase Operation................................................ ... 50
Erase Suspend/Erase Resume Commands ..................................................50
Password Program Command ........................................................................51
Password Verify Command .............................................................................. 51
Password Protection Mode Locking Bit Program Command ............... 51
Persistent Sector Protection Mode Locking Bit Program Command 52
Secured Silicon Sector Protection Bit Program Command .................. 52
PPB Lock Bit Set Command ............................................................................ 52
DYB Write Command ......................................................................................52
Password Unlock Command ..........................................................................52
PPB Program Command .................................................................................. 53
All PPB Erase Command .................................................................................. 53
DYB Write Command ...................................................................................... 53
PPB Lock Bit Set Command ............................................................................ 53
Command .............................................................................................................54
Command Definitions Tables .........................................................................54
Table 12. Memory Array Command Definiti ons ...................... 54
Table 13. Sector Protection Command Def inition s .................. 5 5
Write Operation Status . . . . . . . . . . . . . . . . . . . . 56
DQ7: Data# Polling ............................................................................................ 56
Figure 6. Data# Polling Algorithm........................................ 58
RY/BY#: Ready/Busy# ....................................................................................... 58
DQ6: Toggle Bit I ...............................................................................................58
Figure 7. Toggle Bit Algorithm............................................. 59
DQ2: Toggle Bit II ..............................................................................................60
Reading Toggle Bits DQ6/DQ2 .....................................................................60
DQ5: Exceeded Timing Limits ........................................................................60
DQ3: Sector Erase Timer .................................................................................61
December 23, 2004 S71PL129Jxx_00_A5 3
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Advance Information
Table 14. Write Operation St atus ......... ................................ 61
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . .62
Figure 8. Maximum Overshoo t W ave form s................... ....... ... 62
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Industrial (I) Devices ..........................................................................................63
Extended (E) Devices .........................................................................................63
Supply Voltages ....................................................................................................63
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .64
Table 15. CMOS Compatib le ................................................ 64
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 65
Test Conditions ...................................................................................................65
Figure 9. Test Setups............................. ............................ 65
Table 16. Test Specifications ............................................... 65
Switching Waveforms ........................................................................................65
Table 17. Key to Switching Waveforms ................................. 65
Figure 10. Input Waveforms and Measure m en t Levels............. 66
VCC RampRate .................................................................................................. 66
Read Operations ................................................................................................ 66
Table 18. Read-Only Operation s .......................................... 66
Figure 11. Read Operation Timings....................................... 67
Figure 12. Page Read Operation Timin gs............................... 67
Reset ......................................................................................................................68
Table 19. Hardware Reset (RESET#) .................................... 68
Figure 13. Reset Timings.................................................. ... 68
Erase/Program Operations ............................................................................. 69
Table 20. Erase and Program Operations .............................. 69
Timing Diagrams ................................................................................................. 70
Figure 14. Program Ope ration Timings.................................. 70
Figure 15. Accelerated Program Timi ng Diagram.................... 70
Figure 16. Chip/Sector Erase Operation Timi ng s..................... 71
Figure 17. Back-to-back Read/Write Cyc le Timi ngs................. 72
Figure 18. Data# Polling Timings
(During Embedded Algorithms)............................................ 72
Figure 19. Toggle Bit Timings (During Embedded Algorithms) .. 73
Figure 20. DQ2 vs. DQ6...................................................... 73
Protect/Unprotect . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 21. Temporary Sector Unprotect ................................. 74
Figure 21. Temporary Sector Unprotect Tim ing Diag ram.......... 74
Figure 22. Sector/Sector Block Protect and Unprotect Timing
Diagram............................................................................ 75
Controlled Erase Operations ..........................................................................76
Table 22. Alternate CE# Controlled Erase and
Program Operations ........................................................... 76
Table 23. Alternate CE# Controlled Write (Erase /Pro gram )
Operation Timings ............................................................. 77
Table 24. CE1#/CE2# Tim ing ............................................. 77
Figure 23. Timing Diagram for Alternati ng Between CE1# and CE2#
Control ............................................................................. 78
Table 25. Erase And Progr a mming Performance .................... 78
BGA Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . 78
pSRAM Type 6
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Functional Description . . . . . . . . . . . . . . . . . . . . . 80
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 80
AC Characteristics and Operating Conditions . 81
AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . 82
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Read Timings ........................................................................................................83
Figure 24. Read Cycle.................................................. ....... 83
Figure 25. Page Read Cycle (8 Word s Acc ess )........................ 84
Write Timings ......................................................................................................85
Figure 26. Write Cycle #1 (WE# Controlled) (See Note 8)....... 85
Figure 27. Write Cycle #2 (CE# Cont rolled ) (See Note 8) ....... 86
Deep Power-down Timing ..............................................................................86
Figure 28. Deep Power Do wn Tim in g.................................... 86
Power-on Timing ................................................................................................86
Figure 29. Power-on Timin g................................................ 86
Provisions of Address Skew ............................................................................87
Read ....................................................................................................................87
Figure 30. Read................................. ................................ 87
Write ..................................................................................................................87
Figure 31. Write................................................................ 87
pSRAM Type 1
Functional Description . . . . . . . . . . . . . . . . . . . . . 88
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 88
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .89
Timing Test Conditions . . . . . . . . . . . . . . . . . . . . 94
Output Load Circuit ..........................................................................................95
Figure 32. Output Load Circuit........................... .... ....... .... ... 95
Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . 95
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 96
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 107
Read Cycle ...........................................................................................................107
Figure 33. Timing of Read Cycle
(CE# = OE# = VIL, WE# = ZZ# = VIH).............................. 107
Figure 34. Tim i ng Waveform of Rea d Cycle
(WE# = ZZ# = VIH)............................... .......................... 108
Figure 35. Timing Waveform of Page Mode Read Cycle
(WE# = ZZ# = VIH)............................... .......................... 109
Write Cycle ..........................................................................................................110
Figure 36. Timing Waveform of Write Cycle
(WE# Control, ZZ# = VIH)................................................ 110
Figure 37. Timing Waveform of Write Cycle
(CE# Control, ZZ# = VIH)..................................... ............ 110
Figure 38. Timing Waveform of Page Mode Write Cycle
(ZZ# = VIH) .......................... ......................................... 111
Partial Array Self Refresh (PAR) .....................................................................111
Temperature Compensated Refresh (for 64Mb) .....................................112
Deep Sleep Mode ...............................................................................................112
Reduced Memory Size (for 32M and 16M) ..................................................112
Other Mode Register Settings (for 64M) ....................................................112
Figure 39. Mode Register.................................................. 113
Figure 40. Mode Registe r Update Timings (UB#, LB#, OE# are
Don’t Care)......................................................... .... ....... . 113
Figure 41. Deep Sleep Mod e - En try/ Exit Timings (for 64M)... 114
Figure 42. Deep Sleep Mode - Entry/Exit Timings
(for 32M and 16M)........................................... ........ ... ..... 114
Type 2 pSRAM
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Product Information . . . . . . . . . . . . . . . . . . . . . . 118
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . 119
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 119
Power Up ..............................................................................................................119
Figure 43. Power Up 1 (CS1# Contro lled)........................... 119
Figure 44. Power Up 2 (CS2 Controlle d).............. .... ....... .... . 119
Functional Description . . . . . . . . . . . . . . . . . . . . 120
Absolute Maximum Ratings . . . . . . . . . . . . . . . 120
DC Recommended Operating Conditions . . . . 120
4 S71PL129Jxx_00_A5 December 23, 2004
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Advance Information
DC and Operating Characteristics . . . . . . . . . . . 121
Common ...............................................................................................................121
16M pSRAM .........................................................................................................122
32M pSRAM ........................................................................................................122
64M pSRAM ........................................................................................................ 123
128M pSRAM ....................................................................................................... 123
AC Operating Conditions . . . . . . . . . . . . . . . . . 124
Test Conditions (Test Load and Test Input/Output Reference) ....... 124
Figure 45. Output Load......................................... .... ....... . 124
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 126
Read Timings ......................................................................................................126
Figure 46. Timing Waveform of Read Cycle (1).............. ....... . 126
Figure 47. Timing Waveform of Read Cycle (2).............. ....... . 126
Figure 48. Timing Waveform of Page Cycle (Page Mode Only) 127
Write Timings .................................................................................................... 127
Figure 49. Write Cycle #1 (WE# Control led )........................ 127
Figure 50. Write Cycle #2 (CS1# Contr olle d)....................... 128
Figure 51. Timing Waveform of Write Cycle(3)
(CS2 Controlled)....................................... .... ....... .... ....... . 128
Figure 52. Timing Waveform of Write Cycle(4) (UB#, LB#
Controlled)...................................................................... 129
pSRAM Type 7
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Functional Description . . . . . . . . . . . . . . . . . . . . . 131
Power Down (for 32M, 64M Only) . . . . . . . . . . . . 131
Power Down ....................................................................................................... 131
Power Down Program Sequence ................................................................. 132
Address Key ....................................................................................................... 132
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 133
Package Capacitance . . . . . . . . . . . . . . . . . . . . . . 133
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 134
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 135
Read Operation ..................................................................................................135
Write Operation ............................................................................................... 136
Power Down Parameters ...............................................................................137
Other Timing Parameters ...............................................................................137
AC Test Conditions .........................................................................................138
AC Measurement Output Load Circuits ...................................................138
Figure 53. AC Output Lo ad Circuit – 16 Mb.......................... 138
Figure 54. AC Output Load Circuit – 32 Mb and 64 Mb.......... 138
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 139
Read Timings .......................................................................................................139
Figure 55. Read Timing #1 (Basic Tim in g) .......................... 139
Figure 56. Read Timing #2 (OE# A dd ress Acces s................. 139
Figure 57. Read Timing #3 (LB# /UB# Byte Acc ess )............. 140
Figure 58. Read Timing #4 (Page Address Access after CE1#
Control Access for 32M and 64M Only) ............................... 140
Figure 59. Read Timing #5 (Random and Page Address Access for
32M and 64M Only) ......................................................... 141
Write Timings ......................................................................................................141
Figure 60. Write Timing #1 (Basi c Timi ng ).......................... 141
Figure 61. Write Timing #2 (WE# Co ntro l).......................... 142
Figure 62. Write Timing #3-1
(WE#/LB#/UB# Byte Write Contro l) .................................. 142
Figure 63. Write Timing #3-3
(WE#/LB#/UB# Byte Write Contro l) .................................. 143
Figure 64. Write Timing #3-4
(WE#/LB#/UB# Byte Write Contro l) .................................. 143
Read/Write Timings ..........................................................................................144
Figure 65. Read/Write Timing #1-1 (C E1# Cont rol) . ....... ..... 144
Figure 66. Read / Write Timing #1-2
(CE1#/WE#/OE# Contro l)................................................ 144
Figure 67. Read / Write Timing #2 (OE# , W E# Con trol ) ....... 145
Figure 68. Read / Write Timing #3
(OE#, WE#, LB#, UB# Control ) ........................................ 145
Figure 69. Power-up Timing #1......................................... 146
Figure 70. Power-up Timing #2......................................... 146
Figure 71. Power Down Entry and Exit Ti ming ..................... 146
Figure 72. Standby Entry Timing after Read or Write............ 147
Figure 73. Power Down Program Timing (for 32M/64M Only). 147
Revision Summary
December 23, 2004 S71PL129Jxx_00_A5 5
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MCP Block Diagram
CE1#f
CE2#f
WP#/ACC
RESET#
Flash-only Address
Shared Address
OE#
WE#
Advance Information
VCCf
V
V
CC
CC
Flash 1
V
SS
RY/BY#
CE#s
UB#s
LB#s
CE2#ps
CEM1#ps
CE#
UB#
LB#
V
CCS
V
CC
pSRAM
IO15-IO
DQ
to DQ
15
0
0
6 S71PL129Jxx_00_A5 December 23, 2004
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Advance Information
r
Connection Diagram
64-ball Fine-Pitch Ball Grid Array
(Top View, Balls Facing Down)
A1
NC
B6B5
RFU
RFU
C4
C3
LB#
A7
D2
A3
A0
CE1#f
M1 M10
NC NC
E2
A2
F2
A1
G2
H2
J2
D3
A6
E3
A5
F3
A4
G3
VSS
H3
OE#
J3
DQ0CE1#s
K3
DQ8
UB#
A18
A17
DQ1
DQ9
DQ10
DQ2
D4
E4
F4
G4
H4
J4
K4
C5
WP/ACC
D5
RST#f
E5
RY/BY#
DQ3
J5
VCCf
K5
DQ11
WE#C6A8
CE2s
DQ4
VCCs
RFU
RFURFU
D6
E6
A20
H6H5
J6
K6
L6L5
C7
D7
A19
E7
A9
F7
A10
G7
DQ6
H7
DQ13
J7
DQ12
K7
DQ5
C8
A11
D8
A12
E8
A13
F8
A14
G8
RFU
H8
DQ15
J8
DQ7
K8
DQ14
A10
NC
D9
A15
E9
A21
F9
CE2#
G9
A16
H9
RFU
J9
VSS
Legend
Shared
(Note 1)
Flash only
RAM only
Reserved fo
Future Use
Note: May be shared depending on density:
— A21 is shared for the 64M pSRAM configuration.
— A20 is shred for the 32M pSRAM configuration.
— A19 is shared for the 16M pSRAM configuration.
MCP Flash-only Addresses Shared Addresses
S71PL129JC0 A22 A21-A0
S71PL129JB0 A22-A21 A20-A0
S71PL129JA0 A22-A20 A19-A0
Note: It is advised to tie J5 and L5 together on the board.
December 23, 2004 S71PL129Jxx_00_A5 7
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Input/Output Description
Pin Description
A21–A0 = 22 Address Inputs (Common)
DQ15–DQ0 = 16 Data Inputs/Outputs (Common)
CE1#f = Chip Enable 1 (Flash)
CE2#f = Chip Enable 2 (Flash)
CE1#ps = Chip Enable 1 (pSRAM)
CE2ps = Chip Enable 2 (pSRAM)
OE# = Output Enable (Common)
WE# = Write Enable (Common)
RY/BY# = Ready/Busy Output
UB# = Upper Byte Control (pSRAM)
LB# = Lower Byte Control (pSRAM)
RESET# = Hardware Reset Pin, Active Low (Flash 1 )
WP#/ACC = Hardware Write Protect/Acceleration Pin (Flash)
f = Flash 3.0 volt-o nly single power supply (see Prod uct
V
CC
ps = pSRAM Power Supply
V
CC
V
SS
NC = Pin Not Connected Internally
= Device Ground (Common)
Advance Information
Selector Guide for speed options and voltage supply
tolerances)
Logic Symbol
22
A21–A0
CE1#f
CE2#f
CE1#ps
CE2ps
OE#
WE#
WP#/ACC
RESET#
UB#
16
DQ15–DQ0
R Y/BY#
LB#
8 S71PL129Jxx_00_A5 December 23, 2004
Page 9
Advance Information
Ordering Information
The order number is formed by a valid combinations of the following:
S71PL 129 J B0 BA W 9 Z 0
PACKING TYPE
0=Tray
2 = 7” Tape and Reel
3 = 13” Tape and Reel
MODEL NUMBER
See valid combinations table.
PACKAGE MODIFIER
9 = 8 x 11.6 mm, 1.2 mm height, 64 balls (TLA064)
TEMPERATURE RANGE
W=Wireless (-25°C to +85°C)
I = Industrial (-40
PACKAGE TYPE
BA = Fine-pitch BGA Lead (Pb)-free compliant package
BF = Fine-pitch BGA Lead (Pb)-free package
pSRAM DENSITY
C0 = 64 Mb pSRAM
B0 = 32 Mb pSRAM
A0 = 16 Mb pSRAM
°
C to +85°C)
PROCESS TECHNOLOGY
J = 110 nm, Floating Gate Technology
FLASH DENSITY
129 = 128Mb, dual CE#
PRODUCT FAMILY
S71PL Multi-chip Product (MCP)
3.0-volt Simultaneous Read/Write, Page Mode Flash Memory and RAM
December 23, 2004 S71PL129Jxx_00_A5 9
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Advance Information
S71PL129J Valid Combinations
Base Ordering
Part Number
S71PL129JA0
S71PL129JB0 9Z
S71PL129JB0 9B
S71PL129JB0 9U
S71PL129JC0 9Z
S71PL129JC0 9U
S71PL129JA0
S71PL129JB0 9Z
S71PL129JB0 9B
S71PL129JB0 9U
S71PL129JC0 9Z
S71PL129JC0 9U
S71PL129JA0
S71PL129JB0 9Z
S71PL129JB0 9B
S71PL129JB0 9U
S71PL129JC0 9Z
S71PL129JC0 9U
S71PL129JA0
S71PL129JB0 9Z
S71PL129JB0 9B
S71PL129JB0 9U
S71PL129JC0 9Z
S71PL129JC0 9U
Package &
Temperature
BAW
BFW
BAI
BFI
Package Modifier/
Model Number
9P
9P
9P
9P
Speed Options
Packing Type
0, 2, 3 (Note 1)65
0, 2, 3 (Note 1)65
0, 2, 3 (Note 1)65
0, 2, 3 (Note 1)65
(ns)
(p)SRAM
Type/Access
Time (ns)
pSRAM 7 / 70
pSRAM 7 / 70
pSRAM 2 / 70
pSRAM 6 / 70
pSRAM 7 / 70
pSRAM 6 / 70
pSRAM 7 / 70
pSRAM 7 / 70
pSRAM 2 / 70
pSRAM 6 / 70
pSRAM 7 / 70
pSRAM 6 / 70
pSRAM 7 / 70
pSRAM 7 / 70
pSRAM 2 / 70
pSRAM 6 / 70
pSRAM 7 / 70
pSRAM 6 / 70
pSRAM 7 / 70
pSRAM 7 / 70
pSRAM 2 / 70
pSRAM 6 / 70
pSRAM 7 / 70
pSRAM 6 / 70
Package
Marking
(Note 2)
Notes:
1. Type 0 is standard. Specify other options as required.
2. BGA package marking omits leading “S” and packing type
designator from ordering part number.
3. Contact factory for availability of any of the above OPNs. RAM
type availability may vary over time.
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released
combinations.
10 S71PL129Jxx_00_A5 December 23, 2004
Page 11
Advance Information
Physical Dimensions
TLA064—64-ball Fine-Pitch Ball Grid Array (FBGA)
8 x 11.6 mm Package
A
0.15
(2X)
eD
10
9
8
7
eE
0.20
6
5
4
3
2
1
C
E
B
C
0.15
(2X)
CORNER
A
PIN A1
A2
D
C
INDEX MARK
10
TOP VIEW
D1
SE
7
E1
J
L
K
M
7
SD
ABDCEFHG
PIN A1
CORNER
BOTTOM VIEW
A1
PACKAGE TLA 064
JEDEC N/A
D x E 11.60 mm x 8.00 mm
SYMBOL MIN NOM MAX NOTE
A --- --- 1.20 PROFILE
A1 0.17 --- --- BALL HEIGHT
A2 0.81 --- 0.97 BODY THICKNESS
D 11.60 BSC. BODY SIZE
E 8.00 BSC. BODY SIZE
D1 8.80 BSC. MATRIX FOOTPRINT
E1 7.20 BSC. MATRIX FOOTPRINT
MD 12 MATRIX SIZE D DIRECTION
ME 10 MATRIX SIZE E DIRECTION
n 64 BALL COUNT
φb 0.35 0.40 0.45 BALL DIAMETER
eE 0.80 BSC. BALL PITCH
eD 0.80 BSC BALL PITCH
SD / SE 0.40 BSC. SOLDER BALL PLACEMENT
C1,C2,C9,C10,D1,D10,E1,E10,
F1,F5,F6,F10,G1,G5,G6,G10
H1,H10,J1,J10,K1,K2,K9,K10
M2,M3,M4,M5,M6,M7,M8,M9
6
b
64X
0.15 M C A B
0.08 M C
PACKAGE
A2,A3,A4,A5,A6,A7,A8,A9 DEPOPULATED SOLDER BALLS
B1,B2,B3,B4,B7,B8,B9,B10
L1,L2,L3,L4,L7,L8,L9,L10
SIDE VIEW
C
C
0.08
NOTES:
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
4. e REPRESENTS THE SOLDER BALL GRID PITCH.
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3352 \ 16-038.22a
December 23, 2004 S71PL129Jxx_00_A5 11
Page 12
S29PL129J for MCP
128 Megabit (8 M x 16-Bit)
CMOS 3.0 Volt-only, Simultaneous Read/Write
Flash Memory with Enhanced VersatileIO
TM
Control
Datasheet
Distinctive Characteristics
Architectural Advantages
128 Mbit Page Mode devices
— Page size of 8 words: Fast page read access from
random locations within the page
Single power supply operation
— Full Voltage range: 2.7 to 3.6 volt read, erase, and
program operatio ns for battery- powered application s
Dual Chip Enable inputs (only in PL129J)
— Two CE# inputs control selection of each half of the
memory space
Simultaneous Read/Write Operation
— Data can be continuously read from one bank while
executing erase/program functions in another bank
— Zero latency switching from write to read operations
FlexBank Architecture
— 4 separate banks, with up to two simultaneous
operations per device
— CE#1 controlled banks:
Bank 1A:
- 16Mbit (4Kw x 8 and 32Kw x 31)
Bank 1B:
- 48Mbit (32Kw x 96)
— CE#2 controlled banks:
Bank 2A:
- 48 Mbit (32Kw x 96)
Bank 2B:
- 16Mbit (4Kw x 8 and 32Kw x 31)
Enhanced VersatileI/OTM (VIO) Control
— Output voltage generated and input voltages
tolerated on all control inputs and I/Os is determined
by the voltage on the V
Secured Silicon Sector region
— Up to 128 words accessible through a command
sequence
— Up to 64 factory-locked words
— Up to 64 customer-lockable words
Both top and bottom boot blocks in one device
Manufactured on 110 nm process technology
Data Retention: 20 years typical
Cycling Endurance: 1 million cycles per sector
typical
IO
pin
ADVANCE
INFORMATION
Performance Characteristics
High Performance
— Page access times as fast as 20 ns
— Random access times as fast as 55 ns
Power consumption (typical values at 10 MHz)
— 45 mA active read current
— 17 mA program/erase current
— 0.2 µA typical standby mode current
Software Features
Software command-set compatible with JEDEC
42.4 standard
— Backward compatible with Am29F, Am29LV,
Am29DL, and AM29PDL families and MBM29QM/RM,
MBM29LV, MBM29DL, MBM29PDL families
CFI (Common Flash Interface) compliant
— Provides device-specific information to the system,
allowing host software to easily reconfigure for
different Flash devices
Erase Suspend / Erase Resume
— Suspends an erase operation to allow read or
program operations in other sectors of same bank
Unlock Bypass Program command
— Reduces overall programming time when issuing
multiple program command sequences
Hardware Features
Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting program or
erase cycle completion
Hardware reset pin (RESET#)
— Hardware method to reset the device to reading
array data
WP#/ ACC (Write Protect/Acceleration) input
—At VIL, hardware level protection for the first and
last two 4K word sectors.
—At VIH, allows removal of sector protection
—At VHH, provides accelerated programming in a
factory setting
Persiste nt S ec t or Protection
— A command sector protection method to lock
combinations of individual sectors and sector groups
Publication Number S29PL129J_MCP_00 Revision A Amendment 0 Issue Date June 4, 2004
Page 13
Advance Information
to prevent program or erase operations within that
sector
— Sectors can be locked and unlocked in-system at VCC
level
Passwo rd S ec t or Protection
— A sophisticated sector protection method to lock
combinations of individual sectors and sector groups
to prevent program or erase operations within that
sector using a user-defined 64-bit password
June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 13
Page 14
General Description
The PL129J is a 128 Mbit, 3.0 volt -only Pa ge Mode and Simultaneous Rea d/W rite
Flash memory device organized as 8 Mwords.
The word-wide data (x16) appears on DQ15-DQ0. This device can be p rogrammed in-system or in standard EPROM programmers. A 12.0 V VPP is not
required for write or erase operations.
The device offers fast page access times of 20 to 30 ns, with corresponding random access times of 55 to 70 ns, respectively, allowing high speed
microprocessors to operate without wait states. To eliminate bus contention the
device has separate chip enable (CE#), write enable (WE#) and output enable
(OE#) controls. Note: Device PL129J has 2 chip enable inputs (CE1#, CE2#).
Simultaneous Read/Write Operation with Zero Latency
The Simultaneous Read/Write architecture provides simultaneous operation
by dividing the memory space into 4 banks, which can be considered to be four
separate memory arrays as far as certain operations are concerned. The device
can improve overall system performance by allowing a host system to program
or erase in one bank, then immediately and simultaneously read from another
bank with zero latency (with two simultaneous operations operating at any one
time). This releases the system from waiting for the completion of a program or
erase operation, greatly im pr ovi ng system pe rformanc e.
Advance Information
The device can be organized in both top and bottom sector configurations. The
banks are organized as follows:
Bank PL129J Sectors CE# Control
1A 16 Mbit (4 Kw x 8 and 32 Kw x 31) CE1#
1B 48 Mbit (32 Kw x 96) CE1#
2A 48 Mbit (32 Kw x 96) CE2#
2B 16 Mbit (4 Kw x 8 and 32 Kw x 31) CE2#
Page Mode Features
The page size is 8 words. After initial page access is accomplished, the page mode
operation provides fast read access speed of random locations within that page.
Standard Flash Memory Features
The device requires a single 3.0 volt power supply (2.7 V to 3.6 V) for both
read and write functions. Internally generated and regulated voltages are pro
vided for the program and erase operations.
The device is entirely command set compatible with the JEDEC 42.4 single-
power-supply Flash standard. Commands are written to the command regis
ter using standard microprocessor write timing. Register contents serve as inputs
to an internal state-machine that controls the erase and programming circuitry.
Write cycles also internally latch addresses and data needed for the programming
and erase operations. Reading data out of the device is similar to reading f rom
other Flash or EPROM devices.
-
-
Device programming occurs by executing the program command sequence. The
Unlock Bypass mode facilitates faster programming times by requiring only two
14 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004
Page 15
Advance Information
write cycles to program data instead of four. Device erasure occurs by executing
the erase command sequence.
The host system can detect whether a program or erase oper ation is complete by
reading the DQ7 (Data# Polling) and DQ6 (toggl e) status bits. After a program
or erase cycle has been completed, the device is ready to read array data or ac
cept another command.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low VCC detector that automat-
ically inhibits write operations during power transitions. The hardware sector
protection feature disables both program and erase operations in any combina
tion of sectors of memory. This can be achieved in-system or via programming
equipment.
The Erase Suspend/Erase Resume feature enables the user to put erase on
hold for any period of time to read data from, or program data to, an y sector that
is not selected for erasure. T rue background erase can thus be achieved. If a re ad
is needed from the Secured Silicon Sector area (One Time Program area) after
an erase suspend, then the user must use the proper command sequence to
enter and exit this region.
-
-
The device offers two power-saving features. When addresses have been stable
for a specified amount of time, the device enters the automatic sleep mode.
The system can also place the device into the standby mode. Power cons umption
is greatly reduced in both these modes.
The device electrically erases all bits within a sector simultaneously via FowlerNordheim tunneling. The data is programmed using hot electron injection.
June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 15
Page 16
Block Diagram
Advance Information
DQ15–DQ0
V
CC
V
SS
RESET#
WE#
CE#
OE#
Amax–A3
RY/BY# (See Note)
State
Control
Command
Register
VCC Detector Timer
PGM Voltage
Generator
Sector
Switches
Erase Voltage
Generator
V
Chip Enable
Output Enable
Logic
Y-Decoder
X-Decoder
Address Latch
IO
Input/Output
Buffers
Data Latch
Y-Gating
Cell Matrix
A2–A0
Notes:
1. RY/BY# is an open drain output.
2. For PL129J there are two CE# (CE1# and CE2#)
16 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004
Page 17
Advance Information
Simultaneous Read/Write Block Diagram (PL129J)
V
CC
V
SS
Mux
A21–A0
CE1#=L
CE2#=H
Bank 1A
Bank 1A Address
X-Decoder
OE#
Y-gate
A21–A0
RESET#
WE#
CE1#
CE2#
WP#/ACC
DQ0–DQ15
A21–A0
CONTROL
COMMAND
REGISTER
Notes:
1. Amax = A21 (PL129J)
A21–A0A21–A0
STATE
&
RY/BY#
Mux
Bank 1B Address
CE1#=H
CE2#=L
Bank 2A Address
Bank 2B Address
Status
Control
Bank 1B
X-Decoder
X-Decoder
Bank 2A
X-Decoder
Bank 2B
Y-gate
DQ15–DQ0
DQ15–DQ0
DQ15–DQ0
Mux
DQ15–DQ0
DQ15–DQ0
June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 17
Page 18
Pin Description
Amax–A0 = Address bus
DQ15–DQ0 = 16-bit data inputs/outputs/float
CE# = Chip Enable Inputs
OE# = Output Enable Input
WE# = Write Enable
V
SS
NC = Pin Not Connected Internally
RY/BY# = Ready/Busy output and open drain.
WP#/ACC = Write Protect/Acceleration Input.
V
IO
VCC =Chip Power Supply
RESET# = Hardware Reset Pin
CE1#, CE2# = Chip Enable Inputs.
Notes:
1. Amax = A21
Advance Information
= Device Ground
When RY/BY#= VIH, the device is ready to accept
read operations and commands. When RY/BY#=
, the device is either executing an embedded
V
OL
algorithm or the device is executing a hardware
reset operation.
When WP#/ACC= VIL, the highest and lowest two
4K-word sectors are write protected regardless of
other sector protection configurations. When WP#/
ACC= V
DYB or PPB is programmed. When WP#/ACC= 12V ,
program and erase operations are ac cel erated.
= Input/Output Buffer Power Supply 2.7 V to 3.6 V
(2.7 V to 3.6 V or 2.7 to 3.3 V)
CE1# controls the 64Mb in Banks 1A and 1B . CE2#
controls the 64 Mb in Banks 2A and 2B.
, these sector are unprotected unless the
IH
Logic Symbol
max+1
Amax–A0
CE#
OE#
WE#
WP#/ACC
RESET#
VIO (V
CCQ
16
DQ15–DQ0
RY/BY#
)
18 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004
Page 19
Advance Information
Device Bus Operations
This section describes the requirements and use of the device bus operations,
which are initiated through the internal command register . The command register
itself does not occupy any addressable memory location. The register is a latch
used to store the commands, along with the address and data information
needed to execute the command. The contents of the register serve as inputs to
the internal state machine. The state machine outputs dictate the function of the
device.
quired, and the resulting output. The following subsections describe each of these
operations in further detail.
Table 1 lists the device bus operations, the inputs and control levels re-
Ta b l e 1 . PL129J Device Bus Operations
Operation CE1# CE2# OE# WE# RESET# WP#/ACC
Addresses
(A21–A0)
DQ15–
DQ0
L H
Read
Write
Standby
H L
L H
H L
V
±
IO
0.3 V
VIO
0.3 V
±
L H H X A
H L H
X X
VIO
0.3 V
±
X
(Note 2)
X X High-Z
IN
A
IN
D
OUT
D
IN
Output Disable L L H H H X X High-Z
Reset X X X X L X X High-Z
Temporary Sector Unprotect
(High Voltage)
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 8.5–9.5 V, X = Don’t Care, SA = Sector
Address, A
Notes:
1. The sector protect and sector unprotect functions may also be implemented via programming equipment. See
“High Voltage Sector Protection” on page 37.”
“
2. WP#/ACC must be high when writing to upper two and lower two sector s.
= Address In, DIN = Data In, D
IN
X X X X V
= Data Out
OUT
ID
X A
IN
D
IN
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the OE# and appropriate CE# pins to VIL. In PL129J, CE1# and CE2# are the power control and
select the lower (CE1#) or upper (CE2#) halves of the device. CE# is the power
control. OE# is the output control and gates array data to the output pins. WE#
should remain at V
The internal state machine is set for reading array data upon device power-up,
or after a hardware reset. This ensures that no spurious alteration of the memory
content occurs during the power transition. No command is necessary in this
mode to obtain array data. Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid data on the device data
outputs. Each bank remains enabled for read access until the command register
contents are altered.
IH
.
See Table 24 for timing specifications and Figure 11 for the timing diagram. I
CC1
in the DC Characteristics table represents the active current specification for
reading array data.
June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 19
Page 20
Advance Information
Random Read (Non-Page Read)
Address access time (t
output data. The chip enable access time (t
dresses and stable CE# to valid data at the output inputs. The output enable
access time is the delay from the falling edge of the OE# to valid data at the out
put inputs (assuming the addresses have been stable for at leas t t
) is equal to the delay from stable addre sses to valid
ACC
) is the delay from the stable ad-
CE
ACC–tOE
time).
Page Mode Read
The device is capable of fast page mode read and is compatible with the page
mode Mask ROM read operation. This mode provides faster r ead access speed for
random locations within a page. Address bits Amax–A3 select an 8 word page,
and address bits A2–A0 select a specific word within that page. This is an asyn
chronous operation with the microprocessor supplying the specifi c word location.
-
-
The random or initial page access is t
or tCE and subsequent page read ac-
ACC
cesses (as long as the locations specified by the microprocessor falls within that
page) is equivalent to t
reassertion of CE1# or CE#2 for subsequent access has access time of t
. Here again, CE1#/CE#2 selects the device and OE# is the output control and
t
CE
. When CE1# and CE#2 are deasse rted (=VIH), the
PACC
ACC
or
should be used to gate data to the output inputs if the device is selected. Fast
page mode accesses are obtained by keeping Amax–A 3 constant and changing
A2–A0 to select the specific word within that page.
Ta b l e 2 . Page Select
Wo rd A2 A1 A0
Word 0 0 0 0
Word 1 0 0 1
Word 2 0 1 0
Word 3 0 1 1
Word 4 1 0 0
Word 5 1 0 1
Word 6 1 1 0
Word 7 1 1 1
Simultaneous Read/Write Operation
In addition to the conventional features (read, program, erase-suspend read, and
erase-suspend program), the devi ce is capa ble of reading data f rom one bank of
memory while a program or erase operation is in progress in another bank of
memory (simultaneous operation). The bank can be sel ected by bank addresses
(A21–A19) with zero latency.
The simultaneous operation can execute multi-function mode in the same bank.
Bank CE1# CE2# PL129J: A21–A20
Bank 1A 0 1 00
Bank 1B 0 1 01, 10, 11
20 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004
Page 21
Advance Information
Bank 2A 1 0 00, 01, 10
Bank 2B 1 0 11
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data
to the device and erasing sectors of memory), the system must drive WE# and
CE1# or CE#2 to V
The device features an Unlock Bypass mode to facilitate faster programming.
Once a bank enters the Unlock Bypass mode, only two write cycles are required
to program a word, instead of four.
46 has details on programming data to the de vice using both standard and Unlock
Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device.
Table 4 indicates the set of address space that each sector occup ies. A “bank ad -
dress” is the set of address bits required to uniquely select a bank. Similarly, a
“sector address” refers to the address bits required to uniquely select a sector.
“Command Definitions” on page 45 has details on erasing a sector or the entire
chip, or suspending/resuming the erase operation.
I
in the DC Characteristics table represents the active current specification for
CC2
the write mode. See the timing specification tables and timing diagrams in
set” for write operations.
, and OE# to VIH.
IL
“Word Progr am Command Sequence” on page
“Re-
Accelerated Program Operation
The device offers accelerated program oper ations through the ACC function. This
function is primarily intended to allow faster manufacturing throughput at the
factory.
If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors,
and uses the higher voltage on the pin to reduce the time required for program
operations. The system would use a two-cycle program command sequence as
required by the Unlock Bypass mode. Removing V
turns the device to normal operation. Note that VHH must not be asserted on
WP#/ACC for operations other than accelerated programming, or device damage
may result. In addition, the WP#/ACC pin should be raised to V
use. That is, the WP#/ACC pin should not be left floating or unconnected; incon
sistent behavior of the device may result.
Autoselect Functions
If the system writes the autoselect command sequence, the device enters the au toselect mode. The system can then read autoselect codes from the internal
register (which is separate from the memory array) on DQ15–DQ0. Standard
read cycle timings apply in this mode. See
page 29 and “Autoselect Command Sequence” on p age 46 for more inf ormation.
Standby Mode
When the system is not reading or writing to the device, it can place the device
in the standby mode. In this mode, current consumption is greatly reduced, and
the outputs are placed in the high impedance state, independent of the OE#
input.
from the WP#/ACC pin re-
HH
when not in
CC
“Secured Silicon Sector Addresses” on
-
June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 21
Page 22
The device enters the CMOS standby mode when the CE1# or CE#2 and RESET#
pins are both held at V
range than V
.) If CE1# or CE#2 and RESET# are held at VIH, but not within V
IH
± 0.3 V, the device is in standby mode, but the standby current is greater. The
device requires standard access time (t
either of these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device dr aws active current until the operation is completed.
I
in “DC Characteristics” represents the CMOS s tandby current specification.
CC3
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for t
ns. The automatic sleep mode is independent of the CE#, WE#, and OE# con-
30
trol signals. Standard address access timings provide new data when addresses
are changed. While in sleep mode, output data is latched and alw ays a vailable to
the system. Note that during automatic sleep mode, OE# must be at V
the device reduces current to the stated sleep mode specification.
Characteristics” represents the automatic sleep mode current specification.
Advance Information
± 0.3 V. (Note that this is a more restricted voltage
IO
) for read access when the device is in
CE
ACC
before
IH
I
in “DC
CC5
IO
+
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading
array data. When the RESET# pin is driven low for at least a period of t
device immediately terminates any operation in progress, tristates all output
pins, and ignores all read/write commands for the duration of the RESET# pulse.
The device also resets the internal state machine to reading array data. The op
eration that was interrupted should be reinitiated once the device is ready to
accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held
±0.3 V, the device draws CM OS st andby cu rrent (I
at V
SS
at VIL but not within VSS±0.3 V, the standby current is greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would
thus also reset the Flash memory , enabling the system to read the boot-up firm
ware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which re qu ires
a time of t
BY# to determine whether the reset operation is comple te. If RESET# is asserted
when a program or erase oper ation is not executing (RY/BY# pin is “1”), the reset
operation is completed within a time of t
The system can read data t
Refer to the AC Characteristics tables for RESET# parameters and to Figure 13
for the timing diagram.
(during Embedded Algorithms). The system can thus monitor RY/
READY
). If RESET# is held
CC4
(not during Embedded Algorithms).
READY
after the RESET# pin returns to VIH.
RH
, the
RP
-
-
Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The output pins
(except for RY/BY#) are placed in the highest Impedance state
22 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004
Page 23
Advance Information
Ta b l e 3 . S29PL129J Sector Architecture (Sheet 1 of 7)
Bank Sector CE1# CE2#
SA1-0 0 1 0000000000 4 000000h–000FFFh
SA1-1 0 1 0000000001 4 001000h–001FFFh
SA1-2 0 1 0000000010 4 002000h–002FFFh
SA1-3 0 1 0000000011 4 003000h–003FFFh
SA1-4 0 1 0000000100 4 004000h–004FFFh
SA1-5 0 1 0000000101 4 005000h–005FFFh
SA1-6 0 1 0000000110 4 006000h–006FFFh
SA1-7 0 1 0000000111 4 007000h–007FFFh
SA1-8 0 1 0000001XXX 32 008000h–00FFFFh
SA1-9 0 1 0000010XXX 32 010000h–017FFFh
SA1-10 0 1 0000011XXX 32 018000h–01FFFFh
SA1-11 0 1 0000100XXX 32 020000h–027FFFh
SA1-12 0 1 0000101XXX 32 028000h–02FFFFh
SA1-13 0 1 0000110XXX 32 030000h–037FFFh
SA1-14 0 1 0000111XXX 32 038000h–03FFFFh
SA1-15 0 1 0001000XXX 32 040000h–047FFFh
SA1-16 0 1 0001001XXX 32 048000h–04FFFFh
SA1-17 0 1 0001010XXX 32 050000h–057FFFh
SA1-18 0 1 0001011XXX 32 058000h–05FFFFh
SA1-19 0 1 0001100XXX 32 060000h–067FFFh
Bank 1A
SA1-20 0 1 0001101XXX 32 068000h–06FFFFh
SA1-21 0 1 0001110XXX 32 070000h–077FFFh
SA1-22 0 1 0001111XXX 32 078000h–07FFFFh
SA1-23 0 1 0010000XXX 32 080000h–087FFFh
SA1-24 0 1 0010001XXX 32 088000h–08FFFFh
SA1-25 0 1 0010010XXX 32 090000h–097FFFh
SA1-26 0 1 0010011XXX 32 098000h–09FFFFh
SA1-27 0 1 0010100XXX 32 0A0000h–0A7FFFh
SA1-28 0 1 0010101XXX 32 0A8000h–0AFFFFh
SA1-29 0 1 0010110XXX 32 0B0000h–0B7FFFh
SA1-30 0 1 0010111XXX 32 0B8000h–0BFFFFh
SA1-31 0 1 0011000XXX 32 0C0000h–0C7FFFh
SA1-32 0 1 0011001XXX 32 0C8000h–0CFFFFh
SA1-33 0 1 0011010XXX 32 0D0000h–0D7FFFh
SA1-34 0 1 0011011XXX 32 0D8000h–0DFFFFh
SA1-35 0 1 0011100XXX 32 0E0000h–0E7FFFh
SA1-36 0 1 0011101XXX 32 0E8000h–0EFFFFh
SA1-37 0 1 0011110XXX 32 0F0000h–0F7FFFh
SA1-38 0 1 0011111XXX 32 0F8000h–0FFFFFh
Sector Address (A21-
A12)
Sector Size
(Kwords)
Address Range (x16)
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Table 3. S29PL129J Sector Architecture (Sheet 2 of 7)
Bank Sector CE1# CE2#
SA1-39 0 1 0100000XXX 32 100000h–107FFFh
SA1-40 0 1 0100001XXX 32 108000h–10FFFFh
SA1-41 0 1 0100010XXX 32 110000h–117FFFh
SA1-42 0 1 0100011XXX 32 118000h–11FFFFh
SA1-43 0 1 0100100XXX 32 120000h–127FFFh
SA1-44 0 1 0100101XXX 32 128000h–12FFFFh
SA1-45 0 1 0100110XXX 32 130000h–137FFFh
SA1-46 0 1 0100111XXX 32 138000h–13FFFFh
SA1-47 0 1 0101000XXX 32 140000h–147FFFh
SA1-48 0 1 0101001XXX 32 148000h–14FFFFh
SA1-49 0 1 0101010XXX 32 150000h–157FFFh
SA1-50 0 1 0101011XXX 32 158000h–15FFFFh
SA1-51 0 1 0101100XXX 32 160000h–167FFFh
SA1-52 0 1 0101101XXX 32 168000h–16FFFFh
SA1-53 0 1 0101110XXX 32 170000h–177FFFh
SA1-54 0 1 0101111XXX 32 178000h–17FFFFh
SA1-55 0 1 0110000XXX 32 180000h–187FFFh
SA1-56 0 1 0110001XXX 32 188000h–18FFFFh
SA1-57 0 1 0110010XXX 32 190000h–197FFFh
SA1-58 0 1 0110011XXX 32 198000h–19FFFFh
SA1-59 0 1 0110100XXX 32 1A0000h–1A7FFFh
SA1-60 0 1 0110101XXX 32 1A8000h–1AFFFFh
Bank 1B
SA1-61 0 1 0110110XXX 32 1B0000h–1B7FFFh
SA1-62 0 1 0110111XXX 32 1B8000h–1BFFFFh
SA1-63 0 1 0111000XXX 32 1C0000h–1C7FFFh
SA1-64 0 1 0111001XXX 32 1C8000h–1CFFFFh
SA1-65 0 1 0111010XXX 32 1D0000h–1D7FFFh
SA1-66 0 1 0111011XXX 32 1D8000h–1DFFFFh
SA1-67 0 1 0111100XXX 32 1E0000h–1E7FFFh
SA1-68 0 1 0111101XXX 32 1E8000h–1EFFFFh
SA1-69 0 1 0111110XXX 32 1F0000h–1F7FFFh
SA1-70 0 1 0111111XXX 32 1F8000h–1FFFFFh
SA1-71 0 1 1000000XXX 32 200000h–207FFFh
SA1-72 0 1 1000001XXX 32 208000h–20FFFFh
SA1-73 0 1 1000010XXX 32 210000h–217FFFh
SA1-74 0 1 1000011XXX 32 218000h–21FFFFh
SA1-75 0 1 1000100XXX 32 220000h–227FFFh
SA1-76 0 1 1000101XXX 32 228000h–22FFFFh
SA1-77 0 1 1000110XXX 32 230000h–237FFFh
SA1-78 0 1 1000111XXX 32 238000h–23FFFFh
SA1-79 0 1 1001000XXX 32 240000h–247FFFh
SA1-80 0 1 1001001XXX 32 248000h–24FFFFh
SA1-81 0 1 1001010XXX 32 250000h–257FFFh
SA1-82 0 1 1001011XXX 32 258000h–25FFFFh
Sector Address (A21-
A12)
Sector Size
(Kwords) Address Range (x16)
24 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004
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Table 3. S29PL129J Sector Architecture (Sheet 3 of 7)
Bank Sector CE1# CE2#
SA1-83 0 1 1001100XXX 32 260000h–267FFFh
SA1-84 0 1 1001101XXX 32 268000h–26FFFFh
SA1-85 0 1 1001110XXX 32 270000h–277FFFh
SA1-86 0 1 1001111XXX 32 278000h–27FFFFh
SA1-87 0 1 1010000XXX 32 280000h–287FFFh
SA1-88 0 1 1010001XXX 32 288000h–28FFFFh
SA1-89 0 1 1010010XXX 32 290000h–297FFFh
SA1-90 0 1 1010011XXX 32 298000h–29FFFFh
SA1-91 0 1 1010100XXX 32 2A0000h–2A7FFFh
SA1-92 0 1 1010101XXX 32 2A8000h–2AFFFFh
SA1-93 0 1 1010110XXX 32 2B0000h–2B7FFFh
SA1-94 0 1 1010111XXX 32 2B8000h–2BFFFFh
SA1-95 0 1 1011000XXX 32 2C0000h–2C7FFFh
SA1-96 0 1 1011001XXX 32 2C8000h–2CFFFFh
SA1-97 0 1 1011010XXX 32 2D0000h–2D7FFFh
SA1-98 0 1 1011011XXX 32 2D8000h–2DFFFFh
SA1-99 0 1 1011100XXX 32 2E0000h–2E7FFFh
SA1-100 0 1 1011101XXX 32 2E8000h–2EFFFFh
SA1-101 0 1 1011110XXX 32 2F0000h–2F7FFFh
SA1-102 0 1 1011111XXX 32 2F8000h–2FFFFFh
SA1-103 0 1 1100000XXX 32 300000h–307FFFh
SA1-104 0 1 1100001XXX 32 308000h–30FFFFh
Bank 1B
SA1-105 0 1 1100010XXX 32 310000h–317FFFh
SA1-106 0 1 1100011XXX 32 318000h–31FFFFh
SA1-107 0 1 1100100XXX 32 320000h–327FFFh
SA1-108 0 1 1100101XXX 32 328000h–32FFFFh
SA1-109 0 1 1100110XXX 32 330000h–337FFFh
SA1-110 0 1 1100111XXX 32 338000h–33FFFFh
SA1-111 0 1 1101000XXX 32 340000h–347FFFh
SA1-112 0 1 1101001XXX 32 348000h–34FFFFh
SA1-113 0 1 1101010XXX 32 350000h–357FFFh
SA1-114 0 1 1101011XXX 32 358000h–35FFFFh
SA1-115 0 1 1101100XXX 32 360000h–367FFFh
SA1-116 0 1 1101101XXX 32 368000h–36FFFFh
SA1-117 0 1 1101110XXX 32 370000h–377FFFh
SA1-118 0 1 1101111XXX 32 378000h–37FFFFh
SA1-119 0 1 1110000XXX 32 380000h–387FFFh
SA1-120 0 1 1110001XXX 32 388000h–38FFFFh
SA1-121 0 1 1110010XXX 32 390000h–397FFFh
SA1-122 0 1 1110011XXX 32 398000h–39FFFFh
SA1-123 0 1 1110100XXX 32 3A0000h–3A7FFFh
SA1-124 0 1 1110101XXX 32 3A8000h–3AFFFFh
SA1-125 0 1 1110110XXX 32 3B0000h–3B7FFFh
SA1-126 0 1 1110111XXX 32 3B8000h–3BFFFFh
Sector Address (A21-
A12)
Sector Size
(Kwords) Address Range (x16)
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Table 3. S29PL129J Sector Architecture (Sheet 4 of 7)
Bank Sector CE1# CE2#
SA1-127 0 1 1111000XXX 32 3C0000h–3C7FFFh
SA1-128 0 1 1111001XXX 32 3C8000h–3CFFFFh
SA1-129 0 1 1111010XXX 32 3D0000h–3D7FFFh
SA1-130 0 1 1111011XXX 32 3D8000h–3DFFFFh
Bank 1B
Bank 2A
SA1-131 0 1 1111100XXX 32 3E0000h–3E7FFFh
SA1-132 0 1 1111101XXX 32 3E8000h–3EFFFFh
SA1-133 0 1 1111110XXX 32 3F0000h–3F7FFFh
SA1-134 0 1 1111111XXX 32 3F8000h–3FFFFFh
SA2-0 1 0 0000000XXX 32 000000h–007FFFh
SA2-1 1 0 0000001XXX 32 008000h–00FFFFh
SA2-2 1 0 0000010XXX 32 010000h–017FFFh
SA2-3 1 0 0000011XXX 32 018000h–01FFFFh
SA2-4 1 0 0000100XXX 32 020000h–027FFFh
SA2-5 1 0 0000101XXX 32 028000h–02FFFFh
SA2-6 1 0 0000110XXX 32 030000h–037FFFh
SA2-7 1 0 0000111XXX 32 038000h–03FFFFh
SA2-8 1 0 0001000XXX 32 040000h–047FFFh
SA2-9 1 0 0001001XXX 32 048000h–04FFFFh
SA2-10 1 0 0001010XXX 32 050000h–057FFFh
SA2-11 1 0 0001011XXX 32 058000h–05FFFFh
SA2-12 1 0 0001100XXX 32 060000h–067FFFh
SA2-13 1 0 0001101XXX 32 068000h–06FFFFh
SA2-14 1 0 0001110XXX 32 070000h–077FFFh
SA2-15 1 0 0001111XXX 32 078000h–07FFFFh
SA2-16 1 0 0010000XXX 32 080000h–087FFFh
SA2-17 1 0 0010001XXX 32 088000h–08FFFFh
SA2-18 1 0 0010010XXX 32 090000h–097FFFh
SA2-19 1 0 0010011XXX 32 098000h–09FFFFh
SA2-20 1 0 0010100XXX 32 0A0000h–0A7FFFh
SA2-21 1 0 0010101XXX 32 0A8000h–0AFFFFh
SA2-22 1 0 0010110XXX 32 0B0000h–0B7FFFh
SA2-23 1 0 0010111XXX 32 0B8000h–0BFFFFh
SA2-24 1 0 0011000XXX 32 0C0000h–0C7FFFh
SA2-25 1 0 0011001XXX 32 0C8000h–0CFFFFh
SA2-26 1 0 0011010XXX 32 0D0000h–0D7FFFh
SA2-27 1 0 0011011XXX 32 0D8000h–0DFFFFh
SA2-28 1 0 0011100XXX 32 0E0000h–0E7FF Fh
SA2-29 1 0 0011101XXX 32 0E8000h–0EFFFFh
SA2-30 1 0 0011110XXX 32 0F0000h–0F7FFFh
SA2-31 1 0 0011111XXX 32 0F8000h–0FFFFFh
SA2-32 1 0 0100000XXX 32 100000h–107FFFh
SA2-33 1 0 0100001XXX 32 108000h–10FFFFh
SA2-34 1 0 0100010XXX 32 110000h–117FFFh
SA2-35 1 0 0100011XXX 32 118000h–11FFFFh
Sector Address (A21-
A12)
Sector Size
(Kwords) Address Range (x16)
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Table 3. S29PL129J Sector Architecture (Sheet 5 of 7)
Bank Sector CE1# CE2#
SA2-36 1 0 0100100XXX 32 120000h–127FFFh
SA2-37 1 0 0100101XXX 32 128000h–12FFFFh
SA2-38 1 0 0100110XXX 32 130000h–137FFFh
SA2-39 1 0 0100111XXX 32 138000h–13FFFFh
SA2-40 1 0 0101000XXX 32 140000h–147FFFh
Bank 2A
Bank 2A
SA2-41 1 0 0101001XXX 32 148000h–14FFFFh
SA2-42 1 0 0101010XXX 32 150000h–157FFFh
SA2-43 1 0 0101011XXX 32 158000h–15FFFFh
SA2-44 1 0 0101100XXX 32 160000h–167FFFh
SA2-45 1 0 0101101XXX 32 168000h–16FFFFh
SA2-46 1 0 0101110XXX 32 170000h–177FFFh
SA2-47 1 0 0101111XXX 32 178000h–17FFFFh
SA2-48 1 0 0110000XXX 32 180000h–187FFFh
SA2-49 1 0 0110001XXX 32 188000h–18FFFFh
SA2-50 1 0 0110010XXX 32 190000h–197FFFh
SA2-51 1 0 0110011XXX 32 198000h–19FFFFh
SA2-52 1 0 0110100XXX 32 1A0000h–1A7FFFh
SA2-53 1 0 0110101XXX 32 1A8000h–1AFFFFh
SA2-54 1 0 0110110XXX 32 1B0000h–1B7FFFh
SA2-55 1 0 0110111XXX 32 1B8000h–1BFFFFh
SA2-56 1 0 0111000XXX 32 1C0000h–1C7FFFh
SA2-57 1 0 0111001XXX 32 1C8000h–1CFFFFh
SA2-58 1 0 0111010XXX 32 1D0000h–1D7FFFh
SA2-59 1 0 0111011XXX 32 1D8000h–1DFFFFh
SA2-60 1 0 0111100XXX 32 1E0000h–1E7FF Fh
SA2-61 1 0 0111101XXX 32 1E8000h–1EFFFFh
SA2-62 1 0 0111110XXX 32 1F0000h–1F7FFFh
SA2-63 1 0 0111111XXX 32 1F8000h–1FFFFFh
SA2-64 1 0 1000000XXX 32 200000h–207FFFh
SA2-65 1 0 1000001XXX 32 208000h–20FFFFh
SA2-66 1 0 1000010XXX 32 210000h–217FFFh
SA2-67 1 0 1000011XXX 32 218000h–21FFFFh
SA2-68 1 0 1000100XXX 32 220000h–227FFFh
SA2-69 1 0 1000101XXX 32 228000h–22FFFFh
SA2-70 1 0 1000110XXX 32 230000h–237FFFh
SA2-71 1 0 1000111XXX 32 238000h–23FFFFh
SA2-72 1 0 1001000XXX 32 240000h–247FFFh
SA2-73 1 0 1001001XXX 32 248000h–24FFFFh
SA2-74 1 0 1001010XXX 32 250000h–257FFFh
SA2-75 1 0 1001011XXX 32 258000h–25FFFFh
SA2-76 1 0 1001100XXX 32 260000h–267FFFh
SA2-77 1 0 1001101XXX 32 268000h–26FFFFh
SA2-78 1 0 1001110XXX 32 270000h–277FFFh
SA2-79 1 0 1001111XXX 32 278000h–27FFFFh
Sector Address (A21-
A12)
Sector Size
(Kwords) Address Range (x16)
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Table 3. S29PL129J Sector Architecture (Sheet 6 of 7)
Bank Sector CE1# CE2#
SA2-80 1 0 1010000XXX 32 280000h–287FFFh
SA2-81 1 0 1010001XXX 32 288000h–28FFFFh
SA2-82 1 0 1010010XXX 32 290000h–297FFFh
SA2-83 1 0 1010011XXX 32 298000h–29FFFFh
SA2-84 1 0 1010100XXX 32 2A0000h–2A7FFFh
SA2-85 1 0 1010101XXX 32 2A8000h–2AFFFFh
SA2-86 1 0 1010110XXX 32 2B0000h–2B7FFFh
SA2-87 1 0 1010111XXX 32 2B8000h–2BFFFFh
SA2-88 1 0 1011000XXX 32 2C0000h–2C7FFFh
Bank 2A
Bank 2B
SA2-89 1 0 1011001XXX 32 2C8000h–2CFFFFh
SA2-90 1 0 1011010XXX 32 2D0000h–2D7FFFh
SA2-91 1 0 1011011XXX 32 2D8000h–2DFFFFh
SA2-92 1 0 1011100XXX 32 2E0000h–2E7FF Fh
SA2-93 1 0 1011101XXX 32 2E8000h–2EFFFFh
SA2-94 1 0 1011110XXX 32 2F0000h–2F7FFFh
SA2-95 1 0 1011111XXX 32 2F8000h–2FFFFFh
SA2-96 1 0 1100000XXX 32 300000h–307FFFh
SA2-97 1 0 1100001XXX 32 308000h–30FFFFh
SA2-98 1 0 1100010XXX 32 310000h–317FFFh
SA2-99 1 0 1100011XXX 32 318000h–31FFFFh
SA2-100 1 0 1100100XXX 32 320000h–327FFFh
SA2-101 1 0 1100101XXX 32 328000h–32FFFFh
SA2-102 1 0 1100110XXX 32 330000h–337FFFh
SA2-103 1 0 1100111XXX 32 338000h–33FFFFh
SA2-104 1 0 1101000XXX 32 340000h–347FFFh
SA2-105 1 0 1101001XXX 32 348000h–34FFFFh
SA2-106 1 0 1101010XXX 32 350000h–357FFFh
SA2-107 1 0 1101011XXX 32 358000h–35FFFFh
SA2-108 1 0 1101100XXX 32 360000h–367FFFh
SA2-109 1 0 1101101XXX 32 368000h–36FFFFh
SA2-110 1 0 1101110XXX 32 370000h–377FFFh
SA2-111 1 0 1101111XXX 32 378000h–37FFFFh
SA2-112 1 0 1110000XXX 32 380000h–387FFFh
SA2-113 1 0 1110001XXX 32 388000h–38FFFFh
SA2-114 1 0 1110010XXX 32 390000h–397FFFh
SA2-115 1 0 1110011XXX 32 398000h–39FFFFh
SA2-116 1 0 1110100XXX 32 3A0000h–3A7FFFh
SA2-117 1 0 1110101XXX 32 3A8000h–3AFFFFh
SA2-118 1 0 1110110XXX 32 3B0000h–3B7FFFh
SA2-119 1 0 1110111XXX 32 3B8000h–3BFFFFh
SA2-120 1 0 1111000XXX 32 3C0000h–3C7FFFh
SA2-121 1 0 1111001XXX 32 3C8000h–3CFFFFh
SA2-122 1 0 1111010XXX 32 3D0000h–3D7FFFh
SA2-123 1 0 1111011XXX 32 3D8000h–3DFFFFh
Sector Address (A21-
A12)
Sector Size
(Kwords) Address Range (x16)
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Table 3. S29PL129J Sector Architecture (Sheet 7 of 7)
Bank Sector CE1# CE2#
SA2-124 1 0 1111100XXX 32 3E0000h–3E7FFFh
SA2-125 1 0 1111101XXX 32 3E8000h–3EFFFFh
SA2-126 1 0 1111110XXX 32 3F0000h–3F7FFFh
SA2-127 1 0 1111111000 4 3F8000h–3F8FFFh
SA2-128 1 0 1111111001 4 3F9000h–3F9FFFh
SA2-129 1 0 1111111010 4 3FA000h–3FAFFFh
Bank 2B
SA2-130 1 0 1111111011 4 3FB000h–3FBFFFh
SA2-131 1 0 1111111100 4 3FC000h–3FCFFFh
SA2-132 1 0 1111111101 4 3FD000h–3FDFFFh
SA2-133 1 0 1111111110 4 3FE000h–3FEFFFh
SA2-134 1 0 1111111111 4 3FF000h–3FFFFFh
Ta bl e 4 . Secured Silicon Sector Addresses
Factory-Locked Area 64 words 000000h-00003Fh
Customer-Lockable Area 64 words 000040h-00007Fh
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector
protection verification, through identifier codes output on DQ7–DQ0. This mode
is primarily intended for programming equipment to automatically match a device
to be programmed with its corresponding programming algorithm. However, the
autoselect codes can also be accessed in-system through the command register.
Sector Address (A21-
A12)
Sector Size Address Range
Sector Size
(Kwords) Address Range (x16)
When using programming equipment, the autoselect mode requires VID on address pin A9. Address pins must be as shown in Table 5. In addition, when
verifying sector protection, the sector address must appear on the appropriate
highest order address bits.
Table 5 shows the remaining address bits that are
don’t care. When all necessary bits have been set as required, the programming
equipment may then read the corresponding identifier code on DQ7–DQ0. How
ever, the autoselect codes can also be accessed in-system through the command
register , for ins tances when the device is erased or p rogrammed in a system with
out access to high voltage on the A9 pin. The command sequence is illustr ated in
Table 12. Note: If a Bank Address (BA) (on a ddress bits A21–A19) is asserted
during the third write cycle of the autoselect command, the host system can read
autoselect data that bank and then immediately read array data from the other
bank, without exiting the autoselect mode.
To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 12. This method does
not require VID. See “Autoselect Command Sequence” on page 46 for more
information.
-
-
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Ta b l e 5 . Autoselect Codes for PL129J
Description CE1# CE2# OE# WE#
Manufacturer
:
Spansion
ID
products
Read
Cycle 1
Read
Cycle 2
L H
L H X X
H L
L H
H L
L H
L H X X
H L
A21
to
A10 A9 A8 A7 A6
A12
V
I
D
V
I
D
X L L X L L L L 0001h
X L L L
A5
to
A3 A2 A1 A0
A4
L L L H 227Eh
H H H L 2221h
DQ15
to DQ0
Device ID
L H
H L
L H
H L
L H
H L
L H SA X
L H X X
H H H H 2200h
V
I
X L L L L L H L
D
V
I
X X L X L L H H
D
0001h (protected),
0000h (unprotected)
DQ7=1 (factory
locked),
DQ6=1 (factory and
customer locked)
Read
Cycle 3
Sector
Protection
Verification
Secured
Silicon
Indicator Bit
(DQ7, DQ6)
Legend: L = Logic Low = VIL, H = Logic High = VIH, BA = Bank Address, SA = Sect or Ad dress, X = Don’t care.
Note: The autoselect codes may also be accessed in-system via command sequences
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Ta b l e 6 . PL129J Boot Sector/Sector Block Addresses for Protection/Unprotection
CE1# Control CE2# Control
Sector/Sector Block
Sector Group A21-12
SA1-0 0000000000 4 Kwords
SA1-1 0000000001 4 Kwords
SA1-2 0000000010 4 Kwords
SA1-3 0000000011 4 Kwords
SA1-4 0000000100 4 Kwords
SA1-5 0000000101 4 Kwords
SA1-6 0000000110 4 Kwords
SA1-7 0000000111 4 Kwords
SA1-8 0000001XXX 32 Kwords
SA1-9 0000010XXX 32 Kwords
SA1-10 0000011XXX 32 Kwords
SA1-11 - SA1-14 00001XXXXX 128 (4x32) Kwords
SA1-15 - SA1-18 00010XXXXX 128 (4x32) Kwords
SA1-19 - SA1-22 00011XXXXX 128 (4x32) Kwords
SA1-23 - SA1-26 00100XXXXX 128 (4x32) Kwords
SA1-27 - SA1-30 00101XXXXX 128 (4x32) Kwords
SA1-31 - SA1-34 00110XXXXX 128 (4x32) Kwords
SA1-35 - SA1-38 00111XXXXX 128 (4x32) Kwords
SA1-39 - SA1-42 01000XXXXX 128 (4x32) Kwords
SA1-43 - SA1-46 01001XXXXX 128 (4x32) Kwords
SA1-47 - SA1-50 01010XXXXX 128 (4x32) Kwords
SA1-51 - SA1-54 01011XXXXX 128 (4x32) Kwords
SA1-55 - SA1-58 01100XXXXX 128 (4x32) Kwords
SA1-59 - SA1-62 01101XXXXX 128 (4x32) Kwords
SA1-63 - SA1-66 01110XXXXX 128 (4x32) Kwords
SA1-67 - SA1-70 01111XXXXX 128 (4x32) Kwords
SA1-71 - SA1-74 10000XXXXX 128 (4x32) Kwords
SA1-75 - SA1-78 10001XXXXX 128 (4x32) Kwords
SA1-79 - SA1-82 10010XXXXX 128 (4x32) Kwords
SA1-83 - SA1-86 10011XXXXX 128 (4x32) Kwords
SA1-87 - SA1-90 10100XXXXX 128 (4x32) Kwords
SA1-91 - SA1-94 10101XXXXX 128 (4x32) Kwords
SA1-95 - SA1-98 10110XXXXX 128 (4x32) Kwords
SA1-99 - SA1-102 10111XXXXX 128 (4x32) Kwords
SA1-103 - SA1-106 11000XXXXX 128 (4x32) Kwords
SA1-107 - SA1-110 11001XXXXX 128 (4x32) Kwords
SA1-111 - SA1-114 11010XXXXX 128 (4x32) Kwords
SA1-115 - SA1-118 11011XXXXX 128 (4x32) Kwords
SA1-119 - SA1-122 11100XXXXX 128 (4x32) Kwords
SA1-123 - SA1-126 11101XXXXX 128 (4x32) Kwords
SA1-127 - SA1-130 11110XXXXX 128 (4x32) Kwords
SA1-131 - SA1-134 11111XXXXX 128 (4x32) Kwords
Size
Sector/Sector Block
Sector Group A21-12
SA2-0–SA2-3 00000XXXXX 128 (4x32) Kwords
SA2-4–SA2-7 00001XXXXX 128 (4x32) Kwords
SA2-8–SA2-11 00010XXXXX 128 (4x32) Kwords
SA2-12–SA2-15 00011XXXXX 128 (4x32) Kwords
SA2-16–SA2-19 00100XXXXX 128 (4x32) Kwords
SA2-20–SA2-23 00101XXXXX 128 (4x32) Kwords
SA2-24–SA2-27 00110XXXXX 128 (4x32) Kwords
SA2-28–SA2-31 00111XXXXX 128 (4x32) Kwords
SA2-32–SA2-35 01000XXXXX 128 (4x32) Kwords
SA2-36–SA2-39 01001XXXXX 128 (4x32) Kwords
SA2-40–SA2-43 01010XXXXX 128 (4x32) Kwords
SA2-44–SA2-47 01011XXXXX 128 (4x32) Kwords
SA2-48–SA2-51 01100XXXXX 128 (4x32) Kwords
SA2-52–SA2-55 01101XXXXX 128 (4x32) Kwords
SA2-56–SA2-59 01110XXXXX 128 (4x32) Kwords
SA2-60–SA2-63 01111XXXXX 128 (4x32) Kwords
SA2-64–SA2-67 10000XXXXX 128 (4x32) Kwords
SA2-68–SA2-71 10001XXXXX 128 (4x32) Kwords
SA2-72–SA2-75 10010XXXXX 128 (4x32) Kwords
SA2-76–SA2-79 10011XXXXX 128 (4x32) Kwords
SA2-80–SA2-83 10100XXXXX 128 (4x32) Kwords
SA2-84–SA2-87 10101XXXXX 128 (4x32) Kwords
SA2-88–SA2-91 10110XXXXX 128 (4x32) Kwords
SA2-92–SA2-95 10111XXXXX 128 (4x32) Kwords
SA2-96–SA2-99 11000XXXXX 128 (4x32) Kwords
SA2-100–SA2-103 11001XXXXX 128 (4x32) Kwords
SA2-104–SA2-107 11010XXXXX 128 (4x32) Kwords
SA2-108–SA2-111 11011XXXXX 128 (4x32) Kwords
SA2-112–SA2-115 11100XXXXX 128 (4x32) Kwords
SA2-116–SA2-119 11101XXXXX 128 (4x32) Kwords
SA2-120–SA2-123 11110XXXXX 128 (4x32) Kwords
SA2-124 1111100XXX 32 Kwords
SA2-125 1111101XXX 32 Kwords
SA2-126 1111110XXX 32 Kwords
SA2-127 1111111000 4 Kwords
SA2-128 1111111001 4 Kwords
SA2-129 1111111010 4 Kwords
SA2-130 1111111011 4 Kwords
SA2-131 1111111100 4 Kwords
SA2-132 1111111101 4 Kwords
SA2-133 1111111110 4 Kwords
SA2-134 1111111111 4 Kwords
Size
June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 31
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Advance Information
Selecting a Sector Protection Mode
The device is shipped with all sectors unprotected. Optional Spansion programming services enable programming and protecting sectors at the factory prior to
shipping the device. Contact your local sales office for details.
It is possible to determine whether a sector is protected or unprotected. See “Se-
cured Silicon Sector Addresses” on page 29 for details.
Ta b l e 7 . Sector Protection Schemes
DYB PPB PPB Lock Sector State
0 0 0 Unprotected—PPB and DYB are changeable
0 0 1 Unprotected—PPB not changeable, D Y B is chan ge ab le
0 1 0
Protected—PPB and DYB are chan ge ab le1 0 0
1 1 0
0 1 1
Protected—PPB not changeable, DYB is changeable1 0 1
1 1 1
Sector Protection
The PL129J features several levels of sector protection, which can disable both
the program and erase operations in certain se ctors or s ector groups:
Persistent Sector Protection
A command sector protection method that replaces the old 12 V controlled protection method.
Password Sector Protection
A highly sophisticated protection method that requires a password before
changes to certain sectors or sector groups are permitted
WP# Hardware Protection
A write protect pin that can prevent program or erase oper ations in sectors S A1133, SA1-134, SA2-0 and SA2 - 1.
The WP# Hardware Protection feature is always available, independent of the
software managed protection method chosen.
Selecting a Sector Protection Mode
All parts default to operate in the Persistent Sector Protection mode. The customer must then choose if the Persistent or Password Protection method is most
desirable. There are two one-time programmable non-volatile bits that define
which sector protection method is used. If the Persistent Sector Protection
method is desired, programming the Persistent Sector Protection Mode Locking
Bit permanently sets the device to the Persistent Sector Protection mode. If the
Password Sector Protection method is desired, programming the Password Mode
Locking Bit permanently sets the device to the Password Sector Protection mode.
It is not possible to switch betw een t h e two protection modes once a locking bit
has been set. One of the two modes must be selected when the device is first
32 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004
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programmed. This prevents a program or virus from later setting the Password
Mode Locking Bit, which would cause an unexpected shift from the default Per
sistent Sector Protection Mode into the P a sswor d Protection Mode.
The device is shipped with all sectors unprotected. Optional Spansion programming services enable programming and protecting sectors at the factory prior to
shipping the device. Contact your local sales office for details.
It is possible to determine whether a sector is protected or unprotected. See Autoselect Mode for details.
Persistent Sector Protection
The Persistent Sector Protection method replaces the 12 V controlled protection
method in previous flash devices. This new method provides three different sec
tor protection states:
Persistently Locked—The sector is protected and cannot be changed.
Dynamically Locked—The sector is protected and can be changed by a simple
command.
Unlocked—The sector is unprotected and can be changed by a simple com-
mand.
To achieve these states, three types of “bits” are used:
-
-
Persistent Protection Bit
Persistent Protection Bit Lock
Persistent Sector Protection Mode Locking Bit
Persistent Protection Bit (PPB)
A single Persistent (non-volatile) Protection Bit is assigned to a maximum four
sectors (see the sector address tables for specific sector protection groupings).
All 4 Kword boot-block sectors have individual sector Persistent Protection Bits
(PPBs) for greater flexibility. Each PPB is individually modifiable through the PPB
Write Command.
The device erases all PPBs in parallel. If any PPB requires erasure, the devic e
must be instructed to preprogram all of the sector PPBs prior to PPB erasure. Oth
erwise, a previously erased sector PPBs can potentially be over-er ased. The flash
device does not have a built-in means of preventing sector PPBs over-erasure.
Persistent Protection Bit Lock (PPB Lock)
The Persistent Protection Bit Lock (PPB Lock) is a global volatile bit. When set to
“1”, the PPBs cannot be changed. When cleared (“0”), the PPBs are changeable.
There is only one PPB Lock bit per device. The PPB Lock is cleared after powerup or hardware reset. There is no command sequence to unlock the PPB Lock.
Dynamic Protection Bit (DYB)
A volatile protection bit is assigned for each sector. After power-up or hardware
reset, the contents of all DYBs is “0”. Each DYB is individually modifiable through
the DYB Write Command.
-
When the parts are first shipped, the PPBs are cleared, the DYBs are cleared, and
PPB Lock is defaulted to power up in the cleared state – meaning the PPBs are
changeable.
When the device is first powered on the DYBs power up cleared (sectors not protected). The Protection State for each sector is determined by the logical OR of
June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 33
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Advance Information
the PPB and the DYB related to that sector. For the sectors that have the PPBs
cleared, the DYBs control whether or not the sector is protected or unprotected.
By issuing the DYB Write command sequences, the DYBs are set or cleared, thus
placing each sector in the protected or unprotected state. These are the so-called
Dynamic Locked or Unlocked states. These states are called dynamic states be
cause it is very easy to switch back and forth between the protected and
unprotected conditions. This allows software to easily protect sectors against in
advertent changes yet does not prevent the easy removal of protection when
changes are needed. The DYBs maybe set or cleared as often as needed.
The PPBs allow for a more static, and difficult to change, level of protection. The
PPBs retain their state across power cycles because the PPBs are non- volatile. In
dividual PPBs are set with a command but must all be cleared as a group through
a complex sequence of program and erasing commands. The PPBs are also lim
ited to 100 erase cycles.
The PPB Lock bit adds an additional level of protection. Once all PPBs are programmed to the desired settings, the PPB Lock may be set to “1” . Setting the PPB
Lock disables all program and erase commands to the non-volatile PPBs. In ef
fect, the PPB Lock Bit locks the PPBs into their current state. The only way to clear
the PPB Lock is to go through a power cycle. System boot code can determine if
any changes to the PPB are needed; for example, to allow new system code to
be downloaded. If no changes are needed then the boot code can set the PPB
Lock to disable any further changes to the PPBs during system oper ati on.
-
-
-
-
-
The WP#/ACC write protect pin adds a final level of hardware protection to sectors SA1-133, SA1-134, SA2-0 and S A2- 1. When thi s pin is l ow it is not possib le
to change the contents of these sectors. These sectors generally hold system
boot code. The WP#/ACC pin can prevent any changes to the boot code that could
override the choices made while setting up sector protection during system
initialization.
For customers who are concerned about malicious viruses there is another level
of security - the persistently locked state. To persistently protect a given sector
or sector group, the PPBs associated with that sector need to be set to “1”. Once
all PPBs are programmed to the desired settings, the PPB Lock should be set to
“1” . Setting the PPB Lock automatically disables all progr am and erase commands
to the Non-Volatile PPBs. In effect, the PPB Lock “freezes” the PPBs into their c ur
rent state. The only way to clear the PPB Lock is to go through a power cycle.
It is possible to have sectors that have been persistently locked, and sectors that
are left in the dynamic state. The sectors in the dynamic state are all unprote cted.
If there is a need to protect some of them, a simp le DYB Write command se
quence is all that is necessary. The DYB write command for the dynamic sectors
switch the DYBs to signify protected and unprotected, respectively. If there is a
need to change the status of the persistently locked sectors, a few more steps
are required. First, the PPB Lock bit must be disabled by either putting the device
through a power-cycle, or hardware reset. The PPBs can then be changed to re
flect the desired settings. Setting the PPB lock bit once again lock the PPBs, and
the device operates normally agai n.
-
-
-
The best protection is achieved by executing the PPB lock bit set command e arly
in the boot code, and protect the boot code by holding WP#/ACC = VIL.
T able 17 contains all possi ble combinations of the DYB, PPB, and PPB lock relating
to the status of the sector.
34 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004
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In summary , if the PPB is set, and the PPB lock is set, the sector is protected and
the protection can not be removed until the next power cycle clears the PPB lock.
If the PPB is cleared, the sector can be dynamically locked or unlocked. The DYB
then controls whether or not the sector is protected or unprotected.
If the user attempts to program or erase a protected sector, the device ignores
the command and returns to read mode. A program command to a protected sec
tor enables status polling for approximately 1 µs before the device returns to read
mode without having modified the contents of the protected sector. An erase
command to a protected sector enables status polling for approximately 50 µs
after which the device returns to read mode without having erased the protected
sector.
The programming of the DYB, PPB, and PPB lock for a given sector can be verified
by writing a DYB/PPB/PPB lock verify command to the device. There is an alter
native means of reading the protection status. Take RESET# to VIL and hold WE#
at VIH.(The high voltage A9 Autoselect Mode also works for reading the status of
the PPBs). Scanning the addresses (A18–A 11) while (A6, A1, A0) = (0, 1, 0) pro
duces a logical ‘1” code at device output DQ0 for a protected sector or a “0” for
an unprotected sector . In this mode, the other addresses are don’t cares. Address
location with A1 = VIL are reserved for a utoselect manufacturer and device
codes.
-
-
-
Persistent Sector Protection Mode Locking Bit
Like the password mode locking bit, a Persistent Sector Protection mode locking
bit exists to guarantee that the device remain in software sector protection. Once
set, the Persistent Sector Protection locking bit prevents programming of the
password protection mode locking bit. This guarantees that a hacker could not
place the device in password protection mode.
Password Protection Mode
The Password Sector Protection Mode method allows an even higher level of security than the Persistent Sector Protection Mode. There are two main differences
between the Persistent Sector Protection and the Password Sector Protection
Mode:
When the device is first powered on, or comes out of a reset cycle, the PPB Lock
bit set to the locked state, rather than cleared to the unlocked state.
The only means to clear the PPB Lock bit is by writing a unique 64-bit Password
to the device.
The Password Sector Protection method is otherwise identical to the Persistent
Sector Protection method.
A 64-bit password is the only additional tool utilized in this method.
Once the Password Mode Locking Bit is se t, the password is permanently set with
no means to read, program, or erase it. The password is used to clear the PPB
Lock bit. The Password Unlock command must be written to the flash, along with
a password. The flash device internally compares the given password with the
pre-programmed password. If they match, the PPB Lock bit is cleared, and the
PPBs can be altered. If they do not match, the flash device does nothing. There
is a built-in 2 µs delay for each “password check.” This delay is intended to thwart
any efforts to run a program that tries all possible combinations in order to cr ack
the password.
June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 35
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Password and Password Mode Locking Bit
In order to select the Password sector protection scheme, the customer must first
program the password. The password may be correlated to the unique Electronic
Serial Number (ESN) of the particular flash device. Each ESN is different for every
flash device; therefore each password should be different for every flash device.
While programming in the password region, the customer may perform P assword
Verify operations.
Once the desired password is programmed in, the customer must then set the
Password Mode Locking Bit. This operation achi eves two objectives:
Permanently sets the device to operate using the P assword Protection Mode. It is
not possible to reverse this function.
Disables all further commands to the password region. All program, and read operations are ignored.
Both of these objectives are important, and if not carefully considered , may le ad
to unrecoverable errors. The user must be sure that the Password Protection
method is desired when setting the Password Mode Locking Bit. More importantly ,
the user must be sure that the password is correct when the Password Mode
Locking Bit is set. Due to the fact that read operations are disabled, there is no
means to verify what the password is afterwards. If the password is lost afte r set
ting the Password Mode Locking Bit, there is not any way to clear the PPB Lock bit.
-
The Password Mode Locking Bit, once set, prevents reading the 64-bit password
on the DQ bus and further password programming. The Password Mode Locking
Bit is not erasable. Once Password Mode Locking Bit is programmed, the Persis
tent Sector Protection Locking Bit is disabled from programming, guaranteeing
that no changes to the protection scheme are allowed.
64-bit Password
The 64-bit Password is located in its own memory space and is accessi ble through
the use of the Password Program and Verify commands (see “Password Verify
Command”). The password functio n works in conjunction with the Password
Mode Locking Bit, which when set, prevents the Password Verify command from
reading the contents of the password on the pins of the device.
Write Protect (WP#)
The Write Protect feature provides a hardware method of protecting the upper
two and lower two sectors(PL127J: 0, 1, 268, and 269, PL064J: 0, 1, 140, and
141, PL032J: 0, 1, 76, and 77, PL129J: SA1-133, SA1-134,SA2-0 and SA2-1)
without using V
viously discussed method, “High Voltage Sector Protection” on page 37.
If the system asserts VIL on the WP#/ACC pin, the device disables program and
erase functions in the two outermost 4 Kword sectors on both ends of the flash
array independent of whether it was previously protected or unprotected.
If the system asserts VIH on the WP#/ACC pin, the device reverts the upper two
and lower two sectors to whether they were last set to be protected or unpro
tected. That is, sector protection or unprotection for these sectors depends on
whether they were last protected or unprotected using the method described in
“High Voltage Sector Prote ction ” on page 37.
. This function is provided by the WP# pin and overrides the pre-
ID
-
-
Note that the WP#/ACC pin must not be left floating or unconnected; inconsistent
behavior of the device may result.
36 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004
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Persistent Protection Bit Lock
The Persistent Protection Bit (PPB) Lock is a volatile bit that reflects the state of
the Password Mode Locking Bit after power- up reset. If the Password Mode Lock
Bit is also set after a hardware reset (RESET# asserted) or a power-up reset, the
ONLY means for clearing the PPB Lock Bit in Password Protection Mode is to issue
the Password Unlock command. Successful execution of the Password Unlock
command clears the PPB Lock Bit, allowing for sector PPBs modifications. Assert
ing RESET#, taking the device through a power-on reset, or issuing the PPB Lock
Bit Set command sets the PPB Lock Bit to a “1” when the Password Mode Lock Bit
is not set.
If the Password Mode Locking Bit is not set, including Persistent Protection Mode,
the PPB Lock Bit is cleared after power-up or hardware reset. The PPB Lock Bit is
set by issuing the PPB Lock Bit Set command. Once set the only means for clear
ing the PPB Lock Bit is by issuing a hardware or power-up reset. The Password
Unlock command is ignored in Persistent Protection Mode.
High Voltage Sector Protection
Sector protection and unprotection may also be implemented using programming
equipment. The procedure requires high voltage (V
SET# pin. Refer to Figure 1 for details on this procedure. Note that for sector
unprotect, all unprotected sectors must first be protected prior to the first sector
write cycle.
) to be placed on the RE-
ID
-
-
June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 37
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Advance Information
Temporary Sector
Unprotect Mode
Increment
PLSCNT
No
PLSCNT
= 25?
Yes
Remove VID
from RESET#
Write reset
command
Sector Protect
complete
Device failed
Sector Protect
Algorithm
START
PLSCNT = 1
RESET# = V
Wait 4 µs
No
First Write
Cycle = 60h?
Set up sector
address
Sector Protect:
Write 60h to sector
address with
A7-A0 =
00000010
Wait 100 µs
Verify Sector
Protect: Write 40h
to sector address
with A7-A0 =
00000010
Read from
sector address
with A7-A0 =
00000010
No
Data = 01h?
Protect another
sector?
Remove V
from RESET#
Write reset
command
Sector Protect
complete
Yes
Yes
No
START
Protect all sectors:
The indicated portion
of the sector protect
ID
Reset
PLSCNT = 1
Yes
ID
algorithm must be
performed for all
unprotected sectors
prior to issuing the
first sector
unprotect address
Increment
PLSCNT
PLSCNT
= 1000?
Remove VID
from RESET#
Write reset
command
Sector Unprotect
complete
Device failed
No
Yes
PLSCNT = 1
RESET# = V
Wait 4 µs
First Write
Cycle = 60h?
No
All sectors
protected?
Set up first sector
address
Sector Unprotect:
Write 60h to sector
address with
A7-A0 =
01000010
Wait 1.2 ms
Verify Sector
Unprotect: Write
40h to sector
address with
A7-A0 =
00000010
Read from
sector address
with A7-A0 =
00000010
No
Data = 00h?
Last sector
verified?
Remove V
from RESET#
Write reset
command
Sector Unprotect
complete
Yes
Yes
Yes
Yes
ID
No
Temporary Sector
Unprotect Mode
Set up
next sector
address
No
ID
Sector Unprotect
Algorithm
Figure 1. In-System Sector Protection/Sector Unprotection Algorithms
38 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004
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Advance Information
Temporary Sector Unprotect
This feature allows temporary unprotection of previously protected sectors to
change data in-system. The Sector Unprotect mode is activated by setting the
RESET# pin to
grammed or erased by selecting the sector addresses. Once VID is removed from
the RESET# pin, all the previously protected sectors are protected
Figure 2 shows the algorithm, and Figure 21 shows the timing diagrams, for this
feature. While PPB lock is set, the device cannot enter the Temporary Sector Unprotection Mode.
VID. During this mode, formerly protected sectors can be pro-
again.
START
RESET# = V
(Note 1)
Perform Erase or
Program Operations
RESET# = V
Temporary Sector
Unprotect Completed
(Note 2)
Notes:
1. All protected sectors are unprotected (If WP#/ACC = VIL, upper two and lower
two sectors remain protected).
2. All previously protected sectors are protected once again
ID
IH
Figure 2. Temporary Sector Unprotect Operation
Secured Silicon Sector Flash Memory Region
The Secured Silicon Sector feature provides a Flash memory regio n that enables
permanent part identification through an Electronic Serial Number (ESN) The
128-word Secured Silicon sector is divided into 64 factory-lockable words that
can be programmed and locked by the customer. The Secured Silicon sector is
located at addresses 000000h-00007Fh in both Persistent Protection mode and
Password Protection mode. Indicator bits DQ6 and DQ7 are used to indicate the
factory-locked and customer locked status of the part.
The system accesses the Secured Silicon Sector through a command sequence
“Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Se-
(see
quence” on page 46). After the system has written the Enter Secured Silicon
Sector command sequence, it may read the Secured Silicon Sector by using the
addresses normally occupied by the boot sectors. This mode of oper ation contin
ues until the system issues the Exit Secured Silicon Sector command sequence,
or until power is removed from the device. On power-up, or following a hardware
reset, the device reverts to sending commands to the normal address space. Note
that the ACC function and unlock bypass modes are not available when the Se
cured Silicon Sector is enabled.
-
-
June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 39
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Advance Information
Factory-Locked Area (64 words)
The factory-locked area of the Secured Silicon Sector (000000h-00003Fh) is
locked when the part is shipped, whether or not the area was programmed at the
factory. The Secured Silicon Sector Factory-locked Indicator Bit (DQ7) is perma
nently set to a “1”. Optional Spansion programming services can program the
factory-locked area with a random ESN, a customer-defined code, or any combi
nation of the two. Because only F ASL can program and protect the factory-l ocked
area, this method ensures the security of the ESN once the product is shipped to
the field. Contact your local sales office for details on using Spansion’s program
ming services. Note that the ACC function and unlock bypass modes are not
available when the Secured Silicon sector is enabled.
-
-
-
Customer-Lockable Area (64 words)
The customer-lockable area of the Secured Silicon Sector (000040h-00007Fh) is
shipped unprotected, which allows the customer to program and optionally lock
the area as appropriate for the application. The Secured Silicon Sector Customer locked Indicator Bit (DQ6) is shipped as “0” and can be permanently locked to “1”
by issuing the Secured Silicon Protection Bit Progr am Command. The Secured Sil
icon Sector can be read any number of times, but c an be programmed and locked
only once. Note that the accelerated programming (A CC) and unlock bypass func
tions are not available when programming the Secured Silicon Sector.
-
-
The Customer-lockable Secured Silicon Sector area can be protected using one
of the following procedures:
Write the three-cycle Enter Secured Silicon Sector Region command se-
quence, and then follow the in-system sector protect algorithm as shown in
Figure 1, except that RESET# may be at either VIH or VID. This allows in-sys-
tem protection of the Secured Silicon Sector Region without raising any device pin to a high voltage. Note that this method is only applicable to the
Secured Silicon Sector.
T o verify the protect/unprotect status of the Secured Silicon Sector , follow the
algorithm shown in
Once the Secured Silicon Sector is locked and verified, the system must write the
Exit Secured Silicon Sector Region co mmand se quence to return to readin g and
writing the remainder of the array.
The Secured Silicon Sector lock must be used with caution since, once locked,
there is no procedure available for unlocking the Secured S ilicon Sector area and
none of the bits in the Secur ed Sili con S ector memory space can be modif ied in
any way.
Figure 3.
Secured Silicon Sector Protection Bits
The Secured Silicon Sector Protection Bits prevent programming of the Secured
Silicon Sector memory area. Once set, the Secured Silicon Sector memory area
contents are non-modifiable.
40 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004
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Advance Information
START
Write 40h to SecSi
Figure 3. Secured Silicon Sector Protect Verify
Hardware Data Protection
The command sequence requirement of unlock cycles for progr amming or erasing
provides data protection against inadvertent writes. In addition, the following
hardware data protection measures prevent accidental erasure or programming,
which might otherwise be caused by spurious system level signals during V
power-up and power-down transitions, or from system noise.
RESET# =
or V
V
IH
ID
Wait 1 µs
Write 60h to
any address
Sector address
with A6 = 0,
A1 = 1, A0 = 0
Read from SecSi
Sector address
with A6 = 0,
A1 = 1, A0 = 0
If data = 00h,
SecSi Sector is
unprotected.
If data = 01h,
SecSi Sector is
protected.
Remove VIH or VID
from RESET#
Write reset
command
SecSi Sector
Protect Verify
complete
CC
Low VCC Write Inhibit
When VCC is less than V
tects data during VCC power-up and power-down. The command register and all
internal program/erase circuits are disabled, and the device resets to the read
mode. Subsequent writes are ignored until V
must provide the proper signals to the control pins to prevent unintentional writes
when V
is greater than V
CC
, the device does not accept any write cycl es. This pro-
LKO
LKO
is greater than V
CC
.
. The system
LKO
Write Pulse “Glitch” Protection
Noise pulses of less than 3 ns (typical) on OE#, CE1#, CE2# or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holdi ng any one of OE# = VIL, CE1# = CE2# = V
or WE# = VIH. To initiate a write cycle, CE1# / CE2# and WE# must be a logical
zero while OE# is a logical one.
IH
Power-Up Write Inhibit
If WE# = CE# (CE1#, CE2# in PL129J) = VIL and OE# = VIH during power up,
the device does not accept commands on the rising edge of WE#. The internal
state machine is automatically reset to the read mode on power-up.
June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 41
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Common Flash Memory Interface (CFI)
The Common Flash Interface (CFI) specification outlines device and host system
software interrogation handshake, which allows specific vendor-specified soft
ware algorithms to be used for entire families of devices. Software support can
then be device-independent, JEDEC ID-independent, and forward- and back
ward-compatible for the specified flash device families. Flash vendors can
standardize their existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query
command, 98h, to address 55h, any time the device is ready to read array data.
The system can read CFI information at the addresses given in
Table 10, and Table 11. T o terminate reading CFI data, the system must write the
reset command. The CFI Query mode is not accessible when the device is executing an Embedded Program or embedded Er as e al gorithm.
The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read
CFI data at the addresses given in
system must write the reset command to return the device to reading array data.
For further information, please refer to the CFI Specification and CFI Publication
100. Contact your local sales office for copies of these documents .
Table 8, Table 9, Table 10, and Table 11. The
-
-
Table 8, Table 9,
Ta bl e 8 . CFI Query Identification String
Addresses Data Description
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
0051h
0052h
0059h
0002h
0000h
0040h
0000h
0000h
0000h
0000h
0000h
Query Unique ASCII string “QRY”
Primary OEM Command Set
Address for Primary Extended Table
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
42 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004
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Ta b l e 9 . System Interface String
Addresses Data Description
1Bh 0027h
1Ch 0036h
VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Dh 0000h VPP Min. voltage (00h = no VPP pin present)
1Eh 0000h VPP Max. voltage (00h = no VPP pin present)
1Fh 0003h Ty pical timeout per single byte/w ord write 2N µs
20h 0000h Typical timeout for Min. size buffer write 2N µs (00h = not supported)
21h 0009h Typical timeout per individual block erase 2N ms
22h 0000h Typical timeout for full chip erase 2N ms (00h = not supported)
23h 0004h Max. timeout for byte/word write 2N times typical
24h 0000h Max. timeout for buffer write 2N times typical
25h 0004h Max. timeout per individual block erase 2N times typical
26h 0000h Max. timeout for full chip erase 2N times typical (00h = not supported)
Ta b l e 1 0 . Device Geometry Definition
Addresses Data Description
27h 0018h (PL129J) Device Size = 2N byte
28h
29h
2Ah
2Bh
2Ch 0003h Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
31h 00FDh (PL129J)
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
0001h
0000h
0000h
0000h
0007h
0000h
0020h
0000h
0000h
0000h
0001h
0007h
0000h
0020h
0000h
0000h
0000h
0000h
0000h
Flash Device Interface description (refer to CFI publication 100)
Max. number of byte in multi-byte write = 2N
(00h = not supported)
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
Erase Block Region 2 Information
(refer to the CFI specification or CFI publication 100)
Erase Block Region 3 Information
(refer to the CFI specification or CFI publication 100)
Erase Block Region 4 Information
(refer to the CFI specification or CFI publication 100)
Ta b l e 1 1 . Primary Vendor-Specific Extended Query
Addresses Data Description
40h
41h
42h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 43
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Advance Information
Table 11. Primary Vendor-Specific Extended Query (Continued)
Addresses Data Description
43h 0031h Major version number, ASCII (reflects modifications to the silicon)
44h 0033h Minor version number, ASCII (reflects modifications to the CFI table)
45h
46h 0002h
47h 0001h
48h 0001h
49h 0007h (PLxxxJ)
4Ah 00E7h (PL129J)
4Bh 0000h
4Ch 0002h (PLxxxJ)
4Dh 0085h
4Eh 0095h
TBD
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
Silicon Revision Number (Bits 7-2)
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
Sector Protect
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
07 = Advanced Sector Protection
Simultaneous Operation
00 = Not Supported, X = Number of Sectors excluding Bank 1
Burst Mode Type
00 = Not Supported, 01 = Supported
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
ACC (Acceleration) Supply Minimum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
4Fh 0001h
50h 0001h
57h 0004h
58h 0027h (PL129J)
59h 0060h (PL129J)
5Ah 0060h (PL129J)
5Bh 0027h (PL129J)
Top/Bottom Boot Sector Flag
00h = Uniform device, 01h = Both top and bottom boot with write protect,
02h = Bottom Boot Device, 03h = Top Boot Device,
04h = Both Top and Bottom
Program Suspend
0 = Not supported, 1 = Supported
Bank Organization
00 = Data at 4Ah is zero, X = Number of Banks
Bank 1 Region Information
X = Number of Sectors in Bank 1
Bank 2 Region Information
X = Number of Sectors in Bank 2
Bank 3 Region Information
X = Number of Sectors in Bank 3
Bank 4 Region Information
X = Number of Sectors in Bank 4
44 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004
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Command Definitions
Writing specific address and data commands or sequences into the command
register initiates device operations.
sequences. Writing incorrect address and data values or writing them in the
improper sequence may place the device in an unknown state. A reset com
mand is then required to return the device to reading array data.
All addresses are latched on the falling edge of WE# or CE# (CE1# / CE2# in
PL129J), whichever happens later. All data is latched on the rising edge of WE#
or CE# (CE1# / CE2# in PL129J), whichever happens first. See
for timing diagrams.
Reading Array Data
The device is automatically set to reading array data after device power-up. No
commands are required to retrieve data. Each bank is ready to read array data
after completing an Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the corresponding bank
enters the erase-suspend-read mode, after which the system can read data from
any non-erase-suspended sector within the same bank. The system can read
array data using the standard read timing, except that if it reads at an address
within erase-suspended sectors, the device outputs status data. After completing
a programming operation in the Erase Suspend mode, the system may once
again read array data with the same exception. See
sume Commands” on page 50 for more information.
Table 12 defines the valid register command
-
AC Characteristics
“Erase Suspend/Erase Re-
The system must issue the reset command to return a bank to the read (or erase-
suspend-read) mode if DQ5 goes high during an active program or erase opera
tion, or if the bank is in the autoselect mode. See “Reset Co mm and ,” for more
information.
See “Requirements for Reading Array Data” on page 19 in “Device Bus Opera-
tions” for more information. The AC Characteristics table provides the read
parameters, and Figure 12 shows the timing diag ram.
Reset Command
Writing the reset command resets the banks to the read or erase-suspend-read
mode. Address bits are don’t cares for this command.
The reset command may be written between the sequence cycles in an erase
command sequence before erasing begins. This resets the bank to which the sys
tem was writing to the read mode. Once erasure begins, however, the device
ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in a program
command sequence before programming begins. This resets the bank to which
the system was writing to the read mode. If the program command sequence is
written to a bank that is in the Erase Suspend mode, writing the reset command
returns that bank to the erase-suspend-read mode. Once programming begins,
however, the device ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in an autoselect
command sequence. Once in the autoselect mode, the reset command must be
written to return to the read mode. If a bank entered the autoselect mode while
in the Erase Suspend mode, writing the reset command returns that bank to the
erase-suspend-read mode.
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-
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Advance Information
If DQ5 goes high during a program or er ase operation, writing the reset command
returns the banks to the read mode (or erase-suspend-read mode if that bank
was in Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected.
The autoselect command sequence may be written to an address within a bank
that is either in the read or erase-suspend-read mode. The autosel ect command
may not be written while the device is actively programming or erasing in the
other bank.
The autoselect command sequence is initiated by first writing two unlock cycl es.
This is followed by a third write cycle that contains the bank address and the au
toselect command. The bank then enters the autoselect mode. The system may
read any number of autoselect codes without reinitiating the command sequence.
Table 12 shows the address and data requirements. To determine sector protec-
tion information, the system must write to the appropriate bank address (BA) and
sector address (SA).
The system must write the reset command to return to the read mode (or erasesuspend-read mode if the bank was previously in Erase Suspend).
-
Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Sequence
The Secured Silicon Sector region provides a secured data area containing a ran dom, eight word electronic serial number (ESN). The system can access the
Secured Silicon Sector region by issuing the three-cycle Enter Secured Silicon
Sector command sequence. The device continues to access the Secured Silicon
Sector region until the system issues the four-cycle Exit Secured Silicon Sector
command sequence. The Exit Secured Silicon Sector command sequence returns
the device to normal operation. The Secured Silicon Sector is not ac cessible when
the device is executing an Embedded Program or embedded Erase algorithm.
Table 12 shows the address and data requirements for both command sequences.
Also see, “Secured Silicon Sector Flash Memory Region” on page 39 for further information. Note: The ACC function and unlock byp ass modes are not availabl e
when the Secured Silicon Sector is enabled.
Word Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is
initiated by writing two unlock write cycles, followed by the program set-up com
mand. The program address and data are written next, which in turn initi ate the
Embedded Program algorithm. The system is not re quired to provide further con
trols or timings. The device automatically provides internally generated program
pulses and verifies the programmed cell margin.
data requirements for the program command sequence. Note that the Secured
Silicon Sector, autoselect, and CFI functions are unavailable when a [program/
erase] operation is in progress.
Table 12 shows the address and
-
-
When the Embedded Program algorithm is complete, that bank then returns to
the read mode and addresses are no longer latched. The system can determine
the status of the program operation by using DQ7, DQ6, or RY/BY#. See
Operation Status” on page 56 for information on these status bits.
“Write
46 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004
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Any commands written to the device during the Embedded Program Algorithm
are ignored. Note that a hardware reset immediately terminates the program
operation. The program command sequence should be reinitiated once that bank
has returned to the read mode, to ensure data integrity. Note that the Secured
Silicon Sector, autoselect and CFI functions are unavailable when the Secured Sil
icon Sector is enabled.
Programming is allowed in any sequence and across sector boundaries. A bit
cannot be programmed from “0” back to a “1.” Attempting to do so may
cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate
the operation was successful. However, a succeed ing read shows that the data is
still “0.” Only erase operations can convert a “0” to a “1.”
Unlock Bypass Command Sequence
The unlock bypass feature allows the sy stem to program data to a bank faster
than using the standard program command sequence. The unlock bypass com
mand sequence is initiated by first writing two unlock cycles. This is followed by
a third write cycle containing the unlock bypass command, 20h. That bank then
enters the unlock bypass mode. A two-cycle unlock bypass program command
sequence is all that is required to program in this mode. The first cy cle in this se
quence contains the unlock bypass program command, A0h; the second cycle
contains the program address and data. Additional data is programmed in the
same manner. This mode dispenses with the initial two unlock cycles required in
the standard program command sequence, resulting in faster tota l progr amming
Table 12 shows the requirements for the command sequence.
time.
-
-
-
During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset command sequence. (
Table 13)
The device offers accelerated program operations through the WP#/ACC pin.
When the system asserts V
on the WP#/ACC pin, the device automatically en-
HH
ters the Unlock Bypass mode. The system may then write the two-cycle Unlock
Bypass program command sequence. The device uses the higher voltage on the
WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not
be at V
may result. In addition, the WP#/ACC pin must not be left floating or uncon
any operation other than accelerated programming, or device damage
HH
-
nected; inconsistent behavior of the device may result.
Figure 4 illustrates the algorithm for the program operation. See the Erase/Pro-
gram Operations table in AC Characteristics for parameters, and Figure 14 for
timing diagrams.
June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 47
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Advance Information
START
Write Program
Command Sequence
Data Poll
Embedded
Program
algorithm
in progress
from System
Verify Data?
Yes
No
Increment Address
Note: See Table 12 for program command sequence.
Figure 4. Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle oper ation. The chip er ase command sequence is ini tiated by writing two unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the chip erase command,
which in turn invokes the Embedded Erase algorithm. The devi ce does not require
the system to preprogram prior to erase. The Embedded Erase algorithm auto
matically preprograms and verifies the entire memory for an all z ero data pattern
prior to electrical erase. The system is not required to provide any controls or tim
ings during these operations. Table 12 shows the address and data requirements
for the chip erase command sequence.
When the Embedded Erase algorithm is complete, that bank returns to the read
mode and addresses are no longer latched. The system can determine the status
of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to
eration Status” on page 56 for information on these status bits.
No
Last Address?
Yes
Programming
Completed
-
-
“Write Op-
Any commands written during the chip erase operation are ignored. Note that Se-
cured Silicon Sector, autoselect, and CFI functions are unavailable when a
[program/erase] operation is in progress. However, note that a hardware reset
immediately terminates the erase operation. If that occurs, the chip erase com
mand sequence should be reinitiated once that bank has returned to reading
array data, to ensure data integrity.
Figure 5 illustrates the algorithm for the er ase operation. Se e the Erase/ Pr ogram
Operations tables in AC Characteristics for parameters, and Figure 16 for timing
diagrams.
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Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command seq uence is
initiated by writing two unlock cycles, followed by a set-up command. Two addi
tional unlock cycles are written, and are then followed by the address of the
sector to be erased, and the sector erase command.
and data requirements for the sector erase command sequence.
The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory
for an all zero data pattern prior to electrical er ase. The system is not required to
provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out of 50 µs occurs.
During the time-out period, additional sector addresses and sector erase com
mands may be written. Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one sector to all sectors. The
time between these additional cycles must be less than 50 µs, otherwise erasure
may begin. Any sector eras e address and command following the ex ceeded timeout may or may not be accepted. It is recommended that processor interrupts be
disabled during this time to ensure all commands are accepted. The interrupts
can be re-enabled after the last Sector Erase command is written. If any com
mand other than 30h, B0h, F0h is input during the time-out period, the
normal operation cannot be guaranteed. The system must rewrite the com
mand sequence and any additional addresses and commands. Note that Secured
Silicon Sector, autoselect, and CFI functions are unavailable when a [program/
erase] operation is in progress.
-
Table 12 shows the address
-
-
-
The system can monitor DQ3 to determine if the sector erase timer has timed out
“DQ3: Sector Erase Timer” on page 61). The time-out begins from the rising
(See
edge of the final WE# pulse in the command sequence.
When the Embedded Erase algorithm is complete, the bank returns to reading
array data and addresses are no longer latched. Note that while the Embedded
Erase operation is in progress, the system can read data from the non-erasing
bank. The system can determine the status of the erase operation by reading
DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. See
page 56 for information on these status bits.
Once the sector erase operation has begun, only the E rase Suspend command is
valid. All other commands are ignored. Howev er , note that a hardware reset im
mediately terminates the erase operation. If that occurs, the sector erase
command sequence should be reinitiated once that bank has returned to reading
array data, to ensure data integrity.
Figure 5 illustrates the algorithm for the er ase operation. Se e the Erase/ Pr ogram
Operations tables in AC Characteristics for parameters, and Figure 16 for timing
diagrams.
“Write Operation Status” on
-
June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 49
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Advance Information
START
Write Erase
Command Sequence
(Notes 1, 2)
Data Poll to Erasing
Bank from System
No
Data = FFh?
Yes
Embedded
Erase
algorithm
in progress
Erasure Completed
Notes:
1. See Table 12 for erase command sequence.
2. See “DQ3: Sector Erase Timer” on page 61 for information on the sector erase
timer.
Figure 5. Erase Operation
Erase Suspend/Erase Resume Commands
The Erase Suspend command, B0h, allows the system to interrupt a sector erase
operation and then read data from, or program data to, any sector not selected
for erasure. The bank address is required when writ ing this command. This com
mand is valid only during the sector erase operation, including the 80 µs time-out
period during the sector erase command sequence. The Erase Suspend command
is ignored if written during the chip erase operation or Embedded Program
algorithm.
When the Erase Suspend command is written during the sector erase operation,
the device requires a maximum of 35 µs to suspend the erase operation. How
ever, when the Erase Suspend command is written during the sector erase
time-out, the device immediately terminates the time-out period and suspends
the erase operation. Addresses are “don’t-cares” when writing the Erase suspend
command.
After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The system can read data from or program data to any sector
not selected for erasure. (The device “erase suspends” all sectors selected for
erasure.) Reading at any address within erase-suspended sectors produces sta
tus information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2
together, to determine if a sector is actively erasing or is erase-susp ended. Se e
“Write Operation Status” on page 56 for information on these status bits.
-
-
-
After an erase-suspended program operatio n is complete, the bank returns to the
erase-suspend-read mode. The system can determine the status of the progr am
50 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004
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operation using the DQ7 or DQ6 status bits, just as in the standard W ord Program
operation. See
In the erase-suspend-read mode, the system can also issue the autosele ct command sequence. The device allows reading autoselect codes even at addresses
within erasing sectors, since the codes are not stored in the memory array . When
the device exits the autoselect mode, the device reverts to the Erase Suspend
mode, and is ready for another valid operation. See
dresses” on page 29 and “Autoselect Command Sequence” on page 46 for details.
To resume the sector erase operation, the system must write the Erase Resume
command (address bits are don’t care). The bank a ddress of the erase-sus
pended bank is required when writing this command. Further writes of the
Resume command are ignored. Another Erase Suspend command can be written
after the chip has resumed erasing.
“Write Operation Status ” on page 56 for more information.
Password Program Command
The Password Program Command permits programming the password that is
used as part of the hardware protection scheme. The actual password is 64-bits
long. Four Password Program commands ar e requi red to program the password.
The system must enter the unlock cycle, password program command (38h) and
the program address/data for each portion of the password when programming.
There are no provisions for entering the 2-cycle unlock cycle, the password pro
gram command, and all the password data. There is no special ad dressing order
required for programming the password. Also, when the password is undergoing
programming, Simultaneous Operation is disabled. Read oper ations to any mem
ory location will return the programming status. Once programming is complete,
the user must issue a Read/Reset command to return the device to normal oper
ation. Once the Password is written and verified, the Password Mode Locking Bit
must be set in order to prevent verification. The Passwor d Progr a m Command is
only capable of programming “0”s. Programming a “1” after a cell is programmed
as a “0” results in a time-out by the Embedded Program Algorithm™ with the cell
remaining as a “0”. The password is all ones when shipped from the factory. All
64-bit password combinations are valid as a password.
“Secured Silicon Sector Ad-
-
-
-
-
Password Verify Command
The Password Verify Command is used to verify the Password. The Password is
verifiable only when the Password Mode Locking Bit is not programmed. If the
Password Mode Locking Bit is programmed and the user attempts to verify the
Password, the device will always dr ive all F’s onto the DQ data bus.
The Password Verify command is permitted if the Secured Silicon sector is enabled. Also, the device will not operate in Simultaneous Operation when the
Password V erify command is executed. O nly the password is returned regardless
of the bank address. The lower two address bits (A1-A0) are valid during the
Password Verify. Writing the Read/Reset command returns the device back to
normal operation.
Password Protection Mode Locking Bit Program Command
The Password Protection Mode Locking Bit Program Command programs the
Password Protection Mode Locking Bit, which prevents further verifies or updates
to the Password. Once programmed, the Password Protection Mode Locking Bit
cannot be erased! If the Password Pr otecti on Mode Locking Bit is v erified as p ro
gram without margin, the Password Protection Mode Locking Bit Program
June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 51
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command can be executed to improve the program margin. Once the Password
Protection Mode Locking Bit is programmed, the Persistent Sector Protection
Locking Bit program circuitry is disabled, thereby forcing the device to remain in
the Password Protection mode. Exiting the Mode Locking Bit Program command
is accomplished by writing the Read/Reset command.
Persistent Sector Protection Mode Locking Bit Program Command
The Persistent Sector Protection Mode Locking Bit Program Command programs
the Persistent Sector Protection Mode Locking Bit, which prevents the Password
Mode Locking Bit from ever being programmed. If the Persistent Sector Protec
tion Mode Locking Bit is verified as programmed without margin, the Persistent
Sector Protection Mode Locking Bit Program Command should be reissued to im
prove program margin. By disabling the program circuitry of the Password Mode
Locking Bit, the device is forced to remain in the Persistent Sector Protection
mode of operation, once this bit is set. Exiting the Persistent Protection Mode
Locking Bit Program command is accomplished by writing the Read/Reset
command.
Secured Silicon Sector Protection Bit Program Command
The Secured Silicon Sector Protection Bit Program Command programs the Secured Silicon Sector Protection Bit, which prevents the Secured Silicon sector
memory from being cleared. If the Secured Silicon Sector Protection Bit is verified
as programmed without margin, the Secured Silicon Sector Protection Bit Pro
gram Command should be reissued to improve program margin. Exiting the VCC-
level Secured Silicon Sector Protection Bit Program Command is accompli shed by
writing the Read/Reset command.
-
-
-
PPB Lock Bit Set Command
The PPB Lock Bit Set command is used to set the PPB Lock bit if it is cleared either
at reset or if the Password Unlock command was successfully executed. There is
no PPB Lock Bit Clear command. Once the PPB Lock Bit is set, it cannot be cleared
unless the device is taken through a power-on clear or the Password Unlock com
mand is executed. Upon setting the PPB Lock Bit, the PPBs are latched into the
DYBs. If the Password Mode Locking Bit is set, the PPB Lock Bit status is reflected
as set, even after a power-on reset cycle. Exiting the PPB Lock Bit Set command
is accomplished by writing the Read/Re set command (only in the Persistent Pro
tection Mode).
DYB Write Command
The DYB Write command is used to set or clear a DYB for a given sector. The high
order address bits (Amax–A12) are issued at the same time as the code 01h or
00h on DQ7-DQ0. All other DQ data bus pins are ignored during the data write
cycle. The DYBs are modifiable at any time, regardless of the state of the PPB or
PPB Lock Bit. The DYBs are cleared at power-up or hardware reset.Exiting the
DYB Write command is accomplished by writing the Read/Reset command.
Password Unlock Command
The Password Unlock command is used to clear the PPB Lock Bit so that the PPBs
can be unlocked for modification, thereby allowing the PPBs to become accessible
for modification. The exact password must be entered in order for the unlocking
function to occur. This command cannot be issued any faster than 2
to prevent a hacker from running through all 64-bit combinations in an attempt
-
-
µs at a time
52 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004
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to correctly match a password. If the command is issued before the 2 µs execution window for each portion of the unlock, the command will be ignored.
Once the Password Unlock command is entered, the RY/BY# indicates that the
device is busy . Approximately 1 µs is required for each portion of the unlock. Once
the first portion of the password unlock completes (RY/BY# is not low or DQ6
does not toggle when read), the next part of the password is written. The system
must thus monitor RY/BY# or the status bits to confirm when to write the next
portion of the password. Seven cycles are required to successfully clear the PPB
Lock Bit.
PPB Program Command
The PPB Program command is used to program, or set, a given PPB. Each PPB is
individually programmed (but is bulk erased with the other PPBs). The specific
sector address (A22–A12) are written at the same time as the program command
60h with A6 = 0. If the PPB Lock Bit is set and the corresponding PPB is set for
the sector, the PPB Program command will not execute and the c ommand will
time-out without programming the PPB.
After programming a PPB, two additional cycles are needed to determine whether
the PPB has been programmed with margin. If the PPB has been progra mmed
without margin, the program command should be reissued to improve the pro
gram margin. Also note that the total number of PPB program/erase cycles is
limited to 100 cycles. Cycling the PPBs beyond 100 cycles is not guaranteed.
-
The PPB Program command does not follow the Embedded Program algorithm.
All PPB Erase Command
The All PPB Erase command is used to erase all PPBs in bulk. There is no means
for individually erasing a specific PPB. Unli k e the PPB program, no specific se ctor
address is required. However, when the PPB erase command is written all Sector
PPBs are erased in parallel. If the PPB Lock Bit is set the ALL PPB Erase command
will not execute and the command will time-out without erasing the PPBs. After
erasing the PPBs, two additional cycles are needed to determine whet her the PPB
has been erased with margin. If the PPBs has been erased without margin, the
erase command should be reissued to improve the program margin.
It is the responsibility of the user to preprogram all PPBs prior to issuing the All
PPB Erase command. If the user attempts to erase a cleared PPB, over-erasure
may occur making it difficult to program the PPB at a later time. Also note that
the total number of PPB program/erase cycles is limited to 100 cycles. Cy cling the
PPBs beyond 100 cycles is not guaranteed.
DYB Write Command
The DYB Write command is used for setting the DYB, which is a volatile bit that
is cleared at reset. There is one DYB per sector. If the PPB is set, the sector is
protected regardless of the value of the DYB. If the PPB is cleared, setting the
DYB to a 1 protects the sector from programs or erases. Since this is a volatile
bit, removing power or resetting the device will clear the DYBs. The bank add ress
is latched when the command is written.
PPB Lock Bit Set Command
The PPB Lock Bit set command is used for setting the DYB, which is a volatile bit
that is cleared at reset. There is one DYB per sector. If the PPB is set, the sector
is protected regardless of the value of the DYB. If the PPB is cleared, setting the
June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 53
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Advance Information
DYB to a 1 protects the sector from programs or erases. Since this is a volatile
bit, removing power or resetting the device will clear the DYBs. The bank add ress
is latched when the command is written.
Command
The programming of either the PPB or D YB for a given sector or sector g roup can
be verified by writing a Sector Protection Status command to the device.
Note that there is no single command to independently verify the programming
of a DYB for a given sector group.
Command Definitions Tables
Ta bl e 1 2 . Memory Array Command Definitions
Bus Cycles (Notes 1–4)
Command (Notes)
Read (Note 5) 1 RA RD
Reset (Note 6) 1 XXX F0
Manufacturer ID 4 555 AA 2AA 55
Device ID (Note 10) 6 555 AA 2AA 55
Autoselect
(Note 7)
Program 4 555 AA 2AA 55 555 A0 PA PD
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Program/Erase Suspend (Note 11) 1 BA B0
Program/Erase Resume (Note 12) 1 BA 30
CFI Query (Note 13) 1 55 98
Accelerated Program (Note 15) 2 XX A0 PA PD
Unlock Bypass Entry (Note 15) 3 555 AA 2AA 55 555 20
Unlock Bypass Program (Note 15) 2 XX A0 PA PD
Unlock Bypass Erase (Note 15) 2 XX 80 XX 10
Unlock Bypass CFI (Notes 13, 15) 1 XX 98
Unlock Bypass Reset (Note 15) 2 XXX 90 XXX 00
Secured Silicon Sector
Factory Protect
Sector Group Protect
(Note 9)
Verify
(Note 8)4 555 AA 2AA 55
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Cycles
4 555 AAA 2AA 55
(BA)
555
(BA)
555
(BA)
555
(BA)
555
(BA)
90
X00
(BA)
90
X01
90 X03
(SA)
90
X02
01
227E
(Note
8)
XX00/
XX01
(BA)
X0E
(Note
10)
(BA)
X0F
(Note
10)
Legend:
BA = Address of bank switching to autoselect mode, bypass mode, or erase operation. Determin ed by Amax :A19.
PA = Program Address (Amax:A0). Addresses latch on falling edge of WE# or CE1#/CE2# pulse, whichever happens
later.
PD = Program Data (DQ15:DQ0) written to location PA. Data latches on rising edge of WE# or CE1#/CE2# pulse,
whichever happens first.
RA = Read Address (Amax:A0).
RD = Read Data (DQ15:DQ0) from location RA.
SA = Sector Address (Amax:A12) for verifying (in autoselect mode) or erasing.
WD = Write Data. See “Configuration Register” definition for specific write data. Data latched on rising edge of WE#.
X = Don’t care
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells in table denote read cycles. All other cycles are write operations.
54 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004
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Advance Information
4. During unlock and command cycles, when lower address bits are 555 or 2AAh as shown in table, address bits higher than
A11 (except where BA is required) and data bits higher than DQ7 are don’t cares.
5. No unlock or command cycles required when bank is reading array data.
6. The Reset command is required to return to reading array (or to erase-suspend-read mode if previously in Erase Suspend)
when bank is in autoselect mode, or if DQ5 goes high (while bank is providing status information).
7. Fourth cycle of autoselect command sequence is a read cycle. System must provide bank address to obtain manufacturer ID
or device ID information. See
“Autoselect Command Sequence” on page 46 for more information.
8. The data is DQ6=1 for factory and customer locked and DQ7=1 for factory locked.
9. The data is 00h for an unprotected sector group and 01h for a protected sector group.
10.Device ID must be read across cycles 4, 5, and 6. PL129J (X0Eh = 2221h, X0Fh = 2200h).
11.System may read and program in non-erasing sectors, or enter autoselect mode, when in Program/Erase Suspend mode.
Program/Erase Suspend command is valid only during a sector erase operation, and requires bank address.
12.Program/Erase Resume command is valid only during Erase Suspend mode, and requires bank address.
13.Command is valid when device is ready to read array data or when device is in autoselect mode.
14.WP#/ACC must be at VID during the entire operation of command.
15.Unlock Bypass Entry command is required prior to any Unlock Bypass operation. Un lock Bypass Reset command is required
to return to the reading array.
Ta b l e 1 3 . Sector Protection Command Definitions
Command (Notes)
Reset 1 XXX F0
Secured Silicon Sector Entry 3 555 AA 2AA 55 555 88
Secured Silicon Sector Exit 4 555 AA 2AA 55 555 90 XX 00
Secured Silicon Protection Bit Program
(Notes
5, 6)
Secured Silicon Protection Bit Status 5 555 AA 2AA 55 555 60 OW 48 OW
Password Program (Notes 5, 7, 8) 4 555 AA 2AA 55 555 38
Password Verify (Notes 6, 8, 9) 4 555 AA 2AA 55 555 C8
Password Unlock (Notes 7, 10, 11) 7 555 AA 2AA 55 555 28
PPB Program (Notes 5, 6, 12) 6 555 AA 2AA 55 555 60
PPB Status 4 555 AA 2AA 55 555 90
All PPB Erase (Notes 5, 6, 13, 14) 6 555 AA 2AA 55 555 60 WP 60 (SA) 40
PPB Lock Bit Set 3 555 AA 2AA 55 555 78
PPB Lock Bit Status (Note 15) 4 555 AA 2AA 55 555 58 SA
DYB Write (Note 7) 4 555 AA 2AA 55 555 48 SA X1
DYB Erase (Note 7) 4 555 AA 2AA 55 555 48 SA X0
DYB Status (Note 6) 4 555 AA 2AA 55 555 58 SA
PPMLB Program (Notes 5, 6, 12) 6 555 AA 2AA 55 555 60 PL 68 PL 48 PL
PPMLB Status (Note 5) 5 555 AA 2AA 55 555 60 PL 48 PL
SPMLB Program (Notes 5, 6, 12) 6 555 AA 2AA 55 555 60 SL 68 SL 48 SL
SPMLB Status (Note 5) 5 555 AA 2AA 55 555 60 SL 48 SL
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Cycles
6 555 AA 2AA 55 555 60 OW 68 OW 48 OW
Bus Cycles (Notes 1-4)
XX
[0-3]PD[0-3]
PWA
PWD
[0-3]
[0-3]
PWA
PWD
[0]
68
(0)
RD
(1)
RD
(0)
PWA
[1]
(SA)
WP
[0]
(SA)
WP
(SA)WPRD
RD
(0)
PWD
[1]
48
RD
(0)
RD
(0)
RD
(0)
PWA
PWD
[2]
[2]
(SA)WPRD
(0)
(SA)WPRD
(0)
RD
(0)
RD
(0)
PWA
[3]
PWD
[3]
Legend:
DYB = Dynamic Protection Bit
OW = Address (A7:A0) is (00011010)
PD[3:0] = Password Data (1 of 4 portions)
PPB = Persistent Protection Bit
June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 55
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Advance Information
PWA = Password Address. A1:A0 selects portion of password.
PWD = Password Data being verified.
PL = Password Protection Mode Lock Address (A7:A0) is (00001010)
RD(0) = Read Data DQ0 for protection indicator bit.
RD(1) = Read Data DQ1 for PPB Lock status.
SA = Sector Address where security command applies. Address bits Amax:A12 uniquely select any sector.
SL = Persistent Protection Mode Lock Address (A7:A0) is (00010010)
WP = PPB Address (A7:A0) is (00000010)
X = Don’t care
PPMLB = Password Protection Mode Locking Bit
SPMLB = Persistent Protection Mode Locking Bit
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells in table denote read cycles. All other cycles are write operations.
4. During unlock and command cycles, when lower address bits are 555 or 2AAh as shown in table, address bits higher than
A11 (except where BA is required) and data bits higher than DQ7 are don’t cares.
5. The reset command returns device to reading array.
6. Cycle 4 programs the addressed locking bit. Cyc les 5 and 6 vali date bit has been ful ly programme d when DQ 0 = 1. If DQ0 =
0 in cycle 6, program command must be issued and verified again.
7. Data is latched on the rising edge of WE#.
8. Entire command sequence must be entered for each portion of password.
9. Command sequence returns FFh if PPMLB is set.
10.The password is written over four consecutive cycles, at addresses 0-3.
11.A 2 µs timeout is required between any two portions of password.
12.A 100 µs timeout is required between cycles 4 and 5.
13.A 1.2 ms timeout is required between cycles 4 and 5.
14.Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been fully erased when DQ0 = 0. If DQ0 = 1 in cycle 6, erase
command must be issued and verified aga in. Before issuing erase command, all PPBs should be pro grammed to preven t PPB
overerasure.
15.DQ1 = 1 if PPB locked, 0 if unlocked.
Write Operation Status
The device provides several bits to determi ne the status of a progr am or erase oper a tion: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 14 and the following subsections descri be
the function of these bits. DQ7 and DQ6 each offer a method for determining whether
a program or erase operation is complete or in progress. The device also provides a
hardware-based output signal, RY/BY#, to determine whether an Embedd ed Program
or Erase operation is in progress or has been completed.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether a bank is in Erase
Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the com
mand sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the complement
of the datum programmed to DQ7. This DQ7 st atus also applies to programming during
Erase Suspend. When the Embedded Program algorithm is complete, the device out
puts the datum programmed to DQ7. The s ystem must provide the program address
to read valid status information on DQ7. If a program address falls within a protected
sector, Data# Polling on DQ7 is active for approximately 1 µs, then that bank returns
to the read mode.
56 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004
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-
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During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7.
When the Embedded Erase algorithm is comp lete, or if the bank enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7. The system must provide
an address within any of the sectors selected for erasure to read valid status in
formation on DQ7.
After an erase command sequence is written, if all sectors selected for erasing
are protected, Data# Polling on DQ7 is active for approximately 400 µs, then the
bank returns to the read mode. If not all selected sectors are protected, the Em
bedded Erase algorithm erases the unprotected sec tors, and ignores the selected
sectors that are protected. However, if the system reads DQ7 at an address within
a protected sector, the status may not be valid.
When the system detects DQ 7 has changed from the complement to true data,
it can read valid data at D Q15–DQ0 on the following read cy cles. Just prior to the
completion of an Embedded Program or Erase oper ation, DQ7 may change asyn
chronously with DQ15–DQ0 while Output Enable (OE#) is asserted low. That is,
the device may change from providing status information to valid data on DQ7.
Depending on when the system samples the DQ7 output, it may read the status
or valid data. Even if the device has completed the program or erase operation
and DQ7 has valid data, the data outputs on DQ15–DQ0 may be still invalid. Valid
data on DQ15–DQ0 appears on successive read cycles.
-
-
-
Table 14 shows the outputs for Data# Polling on DQ7. 6 shows the Data# Polling
algorithm. Fi gure 18 in AC Characteristics shows the Data# Polling timing
diagram.
June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 57
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Advance Information
START
Read DQ7–DQ0
Addr = VA
Notes:
1. VA = Valid address for programming. During a sector erase operation, a valid address is
any sector address within t he sector being erased. During chip erase, a valid address is
any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously
with DQ5.
RY/ BY# : Rea d y/ B usy #
The RY/BY# is a dedicated, open-drain output pin which indicates whether an
Embedded Algorithm is in progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command sequence. Since RY/BY#
is an open-drain output, several RY/BY# pins can be tied together in parallel with
a pull-up resistor to V
If the output is low (Busy), the device is actively erasing or programming. (This
includes programming in the Erase Suspend mode.) If the output is high (Ready),
the device is in the read mode, the standby mode, or one of the banks is in the
erase-suspend-read mode.
Yes
Yes
PASS
No
DQ7 = Data?
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
No
FAIL
Figure 6. Data# Polling Algorithm
.
CC
Table 14 shows the outputs for RY/BY#.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm
is in progress or complete, or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is valid after the rising edge
of the final WE# pulse in the command sequence (prior to the program or erase
operation), and during the sector erase time-out.
58 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004
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Advance Information
During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system may use either OE# or CE#
to control the read cycles. When the operation is complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing
are protected, DQ6 toggles for approxi mately 400 µs, then returns to reading
array data. If not all selected sectors are protected, the Embedded Erase algo
rithm erases the unprotected sectors, and ignores the selected sectors that are
protected.
The system can use DQ6 and DQ2 together to determine whether a sector is ac tively erasing or is erase-suspende d. When the device is actively er asing (that is,
the Embedded Erase algorithm is in progress), DQ6 toggles. When the device en
ters the Erase Suspend mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing or erase-suspende d. A lter
natively, the system can use DQ7 (see “DQ7: Data# Polling” on page 56).
If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program command sequence is written, then returns to
reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling
once the Embedded Program algorithm is complete.
-
-
-
Table 14 shows the outputs for T og gle Bit I on DQ6. Fi gure 7 shows the toggle bit
algorithm. Figure 19 in “R ead Operation Timings” shows the toggle bit timing diagrams. Figure 20 shows the differences between DQ2 and DQ6 in graphical
form. See also “DQ2: Toggle Bit II”.
START
Read Byte
(DQ7–DQ0)
Address =VA
Read Byte
(DQ7–DQ0)
Address =VA
No
No
Toggle Bit
= Toggle?
Yes
DQ5 = 1?
Yes
Read Byte Twice
(DQ7–DQ0)
Address = VA
Toggle Bit
= Toggle?
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
No
Program/Erase
Operation Complete
Figure 7. Tog g l e B i t A l go r it h m
June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 59
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Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle
bit may stop toggling as DQ5 changes to “1.” See
gle Bit II” for more information.
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular
sector is actively erasing (that is, the Embedded Er ase al gorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit II is valid after the rising
edge of the final WE# pulse in the command sequence.
DQ2 toggles when the system reads at addresses within those sectors that hav e
been selected for erasure. (The system may use either OE# or CE1# / CE2# to
control the read cycles.) But DQ2 cannot distinguish whether the sector is actively
erasing or is erase-suspend ed. DQ6, by comparison, indicates whether the device
is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors
are selected for erasure. Thus, both status bits are required for s ector and mode
information. See
Figure 7 shows the toggle bit algorithm in flowchart form, and the “DQ2: To ggle
Bit II” explains the algorithm. See also “DQ6: Toggle Bit I.” Figure 19 shows the
toggle bit timing diagram. Figure 20 shows the differences between DQ2 and DQ6
in graphical form.
Advance Information
“DQ6: Toggle Bit I” and “DQ2: Tog-
Figure 7. Toggle Bit Algorithm
Table 14 to compare outputs for DQ2 and DQ6.
Reading Toggle Bits DQ6/DQ2
Refer t o Fi gure 7 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the system would note and
store the value of the toggle bit after the first read. After the second read, the
system would compare the new value of the toggle bit with the first. If the toggle
bit is not toggling, the device has completed the program or erase ope ration. The
system can read array data on DQ7–DQ0 on the following read cycle.
However , if after the initial two read cycles, the system determines that the toggle
bit is still toggling, the system also should note whether the value of DQ5 is high
“DQ5: Exceeded Timing Limits”). If it is, the system should then determine
(see
again whether the toggle bit is toggling, since the toggle bit may have stopped
toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device
has successfully completed the program or erase operation. If it is still toggling,
the device did not completed the operation successfully, and the system must
write the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit
is toggling and DQ5 has not gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, determining the status as de
scribed in the previous paragraph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the beginning of the algo
rithm when it returns to determine the status of the operation (top of Figure 7).
-
-
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceede d a speci fied in ternal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that the
program or erase cy cle was not su ccessfully completed .
The device may output a “1” on DQ5 if the system tries to program a “1” to a
location that was previously programmed to “0.” Only an erase operation can
60 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004
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Advance Information
change a “0” back to a “1.” Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a “1.”
Under both these conditions, the system must write the reset command to return
to the read mode (or to the erase-suspend-read mode if a bank was previously
in the erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not
apply to the chip erase command.) If additional sectors ar e selected for er asure,
the entire time-out also applies after each additional sector erase command.
When the time-out period is complete, DQ3 switches from a “0” to a “1.” See also
“Sector Erase Command Sequence” on page 49.
After the sector erase command is written, the sys tem shoul d re ad the status of
DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted
the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase
algorithm has begun; all further commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is “0,” the device accepts additional
sector erase commands. To ensure the command has been accepted, the system
software should check the status of DQ3 prior to and following each subsequent
sector erase command. If DQ3 is high on the second status check, the last com
mand might not have been accepted.
-
Table 14 shows the status of DQ3 relative to the other status bits.
Ta bl e 1 4 . Write Operation Status
DQ7
Status
Standard
Mode
Erase
Suspend
Mode
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing
limits.
2. DQ7 and DQ2 require a valid addres s when read ing status information. Refer to the appropriate subsection for
further details.
3. When reading write operation status bits, the system must always provide the bank address where the Embedded
Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank.
Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0
Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0
Erase
Erase-SuspendRead
Erase-Suspend-Progr a m DQ7# T oggle 0 N/A N/A 0
“DQ5: Exceeded Timing Limits” for more information.
Suspended Sector
Non-Erase
Suspended Sector
(Note 2) DQ6
1 No toggle 0 N/A Toggle 1
Data Data Data Data Data 1
DQ5
(Note 1) DQ3
DQ2
(Note 2) RY /B Y #
June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 61
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Absolute Maximum Ratings
20
20
20
Storage Temperature Plastic Packages . . . . . . . . . . . . . . . . –65°C to +150°C
Ambient Tempe rature with Power Applied . . . . . . . . . . . . . . –65°C to +125°C
Voltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
A9, OE#, and RESET# (Note 2) . . . . . . . . . . . . . . . . . . . . .–0.5 V to +13.0 V
WP#/ACC (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +10.5 V
All other pins (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to VCC +0.5 V
Output Short Circuit Current (Note 3). . . . . . . . . . . . . . . . . . . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions,
input or I/O pins may overshoot V
DC voltage on input or I/O pins is V
I/O pins may overshoot to V
2. Minimum DC input voltage on pins A9, OE#, RESET#, and WP#/ACC is –0.5 V.
During voltage transitions, A9, OE#, WP#/ACC, and RESET# may overshoot V
to –2.0 V for periods of up to 20 ns. See Figure 8. Maximum DC input voltage on
pin A9, OE#, and RESET# is +12.5 V which may overshoot to +14.0 V for periods
up to 20 ns. Maximum DC input voltage on WP#/ACC is +9.5 V which may
overshoot to +12.0 V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a time. Duration of the
short circuit should not be greater than one second.
4. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this data sheet is not implied. Exp osure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
Advance Information
to –2.0 V for periods of up to 20 ns. Maximum
SS
+0.5 V. During voltage transitions, input or
CC
+2.0 V for periods up to 20 ns. See Figure 8.
CC
SS
+0.8 V
–0.5 V
–2.0 V
ns
ns
V
CC
+2.0 V
V
CC
+0.5 V
2.0 V
20 ns
Maximum Negative Overshoot Waveform Maximum Positive Overshoot Waveform
20 ns
Figure 8. Maximum Overshoot Waveforms
ns
20 ns
62 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004
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Operating Ranges
Operating ranges define those limits between which the functionality of the device is guaranteed.
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to +85°C
Extended (E) Devices
Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . –5 5°C to +125°C
Supply Voltages
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.7–3.6 V
VIO or 2.7–3.6 V
Notes:
For all AC and DC specifications, V
options.
V
IO
Advance Information
= VCC; contact your local sales office for other
IO
June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 63
Page 64
DC Characteristics
Advance Information
Ta bl e 1 5 . CMOS Compatible
Parameter
Symbol
I
LI
I
LIT
I
LR
I
LO
I
CC1
I
CC2
I
CC3
I
CC4
I
CC5
I
CC6
I
CC7
I
CC8
I
CC9
V
IL
V
IH
V
HH
V
ID
V
OL
V
OH
V
LKO
Parameter Description Test Conditions Min Typ Max Unit
Input Load Current
A9, OE#, RESET# Input Load Current VCC = V
Reset Leakage Current VCC = V
Output Leakage Current
VCC Active Read Current (Notes 1, 2)
VCC Active Write Current (Notes 2, 3) OE# = VIH, WE# = V
VCC Standby Current (Note 2)
VCC Reset Current (Note 2) RESET# = V
Automatic Sleep Mode (Notes 2, 4)
VCC Active Read-While-Program Current
1, 2)
(Notes
VCC Active Read-While-Erase Current
(Notes
1, 2)
VCC Active Program-While-EraseSuspended Current (Notes 2, 5)
VIN = VSS to VCC,
VCC = VCC
V
OUT
VCC = V
OE# = VIH, VCC = V
(Note 1)
CE#, RESET#, WP#/ACC
= VIO ± 0.3 V
VIH = V
V
IL
max
; VID= 12.5 V 35 µA
CC max
; VID= 12.5 V 35 µA
CC max
= VSS to VCC, OE# = V
CC max
CC max
IL
± 0.3 V 0.2 5 µA
SS
± 0.3 V;
IO
= V
± 0.3 V
SS
OE# = VIH,
OE# = VIH,
OE# = V
IH
IH
5 MHz 20 30
10 MHz 45 55
5 MHz 21 45
10 MHz 46 70
5 MHz 21 45
10 MHz 46 70
±1.0 µA
±1.0 µA
mA
15 25 mA
0.2 5 µA
0.2 5 µA
mA
mA
17 25 mA
VCC Active Page Read Current (Note 2) OE# = VIH, 8 word Page Read 10 15 mA
Input Low Voltage VIO = 2.7–3.6 V –0.5 0.8 V
Input High Voltage VIO = 2.7–3.6 V 2.0 VCC+0.3 V
Voltage for ACC Program Acceleration VCC = 3.0 V ± 10% 8.5 9.5 V
Voltage for Autoselect and Temporary
Sector Unprotect
Output Low Voltage
Output High Voltage
VCC = 3.0 V ± 10% 11.5 12.5 V
IOL = 2.0 mA, VCC = V
V
IOH = –2.0 mA, VCC = V
V
, VIO = 2.7–3.6
CC min
, VIO = 2.7–3.6
CC min
0.4 V
2.4 V
Low VCC Lock-Out Voltage (Note 5) 2.3 2.5 V
Notes:
1. The ICC current listed is typically less than 5 mA/MHz, with OE# at VIH.
2. Maximum ICC specifications are tested with VCC = V
CCmax
.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. Automatic sleep mode enables the low power mode when addresses rema in stable for t
+ 30 ns. Typical sleep
ACC
mode current is 1 mA.
5. Not 100% tested.
6. In S29PL129J there are two CE# (CE1#, CE2#).
7. Valid CE1#/CE2# conditions: (CE1# = V
CE2# = V
IL,
) or (CE1# = V
IH,
CE2# = VIL) or (CE1# = V
IH,
CE2# = VIH)
IH,
64 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004
Page 65
AC Characteristics
Test Conditions
Advance Information
3.6 V
Device
Under
Test
Note: Diodes are IN3064 or equivalent
C
L
VIO = 3.0 V
6.2 kΩ
2.7 kΩ
Figure 9. Test Setups
Ta b l e 1 6 . Test Specifications
Test Condition All Speeds Unit
Output Load 1 TTL gate
Output Load Capacitance, CL (including jig capacitance) 30 pF
Input Rise and Fall Times VIO = 3.0 V 5 ns
Input Pulse Levels VIO = 3.0 V 0.0–3.0 V
Input timing measurement reference levels VIO/2 V
Output timing measurement reference levels VIO/2 V
Switching Waveforms
Ta b l e 1 7 . Key to Switching Waveforms
Wavef orm Inputs Outputs
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted Changing, State Unknown
Does Not Apply Center Line is High Impedance State (High Z)
June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 65
Page 66
Advance Information
VIO
VIO/2 VIO/2
OutputMeasurement LevelIn
0.0 V
Figure 10. Input Waveforms and Measurement Levels
VCC RampRate
All DC characteristics are specified for a VCC ramp rate > 1V/100 µs and V
>=V
- 100 mV. If the VCC ramp rate is < 1V/100 µs, a hardware reset
CCQ
required.+
CC
Read Operations
Ta bl e 1 8 . Read-Only Operations
Parameter
JEDEC Std. 55 60 65 70 Unit
t
AVAVtRC
t
AVQVtACC
t
ELQV
t
GLQVtOE
t
EHQZtDF
t
GHQZtDF
t
AXQXtOH
Description
Read Cycle Time (Note 1) Min 55 60 65 70 ns
Address to Output Delay CE#, OE# = VILMax 55 60 65 70 ns
t
Chip Enable to Output Delay OE# = V
CE
t
Page Access Time Max 20 25 25 30 ns
PACC
Output Enable to Output Delay Max 20 25 30 ns
Chip Enable to Output High Z (Note 3) Max 16 ns
Output Enable to Output High Z
(Notes 1, 3)
Output Hold Time From Addresses, CE# or
OE#, Whichever Occurs First
(Note 3)
Te s t S e t up
IL
Max 55 60 65 70 ns
Max 16 ns
Min 5 ns
Speed Options
Read Min 0 ns
Output Enable Hold
t
OEH
Notes:
1. Not 100% tested.
2. See Figure 9 and Table 16 for test specifications
3. Measurements performed by placing a 50 ohm termination on the data pin with a bias of VCC /2. The time from OE#
high to the data bus driven to V
4. S29PL129J has two CE# (CE1#, CE2 #).
5. Valid CE1# / CE2# conditions: (CE1# = VIL,CE2# = VIH) or (CE1# = VIH,CE2# = VIL) or (CE1# = V
6. Valid CE1# / CE2# transitions: (CE1# = VIL,CE2# = VIH) or (CE1# = VIH,CE2# = VIL) to (CE1# = CE2# = VIH)
7. Valid CE1# / CE2# transitions: (CE1# = CE2# = VIH) to (CE1# = VIL,CE2# = VIH) or (CE1# = VIH,CE2# = VIL)
8. For 70pF Output Load Capacitance, 2 ns is added to the above t
Time
(Note 1)
Toggle and
Data# Polling
/2 is taken as tDF.
CC
ACC,tCE,tPACC,tOE
Min 10 ns
CE2# = VIH)
IH,
values for all speed grades
66 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004
Page 67
Advance Information
t
RC
Addresses
Addresses Stable
t
ACC
CE#
t
RH
OE#
WE#
t
RH
t
OEH
t
OE
t
CE
t
OH
t
DF
HIGH Z
Data
Valid Data
RESET#
RY/BY#
Notes:
1. S29PL129J - During CE1# transitions, CE2# = VIH; During CE2# transitions, CE1# = VIH
2. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2#
0 V
Figure 11. Read Operation Timings
Amax-A3
Same Page
HIGH Z
-
A0
A2
Data
t
ACC
Aa
Ab Ac
t
PACC
t
PACC
Qa Qb Qc Qd
t
PACC
Ad
CE#
OE#
Notes:
1. S29PL129J - During CE1# transitions, CE2# = VIH; During CE2# transitions, CE1# = VIH
2. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2#
Figure 12. Page Read Operation Timings
June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 67
Page 68
Advance Information
Reset
Ta bl e 1 9 . Hardware Reset (RESET#)
Parameter
Description All Speed Options UnitJEDEC Std
t
Ready
t
Ready
t
Note: Not 100% tested.
RESET# Pin Low (During Embedded Algorithms)
to Read Mode
RESET# Pin Low (NOT During Embedded
Algorithms) to Read Mode
t
RESET# Pulse Width Min 500 ns
RP
t
Reset High Time Before Read (See Note) Min 50 ns
RH
RESET# Low to Standby Mode Min 20 µs
RPD
t
RY/BY# Recovery Time Min 0 ns
RB
RY/BY#
CE#, OE#
RESET#
(See Note)
t
RP
t
Ready
(See Note)
Max 20 µs
Max 500 ns
t
RH
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
t
Ready
RY/BY#
t
RB
CE#, OE#
RESET#
t
RP
Notes:
1. S29PL129J - During CE1# transitions, CE2# = VIH; During CE2# transitions, CE1# = VIH
2. S29PL129J - There are two CE# (CE1#, CE2#). In the below waveform CE# = CE1# or CE2#
Figure 13. Reset Timings
68 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004
Page 69
Advance Information
Erase/Program Operations
Ta bl e 2 0 . Erase and Program Operations
Parameter Speed Options
JEDEC Std
t
AVAV
t
AVWL
t
WLAX
t
DVWH
t
WHDX
t
GHWL
t
ELWL
t
WHEH
t
WLWH
t
WHDL
t
WHWH1tWHWH1
t
WHWH1tWHWH1
t
WHWH2tWHWH2
t
WC
t
AS
t
ASO
t
AH
t
AHT
t
DS
t
DH
t
OEPH
t
GHWL
t
CS
t
CH
t
WP
t
WPH
t
SR/W
t
VCSVCC
t
RB
t
BUSY
Description
55 60 65 70 Unit
Write Cycle Time (Note 1) Min 55 60 65 70 ns
Address Setup Time Min 0 ns
Address Setup Time to OE# low during toggle bit
polling
Min 15 ns
Address Hold Time Min 30 35 ns
Address Hold Time From CE1#, CE#2 or OE# high
during toggle bit polling
Min 0 ns
Data Setup Time Min 25 30 ns
Data Hold Time Min 0 ns
Output Enable High during toggle bit polling Min 10 ns
Read Recovery Time Before Write
(OE# High to WE# Low)
Min 0 ns
CE1# or CE#2 Setup Time Min 0 ns
CE1# or CE#2 Hold Time Min 0 ns
Write Pulse Width Min 35 ns
Write Pulse Width High Min 20 25 ns
Latency Between Read and Write Operations Min 0 ns
Programming Operation (Note 4) Typ 6 µs
Accelerated Programming Operation (Note 4) Typ 4 µs
Sector Erase Operation (Note 4) Typ 0.5 sec
Setup Time (Note 1) Min 50 µs
Write Recovery Time from RY/BY# Min 0 ns
Max 90 ns
Program/Erase Valid to RY/BY# Delay
Min 35 ns
Notes:
1. Not 100% tested.
2. S29PL129J - During CE1# transitions, CE2# = VIH; During CE2# transitions, CE1# = VIH
3. S29PL129J - There are two CE# (CE1#, CE2#).
4. See Table 25, “Erase And Programming Performance,” on page 78 for more information.
June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 69
Page 70
Timing Diagrams
Advance Information
Addresses
CE#
Program Command Sequence (last two cycles)
t
WC
555h
t
AS
PA PA
t
AH
t
CH
Read Status Data (last two cycles)
PA
OE#
t
t
WP
WHWH1
WE#
t
WPH
t
DH
PD
t
BUSY
Status
Data
t
CS
t
DS
A0h
RY/BY#
V
CC
t
VCS
Notes:
1. PA = program address, PD = program data, D
2. S29PL129J - During CE1# transitions, CE2# = VIH; During CE2# transitions, CE1# = VIH
is the true data at the program address
OUT
3. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2#
Figure 14. Program Operation Timings
D
OUT
t
RB
V
HH
V
or V
IL
WP#/ACC
IH V
t
VHH
t
VHH
IL
or V
IH
Figure 15. Accelerated Program Timing Diagram
70 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004
Page 71
Advance Information
Erase Command Sequence (last two cycles) Read Status Data
t
AS
555h for chip erase
VA
t
AH
VA
Addresses
t
WC
2AAh SA
CE#
t
t
WP
t
DS
55h
CH
t
WPH
t
DH
30h
10 for Chip Erase
t
BUSY
t
WHWH2
Status D
t
OUT
RB
OE#
WE#
Data
t
CS
RY/BY#
t
VCS
V
CC
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status” on
page 56
2. S29PL129J - During CE1# transitions, CE2# = VIH; During CE2# transitions, CE1# = V
3. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2#
IH
Figure 16. Chip/Sector Erase Operation Timings
June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 71
Page 72
Advance Information
Addresses
CE#
OE#
WE#
Data
t
WC
Valid PA
t
t
AS
t
WPH
AH
t
WP
t
DS
t
DH
Valid
In
t
OEH
t
RC
Valid RA
t
ACC
t
CE
t
SR/W
t
OE
t
GHWL
t
DF
t
OH
Valid
Out
Read Cycle
t
WC
Valid PA
Valid
In
CE# Controlled Write CyclesWE# Controlled Write Cycle
t
CPH
t
WC
Valid PA
t
AS
t
AH
t
CP
Valid
In
Figure 17. Back-to-back Read/Write Cycle Timings
t
RC
Addresses
t
ACC
t
CE
VA
VA VA
CE#
t
CH
t
OE
OE#
t
OEH
t
DF
WE#
t
DQ7
DQ6–DQ0
t
BUSY
OH
Complement
Status Data
Complement
Status Data
Tr u e
Tr u e
Valid Data
Valid Data
High Z
High Z
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array
data read cycle
Figure 18. Data# Polling Timings (During Embedded Algorithms)
72 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004
Page 73
Advance Information
t
AHT
Addresses
t
ASO
CE#
t
OEH
WE#
OE#
t
DH
DQ6/DQ2 Valid Data
RY/BY#
Valid Data
(first read) (second read) (stops toggling)
Valid
Status
t
OEPH
t
OE
Valid
Status
t
CEPH
t
t
AS
AHT
Valid
Status
Notes:
1. VA = Valid address; not required for DQ6. Illustration shows first two status cycle after co mmand sequence, last
status read cycle, and array data read cycle
2. S29PL129J - During CE1# transitions, CE2# = VIH; During CE2# transitions, CE1# = VIH
3. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2#
Figure 19. Toggle Bit Timings (During Embedded Algorithms)
Enter
Embedded
Erasing
WE#
Erase
Erase
Suspend
Erase Suspend
Suspend Program
Read
Enter Erase
Erase
Suspend
Program
Erase Suspend
Read
Erase
Resume
Erase
Erase
Complete
DQ6
DQ2
Note:Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or
CE# to toggle DQ2 and DQ6.
Figure 20. DQ2 vs. DQ6
June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 73
Page 74
Protect/Unprotect
Parameter
Advance Information
Ta bl e 2 1 . Temporary Sector Unprotect
Description
t
VIDR VID
t
VHHVHH
t
t
RESET# Setup Time for Temporary Sector
RSP
Unprotect
RESET# Hold Time from RY/BY# High for
RRB
Temporary Sector Unprotect
Note: Not 100% tested.
V
RESET#
WE#
V
CE#
All Speed OptionsJEDEC Std
Rise and Fall Time (See Note) Min 500 ns
Rise and Fall Time (See Note) Min 250 ns
Min 4 µs
Min 4 µs
ID
IL
or V
IH
t
RRB
t
VIDR
t
VIDR
t
Program or Erase Command Sequence
RSP
V
ID
V
or V
IL
IH
Unit
RY/BY#
Figure 21. Temporary Sector Unprotect Timing Diagram
74 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004
Page 75
RESET#
Advance Information
V
ID
V
IH
SA, A6,
A1, A0
Valid* Valid* Valid*
Sector Group Protect/Unprotect Verify
Data
60h 60h 40h
1 µs
CE#
Sector Group Protect: 150 µs
Sector Group Unprotect: 15 ms
WE#
OE#
Notes:
1. For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
2. S29PL129J - During CE1# transitions, CE2# = VIH; During CE2# transitions, CE1# = VIH
3. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2#
Figure 22. Sector/Sector Block Protect and Unprotect Timing Diagram
Status
June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 75
Page 76
Advance Information
Controlled Erase Operations
Table 22. Alternate CE# Controlled Erase and Program Operations
Parameter Speed Options
JEDEC Std
t
AVAV
t
AVWL
t
ELAX
t
DVEH
t
EHDX
t
GHEL
t
WLEL
t
EHWH
t
ELEH
t
EHEL
t
WHWH1
t
WHWH1
t
WHWH2
Notes:
1. Not 100% tested.
2. See the Table 25, “Erase And Programming Performance,” on page 78 for more information.
t
WC
t
t
t
t
DH
t
GHEL
t
WS
t
WH
t
t
CPH
t
WHWH1
t
WHWH1
t
WHWH2
Description
55 60 65 70 Unit
Write Cycle Time (Note 1) Min 55 60 65 70 ns
Address Setup Time Min 0 ns
AS
Address Hold Time Min 30 35 ns
AH
Data Setup Time Min 25 30 ns
DS
Data Hold Time Min 0 ns
Read R e c o very Time Before Write
(OE# High to WE# Low)
Min 0 ns
WE# Setup Time Min 0 ns
WE# Hold Time Min 0 ns
CE1# or CE#2 Pulse Width Min 35 40 ns
CP
CE1# or CE#2 Pulse Width High Min 20 25 ns
Programming Operation (Note 2) Typ 6 µs
Accelera ted Programming Operat io n (Note 2) Typ 4 µs
Sector Erase Operation (Note 2) Typ 0.5 sec
76 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004
Page 77
Advance Information
Addresses
WE#
OE#
CE#
Data
RESET#
555 for program
2AA for erase
t
WC
t
WH
t
WS
t
RH
PA for program
SA for sector erase
555 for chip erase
t
AS
t
GHEL
t
CP
t
CPH
t
DS
t
DH
A0 for program
55 for erase
t
AH
t
BUSY
PD for program
30 for sector erase
10 for chip erase
Data# Polling
t
WHWH1 or 2
PA
DQ7# D
OUT
RY/BY#
Notes:
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. D
4. S29PL129J - During CE1# transitions, CE2# = VIH; During CE2# transitions, CE1# = VIH
is the data written to the device
OUT
5. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2#
Ta b l e 2 3 . Alternate CE# Controlled Write (Erase/Program) Operation Timings
Ta b l e 2 4 . CE1#/CE2# Timing
Parameter
Description All Speed Options UnitJEDEC Std
t
CE1#/CE2# Recover Time Min 30 ns
CCR
June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 77
Page 78
CE1#
CE2#
Advance Information
t
CCR
t
CCR
Figure 23. Timing Diagram for Alternating Between CE1# and CE2# Control
Ta bl e 2 5 . Erase And Programming Performance
Parameter
Sector Erase Time
Chip Erase Time
Word Program Time
Accelerated Word Program Time
Chip Program Time
(Note 3)
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 100,000 cycles. Additionally,
programming typicals assume checkerboard pattern. All values are subject to change.
2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles. All values are subject to change.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most
bytes program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h b e fore erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program
command. See
6. The device has a minimum erase and program cycle endurance of 100,000 cycles.
Table 12 for further information on command definitions.
PL129J 135 216 sec
PL129J 50.4 200 sec
Ty p (Note 1) Max (Note 2) Unit Comments
0.5 2 sec
6 100 µs
4 60 µs
Excludes 00h programming
prior to erasure
Excludes system level
overhead
(Note 5)
(Note 4)
BGA Pin Capacitance
Parameter Symbol Parameter Description Te s t S e t up Ty p Max Unit
C
C
C
C
OUT
IN
IN2
IN3
Input Capacitance VIN = 0 6.3 7 pF
Output Capacitance V
Control Pin Capacitance VIN = 0 5.5 8 pF
WP#/ACC Pin Capacitance VIN = 0 11 12 pF
= 0 7.0 8 pF
OUT
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
78 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004
Page 79
Advance Information
pSRAM Type 6
2M Word by 16-bit Cmos Pseudo Static RAM (32M Density)
4M Word by 16-bit Cmos Pseudo Static RAM (64M Density)
Features
Single power supply voltage of 2.6 to 3.3 V
Direct TTL compatibility for all inputs and outputs
Deep power-down mode: Memory cell data invalid
Page operation mode:
— Page read operation by 8 words
Logic compatible with SRAM R/W pin
Standby current
— Standby = 70 µA (32M)
— Standby = 100 µA (64M)
— Deep power-down Standby = 5 µA
Access Times
32M
64M
Pin Description
Pin Name Description
A0 to A
A0 to A2 Page Address Inputs
I/O1 to I/O16 Data Inputs/Outputs
CE1# Chip Enable Input
CE2 Chip select Input
WE# Write Enable Input
OE# Output Enable Input
LB#,UB# Data Byte Control Inputs
V
DD
GND Ground
21
Access Time 70 ns
CE1# Access Time 70 ns
OE# Access Time 25 ns
Page Access Time 30 ns
Address Inputs
Power Supply
NC Not Connec tion
Ocotober 16, 2004 pSRAM_Type06_14_A1 pSRAM Type 6 79
Page 80
Functional Description
Advance Information
Mode CE1# CE2 OE# WE# LB# UB# Address I/O
Read (Word) L H L H L L X D
Read (Lower Byte) L H L H L H X D
Read (Upper Byte) L H L H H L X High-Z D
Write (Word) L H X L L L X D
Write (Lower Byte) L H X L L H X D
Write (Upper Byte) L H X L H L X Invalid D
Outputs Disabled L H H H X X X High-Z High-Z I
Standby H H X X X X X High-Z High-Z I
Deep Power-down Standby H L X X X X X High-Z High-Z I
1-8
OUT
OUT
IN
IN
I/O
9-16
D
OUT
High-Z I
OUT
D
IN
Invalid I
IN
Power
Legend:L = Low-level Input (VIL), H = High-level Input (VIH), X = VIL or VIH, High-Z = High Impedance.
Absolute Maximum Ratings
Symbol Rating Val ue Unit
V
V
V
T
T
I
DD
IN
OUT
opr
strg
P
D
OUT
Power Supply Voltage -1.0 to 3.6 V
Input Voltage -1.0 to 3.6 V
Output Voltage -1.0 to 3.6 V
Operating Temperature -40 to 85 °C
Storage Temperature -55 to 150 °C
Power Dissipation 0.6 W
Short Circuit Output Current 50 mA
I
DDO
DDO
I
DDO
I
DDO
DDO
I
DDO
DDO
DDO
DDSD
Note: ESD Immunity: Spansion Flash memory Multi-Chip Products (MCPs) may contain component devices that are
developed by Spansion and component devices that are developed by a third party (third-party components). Spansion
components are tested and guaranteed to the ESD immunity levels listed in the corresponding Spansion Flash memory
Qualification Database. Third-party components are neither tested nor guaranteed by Spansion for ESD immunity. How
ever, ESD test results for third-party components may be available from the component manufacturer. Component manufacturer contact information is listed in the Spansion MCP Qualification Report, when available. The Sp ansi on Flash
memory Qualification Database and Spansion MCP Qua li f ic ation Report are available from Spansion sales offices.
DC Recommended Operating Conditions (Ta = -40°C to 85°C)
Symbol Parameter Min Ty p Max Unit
V
DD
IH
V
IL
Note: VIH (Max) VDD = 1.0 V with 10 ns pulse width. VIL (Min) -1.0 V with 10 ns pulse width.
80 pSRAM Type 6 pSRAM_Type06_14_A1 Ocotober 16, 2004
Power Supply Voltage 2.6 2.75 3.3
Input High Voltage 2.0 — VDD + 0.3 (Note)
Input Low Voltage -0.3 (Note) — 0.4
VV
-
Page 81
Advance Information
DC Characteristics (Ta = -40°C to 85°C, VDD = 2.6 to 3.3 V) (See Note 3 to 4)
Symbol Parameter Test Condition Min Ty p . Max Unit
Input Leakage
I
I
V
V
I
DDO1
IL
Current
Output Leakage
LO
Current
Output High Voltage IOH = - 0.5 mA 2.0 ¾ V V
OH
Output Low Voltage IOL = 1.0 mA — — 0.4 V
OL
Operating Current
VIN = 0 V to V
Output disable, V
DD
= 0 V to V
OUT
CE1#= VIL, CE2 = VIH, I
mA, t
= min.
RC
OUT
-1.0 — +1.0 µA
DD
ET5UZ8A-43DS — — 40
= 0
-1.0 — +1.0 µA
ET5VB5A-43DS — — 50
mA
I
DDO2
I
DDS
I
DDSD
Page Access
Operating Current
Standby Current
(MOS)
Deep Power-down
Standby Current
CE1#= VIL, CE2 = VIH, I
OUT
= 0 mA
Page add. cycling, tRC = min.
CE1# = VDD - 0.2 V,
CE2 = VDD - 0.2 V
ET5UZ8A-43DS — — 70 mA
ET5VB5A-43DS — — 100 µA
CE2 = 0.2 V — — 5 µA
Capacitance (Ta = 25°C, f = 1 MHz)
Symbol Parameter Test Condition Max Unit
C
IN
C
OUT
Note: This parameter is sampled periodically and is not 100% tested.
Input Capacitance VIN = GND 10 pF
Output Capacitance V
= GND 10 pF
OUT
AC Characteristics and Operating Conditions
(Ta = -40°C to 85°C, VDD = 2.6 to 3.3 V) (See Note 5 to 11)
Symbol Parameter Min Max Unit
t
RC
t
ACC
t
CO
t
OE
t
BA
t
COE
t
OEE
t
BE
t
OD
t
ODO
t
BD
Read Cycle Time 70 10000 ns
Address Access Time — 70 ns
Chip Enable (CE1#) Access Time — 70 ns
Output Enable Access Time — 25 ns
Data Byte Control Access Time — 25 ns
Chip Enable Low to Output Active 10 — ns
Output Enable Low to Output Active 0 — ns
Data Byte Control Low to Output Active 0 — ns
Chip Enable High to Output High-Z — 20 ns
Output Enable High to Output High-Z — 20 ns
Data Byte Control High to Output High-Z — 20 ns
— — 25 mA
Ocotober 16, 2004 pSRAM_Type06_14_A1 pSRAM Type 6 81
Page 82
Advance Information
Symbol Parameter Min Max Unit
t
OH
t
PM
t
PC
t
AA
t
AOH
t
WC
t
WP
t
CW
t
BW
t
AW
t
AS
t
WR
t
CEH
t
WEH
t
ODW
t
OEW
t
DS
t
DH
t
CS
t
CH
t
DPD
t
CHC
t
CHP
Output Data Hold Time 10 — ns
Page Mode Time 70 10000 ns
Page Mode Cycle Time 30 — ns
Page Mode Address Access Time — 30 ns
Page Mode Output Data Hold Time 10 — ns
Write Cycle Time 70 10000 ns
Write Pulse Width 50 — ns
Chip Enable to End of Write 70 — ns
Data Byte Control to End of W rite 60 — ns
Address Valid to End of Wr ite 60 — ns
Address Set-up Time 0 — ns
Write Recov ery Time 0 — ns
Chip Enable High Pulse Width 10 — ns
Write Enable High Pulse Width 6 — ns
WE# Low to Output High-Z — 20 ns
WE# High to Output Active 0 ns
Data Set-up Time 30 — ns
Data Hold Time 0 — ns
CE2 Set-up Time 0 — ns
CE2 Hold Time 300 — µs
CE2 Pulse Width 10 — ms
CE2 Hold from CE1# 0 — ns
CE2 Hold from Power On 30 — µs
AC Test Conditions
Parameter Condition
Output load 30 pF + 1 TTL Gate
Input pulse level VDD - 0.2 V, 0.2 V
Timing measurements VDD x 0.5
Reference level VDD x 0.5
tR, t
F
82 pSRAM Type 6 pSRAM_Type06_14_A1 Ocotober 16, 2004
5 ns
Page 83
Timing Diagrams
Read Timings
Address
A0 to A20(32M)
A0 to A21(64M)
CE1#
Advance Information
t
RC
t
ACC
t
CO
t
OH
CE2
OE#
WE#
UB#, LB#
D
OUT
I/O1 to I/O16
Fix-H
t
t
ODO
BD
t
OD
t
OE
t
BA
t
BE
t
OEE
Hi-Z Hi-Z
t
COE
INDETERMINATE
VALID DATA OUT
Figure 24. Read Cycle
Ocotober 16, 2004 pSRAM_Type06_14_A1 pSRAM Type 6 83
Page 84
Address
A
A0 to A2
Address
3 to A20(32M)
A3 to A21(64M)
CE1#
Advance Information
t
PM
t
RC
t
PC
t
PC
t
PC
CE2
OE#
WE#
UB#, LB#
D
OUT
I/O1 to I/O16
Fix-H
t
t
BA
t
OEE
t
BE
Hi-Z Hi-Z
t
COE
t
CO
t
ACC
OE
D
OUT
t
AOH
t
AOH
D
OUT
t
AA
D
OUT
t
AA
* Maximum 8 words
t
AOH
t
BD
t
OH
D
OUT
t
AA
t
ODO
t
OD
Figure 25. Page Read Cycle (8 Words Access)
84 pSRAM Type 6 pSRAM_Type06_14_A1 Ocotober 16, 2004
Page 85
Write Timings
A
A
Address
0 to A20
(32M)
0 to
A21(64M)
WE#
CE1#
CE2
, LB#
UB#
D
OUT
I/O1 to I/O16
D
IN
I/O1 to I/O16
Advance Information
t
WC
t
AW
t
CH
t
AS
t
ODW
(See Note 9) (See Note 9)
t
WP
t
CW
t
BW
t
VALID DATA IN
DS
t
OEW
t
DH
t
WR
t
WR
t
WR
Figure 26. Write Cycle #1 (WE# Controlled) (See Note 8)
t
WEH
(See Note 11)(S )ee Note 10 Hi-Z
Ocotober 16, 2004 pSRAM_Type06_14_A1 pSRAM Type 6 85
Page 86
Address
A0 to A20
A0 to
(32M)
A21(64M)
UB#, LB#
D
I/O1 to I/O16
I/O1 to I/O16
WE#
CE1#
CE2
OUT
D
Advance Information
t
WC
t
AW
t
CW
t
BW
t
WP
t
WR
t
WR
t
WR
t
CEH
t
AS
t
CH
t
t
ODW
BE
Hi-Z Hi-Z
t
COE
t
DS
IN
(See Note 9)
VALID DATA IN
t
DH
Figure 27. Write Cycle #2 (CE# Controlled) (See Note 8)
Deep Power-down Timing
CE1#
CE2
t
Figure 28. Deep Power Down Timing
Power- on Ti ming
V
DD
CE1#
CE2
VDD min
t
DPD
CS
t
CHC
t
CHP
Figure 29. Power-on Timing
t
CH
t
CH
86 pSRAM Type 6 pSRAM_Type06_14_A1 Ocotober 16, 2004
Page 87
Advance Information
A
A
Provisions of Address Skew
Read
In case multiple invalid address cycles shorter than tRC min. sustain over 10 µs
in an active status, at least one valid address cy cle over t
ing 10µs.
CE1#
WE#
ddress
Write
In case multiple invalid address cycles shorter than tWC min. sustain over 10 µs
in an active status, at least one valid addre ss cycle over t
ing 10 µs.
over 10µs
Figure 30. Read
min. is required dur-
RC
t
min
RC
min. is required dur-
WC
CE1#
tWPmin
WE#
ddress
t
min
WC
Figure 31. Write
Notes:
1. Stresses greater than listed under "Absolute Maximum Ratings" section may cause perma nent damage to the device.
2. All voltages are reference to GND.
3. I
4. I
5. AC measurements are assumed t
6. Parameters t
7. Data cannot be retained at deep power-down stan d-by mode.
8. If OE# is high during the write cycle, the outputs will remain at high impedance.
9. During the output state of I/O signals, input signals of reverse polarity must not be applied.
10.If CE1# or LB#/UB# goes LOW coincident with or after WE# goes LOW, the outputs will remain at high impedance.
11.If CE1# or LB#/UB# goes HIGH coincident with or before WE# goes HIGH, the outputs will remain at high impedance.
depends on the cycle time.
DDO
depends on output loading. Specified values are defined with the output open condition.
DDO
, tF = 5 ns.
R
, t
reference levels.
OD
, tBD and tODW define the time at which the output goes the open condition and are not output voltage
ODO
Ocotober 16, 2004 pSRAM_Type06_14_A1 pSRAM Type 6 87
Page 88
Advance Information
pSRAM Type 1
4Mbit (256K Word x 16-bit)
8Mbit (512K Word x 16-bit)
16Mbit (1M Word x 16-bit)
32Mbit (2M Word x 16-bit)
64Mbit (4M Word x 16-bit)
Functional Description
Mode CE# CE2/ZZ# OE# WE# UB# LB# Addresses I/O 1-8 I/O 9-16 Power
Read (word) L H L H L L X Dout Dout I
Read (lower byte) L H L H H L X Dout High-Z I
Read (upper byte) L H L H L H X High-Z Dout I
Write (word) L H X L L L X Din Din I
Write (lower byte) L H X L H L X Din Invalid I
Write (upper byte) L H X L L H X Invalid Din I
Outputs disabled L H H H X X X High-Z High-Z I
Standby H H X X X X X High-Z High-Z I
Deep power down H L X X X X X High-Z High-Z I
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
STANDBY
DEEP SLEEP
Absolute Maximum Ratings
Item Symbol Ratings Units
Voltage on any pin relative to V
Voltage on VCC relative to V
Power dissipation P
Storage temperature T
Operating temperature T
SS
SS
Vin, Vout -0.2 to VCC +0.3 V
V
CC
D
STG
A
-0.2 to 3.6 V
1 W
-55 to 150 °C
-25 to 85 °C
88 pSRAM Type 1 pSRAM_Type01_12_A1 August 30, 2004
Page 89
DC Characteristics
(4Mb pSRAM Asynchronous)
Symbol Parameter Conditions Min Max Units
V
Power Supply 2.7 3.3 V
CC
V
Input High Level 0.8 Vccq VCC + 0.3 V
IH
Input Low Level -0.3 0.4 V
V
IL
Input Leakage
I
IL
Current
Output Leakage
I
LO
Current
Output High
V
OH
Voltage
Output Low
V
OL
Voltage
DEEP
Operating
Current
Standby Current
Deep Power
Down Current
1/4 Array PAR
Current
1/2 Array PAR
Current
I
ACTIVE
I
STANDBY
I
SLEEP
I
PAR 1/4
I
PAR 1/2
Advance Information
Performance Grade -70
Density 4Mb pSRAM
Vin = 0 to V
OE = VIH or
Chip Disabled
= -1.0 mA
I
OH
= -0.2 mA 0.8 Vccq
OH
= -0.5 mA
I
OH
I
OL
OL
I
OL
V
CC
V
CC
V
CC
CC
= 2.0 mA
= 0.2 mA 0.2
= 0.5 mA
= 3.3 V 25 mA
= 3.0 V 70
= 3.3 V
Asynchronous
0.5 µA
0.5 µA
VI
VI
µA
xµA
xµA
xµA
August 30, 2004 pSRAM_Type01_12_A1 pSRAM Type 1 89
Page 90
Advance Information
DC Characteristics
(8Mb pSRAM Asynchronous)
Asynchronous
Version B C
Performance Grade -55 -70 -70
Density 8Mb pSRAM 8Mb pSRAM 8Mb pSRAM
Symbol Parameter Conditions Min Max Units Min Max Units Min Max Units
V
Power Supply 2.7 3.3 V 2.7 3.6 V 2.7 3.3 V
CC
Input High Level 2.2 VCC + 0.3 V 2.2 VCC + 0.3 V 0.8 VCC+0.3 V
V
IH
Input Low Level -0.3 0.6 V -0.3 0.6 V -0.3 0.4 V
V
IL
Input Leakage
I
IL
I
LO
V
OH
V
OL
I
ACTIVE
I
STANDBY
I
DEEP
SLEEP
I
PAR 1/4
I
PAR 1/2
Current
Output Leakage
Current
Output High Voltage
Vin = 0 to V
OE = VIH or
Chip Disabled
I
OH
OH
CC
= -1.0 mA VCC-0.4
= -0.2 mA 0.8 V
IOH = -0.5 mA
I
= 2.0 mA 0.4
OL
Output Low Voltage
= 0.2 mA 0.2
OL
I
= 0.5 mA
OL
Operating Current VCC = 3.3 V 25 mA 23 mA 25 mA
= 3.0 V 60
V
Standby Current
Deep Power Down
Current
1/4 Array PAR
Current
1/2 Array PAR
Current
CC
V
CC
= 3.3 V
0.5 µA 0.5 µA 0.5 µA
0.5 µA 0.5 µA 0.5 µA
VCC-0.4
V
VVI
CCQ
0.4
µA
V
60
µA
VVI
70
xµA xµA xµA
xµA xµA xµA
xµA xµA xµA
µA
90 pSRAM Type 1 pSRAM_Type01_12_A1 August 30, 2004
Page 91
Advance Information
DC Characteristics
(16Mb pSRAM Asynchronous)
Asynchronous
Performance Grade -55 -70
Density 16Mb pSRAM 16Mb pSRAM
Symbol Parameter Conditions Minimum Maximum Units Minimum Maximum Units
V
V
V
I
V
V
I
ACTIVE
I
STANDBY
I
DEEP SLEEP
I
PAR 1/4
I
PAR 1/2
Power Supply 2.7 3.6 V 2.7 3.6 V
CC
Input High Level 2.2 VCC + 0.3 V 2.2 VCC + 0.3 V
IH
Input Low Level -0.3 0.6 V -0.3 0.6 V
IL
Input Leakage Current Vin = 0 to V
I
IL
Output Leakage Current OE = VIH or Chip Disabled 0.5 µA 0.5 µA
LO
I
= -1.0 mA VCC-0.4
OH
Output High Voltage
OH
Output Low Voltage
OL
= -0.2 mA
OH
I
= -0.5 mA
OH
I
OL
OL
I
OL
CC
= 2.0 mA 0.4
= 0.2 mA
= 0.5 mA
0.5 µA 0.5 µA
VCC-0.4
V
V
Operating Current VCC = 3.3 V 25 mA 25 mA
V
= 3.0 V 100
Standby Current
CC
V
CC
= 3.3 V
µA
Deep Power Down Current x µA x µA
1/4 Array PAR Current x µA x µA
1/2 Array PAR Current x µA x µA
0.4
100
VI
VI
µA
August 30, 2004 pSRAM_Type01_12_A1 pSRAM Type 1 91
Page 92
Advance Information
DC Characteristics
(16Mb pSRAM Page Mode)
Page Mode
Performance Grade -60 -65 -70
Density 16Mb pSRAM 16Mb pSRAM 16Mb pSRAM
Symbol Parameter Conditions Min Max Units Min Max Units Min Max Units
V
Power Supply 2.7 3.3 V 2.7 3.3 V 2.7 3.3 V
CC
Input High
V
IH
V
IL
I
IL
I
LO
V
OH
V
OL
I
ACTIVE
I
STANDBY
I
DEEP
SLEEP
I
PAR 1/4
I
PAR 1/2
Level
Input Low
Level
Input Leakage
Current
Output
Leakage
Current
Output High
Voltage
Output Low
Voltage
Operating
Current
Standby
Current
Deep Power
Down Current
1/4 Array PAR
Current
1/2 Array PAR
Current
0.8 Vccq V
-0.2 0.2 Vccq V -0.2 0.2 Vccq V -0.2 0.2 Vccq V
Vin = 0 to V
OE = V
Chip Disabled
= -1.0 mA
I
OH
= -0.2 mA
OH
= -0.5 mA 0.8 Vccq 0.8 Vccq 0.8 Vccq
I
OH
I
= 2.0 mA
OL
= 0.2 mA
OL
= 0.5 mA 0.2 Vccq 0.2 Vccq 0.2 Vccq
I
OL
V
CC
V
CC
V
CC
CC
or
IH
= 3.3 V 25 mA 25 mA 25 mA
= 3.0 V
= 3.3 V 100 100 100
+ 0.2 V 0.8 Vccq VCC + 0.2 V 0.8 Vccq VCC + 0.2 V
CC
1µA 1µA 1µA
1µA 1µA 1µA
VV VI
VV VI
µA µA µA
10 µA 10 µA 10 µA
65 µA 65 µA 65 µA
80 µA 80 µA 80 µA
92 pSRAM Type 1 pSRAM_Type01_12_A1 August 30, 2004
Page 93
Advance Information
DC Characteristics
(32Mb pSRAM Page Mode)
Page Mode
Version C E
Performance Grade -65 -60 -65 -70
Density 32Mb pSRAM 32Mb pSRAM 32Mb pSRAM 32Mb pSRAM
Symbol Parameter Conditions Min Max Units Min Max Units Min Max Units Min Max Units
Power
V
CC
V
IH
V
IL
I
IL
I
LO
V
OH
V
OL
I
ACTIVE
I
STANDBY
I
DEEP
SLEEP
I
PAR 1/4
I
PAR 1/2
Supply
Input High
Level
Input Low
Level
Input
Leakage
Current
Output
Leakage
Current
Output High
Voltage
Output Low
Voltage
Operating
Current
Standby
Current
Deep Power
Down
Current
1/4 Array
PAR Current
1/2 Array
PAR Current
Vin = 0 to V
OE = V
IH
Chip Disabled
= -1.0 mA
I
OH
I
= -0.2 mA
OH
= -0.5 mA 0.8 Vccq 0.8 Vccq
I
OH
= 2.0 mA
I
OL
I
= 0.2 mA 0.2
OL
I
= 0.5 mA
OL
= 3.3 V 25 mA 25 mA 25 mA 25 mA
V
CC
V
= 3.0 V
CC
= 3.3 V 100 120 120 120
V
CC
2.7 3.6 V 2.7 3.3 V 2.7 3.3 V 2.7 3.3 V
VCC +
1.4
0.2
-0.2 0.4 V -0.2
CC
or
Vccq
0.5 µA 1 µA 1 µA 1 µA
0.5 µA 1 µA 1 µA 1 µA
0.8
V0.8 Vccq
VVVV
VCC
+ 0.2
0.2
Vccq
V0.8 Vccq
V-0.2
+ 0.2
Vccq
VCC
0.2
0.8
V
Vccq
V-0.2
0.8
Vccq
VVVV
0.2
Vccq
0.2
Vccq
µA µA µA µA
10 µA 10 µA 10 µA 10 µA
65 µA 75 µA 75 µA 75 µA
80 µA 90 µA 90 µA 90 µA
V
CC
+
0.2
0.2
Vccq
0.2
Vccq
V
V
August 30, 2004 pSRAM_Type01_12_A1 pSRAM Type 1 93
Page 94
DC Characteristics
(64Mb pSRAM Page Mode)
Symbol Parameter Conditions Min Max Units
V
Power Supply 2.7 3.3 V
CC
V
Input High Level 0.8 Vccq VCC + 0.2 V
IH
Input Low Level -0.2 0.2 Vccq V
V
IL
Input Leakage
I
IL
Current
Output Leakage
I
LO
Current
Output High
V
OH
Voltage
Output Low
V
OL
Voltage
DEEP
Operating
Current
Standby Current
Deep Power
Down Current
1/4 Array PAR
Current
1/2 Array PAR
Current
I
ACTIVE
I
STANDBY
I
SLEEP
I
PAR 1/4
I
PAR 1/2
Advance Information
Page Mode
Performance Grade -70
Density 64Mb pSRAM
Vin = 0 to V
OE = VIH or
Chip Disabled
= -1.0 mA
I
OH
= -0.2 mA
OH
= -0.5 mA 0.8 Vccq
I
OH
I
OL
OL
I
OL
V
CC
V
CC
V
CC
CC
= 2.0 mA
= 0.2 mA
= 0.5 mA 0.2 Vccq
= 3.3 V 25 mA
= 3.0 V
= 3.3 V 120
1µA
1µA
VI
VI
µA
10 µA
65 µA
80 µA
Timing Test Conditions
Item
Input Pulse Level 0.1 VCC to 0.9 V
Input Rise and Fall Time 5ns
Input and Output Timing R e fere n ce Lev els 0.5 V
Operating Temperature -25°C to +85°C
94 pSRAM Type 1 pSRAM_Type01_12_A1 August 30, 2004
CC
CC
Page 95
Advance Information
Output Load Circuit
Power Up Sequence
After applying power, maintain a stable power supply for a minimum of 200 µs
after CE# > V
IH
V
CC
14.5K
I/O
14.5K
30 pF
Output Load
Figure 32. Output Load Circuit
.
August 30, 2004 pSRAM_Type01_12_A1 pSRAM Type 1 95
Page 96
AC Characteristics
(4Mb pSRAM Page Mode)
Advance Information
Asynchronous
Performance Grade -70
Density 4Mb pSRAM
3 Volt Symbol Parameter Min Max Units
trc Read cycle time 70 ns
Address Access
taa
Time
Chip select to
tco
output
Output enable to
toe
valid output
UB#, LB# Access
tba
time
Chip select to
tlz
Low-z output
UB#, LB# Enable
tblz
Read
tolz
thz
tbhz
tohz
toh
to Low-Z output
Output enable to
Low-Z output
Chip enable to
High-Z output
UB#, LB#
disable to High-Z
output
Output disable to
High-Z output
Output hold from
Address Change
10 ns
10 ns
5ns
020ns
020ns
020ns
10 ns
70 ns
70 ns
20 ns
70 ns
96 pSRAM Type 1 pSRAM_Type01_12_A1 August 30, 2004
Page 97
Advance Information
Asynchronous
Performance Grade -70
Density 4Mb pSRAM
3 Volt Symbol Parameter Min Max Units
twc Write cycle time 70 ns
Chipselect to end
tcw
of write
Address set up
tas
Time
Address valid to
taw
end of write
UB#, LB# valid
tbw
to end of write
twp Write pulse width 55 ns
Write recovery
twr
twhz
tdw
tdh
tow
tow
time
Write to output
High-Z
Data to write
time overlap
Data hold from
write time
End write to
output Low-Z
Write high pulse
width
Write
70 ns
0ns
70 ns
70 ns
0ns
20 ns
25 ns
0ns
5
7.5 ns
tpc Page read cycle x
Page address
tpa
access time
twpc Page write cycle x
Other
Chip select high
tcp
pulse width
x
x
August 30, 2004 pSRAM_Type01_12_A1 pSRAM Type 1 97
Page 98
AC Characteristics
(8Mb pSRAM Asynchronous)
Performance Grade -55 -70 -70
3 Volt Symbol Parameter Min Max Units Min Max Units Min Max Units
trc Read cycle time 55 ns 70 ns 70 ns
Address Access
taa
Time
Chip select to
tco
output
Output enable to
toe
valid output
UB#, LB# Access
tba
time
Chip select to
tlz
Low-z output
UB#, LB# Enable
tblz
Read
tolz
thz
tbhz
tohz
toh
to Low-Z output
Output enable to
Low-Z output
Chip enable to
High-Z output
UB#, LB#
disable to High- Z
output
Output disable to
High-Z output
Output hold from
Address Change
Advance Information
Asynchronous
Version B C
Density 8Mb pSRAM 8Mb pSRAM 8Mb pSRAM
55 ns 70 ns 70 ns
55 ns 70 ns 70 ns
30 ns 35 ns 20 ns
55 ns 70 ns 70 ns
5 ns 5 ns 10 ns
5 ns 5 ns 10 ns
5ns5ns5ns
020ns025ns020ns
020ns025ns020ns
020ns025ns020ns
10 ns 10 ns 10 ns
98 pSRAM Type 1 pSRAM_Type01_12_A1 August 30, 2004
Page 99
Advance Information
Asynchronous
Version B C
Performance Grade -55 -70 -70
Density 8Mb pSRAM 8Mb pSRAM 8Mb pSRAM
3 Volt Symbol Parameter Min Max Units Min Max Units Min Max Units
twc Write cycle time 55 ns 70 ns 70 ns
Chip select to
tcw
end of write
Address set up
tas
Time
Address valid to
taw
end of write
UB#, LB# valid
tbw
to end of write
twp Write pulse width 45 ns 55 ns 55 ns
Write recovery
twr
twhz
tdw
tdh
tow
tow
time
Write to output
High-Z
Data to write
time overlap
Data hold from
write time
End write to
output Low-Z
Write high pulse
width
Write
45 ns 55 ns 70 ns
0ns0ns0ns
45 ns 55 ns 70 ns
45 ns 55 ns 70 ns
0ns0ns0ns
25 ns 25 20 ns
40 ns 40 ns 25 ns
0ns0ns0ns
555
xxnsxxnsxxns
tpc Page read cycle x x x
Page address
tpa
access time
twpc Page write cycle x x x
Other
Chip select high
tcp
pulse width
xxx
xxx
August 30, 2004 pSRAM_Type01_12_A1 pSRAM Type 1 99
Page 100
AC Characteristics
(16Mb pSRAM Asynchronous)
3 Volt Symbol Parameter Min Max Units Min Max Units
Read
Advance Information
Asynchronous
Performance Grade -55 -70
Density 16Mb pSRAM 16Mb pSRAM
trc Read cycle time 55 ns 70 ns
Address Access
taa
tco
toe
tba
tlz
tblz
tolz
thz
tbhz
tohz
toh
Time
Chip select to
output
Output enable to
valid output
UB#, LB# Access
time
Chip select to
Low-z output
UB#, LB# Enable
to Low-Z output
Output enable to
Low-Z output
Chip enable to
High-Z output
UB#, LB#
disable to High-Z
output
Output disable to
High-Z output
Output hold from
Address Change
5ns5ns
5ns5ns
5ns5ns
025ns025ns
025ns025ns
025ns025ns
10 ns 10 ns
55 ns 70 ns
55 ns 70 ns
30 ns 35 ns
55 ns 70 ns
100 pSRAM Type 1 pSRAM_Type01_12_A1 August 30, 2004
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