Datasheet S6B0796 Datasheet (Samsung)

S6B0796

written permission of LCD Driver IC Team.

240 SEG / COM DRIVER FOR STN LCD

Contents in this document are subject to change without notice. No part of this document may be reproduced
or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express

January, 2000

Ver. 1.0

Prepared by: Gyeong-Nam, Kim

[e-mail]

240 SEG / COM DRIVER FOR STN LCD PRELIMINARY SPEC. VER. 1.0 S6B0796

S6B0796 Specification Revision History

Version Content Date

0.0 l Original June.1999

0.1 l p6, p16 revision August.1999

1.0 l p4 Introduction revision. January. 2000

2

S6B0796 PRELIMINARY SPEC. VER. 1.0 240 SEG / COM DRIVER FOR STN LCD

CONTENTS

INTRODUCTION ..................................................................................................................................................4

FEATURES..........................................................................................................................................................4

BLOCK DIAGRAM...............................................................................................................................................5

PAD CONFIGURATION (TBD).............................................................................................................................6

PAD CENTER COORDINATES ............................................................................................................................7

PIN DESCRIPTION ..............................................................................................................................................9

FUNCTIONAL DESCRIPTION............................................................................................................................ 10

BLOCK FUNCTION.....................................................................................................................................10

PIN FUNCTION...........................................................................................................................................11

FUNCTIONAL OPERATIONS......................................................................................................................15

SPECIFICATIONS..............................................................................................................................................18

ABSOLUTE MAXIMUM RATINGS...............................................................................................................18

RECOMMENDED OPERATING CONDITIONS ...........................................................................................18

DC CHARACTERISTICS.............................................................................................................................19

AC CHARACTERISTICS.............................................................................................................................21

PRECAUTION....................................................................................................................................................28

CONNECTION EXAMPLES OF PLURAL SEGMENT DRIVERS........................................................................29

TIMING CHART OF 4-DEVICE CASECADE CONNECTION OF SEGMENT DRIVERS......................................30

CONNECTION EXAMPLES OF PLURAL COMMON DRIVERS.........................................................................31

3

240 SEG / COM DRIVER FOR STN LCD PRELIMINARY SPEC. VER. 1.0 S6B0796

INTRODUCTION

The S6B0796 is a 240-outputs segment/common driver LSI for graphic dot-matrix liquid
crystal display systems. It is fabricated by low power CMOS high voltage process technology.
This device consists of 240-bits bi-directional shift register, 240-bits data latch and 240-bits
driver. In case of segment mode, the data input is selected 4bit parallel input mode and 8bit
parallel input mode by a mode (MD) pin. In case of common mode, data input/output pins are
bi-directional, four data shift directions are pin-selectable.

FEATURES

Both Segment Mode and Common Mode

- Supply voltage for LC driver: +15.0 to +32.0V

- Number of LC driver outputs: 240

- Low output impedance

- Low power consumption

- Supply voltage for the logic system: +2.4V to +5.5V

- CMOS silicon gate process (P-type Silicon Substrate)

- Package: 268-pin TCP (Tape Carrier Package) or Gold bumped chip

Segment Mode

- Shift clock frequency: 20MHz (Max) (Vdd=+5V±10%)
12MHz (Max) (Vdd=+2.4V to +4.5V)

- Adopts a data bus system

- 4- / 8-bit parallel input modes are selectable with a mode (MD) pin

- Automatic transfer function of an enable signal

- Automatic counting function which, in the chip select, causes the internal clock to be stopped

by automatically counting 240 of input data

- Line latch circuit reset function when DISPOFFB active

Common Mode

- Shift clock frequency: 4.0MHz (Max) (vdd=+2.4V to +5.5V)

- Built-in 240-bits bi-directional shift register (divisible into 120-bits ×2)

- Available in a single mode (240-bits shift register)

or in a dual mode (120-bits shift register ×2)

- Shift register circuit reset function when DISPOFFB active

4

S6B0796 PRELIMINARY SPEC. VER. 1.0 240 SEG / COM DRIVER FOR STN LCD

BLOCK DIAGRAM

FR

260

DISPOFFB

EIO1

EIO2

LP

XCK

257

259

247

258

256

VORV

12R

V43R V5L

268 267 266 265

LEVEL

SHIFTER

ACTIVE

CONTROL

CONTROL

LOGIC

Y240Y239Y1 Y2

1 2 240239

240 BITS 4-LEVEL DRIVER

240

240 BITS LEVEL SHIFTER

240

240 BITS LINE LATCH/SHIFTER

REGISTER

16 16

8BITS*2

DATA

LATCH

16

16 16

16

16

16

244

243

242

241

V5L

V43L

V12L

VOL

L/R

MD

S/C

261

262

246

DATA LATCH CONTROL

8

SP CONVERSION & DATA CONTROL

(4 to 8 or 8to 8)

248 249 250 251 252 253 254 255 264245

D I0D I1D

D I3DI4DI5DI6DI

I

2

Figure 1. Block Diagram

7

V

DD

VSS

5

240 SEG / COM DRIVER FOR STN LCD PRELIMINARY SPEC. VER. 1.0 S6B0796

1

240

ð

ð

ð

ð

ð

ð

ð

ð

PAD CONFIGURATION

ррррррррррррррррррррр

241

S6B0796

(TOP VIEW, Pads Up)

- - - - - - - - - -

Y

(0,0)

рррррррррррррррррррр

X

ð ð ð ð ð ð ð ð ð ð ð ð ð ð - - - - - - - - - - ð ð ð ð ð ð ð ð ð ð ð ð

Figure 2. S6B0796 Chip Configuration

Table 1. S6B0796 Pad Dimensions

Item Pad NO.

Chip size - 16200 1100

Pad pitch

1 to 240

241 to 292

Size

X Y

65 (Min.)

260 (Min.)

288 245

ð

Unit

292

289244

1 to 240

Bumped pad size

Bumped pad height 1 to 292 14 (Typ.)

6

241 to 244

289 to 292
245 to 288 58 76

43 108

µm

76 73

S6B0796 PRELIMINARY SPEC. VER. 1.0 240 SEG / COM DRIVER FOR STN LCD

PAD CENTER COORDINATES

Table 2. Pad Center Coordinates

[Unit: µm]

NO NAME X Y NO NAME X Y NO NAME X Y

1 Y1 7767.5 395 51 Y51 4517.5 395 101 Y101 1267.5 395
2 Y2 7702.5 395 52 Y52 4452.5 395 102 Y102 1202.5 395
3 Y3 7637.5 395 53 Y53 4387.5 395 103 Y103 1137.5 395
4 Y4 7572.5 395 54 Y54 4322.5 395 104 Y104 1072.5 395
5 Y5 7507.5 395 55 Y55 4257.5 395 105 Y105 1007.5 395
6 Y6 7442.5 395 56 Y56 4192.5 395 106 Y106 942.5 395
7 Y7 7377.5 395 57 Y57 4127.5 395 107 Y107 877.5 395
8 Y8 7312.5 395 58 Y58 4062.5 395 108 Y108 812.5 395

9 Y9 7247.5 395 59 Y59 3997.5 395 109 Y109 747.5 395
10 Y10 7182.5 395 60 Y60 3932.5 395 110 Y110 682.5 395
11 Y11 7117.5 395 61 Y61 3867.5 395 111 Y111 617.5 395
12 Y12 7052.5 395 62 Y62 3802.5 395 112 Y112 552.5 395
13 Y13 6987.5 395 63 Y63 3737.5 395 113 Y113 487.5 395
14 Y14 6922.5 395 64 Y64 3672.5 395 114 Y114 422.5 395
15 Y15 6857.5 395 65 Y65 3607.5 395 115 Y115 357.5 395
16 Y16 6792.5 395 66 Y66 3542.5 395 116 Y116 292.5 395
17 Y17 6727.5 395 67 Y67 3477.5 395 117 Y117 227.5 395
18 Y18 6662.5 395 68 Y68 3412.5 395 118 Y118 162.5 395
19 Y19 6597.5 395 69 Y69 3347.5 395 119 Y119 97.5 395
20 Y20 6532.5 395 70 Y70 3282.5 395 120 Y120 32.5 395
21 Y21 6467.5 395 71 Y71 3217.5 395 121 Y121 -32.5 395
22 Y22 6402.5 395 72 Y72 3152.5 395 122 Y122 -97.5 395
23 Y23 6337.5 395 73 Y73 3087.5 395 123 Y123 -162.5 395
24 Y24 6272.5 395 74 Y74 3022.5 395 124 Y124 -227.5 395
25 Y25 6207.5 395 75 Y75 2957.5 395 125 Y125 -292.5 395
26 Y26 6142.5 395 76 Y76 2892.5 395 126 Y126 -357.5 395
27 Y27 6077.5 395 77 Y77 2827.5 395 127 Y127 -422.5 395
28 Y28 6012.5 395 78 Y78 2762.5 395 128 Y128 -487.5 395
29 Y29 5947.5 395 79 Y79 2697.5 395 129 Y129 -552.5 395
30 Y30 5882.5 395 80 Y80 2632.5 395 130 Y130 -617.5 395
31 Y31 5817.5 395 81 Y81 2567.5 395 131 Y131 -682.5 395
32 Y32 5752.5 395 82 Y82 2502.5 395 132 Y132 -747.5 395
33 Y33 5687.5 395 83 Y83 2437.5 395 133 Y133 -812.5 395
34 Y34 5622.5 395 84 Y84 2372.5 395 134 Y134 -877.5 395
35 Y35 5557.5 395 85 Y85 2307.5 395 135 Y135 -942.5 395
36 Y36 5492.5 395 86 Y86 2242.5 395 136 Y136 -1007.5 395
37 Y37 5427.5 395 87 Y87 2177.5 395 137 Y137 -1072.5 395
38 Y38 5362.5 395 88 Y88 2112.5 395 138 Y138 -1137.5 395
39 Y39 5297.5 395 89 Y89 2047.5 395 139 Y139 -1202.5 395
40 Y40 5232.5 395 90 Y90 1982.5 395 140 Y140 -1267.5 395
41 Y41 5167.5 395 91 Y91 1917.5 395 141 Y141 -1332.5 395
42 Y42 5102.5 395 92 Y92 1852.5 395 142 Y142 -1397.5 395
43 Y43 5037.5 395 93 Y93 1787.5 395 143 Y143 -1462.5 395
44 Y44 4972.5 395 94 Y94 1722.5 395 144 Y144 -1527.5 395
45 Y45 4907.5 395 95 Y95 1657.5 395 145 Y145 -1592.5 395
46 Y46 4842.5 395 96 Y96 1592.5 395 146 Y146 -1657.5 395
47 Y47 4777.5 395 97 Y97 1527.5 395 147 Y147 -1722.5 395
48 Y48 4712.5 395 98 Y98 1462.5 395 148 Y148 -1787.5 395
49 Y49 4647.5 395 99 Y99 1397.5 395 149 Y149 -1852.5 395
50 Y50 4582.5 395 100 Y100 1332.5 395 150 Y150 -1917.5 395

7

240 SEG / COM DRIVER FOR STN LCD PRELIMINARY SPEC. VER. 1.0 S6B0796

Table 2. Pad Center Coordinates (Continued)

[Unit: µm]

NO NAME X Y NO NAME X Y NO NAME X Y

151 Y151 -1982.5 395 201 Y201 -5232.5 395 251 DUMMY -5900 -419
152 Y152 -2047.5 395 202 Y202 -5297.5 395 252 VDD -5640 -419
153 Y153 -2112.5 395 203 Y203 -5362.5 395 253 VDD -5380 -419
154 Y154 -2177.5 395 204 Y204 -5427.5 395 254 VDD -5120 -419
155 Y155 -2242.5 395 205 Y205 -5492.5 395 255 VDD -4860 -419
156 Y156 -2307.5 395 206 Y206 -5557.5 395 256 VDD -4600 -419
157 Y157 -2372.5 395 207 Y207 -5622.5 395 257 SC -4340 -419
158 Y158 -2437.5 395 208 Y208 -5687.5 395 258 EIO2 -4080 -419
159 Y159 -2502.5 395 209 Y209 -5752.5 395 259 DI0 -3820 -419
160 Y160 -2567.5 395 210 Y210 -5817.5 395 260 DI1 -3560 -419
161 Y161 -2632.5 395 211 Y211 -5882.5 395 261 DI2 -3300 -419
162 Y162 -2697.5 395 212 Y212 -5947.5 395 262 DI3 -3040 -419
163 Y163 -2762.5 395 213 Y213 -6012.5 395 263 DI4 -2780 -419
164 Y164 -2827.5 395 214 Y214 -6077.5 395 264 DI5 -2520 -419
165 Y165 -2892.5 395 215 Y215 -6142.5 395 265 DI6 -2260 -419
166 Y166 -2957.5 395 216 Y216 -6207.5 395 266 DI7 -2000 -419
167 Y167 -3022.5 395 217 Y217 -6272.5 395 267 XCK 1770 -419
168 Y168 -3087.5 395 218 Y218 -6337.5 395 268 DISPOFFB 2030 -419
169 Y169 -3152.5 395 219 Y219 -6402.5 395 269 LP 2290 -419
170 Y170 -3217.5 395 220 Y220 -6467.5 395 270 EIO1 2550 -419
171 Y171 -3282.5 395 221 Y221 -6532.5 395 271 FR 2810 -419
172 Y172 -3347.5 395 222 Y222 -6597.5 395 272 LR 3070 -419
173 Y173 -3412.5 395 223 Y223 -6662.5 395 273 MD 3330 -419
174 Y174 -3477.5 395 224 Y224 -6727.5 395 274 NC 3590 -419
175 Y175 -3542.5 395 225 Y225 -6792.5 395 275 VSS 3850 -419
176 Y176 -3607.5 395 226 Y226 -6857.5 395 276 VSS 4110 -419
177 Y177 -3672.5 395 227 Y227 -6922.5 395 277 VSS 4370 -419
178 Y178 -3737.5 395 228 Y228 -6987.5 395 278 VSS 4630 -419
179 Y179 -3802.5 395 229 Y229 -7052.5 395 279 VSS 4890 -419
180 Y180 -3867.5 395 230 Y230 -7117.5 395 280 VSS 5150 -419
181 Y181 -3932.5 395 231 Y231 -7182.5 395 281 DUMMY 5410 -419
182 Y182 -3997.5 395 232 Y232 -7247.5 395 282 DUMMY 5670 -419
183 Y183 -4062.5 395 233 Y233 -7312.5 395 283 DUMMY 5930 -419
184 Y184 -4127.5 395 234 Y234 -7377.5 395 284 DUMMY 6190 -419
185 Y185 -4192.5 395 235 Y235 -7442.5 395 285 DUMMY 6450 -419
186 Y186 -4257.5 395 236 Y236 -7507.5 395 286 DUMMY 6710 -419
187 Y187 -4322.5 395 237 Y237 -7572.5 395 287 DUMMY 6970 -419
188 Y188 -4387.5 395 238 Y238 -7637.5 395 288 DUMMY 7230 -419
189 Y189 -4452.5 395 239 Y239 -7702.5 395 289 V5R 7969 -348.5
190 Y190 -4517.5 395 240 Y240 -7767.5 395 290 V43R 7969 -127.5
191 Y191 -4582.5 395 241 V0L -7969 344.5 291 V12R 7969 93.5
192 Y192 -4647.5 395 242 V12L -7969 93.5 292 V0R 7969 344.5
193 Y193 -4712.5 395 243 V43L -7969 -127.5
194 Y194 -4777.5 395 244 V5L -7969 -348.5
195 Y195 -4842.5 395 245 DUMMY -7460 -419
196 Y196 -4907.5 395 246 DUMMY -7200 -419
197 Y197 -4972.5 395 247 DUMMY -6940 -419
198 Y198 -5037.5 395 248 DUMMY -6680 -419
199 Y199 -5102.5 395 249 DUMMY -6420 -419
200 Y200 -5167.5 395 250 DUMMY -6160 -419

8

S6B0796 PRELIMINARY SPEC. VER. 1.0 240 SEG / COM DRIVER FOR STN LCD

PIN DESCRIPTION

Pin No. Symbol I/O Description

1 to 240
241, 292
242, 291
243, 290
244, 289

272

252 to

256
257
258

259 to

265
266
267
268
269
270
271

Y1 – Y240 O LC driver output

V0L, V0R - Power supply for LC driver
V12L, V12R - Power supply for LC driver
V43L, V43R - Power supply for LC driver

V5L, V5R - Power supply for LC driver

L/R I Display data shift direction selection

VDD - Power supply for logic system(+2.4 to +5.5V)

S/C I Segment mode/common mode selection

EIO2 I/O Input/output for chip select or data of shift register

DI0 – DI6 I Display data input for segment mode

DI7 I Display data input for segment mode/Dual mode data input

XCK I Display data shift clock input for segment mode

DISPOFFB I Control input for deselect output level

LP I Latch pulse input/shift clock input for shift register

EIO1 I/O Input/output for chip select or data of shift register

FR I AC-converting signal input for LC driver waveform

273

275 to

280

MD I Mode selection input

VSS - Ground(0V)

Table 3 Pin Description

9

240 SEG / COM DRIVER FOR STN LCD PRELIMINARY SPEC. VER. 1.0 S6B0796

FUNCTIONAL DESCRIPTION

BLOCK FUNCTION
. Active Control

In case of segment mode, controls the selection or deselection of the chip. Following a LP
signal, and after the chip select signal is input, a select signal is generated internally until 240
bits of data have been read in. Once data input has been completed, a select signal for
cascade connection is output, and the chip is deselected. In case of common mode, controls
the input/output data of bidirectional pins.

. SP Conversion & Data Control

In case of segment mode, keep input data which are 2 clocks of XCK at 4-bit parallel mode
into latch circuit, or keep input data which are 1 clock of XCK at 8-bits parallel mode into latch
circuit, after that they are put on the internal data bus 8 bits at a time.

. Data Latch Control

In case of segment mode, selects the state of the data latch which reads in the data bus
signals. The shift direction is controlled by the control logic, for every 16 bits of data read in, the
selection signal shifts one bit based on the state of the control circuit.

. Data Latch

In case of segment mode, latches the data on the data bus. The latched state of each LC
driver output pin is controlled by the control logic and the data latch control, 240 bits of data are
read in 30 sets of 8 bits.

. Line Latch / Shift Register

In case of segment mode, all 240 bits which have been read into the data latch are
simultaneously latched on the falling edge of the LP signal, and output to the level shifter block.
In case of common mode, shifts data from the data input pin on the falling edge of the LP
signal.

. Level Shifter

The logic voltage signal is level-shifted to the LC driver voltage level, and output to the driver
block.

. 4-level Driver

Driver the LC driver output pins from the line latch/shift register data, selecting one of 4 levels
(V0, V12, V43, V5) based on the S/C, FR and DISPOFFB signals.

. Control logic

Controls the operation of each block. In case of segment mode, when a LP signal has been
input, all blocks are reset and the control logic waits for the selection signal output from the
active control block. Once the selection signal has been output, operation of the data latch and
data transmission are controlled, 240 bits of data are read in, and the chip is deselected. In
case of common mode, controls the direction of data shift.

10

S6B0796 PRELIMINARY SPEC. VER. 1.0 240 SEG / COM DRIVER FOR STN LCD

PIN FUNCTION
Segment mode

Symbol Function

VDD
VSS

V0R, V0L
V12R , V12L
V43R , V43L

V5R , V5L

DI0 – DI7

XCK

LP

L/R

Logic system power supply pin connects to +2.4 to +5.5V
Ground pin connects to 0 V
Power supply pin for LC driver voltage bias.
. Normally, the bias voltage used is set by a resistor divider.
. Ensure that voltage are set such that VSS ≤ V5 < V43 < V12 < V0.
. To further reduce the difference between the output waveforms of LC driver

output pins Y1 and Y160, externally connect ViR and ViL (I = 0, 12, 43, 5)
Input pin for display data
. In 4-bit parallel input mode, input data into the 4 pins DI0 – DI3.
Connect DI4 – DI7 to VSS or VDD.
. In 8-bit parallel input mode, input data into the 8 pins DI0 – DI7.
Clock input pin for taking display data
. Data is read on the falling edge of the clock pulse.
Latch pulse input pin for display data
. Data is latched on the falling edge of the clock pulse.
Direction selection pin for reading display data
. When set to VSS level “L”, data is read sequentially from Y240 to Y1.

DISPOFFB

. When set to VDD level H”, data is read sequentially from Y1 to Y240.
Control input pin for output deselect level
. The input signal is level-shifted from logic voltage level to LC drive voltage

level, and controls LC drive circuit.
. When set to VSS level “L”, the LC drive output pins (Y1 - Y240) are set to level

V5.
. While set to “L”, the contents of the line latch are reset, but read the display

data in the data latch regardless of condition of DISPOFFB.
When the DISPOFFB function is canceled, the driver outputs deselect level

(V12 or V43), then outputs the contents of the data latch on the next.

Falling edge of the LP. That time, if DISPOFFB removal time can not keep regulation what is
shown AC characteristics (page 21), can not output the reading data correctly.

11

240 SEG / COM DRIVER FOR STN LCD PRELIMINARY SPEC. VER. 1.0 S6B0796

AC signal input for LC driving waveform
. The input signal is level-shifted from logic voltage level to LC drive voltage
level, and controls LC drive circuit.

FR

. Normally, inputs a frame inversion signal.
. The LC driver output pin’s output voltage level can be set using the line
latch output signal and the FR signal.
Table of truth values is shown in table 4.
Mode selection pin
. When set to VSS level “L”, 8-bit parallel input mode is set.

MD

. When set to VDD level “H”, 4-bit parallel input mode is set.
. The relationship between the display data and driver output pins is shown
in table 5.

S/C

EIO1
EIO2

Y1 – Y240

Segment mode/common mode selection pin
. When set to VDD level ‘H”, segment mode is set.
Input / output pin for chip selection
. When L/R input is at VSS level ‘L”, EIO1 is set for output, and EIO2 is set for
input.
. When L/R input is at VDD level ‘H”, EIO1 is set for input, and EIO2 is set for
output.
. During output. set to “H” while LP*XCLKB is ‘H” and after 240-bits of data
have been read, set to “L” for one cycle (from falling edge to falling edge of
XCK), after which it returns to “H”.
. During input, after the LP signal is input, the chip is selected while EI is set
to “L”. After 240-bits of data have been read, the chip is deselected.
LC driver output pins
. Corresponding directly to each bit of the data latch, one level(V0, V12, V43,
or V5) is selected and output.
Table of truth values is shown in table 4.

12

S6B0796 PRELIMINARY SPEC. VER. 1.0 240 SEG / COM DRIVER FOR STN LCD

Common Mode

Symbol Function

VDD
VSS

V0R, V0L
V12R , V12L
V43R , V43L

V5R , V5L

EIO1

EIO2

Logic system power supply pin connects to +2.4 to +5.5V
Ground pin connects to 0 V
Power supply pin for LC driver voltage bias.
. Normally, the bias voltage used is set by a resistor divider.
. Ensure that voltage are set such that VSS<V43<V12<V0.
. To further reduce the difference between the output waveforms of LC driver
output pins Y1 and Y240, externally connect ViR and ViL(i=0, 12, 43, 5)
Bidirectional shift register shift data input/output pin
. Output pin when L/R is at VSS level “L”, input pin when L/R is at VDD level
“H”.
. When EIO1 is used as input pin, it will be pull-down.
. When EIO1 is used as output pin, it won’t be pull-down.
Bidirectional shift register shift data input/output pin
. Input pin when L/R is at VSS level “L”, output pin when L/R is at VDD level
“H”.
. When EIO2 is used as input pin, it will be pull-down.
. When EIO2 is used as output pin, it won’t be pull-down.

LP

L/R

Bidirectional shift register shift clock pulse input pin
. Data is shifted on the falling edge of the clock pulse.
Bidirectional shift register shift direction selection pin
. Data is shifted from Y240 to Y1 when set to VSS to level “L”, and data is

shifted from Y1 to Y240 when set to VDD level “H”.

13

240 SEG / COM DRIVER FOR STN LCD PRELIMINARY SPEC. VER. 1.0 S6B0796

Control input pin for output deselect level
. The input signal is level-shifted from logic voltage level to LC drive voltage
level, and controls LC drive circuit.
. When set to VSS level “L”, the LC drive output pins(Y1-Y240) are set to level

DISPOFFB

V5.
. While set to “L”, the contents of the shift resister are reset not reading data.
When the DISPOFFB function is canceled, the driver outputs deselect
Level(V12 or V43), and the shift data is reading on the falling edge of the LP.
That time, if DISPOFFB removal time can not keep regulation what is
shown AC characteristics (page 26), the shift data is not reading correctly.
AC signal input for LC driving waveform
. The input signal is level-shifted from logic voltage level to LC drive voltage
level, and controls LC drive circuit.

FR

. Normally, input a frame inversion signal.
. The LC driver output pin’s output voltage level can be set using the shift
register output signal and the FR signal.
Table of truth values is shown in table 4.
Mode selection pin

MD

. When set to VSS level “L”, Single mode operation is selected, when set to
VDD level “H”, Dual mode operation is selected.
Dual Mode data input pin
. According to the data shift direction of the data shift register, data can be

DI7

input starting from the 121st bit.
When the chip is used as Dual mode, DI7 will be pull-down.
When the chip is used as Single mode, DI7 won’t be pull-down.

S/C

DI0 – DI6

XCK

Segment mode/common mode selection pin
. When set to VSS level ‘L”, common mode is set.
Not used
. Connect DI0 – DI6 to VSS or VDD. Avoiding floating.
Not used
. XCK is pull-down in common mode, so connect to VSS or open.
LC driver output pins

Y1 – Y240

. Corresponding directly to each bit of the shift register, one level(V0, V12,
V43, or V5) is selected and output. Table of truth values is shown in table 4.

14

S6B0796 PRELIMINARY SPEC. VER. 1.0 240 SEG / COM DRIVER FOR STN LCD

FUNCTIONAL OPERATIONS
TRUTH TABLE (Table 4)

Segment Mode

FR Latch data DISPOFFB Driver output voltage level (Y1 – Y240)

L L H V43

L H H V5
H L H V12
H H H V0

x x L V5

Here, VSS≤V5<V43<V12<V0, H : VDD (+2.4V to +5.5V), L : VSS(0V), x : Don’t care

Common Mode

FR Latch data DISPOFFB Driver output voltage level (Y1 – Y240)

L L H V43

L H H V0
H L H V12
H H H V5

x x L V5

Here, VSS≤V5<V43<V12<V0, H : VDD (+2.4V to +5.5V), L : VSS(0V), x : Don’t care

NOTE : There are two kinds of power supply (logic level voltage, LC drive voltage) for LCD
driver, please supply regular voltage which assigned by specification for each power
pin. That time ‘Don’t care” should be fixed to ‘H” or “L “, avoiding floating.

15

240 SEG / COM DRIVER FOR STN LCD PRELIMINARY SPEC. VER. 1.0 S6B0796

RELATIONSHIP BETWEEN THE DISPLAY DATA AND DRIVER OUTPUT PINS (Table 5)

Segment Mode
(a) 4-bit Parallel Mode

MD L/R EIO1 EIO2

H L Output Input

H H Input Output

(a) 8-bit Parallel Mode

MD L/R EIO1 EIO2

L L Output Input

L H Input Output

Data

Input

DI0 Y237 Y233 Y229 .. Y9 Y5 Y1
DI1 Y238 Y234 Y230 .. Y10 Y6 Y2
DI2 Y239 Y235 Y231 .. Y11 Y7 Y3
DI3 Y240 Y236 Y232 .. Y12 Y8 Y4

DI0 Y4 Y8 Y12 .. Y232 Y236 Y240
DI1 Y3 Y7 Y11 .. Y231 Y235 Y239
DI2 Y2 Y6 Y10 .. Y230 Y234 Y238
DI3 Y1 Y5 Y9 .. Y229 Y233 Y237

Data

Input

DI0 Y233 Y225 Y217 .. Y17 Y9 Y1
DI1 Y234 Y226 Y218 .. Y18 Y10 Y2
DI2 Y235 Y227 Y219 .. Y19 Y11 Y3
DI3 Y236 Y228 Y220 .. Y20 Y12 Y4
DI4 Y237 Y229 Y221 .. Y21 Y13 Y5
DI5 Y238 Y230 Y222 .. Y22 Y14 Y6
DI6 Y239 Y231 Y223 .. Y23 Y15 Y7
DI7 Y240 Y232 Y224 .. Y24 Y16 Y8
DI0 Y8 Y16 Y24 .. Y224 Y232 Y240
DI1 Y7 Y15 Y23 .. Y223 Y231 Y239
DI2 Y6 Y14 Y22 .. Y222 Y230 Y238
DI3 Y5 Y13 Y21 .. Y221 Y229 Y237
DI4 Y4 Y12 Y20 .. Y220 Y228 Y236
DI5 Y3 Y11 Y19 .. Y219 Y227 Y235
DI6 Y2 Y10 Y18 .. Y218 Y226 Y234
DI7 Y1 Y9 Y17 .. Y217 Y225 Y233

1st 2nd 3rd .. 58th 59th 60th

1st 2nd 3rd .. 28th 29th 30th

Figure of clock

Figure of clock

16

S6B0796 PRELIMINARY SPEC. VER. 1.0 240 SEG / COM DRIVER FOR STN LCD

Table 5 (Continued)

Common Mode

MD L/R Data transfer direction EIO1 EIO2 DI7

L

(Single)

L(shift to left)

H(shift to right)

Y240 → Y1
Y1 → Y240

Output Input X

Input Output X

H

(Dual)

Here, L : VSS(0V), H : VDD(+2.4V to +5.5V), X : Don’t care
NOTE: “Don’t care” should be fixed to “H” or “L”, avoid floating.

L(shift to left)

H(shift to right)

Y240 → Y121

Y120 → Y1
Y1 → Y120

Y121 → Y240

Output Input Input

Input Output Input

17

240 SEG / COM DRIVER FOR STN LCD PRELIMINARY SPEC. VER. 1.0 S6B0796

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

Table 6. Absolute Maximum Ratings

Parameter Symbol Conditions Applicable pins Ratings Unit

Ta=25 °C

Supply voltage (1)

Supply voltage (2)

Input voltage

Storage temperature

VDD

V0 V0L, V0R -0.3 to +35 V
V12 V12L, V12R -0.3 to V0+0.3 V
V43 V43L, V43R -0.3 to V0+0.3 V

V5 V5L, V5R -0.3 to V0+0.3 V

V1

TSTG -45 to 125

Referenced to
VSS(0V)

VDD -0.3 to +6.5 V

DI0 –DI7, XCK, LP, L/R,

MD, S/C, EIO1, EIO2,

DISPOFFB

-0.3 to VDD+0.3 V

°C

RECOMMENDED OPERATING CONDITIONS

Table 7. Recommended Operating Conditions

Parameter Symbol Conditions Applicable pins Min. Typ. Max. Unit

Referenced to

Supply voltage (1)

Supply voltage (2)

Operating temperature

NOTE: Ensure that voltage are set such that VSS≤V5<V43<V12<V0

VDD

V0 V0L, V0R +15 +32 V

TOPR -20 +85

VSS(0V)

VDD +2.4 +5.5 V

°C

18

S6B0796 PRELIMINARY SPEC. VER. 1.0 240 SEG / COM DRIVER FOR STN LCD

DC CHARACTERISTICS

DC CHARACTERISTICS(Table 8)
Segment Mode

(VSS=V5=0V, VDD=+2.4 to 5.5V, V0=+15 to +32V, Ta=-20~85°C)

Parameter Symbol Conditions Applicable pins Min. Typ. Max. Unit

Input voltage

Output voltage

Input leakage

current

VIH 0.8VDD V

VIL

VOH IOH=-0.4mA VDD-0.4 V

VOL IOL=+0.4mA

ILIH VI=VDD +10 uA

ILIL VI=VSS

DI0 -DI7, XCK, LP, L/R,

FR, MD, S/C,EIO1, EIO2,

DISPOFFB

EIO1, EIO2

DI0 -DI7, XCK, LP, L/R,

FR, MD, S/C,EIO1, EIO2,

DISPOFFB

0.2VDD V

+0.4 V

-10 uA

Output

resistance

Stand-by

current

RON

|∆VON|
=0.5V

ISTB *1 VSS 75.0 uA

V0=+30V 1.5 2.0 kΩ

Y1- Y240

V0=+20V

Consumed

current(1)

IDD1 *2 VDD 2.0 mA

(Deselection)

Consumed

current(2)

IDD2 *3 VDD 12.0 mA

(Selection)
Consumed

current

I0 *4 V0 1.5 mA

NOTES: *1 VDD=+5V, V0=+32V, VI=VSS

*2 VDD=+5V, V0=+32V, fXCK=20MHz, No-load, EI=VDD
The input data is turned over by data taking clock (4-bit parallel input mode)

*3 VDD=+5V, V0=+32V, fXCK=20MHz, No-load, EI=VSS

The input data is turned over by data taking clock (4-bit parallel input mode)

*4 VDD=+5V, V0=+32V, fXCK=20MHz, fLP=25.6 kHz, fFR=80Hz, No-load

The input data is turned over by data taking clock (4-bit parallel input mode)

2.0 2.5

19

240 SEG / COM DRIVER FOR STN LCD PRELIMINARY SPEC. VER. 1.0 S6B0796

Table 8 (Continued)

Common Mode

(VSS=V5=0V, VDD=+2.4 to 5.5V, V0=+15 to +32V, Ta=-20~85°C)

Parameter Symbol Conditions Applicable pins Min. Typ. Max. Unit

VIH 0.8VDD V

Input voltage

VIL

VOH IOH=-0.4mA VDD-0.4 V

Output voltage

VOL IOL=+0.4mA

ILIH VI=VDD

Input leakage

current

ILIL VI=VSS

DI0 -DI7, XCK, LP, L/R,

FR, MD, S/C,EIO1, EIO2,

DISPOFFB

EIO1, EIO2

DI0 –DI6, LP, L/R, FR,

MD, S/C, DISPOFFB

DI0 -DI7, XCK, LP, L/R,

FR, MD, S/C,EIO1, EIO2,

DISPOFFB

0.2VDD V

+0.4 V

+10 uA

-10 uA

Output

resistance

Input pull-

down current

Stand-by

current

Consumed

current(1)

Consumed

current(2)

RON

|∆ON|

=0.5V

IPD VI=VDD XCK, EIO1, EIO2, DI7 100.0 uA

ISTB *1 VSS 75.0 uA

IDD *2 VDD 120.0 uA

I0 *2 V0 240.0 uA

V0=+30V 1.5 2.0
V0=+20V

NOTES: *1 VDD=+5V, V0=+32V, VI=VSS

*2 VDD=+5V, V0=+32V, fLP=25.6kHz, fFR=80Hz
case of 1/320 duty operation, No-load

Y1 – Y240

kΩ

2.0 2.5

20

S6B0796 PRELIMINARY SPEC. VER. 1.0 240 SEG / COM DRIVER FOR STN LCD

AC CHARACTERISTICS

SEGMENT MODE AC CHARACTERISTICS(Table 9)
Segment Mode 1

(VSS=V5=0V, VDD=+4.5 to +5.5V, V0=+15 to +32V, Ta=-20~85°C)

Parameter Symbol Conditions Min. Typ. Max. Unit

Shift clock period *1 TWCK

Shift clock “H” pulse width TWCKH 15 ns

Shift clock “L” pulse width TWCKL 15 ns

Data setup time TDS 10 ns

Data hold time TDH 12 ns

Latch pulse “H” pulse width TWLPH 15 ns

Shift clock rise to latch pulse rise time TLD 0 ns

Shift clock fall to latch pulse fall time TSL 30 ns

Latch pulse rise to shift clock rise time TLS 25 ns

Latch pulse fall to shift clock fall time TLH 25 ns

Input signal rise time *2 TR 50 ns

Input signal fall time *2 TF 50 ns

Enable setup time TS 10 ns

DISPOFFB removal time TSD 100 ns

DISPOFFB “L” pulse width TWDL 1.2 us

Output delay time (1) TD CL=15pF 30 ns
Output delay time (2)
Output delay time (3) TPD3 CL=15pF 1.2 us

NOTES: *1 Take the cascade connection into consideration.

TPD1,

TPD2

TR, TF≤10 ns

CL=15pF 1.2 us

50 ns

*2 (TWCK – TWCKH – TWCKL) / 2 is maximum in the case of high speed operation.

21

240 SEG / COM DRIVER FOR STN LCD PRELIMINARY SPEC. VER. 1.0 S6B0796

Table 9 (Continued)

Segment Mode 2

(VSS=V5=0V, VDD=+3.0V to +4.5V, V0=+15 to +32V, Ta=-20~85°C)

Parameter Symbol Conditions Min. Typ. Max. Unit

Shift clock period *1 TWCK

Shift clock “H” pulse width TWCKH 23 ns

Shift clock “L” pulse width TWCKL 23 ns

Data setup time TDS 15 ns

Data hold time TDH 23 ns

Latch pulse “H” pulse width TWLPH 30 ns

Shift clock rise to latch pulse rise time TLD 0 ns

Shift clock fall to latch pulse fall time TSL 50 ns

Latch pulse rise to shift clock rise time TLS 30 ns

Latch pulse fall to shift clock fall time TLH 30 ns

Input signal rise time *2 TR 50 ns

Input signal fall time *2 TF 50 ns

Enable setup time TS 15 ns

DISPOFFB removal time TSD 100 ns

DISPOFFB “L” pulse width TWDL 1.2 us

Output delay time (1) TD CL=15pF 41 ns
Output delay time (2)
Output delay time (3) TPD3 CL=15pF 1.2 us

NOTES: *1 Take the cascade connection into consideration.

TPD1,

TPD2

TR, TF≤10 ns

CL=15pF 1.2 us

66 ns

*2 (TWCK – TWCKH – TWCKL) / 2 is maximum in the case of high speed operation.

22

S6B0796 PRELIMINARY SPEC. VER. 1.0 240 SEG / COM DRIVER FOR STN LCD

Table 9 (Continued)

Segment Mode 3

(VSS=V5=0V, VDD=+2.4V to +3.0, V0=+15 to +32V, Ta=-20~85°C)

Parameter Symbol Conditions Min. Typ. Max. Unit

Shift clock period *1 TWCK

Shift clock “H” pulse width TWCKH 28 ns

Shift clock “L” pulse width TWCKL 28 ns

Data setup time TDS 20 ns

Data hold time TDH 23 ns

Latch pulse “H” pulse width TWLPH 30 ns

Shift clock rise to latch pulse rise time TLD 0 ns

Shift clock fall to latch pulse fall time TSL 65 ns

Latch pulse rise to shift clock rise time TLS 30 ns

Latch pulse fall to shift clock fall time TLH 30 ns

Input signal rise time *2 TR 50 ns

Input signal fall time *2 TF 50 ns

Enable setup time TS 15 ns

DISPOFFB removal time TSD 100 ns

DISPOFFB “L” pulse width TWDL 1.2 us

Output delay time (1) TD CL=15pF 57 ns
Output delay time (2)
Output delay time (3) TPD3 CL=15pF 1.2 us

NOTES: *1 Take the cascade connection into consideration.

TPD1,

TPD2

TR, TF≤10 ns

CL=15pF 1.2 us

82 ns

*2 (TWCK – TWCKH – TWCKL) / 2 is maximum in the case of high speed operation.

23

240 SEG / COM DRIVER FOR STN LCD PRELIMINARY SPEC. VER. 1.0 S6B0796

Timing Characteristics of Segment Mode (Figure 3)

T

WLPH

LP

T

LD

T

SL

LS

T

T

WCKH

T

LH

T

WCKL

XCK

R

T

F

T

T

T

T

WCK

DS

DH

DI0 - DI

DISPOFFB

LP

XCK

EI

7

LAST DATA TOP DATA

T

WDL

T

SD

(*)

1

TS

2

n

TD

24

EO

(*) n : 4 - bit parallel mode 60

8 - bit parallel mode 30

S6B0796 PRELIMINARY SPEC. VER. 1.0 240 SEG / COM DRIVER FOR STN LCD

Figure 3. (Continued)

FR

T

PD1

LP

T

PD2

DISPOFFB

T

PD3

Y1 ~Y

240

[L/R="L"]

25

240 SEG / COM DRIVER FOR STN LCD PRELIMINARY SPEC. VER. 1.0 S6B0796

COMMON MODE AC CHARACTERISTICS (Table 10)
Common Mode

(VSS=V5=0V, VDD=+2.4V to +4.5V, V0=+15 to +32V, Ta=-20~85°C)

Parameter Symbol Condition Min. Typ. Max. Unit

Shift clock period

Shift clock “H” pulse width

Data setup time

Data hold time

Input signal rise time

Input signal fall time

DISPOFFB removal time

DISPOFFB ‘L” pulse width

Output delay time (1)
Output delay time (2)
Output delay time (3)

TWLP

TR, TF≤20ns

VDD=+5.0V±10%

250 ns

15 ns

TWLPH

VDD=+2.5V~+4.5V 30 ns

TSU 30 ns

TH 50 ns
TR 50 ns
TF 50 ns

TSD 100 ns

TWDL 1.2 us

TDL CL=15pF 200 ns

TPD1,TPD2 CL=15pF 1.2 us

TPD3 CL=15pF 1.2 us

Timing Characteristics of Common Mode (Figure 4)

LP

T

EIO

R

2

T

WLPH

T

SU

T
T

(DI7)

EIO

1

DISPOFFB

T

WLP

F
H

T

DL

T

T

WDL

SD

26

S6B0796 PRELIMINARY SPEC. VER. 1.0 240 SEG / COM DRIVER FOR STN LCD

Figure 4. (Continued)

FR

TPD1

LP

TPD2

DISPOFFB

TPD3

Y1~ Y240

[L/R="L"]

27

240 SEG / COM DRIVER FOR STN LCD PRELIMINARY SPEC. VER. 1.0 S6B0796

PRECAUTION

. PRECAUTION WHEN CONNECTING OR DISCONNECTING THE POWER

This LSI has a high-voltage LC driver, so it may be permanently damaged by a high current
which may flow if a voltage is supplied to the LC driver power supply while the logic system
power supply is floating. The detail is as follows.

. When connecting the power supply, connect the LC drive power after connecting the logic
system power. Furthermore, when disconnecting the power, disconnect the logic system
power after disconnecting the LC driver power.

. We recommend you connecting the serial resistor (50~100Ω) or fuse to the LC drive power
V0 of the system as a current limiter. And set up the suitable of the resistor in consideration of
LC display grade.

And when connecting the logic power supply, the logic condition of this LSI inside is
insecurity. Therefore connect the LC driver power supply after resetting logic condition of this
LSI inside on DISPOFFB function. After that, cancel the DISPOFFB function after the LC
driver power supply has become stable. Furthermore, when disconnecting the power, set the
LC drive output pins to level V5 on DISPOFFB function. After that, disconnect the logic
system power after disconnecting the LC drive power. When connecting the power supply,
show the following recommend sequence.

V

DD

V

DD

V

SS

V

DD

DISPOFFB

V

SS

V

0

V

0

V

SS

28

Figure 5.

S6B0796 PRELIMINARY SPEC. VER. 1.0 240 SEG / COM DRIVER FOR STN LCD

CONNECTION EXAMPLES OF PLURAL SEGMENT DRIVERS

(a) CASE OF L/R = "L"

XCK

LP

MD

FR

DIO

-

DIO

VSS

VDD

DIO

-

DIO

XCK

top data

Y240

EIO

2

X

LPMDF

C
K

0

7

(b) CASE OF L/R = "H"

0

7

FR

MD

LP

last data

Y1

EIO

1

Y240

EIO

2

L/R

D

D

I

I

­O

O

7

0

R

X
C
K

LPMDF

Y1

EIO

1

Y240

EIO

2

L/R

D

D

I

I

­O

O

7

0

R

X
C
K

LPMDF

Y1

EIO

1

L/R

D

D

I

I

­O

O

7

0

R

8

8

VSS

X
C
K

EIO

Y1

LPMDF

1

X

D

D

R

I

I

­O

O

7

0

LPMDF
C
K

L/R

EIO

EIO

Y240

2

1

Y1

D

D

R

I

I

­O

O

7

0

L/R

EIO

2

Y240

X
C
K

EIO

Y1

LPMDF

1

D

D

R

I

I

­O

O

7

0

L/R

EIO

2

Y240

top data last data

Figure 6.

29

240 SEG / COM DRIVER FOR STN LCD PRELIMINARY SPEC. VER. 1.0 S6B0796

TIMING CHART OF 4-DEVICE CASECADE CONNECTION OF SEGMENT
DRIVERS

FR

LP

XCK

TOP DATA

DI0-DI7

n 1 2 n 1 2 n 1 2 n 1 2 n 1 2

device A device B

EI

(device A)

EO

(device A)

EO

(device B)

EO

(device C)

(*)

device C

LAST DATA

device D

Low

30

(*) n:4-bit parallel mode 60

8-bit parallel mode 30

Figure 7.

S6B0796 PRELIMINARY SPEC. VER. 1.0 240 SEG / COM DRIVER FOR STN LCD

CONNECTION EXAMPLES OF PLURAL COMMON DRIVERS

(a) SINGLE MODE(SHIFTING TOWARD LEFT)

DI

VSS

(VDD)

LP

VSS

FR

DISPOFFB

VSS

VDD

first

Y240

EIO

2

D
I

7

LPMDF

Y1

EIO

1

L/R

D

I
S
P
O
F
F
B

R

Y240

EIO

2

D
I

7

LPMDF

(b) SINGLE MODE(SHIFTING TOWARD RIGHT)

last

Y1

EIO

1

L/R

D

I
S
P
O
F
F
B

R

Y240

EIO

2

D
I

7

LPMDF

Y1

EIO

1

L/R

D

I
S
P
O
F
F
B

R

DISPOFFB

FR

VSS

LP

VSS

(VDD)

DI

D
I

7

EIO

1

Y1

first

LPMDF

D

I

R

S
P
O
F
F
B

L/R

EIO

2

Y240

D

7

EIO

Y1

LPMDF

I

1

D

I

R

S
P
O
F
F
B

L/R

EIO

2

Y240

EIO

Y1

D
I

7

1

LPMDF

D

I

R

S
P
O
F
F
B

L/R

EIO

2

Y240

last

Figure 8.

31

240 SEG / COM DRIVER FOR STN LCD PRELIMINARY SPEC. VER. 1.0 S6B0796

(c) DUAL MODE(SHIFTING TOWARD LEFT)

DI1

VSS

(VDD)

LP

VSS

FR

DISPOFFB

VDD

VSS

DI2

first1

Y240

EIO

2

D
I

7

LPMDF

Y1

EIO

1

L/R

D

I
S
P
O
F
F
B

R

last1 first2 last2

EIO

D
I

7

Y121 Y120

2

LPMDF

R

Y240

(d) DUAL MODE(SHIFTING TOWARD RIGHT)

D

I
S
P
O
F
F
B

Y1

EIO

L/R

Y240

1

EIO

2

D

LPMDF

I

7

Y1

EIO

1

L/R

D
I
S
P
O
F
F
B

R

DI2
VDD
VDD

DISPOFFB

FR

VSS

LP

VSS

(VDD)

DI1

D

I

7

EIO

1

Y1

first1

LPMDF

D

I

R

S
P
O
F
F
B

L/R

EIO

2

Y240

EIO

Y1

D
I

7

LPMDF

1

Y120

Y121

D

I

R

S
P
O
F
F
B

L/R

EIO

2

Y240

EIO

Y1

D
I

7

LPMDF

1

D

I

R

S
P
O
F
F
B

L/R

EIO

2

Y240

last2

last1 first2

Figure 9.

32