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DDU8C |
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5-TAP, HCMOS-INTERFACED |
data |
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FIXED DELAY LINE |
delay |
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(SERIES DDU8C) |
devices, inc. |
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FEATURES
∙Five equally spaced outputs
∙Fits standard 8-pin DIP socket
∙Low profile
∙Auto-insertable
∙Input & outputs fully CMOS interfaced & buffered
∙10 T2L fan-out capability
PACKAGES
IN |
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VDD |
IN |
1 |
14 |
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VDD |
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1 |
8 |
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N/C |
2 |
13 |
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N/C |
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T2 |
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2 |
7 |
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T1 |
N/C |
3 |
12 |
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T1 |
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T2 |
4 |
11 |
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N/C |
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T4 |
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6 |
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T3 |
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3 |
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N/C |
5 |
10 |
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T3 |
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GND |
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4 |
5 |
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T5 |
T4 |
6 |
9 |
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N/C |
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GND |
7 |
8 |
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T5 |
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DDU8C-xx |
DIP |
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Military SMD |
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DDU8C-xxA1 Gull-Wing |
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DDU8C-xxMD1 |
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DDU8C-xxB1 J-Lead |
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DDU8C-xxMD4 |
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DDU8C-xxM |
Military DIP |
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FUNCTIONAL DESCRIPTION
The DDU8C-series device is a 5-tap digitally buffered delay line. The signal input (IN) is reproduced at the outputs (T1-T5), shifted in time by an amount determined by the device dash number (See Table). The total delay of the line is measured from IN to T5. The nominal tap-to-tap delay increment is given by one-fifth of the total delay.
PIN DESCRIPTIONS
IN |
Signal Input |
T1-T5 |
Tap Outputs |
VDD |
+5 Volts |
GND |
Ground |
SERIES SPECIFICATIONS
∙Minimum input pulse width: 40% of total delay
∙Output rise time: 8ns typical
∙Supply voltage: 5VDC ± 5%
∙Supply current: ICCL = 40μa typical
ICCH = 10ma typical
∙Operating temperature: 0° to 70° C
∙Temp. coefficient of total delay: 300 PPM/°C
DASH NUMBER SPECIFICATIONS
Part |
Total |
Delay Per |
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Number |
Delay (ns) |
Tap (ns) |
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DDU8C-5050 |
50 |
± 2.5 |
10.0 ± 3.0 |
DDU8C-5060 |
60 |
± 3.0 |
12.0 ± 3.0 |
DDU8C-5075 |
75 |
± 4.0 |
15.0 ± 3.0 |
DDU8C-5100 |
100 ± 5.0 |
20.0 ± 3.0 |
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DDU8C-5125 |
125 ± 6.5 |
25.0 ± 3.0 |
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DDU8C-5150 |
150 ± 7.5 |
30.0 ± 3.0 |
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DDU8C-5175 |
175 ± 8.0 |
35.0 ± 4.0 |
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DDU8C-5200 |
200 |
± 10.0 |
40.0 ± 4.0 |
DDU8C-5250 |
250 |
± 12.5 |
50.0 ± 5.0 |
NOTE: Any dash number between 5004 and 5250 not shown is also available.
20% 20% 20% 20% 20%
VDD IN |
T1 |
T2 |
T3 |
T4 |
T5 GND |
DDU8C Functional diagram
©1997 Data Delay Devices
Doc #97013 |
DATA DELAY DEVICES, INC. |
1 |
1/28/97 |
3 Mt. Prospect Ave. Clifton, NJ 07013 |
DDU8C
APPLICATION NOTES
HIGH FREQUENCY RESPONSE
The DDU8C tolerances are guaranteed for input pulse widths and periods greater than those specified in the test conditions. Although the device will function properly for pulse widths as small as 40% of the total delay and periods as small as 80% of the total delay (for a symmetric input), the delays may deviate from their values at low frequency. However, for a given input condition, the deviation will be repeatable from pulse to pulse. Contact technical support at Data
Delay Devices if your application requires device testing at a specific input condition.
POWER SUPPLY BYPASSING
The DDU8C relies on a stable power supply to produce repeatable delays within the stated tolerances. A 0.1uf capacitor from VDD to GND, located as close as possible to the VDD pin, is recommended. A wide VDD trace and a clean ground plane should be used.
DEVICE SPECIFICATIONS
TABLE 1: ABSOLUTE MAXIMUM RATINGS
PARAMETER |
SYMBOL |
MIN |
MAX |
UNITS |
NOTES |
DC Supply Voltage |
VDD |
-0.3 |
7.0 |
V |
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Input Pin Voltage |
VIN |
-0.3 |
VDD+0.3 |
V |
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Storage Temperature |
TSTRG |
-55 |
150 |
C |
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Lead Temperature |
TLEAD |
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300 |
C |
10 sec |
TABLE 2: DC ELECTRICAL CHARACTERISTICS
(0C to 70C, 4.75V to 5.25V)
PARAMETER |
SYMBOL |
MIN |
TYP |
MAX |
UNITS |
NOTES |
High Level Output Voltage |
VOH |
3.98 |
4.4 |
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V |
VDD = 5.0, IOH = MAX |
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VIH = MIN, VIL = MAX |
Low Level Output Voltage |
VOL |
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0.15 |
0.26 |
V |
VDD = 5.0, IOL = MAX |
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VIH = MIN, VIL = MAX |
High Level Output Current |
IOH |
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-4.0 |
mA |
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Low Level Output Current |
IOL |
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4.0 |
mA |
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High Level Input Voltage |
VIH |
3.15 |
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V |
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Low Level Input Voltage |
VIL |
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1.35 |
V |
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Input Current |
IIH |
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0.10 |
μA |
VDD = 5.0 |
Doc #97013 |
DATA DELAY DEVICES, INC. |
2 |
1/28/97 |
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com |