DADD 3D7502Z-50, 3D7502Z-5, 3D7502M-20, 3D7502M-10, 3D7502H-50 Datasheet

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3D7502
Doc #97032 DATA DELAY DEVICES, INC. 1
5/19/97 3 Mt. Prospect Ave. Clifton, NJ 07013
MONOLITHIC MANCHESTER DECODER (SERIES 3D7502)
FEATURES
TTL/CMOS compatible inputs and outputs
Vapor phase, IR and wave solderable
Auto-insertable (DIP pkg.)
Low ground bounce noise
Maximum data rate: 50 MBaud
Data rate range: ±15%
FUNCTIONAL DESCRIPTION
The 3D7502 product family consists of monolithic CMOS Manchester Decoders. The unit accepts at the RX input a bi-phase-level, embedded-clock signal. In this encoding mode, a logic one is represented by a high-to-low transition within the bit cell, while a logic zero is represented by a low-to-high transition. The recovered clock and data signals are presented on CLK and DATB, respectively, with the data signal inverted. The operating baud rate (in MBaud) is specified by the dash number. The input baud rate may vary by as much as ±15% from the nominal device baud rate without compromising the integrity of the information received.
Because the 3D7502 is not PLL-based, it does not require a long preamble in order to lock onto the received signal. Rather, the device requires at most one bit cell before the data presented at the output is valid. This is extremely useful in cases where the information arrives in bursts and the input is otherwise turned off.
The all-CMOS 3D7502 integrated circuit has been designed as a reliable, economic alternative to hybrid TTL Manchester Decoders. It is TTL- and CMOS-compatible, capable of driving ten 74LS-type loads. It is offered in standard 8-pin and 14-pin auto-insertable DIPs and space saving surface mount 8-pin and 14­pin SOICs.
TABLE 1: PART NUMBER SPECIFICATIONS
PART BAUD RATE (MBaud)
NUMBER Nominal Minimum Maximum
3D7502-5 5.00 4.25 5.75 3D7502-10 10.00 8.50 11.50 3D7502-20 20.00 17.00 23.00 3D7502-25 25.00 21.25 28.75 3D7502-30 30.00 25.50 34.50 3D7502-40 40.00 34.00 46.00 3D7502-50 50.00 42.50 57.50
NOTES: Any baud rate between 5 and 50 MBaud not shown is also available at no extra cost. 1997 Data Delay Devices
data
delay devices, inc.
3
PACKAGES
8 7 6 5
1 2 3 4
RX
CLK
N/C
GND
VDD N/C N/C DATB
3D7502M-xxx DIP (.300) 3D7502H-xxx Gull Wing (.300) 3D7502Z-xxx SOIC (.150)
14 13 12 11 10
9 8
1 2 3 4 5 6 7
RX N/C N/C
CLK
N/C N/C
GND
VDD N/C N/C N/C N/C N/C DATB
3D7502-xxx DIP (.300) 3D7502G-xxx Gull Wing (.300) 3D7502D-xxx SOIC (.150)
PIN DESCRIPTIONS
RX Signal Input CLK Signal Output (Clock) DATB Signal Output (Data) VCC +5 Volts GND Ground
3D7502
Doc #97032 DATA DELAY DEVICES, INC. 2
5/19/97 Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
APPLICATION NOTES
The 3D7502 Manchester Decoder samples the input at precise pre-selected intervals to retrieve the data and to recover the clock from the received data stream. Its architecture comprises finely tuned delay elements and proprietary circuitry which, in conjunction with other circuits, implement the data decoding and clock recovery function.
INPUT SIGNAL CHARACTERISTICS
Encoded data transmitted from a source arrives at its destination corrupted. Such corruption of the received data manifests itself as jitter and/or pulse width distortion at the input to the device. The instantaneous deviations from nominal Baud Rate and/or Pulse Width (high or low) adversely impact the data extraction and clock recovery function if their published limits are exceeded.
See Table 4, Allowed Baud Rate/Duty Cycle. The 3D7502 Manchester Decoder Data Input is
TTL compatible. The user should assure himself that the 1.5 volt TTL threshold is used
when referring to all timing, especially the input pulse widths.
FREQUENCY (JITTER) ERRORS
The 3D7502 Manchester Decoder, being a self­timed device, is tolerant of frequency modulation (jitter) present in the input data stream, provided that the input data pulse width variations remain within the allowable ranges.
OUTPUT SIGNAL CHARACTERISTICS
The 3D7502 presents at its outputs the decoded data (inverted) and the recovered clock. The decoded data is valid at the rising edge of the
clock.
The clock recovery function operates in two modes dictated by the input data stream bit sequence. When a data bit is succeeded by its inverse, the clock recovery circuit is engaged and forces the clock output low for a time equal to one over twice the baud rate. Otherwise, the input is presented at the clock output unchanged, shifted in time.
When engaged, the clock recovery circuit generates a low-going pulse of fixed width. Therefore, the clock duty cycle is strongly dependent on the baud rate, as this will affect the clock-high duration.
The clock output falling edge is not operated on by the clock recovery circuitry. It, therefore, preserves more accurately the clock frequency information embedded in the transmitted data. Therefore, it can be used, if it is desired, to retrieve clock frequency information.
POWER SUPPLY AND TEMPERATURE CONSIDERATIONS
CMOS integrated circuitry is strongly dependent on power supply and temperature. The monolithic 3D7502 Manchester Decoder utilizes novel and innovative compensation circuitry to minimize timing variations induced by fluctuations in power supply and/or temperature.
CLOCK (CLK)
RECEIVED (RX)
Figure 1: Timing Diagram
t
C
DECODED
1 0 1 1 0 0 1
ENCODED
1 0 1 1 0 0 10
DATA (DATB)
t
CL
t
CWL
t
CD
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