DADD DDU8C-5150M, DDU8C-5150B1, DDU8C-5150A1, DDU8C-5150, DDU8C-5125MD4 Datasheet

DDU8C

Doc #97013 DATA DELAY DEVICES, INC. 1

1/28/97 3 Mt. Prospect Ave. Clifton, NJ 07013

5-TAP, HCMOS-INTERFACED
FIXED DELAY LINE
(SERIES DDU8C)

FEATURES PACKAGES

• Five equally spaced outputs

• Fits standard 8-pin DIP socket

• Low profile

• Auto-insertable

• Input & outputs fully CMOS interfaced & buffered

• 10 T2L fan-out capability

FUNCTIONAL DESCRIPTION

The DDU8C-series device is a 5-tap digitally buffered delay line. The
signal input (IN) is reproduced at the outputs (T1-T5), shifted in time by an
amount determined by the device dash number (See Table). The total
delay of the line is measured from IN to T5. The nominal tap-to-tap delay
increment is given by one-fifth of the total delay.

SERIES SPECIFICATIONS

• Minimum input pulse width: 40% of total delay

• Output rise time: 8ns typical

• Supply voltage: 5VDC ± 5%

• Supply current: I

CCL

= 40µa typical

I

CCH

= 10ma typical

• Operating temperature: 0° to 70° C

• Temp. coefficient of total delay: 300 PPM/°C

20% 20% 20% 20% 20%

VDD GNDIN T1 T2 T3 T4 T5

DDU8C Functional diagram

1997 Data Delay Devices

data

delay
devices, inc.



3

1

2
3
4
5
6
7

14

13
12
11
10

9
8

IN

N/C
N/C

T2

N/C

T4

GND

VDD

N/C
T1
N/C
T3
N/C
T5

8
7
6
5

1
2
3
4

IN
T2
T4

GND

VDD
T1
T3
T5

DDU8C-xx DIP
DDU8C-xxA1 Gull-Wing
DDU8C-xxB1 J-Lead
DDU8C-xxM Military DIP

Military SMD
DDU8C-xxMD1
DDU8C-xxMD4

PIN DESCRIPTIONS

IN Signal Input
T1-T5 Tap Outputs
VDD +5 Volts
GND Ground

DASH NUMBER SPECIFICATIONS

Part

Number

Total

Delay (ns)

Delay Per

Tap (ns)

DDU8C-5050

50 ± 2.5 10.0 ± 3.0

DDU8C-5060

60 ± 3.0 12.0 ± 3.0

DDU8C-5075

75 ± 4.0 15.0 ± 3.0

DDU8C-5100

100 ± 5.0 20.0 ± 3.0

DDU8C-5125

125 ± 6.5 25.0 ± 3.0

DDU8C-5150

150 ± 7.5 30.0 ± 3.0

DDU8C-5175

175 ± 8.0 35.0 ± 4.0

DDU8C-5200

200 ± 10.0 40.0 ± 4.0

DDU8C-5250

250 ± 12.5 50.0 ± 5.0

NOTE: Any dash number between 5004 and 5250

not shown is also available.

DDU8C

Doc #97013 DATA DELAY DEVICES, INC. 2

1/28/97 Tel: [phone] Fax: [phone] http://www.datadelay.com

APPLICATION NOTES

HIGH FREQUENCY RESPONSE

The DDU8C tolerances are guaranteed for input
pulse widths and periods greater than those
specified in the test conditions. Although the
device will function properly for pulse widths as
small as 40% of the total delay and periods as
small as 80% of the total delay (for a symmetric
input), the delays may deviate from their values
at low frequency. However, for a given input
condition, the deviation will be repeatable from
pulse to pulse. Contact technical support at Data

Delay Devices if your application requires device
testing at a specific input condition.

POWER SUPPLY BYPASSING

The DDU8C relies on a stable power supply to
produce repeatable delays within the stated
tolerances. A 0.1uf capacitor from VDD to GND,
located as close as possible to the VDD pin, is
recommended. A wide VDD trace and a clean
ground plane should be used.

DEVICE SPECIFICATIONS

TABLE 1: ABSOLUTE MAXIMUM RATINGS

PARAMETER SYMBOL MIN MAX UNITS NOTES

DC Supply Voltage V

DD

-0.3 7.0 V

Input Pin Voltage V

IN

-0.3 VDD+0.3 V

Storage Temperature T

STRG

-55 150 C

Lead Temperature T

LEAD

300 C 10 sec

TABLE 2: DC ELECTRICAL CHARACTERISTICS

(0C to 70C, 4.75V to 5.25V)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

High Level Output Voltage V

OH

3.98 4.4 V VDD = 5.0, IOH = MAX
VIH = MIN, VIL = MAX

Low Level Output Voltage V

OL

0.15 0.26 V VDD = 5.0, IOL = MAX
VIH = MIN, VIL = MAX

High Level Output Current I

OH

-4.0 mA

Low Level Output Current I

OL

4.0 mA

High Level Input Voltage V

IH

3.15 V

Low Level Input Voltage V

IL

1.35 V

Input Current I

IH

0.10

µA

VDD = 5.0