DADD 3D7010S-90, 3D7010S-80, 3D7010S-500, 3D7010S-400, 3D7010S-300 Datasheet

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3D7010

MONOLITHIC 10-TAP

VDD

data



FIXED DELAY LINE (SERIES 3D7010)

FEATURES

• All-silicon, low-power CMOS technology*

• TTL/CMOS compatible inputs and outputs

• Vapor phase, IR and wave solderable

• Auto-insertable (DIP package)

• Low ground bounce noise

• Leading- and trailing-edge accuracy

• Delay range: 8 through 500ns

• Delay tolerance: 5% or 2ns

• Temperature stability: ±3% typical (0C-70C)

• Vdd stability: ±2% typical (4.75V-5.25V)

• Minimum input pulse width: 20% of total

delay

FUNCTIONAL DESCRIPTION

The 3D7010 10-Tap Delay Line product family consists of fixed-delay CMOS integrated circuits. Each package contains a single delay line, tapped and buffered at 10 points spaced uniformly in time. Tap-to-tap (incremental) delay values can range from 8ns through 50ns. The input is reproduced at the outputs without inversion, shifted in time as per the user-specified dash number. The 3D7010 is TTL- and CMOScompatible, capable of driving ten 74LS-type loads, and features both rising- and falling-edge accuracy.

The all-CMOS 3D7010 integrated circuit has been designed as a reliable, economic alternative to hybrid TTL fixed delay lines. It is offered in a standard 14-pin auto-insertable DIP and a space saving surface mount 16-pin SOIC.

N/C

O2 O4 O6 O8

GND

(For mechanical data, see Case Dimensions document)

2 3 4 5 6 7

3D7010 DIP 3D7010G Gull-Wing

(300 Mil)

delay devices, inc.

PACKAGES

VDD

O10

PIN DESCRIPTIONS

IN Delay Line Input O1 Tap 1 Output (10%) O2 Tap 2 Output (20%) O3 Tap 3 Output (30%) O4 Tap 4 Output (40%) O5 Tap 5 Output (50%) O6 Tap 6 Output (60%) O7 Tap 7 Output (70%) O8 Tap 8 Output (80%) O9 Tap 9 Output (90%) O10 Tap 10 Output (100%) VCC +5 Volts GND Ground

N/C N/C

O2 O4 O6 O8

GND

3 4 5 6 7 8

3D7010S (300 Mil)

SOIC

N/C

O10

TABLE 1: PART NUMBER SPECIFICATIONS

PART NUMBER TOLERANCES INPUT RESTRICTIONS

DIP-14

3D7010

3D7010G

-80 -80

-90 -90

-100 -100

-150 -150

-200 -200

-250 -250

-300 -300

-400 -400

-500 -500

NOTE: Any dash number between 80 and 500 not shown is also available. 1996 Data Delay Devices

*PATENTED

SOIC-16

3D7010S

TOTAL DELAY

(ns)

80 ± 4.0 8.0 ± 1.5

90 ± 4.5 9.0 ± 1.7 100 ± 5.0 10.0 ± 2.0 150 ± 7.5 15.0 ± 2.0

200 ± 10.0 20.0 ± 2.5 250 ± 12.5 25.0 ± 2.5 300 ± 15.0 30.0 ± 3.0 400 ± 20.0 40.0 ± 4.0 500 ± 25.0 50.0 ± 5.0

TAP-TO-TAP

DELAY

(ns)

Max Operating

Frequency

4.17 MHz 31.2 MHz 120.0 ns 16.0 ns

3.70 MHz 27.8 MHz 135.0 ns 18.0 ns

3.33 MHz 25.0 MHz 150.0 ns 20.0 ns

2.22 MHz 16.7 MHz 225.0 ns 30.0 ns

1.67 MHz 12.5 MHz 300.0 ns 40.0 ns

1.33 MHz 10.0 MHz 375.0 ns 50.0 ns

1.11 MHz 8.33 MHz 450.0 ns 60.0 ns

0.83 MHz 6.25 MHz 600.0 ns 80.0 ns

0.67 MHz 5.00 MHz 750.0 ns 100.0 ns

Absolute Max

Oper. Freq.

Min Operating

Pulse Width

Absolute Min

Oper. P.W.

Doc #96004 DATA DELAY DEVICES, INC. 1

12/2/96 3 Mt. Prospect Ave. Clifton, NJ 07013

3D7010

APPLICATION NOTES

OPERATIONAL DESCRIPTION

The 3D7010 ten-tap delay line architecture is shown in Figure 1. The delay line is composed of a number of delay cells connected in series. Each delay cell produces at its output a replica of the signal present at its input, shifted in time. The delay cells are matched and share the same compensation signals, which minimizes tap-totap delay deviations over temperature and supply voltage variations.

INPUT SIGNAL CHARACTERISTICS

The Frequency and/or Pulse Width (high or low) of operation may adversely impact the specified delay accuracy of the particular device. The reasons for the dependency of the output delay accuracy on the input signal characteristics are varied and complex. Therefore a Maximum and an Absolute Maximum operating input frequency and a Minimum and an Absolute Minimum operating pulse width have been specified.

OPERATING FREQUENCY

The Absolute Maximum Operating Frequency specification, tabulated in Table 1, determines the highest frequency of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable duty cycle distortion.

The Maximum Operating Frequency specification determines the highest frequency of the delay line input signal for which the output delay accuracy is guaranteed.

To guarantee the Table 1 delay accuracy for input frequencies higher than the Maximum Operating Frequency, the 3D7010 must be tested at the user operating frequency. Therefore, to facilitate production and device identification, the part number will include a custom reference designator identifying the intended frequency of operation. The programmed delay accuracy of the device is guaranteed, therefore, only at the user specified input frequency. Small input frequency variation about the selected frequency will only marginally impact the programmed delay accuracy, if at all.

Nevertheless, it is strongly recommended that the engineering staff at DATA DELAY DEVICES be consulted.

OPERATING PULSE WIDTH

The Absolute Minimum Operating Pulse Width (high or low) specification, tabulated in Table 1, determines the smallest Pulse Width of

the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable pulse width distortion.

The Minimum Operating Pulse Width (high or low) specification determines the smallest Pulse Width of the delay line input signal for which the output delay accuracy tabulated in Table 1 is guaranteed.

To guarantee the Table 1 delay accuracy for input pulse width smaller than the Minimum Operating Pulse Width, the 3D7010 must be tested at the user operating pulse width. Therefore, to facilitate production and device identification, the part number will include a

O1IN O2 O3 O4

10% 10% 10% 10% 10% 10% 10% 10% 10% 10%

VDD

Figure 1: 3D7010 Functional Diagram

O5 O6 O7 O8 O9 O10

Temp & VDD

Compensation

GND

Doc #96004 DATA DELAY DEVICES, INC. 2

12/2/96 Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com

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