DADD 3D7503G-50, 3D7503G-5, 3D7503D-20, 3D7503D-10, 3D7503-50 Datasheet

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3D7503
Doc #98009 DATA DELAY DEVICES, INC. 1
12/11/98 3 Mt. Prospect Ave. Clifton, NJ 07013
MONOLITHIC MANCHESTER ENCODER/DECODER (SERIES 3D7503)
FEATURES
Encoder and decoder function independently
Encoder has buffered clock output
TTL/CMOS compatible inputs and outputs
Vapor phase, IR and wave solderable
Auto-insertable (DIP pkg.)
Low ground bounce noise
Maximum data rate: 50 MBaud
Data rate range: ±15%
Lock-in time: 1 bit
FUNCTIONAL DESCRIPTION
The 3D7503 is a monolithic CMOS Manchester Encoder/Decoder combo chip. The device uses bi-phase-level encoding to embed a clock signal into a data stream for transmission across a communications link. In this encoding mode, a logic one is represented by a high-to-low transition in the center of the bit cell, while a logic zero is represented by a low-to-high transition.
The Manchester encoder combines the clock (CIN) and data (DIN) into a single bi-phase-level signal (TX). An inverted version of this signal (TXB) is also available. The data baud rate (in MBaud) is equal to the input clock frequency (in MHz). A replica of the clock input is also available (CBUF).
The encoder may be reset by setting the RESB input low; otherwise, it should be left high. The TX and TXB signals may be disabled (high-Z) by setting TXENB high. Similarly, CBUF may be disabled by setting CEN low. Under most operating conditions, the encoder is never reset, TX and TXB are always enabled, and CBUF is not used. With this in mind, the 3D7503 provides an internal pull-up resistor on RESB and internal pull­down resistors on CEN and TXENB, so that most users can leave these inputs uncommitted.
The Manchester decoder accepts the embedded-clock signal at the RX input. The recovered clock and data signals are presented on COUT and DOUTB, respectively, with the data signal inverted. The operating baud rate (in MBaud) is specified by the dash number of the device. The input baud rate may vary by as much as ±15% from the nominal device baud rate without compromising the integrity of the information received.
Because the decoder is not PLL-based, it does not require a long preamble in order to lock onto the received signal. Rather, the device requires at most one bit cell before the data presented at the output is valid. This is extremely useful in cases where the information arrives in bursts and the input is otherwise turned off.
Normally, the encoder and decoder function independently. However, if the LOOP input is set high, the encoded TX signal is fed back internally into the decoder and the RX input is ignored. This feature is useful for diagnostics. The LOOP input has an internal pull-down resistor and may be left uncommitted if this feature is not needed.
data
delay devices, inc.
3
PACKAGES
14 13 12 11 10
9 8
1 2 3 4 5 6 7
CIN
CEN
RX
COUT
DIN
RESB
GND
VDD CBUF LOOP TXENB DOUTB TXB TX
3D7503-xxx DIP (.300) 3D7503G-xxx Gull Wing (.300) 3D7503D-xxx SOIC (.150)
PIN DESCRIPTIONS
Encoder:
CIN Clock Input DIN Data Input RESB Reset CEN Clock buffer enable TXENB Transmit enable CBUF Buffered clock TX,TXB Transmitted signal
Decoder:
RX Received Signal COUT Recovered Clock DOUTB Recovered Data
Common:
LOOP Loop enable VDD +5 Volts GND Ground
1998 Data Delay Devices
3D7503
Doc #98009 DATA DELAY DEVICES, INC. 2
12/11/98 Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
TABLE 1: PART NUMBER SPECIFICATIONS
PART DECODER BAUD RATE (MBaud)
NUMBER Nominal Minimum Maximum
3D7503-5 5.00 4.25 5.75 3D7503-10 10.00 8.50 11.50 3D7503-20 20.00 17.00 23.00 3D7503-25 25.00 21.25 28.75 3D7503-30 30.00 25.50 34.50 3D7503-40 40.00 34.00 46.00 3D7503-50 50.00 42.50 57.50
NOTE: Any baud rate between 5 and 50 MBaud not shown is also available at no extra cost.
APPLICATION NOTES
ENCODER
The Manchester encoder subsystem samples the data input at the rising edge of the input clock. The sampled data is used in conjunction with the clock rising and falling edges to generate the by­phase level Manchester code.
The encoder employs the timing of the clock rising and falling edges (duty cycle) to implement the required coding scheme, as shown in Figure
1. To reduce the difference between the output data high time and low time, it is essential that the deviation of the input clock duty cycle from 50/50 be minimized.
The encoder presents at its outputs the true and the complimented encoded data. The High-to­Low time skew of the selected data output should be budgeted by the user, as it relates to his application, to satisfactorily estimate the distortion of the transmitted data stream. Such an estimate is very useful in determining the functionality and margins of the data link, if a Manchester decoder is used to decode the received data.
RESET (RESB)
CLOCK (CIN)
DATA (DIN)
TRANSMIT (TX)
TRANSMIT (TXB)
t
DS
t
DH
Figure 1: Timing Diagram (Encoder)
1/f
C
1 0 1 1 0 0 1 0
1 0 1 1 0 0 1 0
(Left high for normal operation)
T
2H
T
2L
T
1H
T
1L
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