DADD 3D7110S-8, 3D7110S-5, 3D7110S-4, 3D7110S-2.5, 3D7110S-2 Datasheet

3D7110

Doc #96005 DATA DELAY DEVICES, INC. 1

12/2/96 3 Mt. Prospect Ave. Clifton, NJ 07013

MONOLITHIC 10-TAP
FIXED DELAY LINE
(SERIES 3D7110)

FEATURES

• All-silicon, low-power CMOS technology

• TTL/CMOS compatible inputs and outputs

• Vapor phase, IR and wave solderable

• Auto-insertable (DIP pkg.)

• Low ground bounce noise

• Leading- and trailing-edge accuracy

• Delay range: .75 through 80ns

• Delay tolerance: 5% or 1ns

• Temperature stability: ±3% typical (0C-70C)

• Vdd stability: ±1% typical (4.75V-5.25V)

• Minimum input pulse width: 15% of total delay

• 14-pin Gull-Wing and 16-pin SOIC available as

drop-in replacements for hybrid delay lines

FUNCTIONAL DESCRIPTION

The 3D7110 10-Tap Delay Line product family consists of fixed-delay
CMOS integrated circuits. Each package contains a single delay line,
tapped and buffered at 10 points spaced uniformly in time. Tap-to-tap
(incremental) delay values can range from 0.75ns through 8.0ns. The
input is reproduced at the outputs without inversion, shifted in time as
per the user-specified dash number. The 3D7110 is TTL- and CMOS­compatible, capable of driving ten 74LS-type loads, and features both
rising- and falling-edge accuracy.

The all-CMOS 3D7110 integrated circuit has been designed as a
reliable, economic alternative to hybrid TTL fixed delay lines. It is
offered in a standard 14-pin auto-insertable DIP and space saving
surface mount 14- and 16-pin SOIC packages.

PACKAGES

14
13
12
11
10

9
8

1
2
3
4
5
6
7

IN

N/C

O2
O4
O6
O8

GND

VDD
O1
O3
O5
O7
O9
O10

3D7110 DIP
3D7110G Gull-Wing

(300 Mil)

1

2
3
4
5
6
7
8

16

15
14
13
12
11
10

9

IN

N/C
N/C

O2
O4
O6
O8

GND

VDD

N/C
O1
O3
O5
O7
O9
O10

3D7110S SOIC

(300 Mil)

1

2
3
4
5
6
7

14

13
12
11
10

9
8

IN

N/C

O2
O4
O6
O8

GND

VDD

O1
O3
O5
O7
O9
O10

3D7110D

SOIC

(150 Mil)

data

delay
devices, inc.



3

(For mechanical data, see Case Dimensions document)

PIN DESCRIPTIONS

IN Delay Line Input
O1 Tap 1 Output (10%)
O2 Tap 2 Output (20%)
O3 Tap 3 Output (30%)
O4 Tap 4 Output (40%)
O5 Tap 5 Output (50%)
O6 Tap 6 Output (60%)
O7 Tap 7 Output (70%)
O8 Tap 8 Output (80%)
O9 Tap 9 Output (90%)
O10 Tap 10 Output (100%)
VCC +5 Volts
GND Ground

TABLE 1: PART NUMBER SPECIFICATIONS

PART NUMBER TOLERANCES INPUT RESTRICTIONS

DIP-14

3D7110

3D7110G

SOIC-14

3D7110D

SOIC-16

3D7110S

TOTAL
DELAY

(ns)

TAP-TAP

DELAY

(ns)

Max

Operating

Frequency

Absolute

Max

Oper. Freq.

Min

Operating

Pulse Width

Absolute

Min

Oper. P.W.

-.75 -.75 -.75

6.75 ± 1.0* 0.75 ± 0.4

28.4 MHz 166.7 MHz 17.6 ns 3.00 ns

-1 -1 -1

9.0 ± 1.0* 1.0 ± 0.5

23.8 MHz 166.7 MHz 21.0 ns 3.00 ns

-1.5 -1.5 -1.5

13.5 ± 1.0* 1.5 ± 0.7

18.0 MHz 166.7 MHz 27.8 ns 3.00 ns

-2 -2 -2

18.0 ± 1.0* 2.0 ± 0.8

14.5 MHz 166.7 MHz 34.5 ns 3.00 ns

-2.5 -2.5 -2.5

22.5 ± 1.1* 2.5 ± 1.0

18.2 MHz 125.0 MHz 27.5 ns 4.00 ns

-4 -4 -4

36.0 ± 1.8* 4.0 ± 1.3

8.33 MHz 133.3 MHz 60.0 ns 6.00 ns

-5 -5 -5

50.0 ± 2.5 5.0 ± 1.5

6.67 MHz 66.7 MHz 75.0 ns 7.50 ns

-8 -8 -8

80.0 ± 4.0 8.0 ± 1.5

4.17 MHz 41.7 MHz 120.0 ns 12.0 ns

* Total delay referenced to Tap1 output; Input-to-Tap1 = 5.0ns ±± 1.0ns
NOTE: Any dash number between .75 and 8 not shown is also available. 1996 Data Delay Devices

3D7110

Doc #96005 DATA DELAY DEVICES, INC. 2

12/2/96 Tel: [phone] Fax: [phone] http://www.datadelay.com

APPLICATION NOTES

OPERATIONAL DESCRIPTION

The 3D7110 ten-tap delay line architecture is
shown in Figure 1. The delay line is composed
of a number of delay cells connected in series.
Each delay cell produces at its output a replica of
the signal present at its input, shifted in time.
The delay cells are matched and share the same
compensation signals, which minimizes tap-to­tap delay deviations over temperature and
supply voltage variations.

INPUT SIGNAL CHARACTERISTICS

The Frequency and/or Pulse Width (high or low)
of operation may adversely impact the specified
delay accuracy of the particular device. The
reasons for the dependency of the output delay
accuracy on the input signal characteristics are
varied and complex. Therefore a Maximum and
an Absolute Maximum operating input
frequency and a Minimum and an Absolute
Minimum operating pulse width have been
specified.

OPERATING FREQUENCY

The Absolute Maximum Operating Frequency
specification, tabulated in Table 1, determines
the highest frequency of the delay line input
signal that can be reproduced, shifted in time at
the device output, with acceptable duty cycle
distortion.

The Maximum Operating Frequency
specification determines the highest frequency of
the delay line input signal for which the output
delay accuracy is guaranteed.

To guarantee the Table 1 delay accuracy for
input frequencies higher than the Maximum
Operating Frequency, the 3D7110 must be
tested at the user operating frequency.
Therefore, to facilitate production and device
identification, the part number will include a
custom reference designator identifying the
intended frequency of operation. The
programmed delay accuracy of the device is
guaranteed, therefore, only at the user specified
input frequency. Small input frequency variation
about the selected frequency will only marginally
impact the programmed delay accuracy, if at all.

Nevertheless, it is strongly recommended
that the engineering staff at DATA DELAY
DEVICES be consulted.

OPERATING PULSE WIDTH

The Absolute Minimum Operating Pulse
Width (high or low) specification, tabulated in
Table 1, determines the smallest Pulse Width of

the delay line input signal that can be
reproduced, shifted in time at the device output,
with acceptable pulse width distortion.

The Minimum Operating Pulse Width (high or
low) specification determines the smallest Pulse
Width of the delay line input signal for which the
output delay accuracy tabulated in Table 1 is
guaranteed.

To guarantee the Table 1 delay accuracy for
input pulse width smaller than the Minimum
Operating Pulse Width, the 3D7110 must be
tested at the user operating pulse width.
Therefore, to facilitate production and device
identification, the part number will include a

VDD

O1IN O2 O3 O4

Temp & VDD

Compensation

GND

Figure 1: 3D7110 Functional Diagram

10% 10% 10% 10% 10% 10% 10% 10% 10% 10%

O5 O6 O7 O8 O9 O10

3D7110

Doc #96005 DATA DELAY DEVICES, INC. 3

12/2/96 3 Mt. Prospect Ave. Clifton, NJ 07013

APPLICATION NOTES (CONT’D)

custom reference designator identifying the

intended frequency and duty cycle of operation.
The programmed delay accuracy of the device is
guaranteed, therefore, only for the user specified
input characteristics. Small input pulse width
variation about the selected pulse width will only
marginally impact the programmed delay
accuracy, if at all. Nevertheless, it is strongly

recommended that the engineering staff at
DATA DELAY DEVICES be consulted.

POWER SUPPLY AND
TEMPERATURE CONSIDERATIONS

The delay of CMOS integrated circuits is strongly
dependent on power supply and temperature.
The monolithic 3D7110 programmable delay line
utilizes novel and innovative compensation

circuitry to minimize the delay variations induced
by fluctuations in power supply and/or
temperature.

The thermal coefficient is reduced to 600
PPM/C, which is equivalent to a variation , over
the 0C-70C operating range, of ±±3% from the
room-temperature delay settings and/or 1.0ns,
whichever is greater. The power supply
coefficient is reduced, over the 4.75V-5.25V
operating range, to ±±1% of the delay settings at
the nominal 5.0VDC power supply and/or 1.5ns,
whichever is greater. It is essential that the

power supply pin be adequately bypassed
and filtered. In addition, the power bus
should be of as low an impedance
construction as possible. Power planes are
preferred.

DEVICE SPECIFICATIONS

TABLE 2: ABSOLUTE MAXIMUM RATINGS

PARAMETER SYMBOL MIN MAX UNITS NOTES

DC Supply Voltage V

DD

-0.3 7.0 V

Input Pin Voltage V

IN

-0.3 VDD+0.3 V

Input Pin Current I

IN

-1.0 1.0 mA 25C

Storage Temperature T

STRG

-55 150 C

Lead Temperature T

LEAD

300 C 10 sec

TABLE 3: DC ELECTRICAL CHARACTERISTICS

(0C to 70C, 4.75V to 5.25V)

PARAMETER SYMBOL MIN MAX UNITS NOTES

Static Supply Current* I

DD

30 mA

High Level Input Voltage V

IH

2.0 V

Low Level Input Voltage V

IL

0.8 V

High Level Input Current I

IH

1

µA

VIH = V

DD

Low Level Input Current I

IL

1

µA

VIL = 0V

High Level Output Current I

OH

-4.0 mA VDD = 4.75V
VOH = 2.4V

Low Level Output Current I

OL

4.0 mA VDD = 4.75V
VOL = 0.4V

Output Rise & Fall Time TR & T

F

2 ns CLD = 5 pf

*IDD(Dynamic) = 10 * CLD * VDD * F Input Capacitance = 10 pf typical
where: CLD = Average capacitance load/tap (pf) Output Load Capacitance (CLD) = 25 pf max

F = Input frequency (GHz)

3D7110

Doc #96005 DATA DELAY DEVICES, INC. 4

12/2/96 Tel: [phone] Fax: [phone] http://www.datadelay.com

SILICON DELAY LINE AUTOMATED TESTING

TEST CONDITIONS

INPUT: OUTPUT:
Ambient Temperature: 25oC ± 3oC R

load

: 10KΩ ± 10%

Supply Voltage (Vcc): 5.0V ± 0.1V C

load

: 5pf ± 10%

Input Pulse: High = 3.0V ± 0.1V Threshold: 1.5V (Rising & Falling)

Low = 0.0V ± 0.1V

Source Impedance: 50Ω Max.
Rise/Fall Time: 3.0 ns Max. (measured

between 0.6V and 2.4V )

Pulse Width: PWIN = 1.25 x Total Delay
Period: PERIN = 2.5 x Total Delay

NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.

10KΩ

470Ω

5pf

Device
Under

Test

Digital
Scope

OUT1

OUT2

OUT4

OUT3

OUT

TRIGINREF

TRIG

Figure 2: Test Setup

DEVICE UNDER

TEST (DUT)

DIGITAL SCOPE/

TIME INTERVAL COUNTER

PULSE

GENERATOR

COMPUTER

SYSTEM

PRINTER

IN

OUT5

OUT6

OUT8

OUT7

OUT10

OUT9

Figure 3: Timing Diagram

t

PLH

t

PHL

PER

IN

PW

IN

t

RISE

t

FALL

0.6V

0.6V

1.5V

1.5V

2.4V

2.4V

1.5V

1.5V

V

IH

V

IL

V

OH

V

OL

INPUT
SIGNAL

OUTPUT
SIGNAL