DDU222F
5-TAP, TTL-INTERFACED FIXED DELAY LINE (SERIES DDU222F)
data 3 ® delay
devices, inc.
FEATURES
∙Five equally spaced outputs
∙Very narrow device (SIP package)
∙Stackable for PC board economy
∙Input & outputs fully TTL interfaced & buffered
∙10 T2L fan-out capability
PACKAGES
1 2 3 4 5 6 7 8
VCC IN T1 T2 T3 T4 T5 GND
DDU222F-xx Commercial
DDU222F-xxM Military
FUNCTIONAL DESCRIPTION |
PIN DESCRIPTIONS |
|
The DDU222F-series device is a 5-tap digitally buffered delay line. The |
IN |
Signal Input |
signal input (IN) is reproduced at the outputs (T1-T5), shifted in time by an |
T1-T5 |
Tap Outputs |
amount given by the device dash number. For dash numbers less than |
VCC |
+5 Volts |
25, the total delay of the line is measured from T1 to T5, with the nominal |
GND |
Ground |
value given by the dash number. The nominal tap-to-tap delay increment |
|
|
is given by 1/4 of this number. The inherent delay from IN to T1 is nominally 3.5ns. For dash numbers greater than or equal to 25, the total delay of the line is measured from IN to T5, with the nominal value given by the dash number. The nominal tap-to-tap delay increment is given by 1/5 of this number.
SERIES SPECIFICATIONS
∙Minimum input pulse width: 40% of total delay
∙Output rise time: 2ns typical
∙Supply voltage: 5VDC ± 5%
∙Supply current: ICCL = 32ma typical
ICCH = 7ma typical
∙Operating temperature: 0° to 70° C
∙Temp. coefficient of total delay: 100 PPM/°C
3.5ns 25% 25% 25% 25%
VCC IN |
T1 |
T2 |
T3 |
T4 |
T5 GND |
Functional diagram for dash numbers < 25
20% 20% 20% 20% 20%
VCC IN |
T1 |
T2 |
T3 |
T4 |
T5 GND |
Functional diagram for dash numbers >= 25
©1997 Data Delay Devices
DASH NUMBER SPECIFICATIONS
Part |
Total |
Delay Per |
|
Number |
Delay (ns) |
Tap (ns) |
|
DDU222F-4 |
4 ± 1.0 * |
1.0 ± 0.5 |
|
DDU222F-6 |
6 ± 1.0 * |
1.5 ± 0.5 |
|
DDU222F-8 |
8 ± 2.0 * |
2.0 ± 1.0 |
|
DDU222F-10 |
10 ± 2.0 * |
2.5 ± 1.0 |
|
DDU222F-12 |
12 ± 2.0 * |
3.0 ± 1.0 |
|
DDU222F-16 |
16 ± 2.0 * |
4.0 ± 1.5 |
|
DDU222F-25 |
25 |
± 3.0 |
5.0 ± 2.0 |
DDU222F-30 |
30 |
± 3.0 |
6.0 ± 2.0 |
DDU222F-35 |
35 |
± 3.0 |
7.0 ± 2.0 |
DDU222F-40 |
40 |
± 3.0 |
8.0 ± 2.0 |
DDU222F-45 |
45 |
± 3.0 |
9.0 ± 3.0 |
DDU222F-50 |
50 |
± 3.0 |
10.0 ± 3.0 |
DDU222F-60 |
60 |
± 3.0 |
12.0 ± 3.0 |
DDU222F-75 |
75 |
± 4.0 |
15.0 ± 3.0 |
DDU222F-100 |
100 ± 5.0 |
20.0 ± 3.0 |
|
DDU222F-125 |
125 ± 6.5 |
25.0 ± 3.0 |
|
DDU222F-150 |
150 ± 7.5 |
30.0 ± 3.0 |
|
DDU222F-175 |
175 ± 8.0 |
35.0 ± 4.0 |
|
DDU222F-200 |
200 |
± 10.0 |
40.0 ± 4.0 |
DDU222F-250 |
250 |
± 12.5 |
50.0 ± 5.0 |
*Total delay is referenced to first tap output Input to first tap = 3.5ns ± 1ns
NOTE: Any dash number between 4 and 250 not shown is also available.
Doc #97011 |
DATA DELAY DEVICES, INC. |
1 |
1/27/97 |
3 Mt. Prospect Ave. Clifton, NJ 07013 |
DDU222F
APPLICATION NOTES
HIGH FREQUENCY RESPONSE
The DDU222F tolerances are guaranteed for input pulse widths and periods greater than those specified in the test conditions. Although the device will function properly for pulse widths as small as 40% of the total delay and periods as small as 80% of the total delay (for a symmetric input), the delays may deviate from their values at low frequency. However, for a given input condition, the deviation will be repeatable from pulse to pulse. Contact technical support at Data
Delay Devices if your application requires device testing at a specific input condition.
POWER SUPPLY BYPASSING
The DDU222F relies on a stable power supply to produce repeatable delays within the stated tolerances. A 0.1uf capacitor from VCC to GND, located as close as possible to the VCC pin, is recommended. A wide VCC trace and a clean ground plane should be used.
DEVICE SPECIFICATIONS
TABLE 1: ABSOLUTE MAXIMUM RATINGS
PARAMETER |
SYMBOL |
MIN |
MAX |
UNITS |
NOTES |
DC Supply Voltage |
VCC |
-0.3 |
7.0 |
V |
|
Input Pin Voltage |
VIN |
-0.3 |
VDD+0.3 |
V |
|
Storage Temperature |
TSTRG |
-55 |
150 |
C |
|
Lead Temperature |
TLEAD |
|
300 |
C |
10 sec |
TABLE 2: DC ELECTRICAL CHARACTERISTICS
(0C to 70C, 4.75V to 5.25V)
PARAMETER |
SYMBOL |
MIN |
TYP |
MAX |
UNITS |
NOTES |
High Level Output Voltage |
VOH |
2.5 |
3.4 |
|
V |
VCC = MIN, IOH = MAX |
|
|
|
|
|
|
VIH = MIN, VIL = MAX |
Low Level Output Voltage |
VOL |
|
0.35 |
0.5 |
V |
VCC = MIN, IOL = MAX |
|
|
|
|
|
|
VIH = MIN, VIL = MAX |
High Level Output Current |
IOH |
|
|
-1.0 |
mA |
|
Low Level Output Current |
IOL |
|
|
20.0 |
mA |
|
High Level Input Voltage |
VIH |
2.0 |
|
|
V |
|
Low Level Input Voltage |
VIL |
|
|
0.8 |
V |
|
Input Clamp Voltage |
VIK |
|
|
-1.2 |
V |
VCC = MIN, II = IIK |
Input Current at Maximum |
IIHH |
|
|
0.1 |
mA |
VCC = MAX, VI = 7.0V |
Input Voltage |
|
|
|
|
|
|
High Level Input Current |
IIH |
|
|
20 |
μA |
VCC = MAX, VI = 2.7V |
Low Level Input Current |
IIL |
|
|
-0.6 |
mA |
VCC = MAX, VI = 0.5V |
Short-circuit Output Current |
IOS |
-60 |
|
-150 |
mA |
VCC = MAX |
Output High Fan-out |
|
|
|
25 |
Unit |
|
Output Low Fan-out |
|
|
|
12.5 |
Load |
|
Doc #97011 |
DATA DELAY DEVICES, INC. |
2 |
1/27/97 |
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com |