T2117
Zero-Voltage Switch with Adjustable Ramp
Description
The integrated circuit, T2117, is designed as a zerovoltage switch in bipolar technology. It is used to control resistive loads at mains by a triac in zero-crossing mode.
A ramp generator allows power control function by period group control, whereas full-wave logic guarantees that full mains cycles are used for load switching.
Features
Direct supply from the mains
Current consumption ≤ 0.5 mA
Very few external components
Full-wave drive ± no DC current component in the load circuit
Negative output current pulse typ. 100 mA ± short-circuit protected
Simple power control
Ramp generator
Reference voltage
Applications
Full-wave power control
Temperature regulation
Power blinking switch
Block Diagram
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D1 |
BYT41M |
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L |
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220 k |
R2 |
R1 |
18 k |
Load |
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(250 V~) |
(Rsync) |
2 W |
1000 W |
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C |
R4 |
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±VS |
C |
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2 |
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8 |
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5 |
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2 |
100 k |
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1 |
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2.2 F/ |
1 |
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7 |
100 F/ |
VM = |
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Ramp |
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230 V~ |
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10 V |
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Synchronization |
Supply |
16 V |
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generator |
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GND |
TIC |
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R5 |
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236N |
MT2 |
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12 k |
3 |
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6 |
100 |
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Full-wave logic |
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MT1 |
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max |
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4 |
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Pulse |
R3 |
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Comparator |
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100 k |
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amplifier |
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min |
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Reference voltage |
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R6 |
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1.4 V |
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T2117 |
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18 k |
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N |
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Figure 1. Block diagram with typical circuit, period group control 0 to 100%
Ordering Information
Extended Type Number |
Package |
Remarks |
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T2117-3AS |
DIP8 |
Tube |
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T2117-TAS |
SO8 |
Tube |
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T2117-TAQ |
SO8 |
Taped and reeled |
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Rev. A2, 17-Dec-01 |
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1 (11) |
T2117 |
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Pin Description |
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Ramp |
1 |
8 |
Vsync |
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T2117 |
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CRamp |
2 |
7 |
GND |
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Ramp |
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T2117 |
1 |
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control |
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POSIN |
3 |
6 |
Output |
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R4 |
2 |
C2 |
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NEGIN |
4 |
5 |
VS |
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±VS |
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Figure 2. Pinning |
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Pin |
Symbol |
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Function |
1 |
Ramp |
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Ramp output |
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2 |
CRamp |
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Ramp capacitor |
3 |
POSIN |
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Non-inverting comparator input |
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4 |
NEGIN |
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Inverting comparator input |
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5 |
VS |
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Supply voltage |
6 |
Output |
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Trigger pulse output |
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7 |
GND |
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Ground |
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8 |
Vsync |
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Voltage synchronization |
General Description
The integrated circuit T2117 is a triac controller for zerocrossing mode. It is designed to control power in switching resistive loads of mains supplies.
Information regarding supply sync. is provided at Pin 8
via resistor RSync. To avoid DC load on the mains, the fullwave logic guarantees that complete mains cycles are
used for load switching.
A fire pulse is released when the inverting input of the comparator is negative (Pin 4) with respect to the noninverting input (Pin 3) and internal reference voltage. A ramp generator with free selectable duration can be performed by capacitor C2 at Pin 2. The ramp function is used for open-loop control (figure 4), but also for application with proportional band regulation (figure 11). Ramp voltage available at capacitor C2 is decoupled across the emitter follower at Pin l. To maintain the lamp flicker specification, ramp duration is adjusted according to the controlling load. In practice, interference should be avoided (temperature control). Therefore, a two-point control is preferred to proportional control. One can use internal reference voltage for simple applications. In that case, Pin 3 is inactive and connected to Pin 7 (GND), see figure 13.
Figure 3. Pin 1 internal network |
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V1 |
Final voltage |
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±1.6 V |
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Vmin |
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±7.6 V |
Initial voltage |
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Vmax |
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T |
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Figure 4. Threshold voltage of the ramp at VS = ±8.8 V |
Triac Firing Current (Pulse)
This depends on the triac requirement. It can be limited with gate series resistance which is calculated as follows:
RGmax |
7.5 V ± VGmax |
± 36 |
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IGmax |
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IP = |
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IGmax |
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tp |
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T |
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where: |
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VG |
= Gate voltage |
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IGmax |
= Maximum gate current |
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Ip |
= Average gate current |
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tp |
= Firing pulse width |
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T |
= Mains period duration |
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Firing Pulse Width tp (Figure 5)
This depends on the latching current of the triac and its load current. The firing pulse width is determined by the zero-crossing detection which can be influenced with the help of sync. resistance, Rsync, (figure 6).
2 |
IL VM |
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tp = |
arc. sin |
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P |
2 |
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2 (11) |
Rev. A2, 17-Dec-01 |
T2117
whereby: |
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IL |
= |
Latching current of the triac |
VM |
= |
Mains supply, effective |
P |
= |
Power load (user's power) |
Total current consumption is influenced by the firing pulse width which can be calculated as follows:
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tp |
) 0.6 V |
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VM 2 sin ( 2 |
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Rsync |
3.5 10 5A |
49 k |
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10.00 |
VMains = 230 V |
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1.00 |
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t p ( ms ) |
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IL ( mA) |
0.10 |
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200 |
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100 |
0.01 |
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50 |
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10 |
100 |
1000 |
10000 |
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P ( W ) |
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Figure 5. Output pulse width
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2000 |
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V |
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) |
1600 |
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VMains |
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= 230 |
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( kOhm |
1200 |
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Rsync |
800 |
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0 |
200 |
400 |
600 |
800 |
1000 |
1200 |
1400 |
tp ( s )
Figure 6. Synchronization resistance
Supply Voltage
The T2117 contains voltage limiting and can be connected with the mains supply via the diode D1 and the resistor R1. Supply voltage between Pin 5 and 7 is limited to a typical value of 9.5 V.
Rev. A2, 17-Dec-01
The series resistance R1 can be calculated (figures 7 and 8) as follows:
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V |
V |
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(V |
M ± |
V )2 |
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R |
1max |
= 0.85 |
Mmin ± |
Smax |
; P |
(R1) |
= |
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S |
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2 Itot |
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2 R1 |
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Itot |
= IS + IP + Ix |
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whereby: |
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VM |
= Mains voltage |
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VS |
= Limiting voltage of the IC |
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Itot |
= Total current consumption |
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IS |
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= Current requirement of the IC (without load) |
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Ix |
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= Current requirement of other peripheral |
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components |
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P(R1) |
= Power dissipation at R1 |
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) |
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VMains |
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=230V |
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30 |
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Itot ( mA ) |
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Figure 7. Maximum resistance of R1 |
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VMains |
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=230V |
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( W ) |
4 |
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R1 |
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Itot ( mA )
Figure 8. Power dissipation of R1 according to current consumption
3 (11)
T2117
Absolute Maximum Ratings
Parameter |
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Symbol |
Value |
Unit |
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Supply current |
Pin 5 |
±IS |
30 |
mA |
Sync. current |
Pin 8 |
ISync. |
5 |
mA |
Output current ramp generator |
Pin 1 |
IO |
3 |
mA |
Input voltages |
Pin 1, 3, 4, 6 |
±VI |
≤VS |
V |
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Pin 2 |
±VI |
2 to VS |
V |
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Pin 8 |
±VI |
≤ 7.3 |
V |
Power dissipation |
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Tamb = 45°C |
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Ptot |
400 |
mW |
Tamb = 100°C |
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Ptot |
125 |
mW |
Junction temperature |
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Tj |
125 |
°C |
Operating ambient temperature range |
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Tamb |
0 to 100 |
°C |
Storage temperature range |
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Tstg |
±40 to + 125 |
°C |
Thermal Resistance
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Parameter |
Symbol |
Value |
Unit |
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Junction ambient |
SO8 |
RthJA |
200 |
K/W |
Junction ambient |
DIP8 |
RthJA |
110 |
K/W |
Electrical Characteristics
±VS = 8.8 V, Tamb = 25°C, reference point Pin 7, unless otherwise specified
Parameter |
Test Conditions / Pins |
Symbol |
Min. |
Typ. |
Max. |
Unit |
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Supply-voltage limitation |
±IS = 1 mA |
Pin 5 |
±VS |
9.0 |
9.5 |
10.0 |
V |
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±IS = 10 mA |
Pin 5 |
±VS |
9.1 |
9.6 |
10.1 |
V |
Supply current |
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Pin 5 |
±IS |
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500 |
A |
Voltage limitation |
I8 = ± 1 mA |
Pin 8 |
± VI |
7.7 |
8.2 |
8.7 |
V |
Synchronization current |
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Pin 8 |
±Isync |
0.12 |
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mA |
Zero detector |
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Pin 8 |
±Isync |
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35 |
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A |
Output pulse width |
VM= 230 V , |
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Rsync = 220 k |
Pin 6 |
tP |
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260 |
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s |
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Rsync = 470 k |
Pin 6 |
tP |
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460 |
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s |
Output pulse current |
V6 = 0 V |
Pin 6 |
±IO |
100 |
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mA |
Comparator |
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Input offset voltage |
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Pin 3,4 |
± VI0 |
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15 |
mV |
Input bias current |
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Pin 4 |
IIB |
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1 |
A |
Common-mode input |
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Pin 3,4 |
±VIC |
1 |
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(VS±1) |
V |
voltage |
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Threshold internal |
V3 = 0 V |
Pin 4 |
±VRef |
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1.4 |
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V |
reference |
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4 (11) |
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Rev. A2, 17-Dec-01 |