Apple MACBOOK AIR A1465 Schematic

TABLE_TABLEOFCONTENTS_ITEM

DRAWING

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

II NOT TO REPRODUCE OR COPY IT

3

B

7

BRANCH

DRAWING NUMBER

SIZE

D

SHEET

R

DATE

D

A

C

PAGE

A

C

3456

D

B

8 7 6 5 4 2 1

12

APPD

CK

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

DRAWING TITLE

DESCRIPTION OF REVISION

REV ECN

REVISION

PROPRIETARY PROPERTY OF APPLE INC.

J41 MLB SCHEMATIC 6.6.0

4/09/13

DVT

PCB TO BE SILK-SCREENED WITH UL/CUL RECOGNITION MARK, MANUFACTURER’S UL FILE

Schematic / PCB #’s

NUMBER, UL PCB MATERIAL DESIGNATION, 130-C TEMP. RATING AND V-0 FLAME RATING.

PCB, UL RECOGNIZED, MIN. 130-C TEMP. RATING AND V-0 FLAME RATING PER UL 796 & UL 94.

PRODUCT SAFETY REQUIREMENTS:

ALIASES RESOLVED

1 OF 73

<PART_DESCRIPTION>

<SCH_NUM>

<ECO_DESCRIPTION>

1 OF 120

SMC

12/17/2012

50

WILL_J43

35

IPD Connector

01/17/2013

48

J43_MLB

34

External A USB3 Connector

02/20/2013

46

J43_MLB

33

Camera 2 of 2

09/14/2012

40

J43_MLB

32

Camera 1 of 2

01/09/2013

39

J43_MLB1

31

SSD Connector

02/20/2013

37

J43_MLB

30

Wireless Connector

10/02/2012

35

J43_MLB

29

Thunderbolt Connector A

09/04/2012

32

J43_MLB

28

TBT Power Support

12/17/2012

30

WILL_J43

27

Thunderbolt Host (2 of 2)

07/16/2012

29

J15_MLB

26

Thunderbolt Host (1 of 2)

01/29/2013

28

WILL_J43

25

LPDDR3 DRAM Termination

09/21/2012

27

J43_MLB

24

LPDDR3 DRAM Channel B (32-63)

MASTER

26

MASTER

23

LPDDR3 DRAM Channel B (0-31)

MASTER

25

MASTER

22

LPDDR3 DRAM Channel A (32-63)

MASTER

24

MASTER

21

LPDDR3 DRAM Channel A (0-31)

MASTER

23

MASTER

20

DDR3 VREF MARGINING

02/04/2013

22

WILL_J43

19

Project Chipset Support

01/17/2013

20

J43_MLB

18

Chipset Support

01/09/2013

19

J43_MLB1

17

CPU/PCH Merged XDP

12/17/2012

18

WILL_J43

16

PCH GPIO/MISC/LPIO

01/14/2013

16

WILL_J43

15

PCH PCIe/USB/LPC/SPI/SMBus

09/13/2012

15

WILL_J43

14

PCH PM/PCI/GFX

02/20/2013

14

J43_MLB

13

PCH Audio/JTAG/SATA/CLK

12/17/2012

13

WILL_J43

12

PCH Decoupling

09/13/2012

12

WILL_J43

11

CPU Decoupling

01/11/2013

10

LABEL_J41

10

CPU/PCH GROUNDS

10/02/2012

9

J43_MLB

9

CPU/PCH POWER

10/02/2012

8

J43_MLB

8

CPU DDR3/LPDDR3 Interfaces

09/13/2012

7

WILL_J43

7

CPU Misc/JTAG/CFG/RSVD

09/13/2012

6

WILL_J43

6

CPU GFX/NCTF/RSVD

09/13/2012

5

WILL_J43

5

PD Parts

MASTER

4

MASTER

4

BOM Variants

MASTER

3

MASTER

3

BOM Configuration

01/17/2013

2

J43_MLB

2

73

MASTER

Reference

120

72

09/13/2012

J43_MLB

Project Specific Constraints

118

71

09/13/2012

CHINMAY_J41

SMC Constraints

117

70

09/07/2012

CHINMAY_J41

Camera Constraints

116

69

09/07/2012

CHINMAY_J41

Thunderbolt Constraints

115

68

09/07/2012

CHINMAY_J41

Memory Constraints

114

67

09/14/2012

J43_MLB

PCH Constraints 2

113

66

11/13/2012

CLEAN_J41

PCH Constraints 1

112

65

09/21/2012

J43_MLB

CPU Constraints

111

64

10/24/2012

J43_MLB

PCB Rule Definitions

110

63

MASTER

Project FCT/NC/Aliases

105

62

12/17/2012

WILL_J43

Func Test / No Test

104

61

MASTER

Signal Aliases

102

60

12/17/2012

WILL_J43

Power Aliases

100

59

11/13/2012

CLEAN_J41

LIO Connector

95

58

09/11/2012

J43_MLB

Internal DisplayPort Connector

83

57

09/16/2012

J43_MLB

Power Control

81

56

10/04/2012

J43_MLB

Power FETs

80

55

10/04/2012

J43_MLB

Misc Power Supplies

78

54

09/13/2012

J43_MLB

LCD/KBD Backlight Driver

77

53

09/10/2012

J43_MLB

1.05V S0 Power Supply

76

52

10/02/2012

J43_MLB

5V S4RS3 / 3.3V S5 Power Supply

75

51

09/17/2012

J43_MLB

LPDDR3 Supply

74

50

09/21/2012

J43_MLB

CPU VR12.5 VCC Power Stage

73

49

10/09/2012

J43_MLB

CPU VR12.6 VCC Regulator IC

72

48

09/14/2012

J43_MLB

PBus Supply & Battery Charger

71

47

09/13/2012

J43_MLB

DC-In & G3H Supply

70

46

MASTER

Battery Connector & Hall Effect

69

45

09/04/2012

J43_MLB

Audio: Speaker Amp

64

44

12/13/2010

K21_MLB

LPC+SPI Debug Connector

61

43

09/13/2012

J43_MLB

Fan

60

42

02/20/2013

J43_MLB

Thermal Sensors

58

41

02/26/2013

SID_J41

Debug Sensors 1

56

40

02/26/2013

SID_J41

Voltage & Load Side Current Sensing

55

39

02/26/2013

SID_J41

High Side Current Sensing

54

38

09/28/2012

J43_MLB

SMBus Connections

53

37

02/20/2013

J43_MLB

SMC Project Support

52

Table of Contents

MASTER

1

MASTER

1

820-3435 CRITICAL

1

PCB

PCBF,MLB,J41

SCHEM,MLB,J41

CRITICAL

1

SCH

051-9795

LAST_MODIFIED=Tue Apr 9 19:41:45 2013

TITLE=MLB

ABBREV=DRAWING

Page Contents

(.csa)

Sync

Date

36

12/17/2012

WILL_J43

SMC Shared Support

51

Date

(.csa)

Page SyncContents

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_BOMGROUP_ITEM

DRAM Parts

CFG 0

00

1 0

CFG 1

CPU DRAM CFG Chart

HYNIX

VENDOR

SAMSUNG

1 1

0

0 1

1

0 1

CFG 2

CFG 3

ELPIDA

SIZE 4GB 8GB

MICRON

B

A

DIE REV

BOM Groups

Alternate Parts

Current Sensor Configuration

Module Parts

Programmable Parts

CPU DRAM SPD Straps

RAMCFG0:L,RAMCFG1:H,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:SAMSUNG_8GB

DDR3:SAMSUNG_8GB

TBTROM:BLANK

335S0865

EEPROM,256KBIT,SPI,5MHZ,1.8V,2X3QFN

CRITICAL1 U2890

341S3802

IC,EEPROM,C/R (V23.4) EVT,J41/J41

CRITICAL1

TBTROM:PROG

U2890

335S0809 1

64 MBIT SPI SERIAL DUAL I/O FLASH,8X6X0.8

BOOTROM_MAC:BLANK

CRITICALU6100

SYNC_DATE=01/17/2013

SYNC_MASTER=J43_MLB

BOM Configuration

DDR3:SAMSUNG_4GB

RAMCFG0:L,RAMCFG1:H,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:SAMSUNG_4GB

64 MBIT SPI SERIAL DUAL I/O FLASH,8X6X0.8

BOOTROM_NUM:BLANK

CRITICAL1335S0803 U6100

IC,EFI ROM (V0071) DVT,J41/J43

341S3809 1

BOOTROM:PROG

CRITICALU6100

IC,SMC12-A3,40MHZ/50DMIPS MCU,9X9,157BGA

338S1159 1

SMC:BLANK

U5000 CRITICAL

CPU:1.4GHZ

HSW,SR16L,PRQ,C0,1.4,15W,2+3,1.1,3M,BGA

U0500 CRITICAL1337S4526

DDR3:MICRON_4GB

RAMCFG0:H,RAMCFG1:L,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:MICRON_4GB

IC,TBT,CR-4C,B1,PRQ,CIO,288,12X12 FC-CSP

338S1113 U2800 CRITICAL1

HSW,SR16M,PRQ,C0,1.3,15W,2+3,1.0,3M,BGA

U0500 CRITICAL1

CPU:1.3GHZ

337S4525

CPU_HS_ISNS:YES,CPUVR_ISNS:YES,DRAM_ISNS:YES,P1V05_ISNS:YES,AIRPORT_ISNS:YES,SSD_ISNS:YES,LCDBKLT_ISNS:YES,P3V3S5_ISNS:YES,3V3S0_ISNS:YES,OTHER_HS_ISNS:YES,CAM_ISNS:YES,CPUDDR_ISNS:YES,PANEL_ISNS:YES

ISNS:ENG

CPU_HS_ISNS:YES,CPUVR_ISNS:YES,DRAM_ISNS:YES,P1V05_ISNS:NO,AIRPORT_ISNS:NO,SSD_ISNS:YES,LCDBKLT_ISNS:NO,P3V3S5_ISNS:NO,3V3S0_ISNS:NO,OTHER_HS_ISNS:NO,CAM_ISNS:NO,CPUDDR_ISNS:NO,PANEL_ISNS:NO

ISNS:PROD

DDR3:HYNIX_4GB

RAMCFG0:L,RAMCFG1:L,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:HYNIX_4GB

ALTERNATE,COMMON,MLB_MISC,MLB_DEBUG:ENG,MLB_PROGPARTS

MLB_COMMON

XDP_CONN

MLB_DEVEL:PVT

DEVEL_BOM,XDP,LPCPLUS

MLB_DEBUG:ENG

MLB_MISC

PP5V5_DCIN:NO,TBTHV:P15V,EDP,CAM_XTAL:NO,CAM_WAKE:NO,APCLKRQ:ISOL,TPAD_INTWAKE:SHARED,USB_PWR:S3,SD_ON_MLB,VCORE_FETS

138S0638

Murata alt to Samsung

138S0841

ALL

376S1180

Renesas alt to Vishay

376S0761

ALL

152S1804

ALL

TDK alt to Toko

152S1876

107S0240

ALL

107S0255

Cyntec alt to TFT

ALL

107S0248

Cyntec alt to TFT

107S0250

Epson alt to TXC

ALL

197S0545 197S0544

ALL

377S0104377S0155

OnSemi alt to Infineon

197S0343197S0481

Epson crystal alt to TXC

ALL

Cyntec sense R alt to TFT

107S0254

ALL

107S0241

353S3452 353S1286

ALL

Maxim alt to Microchip

128S0325128S0397

Kemet alt to Sanyo

ALL

197S0542 197S0544

NDK alt to TXC

ALL

DDR3:HYNIX_8GB

RAMCFG0:L,RAMCFG1:L,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:HYNIX_8GB

ALL

197S0478197S0479

200uW Epson alt to NDK

ALL

128S0371 128S0376

Kemet alt to Sanyo

128S0394

ALL

NEC alt to Sanyo

128S0415

197S0480

NDK crystal alt to TXC

ALL

197S0343

ALL

Taiyo alt to Samsung

138S0681 138S0638

152S1821

ALL

Cyntec alt to NEC

152S1757

Kemet alt to Sanyo

128S0398 128S0220

ALL

376S0855

ALL

NXP alt for Diodes dual

376S1129

138S0703 138S0648

Murata alt to Taiyo Yuden

ALL

152S0586

ALL

Dale/Vishay alt to Cyntec

152S1301

372S0186 372S0185

NXP alt to Diodes

ALL

Murata alt to Taiyo Yuden

138S0684

ALL

138S0660

376S1032 376S0855

Toshiba alt for Diodes dual

ALL

371S0558371S0713

ALL

Diodes alt to ST Micro

128S0386

Kemet alt to Sanyo

128S0284

ALL

376S0604376S1053

ALL

Diodes alt to Fairchild

ALL

376S1089

NXP alt for Diodes single

376S1128

1 CRITICAL

IC,BCM15700A2,S2 PCIE CAMERA PROCESSOR

U3900338S1186

ALTERNATE,BKLT:ENG,XDP_CONN,DDRVREF_DAC,S0PGOOD_ISL,DBGLED,ISNS:ENG

MLB_DEVEL:ENG

MLB_DEBUG:PVT

DEVEL_BOM,BKLT:PROD,XDP,LPCPLUS,ISNS:PROD

BKLT:PROD,LPCPLUS,XDP,ISNS:PROD

MLB_DEBUG:PROD

RAMCFG0:H,RAMCFG1:H,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:ELPIDA_8GB

DDR3:ELPIDA_8GB

RAMCFG0:H,RAMCFG1:H,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:ELPIDA_4GB

DDR3:ELPIDA_4GB

CRITICAL J41_MLBJ69551

ASSEMBLY,SUBASSY,PCBA,HALL EFFECT,K99

607-6811

HSW,SR16H,PRQ,C0,1.7,15W,2+3,1.1,4M,BGA

U0500 CRITICAL1

CPU:1.7GHZ

337S4528

IC,SDRAM,8Gb,LPDDR3-1600,178P FBGA

U2300,U2400,U2500,U2600

CRITICAL4

DRAM_TYPE:HYNIX_4GB

333S0677

IC,SDRAM,16Gb,LPDDR3-1600,178P FBGA

333S0681

U2300,U2400,U2500,U2600

DRAM_TYPE:HYNIX_8GB

CRITICAL4

IC,SDRAM,8Gb,LPDDR3-1600,178P FBGA

333S0676

U2300,U2400,U2500,U2600

CRITICAL4

DRAM_TYPE:SAMSUNG_4GB

IC,SDRAM,8Gb,LPDDR3-1600,178P FBGA

U2300,U2400,U2500,U2600

DRAM_TYPE:MICRON_4GB

333S0679 4 CRITICAL

IC,SDRAM,8Gb,LPDDR3-1600,178P FBGA

CRITICAL4

U2300,U2400,U2500,U2600

DRAM_TYPE:ELPIDA_4GB

333S0678

IC,SDRAM,16Gb,LPDDR3-1600,178P FBGA

U2300,U2400,U2500,U2600

333S0666 CRITICAL4

DRAM_TYPE:ELPIDA_8GB

IC,SDRAM,16Gb,LPDDR3-1600,178P FBGA

4 CRITICAL

U2300,U2400,U2500,U2600

DRAM_TYPE:SAMSUNG_8GB

333S0680

VCORE_FET:VSHY

2

CRITICAL

MOSFET,N-CH,30V,22A,6.0M,8P 3.3X3.3 DFN

Q7311,Q7321

376S1174

1

LABEL

825-7670

LABEL,TEXT,MLB,K21/K78

VCORE_FET:REN

2

Q7310,Q7320

CRITICAL376S0964

MOSFET,N-CH,25V,30A,9.6M,8P 3.3X3.3 DFN

VCORE_FET:REN

Q7311,Q7321

CRITICAL

2

376S1104

MOSFET,N-CH,25V,30A,6.1M,8P 3.3X3.3 DFN

VCORE_FET:VSHY

MOSFET,N-CH,30V,15.3A,12M,8P 3.3X3.3 DFN

2

Q7310,Q7320

CRITICAL376S1173

CRITICAL1

SOLDERPASTE

900-0090

1 GLUE946-3892

J11/J13 MLB DYMAX ADHESIVE 29993-SC 0.4G

CRITICAL

<SCH_NUM>

2 OF 120

2 OF 73

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

BOM Groups

Sub-BOMs

BOM Variants

Programmable Parts

Alternate Parts

BOM Variants

SYNC_MASTER=MASTER

SYNC_DATE=MASTER

685-0063

Renesas alt to Vishay

ALL

685-0062

Elpida CAM DRAM alt to Hynix

ALL

333S0704 333S0700

BOOTROM:PROG,SMC:PROG,TBTROM:PROG

MLB_PROGPARTS

985-0017

J41 MLB DEVELOPMENT BOM

MLB_DEVEL:ENG

639-4703

MLB_CMNPTS,CPU:1.3GHZ,DDR3:MICRON_4GB

PCBA,MLB,BETTER,MI 4GB,J41

MLB_CMNPTS,CPU:1.3GHZ,DDR3:ELPIDA_8GB

PCBA,MLB,BETTER,EL 8GB,J41

639-4437

MLB_CMNPTS,CPU:1.7GHZ,DDR3:HYNIX_4GB

PCBA,MLB,BEST,HY 4GB,J41:

639-4118

PCBA,MLB,BEST,EL 4GB,J41

MLB_CMNPTS,CPU:1.7GHZ,DDR3:ELPIDA_4GB

639-4275

PCBA,MLB,BEST,EL 8GB,J41

MLB_CMNPTS,CPU:1.7GHZ,DDR3:ELPIDA_8GB

639-4276

PCBA,MLB,BEST,MI 4GB,J41

MLB_CMNPTS,CPU:1.7GHZ,DDR3:MICRON_4GB

639-4702

MLB_CMNPTS,CPU:1.3GHZ,DDR3:HYNIX_8GB

PCBA,MLB,BETTER,HY 8GB,J41

639-4435 639-4436

MLB_CMNPTS,CPU:1.3GHZ,DDR3:ELPIDA_4GB

PCBA,MLB,BETTER,EL 4GB,J41

685-0024

MLB_COMMON,J41_MLB

CMN PTS,PCBA,MLB,J41

MLB_CMNPTS,CPU:1.7GHZ,DDR3:HYNIX_8GBPCBA,MLB,BEST,HY 8GB,J41

639-4274

PCBA,MLB,BETTER,HY 4GB,J41

639-4434

MLB_CMNPTS,CPU:1.3GHZ,DDR3:HYNIX_4GB

VCOREFETS

VCORE_FETS

VCORE FET,VSHY,J41

685-0063 CRITICAL

1

CMN PTS,PCBA,MLB,J41

685-0024

CMNPTS

1

MLB_CMNPTS

CRITICAL

J41 MLB DEVELOPMENT BOM

CRITICAL985-0017

DEVEL

1

DEVEL_BOM

VCORE_FET:VSHY

685-0063

VCORE FET,VSHY,J41

VCORE FET,REN,J41

685-0062

VCORE_FET:REN

1341S3757 SMC:PROGCRITICAL

IC,SMC-A3 SCPL,EXT,V22.12A18,PROTO 1,J41

U5000

<SCH_NUM>

3 OF 120

3 OF 73

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PD Module Parts

CPU Heat Sink Mounting Bosses

998-2691

Fan Boss

860-1327

4x 860-1327

860-1327

X21 Boss SSD Boss

860-1327

870-1938

870-1940

USB/SD Card Pogo

EMI I/O Pogo Pins

DisplayPort Pogo

998-3975

998-2691

998-3975

998-2691

Can Slots

998-3975

2x TBT pin diodes

2x TBT chip

998-3975

2x USB connector

2x MDP connector

1

Z0410

STDOFF-4.5OD1.8H-SM

1

Z0412

STDOFF-4.5OD1.8H-SM

1

Z0413

STDOFF-4.5OD1.8H-SM

1

Z0411

STDOFF-4.5OD1.8H-SM

1

Z0415

STDOFF-4.5OD1.9H-SM

1

Z0414

STDOFF-4.5OD1.9H-SM

1

Z0405

STDOFF-4.5OD1.8H-SM

1

ZS0405

SM

POGO-2.0OD-3.6H-K86-K87

CRITICAL

1

ZS0407

SM

POGO-2.0OD-2.95H-K86-K87

CRITICAL

1

SL0401

TH-NSP

SL-1.1X0.4-1.4x0.7

1

SL0402

TH-NSP

SL-1.1X0.4-1.4x0.7

1

SL0404

SL-1.1X0.45-1.4x0.75

TH-NSP

1

SL0403

SL-1.1X0.45-1.4x0.75

TH-NSP

1

SL0406

SL-1.1X0.4-1.4x0.7

TH-NSP

1

SL0408

TH-NSP

SL-1.1X0.45-1.4x0.75

1

SL0405

SL-1.1X0.4-1.4x0.7

TH-NSP

1

SL0407

TH-NSP

SL-1.1X0.45-1.4x0.75

806-5108

CAN,TOPSIDE,COVER,ALT,J41/J43

TBTTOPSIDE_2P_COVER

CRITICAL

1

CRITICAL

1

725-1792

INSULATOR,CPU,J41/J43

CPU_INSULATOR

806-3083

1

SHLD,USB,MLB,J11/J13

USBCAN

CRITICAL

806-5107

CAN,TOPSIDE,ALT,J41/J43

TBTTOPSIDE_2P_FENCE

CRITICAL

1

CAN,COVER,TBT,J11/J13

806-3215

1

TBTCOVER CRITICAL

MDPCAN

CRITICAL

CAN,MDP,J11/J13

1

806-3216

CAN,TBT,J11/J13

CRITICAL

1

TBTFENCE806-3142

SYNC_MASTER=MASTER

SYNC_DATE=MASTER

PD Parts

<SCH_NUM>

4 OF 120

4 OF 73

OUT

OUT OUT OUT OUT

BI BI

EDP_TXN0

EDP_TXP1

EDP_TXN1

EDP_TXP0

DDI1_TXP2

DDI1_TXN2

DDI2_TXP3

DDI2_TXN3

DDI2_TXP2

DDI2_TXN2

DDI2_TXP1

DDI2_TXN1

DDI2_TXP0

DDI1_TXP1

DDI1_TXN1

DDI1_TXP0

DDI1_TXN0

DDI2_TXN0

DDI1_TXP3

DDI1_TXN3

EDP_RCOMP

EDP_DISP_UTIL

EDP_AUXN EDP_AUXP

EDP_TXP3

EDP_TXN3

EDP_TXP2

EDP_TXN2

DDI

EDP

SYM 1 OF 19

SYM 17 OF 19

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

RSVD

RSVD RSVD

RSVD

RSVD RSVD

RSVD RSVD RSVD RSVD

RSVD RSVD RSVD

SPARE

SYM 18 OF 19

TP

NC NC

NCNC NCNC NCNC

NCNC NCNC NCNC NC NC NC NC

OUT

OUT OUT OUT

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

if necessary)

(MUXed with HDMI

TBT Sink 1

TBT Sink 0

DDI Port Assignments:

Internal panel

eDP Port Assignment:

exist between both TP’s on each corner.

daisy-chain fashion. Continuity should

NO_TEST NO_TEST

Each corner of CPU has two testpoints.

MCP Daisy-Chain Strategy:

Other corner test signals connected in

18 25 65

58 65

62

58 65

B49

C46

B47

B46

A49

C47

A47

C45

D20 A43

B45

A45

B53

B50

B54

C50

A53

C49

C53

C51

B57

A55

C58

C55

A57

B55

B58

C54

U0500

2C+GT2

OMIT_TABLE

BGA-TSP

HASWELL-ULT

CRITICAL

C2

C1

B63

B62

B61

B3

B2

AY62

AY61

AY60

AY3

AY2

AW63

AW62

AW61

AW3

AW2

AW1

AV1

A62

A61

A60

A4

A3

U0500

CRITICAL

OMIT_TABLE

BGA-TSP

HASWELL-ULT

2C+GT2

U10

T23

R23

N23

J21

H22

F22

D15

AY14

AW14

AV44

AU44

AU15

AU10

AT2

AP7

AM11

AL1

U0500

BGA-TSP

2C+GT2

CRITICAL

OMIT_TABLE

HASWELL-ULT

1

TP0531

TP-P6

1

TP0500

TP-P6

1

TP0510

TP-P6

1

TP0501

TP-P6

1

TP0511

TP-P6

1

TP0520

TP-P6

1

TP0521

TP-P6

1

TP0530

TP-P6

2

1

R0530

1/20W 201

MF

1%

24.9

25 65

18 25 65

SYNC_MASTER=WILL_J43 SYNC_DATE=09/13/2012

CPU GFX/NCTF/RSVD

NC_INT_ML_CP<3>

MCP_EDP_RCOMP

NC_INT_ML_CP<1>

DP_TBTSNK1_ML_C_N<2> DP_TBTSNK1_ML_C_P<2> DP_TBTSNK1_ML_C_N<3>

DP_TBTSNK1_ML_C_P<1>

DP_TBTSNK0_ML_C_P<3>

DP_TBTSNK0_ML_C_N<0>

DP_TBTSNK0_ML_C_P<2>

DP_TBTSNK0_ML_C_P<1>

DP_TBTSNK0_ML_C_N<1>

DP_TBTSNK0_ML_C_P<0>

DP_TBTSNK1_ML_C_N<0> DP_TBTSNK1_ML_C_P<0> DP_TBTSNK1_ML_C_N<1>

DP_TBTSNK1_ML_C_P<3>

DP_TBTSNK0_ML_C_N<2>

DP_TBTSNK0_ML_C_N<3>

PPVCOMP_S0_CPU

DP_INT_ML_C_N<0> DP_INT_ML_C_P<0> NC_INT_ML_CN<1>

NC_INT_ML_CN<2> NC_INT_ML_CP<2> NC_INT_ML_CN<3>

DP_INT_AUXCH_C_N DP_INT_AUXCH_C_P

TRUE

MCP_DC_C1_C2

TRUE

MCP_DC_A3_B3 MCP_DC_A4

MCP_DC_A62

MCP_DC_A61_B61

TRUE

MCP_DC_AW1 MCP_DC_AW2_AY2

TRUE

MCP_DC_AW61_AY61 MCP_DC_AW62_AY62

TRUE

MCP_DC_AW62_AY62

MCP_DC_A61_B61

TRUE

MCP_DC_A3_B3

TRUE

MCP_DC_B62_B63

TRUE

MCP_DC_AW61_AY61

MCP_DC_AY60

MCP_DC_AW2_AY2

TRUE

MCP_DC_B2

MCP_DC_A60

MCP_DC_AW3_AY3

TRUE

MCP_DC_AW63

TRUE

MCP_DC_AW3_AY3

MCP_DC_AV1

TP_EDP_DISP_UTIL

5 OF 73

<SCH_NUM>

5 OF 120

8

5

SM_PG_CNTL1

SM_DRAMRST*

SM_RCOMP1 SM_RCOMP2

SM_RCOMP0

PROCHOT*

PROCPWRGD

PECI

CATERR*

BPM7*

BPM6*

BPM5*

BPM4*

BPM3*

BPM2*

BPM1*

BPM0*

PROC_TDO

PROC_TDI

PROC_TRST*

PROC_TMS

PROC_TCK

PREQ*

PRDY*

PROC_DETECT*

SYM 2 OF 19

MISC

THERMAL

JTAG

DDR3

PWR

BI BI

BI

NC NC

NC

BI

OUT

NC

BI

OUT

IN

OUT

VSS VSS

RSVD

CFG_RCOMP

RSVD

RSVD RSVD

TD_IREF

CFG0 CFG1

CFG5

CFG4

CFG3

CFG2

CFG6

CFG10

CFG9

CFG8

CFG7

CFG11

CFG15

CFG14

CFG13

CFG12

CFG18

CFG16

CFG17 CFG19

RSVD RSVD

RSVD_TP RSVD_TP

EDP_SPARE

RSVD_TP RSVD_TP

RSVD_TP

RSVD

RSVD RSVD

PROC_OPI_COMP

RSVD RSVD

RESERVED

SYM 19 OF 19

NC NC

NC NC NC

NC NC

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

CFG<9> :NO SVID-CAPABLE VR 1 = VR SUPPORTS SVID 0 = VR DOES NOT SUPPORT SVID CFG<8> :ALLOW NOA ON LOCKED UNITS 1 = NORMAL OPERATION 0 = NOA ALWAYS UNLOCKED

NOTE: Pre-ES2 CPUs have issue with Sx cycling, must set CFG<9> low to avoid issue, but this locks CPU VR at 1.7V Vboot (CPU Sighting #4391569).

and are only for debug access

These can be placed close to J1800

(IPU)

(IPD)

(IPU) (IPU) (IPU) (IPU)

(IPU) (IPU) (IPU) (IPU) (IPU)

(IPU)

(IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU)

(IPU)

CFG<0> :RESET SEQUENCE STALL 1 = NORMAL OPERATION 0 = STALL AFTER PCU PLL LOCK

CFG<1> :PCH-LESS MODE 1 = NORMAL OPERATION 0 = PCH-LESS MODE

CFG<4> :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED

(IPU)

CFG<10>:SAFE MODE BOOT 1 = NORMAL OPERATION 0 = POWER FEATURES NOT ACTIVE

(IPU)

AU61

AV60

AU60

AV61

AV15

C61

K63

E59

E61

F62

F63

E60

D61

K62

J62

N62

K61

J61

K60

H63

K59

H62

H61

H60

J60

U0500

CRITICAL

OMIT_TABLE

HASWELL-ULT

2C+GT2

BGA-TSP

2

1

R0640

MF

1/20W

201

5%

1K

NOSTUFF

2

1

R0639

MF

1/20W 201

5%

1K

HSW_PRE_ES2

2

1

R0638

NOSTUFF

1K

5%

201

1/20W

MF

2

1

R0631

NOSTUFF

1K

5%

201

1/20W MF

2

1

R0630

MF

1/20W 201

5%

1K

NOSTUFF

6

16 65

6

16 65

16 62 65

16 65

6

16 65

6

16 65

6

16 65

6

16 65

16

35 36 49 65

2

1

R0610

62

201

MF

1/20W

5%

2 1

R0611

1/20W

56

MF

5%

201

36 65

35 65

2

1

R0620

10K

5%

1/20W

MF

201

PLACE_NEAR=U0500.C61:12.7mm

16 65

16 62 65

12 16 62 65

16 62 65

2

1

R0652

PLACE_NEAR=U0500.AU61:12.7mm

1%

100

201

1/20W

MF

2

1

R0651

121

PLACE_NEAR=U0500.AV60:12.7mm

1%

201

1/20W

MF

2

1

R0650

PLACE_NEAR=U0500.AU60:12.7mm

MF

1/20W

201

200

1%

18

17

2

1

R0680

49.9

MF

201

1/20W

1%

P22 N21

B12

Y22

W23

L60

C63 C62

B51

AV63 AU63

A51

R20

P20

N60

J20 H18

E1

D58

D1

AV62

A5

AY15

B43

V63

V61

V62

Y60

Y61

Y62

AA60

AA63

AC63

U62

U63

AA61

AA62

T60

T61

T62

T63

U60

V60

AC62

AC60

U0500

BGA-TSP

2C+GT2

HASWELL-ULT

OMIT_TABLE

CRITICAL

2

1

R0690

49.9

1% 1/20W MF 201

2

1

R0685

8.25K

1%

201

MF

1/20W

2

1

R0634

EDP

MF

1/20W 201

5%

1K

CPU Misc/JTAG/CFG/RSVD

SYNC_MASTER=WILL_J43 SYNC_DATE=09/13/2012

CPU_SM_RCOMP<0>

PP1V05_S0

CPU_SM_RCOMP<2>

CPU_CATERR_L

CPU_CFG<9> TP_MCP_RSVD_B51

CPU_CFG<0> CPU_CFG<1>

CPU_CFG<5>

CPU_CFG<4>

CPU_CFG<3>

CPU_CFG<2>

CPU_CFG<6>

CPU_CFG<10>

CPU_CFG<8>

CPU_CFG<7>

CPU_CFG<11>

CPU_CFG<15>

CPU_CFG<14>

CPU_CFG<13>

CPU_CFG<18>

CPU_CFG<16>

CPU_CFG<17> CPU_CFG<19>

TP_MCP_RSVD_AV63 TP_MCP_RSVD_AU63

TP_MCP_RSVD_C63 TP_MCP_RSVD_C62

TP_MCP_RSVD_A51

CPU_OPI_RCOMP

CPU_CFG<4>

XDP_CPU_PRDY_L XDP_CPU_PREQ_L

XDP_CPU_TCK XDP_CPU_TMS XDP_CPUPCH_TRST_L

XDP_CPU_TDI XDP_CPU_TDO

XDP_BPM_L<0> XDP_BPM_L<1> XDP_BPM_L<2> XDP_BPM_L<3> XDP_BPM_L<4> XDP_BPM_L<5> XDP_BPM_L<6> XDP_BPM_L<7>

TP_MCP_RSVD_L60

CPU_CFG_RCOMP

CPU_CFG<12>

CPU_PWRGD

CPU_SM_RCOMP<1>

TP_CPU_MEM_RESET_L

CPU_MEMVTT_PWR_EN_LSVDDQ

CPU_PECI

CPU_PROCHOT_R_L

CPU_PROCHOT_L

CPU_CFG<0>

CPU_CFG<10> CPU_CFG<9> CPU_CFG<8> CPU_CFG<1>

PCH_TD_IREF

6 OF 73

6 OF 120

<SCH_NUM>

65

8

11 15 16 17 27 36 40 49 53

56 57 60 62

65

6

16 65

65

6

16 65

6

16 65

6

16 65

6

16 65

6

16 65

BI BI

BI

BI BI BI

BI BI

BI BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

OUT

OUT OUT

OUT

OUT OUT

OUT

OUT OUT OUT

OUT

OUT OUT OUT

OUT

OUT OUT OUT

BI

BI BI BI

BI

SA_DQ63

SA_DQ62

SA_DQ61

SA_DQ60

SA_DQ59

SA_DQ58

SA_DQ57

SA_DQ55 SA_DQ56

SA_DQ54

SA_DQ53

SA_DQ52

SA_DQ51

SA_DQ50

SA_DQ49

SA_DQ48

SA_DQ47

SA_DQ45 SA_DQ46

SA_DQ42 SA_DQ43 SA_DQ44

SA_DQ40 SA_DQ41

SA_DQ39

SA_DQ37 SA_DQ38

SA_DQ34

SA_DQ36

SA_DQ32 SA_DQ33

SA_DQ29 SA_DQ30 SA_DQ31

SA_DQ27 SA_DQ28

SA_DQ24 SA_DQ25

SA_DQ22 SA_DQ23

SA_DQ21

SA_DQ19 SA_DQ20

SA_DQ17 SA_DQ18

SA_DQ16

SA_DQ14 SA_DQ15

SA_DQ11

SA_DQ13

SA_DQ10

SA_DQ9

SA_DQ7 SA_DQ8

SA_DQ6

SA_DQ4 SA_DQ5

SA_DQ3

SA_DQ1

SA_DQ0

SA_CLK1*

SA_CLK0

SA_CLK0*

SA_DQ12

SM_VREF_DQ1

SM_VREF_CA

SM_VREF_DQ0

SA_DQ35

SA_DQ26

SA_DQ2

SA_CLK1

SA_CS0* SA_CS1*

SA_CKE0 SA_CKE1 SA_CKE2 SA_CKE3

SA_ODT0

SA_RAS*

SA_WE*

SA_CAS*

SA_MA0

SA_MA2

SA_MA1

SA_MA3 SA_MA4 SA_MA5

SA_MA7

SA_MA6

SA_MA8

SA_MA10

SA_MA9

SA_MA12

SA_MA11

SA_MA13 SA_MA14 SA_MA15

SA_BA2

SA_BA0 SA_BA1

SA_DQSP0

SA_DQSP2

SA_DQSP1

SA_DQSP3 SA_DQSP4 SA_DQSP5 SA_DQSP6 SA_DQSP7

SA_DQSN1

SA_DQSN0

SA_DQSN2

SA_DQSN4

SA_DQSN3

SA_DQSN5 SA_DQSN6 SA_DQSN7

SYM 3 OF 19

MEMORY CHANNEL A

OUT OUT

OUT

OUT OUT

OUT OUT OUT OUT

OUT OUT

OUT

OUT OUT OUT

OUT OUT OUT OUT OUT OUT OUT OUT

OUT

OUT OUT OUT OUT OUT OUT

BI

BI BI

BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5

SB_CKE0

SB_DQ6

SB_CKE1

SB_DQ7

SB_CKE2

SB_DQ8

SB_CKE3 SB_DQ9 SB_DQ10 SB_CS0* SB_DQ11 SB_CS1* SB_DQ12 SB_DQ13 SB_ODT0 SB_DQ14 SB_DQ15 SB_RAS* SB_DQ16

SB_WE* SB_DQ17 SB_CAS* SB_DQ18 SB_DQ19

SB_BA0 SB_DQ20

SB_BA1 SB_DQ21

SB_BA2 SB_DQ22 SB_DQ23

SB_MA0 SB_DQ24

SB_MA1 SB_DQ25

SB_MA2 SB_DQ26

SB_MA3 SB_DQ27

SB_MA4 SB_DQ28

SB_MA5 SB_DQ29

SB_MA6 SB_DQ30

SB_MA7 SB_DQ31

SB_MA8 SB_DQ32

SB_MA9 SB_DQ33 SB_MA10 SB_DQ34 SB_MA11 SB_DQ35 SB_MA12

SB_MA13 SB_DQ37 SB_MA14 SB_DQ38 SB_MA15 SB_DQ39 SB_DQ40

SB_DQSN0

SB_DQ41

SB_DQSN1

SB_DQ42

SB_DQSN2

SB_DQ43

SB_DQSN3

SB_DQ44

SB_DQSN4

SB_DQ45

SB_DQSN5

SB_DQ46

SB_DQSN6

SB_DQ47

SB_DQSN7 SB_DQ48 SB_DQ49

SB_DQSP0 SB_DQ50

SB_DQSP1 SB_DQ51

SB_DQSP2 SB_DQ52

SB_DQSP3 SB_DQ53

SB_DQSP4 SB_DQ54

SB_DQSP5 SB_DQ55

SB_DQSP6 SB_DQ56

SB_DQSP7 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

SB_DQ36

SB_CK0*

SB_CK0

SB_CK1*

SB_CK1

SYM 4 OF 19

MEMORY CHANNEL B

BI BI BI

BI

BI BI BI

BI BI

BI

BI BI

BI

BI BI BI

BI

BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI BI BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

RSVD4

RSVD3

CAA4

CAA2

CAA0

CAA8

CAA9

CAB0

CAA6

CAA7

CAB7

CAA1

CAA3

LPDDR3

CAB6

CAB4

CAB1

CAB2

CAB3

CAB5

CAB8

CAB9

CAA5

LPDDR3

CAB6

CAB4

CAB1

CAB2

CAB3

CAA4

CAA2

CAA0

RSVD2

RSVD1

CAB5

CAB8

CAB9

CAA5

CAA8

CAA9

CAB0

CAA6

CAA7

CAB7

CAA1

CAA3

61 68

21 61 68

61 68

21 61 68

61 68

61

20 21 24 61 68

20 21 24 68

20 24 68

21 24 68

20 24 68

61

21 24 61 68

61

20 24 61 68

61

61 68

21 61 68

61 68

AP51

AR51

AP49

AW34

AY34

AP32

AU40

AY39

AW39

AV40

AR36

AU39

AP36

AR38

AU42

AV42

AR35

AU41

AW41

AP35

AY37

AU36

AL49

AL42

AW53

AW57

AN55

AN58

AN61

AJ62

AL48

AL43

AV53

AV57

AM55

AM58

AN62

AJ61

AM62

AM63

AK60

AK51

AM51

AK48

AM48

AK61

AK49

AM49

AK46

AM46

AM42

AM40

AK43

AK45

AM45

AM43

AH60

AK42

AK40

AU52

AV52

AU54

AV54

AW52

AY52

AW54

AY54

AH61

AU56

AV56

AU58

AV58

AW56

AY56

AW58

AY58

AN54

AR54

AK62

AK55

AL55

AK54

AM54

AR55

AP55

AN57

AR57

AK58

AL58

AK63

AK57

AM57

AR58

AP58

AP60

AP61

AM60

AM61

AP62

AP63

AH62

AH63

AR32

AP33

AW36 AY36

AU37 AV37

AY43

AY42

AW43

AU43

AU34

AY41

AV35

AU35

U0500

HASWELL-ULT

BGA-TSP

OMIT_TABLE

CRITICAL

2C+GT2

21 24 68

19

22 24 68

23 24 68

22 24 68

23 24 68

22 23 24 68

22 23 24 61 68

61

23 24 61 68

61

22 24 61 68

61

61 68

23 61 68

61 68

23 61 68

61 68

AK35

AM35

AL32

AU46

AY47

AY46

AW46

AP45

AR45

AR42

AP42

AP46

AR46

AK33

AU47

AV47

AK36

AR40

AP40

AM18

AM21

AW18

AV22

AM25

AM28

AW26

AV30

AN18

AN21

AV18

AW22

AN25

AN28

AV26

AW30

AW27

AY27

AU29

AP18

AR18

AM20

AK20

AV29

AL18

AK18

AR20

AN20

AK22

AK21

AP21

AN22

AM22

AL21

AU31

AR22

AR21

AU17

AV17

AU19

AV19

AW17

AY17

AW19

AY19

AV31

AU21

AV21

AU23

AV23

AW21

AY21

AW23

AY23

AL25

AK25

AW29

AM26

AK26

AP25

AR25

AR26

AN26

AP28

AR28

AN29

AR29

AY29

AK28

AL28

AK29

AM29

AU25

AV25

AU27

AV27

AW25

AY25

AW31

AY31

AK32

AM32

AV50

AW49

AU50

AY49

AK38 AL38

AM38 AN38

AM33

AU49

AM36

AL35

U0500

BGA-TSP

2C+GT2

HASWELL-ULT

CRITICAL

OMIT_TABLE

61 68

23 61 68

61 68

CPU DDR3/LPDDR3 Interfaces

SYNC_MASTER=WILL_J43 SYNC_DATE=09/13/2012

MEM_B_DQ<62> MEM_B_DQ<63>

MEM_B_DQ<61>

MEM_A_DQS_N<7>

MEM_A_DQS_P<7>

MEM_A_DQ<63>

MEM_A_DQ<62>

MEM_A_DQ<61>

MEM_A_DQ<60>

MEM_A_DQ<59>

MEM_A_DQ<58>

MEM_A_DQ<57>

MEM_A_DQ<55> MEM_A_DQ<56>

MEM_A_DQ<54>

MEM_A_DQ<53>

MEM_A_DQ<52>

MEM_A_DQ<51>

MEM_A_DQ<50>

MEM_A_DQ<49>

MEM_A_DQ<48>

MEM_A_DQ<47>

MEM_A_DQ<45> MEM_A_DQ<46>

MEM_A_DQ<42> MEM_A_DQ<43> MEM_A_DQ<44>

MEM_A_DQ<40> MEM_A_DQ<41>

MEM_A_DQ<39>

MEM_A_DQ<37> MEM_A_DQ<38>

MEM_A_DQ<34>

MEM_A_DQ<36>

MEM_A_DQ<32> MEM_A_DQ<33>

MEM_A_DQ<29> MEM_A_DQ<30> MEM_A_DQ<31>

MEM_A_DQ<27> MEM_A_DQ<28>

MEM_A_DQ<24> MEM_A_DQ<25>

MEM_A_DQ<22> MEM_A_DQ<23>

MEM_A_DQ<21>

MEM_A_DQ<35>

MEM_A_DQ<26>

MEM_A_DQ<19> MEM_A_DQ<20>

MEM_A_DQ<17> MEM_A_DQ<18>

MEM_A_DQ<16>

MEM_A_DQ<14> MEM_A_DQ<15>

MEM_A_DQ<11>

MEM_A_DQ<13>

MEM_A_DQ<10>

MEM_A_DQ<9>

MEM_A_DQ<7> MEM_A_DQ<8>

MEM_A_DQ<6>

MEM_A_DQ<4> MEM_A_DQ<5>

MEM_A_DQ<3>

MEM_A_DQ<1>

MEM_A_DQ<0>

MEM_A_DQ<12>

MEM_A_DQ<2>

MEM_B_DQ<36>

MEM_B_DQ<60>

MEM_B_DQ<59>

MEM_B_DQ<58>

MEM_B_DQ<57>

MEM_B_DQ<56>

MEM_B_DQ<55>

MEM_B_DQ<54>

MEM_B_DQ<53>

MEM_B_DQ<52>

MEM_B_DQ<51>

MEM_B_DQ<48>

MEM_B_DQ<47>

MEM_B_DQ<46>

MEM_B_DQ<45>

MEM_B_DQ<43>

MEM_B_DQ<42>

MEM_B_DQ<41>

MEM_B_DQ<40>

MEM_B_DQ<39>

MEM_B_DQ<38>

MEM_B_DQ<35>

MEM_B_DQ<34>

MEM_B_DQ<33>

MEM_B_DQ<32>

MEM_B_DQ<31>

MEM_B_DQ<27>

MEM_B_DQ<26>

MEM_B_DQ<25>

MEM_B_DQ<24>

MEM_B_DQ<23>

MEM_B_DQ<22>

MEM_B_DQ<21>

MEM_B_DQ<20>

MEM_B_DQ<19>

MEM_B_DQ<18>

MEM_B_DQ<16>

MEM_B_DQ<15>

MEM_B_DQ<14>

MEM_B_DQ<13>

MEM_B_DQ<12>

MEM_B_DQ<11>

MEM_B_DQ<10>

MEM_B_DQ<9>

MEM_B_DQ<8>

MEM_B_DQ<7>

MEM_B_DQ<6>

MEM_B_DQ<5>

MEM_B_DQ<4>

MEM_B_DQ<3>

MEM_B_DQ<2>

MEM_B_DQ<1>

MEM_B_DQ<0>

MEM_B_DQ<28> MEM_B_DQ<29> MEM_B_DQ<30>

MEM_B_DQ<44>

MEM_B_DQ<50>

MEM_B_DQ<49>

MEM_B_DQ<37>

MEM_B_DQ<17>

MEM_B_CLK_P<0>

MEM_B_CLK_N<0>

MEM_B_CLK_N<1>

MEM_B_CKE<0>

MEM_B_CKE<3>

MEM_B_CS_L<0>

MEM_B_ODT<0>

=MEM_B_WE_L =MEM_B_CAS_L

=MEM_B_BA<0> MEM_B_CAB<6>

=MEM_B_A<0> =MEM_B_A<1> =MEM_B_A<2> TP_LPDDR3_RSVD3 TP_LPDDR3_RSVD4 =MEM_B_A<5> =MEM_B_A<6> =MEM_B_A<7>

=MEM_B_A<9>

=MEM_B_A<8>

=MEM_B_A<10> =MEM_B_A<11> MEM_B_CAA<6> =MEM_B_A<13> =MEM_B_A<14> =MEM_B_A<15>

MEM_B_DQS_N<0>

MEM_B_DQS_N<2>

MEM_B_DQS_N<1>

MEM_B_DQS_N<3>

MEM_B_DQS_N<5>

MEM_B_DQS_N<4>

MEM_B_DQS_N<6> MEM_B_DQS_N<7>

MEM_B_DQS_P<1>

MEM_B_DQS_P<4>

MEM_B_DQS_P<3>

MEM_B_DQS_P<6>

MEM_B_DQS_P<5>

MEM_B_DQS_P<7>

MEM_A_CKE<1>

MEM_A_CLK_N<1> MEM_A_CLK_P<1>

MEM_A_CLK_P<0>

MEM_A_CKE<0>

MEM_A_CLK_N<0>

MEM_A_CKE<2> MEM_A_CKE<3>

MEM_A_ODT<0>

MEM_A_CS_L<0> MEM_A_CS_L<1>

=MEM_A_BA<0>

=MEM_A_CAS_L

=MEM_A_WE_L

=MEM_A_RAS_L

MEM_A_CAB<6> =MEM_A_BA<2>

=MEM_A_A<0>

TP_LPDDR3_RSVD1

=MEM_A_A<2>

=MEM_A_A<1>

=MEM_A_A<5>

TP_LPDDR3_RSVD2

=MEM_A_A<6> =MEM_A_A<7>

=MEM_A_A<15>

=MEM_A_A<14>

=MEM_A_A<8>

=MEM_A_A<10>

=MEM_A_A<9>

=MEM_A_A<11> MEM_A_CAA<6> =MEM_A_A<13>

MEM_A_DQS_N<0>

MEM_A_DQS_P<0> MEM_A_DQS_P<1>

MEM_A_DQS_N<1> MEM_A_DQS_N<2> MEM_A_DQS_N<3> MEM_A_DQS_N<4>

MEM_A_DQS_N<6>

MEM_A_DQS_N<5>

MEM_A_DQS_P<5> MEM_A_DQS_P<6>

MEM_A_DQS_P<3> MEM_A_DQS_P<4>

MEM_A_DQS_P<2>

CPU_DIMM_VREFCA CPU_DIMMA_VREFDQ CPU_DIMMB_VREFDQ

MEM_B_CKE<2>

MEM_B_CLK_P<1>

MEM_B_CKE<1>

MEM_B_CS_L<1>

=MEM_B_BA<2>

MEM_B_DQS_P<0>

MEM_B_DQS_P<2>

=MEM_B_RAS_L

<SCH_NUM>

7 OF 120

7 OF 73

VCC

VCCST

RSVD

RSVD RSVD

RSVD

RSVD_TP

VSS

PWR_DEBUG*

VSS

VCC_SENSE

RSVD

VCC RSVD

VDDQ VDDQ

VDDQ

RSVD

VCC

VCC VCC VCC

VCC VCC

VCC VCC VCC

VCC

VCC VCC VCC

VCC VCC

VCC

VCC VCC

VCC

VCC VCC

VCC

VCC VCC VCC

VCC VCC

VCC VCC VCC

VCC

VCC VCC VCC

VCC VCC

VCC

VCC VCC

VCC VCC VCC

VCC VCC

VCC

VCC VCC

VCC VCC VCC

VCC VCC

VCC

VDDQ

VCCIOA_OUT RSVD RSVD

VIDALERT*

RSVD

VIDSOUT

VIDSCLK

VR_EN

VCCST_PWRGD

VR_READY

VCCIO_OUT

RSVD

HSW ULT POWER

SYM 12 OF 19

OUT

IN

NC NC

NC

VCCHSIO VCCHSIO VCCHSIO

VCCIO VCCIO

VCCUSB3PLL

VCCSATA3PLL

VCCAPLL VCCAPLL VCCAPLL

DCPSUS3

VCCHDA

DCPSUS2

VCCSUS3 VCCSUS3

VCC3 VCC3

VCCDSW3_3

VCC1P05 VCC1P05

VCCCLK

VCCACLKPLL

VCCSUS3

VCCIO

VCCAPLL

DCPSUS4

VCCSUS3

VCCRTC

DCPRTC

VCCSPI

VCCASW

VCC1P05 VCC1P05

VCC1P05

DCPSUSBYP DCPSUSBYP

VCCASW VCCASW VCCASW

DCPSUS1

VCC3

VCCTS1_5

VCCSDIO

SUS OSCILLATOR

SERIAL IO

THERMAL SENSOR

SYM 13 OF 19

USB2

LPT LP POWER

CORE

SPI RTC

HSIO

OPI

USB3

AZALIA/HDA

VRM/USB2/AZALIA

GPIO/LCC

ICC

NC

BI

NC NC

IN OUT IN

NC NC NC

NC

OUT

NC

NC NC

NC

NC NC NC

IN

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

HSW-ULT current estimates from Haswell Mobile ULT Processor EDS vol 1, doc #502406, v0.9.

Note [1] current numbers from clarification email, from Srini, dated 9/10/2012 2:11pm.

LPT-LP current estimates from Lynx Point-LP PCH EDS, doc #503118, v1.0.

R0810.2: R0800.2:

to avoid any extraneous connections.

NOTE: Aliases not used on CPU supply outputs

R0802.2:

Max load: 300mA

VCCCLK: 200mA Max

1499mA Max[1]

VCCCLK: 200mA Max

57mA Max

1838mA Max

WF: RSVD on Sawtooth Peak rev 1.0

41mA Max

59mA Max[1]

0.3mA Max[1]

29mA Max[1]

185mA Max[1]

473mA Max[1]

40mA Max[1]

1mA Max[1]

3.3mA Max[1] 213mA Max[1]

1.1A Max (LPDDR3: 1.2V)

1.4A Max (DDR3: 1.5-1.35V)

32A Max

???mA Max

18mA Max

11mA Max

Powered in DeepSx

31mA Max

3mA Max

17mA Max

42mA Max

Max load: 300mA

114mA Max

P62

D63

C59

F60

L63

N63

L62

AY50

AY44

AY40

AY35

AR48

AP43

AN33

AJ37

AJ33

AJ31

AH26

B59

AE23

AE22

AC22

E20

A59

W57

U57

E63

P57

M57

M23

L22

K57

K23

J23

H23

G57

G55

G53

G51

G49

G47

G45

G43

G41

G39

G37

G35

G33

G31

G29

G27

G25

G23

F56

F52

F48

F44

F40

F36

F32

F28

F24

E57

E55

E53

E51

E49

E47

E45

E43

E41

E39

E37

E35

E33

E31

E29

E27

E25

E23

C56

C52

C48

C44

C40

C36

C32

C28

C24

AG57

AD57

AB57

F59

V59

U59

P61

P60

N61

N59

T59

N58

L59 J58

AG58

AE60

AE59

AD60 AD59

AD23

AC59

AC58

AB23

AA59

AA23

H59

U0500

OMIT_TABLE

2C+GT2

HASWELL-ULT

BGA-TSP

CRITICAL

2

1

R0802

PLACE_NEAR=U0500.L63:2.54mm

1/20W

1%

130

MF 201

49 65

16

2

1

R0860

1/20W

100

PLACE_NEAR=U0500.C50:50.8mm

MF

201

5%

B18

J15

AH11

AE21

AE20

AC9 AA9

Y8

U8 T9

B11

AG10

P9

N8

AG17

AG16

M9

L10

K9

AH14

AH10

V21

T21

R21

M20

K18

J17

AG8

AG14 AG13

AF9

AE9

Y20

W21

AC20

AA21

A20

W9

V8

K16

K14

K19

J18

J11

H15

H11

AF22

AE8

AG20

AG19

AB8

J13

AH13

AD8

AD10

AE7

U0500

CRITICAL

OMIT_TABLE

HASWELL-ULT

2C+GT2

BGA-TSP

49 65

16 17

17 49

49 65

2

1

C0899

BYPASS=R0899:U0500:2.54mm

402

CERM

1UF

10%

6.3V

21

R0899

1%

MF-LF

5.11

PLACE_NEAR=U0500.AG19:2.54mm

1/20W

201

49 65

2

1

C0895

0.1UF

CERM 402

10V

20%

BYPASS=U0500.AE7:6.35mm

2

1

C0892

402

CERM

10V

20%

0.1UF

BYPASS=U0500.AG10:6.35mm

2

1

C0891

BYPASS=U0500.AG10:6.35mm

0.1UF

402

CERM

10V

20%

2

1

C0890

BYPASS=U0500.AG10:6.35mm

1UF

402

CERM

6.3V

10%

21

R0811

MF

1/20W

0201

0

5%

21

R0812

MF

1/20W

0201

0

5%

21

R0810

201

1/20W

PLACE_NEAR=U0500.L62:38.1mm

43

5% MF

2

1

R0800

PLACE_NEAR=R0810.1:2.54mm

75

1/20W

MF

1%

201

SYNC_MASTER=J43_MLB

SYNC_DATE=10/02/2012

CPU/PCH POWER

PP3V3_SUS

PPVOUT_S0_PCH_DCPRTC

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

PP3V3_S0

PP1V05_S0

PP3V3_S0

PP1V05_S0

PP1V5_S0

PP3V3_SUS

PP1V05_S0

PPVRTC_G3H

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 mm

PPVOUT_S5_PCH_DCPSUSBYP

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

PPVOUT_S5_PCH_DCPSUSBYP_R

PP1V05_S0SW_PCH_VCCSATA3PLL

PP1V05_S0SW_PCH_VCCUSB3PLL

PP1V05_S0

PP3V3_S0

PP1V5_S0SW_AUDIO_HDA

PP1V05_S0_PCH_VCCACLKPLL

PP1V05_S0_PCH_VCCAPLL_OPI

PP1V05_S0SW_PCH_HSIO

PP3V3_S5

PP1V05_S0

PP1V05_S0_PCH_VCC_ICC

CPU_VIDSOUT

CPU_VIDALERT_L

CPU_VIDSCLK

TP_CPU_RSVD_N61

TP_CPU_RSVD_N59

TP_CPU_RSVD_P61

TP_CPU_RSVD_P60

CPU_PWR_DEBUG

CPU_VCCSENSE_P

PPVCC_S0_CPU

PPVMEMIO_S0_CPU

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm

PPVCOMP_S0_CPU

PP1V05_S0

CPU_VR_EN

PP1V05_S0

CPU_VCCST_PWRGD

TP_PPVCCIO_S0_CPU

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

CPU_VIDALERT_R_L

CPU_VR_READY

CPU_VIDSCLK_R CPU_VIDSOUT_R

8 OF 73

8 OF 120

<SCH_NUM>

8

11 14 18 44 55 56 57 60 62

8

11 14 18 44 55 56 57 60 62

8

11 14 18 44 55 56 57 60 62

8

11 12 13 15 17 18 27 30 34 36

37 38 39 40 41 42 43 54 57 59

60 62 63 72

6 8

11 15 16 17 27 36 40 49 53

56 57 60 62

8

11 12 13 15 17 18 27 30 34 36

37 38 39 40 41 42 43 54 57 59

60 62 63 72

6 8

11 15 16 17 27 36 40 49 53

56 57 60 62

55 56 57 60 62

8

11 14 18 44 55 56 57

60 62

6 8

11 15 16 17 27 36 40

49 53 56 57 60 62

6 8

11 15 16 17 27 36 40

49 53 56 57 60 62

12 13 17 60 62

11 12

11 14

6 8

11 15 16 17 27 36 40 49 53

56 57 60 62

8

11 12 13 15 17 18 27 30 34 36 37 38 39 40 41 42

43 54 57 59 60 62 63 72

11 17 56

11 12

11

11 56 60

11 13 15 16 17 18 28 29 40 52 55 56 57 58 60 62 72

6 8

11 15 16 17 27 36 40

49 53 56 57 60 62

11

8

10 40 50 60 62

8

10 40 50 60 62

10 40

5

6 8

11 15 16 17 27 36 40 49

53 56 57 60 62

6 8

11 15 16 17 27 36 40 49

53 56 57 60 62

SYM 14 OF 19

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS VSS VSS

VSS

VSS VSS VSS

VSS VSS

VSS VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

OUT

SYM 15 OF 19

VSS

VSS VSS VSS

VSS

VSS VSS VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS VSS

VSS VSS VSS VSS VSS

VSS

VSS VSS VSS

VSS

VSS VSS VSS VSS

VSS

VSS VSS VSS VSS

VSS

VSS VSS VSS

SYM 16 OF 19

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS VSS

VSS

VSS VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS VSS VSS VSS VSS

VSS

VSS_SENSE

VSS

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AP20

AP17

AP10

AN7

AN63

AN60

AN52

AN51

AN49

AN48

AN46

AN45

AN43

AN42

AN40

AN39

AN36

AN35

AN32

AN31

AN23

AN17

AM52

AM31

AM23

AM17

AM1

AL61

AL60

AL57

AL54

AL52

AL51

AL46

AL45

AL40

AL39

AL36

AL33

AL31

AL29

AL26

AL23

AL22

AL20

AL17

AL13

AL10

AK52

AK3

AK23

AJ63

AJ60

AJ58

AJ56

AJ54

AJ52

AJ50

AJ47

AJ45

AJ43

AJ41

AJ39

AJ35

AJ29

AJ27

AJ25

AJ23

AJ14

AJ13

AH57

AH55

AH53

AH51

AH49

AH44

AH42

AH40

AH38

AH36

AH34

AH32

AH30

AH28

AH24

AH22

AH20

AH19

AH17

AG63

AG62

AG61

AG60

AG23

AG21

AG11

AG1

AF18

AF17

AF15

AF14

AF12

AF11

AE58

AE5

AE10

AD63

AD3

AD21

AC61

AB7

AB22

AB20

AB10

AA58

AA1

A56

A52

A48

A44

A40

A36

A32

A28

A24

A18

A14

A11

U0500

2C+GT2

BGA-TSP

HASWELL-ULT

OMIT_TABLE

CRITICAL

2

1

R0960

201

MF

1/20W

100

5%

PLACE_NEAR=U0500.E62:50.8mm

49 65

D31

D30

D29

D27

D26

D25

D23

D21

D2

D18

D14

D12

C57

C39

C38

C27

C25

C20

C18

C14

C11

B60

B56

B52

B48

B44

B40

B4

B36

B32

B28

B26

B24

B20

AY6

AY59

AY57

AY53

AY51

AY4

AY33

AY30

AY26

AY24

AY22

AY18

AY16

AY11

AW60

AW59

AW51

AW50

AW47

AW44

AW42

AW40

AW4

AW37

AW35

AW33

AW24

AW16

AV8

AV59

AV55

AV51

AV49

AV46

AV43

AV41

AV39

AV36

AV34

AV33

AV28

AV24

AV20

AV16

AV14

AU59

AU57

AU55

AU53

AU51

AU33

AU30

AU28

AU26

AU24

AU22

AU20

AU18

AU16

AU1

AT63

AT62

AT61

AT49

AT46

AT43

AT42

AT40

AT37

AT35

AT13

AR52

AR5

AR49

AR43

AR39

AR33

AR31

AR23

AR17

AR15

AR11

AP57

AP54

AP52

AP48

AP39

AP38

AP31

AP3

AP29

AP26

AP23

AP22

U0500

2C+GT2

BGA-TSP

HASWELL-ULT

OMIT_TABLE

CRITICAL

Y63

Y59

Y10

W22

W20

V7

V58

V3

V23

V10

U9

U61

U22

U20

T58

T1

E62

R8

R22

R10

P63

P59

N3

N10

M22

L7

L61

L58

L20

L18

L17

L15

L13

K12

K1

J63

J59

J22

J10

H57

H17

H13

G8

G6

G5

G3

G22

G18

F61

F58

F54

F50

F46

F42

F38

F34

F30

F26

F20

E17

E11

D8

D62

D59

D57

D55

D54

D53

D51

D50

D5

D49

D47

D46

D45

D43

D42

D41

D39

D38

D37

D35

D34

D33

AH46

AH16

U0500

2C+GT2

BGA-TSP

HASWELL-ULT

OMIT_TABLE

CRITICAL

CPU/PCH GROUNDS

SYNC_MASTER=J43_MLB

SYNC_DATE=10/02/2012

CPU_VCCSENSE_N

<SCH_NUM>

9 OF 120

9 OF 73

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

CPU VDDQ DECOUPLING

CPU VCC Decoupling

Intel recommendation (Table 5-1): 23x 22uF 0805 stuff, 7x 22uF 0805 nostuff Apple implementation : 18x 10uF 0402 mirrored stuff, 1x 470uF stuff, 50x 10uF mirrored no stuff, 50x 10uF single sided no stuff

Intel recommendation (Table 5-4): 4x 2.2uF 0402, 6x 10uF 0603

2x Bulk nostuff per Harris Beach v1.0 schematic

Apple implementation : 4x 2.2uF 0402, 6x 10uF 0402, 2x 270uF B2 no stuff

All Intel recommendations from Intel doc #503160 Shark Bay Ultrabook Platform Power Delivery Design Guide Rev 1.0 unless stated otherwise

2

1

C1000

NO STUFF

4V X6S 0402

20%

10UF

2

1

C1050

10UF

0402-1

CERM-X5R

6.3V

20%

2

1

C1051

10UF

CERM-X5R

6.3V

20%

0402-1

2

1

C1052

CERM-X5R 0402-1

10UF

6.3V

20%

2

1

C1053

10UF

0402-1

CERM-X5R

6.3V

20%

2

1

C1054

CERM-X5R

20%

0402-1

10UF

6.3V

2

1

C1055

10UF

0402-1

CERM-X5R

6.3V

20%

2

1

C1040

6.3V CERM 402-LF

2.2UF

20%

2

1

C1041

402-LF

6.3V CERM

2.2UF

20%

2

1

C1042

6.3V CERM 402-LF

20%

2.2UF

2

1

C1043

6.3V

20%

2.2UF

402-LF

CERM

2

1

C1060

TANT

2V

20%

270UF

CASE-B2-SM

2

1

C1061

NO STUFF

CASE-B2-SM

TANT

2V

20%

270UF

2

1

C1001

20% 4V X6S 0402

NO STUFF

10UF

2

1

C1002

4V X6S

10UF

20%

NO STUFF

0402

2

1

C1003

0402

4V X6S

10UF

20%

NO STUFF

2

1

C1004

0402

4V X6S

10UF

20%

NO STUFF

2

1

C1005

NO STUFF

10UF

0402

4V X6S

20%

2

1

C1006

0402

4V X6S

10UF

20%

NO STUFF

2

1

C1007

10UF

0402

4V X6S

20%

NO STUFF

2

1

C1008

0402

4V X6S

10UF

20%

NO STUFF

2

1

C1009

NO STUFF

20%

0402

4V X6S

10UF

2

1

C1010

0402

4V X6S

10UF

20%

NO STUFF

2

1

C1011

0402

4V X6S

10UF

20%

NO STUFF

2

1

C1012

NO STUFF

0402

4V X6S

10UF

20%

2

1

C1013

10UF

0402

4V X6S

20%

NO STUFF

2

1

C1014

0402

4V X6S

10UF

20%

NO STUFF

2

1

C1015

4V X6S

20%

10UF

0402

NO STUFF

2

1

C1016

4V

20%

0402

X6S

NO STUFF

10UF

2

1

C1017

20%

10UF

X6S

4V 0402

NO STUFF

2

1

C1018

4V

20%

0402

X6S

10UF

NO STUFF

2

1

C1019

20% 4V X6S

10UF

0402

NO STUFF

2

1

C1020

20% X6S

4V

10UF

0402

NO STUFF

2

1

C1021

0402

4V X6S

10UF

20%

NO STUFF

2

1

C1084

4V X6S

20%

10UF

0402

CRITICAL

2

1

C1083

4V X6S

20%

10UF

0402

CRITICAL

2

1

C1082

4V X6S

20%

10UF

0402

NO STUFF

2

1

C1081

20%

0402

X6S

4V

10UF

NO STUFF

2

1

C1080

NO STUFF

4V X6S

10UF

20%

0402

2

1

C1079

4V X6S

20%

10UF

0402

NO STUFF

2

1

C1078

NO STUFF

10UF

20% X6S

4V 0402

2

1

C1077

20% X6S

4V

10UF

0402

CRITICAL

2

1

C1076

4V X6S

10UF

20%

0402

CRITICAL

2

1

C1075

NO STUFF

4V X6S

10UF

20%

0402

2

1

C1074

10UF

20% 4V X6S 0402

NO STUFF

2

1

C1073

NO STUFF

X6S

4V

20%

0402

10UF

2

1

C1072

10UF

X6S

4V

20%

0402

NO STUFF

2

1

C1071

4V X6S

10UF

20%

0402

CRITICAL

2

1

C1070

CRITICAL

0402

20%

10UF

X6S

4V

2

1

C1097

0402

20%

10UF

X6S

4V

CRITICAL

2

1

C1096

0402

4V X6S

20%

10UF

NO STUFF

2

1

C1095

0402

20%

10UF

X6S

4V

NO STUFF

2

1

C1094

0402

20%

10UF

X6S

4V

NO STUFF

2

1

C1093

10UF

0402

20% X6S

4V

NO STUFF

2

1

C1092

0402

10UF

20% X6S

4V

CRITICAL

2

1

C1091

CRITICAL

0402

4V

20% X6S

10UF

2

1

C1090

0402

20%

10UF

X6S

4V

NO STUFF

2

1

C1089

0402

20%

10UF

X6S

4V

NO STUFF

2

1

C1088

0402

20%

10UF

X6S

4V

NO STUFF

2

1

C1087

0402

20%

10UF

X6S

4V

CRITICAL

2

1

C1086

10UF

0402

20% 4V

CRITICAL

X6S

2

1

C1085

10UF

0402

20% X6S

4V

CRITICAL

2

1

C1038

NO STUFF

0402

10UF

20% 4V X6S

2

1

C1037

NO STUFF

0402

4V X6S

10UF

20%

2

1

C1036

NO STUFF

4V 0402

X6S

20%

10UF

2

1

C1035

NO STUFF

0402

20%

10UF

4V X6S

2

1

C1034

NO STUFF

X6S 0402

20% 4V

10UF

2

1

C1033

NO STUFF

0402

20% 4V X6S

10UF

2

1

C1032

0402

10UF

20% X6S

4V

NO STUFF

2

1

C1029

0402

20% 4V X6S

NO STUFF

10UF

2

1

C109A

0402

10UF

20% 4V X6S

NO STUFF

2

1

C1099

NO STUFF

0402

X6S

20%

10UF

4V

2

1

C1098

NO STUFF

0402

4V X6S

20%

10UF

2

1

C107B

NO STUFF

20% X6S

4V

10UF

0402

2

1

C107A

4V

20%

10UF

X6S 0402

NO STUFF

2

1

C1069

NO STUFF

10UF

X6S

4V

20%

0402

2

1

C1068

NO STUFF

0402

X6S

4V

10UF

20%

2

1

C108F

NO STUFF

20% 4V X6S 0402

10UF

2

1

C1067

NO STUFF

0402

4V X6S

20%

10UF

2

1

C108E

NO STUFF

20% 4V X6S

10UF

0402

2

1

C1066

NO STUFF

0402

10UF

20% 4V X6S

2

1

C108D

NO STUFF

X6S

4V

20%

0402

10UF

2

1

C108C

NO STUFF

X6S

4V

20%

10UF

0402

2

1

C1065

NO STUFF

0402

10UF

4V

20% X6S

2

1

C1028

NO STUFF

10UF

0402

4V X6S

20%

2

1

C1027

10UF

0402

4V X6S

20%

NO STUFF

2

1

C1049

0402

NO STUFF

4V

20% X6S

10UF

2

1

C1048

0402

4V

20% X6S

10UF

NO STUFF

2

1

C1026

10UF

4V X6S 0402

20%

NO STUFF

2

1

C1047

0402

X6S

10UF

4V

20%

NO STUFF

2

1

C1025

NO STUFF 10UF

20% 4V X6S 0402

2

1

C1024

NO STUFF 10UF

0402

4V X6S

20%

2

1

C1046

NO STUFF

0402

X6S

10UF

4V

20%

2

1

C1045

NO STUFF

0402

10UF

4V

20% X6S

2

1

C1023

NO STUFF

0402

4V X6S

10UF

20%

2

1

C1022

10UF

NO STUFF

0402

20% 4V X6S

2

1

C1044

NO STUFF

0402

20% X6S

4V

10UF

2

1

C1039

NO STUFF

0402

10UF

X6S

4V

20%

2

1

C1064

NO STUFF

X6S 0402

10UF

20% 4V

2

1

C108B

X6S

20% 4V

0402

10UF

NO STUFF

2

1

C1063

0402

X6S

4V

10UF

20%

NO STUFF

2

1

C108A

NO STUFF

20% X6S

4V

10UF

0402

2

1

C1062

10UF

20% 4V X6S

NO STUFF

0402

2

1

C109F

NO STUFF

X6S

10UF

4V

20%

0402

2

1

C109E

NO STUFF

X6S

4V

20%

10UF

0402

2

1

C1059

NO STUFF 10UF

0402

20% 4V X6S

2

1

C1058

NO STUFF

0402

10UF

4V X6S

20%

2

1

C109D

NO STUFF 10UF

20% 4V X6S 0402

2

1

C1057

NO STUFF

4V 0402

X6S

10UF

20%

2

1

C109C

X6S

NO STUFF

10UF

20% 4V

0402

2

1

C1056

NO STUFF

0402

10UF

4V X6S

20%

2

1

C109B

X6S

4V 0402

10UF

20%

NO STUFF

3 2

1

C1031

470UF-0.0045OHM

SM

2.5V POLY-TANT

20%

CRITICAL

2

1

C1030

0402

4V X6S

10UF

20%

NO STUFF

2

1

C104C

10UF

0402

4V X6S

20%

NO STUFF

2

1

C104D

20% X6S

4V

CRITICAL

10UF

0402

2

1

C104E

20%

10UF

X6S

4V 0402

NO STUFF

2

1

C104F

20%

10UF

X6S

4V 0402

CRITICAL

2

1

C106A

20%

10UF

X6S

4V 0402

CRITICAL

2

1

C106B

20%

10UF

X6S

4V 0402

NO STUFF

2

1

C106C

20%

10UF

X6S

4V 0402

NO STUFF

2

1

C106D

0402

4V X6S

10UF

20%

NO STUFF

2

1

C106E

0402

4V X6S

10UF

20%

NO STUFF

2

1

C105A

20%

10UF

X6S

4V 0402

NO STUFF

2

1

C105B

20%

10UF

X6S

4V 0402

CRITICAL

2

1

C105C

20%

10UF

X6S

4V 0402

CRITICAL

2

1

C105D

20%

10UF

X6S

4V 0402

NO STUFF

2

1

C105E

0402

4V X6S

10UF

20%

NO STUFF

2

1

C105F

CRITICAL

0402

4V X6S

10UF

20%

2

1

C104A

NO STUFF

10UF

0402

4V X6S

20%

2

1

C104B

NO STUFF

0402

4V X6S

10UF

20%

SYNC_DATE=01/11/2013

SYNC_MASTER=LABEL_J41

CPU Decoupling

PPVCC_S0_CPU

PPVMEMIO_S0_CPU

10 OF 73

<SCH_NUM>

10 OF 120

8

40 50 60 62

8

40

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

??mA Max

PCH OPI VCCAPLL FILTER/BYPASS

57mA Max

31mA Max

??mA Max

42mA Max83mA Max

41mA Max

PCH VCCDSW3_3 BYPASS

PCH VCCSUS3_3 BYPASS

(PCH 1.05V PCIe/SATA/USB3 PWR)

PCH VCCHSIO BYPASS

PCH VCCASW BYPASS (PCH 1.05V ME CORE PWR)

(PCH 1.05V OPI PLL PWR)

(PCH 1.05V CLK PWR)

PCH VCCCLK BYPASS

PCH VCC3_3 BYPASS (PCH 3.3V GPIO/LPC PWR)

PCH VCC3_3 BYPASS (PCH 3.3V THERMAL PWR)

(PCH 1.05V USB2 PWR)

PCH VCCIO BYPASS

(PCH 1.05V VCCCLK PWR)

PCH VCCCLK FILTER/BYPASS

PCH VCCACLKPLL FILTER/BYPASS (PCH 1.05V ACLK PLL PWR)

(PCH 3.3V DSW PWR)

PCH VCCSUS3_3 BYPASS (PCH 3.3V SUSPEND PWR)

PCH VCCSPI BYPASS (PCH 3.3V SPI PWR)

(PCH 3.3V SUSPEND RTC PWR)

(PCH 3.3V/1.5V HDA PWR)

PCH VCCSDIO BYPASS (PCH 3.3V/1.8V SDIO PWR)

PCH VCCSUSHDA BYPASS

LPT-LP current estimates from Lynx Point-LP PCH EDS, doc #503118, v1.0 as well as from clarification email, from Srini, dated 9/10/2012 2:11pm.

PCH VCCSATA3PLL FILTER/BYPASS

(PCH 1.05V USB3 PLL PWR)

PCH VCCUSB3PLL FILTER/BYPASS

(PCH 1.05V SATA3 PLL PWR)

PCH VCC BYPASS (PCH 1.05V CORE PWR)

2

1

C1202

BYPASS=U0500.Y8:6.35mm

CERM

402

0.1UF

20% 10V

NO STUFF

21

L1280

0603

2.2UH-240MA-0.221OHM

CRITICAL NO STUFF

21

R1280

0

MF-LF

402

5%

1/16W

2

1

C1295

0805-1

47UF

20%

4V

CERM-X5R

BYPASS=U0500.B18:12.7mm

2

1

C1296

0805-1

47UF

20%

4V

CERM-X5R

BYPASS=U0500.B18:12.7mm

NO STUFF

2

1

C1290

BYPASS=U0500.B11:12.7mm

CERM-X5R

4V

20%

47UF

0805-1

2

1

C1291

0805-1

47UF

20%

4V

CERM-X5R

BYPASS=U0500.B11:12.7mm

NO STUFF

2

1

C1280

BYPASS=U0500.AA21:12.7mm

0805-1

47UF

20%

4V

CERM-X5R

NO STUFF

2

1

C1281

CERM-X5R

4V

20%

47UF

BYPASS=U0500.AA21:12.7mm

0805-1

NO STUFF

2

1

C1275

BYPASS=U0500.J18:12.7mm

4V

20%

47UF

0805-1

CERM-X5R

2

1

C1276

0805-1

47UF

20%

4V

CERM-X5R

BYPASS=U0500.J18:12.7mm

2

1

C1270

CERM-X5R

BYPASS=U0500.A20:12.7mm

0805-1

47UF

20%

4V

2

1

C1271

CERM-X5R

4V

20%

47UF

0805-1

BYPASS=U0500.A20:12.7mm

2

1

C1200

6.3V

10%

402

CERM

1UF

BYPASS=U0500.AH10:6.35mm

NO STUFF

2

1

C1210

BYPASS=U0500.AH14:6.35mm

6.3V

10%

1UF

CERM

402

2

1

C1214

BYPASS=U0500.K14:6.35mm

CERM

402

10V

20%

0.1UF

2

1

C1206

BYPASS=U0500.AH11:6.35mm

402

CERM

6.3V

1UF

10%

2

1

C1264

402

CERM

BYPASS=U0500.AG16:6.35mm

1UF

10%

6.3V

2

1

C1261

1UF

CERM

402

10%

6.3V

BYPASS=U0500.L10:6.35mm

2

1

C1262

0402-1

20%

10UF

CERM-X5R

BYPASS=U0500.M9:6.35mm

6.3V

2

1

C1266

6.3V CERM

402

1UF

10%

BYPASS=U0500.J17:6.35mm

2

1

C1255

BYPASS=U0500.J11:12.7mm

6.3V

20% 603

X5R

10UF

2

1

C1250

BYPASS=U0500.AE9:12.7mm

X5R-CERM-1

6.3V

20%

22UF

603

NO STUFF

2

1

C1256

BYPASS=U0500.J11:6.35mm

6.3V 402

10%

1UF

CERM

2

1

C1257

1UF

BYPASS=U0500.AE8:6.35mm

6.3V

10% 402

CERM

2

1

C1251

BYPASS=U0500.AE9:6.35mm

6.3V

10%

402

CERM

1UF

2

1

C1267

6.3V CERM

402

1UF

10%

BYPASS=U0500.R21:6.35mm

2

1

C1204

X5R-CERM-1

6.3V

20%

22UF

603

BYPASS=U0500.AC9:12.7mm

2

1

C1212

22UF

20%

6.3V

X5R-CERM-1

BYPASS=U0500.V8:12.7mm

603

2

1

C1208

BYPASS=U0500.U8:6.35mm

402

CERM

6.3V

1UF

10%

2

1

C1260

BYPASS=U0500.K9:6.35mm

1UF

402

10%

6.3V CERM

2

1

C1277

10V

10%

402

X5R

1UF

BYPASS=U0500.J18:6.35mm

21

L1275

2.2UH-240MA-0.221OHM

0603

CRITICAL

2

1

C1297

10V

10% 402

X5R

1UF

BYPASS=U0500.B18:6.35mm

21

L1295

CRITICAL

0603

2.2UH-240MA-0.221OHM

2

1

C1292

10V

10% 402

X5R

1UF

BYPASS=U0500.B11:6.35mm

21

L1290

2.2UH-240MA-0.221OHM

CRITICAL

0603

21

R1275

0

1/16W

5%

402

MF-LF

2

1

C1272

1UF

X5R 402

10% 10V

BYPASS=U0500.A20:6.35mm

21

L1270

0603

CRITICAL

2.2UH-240MA-0.221OHM

21

R1270

5%

402

MF-LF

1/16W

0

2

1

C1282

1UF

X5R 402

10% 10V

BYPASS=U0500.AA21:6.35mm

SYNC_DATE=09/13/2012SYNC_MASTER=WILL_J43

PCH Decoupling

PP1V05_S0

PP3V3_SUS

PP3V3_S0

PP1V5_S0SW_AUDIO_HDA

PP3V3_S5

PP3V3_SUS

PP1V05_S0

PP3V3_S0

PP1V05_S0

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.2 MM

PP1V05_S0_PCH_VCCACLKPLL_R

PP1V05_S0

PP1V05_S0SW_PCH_HSIO

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.075 MM

MIN_LINE_WIDTH=0.2 MM

PP1V05_S0SW_PCH_VCCUSB3PLL

PP1V05_S0

PP1V05_S0SW_PCH_HSIO

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.075 MM

MIN_LINE_WIDTH=0.2 MM

PP1V05_S0SW_PCH_VCCSATA3PLL

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 MM

PP1V05_S0_PCH_VCC_ICC_R

MIN_NECK_WIDTH=0.2 MM

MIN_NECK_WIDTH=0.075 MM VOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 MM

PP1V05_S0_PCH_VCCACLKPLL

MIN_NECK_WIDTH=0.075 MM VOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 MM

PP1V05_S0_PCH_VCC_ICC

MIN_LINE_WIDTH=0.2 MM VOLTAGE=1.05V

MIN_NECK_WIDTH=0.075 MM

PP1V05_S0_PCH_VCCAPLL_OPI

11 OF 73

12 OF 120

<SCH_NUM>

6 8

11 15 16 17 27 36 40 49

53 56 57 60 62

8

11 14 18 44 55 56 57 60 62

8

11 12 13 15 17 18 27 30 34

36 37 38 39 40 41 42 43 54 57

59 60 62 63 72

8

17 56

8

13 15 16 17 18 28 29 40 52

55 56 57 58 60 62 72

8

11 14 18 44 55 56 57 60 62

8

11 14 18 44 55 56 57 60 62

6 8

11 15 16 17 27 36 40 49

53 56 57 60 62

8

11 12 13 15 17 18 27 30 34

36 37 38 39 40 41 42 43 54 57

59 60 62 63 72

8

11 12 13 15 17 18 27 30 34

36 37 38 39 40 41 42 43 54 57

59 60 62 63 72

6 8

11 15 16 17 27 36 40 49

53 56 57 60 62

6 8

11 15 16 17 27 36 40 49

53 56 57 60 62

8

11 56 60

8

14

6 8

11 15 16 17 27 36 40 49

53 56 57 60 62

8

11 56 60

8

12

8

12

8

IN IN

IN

OUT

BI

OUT

IN

NC NC

NC

IN

OUT

RSVD

HDA_DOCK_EN*/I2S1_TXD

HDA_BCLK/I2S0_SCLK

RTCX1 RTCX2

RTCRST*

INTVRMEN

INTRUDER*

SRTCRST*

HDA_RST*/I2S_MCLK

HDA_SYNC/I2S0_SFRM

HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD

HDA_SDO/I2S0_TXD

HDA_DOCK_RST*/I2S1_SFRM

I2S1_SCLK

SATA_RN0/PERN6_L3 SATA_RP0/PERP6_L3

SATA_TN0/PETN6_L3 SATA_TP0/PETP6_L3

SATA_RN1/PERN6_L2 SATA_RP1/PERP6_L2

SATA_TN1/PETN6_L2 SATA_TP1/PETP6_L2

SATA_RN2/PERN6_L1 SATA_RP2/PERP6_L1

SATA_TN2/PETN6_L1 SATA_TP2/PETP6_L1

SATA_RN3/PERN6_L0 SATA_RP3/PERP6_L0

SATA_TN3/PETN6_L0 SATA_TP3/PETP6_L0

SATA0GP/GPIO34 SATA1GP/GPIO35 SATA2GP/GPIO36 SATA3GP/GPIO37

SATA_IREF

PCH_TRST*

PCH_TDI

PCH_TCK

PCH_TDO

RSVD

PCH_TMS

JTAGX

RSVD

RSVD SATALED*

SATA_RCOMP

AUDIO

SYM 5 OF 19

SATA

JTAG

RTC

OUT

IN

OUT

IN

NC NC

OUT

CLKOUT_LPC_1

CLKOUT_LPC_0

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

PCIECLKRQ5*/GPIO23

PCIECLKRQ4*/GPIO22

CLKOUT_PCIE_N5 CLKOUT_PCIE_P5

PCIECLKRQ3*/GPIO21

CLKOUT_PCIE_P4

CLKOUT_PCIE_N4

PCIECLKRQ2*/GPIO20

CLKOUT_PCIE_P3

CLKOUT_PCIE_N3

PCIECLKRQ1*/GPIO19

CLKOUT_PCIE_P2

CLKOUT_PCIE_N2

PCIECLKRQ0*/GPIO18

CLKOUT_PCIE_P1

CLKOUT_PCIE_N1

CLKOUT_PCIE_N0

XTAL24_OUT

XTAL24_IN

CLKOUT_PCIE_P0

TESTLOW

TESTLOW TESTLOW

DIFFCLK_BIASREF

RSVD

SYM 6 OF 19

CLOCK SIGNALS

OUT

OUT OUT

IN IN

IN

OUT OUT

OUT

IN

OUT

OUT OUT

IN

OUT OUT

IN

NC NC

OUT

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(IPD)

SSD Lane 0

SSD Lane 2

PCIe Port assignments:

SSD Lane 3

(IPD-PWROK)

(IPD-PLTRST#)

(IPU)

(IPD)

Secondary HDD/SSD

Unused

Primary HDD/SSD

Reserved: ODD

SATA Port assignments:

SSD Lane 1

(IPD-PLTRST#)

(IPU)

16 62 67

21

R1345

MF 2015%

1/20W

100K

21

R1375

100K

MF5%

1/20W

201

16

21

R1343

1/20W

MF 2015%

100K

16 62 67

16

59 63 67

21

R1312

PLACE_NEAR=U0500.AU8:1.27mm

1/20W

5% MF33201

21

R1311

201

PLACE_NEAR=U0500.AV11:1.27mm

MF5%

1/20W

33

59 63 67

21

R1310

PLACE_NEAR=U0500.AW8:1.27mm

1/20W

5% 201MF

33

17

2

1

R1302

MF

201

5%

1/20W

330K

2

1

R1301

1M

MF 201

5% 1/20W

2

1

C1300

10V

10% 402

X5R

1UF

2

1

R1300

1/20W

5%

201

MF

20K

2

1

C1303

10V

10%

1UF

402

X5R

2

1

R1303

5%

201

20K

1/20W MF

6

16 62 65

2

1

R1370

PLACE_NEAR=U0500.C12:2.54mm

1% 1/20W

3.01K

MF 201

30 65

AV6

U3

D17

C15

B17

A15

C17

B14

A17

B15

E5

H6

H8

H5

F5

J6

J8

J5

C12

A12

AC1

V6

U1

V1

AY5

AW5

AU7

L11

K10

AV2

AL11

AC4

AU62

AD62

AE61

AD61

AE62

AE63

AV7

AU6

AY8

AV11

AU11

AU12

AY10

AU8

AV10

AW10

AW8

U0500

BGA-TSP

HASWELL-ULT

2C+GT2

OMIT_TABLE

CRITICAL

30 65

30 62 65

30 65

30 62 65

30 65

B25

A25

C35 C34

AL8

AK8

M21

K21

T2

U5

N1

AD1

Y5

U2

C26

A37

B39

C37

B42

A41

C42

B37

A39

B38

C41

B41

C43

AP15

AN15

A35

B35

U0500

BGA-TSP

HASWELL-ULT

2C+GT2

CRITICAL

OMIT_TABLE

30 65

30 62 65

12 29

29 62 67

59 63 67

12 31

32 67

25 67

12 27

30 62 65

12 30

2

1

R1380

1/20W

PLACE_NEAR=U0500.C26:2.54mm

1%

201

MF

3.01K

17 67

21

R1390

10K

MF

1/20W

5% 201

21

R1391

MF 201

1/20W

10K

5%

21

R1392

201MF

1/20W

10K

5%

21

R1393

5%

10K

1/20W

MF 201

17

21

R1313

201

PLACE_NEAR=U0500.AU11:1.27mm

33

1/20W

5% MF

21

R1341

1/20W

5% 201MF

100K

21

R1344

100K

MF 2015%

1/20W

21

R1340

1/20W

5% 201MF

100K

21

R1342

5% MF 201

1/20W

100K

PCH Audio/JTAG/SATA/CLK

SYNC_DATE=12/17/2012SYNC_MASTER=WILL_J43

SSD_CLKREQ_L

PCIE_CLK100M_SSD_P

PCIE_CLK100M_SSD_N

TBT_CLKREQ_L

PCIE_CLK100M_TBT_P

PCIE_CLK100M_TBT_N

PCIE_CLK100M_AP_P AP_CLKREQ_L

PCIE_CLK100M_AP_N

CAMERA_CLKREQ_L

PCIE_CLK100M_CAMERA_P

PCIE_CLK100M_CAMERA_N

ENETSD_CLKREQ_L

TP_PCIE_CLK100M_ENETSDP

TP_PCIE_CLK100M_ENETSDN

NC_PCIE_CLK100M_FWN

FW_CLKREQ_L

NC_PCIE_CLK100M_FWP

PCH_SATA_RCOMP

PCH_CLK24M_XTALOUT

PCH_CLK24M_XTALIN

HDA_BIT_CLK_R

HDA_SYNC_R

HDA_SDIN0

NC_RTC_CLK32K_RTCX2

TP_PCH_I2S1_TXD TP_PCH_I2S1_SFRM

XDP_PCH_TCK

TP_PCH_I2S1_SCLK

XDP_CPUPCH_TRST_L

SSD_CLKREQ_L

TBT_CLKREQ_L

AP_CLKREQ_L FW_CLKREQ_L

CAMERA_CLKREQ_L

ENETSD_CLKREQ_L

PCH_SATALED_L

NC_HDA_SDIN1

XDP_SSD_PCIE0_SEL_L

PCH_INTRUDER_L

PCIE_SSD_D2R_P<0>

PCIE_SSD_D2R_N<0>

PCH_TESTLOW_C34

HDA_SDOUT_R

PCIE_SSD_R2D_C_N<2>

PCIE_SSD_R2D_C_N<3> PCIE_SSD_R2D_C_P<3>

PCIE_SSD_D2R_P<3>

PCIE_SSD_D2R_N<3>

PCIE_SSD_D2R_P<1>

PCIE_SSD_D2R_N<1>

PCIE_SSD_R2D_C_P<1>

PCIE_SSD_R2D_C_N<1>

TP_ITPXDP_CLK100MN TP_ITPXDP_CLK100MP

LPC_CLK24M_SMC_R

PCH_TESTLOW_AK8 PCH_TESTLOW_AL8

PCH_CLK32K_RTCX1

PCIE_SSD_R2D_C_P<0>

PCH_TESTLOW_C35

HDA_RST_R_L

PP3V3_S0

LPC_CLK24M_LPCPLUS_R

PCH_DIFFCLK_BIASREF

PCH_SATALED_L

PP1V05_S0_PCH_VCCACLKPLL

PPVRTC_G3H

PCH_INTVRMEN PCH_SRTCRST_L

XDP_PCH_TDO XDP_PCH_TMS

XDP_PCH_TDI

PCIE_SSD_R2D_C_N<0>

PP1V05_S0SW_PCH_VCCSATA3PLL

PCIE_SSD_D2R_N<2> PCIE_SSD_D2R_P<2>

PCIE_SSD_R2D_C_P<2>

XDP_SSD_PCIE3_SEL_L XDP_SSD_PCIE2_SEL_L XDP_SSD_PCIE1_SEL_L

PCH_JTAGX

HDA_SYNC

HDA_BIT_CLK

RTC_RESET_L

HDA_SDOUT

HDA_RST_L

12 OF 73

<SCH_NUM>

13 OF 120

12

62

12

62

67

12 30

12 27

12 29

12

12 31

12

62

17 67

67

8

11 13 15 17 18 27 30 34 36 37

38 39 40 41 42 43 54 57 59 60

62 63 72

12

8

11

8

13 17 60 62

8

11

IN

OUT

IN

OUT

IN

OUT

SLP_WLAN*/GPIO29

SLP_S0*

BATLOW*/GPIO72

ACPRESENT/GPIO31

PWRBTN*

SUSWARN*/SUSPWRDNACK/GPIO30

RSMRST*

PCH_PWROK

APWROK

SYS_RESET*

SUSACK*

PLTRST*

SYS_PWROK

DPWROK

DSWVRMEN

CLKRUN*/GPIO32

WAKE*

SLP_S5*/GPIO63

SUSCLK/GPIO62

SUS_STAT*/GPIO61

SLP_S4*

SLP_S3*

SLP_A*

SLP_SUS*

SLP_LAN*

SYSTEM POWER MANAGEMENT

SYM 8 OF 19

OUT

BI

IN

OUT

GPIO53

GPIO51

GPIO54

GPIO52

GPIO55

PME*

PIRQC*/GPIO79 PIRQD*/GPIO80

PIRQA*/GPIO77 PIRQB*/GPIO78

EDP_BKLEN

EDP_BKLCTL

EDP_HPD

DDPC_HPD

DDPC_AUXP

DDPB_AUXP

DDPB_HPD

DDPB_AUXN DDPC_AUXN

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPB_CTRLCLK

DDPB_CTRLDATA

EDP_VDDEN

SIDEBAND

eDP

DISPLAY

PCI

SYM 9 OF 19

OUT

BI BI

BI

OUT

IN

IN IN IN IN

OUT OUT OUT

OUT

IN

OUT

IN

NC

08

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SLP_S0# Isolation

SLP_S0# can be driven high outside of S0 U1420 ensures signal will only be high in S0.

(IPD-PLTRST#)

(IPU)

(IPD-DeepSx)

(IPD-PLTRST#)

(IPU)

R1400 kept for debug purposes.

57 62

13 18 35

37

15 16 18

13 17

16 17 35

17 35 62

13 40 57

13 17 18 35 57

AJ5

AC3

AG2

AV4

AE6

AK2

AG4

AM5

AP4

AP5

AJ6

AT4

AF3 AJ7

AL5

AW6

AL7

AG7

AY7

AW7

AV5

V5

AN4

AB5

AJ8

U0500

BGA-TSP

2C+GT2

HASWELL-ULT

CRITICAL

OMIT_TABLE

13 18 29 34 35 57

13 35 57

36 67

35 44 62

13 35 44 62

13 29 31 62

2

1

R1451

5%

201

1/20W MF

100K

35

2

1

R1450

5%

201

1/20W MF

330K

13 54

54

AD4

N2

N4

P4

U6

U7

L3

L4

L1

R5

C6

D6

A9

B8

A8

D11

D9

A6

B6

C8

C9

B9

B5

C5

U0500

HASWELL-ULT

OMIT_TABLE

CRITICAL

BGA-TSP

2C+GT2

13 58

25 65

18 25 65

25 65

18 28

18

18 28

25

18 25

58

21

R1446

5% 201

1/20W

MF

100K

21

R1445

5% 201

1/20W

MF

100K

21

R1442

5% 201

1/20W

MF

100K

21

R1443

5% 201

1/20W

MF

100K

21

R1441

5% 201

1/20W

MF

10K

2

1

R1400

5%

0

0201

1/20W

MF

NO STUFF

21

R1440

5% 201

1/20W

MF

100K

13 25 27

13 35

13 62

13 28

13 62

13 35

21

R1455

5%

201

1/20W

MF

10K

21

R1410

5%

201

1/20W

MF

10K

21

R1447

5% 201

1/20W

MF

100K

21

R1448

5% 201

1/20W

MF

100K

21

R1449

5% 201

1/20W

MF

100K

21

R1431

5%

201

1/20W

MF

100K

21

R1430

5%

201

1/20W

MF

100K

35 36

13 57 59 63

21

R1405

5%

201

1/20W

MF

1K

21

R1452

5%

201

1/20W

MF

10K

21

R1460

5%

201

1/20W

MF

100K

21

R1461

5%

201

1/20W

MF

100K

21

R1462

5%

201

1/20W

MF

100K

21

R1464

5%

201

1/20W

MF

100K

21

R1463

5%

201

1/20W

MF

100K

13 16 35

4

6

53

1

2

U1420

CRITICAL

74LVC1G08

SOT891

2

1

C1420

0201

X5R-CERM

10% 10V

0.1UF

PCH PM/PCI/GFX

SYNC_DATE=02/20/2013

SYNC_MASTER=J43_MLB

PCH_SUSWARN_L

PCH_SUSACK_L

DP_TBTSNK1_HPD

DP_TBTSNK1_AUXCH_C_P

TP_PM_SLP_A_L

DP_TBTSNK1_AUXCH_C_N DP_TBTSNK0_AUXCH_C_P

DP_TBTSNK0_AUXCH_C_N

DP_TBTSNK0_DDC_DATA DP_TBTSNK1_DDC_CLK

DP_TBTSNK0_HPD

DP_INT_HPD

PPVRTC_G3H

PM_SLP_S3_L

PM_SLP_S4_L

PM_CLK32K_SUSCLK_R PM_SLP_S5_L

PCIE_WAKE_L

DP_TBTSNK1_DDC_DATA

DP_TBTSNK0_DDC_CLK

TP_PCH_SLP_LAN_L

PM_SLP_SUS_L

NC_PCI_PME_L

TBT_EN_CIO_PWR_L SMC_RUNTIME_SCI_L AUD_IP_PERIPHERAL_DET AUD_I2C_INT_L

DP_AUXCH_ISOL_L ENET_LOW_PWR

AUD_IPHS_SWITCH_EN

AUD_PWR_EN

ODD_PWR_EN_L

PM_BATLOW_L

SMC_ADAPTER_EN

PM_PWRBTN_L

PM_RSMRST_L

PLT_RESET_L

PM_PCH_PWROK

PM_PCH_SYS_PWROK

PM_SYSRST_L

LPC_PWRDWN_L

PM_CLKRUN_L

PM_DSW_PWRGD

PCH_DSWVRMEN

EDP_PANEL_PWR

PCIE_WAKE_L PM_CLKRUN_L PM_SLP_S5_L

SMC_RUNTIME_SCI_L

TBT_EN_CIO_PWR_L

AUD_I2C_INT_L ODD_PWR_EN_L

DP_AUXCH_ISOL_L ENET_LOW_PWR

AUD_IPHS_SWITCH_EN

AUD_PWR_EN

PP3V3_S5

PM_PWRBTN_L PM_BATLOW_L

TP_PCH_SLP_WLAN_L

EDP_BKLT_PWM

PP3V3_S0

PCH_PM_SLP_S0_L

PM_SLP_S0_L

EDP_BKLT_EN

PM_SLP_S4_L PM_SLP_S3_L PM_SLP_S0_L

AUD_IP_PERIPHERAL_DET

EDP_PANEL_PWR

EDP_BKLT_EN

PM_SLP_SUS_L

PP3V3_S0

13 OF 73

<SCH_NUM>

14 OF 120

8

12 17 60 62

62

13 29 31 62

13 35 44 62

13 35 57

13 35

13 25 27

13 62

13 28

13 62

13 57 59 63

8

11 15 16 17 18 28 29 40 52 55

56 57 58 60 62 72

13 16 35

13 35

8

11 12 13 15 17 18 27 30 34

36 37 38 39 40 41 42 43 54 57

59 60 62 63 72

13 18 29 34 35 57

13 17 18 35 57

13 18 35

13 62

13 58

13 54

13 40 57

8

11 12 13 15 17 18 27 30 34 36

37 38 39 40 41 42 43 54 57 59

60 62 63 72

SPI_IO3

SPI_MISO

SPI_IO2

SPI_CS2*

SPI_MOSI

SPI_CS0*

SPI_CS1*

LFRAME*

LAD2 LAD3

LAD1

SPI_CLK

LAD0

SMBALERT*/GPIO11

SMBCLK

SMBDATA

SML0ALERT*/GPIO60

SML0CLK

SML0DATA

SML1CLK_GPIO75

SML1ALERT*/PCHHOT*/GPIO73

SML1DATA/GPIO74

CL_CLK

CL_DATA

CL_RST*

SYM 7 OF 19

LPC

SMBUS

SPI

C-LINK

OUT

IN IN IN

OUT

IN

OUT

IN IN

OUT OUT

IN IN

OUT OUT

IN

OUT

IN

OUT

PCIE_RCOMP PCIE_IREF

RSVD

PETP1/USB3TP2

PETN1/USB3TN2

PERP1/USB3RP2

PERN1/USB3RN2

PETP4

PETN4

PERP4

PERN4

PETP3

PETN3

PERP3

PERN3

PETP5_L3

PETN5_L3

PETP5_L2

PETN5_L2

PERP5_L2

PERN5_L2

PETP5_L1

PETN5_L1

PERP5_L1

PERN5_L1

PERN2/USB3RN3 PERP2/USB3RP3

PETN2/USB3TN3 PETP2/USB3TP3

USB2P7

USB2N7

PERP5_L3

PERN5_L3

PETP5_L0

PETN5_L0

PERP5_L0

PERN5_L0

OC1*/GPIO41

OC0*/GPIO40

OC2*/GPIO42 OC3*/GPIO43

RSVD RSVD

USBRBIAS*

USBRBIAS

USB3TP1

USB3TN1

USB3RP1

USB3RN1

USB3TP0

USB3TN0

USB3RP0

USB3RN0

USB2N0 USB2P0

USB2N1 USB2P1

USB2N2 USB2P2

USB2N3 USB2P3

USB2N4 USB2P4

USB2N5 USB2P5

USB2N6 USB2P6

USB

PCI-E

SYM 11 OF 19

IN

NC NC

OUT

IN

OUT

IN

OUT

IN

NC NC

BI

IN

BI

OUT

BI

OUT

BI BI

BI

OUT

IN

BI

OUT

BI

OUT

BI

IN

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(IPU)

Otherwise, 100k pull-up to 3.3V SUS required.

Ext A (SS)

SD Card Reader

(IPD)

Reserved: Camera

Trackpad

(IPU)

(IPU/IPD)

(IPU)

(IPU/IPD)

Reserved: SD (HS)

IR

BT

Ext B (LS/FS/HS)

Ext A (LS/FS/HS)

USB Port Assignments:

Ext B (SS)

Camera

AirPort

Reserved: FireWire

Thunderbolt lane 0

USB3 Port Assignments:

PCIe Port Assignments:

Thunderbolt lane 1

Thunderbolt lane 2

Thunderbolt lane 3

(& Ethernet if combo)

Unused

SML1ALERT# pull-up not provided on this page, may be wire-ORed into other signals.

AA2

AA4

AF1

Y6

AC2

Y4

Y7

AA3

AH3

AU3

AU4

AK1

AN1

AL2

AH1

AP2

AN2

AV12

AW11

AY12

AW12

AU14

AF4

AD2

AF2

U0500

HASWELL-ULT

OMIT_TABLE

BGA-TSP

2C+GT2

CRITICAL

25 67

21

R1580

201

1/20W

MF5%

100K

21

R1581

201MF

1/20W

5%

100K

14 16 33

14 16 59 63

14 16

37

14 16

25 67

14 62

25 67

63 66

32 67

29 67

AJ10 AJ11

A33

B34

B33

C33

F18

H20

E18

G20

AP13

AN11

AN13

AL15

AT10

AP8

AT7

AM8

AR13

AP11

AM13

AM15

AR10

AR8

AR7

AN8

E15 E13

AN10 AM10

A21

C21

A23

C22

A29

B30

A31

C31

B22

B21

B23

C23

B29

C29

B31

C30

F6

G10

E8

E10

G13

F11

G15

F17

E6

H10

F8

F10

F13

G11

F15

G17

A27 B27 AV3

AH2

AT1

AL3

U0500

CRITICAL

HASWELL-ULT

BGA-TSP

2C+GT2

OMIT_TABLE

29 62 67

2

1

R1500

1/20W

PLACE_NEAR=U0500.A27:2.54mm

1% MF

201

3.01K

59 63 66

33 66

25 67

33 66

2

1

R1570

PLACE_NEAR=U0500.AJ10:2.54mm

MF

1/20W

1%

201

22.6

34 62 66

62

25 67

62

29 66

59 63 66

25 67

33 66

35 44 62 67

21

R1543

33

MF 2015%

1/20W

21

R1542

33

5% MF

1/20W

201

25 67

21

R1544

1/20W

5% 201MF

33

21

R1540

33

MF 201

1/20W

5%

21

R1541

33

MF 2015%

1/20W

44 67

32 35 38 41 42 62 67 71

25 67

32 35 38 41 42 62 67 71

38 67

16 19 25 38 54 67

44 67

25 67

14

21

R1591

100K

5% MF

1/20W

201

21

R1549

201

1/20W

MF5%

1K

21

R1590

201MF

1/20W

5%

100K

21

R1548

201

1/20W

MF5%

1K

21

R1582

201MF

1/20W

5%

100K

21

R1583

1/20W

5% MF 201

100K

PCH PCIe/USB/LPC/SPI/SMBus

SYNC_MASTER=WILL_J43 SYNC_DATE=09/13/2012

LPC_FRAME_L

SML_PCH_0_DATA

SMBUS_SMC_1_S0_SCL SMBUS_SMC_1_S0_SDA

XDP_USB_EXTD_OC_L

XDP_USB_EXTC_OC_L

XDP_USB_EXTB_OC_L

XDP_USB_EXTA_OC_L

SPI_IO<2> SPI_IO<3>

SPI_MISO

SPI_MOSI_R

LPC_AD_R<3> LPC_FRAME_R_L

PCIE_CAMERA_R2D_C_P

SPI_CS0_R_L TP_SPI_CS1_L TP_SPI_CS2_L

PCH_USB_RBIAS

PCIE_TBT_D2R_N<0>

NC_CLINK_CLK

NC_CLINK_RESET_L

NC_CLINK_DATA

SMBUS_PCH_CLK SMBUS_PCH_DATA

SML_PCH_0_CLK

LPC_AD<3>

LPC_AD<1>

LPC_AD<0>

SPI_CLK_R

NC_USB3RPCIE_SD_R2D_CP

NC_PCIE_FW_D2RN

PCIE_AP_R2D_C_P

PCIE_TBT_R2D_C_P<0>

PCIE_TBT_D2R_N<3> PCIE_TBT_D2R_P<3>

PCIE_CAMERA_R2D_C_N

PCIE_CAMERA_D2R_P

PCIE_CAMERA_D2R_N

PCIE_TBT_D2R_N<1> PCIE_TBT_D2R_P<1>

PCIE_TBT_R2D_C_N<1> PCIE_TBT_R2D_C_P<1>

PCIE_TBT_D2R_N<2> PCIE_TBT_D2R_P<2>

PCIE_TBT_R2D_C_N<2> PCIE_TBT_R2D_C_P<2>

PCIE_TBT_R2D_C_N<3> PCIE_TBT_R2D_C_P<3>

PCIE_AP_D2R_P PCIE_AP_R2D_C_N

NC_PCIE_FW_D2RP

NC_PCIE_FW_R2D_CP

NC_USB3RPCIE_SD_D2RN NC_USB3RPCIE_SD_D2RP

NC_USB3RPCIE_SD_R2D_CN

USB3_EXTA_D2R_N

USB3_EXTA_R2D_C_P

USB3_EXTA_R2D_C_N

USB3_EXTB_D2R_N USB3_EXTB_D2R_P

USB3_EXTB_R2D_C_N

USB_EXTA_N

NC_USB_SDN NC_USB_SDP

NC_USB_CAMERAP

NC_USB_CAMERAN

TP_USB_5P

PCH_SMBALERT_L

PCIE_AP_D2R_N

USB3_EXTB_R2D_C_P

PCIE_TBT_R2D_C_N<0>

PCIE_TBT_D2R_P<0>

USB_EXTB_N

USB3_EXTA_D2R_P

NC_USB_IRN

LPC_AD_R<1> LPC_AD_R<2>

NC_PCIE_FW_R2D_CN

USB_BT_P

TP_USB_5N

USB_TPAD_P

USB_TPAD_N

NC_USB_IRP

USB_BT_N

USB_EXTB_P

USB_EXTA_P

PCH_PCIE_RCOMP

PP1V05_S0SW_PCH_VCCUSB3PLL

PCH_SML1ALERT_L

LPC_AD<2>

LPC_AD_R<0>

WOL_EN

XDP_USB_EXTA_OC_L XDP_USB_EXTB_OC_L XDP_USB_EXTC_OC_L

WOL_EN

SPI_IO<3> PCH_SMBALERT_L

SPI_IO<2>

XDP_USB_EXTD_OC_L

PP3V3_SUS PP3V3_SUS

14 OF 73

15 OF 120

<SCH_NUM>

66

62

14

62

8

11

14 16 33

14 16 59 63

14 16

14 62

14

14 16

8

11 14 18 44 55 56 57 60 62

8

11 14 18 44 55 56 57 60 62

IN

OUT

BI

OUT

IN

OUT

SERIRQ

THRMTRIP*

RCIN*/GPIO82

PCH_OPI_COMP

RSVD

GSPI0_CS*/GPIO83

GSPI0_MISO/GPIO85

GSPI0_CLK/GPIO84

GSPI1_CLK/GPIO88

GSPI1_CS*/GPIO87

GSPI0_MOSI/GPIO86

GSPI_MOSI/GPIO90

GSPI1_MISO/GPIO89

UART0_RXD/GPIO91

UART0_TXD/GPIO92

UART1_RXD/GPIO0

UART0_CTS*/GPIO94

UART0_RTS*/GPIO93

UART1_CTS*/GPIO3

UART1_RST*/GPIO2

UART1_TXD/GPIO1

I2C0_SCL/GPIO5

I2C1_SDA/GPIO6

I2C0_SDA/GPIO4

I2C1_SCL/GPIO7

SDIO_CMD/GPIO65

SDIO_CLK/GPIO64

SDIO_D1/GPIO67

SDIO_D2/GPIO68

SDIO_D0/GPIO66

SDIO_D3/GPIO69

BMBUSY*/GPIO76

GPIO8

LAN_PHY_PWR_CTRL/GPIO12

GPIO15

GPIO17

GPIO16

GPIO24

GPIO28

GPIO27

GPIO26

GPIO56

GPIO57

GPIO58

GPIO59

GPIO47

GPIO44

GPIO48

GPIO49

GPIO50

HSIOPC/GPIO71

GPIO13

GPIO25

GPIO14

GPIO45

GPIO46

GPIO9

GPIO10

DEVSLP0*/GPIO33

DEVSLP1*/GPIO38

SDIO_POWER_EN/GPIO70

DEVSLP2*/GPIO39

SPKR/GPIO81

SYM 10 OF 19

CPU/MISC

GPIO

LPIO

OUT

IN

BI

OUT

NC

OUT

NC

OUT

BI

OUT

IN

OUT

IN

OUT

IN

BI

IN

OUT

BI

OUT

IN

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_BOMGROUP_ITEM

platform does not use SD card

R1616 should also be stuffed if

(IPD-PLTRST#)

RR/FR: DPHDMIMUX_SEL_TBT, requires 100k pull-up to TBTLC

GPIO12:

Redwood Ridge: Alias to TBT_CIO_PLUG_EVENT_L, requires pull-up (S0).

Cactus Ridge: Alias to TBT_CIO_PLUG_EVENT, requires pull-down.

Pull-up/down on chipset support page (depends on TBT controller)

(IPD-PLTRST#)

Requires connection to SMC via 1K series R

(IPD-DeepSx)

(IPD-RSMRST#)

(IPD)

TBTLC for CR, S0 for RR

Pull-up on TBT page

CR: TBT_GO2SX_BIDIR, requires 100k pull-up to SUS

21

R1652

1/20W

5% 201MF

10K

21

R1668

MF 2015%

1/20W

100K

21

R1669

MF 2015%

1/20W

100K

21

R1672

MF 2015%

100K

1/20W

21

R1674

MF 2015%

1/20W

100K

21

R1673

MF 2015%

100K

1/20W

21

R1675

MF 2015%

1/20W

100K

21

R1676

MF 2015%

1/20W

100K

21

R1678

100K

1/20W

5% 201MF

21

R1677

MF 2015%

1/20W

100K

21

R1679

100K

1/20W

5% 201MF

2

1

R1639

5%

1/20W

MF

201

100K

21

R1641

1/20W

5% MF1K201

NO STUFF

21

R1629

5%

1/20W

MF

100K

201

2

1

R1621

201

MF

5%

100K

1/20W

13 15 16 18

18 27

18 25

15 35 44 62

29

15 29

2

1

R1671

MF

1/20W

100K

5%

201

13 15 16 18

15 62

15 18 25

21

R1670

MF 2015%

1/20W

100K

2

1

R1631

RAMCFG3:H

1/20W

5%

201

MF

100K

2

1

R1636

1/20W

5%

201

MF

100K

RAMCFG2:H

2

1

R1635

RAMCFG1:H

1/20W

5% MF

201

100K

2

1

R1611

RAMCFG0:H

100K

1/20W MF 201

5%

27

15 62

G2

K4

J3

J4

K3

J1

J2

G1

D60

V2

T4

C4

E2

C3

E4

D3

F4

E3

AF20 AB21

V4

AW15

AM7

G4

F1

F2

F3

Y2

K2

N7

R7

L5

L8

N6

R6

L6

AM3

AU2

AT5

AL4

AP1

AG6

P3

Y3

U4

AB6

AG3

AG5

AK4

AD7

AN5

AN3

AM4

AD5

T3

Y1

AD6

AH4

AT3

AM2

N5

L2

P2

P1

U0500

2C+GT2

HASWELL-ULT

BGA-TSP

CRITICAL

OMIT_TABLE

15 62

37

15 62

15 16

15 16 18

15 16 44 62

15 34

18

15 30 56 57 62

15 62

15 63

15 25

15 16 18 25

15 18 25

15 56

15 44 62

15 18

15 62

15 30 62

15 29

30

15 35

15 63

15 34

36 65

15 16

15 16 18

18 25

15 34

15 16 63

15 34

15 34 66

2

1

R1650

201

MF

1/20W

1K

5%

15 34 66

21

R1610

100K

1/20W

5% MF 201

21

R1614

100K

5% 201

1/20W

MF

21

R1615

100K

1/20W

201MF5%

21

R1616

SD_ON_MLB

1/20W

MF 2015%

100K

21

R1617

201MF5%

1/20W

100K

21

R1618

MF 2015%

1/20W

100K

21

R1619

5% MF

1/20W

100K

201

21

R1620

MF

1/20W

5%

100K

201

21

R1622

MF 201

1/20W

5%

100K

21

R1623

MF

100K

1/20W

5% 201

21

R1624

100K

5%

1/20W

201MF

21

R1625

201

100K

1/20W

5% MF

21

R1626

1/20W

5%

100K

201MF

21

R1627

MF 201

100K

1/20W

5%

21

R1628

100K

1/20W

5% MF 201

21

R1630

100K

1/20W

5% 201MF

21

R1632

100K

1/20W

5% 201MF

NO STUFF

21

R1633

100K

1/20W

5% 201MF

21

R1634

100K

1/20W

5% 201MF

21

R1640

MF 2015%

1/20W

100K

21

R1637

1/20W

MF 2015%

100K

21

R1638

MF 2015%

1/20W

100K

21

R1691

100K

MF 2015%

1/20W

21

R1694

100K

1/20W

5% 201MF

21

R1693

100K

1/20W

5% 201MF

2

1

R1655

PLACE_NEAR=U0500.AW15:2.54mm

49.9

201

1% 1/20W MF

21

R1695

100K

1/20W

5% 201MF

21

R1660

MF 2015%

1/20W

100K

21

R1661

100K

MF 2015%

1/20W

21

R1662

100K

1/20W

5% 201MF

21

R1663

MF 2015%

1/20W

100K

21

R1664

MF 2015%

1/20W

47K

21

R1665

MF 2015%

1/20W

47K

21

R1666

1/20W

5% 201MF

47K

21

R1667

MF 2015%

1/20W

47K

RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H

RAMCFG_SLOT

PCH GPIO/MISC/LPIO

SYNC_MASTER=WILL_J43 SYNC_DATE=01/14/2013

XDP_PCH_GPIO17

SMC_WAKE_SCI_L

HDD_PWR_EN

SSD_PWR_EN

SD_PWR_EN TBT_PWR_EN

PP3V3_TBTLC

XDP_SDCONN_STATE_CHANGE_L

TPAD_USB_IF_EN

JTAG_TBT_TMS

TPAD_SPI_INT_L

SD_RESET_L

XDP_LPCPLUS_GPIO

TPAD_SPI_MOSI

TPAD_SPI_MISO

HDMITBTMUX_FLAG_L

AP_S0IX_WAKE_L

TPAD_SPI_CLK

TPAD_SPI_CS_L

PCH_GSPI0_MOSI

PCH_GSPI0_MISO

PCH_GSPI0_CLK

PCH_GSPI0_CS_L

PCH_I2C1_SCL

PCH_UART1_CTS_L

PCH_I2C1_SDA

PCH_I2C0_SCL

PCH_I2C0_SDA

PCH_UART1_RTS_L

PCH_UART1_RXD PCH_UART1_TXD

TPAD_SPI_CS_L

TPAD_SPI_MOSI

AP_S0IX_WAKE_L HDMITBTMUX_FLAG_L JTAG_ISP_TDO AP_RESET_L

PP3V3_S3

PP3V3_S3RS0_CAMERA

PP3V3_S3

XDP_PCH_GPIO76

XDP_JTAG_ISP_TCK XDP_JTAG_ISP_TDI

XDP_MLB_RAMCFG1

LCD_PSR_EN

XDP_MLB_RAMCFG3

SD_PWR_EN

PP3V3_S0

TBT_GO2SX_BIDIR

XDP_JTAG_ISP_TCK XDP_JTAG_ISP_TDI

SD_RESET_L

TPAD_USB_IF_EN

XDP_MLB_RAMCFG1

XDP_MLB_RAMCFG0

XDP_MLB_RAMCFG2

PP1V05_S0

PM_THRMTRIP_L

LPC_SERIRQ

TBT_CIO_PLUG_EVENT

PCH_GSPI0_CS_L

PCH_GSPI0_MISO

TPAD_SPI_MISO

PCH_UART1_CTS_L

PCH_UART1_RTS_L

PCH_I2C0_SDA

SMC_WAKE_SCI_L

PCH_HSIO_PWR_EN

FW_PWR_EN

SSD_DEVSLP

XDP_MLB_RAMCFG2

XDP_PCH_GPIO76

TP_MEM_VDD_SEL_1V5_L

XDP_MLB_RAMCFG0

XDP_LPCPLUS_GPIO

JTAG_TBT_TMS

TPAD_SPI_IF_EN XDP_MLB_RAMCFG3 SPIROM_USE_MLB CAMERA_PWR_EN_PCH

PCH_STRP_TOPBLK_SWP_L

LCD_PSR_EN

LCD_IRQ_L

TBT_POC_RESET_L

ENET_MEDIA_SENSE

PCH_UART1_RXD

PCH_I2C1_SCL

PCH_I2C1_SDA

PCH_I2C0_SCL

PLT_RESET_L

TPAD_SPI_CLK

PCH_OPI_COMP

ENET_MEDIA_SENSE LCD_IRQ_L

BT_PWRRST_L

PCH_UART1_TXD

PCH_GSPI0_MOSI

PCH_GSPI0_CLK

PCH_TBT_PCIE_RESET_L

SSD_PWR_EN

XDP_PCH_GPIO17

TPAD_SPI_INT_L

HDD_PWR_EN XDP_SDCONN_STATE_CHANGE_L

TBT_PWR_EN

PLT_RESET_L

CAMERA_PWR_EN_PCH

SPIROM_USE_MLB

TPAD_SPI_IF_EN

PCH_HSIO_PWR_EN

AP_S0IX_WAKE_SEL

SSD_DEVSLP

FW_PME_L

FW_PWR_EN

LPC_SERIRQ JTAG_ISP_TDO

AP_S0IX_WAKE_SEL

PCH_TCO_TIMER_DISABLE

FW_PME_L

SSD_RESET_L

PP3V3_S0

PP3V3_S5

BT_PWRRST_L

PP3V3_S0

16 OF 120

<SCH_NUM>

15 OF 73

15 16

15 35

15 62

15 30 56 57 62

15 63

15 25

17 25 26 27 60 62

15 16 63

15 34

15 18 25

15 34

15 63

15 16 44 62

15 34 66

15 62

15 29

15 34 66

15 34

15

15 18 19 34 38 39 56 60 62 63

31 39

15 18 19 34 38 39 56 60 62 63

15 16

15 16 18 25

15 62

15 16 18

8

11 12 13 15 17 18 27 30 34 36

37 38 39 40 41 42 43 54 57 59

60 62 63 72

15 16 18

6 8

11 16 17 27 36 40 49 53

56 57 60 62

15

15 62

15

15 18

15 44 62

15 34

15 56

15 29

15 30 62

15 62

15 35 44 62

15 18 25

8

11 12 13 15 17 18 27 30 34 36

37 38 39 40 41 42 43 54 57 59

60 62 63 72

8

11 13 16 17 18 28 29 40 52 55

56 57 58 60 62 72

15 62

8

11 12 13 15 17 18 27 30 34

36 37 38 39 40 41 42 43 54 57

59 60 62 63 72

8

11 12 13 15 17 18 27 30 34

36 37 38 39 40 41 42 43 54 57

59 60 62 63 72

IN

IN IN

IN

OUT

IN

OUT

IN

OUT OUT

IN

NC NC

IN IN

IN

TP

OUT

G

D

S G

D

SG

D

S G

D

S

OUT

IN

OUT

IN

OUT

IN

TP

OUT

IN

BI

OUT

TP

BI

TP

BI

TP

BI

OUT

BI

IN

OUT

BI

IN

BI

IN

OUT

IN

OUT

BI

TP

IN

OUT

GND

VCC

NCNC

YA

NC

IN

NC

IN

TP

IN

TP

IN IN

BI

IN

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

VCC_OBS_AB

PWRGD/HOOK0

OBSDATA_B2

518S0847

CPU JTAG Isolation

TCK0

OBSDATA_D1

OBSDATA_B3

NOTE: Must not short XDP pins together!

USB Overcurrents are aliased, do not cause USB OC# events during PCH debug.

what restrictions exist on PCH GPIOs when Top-Side Probe is used for PCH debug.

via Top-Side Probe. Nets are listed here to show XDP associations and to make clear

These signals do not connect to XDP connector in this architecture, only accessible

Non-XDP Signals

PCH XDP Signals

RESET#/HOOK6

PCH/XDP Signals

SSD_PCIEx_SEL_L straps are connected via 1K to common net.

Unused & MLB_RAMCFGx GPIOs have TPs.

NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page

TDI and TMS are terminated in CPU.

HOOK2

TDO TRSTn

Merged (CPU/PCH) Micro2-XDP

OBSFN_D0

SCL

OBSDATA_D2

OBSDATA_A1

Use with 921-0133 Adapter Flex to

NOTE: This is not the standard XDP pinout.

TCK1

SDA

HOOK1

HOOK3

OBSDATA_B1

OBSDATA_B0

OBSFN_B0

OBSDATA_A2 OBSDATA_A3

OBSFN_B1

OBSDATA_A0

TDI TMS

ITPCLK/HOOK4

XDP_PRESENT#

DBR#/HOOK7

OBSDATA_D3

ITPCLK#/HOOK5

OBSFN_D1

OBSDATA_D0

OBSDATA_C2 OBSDATA_C3

OBSDATA_C1

OBSFN_C1

OBSDATA_C0

OBSFN_C0

support chipset debug.

Extra BPM Testpoints

VCC_OBS_CD

OBSFN_A1

OBSFN_A0

NOTE: Should force PCH GPIO47 high to ensure TBT router powered to avoid leakage/clamping of signals.

JTAG_ISP (non-TMS) nets are aliased, do not attempt bit-banged JTAG during PCH debug.

SDCONN_STATE_CHANGE_L is aliased, do not plug/unplug SD Cards during PCH debug.

LPCPLUS_GPIO is aliased, do not attempt use during PCH debug.

6

13 15 18

6

65

6

62 65

6

65

6

65

6

65

6

65

13 35

13 17 35

12 16 62 67

17 65

6

12 16 62 67

21

R1805

XDP

1K

PLACE_NEAR=U0500.AG7:2.54mm

MF

1/20W

2015%

12

R1813

XDP

51

PLACE_NEAR=U0500.E60:28mm

MF

1/20W

2015%

21

R1804

1/16W MF-LF

402

XDP

0

5%

21

R1802

XDP

PLACE_NEAR=U5000.J3:2.54mm

MF

1/20W

0201

0

5%

21

R1800

1K

XDP

PLACE_NEAR=U0500.C61:2.54mm

MF

1/20W

2015%

6

65

9

8 7

64 63

62

61

60659

58 57

56 55

54 53

52 51

50549

48 47

46 45

44 43

42 41

40439

38 37

36 35

34 33

32 31

30329

28 27

26 25

24 23

22 21

20219

18 17

16 15

14 13

12 11

10

1

J1800

M-ST-SM1

CRITICAL

DF40RC-60DP-0.4V

XDP_CONN

6

65

6

65

6

65

6

65

6

65

6

65

6

65

6

65

6

65

6

65

1

TP1806

TP-P6

1

TP1807

TP-P6

1

TP1805

TP-P6

1

TP1804

TP-P6

1

TP1803

TP-P6

1

TP1802

TP-P6

8

2

1

R1830

150

402

MF-LF

1/16W

5%

21

R1810

51

XDP

PLACE_NEAR=U0500.F62:28mm

MF

1/20W

2015%

12 16 62 67

2

1

R1831

1K

1/16W 402

MF-LF

XDP

5%

12

R1896

51

PLACE_NEAR=U0500.AE62:28mm

NO STUFF

MF

1/20W

2015%

12

R1892

51

XDP

PLACE_NEAR=U0500.AD62:28mm

MF

1/20W

2015%

12

R1891

51

XDP

PLACE_NEAR=U0500.AD61:28mm

MF

1/20W

2015%

12

R1890

XDP

51

PLACE_NEAR=U0500.AE61:28mm

MF

1/20W

2015%

12

R1899

1K

PLACE_NEAR=U0500.AE63:28mm

NO STUFF

MF

1/20W

2015%

21

R1835

XDP

PLACE_NEAR=J1800.58:28mm

MF

1/20W

0201

0

5%

12 16

1

2

6

Q1842

PLACE_NEAR=J1800.57:28mm

XDP

SOT-563

DMN5L06VK-7

CRITICAL

4

5

3

Q1840

XDP

SOT-563

DMN5L06VK-7

CRITICAL

PLACE_NEAR=J1800.51:28mm

4

5

3

Q1842

PLACE_NEAR=J1800.55:28mm

CRITICAL

XDP

DMN5L06VK-7

SOT-563

1

2

6

Q1840

CRITICAL

XDP

DMN5L06VK-7

SOT-563

PLACE_NEAR=J1800.53:28mm

6

12 16 62 65

6

62 65

6

62 65

6

16 62 65

2

1

C1801

10%

0.1UF

0201

CERM-X5R

6.3V

XDP

15 16 63

14

14 16 59 63

6

65

14 16 59 63

1

TP1870

TP-P6

14 16 33 14 16 33

15 18

14

1

TP1874

TP-P6

2

1

C1800

10%

0.1UF

0201

CERM-X5R

6.3V

XDP

1

TP1876

TP-P6

15 18

1

TP1877

TP-P6

15 18

1

TP1878

TP-P6

15 18

12

15

15 16 18 25 15 16 18 25

12

21

R1881

1K

MF

1/20W

2015%

21

R1882

1K

MF

1/20W

2015%

6

62 65

21

R1883

1K

MF

1/20W

2015%

21

R1884

1K

MF

1/20W

2015%

30 62

15 16 44 62

6

62 65

15

15 16 18 25 15 16 18 25

15 16 44 62

1

TP1887

TP-P6

2

1

C1804

10%

0.1UF

0201

CERM-X5R

6.3V

XDP

2

1

C1806

10%

0.1UF

0201

CERM-X5R

6.3V

XDP

6

65

6

12 16 62 65

12

R1897

PLACE_NEAR=U0500.AU62:28mm

NO STUFF

51

MF

1/20W

2015%

4

6

5

1

3

2

U1845

74LVC1G07GF

SOT891

2

1

C1845

10%

0.1UF

16V

0201

X5R-CERM

6

65

2

1

R1845

330K

MF

1/20W 201

5%

17 35 57

1

TP1873

TP-P6

15 16 63

1

TP1886

TP-P6

6

65

6

65

14 19 25 38 54 67

6

16 62 65

6

8

17

6

65

6

65

SYNC_MASTER=WILL_J43

CPU/PCH Merged XDP

SYNC_DATE=12/17/2012

XDP_LPCPLUS_GPIO

XDP_JTAG_ISP_TDI

SSD_PCIE_SEL_L

ALL_SYS_PWRGD

PP5V_S0

XDP_PCH_TMS

XDP_CPUPCH_TRST_L

CPU_CFG<1>

XDP_PCH_TDO

XDP_PCH_TDI

MAKE_BASE=TRUE

XDP_CPUPCH_TRST_L

XDP_CPU_TCK

XDP_BPM_L<6> XDP_BPM_L<7>

XDP_BPM_L<5>

XDP_BPM_L<4>

XDP_BPM_L<3>

XDP_BPM_L<2>

PP1V05_SUS

PCH_JTAGX

XDP_PCH_TDI

XDP_CPU_TDO

XDP_PCH_TDO

PP1V05_S0

CPU_CFG<0>

CPU_CFG<2>

XDP_BPM_L<1>

CPU_CFG<4> CPU_CFG<5>

SMBUS_PCH_CLK XDP_PCH_TCK

CPU_VCCST_PWRGD

PM_PWRBTN_L

PM_PCH_SYS_PWROK

CPU_CFG<8> CPU_CFG<9>

CPU_CFG<12>

CPU_CFG<14> CPU_CFG<15>

PLT_RESET_L

XDP_CPU_TDO

XDP_CPUPCH_TRST_L XDP_CPUPCH_TRST_L

XDP_CPU_TDI

XDP_CPU_TMS

CPU_CFG<10> CPU_CFG<11>

XDP_PCH_TCK

XDP_JTAG_CPU_ISOL_L

XDP_CPU_TCK

XDP_USB_EXTB_OC_L

XDP_MLB_RAMCFG0 XDP_USB_EXTA_OC_L

MAKE_BASE=TRUE

XDP_USB_EXTB_OC_L

MAKE_BASE=TRUE

XDP_USB_EXTC_OC_L

MAKE_BASE=TRUE

XDP_SDCONN_STATE_CHANGE_L

XDP_USB_EXTD_OC_L

XDP_MLB_RAMCFG1

MAKE_BASE=TRUE

XDP_JTAG_ISP_TCK

XDP_SSD_PCIE1_SEL_L

XDP_PCH_GPIO76

MAKE_BASE=TRUE

XDP_JTAG_ISP_TDI

SMBUS_PCH_DATA

MAKE_BASE=TRUE

XDP_LPCPLUS_GPIO

XDP_SSD_PCIE0_SEL_L

XDP_SSD_PCIE2_SEL_L

XDP_PCH_GPIO17

XDP_SSD_PCIE3_SEL_L

XDP_MLB_RAMCFG2

XDP_TRST_L

CPU_CFG<13>

CPU_CFG<18>

CPU_CFG<19>

CPU_CFG<16>

CPU_CFG<17>

XDP_CPU_PREQ_L

XDP_SYS_PWROK

PP3V3_S5

PCH_JTAGX

XDP_MLB_RAMCFG3

XDP_SDCONN_STATE_CHANGE_L

XDP_USB_EXTA_OC_L

XDP_JTAG_ISP_TCK

XDP_DBRESET_L

XDP_CPURST_L

XDP_CPU_VCCST_PWRGD

XDP_CPU_PRDY_L

CPU_CFG<3>

XDP_BPM_L<0>

XDP_CPU_PWRBTN_L

PP1V05_S0

CPU_PWR_DEBUG

CPU_CFG<7>

CPU_CFG<6>

XDP_CPU_PRESENT_L

18 OF 120

<SCH_NUM>

16 OF 73

17 32 43 44 49 50 54 56 57 59 60 62

12 16 62 67

6

12 16 62 65

6

12 16 62 65

6

16 62 65

55 60

12 16

12 16 62 67

6

16 62 65

12 16 62 67

6 8

11 15 16 17 27 36 40 49

53 56 57 60 62

12 16 62 67

62

8

11 13 15 17 18 28 29 40 52

55 56 57 58 60 62 72

65

62

6 8

11 15 16 17 27 36 40 49

53 56 57 60 62

OUT

NC NC

OUT

IN

BIIN

OUT

IN

S

D

G

SDG

OUT

NC

NC NC

OUT

IN

NC

OUT

IN

NC

A Y

NC NC

VCC

GND

NC

IN

OUT

IN

Y

A

B

08

Y

A

B

08

OUT

IN

OUT

IN

YA

B

NC

GND

VCC

32.768K

GND

THRM

VOUT

X2 X1

25M_A 25M_B 25M_C

VIOE_25M_A VIOE_25M_B VIOE_25M_C

VG3HOT

NC

VDD

PAD

NC NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

This looks a little ugly to support new and old parts. With GreenCLK Rev C pin 5 must receive S5 power (Stuff R2042)

NOTE: 30 PPM or better required for RTC accuracy

PCH ME Disable Strap

For SB RTC Power

to reduce VBAT draw.

+V3.3A should be first

create VDD_RTC_OUT.

internally ORed to

VBAT and +V3.3A are

Chipset uses 24MHz crystal, GreenCLK kept to save 1x 25MHz crystal & 1x 32kHz crystal

System RTC Power Source & 32kHz / 25MHz Clock Generator

Coin-Cell: VBAT (300-ohm & 10uF RC) No Coin-Cell: 3.42V G3Hot (no RC)

Coin-Cell & G3Hot: 3.42V G3Hot

PCH 24MHz Crystal

GreenCLK 25MHz Power

TBT XTAL Power

Coin-Cell & No G3Hot: 3.3V S5 No Coin-Cell: 3.3V S5

No bypass necessary

PCH 24MHz Outputs

PCH PWROK Generation

CAM XTAL Power

If high, ME is disabled. This allows for full re-flashing of SPI ROM.

Q1920 & 5V pull-up allows circuit to work regardless of HDA voltage.

PCH Reset Button

PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.

IPD = 9-50k

VCCST (1.05V S0) PWRGD

SMC controls strap enable to allow in-field control of strap setting.

Memory VTT Enable Level-Shifter

CPU output is on VDDQ rail (1.2V), TPS51916 has 1.8V Vih(min).

33uW when driven-low

Vih(min) = 1.8V

TPS51916 I(leak) = +/- 1uA,

WF: Do we need this?

available ~3.3V power

Must be powered if any VDDIO is powered.

12

25 67

2

1

C1902

6.3V

20%

0201

1UF

X5R

2

1

C1910

X5R

1UF

20%

6.3V 0201

31

42

Y1905

25.000MHZ-12PF-20PPM

CRITICAL

SM-3.2X2.5MM

2 1

C1905

5%

0201

NP0-C0G-CERM

25V

12PF

21

C1906

5%

12PF

0201

NP0-C0G-CERM

25V

17 35 67

44 62 67

21

R1927

5%

201

1/20W

MF

22

PLACE_NEAR=U0500.AN15:5.1mm

21

R1926

5%

201

1/20W

MF

22

PLACE_NEAR=U0500.AP15:5.1mm

12 67

13 35 62 16 65

2

1

C1924

0.1UF

10% 16V

X5R-CERM

0201

21

R1905

5%

0

0201

1/20W

MF

2

1

R1906

5%

201

1/20W MF

1M

NO STUFF

21

R1996

5%

0

0201

1/20W

MF

XDP

2

1

R1997

5%

0

NO STUFF

SILK_PART=SYS RESET

MF-LF

1/16W 402

2

1

R1995

5%

201

1/20W MF

10K

2

1

R1920

5%

201

1/20W MF

100K

2

1

R1921

5%

201

1/20W MF

1K

12 67

35

4

5

3

Q1920

SOT-563

DMN5L06VK-7

1

2

6

Q1920

DMN5L06VK-7

SOT-563

2

1

C1922

X5R-CERM

0201

16V

10%

0.1UF

32 67

2

1

R1916

5%

201

1/20W MF

1M

21

R1915

5%

0

0201

1/20W

MF

21

C1915

25V

+/-0.1PF

0201

6.8PF

C0G

21

C1916

+/-0.1PF

25V C0G

0201

6.8PF

12

12 17

8

16

2

1

R1931

5%

201

1/20W MF

10K

2

1

C1930

0.1UF

10%

X5R-CERM

16V

0201

13 18 35 57

2

1

R1970

5%

201

1/20W MF

330K

4

6

5

1

3

2

U1970

74AUP1G07GF

SOT891

2

1

C1970

X5R-CERM

0201

16V

10%

0.1UF

6

17 51

27 35 36

16 17 35 57

7

8

4

2

1

U1950

SOT833

74LVC2G08GT

2

1

C1950

BYPASS=U1950:5MM

0.1UF

16V 0201

10% X5R-CERM

3

8

4

6

5

U1950

CKPLUS_WAIVE=UNCONNECTED_PINS

74LVC2G08GT

SOT833

CKPLUS_WAIVE=UNCONNECTED_PINS

1

2

R1963

5%

0

0201

1/20W

MF

1

2

R1960

5%

0

0201

1/20W MF

NO STUFF

21

R1962

5%

201

1/20W

MF

1K

13 16 35

13 17

21

R1951

5%

0

0201

1/20W

MF

NO STUFF

2

1

R1950

5%

201

1/20W

MF

10K

2

1

R1955

5%

201

1/20W

MF

10K

8

49

8

17 49

8

17 49

2

1

R1961

5%

201

1/20W

MF

100K

NO STUFF

4

6

5

3

1

2

U1930

CRITICAL

SOT891

74AUP1G09

3 4

1

14

6

11

13

5

17216107

12

15

8

9

U1900

CKPLUS_WAIVE=PwrTerm2Gnd

TQFN

CRITICAL

SLG3NB148CV

3 1

4 2

Y1915

24.000MHZ-20PPM-6PF

3.20X2.50MM-SM1

CRITICAL

SYNC_MASTER=J43_MLB1 SYNC_DATE=01/09/2013

Chipset Support

SYSCLK_CLK25M_TBT

SYSCLK_CLK25M_CAMERA

SYSCLK_CLK25M_X2_R

PPVRTC_G3H

MAKE_BASE=TRUE

LPC_CLK24M_SMC LPC_CLK24M_SMC

NC_RTC_CLK32K_RTCX2

MAKE_BASE=TRUE

NO_TEST=TRUE

SYSCLK_CLK25M_X2

PP3V3_S0

CPUVR_PGOOD_R

PM_PCH_PWROK

PM_S0_PGOOD

PM_PCH_SYS_PWROK

MEMVTT_PWR_EN

PP3V3_S0

MAKE_BASE=TRUE

MEMVTT_PWR_EN

PP1V2_S3

CPU_MEMVTT_PWR_EN_LSVDDQ

SPI_DESCRIPTOR_OVERRIDE_LS5V

PP5V_S0

SYS_PWROK_R

LPC_CLK24M_LPCPLUS_R

LPC_CLK24M_SMC_R

PCH_CLK24M_XTALOUT

LPC_CLK24M_LPCPLUS

HDA_SDOUT_R

SPI_DESCRIPTOR_OVERRIDE

SPI_DESCRIPTOR_OVERRIDE_L

PP1V5_S0SW_AUDIO_HDA

PP3V3_S0

PM_SYSRST_L

XDP_DBRESET_L

PP3V42_G3H

CPU_VR_READY

CPU_VR_EN

CPU_VR_READY

MAKE_BASE=TRUE

ALL_SYS_PWRGD

SMC_DELAYED_PWRGD

MAKE_BASE=TRUE

PM_PCH_PWROK

PP1V05_S0

CPU_VCCST_PWRGD

PP3V3_S5

ALL_SYS_PWRGD PM_SLP_S3_L

PCH_CLK24M_XTALIN

PCH_CLK24M_XTALOUT_R

SYSCLK_CLK25M_X1

PP1V2_CAM_XTALPCIEVDD

PP3V42_G3H

PP3V3_TBTLC

PCH_CLK32K_RTCX1

NC_RTC_CLK32K_RTCX2

PP3V3_S5RS3RS0_SYSCLKGEN

PP3V3_S5

<SCH_NUM>

19 OF 120

17 OF 73

67

8

12 13 60 62

17 35 67

12 17

67

8

11 12 13 15 17 18 27 30 34

36 37 38 39 40 41 42 43 54 57

59 60 62 63 72

8

11 12 13 15 17 18 27 30 34 36

37 38 39 40 41 42 43 54 57 59

60 62 63 72

17 51

19 20 21 22 23 40 51 60 68

16 32 43 44 49 50 54 56 57 59 60 62

8

11 56

8

11 12 13 15 17 18 27 30 34

36 37 38 39 40 41 42 43 54 57

59 60 62 63 72

17 30 33 34 35 36 38 44 46 47 48 57 59 60 62 63

6 8

11 15 16 27 36 40 49 53 56

57 60 62

8

11 13 15 16 17 18 28 29 40

52 55 56 57 58 60 62 72

16 17 35 57

67

31

17 30 33 34 35 36 38 44 46 47 48 57 59 60 62 63

15 25 26 27 60 62

18

8

11 13 15 16 17 18 28 29 40 52 55 56

57 58 60 62

72

SDG SDG

OUT

IN

IN IN IN IN

SDG SDG

IN OUT OUT

BI

BI BI

OUT

BI

OUT IN IN

IN

OUT

IN

OUT

IN

IN BI

BIBI

NC

08

NC

OUT

IN

IN OUT OUT

OUT IN IN

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

MAKE_BASEMAKE_BASE

NOTE: Only DDC_DATA is sensed by PCH, so

Unbuffered

to indicate active display interface.

Power State Debug LEDs

DDC_CLK pull-ups are unstuffed.

LPDDR3 Alias Support

MAKE_BASE

DDC Pull-Ups

Cactus Ridge GO2SX signal pulled-up to SUS rail

GreenCLK 25MHz Power

R2041/2 should be stuffed for

DP++ spec violation, should remove!

TBTSNK1_DDC is pulled-up just to indicate that DP port is used. No DDC on this port, AUX-only.

2.2k pull-ups are required by PCH

Thunderbolt Pull-up/downs

Required for unused second TBT port

R2042 should be stuffed for GreenCLK C

GreekCLK A or B depending on S2 rail

(For development only)

Buffered

Cactus Ridge PLUG_EVENT is active-high, always driven (pull-down)

TBT Aliases

MAKE_BASE

Scrub for Layout Optimization

Platform Reset Connections

Pull-downs for chip-down RAM systems

RAM Configuration Straps

No MAKE_BASE on TCK/TDI as these are provided on XDP page.

Single-port TBT implementation does not require DDC Crossbar

MAKE_BASE

2

1

R2022

2.2K

NO STUFF

MF

1/20W

201

5%

2

1

R2023

2.2K

MF

1/20W 201

5%

2

1

R2020

NO STUFF

2.2K

MF

1/20W

201

5%

2

1

R2021

2.2K

MF

1/20W 201

5%

2

1

R2050

10K

RAMCFG3:L

MF

1/20W

201

5%

2

1

R2051

10K

RAMCFG2:L

MF

1/20W

201

5%

2

1

R2052

10K

RAMCFG1:L

MF

1/20W

201

5%

2

1

R2053

10K

RAMCFG0:L

MF

1/20W

201

5%

2

1

R2016

10K

MF

1/20W

201

5%

2

1

R2017

10K

MF

1/20W 201

5%

2

1

R2018

10K

MF

1/20W

201

5%

2

1

R2019

10K

MF

1/20W 201

5%

2

1

R2014

10K

MF

1/20W 201

5%

1

2

6

Q2090

SOT-563

DMN5L06VK-7

DBGLED

4

5

3

Q2090

SOT-563

DBGLED

DMN5L06VK-7

K

A

D2090

SILK_PART=S5_ON

DBGLED

PLACE_SIDE=BOTTOM

LTQH9G-SM

GREEN-56MCD-2MA-2.65V

K

A

D2091

SILK_PART=STBY_ON

DBGLED

PLACE_SIDE=BOTTOM

GREEN-56MCD-2MA-2.65V LTQH9G-SM

2

1

R2090

20K

DBGLED

MF

1/20W

201

5%

2 1

R2094

DBGLED

PLACE_SIDE=BOTTOM

1/16W MF-LF

402

0

5%

2

1

R2091

20K

DBGLED

MF

1/20W

201

5%

K

A

D2092

LTQH9G-SM

GREEN-56MCD-2MA-2.65V

SILK_PART=S3_ON

DBGLED

PLACE_SIDE=BOTTOM

2

1

R2092

20K

DBGLED

MF

1/20W

201

5%

K

A

D2093

DBGLED

SILK_PART=S0I3_ON

PLACE_SIDE=BOTTOM

LTQH9G-SM

GREEN-56MCD-2MA-2.65V

2

1

R2093

20K

DBGLED

MF

1/20W

201

5%

15 16

25

6

18

15 18

28 56 57

13 18 29 34 35 57

13 17 35 57

2

1

R2095

DBGLED

20K

MF

1/20W

201

5%

K

A

D2095

SILK_PART=S0_ON

DBGLED

PLACE_SIDE=BOTTOM

LTQH9G-SM

GREEN-56MCD-2MA-2.65V

13 35

1

2

6

Q2091

DMN5L06VK-7

SOT-563

DBGLED

4

5

3

Q2091

DMN5L06VK-7

SOT-563

DBGLED

13 18 25

5

25 65

5

25 65

13 18 28

13 18 25 65

13 18 28

13 18

13 18 25 65

13 18 25

13 18

2

1

C2071

0201

X5R-CERM

0.1UF

16V

10%

5

4

1

2

3

U2071

MC74VHC1G08

CRITICAL

SC70-HF

2

1

R2070

100K

MF

1/20W 201

5%

21

R2088

MF

1/20W

0201

0

5%

21

R2072

MF

1/20W

0201

0

5%

13 15 16

21

R2071

MF

1/20W

0201

0

5%

21

R2081

33

MF

1/20W

201

5%

54

35

19

44 62 67

15 18 25

2

1

R2015

100K

MF

1/20W

201

5%

15 18 25

21

R2089

MF

1/20W

0201

0

5%

31

15 18 27 15 18 27

21

R2040

NO STUFF

MF

1/20W

0201

0

5%

21

R2041

NO STUFF

MF

1/20W

0201

0

5%

13 18 28

15 18 25 15 18 25

2

1

R2013

10K

MF

1/20W

201

5%

4

6

5 3

1

2

U2030

SOT891

74LVC1G08

CRITICAL

NOSTUFF

2

1

C2030

10V

10%

X5R-CERM

0201

BYPASS=U2030:3mm

0.1UF

NOSTUFF

21

R2030

MF

1/20W

0201

0

5%

31

15

13 18 29 34 35 57

21

R2042

MF

1/20W

0201

0

5%

15 18 25

15 16 18 25

15 18 25

15 16 18 25

15 18 25 15 18 25

SYNC_DATE=01/17/2013

Project Chipset Support

SYNC_MASTER=J43_MLB

PP3V3_S5

DP_TBTSNK1_HPD

TRUE TRUE

DP_TBTSNK1_ML_C_P<3..0>

=DP_TBTSNK1_ML_C_P<3..0> =DP_TBTSNK1_ML_C_N<3..0>

DP_TBTSNK1_DDC_DATA

JTAG_TBT_TMS

DP_TBTSNK0_DDC_DATA

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.5 MM

PP3V3_S5_DBGLED

PP3V3_S0

PP3V3_S5RS3RS0_SYSCLKGEN

MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.5 MM

LPCPLUS_RESET_L

BKLT_PLT_RST_L

DP_TBTSNK1_ML_C_N<3..0>

TRUE

DP_TBTSNK1_HPD

TBT_B_LSRX

DP_TBTSNK1_AUXCH_C_P

TRUE

DP_TBTSNK1_AUXCH_C_N

PCH_TBT_PCIE_RESET_L

CAM_PCIE_RESET_L

SMC_LRESET_L

PCH_TBT_PCIE_RESET_L

MAKE_BASE=TRUE

PLT_RST_BUF_L

PP3V3_S0

PLT_RESET_L

PCA9557D_RESET_L

PM_SLP_S4_L

CAMERA_PWR_EN_PCH

PP3V3_S5

CAMERA_PWR_EN

DP_TBTSNK0_DDC_DATA

PP3V3_S3

DP_TBTSNK1_DDC_DATA

DP_TBTSNK0_DDC_CLK

PP3V3_S0

PP3V3_S5RS3RS0_SYSCLKGEN

TBT_GO2SX_BIDIR

XDP_MLB_RAMCFG0 XDP_MLB_RAMCFG1

PP3V3_SUS

TBT_GO2SX_BIDIR

TRUE

TBT_CIO_PLUG_EVENTTBT_CIO_PLUG_EVENT

DP_TBTSNK1_AUXCH_C_N

TRUE

DP_TBTSNK0_DDC_DATA

TRUE

DP_TBTSNK1_DDC_DATA

TRUE

DP_TBTSNK1_DDC_CLK

TRUE

DP_TBTSNK1_AUXCH_C_P

DP_TBTSNK0_DDC_CLK

TBT_B_CONFIG1_BUF

TBT_B_CONFIG2_RC

DP_TBTPB_HPD

TBT_B_CIO_SEL

PP0V6_S3_MEM_VREFCA_B

MAKE_BASE=TRUE

VOLTAGE=0.6V

PP0V6_S3_MEM_VREFCA_B

PP0V6_S3_MEM_VREFDQ_B

MAKE_BASE=TRUE

VOLTAGE=0.6V

PP0V6_S3_MEM_VREFDQ_B

TP_MEM_VDD_SEL_1V5_L

TP_CPU_MEM_RESET_L

PP0V6_S3_MEM_VREFCA_A

MAKE_BASE=TRUE

VOLTAGE=0.6V

PP0V6_S3_MEM_VREFCA_A

PP0V6_S3_MEM_VREFDQ_A PP0V6_S3_MEM_VREFDQ_A

MAKE_BASE=TRUE

VOLTAGE=0.6V

TP_MEM_VDD_SEL_1V5_L

MAKE_BASE=TRUE

TP_CPU_MEM_RESET_L

MAKE_BASE=TRUE

XDP_MLB_RAMCFG3

XDP_MLB_RAMCFG2

PM_SLP_S4_L

DP_TBTSNK1_DDC_CLK

DBGLED_S0

DBGLED_S0I3

DBGLED_S0_D

DBGLED_S0I3_D

DBGLED_S5

S4_PWR_EN

TRUE

DP_TBTSNK0_DDC_CLK

DP_TBTSNK1_DDC_CLK

XDP_JTAG_ISP_TCK

JTAG_ISP_TDOJTAG_ISP_TDO

TRUE

XDP_JTAG_ISP_TCK XDP_JTAG_ISP_TDI XDP_JTAG_ISP_TDI

JTAG_TBT_TMS

TRUE

PP3V3_S5

PM_SLP_S0_L

PM_SLP_S3_L

DBGLED_S3_D

DBGLED_S3

DBGLED_S4_D

DBGLED_S4

<SCH_NUM>

20 OF 120

18 OF 73

8

11 13 15 16 17 18 28 29 40

52 55 56 57 58 60 62 72

8

11 12 13 15 17 18 27 30 34

36 37 38 39 40 41 42 43 54 57

59 60 62 63 72

17 18

25

8

11 12 13 15

17 18 27 30 34

36 37 38 39 40

41 42 43 54 57

59 60 62 63 72

8

11 13 15 16 17 18 28 29 40

52 55 56 57 58 60 62 72

13 18 28

15 19 34 38 39 56 60 62 63

13 18

13 18 28

8

11 12 13 15 17 18 27 30 34

36 37 38 39 40 41 42 43 54 57

59 60 62 63 72

17 18

8

11 14 44 55 56 57 60 62

13 18

18 19 22 23 68 18 19 22 23 68

18 19 20 21 68 18 19 20 21 68

15 18

6

18

13 18

8

11 13

15 16 17

18 28 29

40 52 55

56 57 58

60 62 72

OUT

V-

V+

V-

V+

IN

G

D

SG

D

SG

D

S G

D

S

IN

G

D

SG

D

SG

D

SG

D

S

RESET*

A0 A1 A2

SCL SDA

P0 P1 P2

P5 P6 P7

P3 P4

THRM

VCC

GND

PAD

NC

IN

BI

VDD

VOUTD

VOUTC

VOUTB

VOUTA

SCL

SDA

A0

A1

GND

IN

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

6.36mV / step @ output

0.337V - 1.013V (+/- 337.5mV)

MEM B VREF DQ

NOTE: CPU has single output for

signals for independent DAC

DAC-Based Margining

4.28mV / step @ output

LPDDR3 (1.2V)

DAC margining VREFCA ensure

LPDDR3 (1.2V) ?.??mV per step

May not be necessary due to C22x0

EN RC’s to avoid drain glitches

- DDRVREF_DAC - Stuffs DAC margining circuit.

BOM options provided by this page:

0.000V - 1.354V (0x00 - 0x69) 0.000V - 2.694V (0x00 - 0xD1)

- =I2C_VREFDACS_SDA

- =PPDDR_S3_MEMVREF

- =PP3V3_S3_VREFMRGN

DAC step size:

VRef current:

Nominal value

DAC range:

- =I2C_VREFDACS_SCL

VREFCA. Split into two

VREFMRGN_CPU_EN is low

DDR3L (1.35V) 6.99mV per step

Q2225 pin 6:

(OD)

both at the same time!

Pins B1 & B4:

Page Notes

Power aliases required by this page:

Signal aliases required by this page:

- =I2C_PCA9557D_SCL

- =I2C_PCA9557D_SDA

margining support. When

CPU-Based Margining

0.000V - 1.199V (0x00 - 0x5D)

0.300V - 0.900V (+/- 300mV)

Margined target:

0.675V (DAC: 0x34)

0.600V (DAC: 0x2E.5)

+73uA - -73uA (- = sourced)

(All 4 R’s)

NOTE: MEMVREG and SPARE share a DAC output, cannot enable

+82uA - -82uA (- = sourced)

6.36mV / step @ output

4

C

DDR3L (1.35V)

MEM B VREF CA

3

C

MEM A VREF CA

2

BA

1

MEM A VREF DQ

PCA9557D Pin:

DAC Channel:

LPDDR3 (1.2V)

MEM VREG

D 5

1.200V (DAC: 0x5D)

NOTE: LPDDR3 assumes TPS51916 supply with 28.7k/57.6k divider DDR3L assumes TPS51916 supply with 19.6k/57.6k divider

DDR3L (1.35V)

0.972V - 1.714V (+/- 371mV)

1.343V (DAC: 0x68)

+25uA - -25uA (- = sourced)

3.53mV / step @ output

RST* on ’platform reset’ so that system watchdog will disable margining.

soft-resets and sleep/wake cycles.

Addr=0x30(WR)/0x31(RD)

DAC sets voltage level, PCA9557 & FETs enable outputs and disables margining after platform reset.

to remove short due to CPU.

Q2265 pin 6:

R22x6 pin 2:

FETs for CPU isolation during DAC margining

DDR3 (1.5V) 7.70mV per step

NOTE: CPU DAC output step sizes:

Addr=0x98(WR)/0x99(RD)

Always used, regardless

NOTE: Margining will be disabled across all

0.800V - 1.600V (+/- 400mV)

0.000V - 2.397V (0x00 - 0xBA) +21uA - -21uA (- = sourced)

of margining option.

VRef Dividers

51

2

1

C2202

DDRVREF_DAC

CERM-X5R

0201

0.1UF

6.3V

10%

21

R2214

38.3K

MF

1/20W

DDRVREF_DAC

1%

PLACE_NEAR=R7415.2:1mm

201

2

1

R2213

DDRVREF_DAC

MF

1/20W

100K

5%

201

2

1

R2212

DDRVREF_DAC

MF

1/20W

100K

5%

201

B4

B1

A4

A1

A2

A3

U2204

DDRVREF_DAC

CRITICAL

UCSP

MAX4253

CKPLUS_WAIVE=unconnected_pinsCKPLUS_WAIVE=unconnected_pins

B4

B1

C4

C1

C2

C3

U2204

CRITICAL

MAX4253

DDRVREF_DAC

UCSP

21

R2218

402

OMIT

NONE NONE

NONE

SHORT

18

7

1

2

6

Q2260

SOT-563

CRITICAL

DMN5L06VK-7

2

1

R2202

100K

DDRVREF_DAC

MF

5%

1/20W

201

4

5

3

Q2220

SOT-563

DMN5L06VK-7

CRITICAL

4

5

3

Q2260

SOT-563

DMN5L06VK-7

CRITICAL

1

2

6

Q2220

SOT-563

DMN5L06VK-7

CRITICAL

7

1

2

6

Q2225

SOT-563

PLACE_NEAR=Q2220.6:2.54mm

DDRVREF_DAC

CRITICAL

DMN5L06VK-7

2

1

R2201

MF

1/20W

5%

DDRVREF_DAC

100K

201

21

R2225

100K

DDRVREF_DAC

MF

5%

1/20W

201

2

1

C2225

CERM-X5R

0201

0.1UF

DDRVREF_DAC

6.3V

10%

1

2

6

Q2265

PLACE_NEAR=Q2260.6:2.54mm

SOT-563

DMN5L06VK-7

DDRVREF_DAC

CRITICAL

2

1

C2245

DDRVREF_DAC

CERM-X5R

0201

0.1UF

6.3V

10%

21

R2245

100K

5%

DDRVREF_DAC

1/20W

MF

201

21

R2265

100K

DDRVREF_DAC

5%

1/20W

MF

201

4

5

3

Q2225

SOT-563

DMN5L06VK-7

CRITICAL DDRVREF_DAC

2

1

C2265

DDRVREF_DAC

CERM-X5R

0201

0.1UF

6.3V

10%

4

5

3

Q2265

SOT-563

DMN5L06VK-7

CRITICAL DDRVREF_DAC

2

1

C2285

DDRVREF_DAC

CERM-X5R

0201

0.1UF

6.3V

10%

2

1

R2215

DDRVREF_DAC

MF

1/20W

5%

100K

201

21

R2285

100K

5%

1/20W

MF

DDRVREF_DAC

201

2

1

R2207

MF

1/20W

5%

100K

DDRVREF_DAC

201

21

R2226

PLACE_NEAR=Q2225.1:2.54mm

DDRVREF_DAC

4.02K

MF

1/20W

1% 201

21

R2246

PLACE_NEAR=Q2265.1:2.54mm

DDRVREF_DAC

4.02K

MF

1/20W

1% 201

21

R2266

PLACE_NEAR=Q2225.4:2.54mm

DDRVREF_DAC

4.02K

MF

1/20W

1% 201

21

R2286

PLACE_NEAR=Q2265.4:2.54mm

DDRVREF_DAC

4.02K

MF

1/20W

1% 201

2

1

R2217

1M

DDRVREF_DAC

5% 1/20W MF 201

2

1

R2200

MF

1/20W

5%

100K

201

2

1

R2221

1/20W

8.2K

1% MF

PLACE_NEAR=Q2220.6:3mm

201

21

R2280

24.9

1%

1/20W

MF

201

2

1

C2280

PLACE_NEAR=Q2260.3:2mm

6.3V X5R-CERM 0201

0.022UF

10%

21

R2283

1%

10

1/20W

MF

201

2

1

R2281

MF

1/20W

8.2K

1%

PLACE_NEAR=Q2260.3:3mm

201

2

1

R2282

PLACE_NEAR=R2281.2:1mm

MF

1/20W

8.2K

1%

201

2

1

R2262

MF

1/20W

8.2K

1%

PLACE_NEAR=R2261.2:1mm

201

21

R2260

24.9

1%

1/20W

MF

201

21

R2263

1%

10

1/20W

MF

201

2

1

C2260

PLACE_NEAR=Q2220.3:2mm

6.3V X5R-CERM 0201

0.022UF

10%

2

1

R2261

MF

1/20W

8.2K

1%

PLACE_NEAR=Q2220.3:3mm

201

2

1

R2242

MF

1/20W

8.2K

1%

PLACE_NEAR=R2241.2:1mm

201

21

R2240

24.9

1%

1/20W

MF

201

21

R2243

1%

1/20W

MF

10

201

2

1

C2240

PLACE_NEAR=Q2260.6:2mm

10%

0.022UF

0201

X5R-CERM

6.3V

2

1

R2241

MF

1/20W

1%

PLACE_NEAR=Q2260.6:3mm

8.2K

201

21

R2223

1%

10

MF

1/20W

201

2

1

R2222

1/20W

MF

8.2K

1%

PLACE_NEAR=R2221.2:1mm

201

21

R2220

24.9

1%

1/20W

MF

201

2

1

C2220

PLACE_NEAR=Q2220.6:2mm

6.3V X5R-CERM 0201

0.022UF

10%

16

17

2

1

15

14

13

12

11

10

9

7

6

8

5

4

3

U2201

PCA9557

QFN

CRITICAL DDRVREF_DAC

14 16 19 25 38 54 67

5

4

2

1

8

7

6

3

10

9

U2200

DAC5574

CRITICAL DDRVREF_DAC

MSOP

14 16 19 25 38 54 67

2

1

C2201

DDRVREF_DAC

CERM-X5R 0201

0.1UF

6.3V

10%

2

1

C2200

402-LF

DDRVREF_DAC

2.2UF

CERM

20%

6.3V

2

1

C2205

DDRVREF_DAC

CERM-X5R

0201

0.1UF

6.3V

10%

SYNC_MASTER=WILL_J43

DDR3 VREF MARGINING

SYNC_DATE=02/04/2013

VREFMRGN_SPARE_EN

VREFMRGN_CA_B_EN

VREFMRGN_CA_A_EN

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP3V3_S3_VREFMRGN_DAC

VREFMRGN_MEMVREG_EN

VREFMRGN_DQ_B_EN

VREFMRGN_DQ_A_EN

VREFMRGN_CPU_EN

SMBUS_PCH_DATA

SMBUS_PCH_CLK

PCA9557D_RESET_L

MEM_VREFDQ_A_RC

CPU_MEM_VREFDQ_A_ISOL

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

PP0V6_S3_MEM_VREFDQ_B

VREFMRGN_DQ_B_EN_RC

CPU_MEM_VREFCA_B_ISOL

VREFMRGN_MEMVREG

CPU_DIMMB_VREFDQ

VREFMRGN_DQ_A_RDIV VREFMRGN_DQ_B_RDIV

CPU_MEM_VREFCA_A_ISOL

CPU_DIMMA_VREFDQ

VREFMRGN_DQ_B

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP0V6_S3_MEM_VREFCA_B

PP1V2_S3

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP0V6_S3_MEM_VREFCA_A

CPU_DIMM_VREFCA

VREFMRGN_CA_AB

VREFMRGN_CA_B_RDIV

VREFMRGN_CA_A_RDIV

VREFMRGN_DQ_A

MEM_VREFCA_B_RC

DDRREG_FB

VREFMRGN_CA_B_EN_RC

SMBUS_PCH_DATA

SMBUS_PCH_CLK

MEM_VREFDQ_B_RC

MEM_VREFCA_A_RC

VREFMRGN_MEMVREG_BUF

VREFMRGN_SPARE_BUF

PP3V3_S3

VREFMRGN_CA_A_EN_RC

PP0V6_S3_MEM_VREFDQ_A

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

CPU_MEM_VREFDQ_B_ISOL

VREFMRGN_DQ_A_EN_RC

<SCH_NUM>

22 OF 120

19 OF 73

18 22 23 68

17 20 21 22 23 40 51 60 68

18 20 21 68

15 18 19 34 38 39 56 60 62 63

18 20 21 68

BI BI BI BI BI

BI

NC

IN IN IN IN IN IN IN IN

BI

IN IN

IN

BI

(1 OF 2)

CA5

CK_T

CKE1

CK_C

DM1

CA0 CA1 CA2 CA3 CA4

CA6 CA7 CA8 CA9

CKE0

DM0

DM2 DM3

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQS0_C

DQS0_T

DQS1_C

DQS1_T

DQS2_C

DQS2_T

DQS3_C

DQS3_T

NC

ODT

VREFCA VREFDQ

ZQ0 ZQ1

CS0* CS1*

NU

VDDCA

VDDQ

VSS

VSSCA

VSSQ

VDD2

VDD1

(2 OF 2)

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Distribute evenly.

LPDDR3 CHANNEL A (0-31)

PLACEMENT_NOTE:

10uF caps are shared between DRAM.

61

2

1

C2306

10UF

20% 25V X5R-CERM 0603

2

1

C2307

25V 0603

10UF

20% X5R-CERM

2

1

C2302

402

10V X5R

1UF

10%

61

2

1

C2300

10%

0.1UF

X5R-CERM

16V 0201

2

1

C2303

402

10V X5R

1UF

10%

2

1

C2304

10V X5R 402

1UF

10%

2

1

C2301

10%

0.1UF

0201

X5R-CERM

16V

2

1

C2305

10V X5R 402

1UF

10%

61

2

1

C2310

10V X5R 402

1UF

10%

2

1

C2311

10V X5R 402

1UF

10%

2

1

C2312

25V 0603

10UF

20% X5R-CERM

2

1

C2320

10%

1UF

402

X5R

10V

2

1

C2321

10%

1UF

402

X5R

10V

2

1

C2322

10%

1UF

402

X5R

10V

61

2

1

C2324

X5R-CERM

20%

10UF

0603

25V

2

1

C2323

X5R-CERM

20%

10UF

0603

25V

2

1

C2333

10UF

20%

0603

25V X5R-CERM

2

1

C2332

25V 0603

10UF

20% X5R-CERM

2

1

C2331

10%

1UF

402

X5R

10V

2

1

C2330

10%

1UF

X5R

10V 402

61

2

1

C2341

0.047UF

201

10% X5R

6.3V

2

1

C2340

201

0.047UF

X5R

6.3V

10%

61

24 61 68

7

24 61 68

61

24 61 68

7

24 68

7

24 68

7

24 68

7

24 68

7

21 24 68

7

21 24 68

7

21 24 61 68

61

2

1

R2300

201

MF

1/20W

1%

243

2

1

R2301

1%

243

1/20W

MF

201

B4

B3

J11

H4

J8

U2

U1

T13

T1

B13

B1

A13

A12

U13

U12

A2

A1

R3

K9

C4

D10

D11

P10

P11

G10

G11

L10

L11

F10

F11

M11

M10

M9

M8

B8

B9

N11

B10

B11

C8

C9

C10

C11

R11

R10

R9

R8

N10

T11

T10

T9

T8

D9

E9

E10

E11

F8

F9

N9

P9

D8

P8

G8

L8

L4

L3

K4

K3

J3 J2

C2

D2

E2

E3

F3

M3

N3

N2

P2

R2

U2300

FBGA

LPDDR3-16GB

EDFA232A1MA-GD-F

CRITICAL

OMIT_TABLE

H10

G9

G6

F12

F6

E6

D12

C6

T12

T6

R6

P12

N6

M12

M6

L9

K10

B12

B6

J4

M4

P3

G4

G3

F4

D3

C3

M5

L6

K2

J12

F5

E5

E4

C5

H2

T5

T4

T3

T2

R5

R4

N5

N4

B5

B2

J10

J9

H11

H9

H8

G12

E12

E8

U11

R12

N12

N8

L12

K11

K8

C12

A11

M2

L2

H3

G2

F2

J5

H12

H6

H5

G5

D6

D5

D4

U9

U8

P6

P5

P4

L5

K12

K6

K5

J6

A9

A8

U10

U6

U5

U4

U3

A10

A6

A5

A4

A3

U2300

FBGA

LPDDR3-16GB

EDFA232A1MA-GD-F

CRITICAL

OMIT_TABLE

61

LPDDR3 DRAM Channel A (0-31)

SYNC_MASTER=MASTER

SYNC_DATE=MASTER

PP1V2_S3

MEM_A_ZQ<0>

PP0V6_S3_MEM_VREFCA_A PP0V6_S3_MEM_VREFDQ_A

MEM_A_ZQ<1>

MEM_A_CLK_N<0> MEM_A_CS_L<0>

MEM_A_CAA<5>

MEM_A_CAA<7>

MEM_A_CLK_P<0>

MEM_A_CKE<1>

MEM_A_CAA<8>

MEM_A_CAA<4>

PP1V8_S3

MEM_A_CAA<9>

MEM_A_CAA<6>

=MEM_A_DQ<4>

PP1V2_S3

=MEM_A_DQ<13> =MEM_A_DQ<14> =MEM_A_DQ<15> =MEM_A_DQ<16>

=MEM_A_DQ<18>

=MEM_A_DQ<22> =MEM_A_DQ<23>

=MEM_A_DQ<20>

MEM_A_CAA<2>

MEM_A_CAA<0>

=MEM_A_DQ<24>

=MEM_A_DQ<17>

PP1V2_S3

=MEM_A_DQ<25>

=MEM_A_DQS_P<0>

PP1V2_S3

=MEM_A_DQ<3>

=MEM_A_DQS_N<1>

=MEM_A_DQ<19>

=MEM_A_DQS_P<3>

=MEM_A_DQS_P<1> =MEM_A_DQS_P<2>

=MEM_A_DQS_N<3>

=MEM_A_DQS_N<2>

=MEM_A_DQS_N<0>

=MEM_A_DQ<31>

=MEM_A_DQ<30>

=MEM_A_DQ<29>

=MEM_A_DQ<27> =MEM_A_DQ<28>

=MEM_A_DQ<26>

=MEM_A_DQ<21>

=MEM_A_DQ<12>

=MEM_A_DQ<10> =MEM_A_DQ<11>

=MEM_A_DQ<9>

=MEM_A_DQ<8>

=MEM_A_DQ<7>

=MEM_A_DQ<6>

=MEM_A_DQ<5>

=MEM_A_DQ<2>

=MEM_A_DQ<1>

=MEM_A_DQ<0>

MEM_A_CS_L<1>

MEM_A_ODT<0>

PP1V8_S3

MEM_A_CKE<0>

MEM_A_CAA<3>

MEM_A_CAA<1>

PP1V2_S3

23 OF 120

<SCH_NUM>

20 OF 73

17 19 20 21 22 23 40 51 60 68

18 19 21 68

20 21 22 23 55 60

17 19 20 21 22 23 40 51 60 68

20 21 22 23 55 60

17 19 20 21 22 23 40 51 60 68

BI BI

IN

BI BI BI

BI

NC

IN IN IN IN IN IN IN IN

BI

IN IN

BI

(1 OF 2)

CA5

CK_T

CKE1

CK_C

DM1

CA0 CA1 CA2 CA3 CA4

CA6 CA7 CA8 CA9

CKE0

DM0

DM2 DM3

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQS0_C

DQS0_T

DQS1_C

DQS1_T

DQS2_C

DQS2_T

DQS3_C

DQS3_T

NC

ODT

VREFCA VREFDQ

ZQ0 ZQ1

CS0* CS1*

NU

VDDCA

VDDQ

VSS

VSSCA

VSSQ

VDD2

VDD1

(2 OF 2)

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

LPDDR3 CHANNEL A (32-63)

10uF caps are shared between DRAM.

PLACEMENT_NOTE:

Distribute evenly.

61

2

1

C2423

25V 0603

10UF

20% X5R-CERM

2

1

C2403

10%

1UF

402

X5R

10V

2

1

C2404

10%

1UF

402

X5R

10V

2

1

C2405

10%

1UF

402

X5R

10V

2

1

C2406

0603

X5R-CERM

25V

20%

10UF

61

7

20 24 61 68

2

1

R2400

243

1%

1/20W

MF

201

2

1

R2401

201

MF

1/20W

243

1%

2

1

C2440

6.3V X5R

0.047UF

201

10%

61

2

1

C2441

6.3V X5R

10%

0.047UF

201

61

7

61 68

61

7

61 68

7

61 68

61

24 61 68

7

24 61 68

61

24 61 68

7

24 68

7

24 68

7

24 68

7

24 68

7

20 24 68

7

20 24 68

61

B4

B3

J11

H4

J8

U2

U1

T13

T1

B13

B1

A13

A12

U13

U12

A2

A1

R3

K9

C4

D10

D11

P10

P11

G10

G11

L10

L11

F10

F11

M11

M10

M9

M8

B8

B9

N11

B10

B11

C8

C9

C10

C11

R11

R10

R9

R8

N10

T11

T10

T9

T8

D9

E9

E10

E11

F8

F9

N9

P9

D8

P8

G8

L8

L4

L3

K4

K3

J3 J2

C2

D2

E2

E3

F3

M3

N3

N2

P2

R2

U2400

OMIT_TABLE

FBGA

EDFA232A1MA-GD-F

CRITICAL

LPDDR3-16GB

H10

G9

G6

F12

F6

E6

D12

C6

T12

T6

R6

P12

N6

M12

M6

L9

K10

B12

B6

J4

M4

P3

G4

G3

F4

D3

C3

M5

L6

K2

J12

F5

E5

E4

C5

H2

T5

T4

T3

T2

R5

R4

N5

N4

B5

B2

J10

J9

H11

H9

H8

G12

E12

E8

U11

R12

N12

N8

L12

K11

K8

C12

A11

M2

L2

H3

G2

F2

J5

H12

H6

H5

G5

D6

D5

D4

U9

U8

P6

P5

P4

L5

K12

K6

K5

J6

A9

A8

U10

U6

U5

U4

U3

A10

A6

A5

A4

A3

U2400

FBGA

EDFA232A1MA-GD-F

LPDDR3-16GB

CRITICAL

OMIT_TABLE

2

1

C2430

10V X5R 402

1UF

10%

2

1

C2431

10V X5R 402

1UF

10%

2

1

C2410

10%

1UF

402

X5R

10V

2

1

C2411

10%

1UF

402

X5R

10V

61

2

1

C2432

X5R-CERM

20%

10UF

0603

25V

2

1

C2412

10UF

X5R-CERM

20%

0603

25V

2

1

C2420

10V X5R 402

1UF

10%

2

1

C2400

10%

0.1UF

X5R-CERM

16V 0201

2

1

C2421

10V X5R 402

1UF

10%

2

1

C2401

0.1UF

16V X5R-CERM

10%

0201

2

1

C2422

10V X5R 402

1UF

10%

2

1

C2402

10V

10%

1UF

402

X5R

SYNC_DATE=MASTER

SYNC_MASTER=MASTER

LPDDR3 DRAM Channel A (32-63)

MEM_A_CLK_P<1>

MEM_A_CAB<9>

MEM_A_CAB<8>

MEM_A_CAB<7>

MEM_A_CAB<6>

=MEM_A_DQ<44>

MEM_A_CLK_N<1>

=MEM_A_DQS_P<7>

=MEM_A_DQS_P<5> MEM_A_DQS_P<6>

=MEM_A_DQS_P<4>

=MEM_A_DQS_N<7>

MEM_A_DQS_N<6>

=MEM_A_DQS_N<4> =MEM_A_DQS_N<5>

=MEM_A_DQ<63>

=MEM_A_DQ<62>

=MEM_A_DQ<61>

=MEM_A_DQ<59> =MEM_A_DQ<60>

=MEM_A_DQ<58>

=MEM_A_DQ<57>

=MEM_A_DQ<56>

=MEM_A_DQ<55>

=MEM_A_DQ<54>

=MEM_A_DQ<53>

=MEM_A_DQ<52>

=MEM_A_DQ<51>

=MEM_A_DQ<50>

=MEM_A_DQ<49>

=MEM_A_DQ<48>

=MEM_A_DQ<47>

=MEM_A_DQ<46>

MEM_A_DQ<33>

=MEM_A_DQ<42> =MEM_A_DQ<43>

=MEM_A_DQ<41>

=MEM_A_DQ<40>

=MEM_A_DQ<39>

=MEM_A_DQ<38>

=MEM_A_DQ<37>

=MEM_A_DQ<36>

=MEM_A_DQ<34> =MEM_A_DQ<35>

=MEM_A_DQ<33>

=MEM_A_DQ<32>

MEM_A_CS_L<1>

PP1V2_S3

PP1V8_S3

PP1V2_S3

PP1V8_S3

PP1V2_S3

MEM_A_CAB<4>

MEM_A_CAB<0> MEM_A_CAB<1> MEM_A_CAB<2> MEM_A_CAB<3>

MEM_A_CAB<5>

MEM_A_CKE<2> MEM_A_CKE<3>

MEM_A_CS_L<0>

MEM_A_ODT<0>

MEM_A_ZQ<2> MEM_A_ZQ<3>

PP0V6_S3_MEM_VREFDQ_A

PP0V6_S3_MEM_VREFCA_A

<SCH_NUM>

21 OF 73

24 OF 120

17 19 20 21 22 23 40 51 60 68

20 21 22 23 55 60

17 19 20 21 22 23 40 51 60 68

20 21 22 23 55 60

17 19 20 21 22 23 40 51 60 68

18 19 20 68

BI BI

IN

BI BI BI

BI

NC

IN IN IN IN IN IN IN IN

BI

IN IN

BI

(1 OF 2)

CA5

CK_T

CKE1

CK_C

DM1

CA0 CA1 CA2 CA3 CA4

CA6 CA7 CA8 CA9

CKE0

DM0

DM2 DM3

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQS0_C

DQS0_T

DQS1_C

DQS1_T

DQS2_C

DQS2_T

DQS3_C

DQS3_T

NC

ODT

VREFCA VREFDQ

ZQ0 ZQ1

CS0* CS1*

NU

VDDCA

VDDQ

VSS

VSSCA

VSSQ

VDD2

VDD1

(2 OF 2)

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PLACEMENT_NOTE:

10uF caps are shared between DRAM. Distribute evenly.

LPDDR3 CHANNEL B (0-31)

61

2

1

C2523

X5R-CERM

20%

10UF

0603

25V

2

1

C2503

10V X5R 402

1UF

10%

2

1

C2504

10V X5R 402

1UF

10%

2

1

C2505

10V X5R 402

1UF

10%

2

1

C2506

10UF

20% 25V X5R-CERM 0603

61

7

23 24 61 68

2

1

R2500

243

1%

1/20W

MF

201

2

1

R2501

201

MF

1/20W

243

1%

2

1

C2540

10%

6.3V X5R

0.047UF

201

2

1

C2541

6.3V X5R

10%

0.047UF

201

61

24 61 68

7

24 61 68

61

24 61 68

7

24 68

7

24 68

7

24 68

7

24 68

7

23 24 68

7

23 24 68

61

B4

B3

J11

H4

J8

U2

U1

T13

T1

B13

B1

A13

A12

U13

U12

A2

A1

R3

K9

C4

D10

D11

P10

P11

G10

G11

L10

L11

F10

F11

M11

M10

M9

M8

B8

B9

N11

B10

B11

C8

C9

C10

C11

R11

R10

R9

R8

N10

T11

T10

T9

T8

D9

E9

E10

E11

F8

F9

N9

P9

D8

P8

G8

L8

L4

L3

K4

K3

J3 J2

C2

D2

E2

E3

F3

M3

N3

N2

P2

R2

U2500

OMIT_TABLE

CRITICAL

EDFA232A1MA-GD-F

LPDDR3-16GB

FBGA

H10

G9

G6

F12

F6

E6

D12

C6

T12

T6

R6

P12

N6

M12

M6

L9

K10

B12

B6

J4

M4

P3

G4

G3

F4

D3

C3

M5

L6

K2

J12

F5

E5

E4

C5

H2

T5

T4

T3

T2

R5

R4

N5

N4

B5

B2

J10

J9

H11

H9

H8

G12

E12

E8

U11

R12

N12

N8

L12

K11

K8

C12

A11

M2

L2

H3

G2

F2

J5

H12

H6

H5

G5

D6

D5

D4

U9

U8

P6

P5

P4

L5

K12

K6

K5

J6

A9

A8

U10

U6

U5

U4

U3

A10

A6

A5

A4

A3

U2500

OMIT_TABLE

CRITICAL

FBGA

LPDDR3-16GB

EDFA232A1MA-GD-F

2

1

C2530

10%

1UF

402

X5R

10V

2

1

C2531

10%

1UF

402

X5R

10V

2

1

C2510

10V X5R 402

1UF

10%

2

1

C2511

10V X5R 402

1UF

10%

61

2

1

C2532

25V 0603

10UF

20% X5R-CERM

2

1

C2512

25V 0603

10UF

20% X5R-CERM

2

1

C2520

10%

1UF

402

X5R

10V

2

1

C2500

0201

16V X5R-CERM

0.1UF

10%

2

1

C2521

10%

1UF

402

X5R

10V

2

1

C2501

0201

10%

0.1UF

X5R-CERM

16V

2

1

C2522

10%

1UF

402

X5R

10V

2

1

C2502

10V X5R 402

1UF

10%

LPDDR3 DRAM Channel B (0-31)

SYNC_MASTER=MASTER

SYNC_DATE=MASTER

PP1V8_S3

PP1V2_S3

MEM_B_CAA<0> MEM_B_CAA<1> MEM_B_CAA<2> MEM_B_CAA<3> MEM_B_CAA<4> MEM_B_CAA<5> MEM_B_CAA<6> MEM_B_CAA<7> MEM_B_CAA<8> MEM_B_CAA<9>

MEM_B_CKE<0> MEM_B_CKE<1>

MEM_B_CLK_P<0> MEM_B_CLK_N<0>

MEM_B_CS_L<0>

PP1V8_S3

PP1V2_S3

MEM_B_CS_L<1>

=MEM_B_DQ<0> =MEM_B_DQ<1>

=MEM_B_DQ<3>

=MEM_B_DQ<2>

=MEM_B_DQ<4> =MEM_B_DQ<5> =MEM_B_DQ<6> =MEM_B_DQ<7> =MEM_B_DQ<8> =MEM_B_DQ<9>

=MEM_B_DQ<11>

=MEM_B_DQ<10>

=MEM_B_DQ<12> =MEM_B_DQ<13> =MEM_B_DQ<14> =MEM_B_DQ<15> =MEM_B_DQ<16> =MEM_B_DQ<17> =MEM_B_DQ<18> =MEM_B_DQ<19> =MEM_B_DQ<20> =MEM_B_DQ<21> =MEM_B_DQ<22> =MEM_B_DQ<23> =MEM_B_DQ<24> =MEM_B_DQ<25> =MEM_B_DQ<26>

=MEM_B_DQ<28>

=MEM_B_DQ<27>

=MEM_B_DQ<29> =MEM_B_DQ<30> =MEM_B_DQ<31>

=MEM_B_DQS_N<1>

=MEM_B_DQS_N<0>

=MEM_B_DQS_N<2> =MEM_B_DQS_N<3>

=MEM_B_DQS_P<0>

=MEM_B_DQS_P<2>

=MEM_B_DQS_P<1>

=MEM_B_DQS_P<3>

MEM_B_ODT<0>

MEM_B_ZQ<0> MEM_B_ZQ<1>

PP0V6_S3_MEM_VREFDQ_B

PP0V6_S3_MEM_VREFCA_B

<SCH_NUM>

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Apple MACBOOK AIR A1465 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual