Apple D1 Book

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

6 5 4 3

2 1

REV ECN

DESCRIPTION OF REVISION

CK APPD

DATE

<ECO_DESCRIPTION>

SCHEM,MLB,D1

8/8/12

Page

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

39 SMC

TABLE_TABLEOFCONTENTS_ITEM

(.csa)

Table of Contents

System Block Diagram

Power Block Diagram

Revision History

BOM Configuration

Functional / ICT Test

Power Aliases

Signal Aliases

CPU DMI/PEG/FDI/RSVD

CPU CLOCK/MISC/JTAG

CPU DDR3 INTERFACES

CPU POWER

CPU GROUNDS

CPU DECOUPLING-I

CPU DECOUPLING-II

PCH SATA/PCIe/CLK/LPC/SPI

PCH DMI/FDI/PM/Graphics

PCH PCI/USB/TP/RSVD

PCH GPIO/MISC/NCTF

PCH POWER

PCH GROUNDS

PCH DECOUPLING

CPU & PCH XDP

Chipset Support

USB HUB & MUX

CPU Memory S3 Support

DDR3 SDRAM Bank A (Rank 0)

DDR3 SDRAM Bank B (Rank 0)

DDR3 Termination

DDR3/FRAMEBUF VREF MARGINING

ALS/CAMERA CONNECTOR

Thunderbolt Host (1 of 2)

Thunderbolt Host (2 of 2)

Thunderbolt Power Support

RIO CONNECTORS

SSD/HDD Connectors

USB 3.0 CONNECTORS

SMC Support

LPC+SPI Debug Connector

SMBus Connections

Power Sensor: Load Side

Power Sensor: High Side

Thermal Sensors

Contents

Sync

MASTER

K17_REF

MASTER

D1_MLB_TEST

J30_MLB

MASTER

J13_MLB

J30_MLB

MASTER

J5_AMD

J5_MLB

MASTER

J5_MLB

MASTER

J5_MLB_KEPLER

MASTER

J5_AMD

D1_SENSORS

MASTER

D1_SENSORS

Date

MASTER

02/15/2011

06/30/2009

MASTER

01/27/2012

07/14/2011

MASTER

09/15/2011

07/14/2011

MASTER

08/17/2011

07/29/2011

07/14/2011

MASTER

07/29/2011

MASTER

11/14/2011

MASTER

08/24/2011

02/20/2012

MASTER

02/20/2012

Page

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

(.csa)

Fan Connectors

KEYBOARD/TRACKPAD (1 OF 2)

KEYBOARD/TRACKPAD (2 OF 2)

DIGITAL ACCELEROMETER & GYRO

SPI ROM

AUDIO: CODEC/REGULATOR

AUDIO: HEADPHONE FILTER

AUDIO: SPEAKER AMP

AUDIO: JACK

AUDIO: JACK TRANSLATORS

DC-In & Battery Connectors

PBus Supply & Battery Charger

System Agent Supply

5V / 3.3V Power Supply

1.5V DDR3 Supply

CPU IMVP7 & AXG VCore Regulator

CPU IMVP7 & AXG VCore Output

CPUVCCIO (1.05V) Power Supply

Misc Power Supplies

Power FETs

Power Control 1/ENABLE

eDP Display Connector

DDC Crossbar

Thunderbolt Connector A

Thunderbolt Connector B

LCD Backlight Driver (LP8545)

100

CPU Constraints

101

Memory Constraints

102

PCH Constraints 1

103

PCH Constraints 2

105

Thunderbolt Constraints

106

SMC Constraints

108

Project Specific Constraints

109

PCB Rule Definitions

132

Power Sensors: Extended

Contents

J5_MLB

D2_MLB_KEPLER

J5_MLB

J13_MLB

D1_AUDIO

MASTER

D1_SENSORS

MASTER

J5_MLB_KEPLER

J5_MLB

J5_MLB_KEPLER

J5_MLB

T29_CR

J5_MLB

D1_SENSORS

Sync

Date

07/29/2011

12/08/2011

07/29/2011

01/20/2012

06/06/2012

MASTER

07/11/2012

MASTER

11/14/2011

09/21/2011

09/13/2011

09/21/2011

07/29/2011

08/31/2011

07/29/2011

07/11/2012

Schematic / PCB #’s

PART NUMBER

820-3462

DRAWING

TITLE=MLB ABBREV=ABBREV

LAST_MODIFIED=Thu Aug 9 12:34:09 2012

QTY

1 SCH

DESCRIPTION

SCHEM,MLB,D1

PCBF,MLB(NEW),D1

REFERENCE DES

PCB1

CRITICAL

CRITICAL051-9216

CRITICAL

BOM OPTION

SIZE

DRAWING TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SCHEM,MLB,D1

Apple Inc.

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

1 OF 132

SHEET

1 OF 80

1245678

8 7 6 5 4 3

J2500

XDP CONN

U1000

PG 23

J3502

U3100-U3170

Mem

CAMERA

PG 31

PG 28

U6100

SPI

Boot ROM

PG 49

J4410

RIO CONN

Bluetooth

PG 35

1 2 3

U2700

USB HUB

PG 25

U4900

I2C Ser

U5701

TP/KB

PSOC

PG 46 PG 46

From PCH

SMC

PG 38

J5700, J5713

U4900

U2760

EHCI XHCI

J2550

Fan

ADCSMS

Prt

TRACKPAD/

KEYBOARD

SMC

PG 38

USB MUX

PG 25

PCH XDP

J6900, J6950

DC/BATT

PG 55

U5550,U5570

TEMP SENSOR

PG 47

U5920,U5940

Motion Sensor/GYRO

U5340,U5350,U5360,U5370,U5400,U5410,Q5480 Q5490

J5650,J5660

FAN CONN AND CONTROL

PG 48

POWER SENSE

PG 42, 43

PG 45

J5100

SPI

Port80,serial

J4410

RIO CONN

USB 3

PG 35

J4600

EXTERNAL A

USB 3

PG37

LPC+SPI Conn

PG 40

POWER SUPPLY

PG 56-65

INTEL CPU

2.X GHz

IVY BRIDGE 2C-35W

PG 9-15

U2600

SYSTEM

CLOCK

PG 24

GPIO

PG 19

CLK

BUFFER

PG 16

FDI

PG 17

DMI

PG 17

DDR3-1333/1600MHZ

U2900-U2970

Mem

PG 27

RTC

PG 16

MISC

PG 19

SPI

U4510

SATA

REDRIVER

PG 36

U9420

J9400

DP/TBT

PORT

CONN

PG 68,69

PortA

PortB

MUX

PG 68

U9620

U3600

CIO

TBT Host

CIO

PG 32,33

PCIe x4

J4500

SATA CONN

HDD

PG 36

MUX

PG 69

J9000

eDP

CONN

PG 66

J4410

RIO CONN

HDMI

PG 35

1.05V/6GHZ. 0

SATA

PG 16

LVDS OUT

RGB OUT

DP OUT

DVI OUT

TMDS OUT

PG 17

eDP OUT

PG 17

PCI

PG 18

HDMI

PG 17

JTAG

PG 16

PEG

PG 16

INTEL

PANTHER POINT-MPCH

U1800

PG 16-21

PCI-E

(UP TO 8 LINES)

PG 16

2 1

PG 16

LPC

PG 16

PWR

CTRL

PG 17

13 12 1110

USB

PG 18

4 3 5

(UP TO 14 DEVICES)

1 2 0 76

4 32

PG 18

USB 3

SMBUS

PG 16

HDA

PG 16

CONN

PG 23

U6201

EXTMIC LINEIN HPOUT SPDIF MICIN LINEOUT

J4410

AUDIO Codec

PG 50

RIO CONN

J6802 J6803

PG 54

U6610,U6620 U6630,U6640

SPEAKER

AMPs

PG 52

SYNC_MASTER=MASTER

PAGE TITLE

System Block Diagram

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=02/15/2011

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

2 OF 132

SHEET

2 OF 80

124578

SIZE

Airport/SD Card

PG 35

U6750

MIC BIAS

PG53

J6701

PG 53

AUDIO CONNs

J5815 PG 47

6 3

8 7 6 5 4 3

D1 POWER SYSTEM ARCHITECTURE

PPDCIN_G3H

P5V1_VIN

J6900

ADAPTER

DCIN(16.5V)

F6905 6A FUSE

R7020

SMC_DCIN_ISENSE

SMC_RESET_L

ENABLE

LT3470A

U7090

(PAGE 56)

VIN

PBUS SUPPLY/

BATTERY CHARGER

PP5V1_CHGR_VDDP

U7000

ISL6259

R6920

VOUT

PPVBAT_G3H

R7050

SMC_BATT_ISENSE

(PAGE 56)

J6950

PPVBATT_G3H_CONN

3S2P

(9 TO 12.6V)

Q7055

CHGR_BGATE

PPVBAT_G3H_CHGR_R

PPDCIN_S5_P3V42G3H

F7040

www.qdzbwx.com

PPBUS_G3H

SMC

U4900

(PAGE 38)

Panther-POINT

(PCH)

(PAGE 16~21)

DELAY

U1800

SLP_S3#(D4)

PVCCSA_EN

CPUVCCIOS0_EN

P1V8S0_EN

P1V5S0_EN

P60

SMC_S4_WAKESRC_EN

SLP_S5#(F6)

SLP_S4#(K10)

PG67

SMC_PM_G2_EN

PM_SLP_S5_L

PG67

DELAY

PG 17

DDRREG_EN

DELAY

P5VS3_EN

DELAY

P3V3S3_EN

DELAY

P1V2S3_EN

DELAY

TPAD_VBUS_EN

DELAY

PM_SLP_S4_L

PM_SLP_S3_L

R7978

PG65

PM_SLP_S3_R_L

P5VS0_EN

P3V3S0_EN

PBUSVSENS_EN

TBT_S0_EN

P3V3S5_EN

74LVG1G32

U7970

(PAGE 65)

PG67

PG 17

TBTAPWRSW_EN TBTBPWRSW_EN P3V3S4_EN

P5VS4_EN

PG59

PG64

PG46

F9700

LCD_BKLT_EN

BKLT_PLT_RST_L

PPBUS_S0_LCDBKLT_PWR

Q4260

PP3V3_S0 && FWPORT_PWR_EN

T29_A_HV_EN

Q9706

Q3880

R5430

VIN

LP8545SQX-EXTJ

U9701

(PAGE 70)

PPBUS_S5_HS_OTHER_ISNS

P5V3V3S4_EN

P3V3S5_EN

PPVOUT_S0_LCDBKLT

VOUT

F4260

VIN

LT3957

U3890

VOUT

(PAGE 34)

EN1

EN2

PPVP_FW

PP15V_TBT_REG

VIN

TPS51980

U7201

(PAGE 60)

(L/H)

3.3V

(R/H)

PGOOD

P5V3V3_PGOOD

VREG5

VOUT1

VOUT2

Q5720

SLG5AP020

VCC

(PAGE 64)

U7801

6 3

D6905

PP5V_S5RS4_CUMUUS

P5VS4_EN

P1V5CPU_EN

P1V5_CPU_EN

PPVIN_S3_P1V5S3RS0_FET

PP5V_S4

PP3V3_S5

SMC_PBUS_VSENSE

P1V5S3RS0FET_GATE

PP3V3_S5

Q7800

P3V3_S4_EN

Q7840

Q7810

Q7830

Q7850

P5VS3_EN

Q7820

P3V3_SUS_EN

PP3V3_S4_FET

P5VSUS_EN

P3V3S3_EN

PP3V3_S0_FET

P3V3_S0_EN

PP5VS3_FET

PP3V3_SUS_FET

PP5V_S0

CPUVCCIOS0_EN

CPUIMVP_VR_ON

DDRREG_EN

MEMVTT_EN

PP5V_S0

PVCCSA_EN

Q7801

PP1V5_S3RS0_FET

PP5V_SUS_FET

PP3V3_S3

PP3V3_S0_P1V8S0

P1V8_S0_EN

ENABLE

3.425V G3HOT

LT3470A

U6990

(PAGE 55)

1.05V

VCC

ISL95874

U7600

(PAGE 62)

CPU VCORE

VIN

MAX15119GTM

U7400

VR_ON

(PAGE 60)

VIN

1.5V

0.75V

TPS51916

U7300

(PAGE 59)

VCC

ISL95875

U7100

(PAGE 57)

Q7850

Q7860

P5V_S0_EN

PP5V_S4_1V05BTS0

TBT_EN_LC_ISOL

PP3V3_S0_P1V5S0

P1V5_S0_EN

MAX15053EWL

U7760

(PAGE 63)

PP3V3_SUS_P1V05SUSLDO

VOUT

CPUVCCIOS0_PGOOD

PGOOD

VOUT

IMON

IMONG PGOOD PGOODG

VLDOIN

VOUT1

VOUT2

PGOOD

VOUT

PGOOD

P5V_S3_EN

VIN

ISL8014A

U7720

(PAGE 63)

ISL8009B

U7770

(PAGE 63)

PP1V8_S0_REG

TPS720105

U7740

(PAGE 63)

PP3V42_G3H

R7640

SMC_CPU_ISENSE

CPUIMVP_IMON

CPUIMVP_IMONG

CPUIMVP_PGOOD CPUIMVP_AXG_PGOOD

PP1V5R1V35_S3

PP0V75_S0_DDRVTT

TP_DDRREG_PGOOD

PPVCCSA_S0_REG

PVCCSA_PGOOD

PP5V_S0_FET

PP1V05_S0_P1V05BTREG_R

VIN

PP1V5_S0_REG

PP1V05_SUS_LDO

PP1V05_S0

SMC_CPU_FSB_ISENSE

PP5V_S3_FET

PP5V_S0_VMON

PP1V5_S3RS0_VMON

PP1V05_S0_VMON

SMC_CPU_VSENSE

PPVCORE_S0_CPUPPVCORE_S0_CPU

SMC_CPU_VSENSE

PPVCORE_S0_AXG

SMC_GFX_VSENSE

CPUIMVP_AXG_PWM2

SMC PWRGD

SN0903048

(PAGE 39)

VDD

MAX17491

PWN

U7542

(PAGE 61)

P1V5S0_PGOOD

P1V8S0_PGOOD P5VS4_PGOOD

PVCCSA_PGOOD

CPUVCCIOS0_PGOOD

PP3V3_S0

VMON_Q2

VMON_Q3

VMON_Q4

U5010

PP5V_S0_CPUIMVP

U7960

ISL88042IRTEZ

(PAGE 67)

SMC_RESET_L

ALL_SYS_PWRGD

PPVCORE_S0_AXG

ALL_SYS_PWRGD

SMC_ONOFF_L

R7962

Panther-POINT

(PCH)

U1800

PM_PCH_PWROK

U7950

(PAGE 16~21)

CPU

U1000

SM_DRAMPWROK

UNCOREPWRGOOD

(PAGE 9~13)

SMC

PWRGD(P38)

S5_PWRGD

PM_SLP_S5_L

PM_SLP_S4_L

PM_SLP_S3_L

RSMRST_IN(P38)

PWR_BUTTON(P90)

SLP_S5_L(P38)

SLP_S4_L(P38)

SLP_S3_L(P38)

(PAGE 38)

SYNC_MASTER=K17_REF

PAGE TITLE

U4900

Power Block Diagram

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

PWRBTN#

SYS_RERST#

RSMRST#

PLTRST#

PROCPWRGD

DRAMPWROK

RESET*

RSMRST_OUT(P15)

99ms DLY

IMVP_VR_ON(P16)

SYSRST(PA2)

P17(BTN_OUT)

RES*

PM_PWRBTN_L

PM_SYSRST_L

PM_RSMRST_L

PLT_RERST_L

CPU_PWRGD

PM_MEM_PWRGD

PM_RSMRST_L

CPUIMVP_VR_ON

PM_SYSRST_L

PM_PWRBTN_L

SMC_RESET_L

SYNC_DATE=06/30/2009

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

3 OF 132

SHEET

3 OF 80

124578

SIZE

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

8 7 6 5 4 3

NOTICE OF PROPRIETARY PROPERTY:

PAGE

PAGE TITLE

SHEET

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SYNC_DATE=MASTER

SYNC_MASTER=MASTER

Revision History

<SCH_NUM>

4 OF 132

4 OF 80

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

8 7 6 5 4 3

NOTICE OF PROPRIETARY PROPERTY:

PAGE

PAGE TITLE

SHEET

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Bar Code Labels / EEE #’s

Alternate Parts

Module Parts

DDR3 SPD STRAPPINGS

Module Parts

D1 BOM GROUPS

BOM Variants

EEEE:F33G

[EEEE:F33G]

CRITICAL826-4393

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE:F2WR]

CRITICAL

826-4393

EEEE:F2WR

EEEE:F2WV

[EEEE:F2WV]

CRITICAL

826-4393

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

EEEE:F336

LBL,P/N LABEL,PCB,28MM X 6 MM

826-4393

[EEEE:F336]

CRITICAL826-4393

EEEE:F33H

[EEEE:F33H]

826-4393

[EEEE:F33F]

CRITICAL

EEEE:F33F

[EEEE:F33D]

826-4393 CRITICAL

EEEE:F33D

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE:F16N]

826-4393 CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

EEEE:F16N

EEEE:F16P

[EEEE:F16P]

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

826-4393

EEEE:F16V

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

826-4393

[EEEE:F16V]

EEEE:DV7Q

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL826-4393

[EEEE:DV7Q]

LBL,P/N LABEL,PCB,28MM X 6 MM

EEEE:F26J

[EEEE:F26J]

826-4393

CRITICAL

[EEEE:F26M]

LBL,P/N LABEL,PCB,28MM X 6 MM

826-4393 CRITICAL

EEEE:F26M

[EEEE:F26L]

826-4393

EEEE:F26L

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

EEEE:F2WT

[EEEE:F2WT]

826-4393 CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

EEEE:F26H

[EEEE:F26H]

826-4393

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE:F337]

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

826-4393

EEEE:F337

[EEEE:F338]

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

EEEE:F338

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

EEEE:DWNW

826-4393

[EEEE:DWNW]

[EEEE:F16M]

826-4393 CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

EEEE:F16M

CRITICAL

EEEE:DWP0

LBL,P/N LABEL,PCB,28MM X 6 MM

826-4393

[EEEE:DWP0]

EEEE:F2WQ

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

826-4393

[EEEE:F2WQ]

[EEEE:F339]

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

EEEE:F339

EEEE:F33C

[EEEE:F33C]

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

ALL

128S0264128S0364

Kemet alt to Sanyo

Panasonic alt to Sanyo

128S0303

ALL

128S0353

ALL

128S0311 128S0329

NEC ALT TO SANYO

ALL

376S0953 376S0958

RENESAS ALT TO FAIRCHILD

353S3237

TI ALT TO INTERSIL

353S2192

ALL

138S0722 138S0691

Multi alt to Samsung

ALL

376S0977

Diodes alt to Toshiba

376S0859

197S0487

Epson alt to TXC

197S0485

ALL

NDK alt to TXC

ALL

197S0485197S0484

ALL

197S0478

NDK alt to TXC

197S0486

376S0612376S1017

ALL

ROHM alt to Toshiba

376S0604

ALL

376S1053

Diodes alt to Fairchild

ALL

138S0677138S0624

Murata alt to Taiyo Yuden

ALL

138S0681 138S0638

Taiyo Yuden alt to Samsung

152S1703

Sumida alt to Cyntec

ALL

152S1701

371S0490

ALL

Diodes alt to NXP

371S0730

138S0709138S0727

ALL

Samsung alt to Murata

376S0820376S1080

ALL

Diodes alt to ON Semi

372S0186 372S0185

ALL

NXP alt to Diodes

ALL

128S0296

NEC alt to Sanyo

128S0363

376S0796

ALL

376S0903

Fairchild alt to Siliconix

ALL

740S0118

Littlefuse alt to Polytronic

740S0144

Cyntec alt to Vishay

152S1645 152S0461

ALL

155S0583155S0667

ALL MAG LAYERS ALT TO MURATA

ALL

Yageo alt to Cyntec

112S0254112S0274

ALL

Diodes to AOS

376S1113 376S1110

ALL

murata ALT TO MURATA

155S0367155S0588

103S0266

Yageo alt to Cyntec

103S0305

ALL

152S1539

ALL

152S1598

Cyntec alt to Toko

138S0725 138S0724

ALL

Samsung alt to Murata

376S0612

ROHM alt to Toshiba

376S0972

ALL

197S0480

Epson alt to NDK

197S0481

Epson alt to TXC

ALL

197S0486197S0479

826-4393

[EEEE:DWP2]

EEEE:DWP2

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

826-4393

CRITICAL

EEEE:DWNY

[EEEE:DWNY]

EEEE:F33N

CRITICAL826-4393

[EEEE:F33N]

[EEEE:F33J]

CRITICAL

826-4393

EEEE:F33J

D1_DEVEL:PVB

BOM Configuration

SYNC_DATE=MASTER

SYNC_MASTER=MASTER

826-4393

EEEE:F33Q

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE:F33Q]

EEEE:F33P

826-4393 CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE:F33P]

EEEE:F33M

826-4393 CRITICAL

[EEEE:F33M]

[EEEE:F33L]

EEEE:F33L

CRITICAL

826-4393

EEEE:F33K

CRITICAL

[EEEE:F33K]

826-4393

LBL,P/N LABEL,PCB,28MM X 6 MM

826-4393

085-4094

D1_COMMON

607-9189

CMN PTS,PCBA,MLB,D1

DEV BOM,MLB,D1

LBL,P/N LABEL,PCB,28MM X 6 MM

PCBA,2.6G,MICRON 8GB,MLB,D1

639-3887

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.6G,PCH_C1,EEEE:F33K,RAM_4G_MICRON_1600_S

PCBA,2.8G,MICRON 8GB,MLB,D1

639-3888

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.8G,PCH_C1,EEEE:F33F,RAM_4G_MICRON_1600_S

PCBA,2.9G,MICRON 8GB,MLB,D1

639-3847

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.9G,PCH_C1,EEEE:F2WQ,RAM_4G_MICRON_1600_S

PCBA,2.8G,MICRON 6GB,MLB,D1

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.8G,PCH_C1,EEEE:F336,RAM_6G_MICRON_CH0_1600_S

639-3880

PCBA,2.5G,MICRON 8GB,MLB,D1

639-3846

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.5G,PCH_C1,EEEE:F2WV,RAM_4G_MICRON_1600_S

PCBA,2.6G,MICRON 6GB,MLB,D1

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.6G,PCH_C1,EEEE:F33M,RAM_6G_MICRON_CH0_1600_S

639-3879

PCBA,2.8G,ELPIDA 6GB,MLB,D1

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.8G,PCH_C1,EEEE:F338,RAM_6G_ELPIDA_CH0_1600_S

639-3878

PCBA,2.6G,ELPIDA 8GB,MLB,D1

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.6G,PCH_C1,EEEE:F33J,RAM_4G_ELPIDA_1600_S

639-3885

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.8G,PCH_C1,EEEE:F33N,RAM_4G_ELPIDA_1600_S

PCBA,2.8G,ELPIDA 8GB,MLB,D1

639-3886

639-3877

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.6G,PCH_C1,EEEE:F33Q,RAM_6G_ELPIDA_CH0_1600_S

PCBA,2.6G,ELPIDA 6GB,MLB,D1

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.8G,PCH_C1,EEEE:F337,RAM_4G_HYNIX_1600_S

PCBA,2.8G,HYNIX 8GB,MLB,D1

639-3884

639-3883

PCBA,2.6G,HYNIX 8GB,MLB,D1

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.6G,PCH_C1,EEEE:F33D,RAM_4G_HYNIX_1600_S

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.8G,PCH_C1,EEEE:F33C,RAM_4G_SAMSUNG_35NM_1600_S

639-3882

PCBA,2.8G,SS 8GB,MLB,D1

639-3881

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.6G,PCH_C1,EEEE:F33G,RAM_4G_SAMSUNG_35NM_1600_S

PCBA,2.6G,SS 8GB,MLB,D1

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.8G,PCH_C1,EEEE:F339,RAM_6G_HYNIX_CH0_1600_S

639-3876

PCBA,2.8G,HYNIX 6GB,MLB,D1

639-3875

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.6G,PCH_C1,EEEE:F33L,RAM_6G_HYNIX_CH0_1600_S

PCBA,2.6G,HYNIX 6GB,MLB,D1

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.6G,PCH_C1,EEEE:F33H,RAM_6G_SAMSUNG_35NM_CH0_1600_S

639-3873

PCBA,2.6G,SS 6GB,MLB,D1

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.9G,PCH_C1,EEEE:F2WR,RAM_6G_MICRON_CH0_1600_S

639-3848

PCBA,2.9G,MICRON 6GB,MLB,D1

639-3874

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.8G,PCH_C1,EEEE:F33P,RAM_6G_SAMSUNG_35NM_CH0_1600_S

PCBA,2.8G,SS 6GB,MLB,D1

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.5G,PCH_C1,EEEE:F2WT,RAM_6G_MICRON_CH0_1600_S

639-3849

PCBA,2.5G,MICRON 6GB,MLB,D1

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.9G,PCH_C1,EEEE:F26H,RAM_4G_ELPIDA_1600_S

639-3771

PCBA,2.9G,ELPIDA 8GB,MLB,D1

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.5G,PCH_C1,EEEE:F26L,RAM_4G_ELPIDA_1600_S

639-3770

PCBA,2.5G,ELPIDA 8GB,MLB,D1

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.9G,PCH_C1,EEEE:F26J,RAM_6G_ELPIDA_CH0_1600_S

639-3772

PCBA,2.9G,ELPIDA 6GB,MLB,D1

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.9G,PCH_C1,EEEE:F16N,RAM_4G_HYNIX_1600_S

639-3696

PCBA,2.9G,HYNIX 8GB,MLB,D1

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.5G,PCH_C1,EEEE:F16V,RAM_4G_HYNIX_1600_S

639-3697

PCBA,2.5G,HYNIX 8GB,MLB,D1

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.5G,PCH_C1,EEEE:F26M,RAM_6G_ELPIDA_CH0_1600_S

639-3773

PCBA,2.5G,ELPIDA 6GB,MLB,D1

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.9G,PCH_C1,EEEE:F16M,RAM_4G_SAMSUNG_35NM_1600_S

639-3695

PCBA,2.9G,SS 8GB,MLB,D1

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.9G,PCH_C1,EEEE:DWNW,RAM_6G_HYNIX_CH0_1600_S

639-3291

PCBA,2.9G,HYNIX 6GB,MLB,D1

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.5G,PCH_C1,EEEE:F16P,RAM_4G_SAMSUNG_35NM_1600_S

639-3694

PCBA,2.5G,SS 8GB,MLB,D1

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.5G,PCH_C1,EEEE:DWP0,RAM_6G_HYNIX_CH0_1600_S

639-3290

PCBA,2.5G,HYNIX 6GB,MLB,D1

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.9G,PCH_C1,EEEE:DWNY,RAM_6G_SAMSUNG_35NM_CH0_1600_S

PCBA,2.9G,SS 6GB,MLB,D1

639-3289

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.5G,PCH_C1,EEEE:DWP2,RAM_6G_SAMSUNG_35NM_CH0_1600_S

PCBA,2.5G,SS 6GB,MLB,D1

639-3288

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170

333S0660

CRITICAL

IC,SDRAM,DDR3-1600,512MX8,78FBGA,MICRON

4G_MICRON_1600_S

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970

CRITICAL333S0660

6G_MICRON_CH0_1600_S

IC,SDRAM,DDR3-1600,512MX8,78FBGA,MICRON

U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170

333S0649 CRITICAL

6G_MICRON_CH0_1600_S

IC,SDRAM,DDR3-1600,256MX8,78FBGA,MICRON

333S0629

IC,SDRAM,DDR3-1600,512MX8,78FBGA,B-DIE,ELPIDA

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970

CRITICAL

6G_ELPIDA_CH0_1600_S

333S0625

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970

6G_HYNIX_CH0_1600_S

CRITICAL

IC,SDRAM,DDR3-1600,512MX8,78FBGA,HYNIX

333S0628

IC,SDRAM,DDR3-1600,256MX8,78FBGA,D-DIE,ELPIDA

U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170

6G_ELPIDA_CH0_1600_S

CRITICAL

333S0622

U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170

6G_HYNIX_CH0_1600_S

CRITICAL

IC,SDRAM,2GBIT,256MX8,DDR3-1600,78FBGA

IC,SDRAM,DDR3-1600,512MX8,78FBGA,D35,SAMSUNG

333S0624

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170

CRITICAL

4G_SAMSUNG_35NM_1600_S

IC,SDRAM,DDR3-1600,512MX8,78FBGA,D35,SAMSUNG

333S0624

CRITICAL

6G_SAMSUNG_35NM_CH0_1600_S

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970

IC,SDRAM,2GBIT,256MX8,DDR3-1600,78FBGA

333S0623

CRITICAL

6G_SAMSUNG_35NM_CH0_1600_S

U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170

333S0629

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170

CRITICAL

4G_ELPIDA_1600_S

IC,SDRAM,DDR3-1600,512MX8,78FBGA,B-DIE,ELPIDA

IC,SDRAM,DDR3-1600,512MX8,78FBGA,HYNIX

333S0625

CRITICAL

4G_HYNIX_1600_S

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170

CRITICAL333S0649

2G_MICRON_1600_S

IC,SDRAM,DDR3-1600,256MX8,78FBGA,MICRON

IC,SDRAM,DDR3-1600,256MX8,78FBGA,D-DIE,ELPIDA

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170

2G_ELPIDA_1600_S

CRITICAL

333S0628

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170

2G_SAMSUNG_35NM_1600_S

CRITICAL

IC,SDRAM,2GBIT,256MX8,DDR3-1600,78FBGA

333S0623

TBTRTR:B1

CRITICAL

IC,TBT,CR-4C,B1,PRQ,288FCBGA,12X12MM

U3600

338S1113

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170

2G_HYNIX_1600_S

CRITICAL

IC,SDRAM,2GBIT,256MX8,DDR3-1600,78FBGA

333S0622

U1800

PCH_C1

IC,PCH,PPT-MB SFF,PRQ,C1

337S4283

CRITICAL

PCH_C0

U1800

CRITICAL337S4235

IC,PCH,PPT-MB SFF,P-QS,C0

IC,PCH,PPT-MB SFF,ES2,B0

PCH_ES2

U1800

337S4180 CRITICAL

IVB,S R0MU,PRQ,L1,2.9,35W,2+2,1.25,4M,BGA

CRITICAL

CPU_IVB_2C_2.9G

337S4265

U1000

IVB,S R0MY,PRQ,L1,2.6,35W,2+2,1.2,3M,BGA

CPU_IVB_2C_2.6G

CRITICAL337S4338

U1000

CPU_IVB_2C_2.8G

CRITICAL337S4339

IVB,S R0MU,PRQ,L1,2.8,35W,2+2,1.2,3M,BGA

CRITICAL

U1000

CPU_IVB_2C_2.5G

337S4264

IVB,S R0N0,PRQ,L1,2.5,35W,2+2,1.1,3M,BGA

CPU_IVB_2C_2.6G_QS

CRITICAL

IVB,QC96,QS,L1,2.6,35W,2+2,1.2,3M,BGA

U1000

337S4300

CPU_IVB_2C_2.8G_QS

IVB,QC94,QS,L1,2.8,35W,2+2,1.2,3M,BGA

CRITICAL

U1000

337S4302

CRITICAL

337S4294

IVB,QC4M,QS,L1,2.9,35W,2+2,1.25,4M,BGA

CPU_IVB_2C_2.9G_QS

U1000

CRITICAL

U1000

337S4292

CPU_IVB_2C_2.5G_QS

IVB,Q4CT,QS,L1,2.5,35W,2+2,1.1,3M,BGA

U1000

CPU_IVB_2C_2.3G_ES2

337S4181

CRITICAL

IVB,QBP0,ES2,K0,2.3,35W,2+2,1.0,3M,BGA

CPU_IVB_2C_2.6G_ES2

337S4182

U1000

CRITICAL

IVB,QBP0,ES2,K0,2.6,35W,2+2,1.05,4M,BGA

IC,SDRAM,2GBIT,256MX8,DDR3-1600,78FBGA

6G_SAMSUNG_28NM_CH0_1600_S

CRITICAL

333S0623

U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170

IC,SDRAM,DDR3-1600,512MX8,78FBGA,C-DIE,SAMSUNG

6G_SAMSUNG_28NM_CH0_1600_S

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970

CRITICAL

333S0642

IC,SDRAM,DDR3-1600,512MX8,78FBGA,C-DIE,SAMSUNG

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170

4G_SAMSUNG_28NM_1600_S

CRITICAL

333S0642

2G_HYNIX_1600_S,RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:L

RAM_2G_HYNIX_1600_S

2G_SAMSUNG_35NM_1600_S,RAMCFG3:H,RAMCFG2:H,RAMCFG1:L,RAMCFG0:H

RAM_2G_SAMSUNG_1600_S

6G_HYNIX_CH0_1600_S,RAMCFG3:H,RAMCFG2:H,RAMCFG1:L,RAMCFG0:L

RAM_6G_HYNIX_CH0_1600_S

6G_SAMSUNG_28NM_CH0_1600_S,RAMCFG3:H,RAMCFG2:L,RAMCFG1:H,RAMCFG0:H

RAM_6G_SAMSUNG_28NM_CH0_1600_S

6G_ELPIDA_CH0_1600_S,RAMCFG3:H,RAMCFG2:L,RAMCFG1:H,RAMCFG0:L

RAM_6G_ELPIDA_CH0_1600_S

6G_MICRON_CH0_1600_S,RAMCFG3:H,RAMCFG2:L,RAMCFG1:L,RAMCFG0:L

RAM_6G_MICRON_CH0_1600_S

4G_MICRON_1600_S,RAMCFG3:L,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H

RAM_4G_MICRON_1600_S

6G_SAMSUNG_35NM_CH0_1600_S,RAMCFG3:L,RAMCFG2:H,RAMCFG1:H,RAMCFG0:L

RAM_6G_SAMSUNG_35NM_CH0_1600_S

4G_SAMSUNG_35NM_1600_S,RAMCFG3:L,RAMCFG2:H,RAMCFG1:L,RAMCFG0:H

RAM_4G_SAMSUNG_35NM_1600_S

4G_SAMSUNG_28NM_1600_S,RAMCFG3:L,RAMCFG2:L,RAMCFG1:H,RAMCFG0:L

RAM_4G_SAMSUNG_28NM_1600_S

2G_MICRON_1600_S,RAMCFG3:L,RAMCFG2:L,RAMCFG1:H,RAMCFG0:H

RAM_2G_MICRON_1600_S

4G_ELPIDA_1600_S,RAMCFG3:L,RAMCFG2:H,RAMCFG1:L,RAMCFG0:L

RAM_4G_ELPIDA_1600_S

2G_ELPIDA_1600_S,RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:H

RAM_2G_ELPIDA_1600_S

4G_HYNIX_1600_S,RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:L

RAM_4G_HYNIX_1600_S

D1_DEVEL:PVB

ALTERNATE,IVB_PPT_XDP,VREFDQ:M1_M3,VREFCA:LDO

IVB_PPT_XDP

XDP,XDP_CONN,XDP_CPU:BPM,XDP_PCH

D1_DEVEL:ENG

ALTERNATE,IVB_PPT_XDP,LOADISNS:YES,S0PGOOD_ISL,DDRVREF_DAC,VREFDQ:M1_M3,VREFCA:LDO_DAC

D1_BLANK

D1_PROGPARTS

SMC_PROG:PVB,TBTROM:PROG,BOOTROM_PROG:PVB,TPAD_PSOC:PROG

D1_PVB

LOADISNS:NO,LCDBKLT:PROD,KBDBKLT:PROD

D1_COMMON2

EDP:YES,PPDDR:1V35,LPCPLUS_CONN:YES,LPCPLUS_R:YES,CAPS:INT,BTPWR:S4,SKIP_5V3V3:AUDIBLE,TPAD_5V_LDO:S5,SMS

D1_COMMON

ALTERNATE,COMMON,D1_COMMON1,D1_COMMON2,D1_PROGPARTS,D1_PVB

D1_COMMON1

CPUMEM:S0,SMC_DEBUG_YES,TBTBST:Y,TBTRTR:B1,TBTHV:P15V,HUB_2NONREM,USBHUB:2512B,AXG_PHASE2,TBTISNS:YES

<SCH_NUM>

5 OF 132

5 OF 80

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

8 7 6 5 4 3

NOTICE OF PROPRIETARY PROPERTY:

PAGE

PAGE TITLE

SHEET

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

PD Module Parts

DEVELOPMENT/BASE BOMs

EFI ROM

SMC

Programmables - All builds

946-4350

D1 MLB LOCTITE UV GLUE 190024/S 0.24G

STDOFF-1.9D2.93H-TH-0.85-1.2

STDOFF-1.80D1.53H-SM

LBL,PART CONFIG,BOARDS,D2

EDGE_BOND

CRITICAL

825-7841 CONFIG_LABEL

IC,TP PSOC,V224,PVB,D1

341S3670

IC,EFI,ROM,FSB2, D1

IC,EFI,ROM,PVB, D1

64 MBIT SPI SERIAL DUAL I/O FLASH,Macronix

IC,TP PSOC,QFN,BLANK

IC,EEPROM,SERIAL,8KB,SOIC

IC,SMC12-A3,LX4FS1AH5BBCIGA3

341S3528

J6950_65860-1529

CRITICAL

J6950_64860-1530 CRITICAL

J6950_63860-1533

STDOFF,BMU,TOPSIDE,D1,SM

CRITICAL

341S3668

IC,EEPROM,CR,V14.1,D1 PVB

341S3406

IC,SMC,DEVELOPMENT-PVB,D1

SMC_PROG:PVB

341S3667

BOOTROM_PROG:PVB

BASE BASE_BOMCRITICAL

D1 MLB BASE BOM

607-9189

DEVEL

CRITICAL

DEVEL_BOM

D1 MLB DEVELOPMENT BOM

085-4094

SYNC_DATE=MASTER

BOM Configuration

SYNC_MASTER=MASTER

U4900

CRITICAL

IC,SMC,DEVELOPMENT-FSB,D1

SMC_PROG:FSB

341S3405

U6100

335S0809

BOOTROM_BLANK

CRITICAL

64 MBIT SPI SERIAL DUAL I/O FLASH,Numonyx

335S0803

U6100

BOOTROM_BLANK

CRITICAL

TPAD_PSOC:PROG

U5701

337S2983

TPAD_PSOC:BLANK

CRITICAL

U5701

TBTROM:PROG

CRITICAL

U3690

TBTROM:BLANK

335S0865 CRITICAL

SMC_BLANK

U4900

CRITICAL

338S1098

SMC_SOCKET

998-3919 CRITICAL

SOCKET, SMC12

J4900

341S3650

IC,EFI,ROM,FSB, D1

BOOTROM_PROG:FSB

U6100

CRITICAL

BOOTROM_PROG:PIB2

IC,EFI,ROM,PIB2, D1

341S3636

U6100

CRITICAL

BOOTROM_PROG:FSB2

341SXXXX

CRITICAL

U6100

CRITICAL

U6100

BOOTROM_PROG:PIB

CRITICAL

U6100

IC,EFI,ROM,PIB, D1

341S3603

BOOTROM_PROG:PROTO

341S3571

IC,EF,ROM,PROTO1,D1

U6100

CRITICAL

U4900

CRITICAL

341S3404

IC,SMC,DEVELOPMENT-PIB,D1

U4900

CRITICAL

SMC_PROG:PIB

CRITICAL

U4900

SMC_PROG:PROTO

IC,SMC12,PROTO1,D1

<SCH_NUM>

6 OF 132

6 OF 80

PP PP PP PP

PP PP PP PP PP PP PP PP PP PP

PP PP

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

8 7 6 5 4 3

NOTICE OF PROPRIETARY PROPERTY:

PAGE

PAGE TITLE

SHEET

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PCH ALIASES

Functional Test Points

J6801 (2 MIC CONN)

J6701 (AUDIO JACK CONN)

NO_TEST

NC NO_TESTs

S2 CAMERA PCIE SIGNALS

J4410 (RIO FLEX CONN)

J6950 (MAIN BATT CONN)

per Fan

U1000 CHARZ TPS

U4900 CHARZ TPS

J5713 (KEY BOARD CONN)

J3502 (ALS/CAMERA CONN)

J5815 (KBD BACKLIGHT CONN)

J5650 (LEFT FAN CONN)

per Fan

U1800 CHARZ TPS

J5660 (RIGHT FAN CONN)

5 TPs

J4400 (RIO CABLE CONN)

J9000 (EDP CONN)

J3401 & J3402 (AIRPORT/BT/CAMERA CONN)

2 TP needed

J6802 (AUDIO LEFT SPEAKER CONN)

J6803 (AUDIO RIGHT SPEAKER CONN)

3 TPs

6 TPs

J5100 (LPC + SPI CONN)

FUNC_TEST

4 TPs

J6900 (DC POWER CONN)

J5700 (IPD FLEX CONN)

FUNC_TEST

J4600 (LEFT USB CONN)

ICT Test Points

POWER RAILS

FUNC_TEST

J4500 (SSD/HDD FLEX CONN)

CPU NO_TESTs

I1493

I1502

I1503

I1504

I1511

I1512

I1513

I1514

I1515

I1516

I1517

I1518

I1519

I1520

I1522

I1523

I1524

I1525

I1526

I1527

I1528

I1529

I1531

I1533

I1534

I1535

I1536

I1538

I1540

I1541

I1542

I1543

I1544

I1545

I1547

I1566

I1567

I1569

I1571

I1584

I1585

I1586

I1601

I1602

I1603

I1604

I1605

I1606

I1607

I1608

I1609

I1610

I1611

I1612

I1613

I1614

I1615

I1616

I1617

I1618

I1619

I1620

I1621

I1622

I1623

I1624

I1625

I1626

I1627

I1628

I1629

I1630

I1631

I1632

I1633

I1634

I1635

I1636

I1637

I1638

I1639

I1640

I1644

I1646

I1647

I1648

I1649

I1651

I1652

I1653

I1654

I1655

I1656

I1657

I1658

I1659

I1660

I1661

I1662

I1663

I1664

I1668

I1669

I1670

I1671

I1672

I1673

I1674

I1675

I1676

I1677

I1678

I1679

I1680

I1681

I1682

I1683

I1684

I1685

I1709

I1710

I1711

I1712

I1713

I1714

I1715

I1716

I1717

I1718

I1719

I1720

I1721

I1722

I1723

I1724

I1725

I1726

I1731

I1806

I1808

I1809

I1811

I1812

I1814

I1815

I1817

I1818

I1820

I1821

I1822

I1823

I1824

I1825

I1826

I1827

I1828

I1829

I1830

I1831

I1834

I1835

I1836

I1837

I1838

I1839

I1840

I1841

I1842

I1843

I1844

I1845

I1846

I1847

I1848

I1849

I1850

I1851

I1852

I1853

I1854

I1855

I1856

I1857

I1858

I1859

I1860

I1861

I1862

I1863

I1864

I1865

I1866

I1867

I1868

I1869

I1870

I1871

I1872

I1873

I1874

I1875

I1876

I1877

I1878

I1879

I1880

I1881

I1884

I1885

I1886

I1887

I1888

I1889

I1892

I1893

I1894

I1895

I1896

I1897

I1899

I1901

I1902

I1903

I1904

I1905

I1906

I1909

I1910

I1911

I1912

I1913

I1914

I1915

I1916

I1917

P2MM

I1919

I1920

I1921

I1922

I1923

I1924

I1925

I1926

I1927

I1928

I1929

I1930

I1931

I1932

P2MM P2MM

SM SM

P2MM

P2MM P2MM

SM SM

P2MM P2MM

SM SM

P2MM

I1954

I1955

I1956

I1957

I1958

I1959

I1960

I1961

I1962

I1963

I1964

I1965

I1966

I1967

I1968

I1969

I1970

I1971

I1972

P2MM

I1974

I1975

I1976

P2MM

SM SM

P2MM

I1979

I1980

P2MM P2MM

I1983

I1984

I1985

I1986

I1987

I1988

I1989

I1990

Functional / ICT Test

SYNC_DATE=MASTERSYNC_MASTER=MASTER

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

SYS_DETECT_L_R

PCIE_CLK100M_TBT_N

DMI_S2N_P<0>

AUD_SPDIF_OUT_JACK

TRUE

PCH_VSS_NCTF<19>

TP_SDVO_INTP

TP_PCI_PME_L

TRUE

NC_ISNS_WLANN

MAKE_BASE=TRUE

TRUE

NC_ISNS_WLANP

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_ISNS_LCD_PANELN

NC_PCI_PME_L

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_ISNS_LCDBKLTP

TRUE

TP_PCI_CLK33M_OUT3

NC_ISNS_LCDBKLTN

MAKE_BASE=TRUE

TRUE

TP_SDVO_INTN

TP_SDVO_STALLP

TP_SDVO_STALLN

TP_SDVO_TVCLKINP

TP_SDVO_TVCLKINN

TP_HDA_SDIN3

TP_CRT_IG_VSYNC

TP_CRT_IG_RED

LED_RETURN_3

TRUE

PP3V3_S5

TRUE

TP_SMS_INT2

TRUE

MEM_A_DQ<24..21>

TP_LPC_DREQ1_L

NC_SDVO_STALLN

MAKE_BASE=TRUE

TRUE

TP_HDA_SDIN1

TP_SATA_D_R2D_CP

TP_SATA_C_R2D_CN

TP_SATA_C_D2RN

TP_TBT_PCIE_RESET0_L

TRUE

PP1V05_S0

TRUE

WS_KBD3

TRUE

WS_KBD12

TRUE

MAKE_BASE=TRUE

NC_ISNS_LCD_PANELP

TRUE

MAKE_BASE=TRUE

NC_PCIE_5_D2RN

TRUE

MAKE_BASE=TRUE

NC_PCIE_5_D2RP

TRUE

MAKE_BASE=TRUE

NC_PCIE_5_R2D_CN

TRUE

MAKE_BASE=TRUE

NC_PCIE_5_R2D_CP

TRUE

MAKE_BASE=TRUE

NC_PCIE_6_D2RP

TRUE

MAKE_BASE=TRUE

NC_PCIE_6_D2RN

Z2_SCLK

TRUE

TP_PCH_TP23

NC_PCI_CLK33M_OUT3

TRUE MAKE_BASE=TRUE

NC_SDVO_INTP

TRUE MAKE_BASE=TRUE

NC_SDVO_INTN

MAKE_BASE=TRUE

TRUE

NC_SDVO_STALLP

TRUE MAKE_BASE=TRUE

NC_SDVO_TVCLKINP

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

NC_SDVO_TVCLKINN

TRUE

NC_HDA_SDIN3

MAKE_BASE=TRUE

TP_HDA_SDIN2 NC_HDA_SDIN2

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

NC_HDA_SDIN1

NC_CRT_IG_VSYNC

MAKE_BASE=TRUE

TRUE

TP_CRT_IG_HSYNC

MAKE_BASE=TRUE

TRUE

NC_CRT_IG_HSYNC

TP_CRT_IG_DDC_DATA

TRUE

NC_CRT_IG_DDC_DATA

MAKE_BASE=TRUE

TP_CRT_IG_DDC_CLK NC_CRT_IG_DDC_CLK

TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE

TRUE

NC_CRT_IG_RED

TP_CRT_IG_GREEN NC_CRT_IG_GREEN

MAKE_BASE=TRUE

TRUE

TP_SATA_F_R2D_CP NC_SATA_F_R2D_CP

MAKE_BASE=TRUE

TRUE

TP_SATA_F_R2D_CN NC_SATA_F_R2D_CN

MAKE_BASE=TRUE

TRUE

TP_SATA_F_D2RP NC_SATA_F_D2RP

MAKE_BASE=TRUE

TRUE

TP_CRT_IG_BLUE NC_CRT_IG_BLUE

MAKE_BASE=TRUE

TRUE

TP_SATA_E_R2D_CN NC_SATA_E_R2D_CN

MAKE_BASE=TRUE

TRUE

TP_SATA_E_R2D_CP NC_SATA_E_R2D_CP

MAKE_BASE=TRUE

TRUE

TP_SATA_F_D2RN NC_SATA_F_D2RN

MAKE_BASE=TRUE

TRUE

TP_SATA_E_D2RP NC_SATA_E_D2RP

MAKE_BASE=TRUE

TRUE

TP_SATA_E_D2RN NC_SATA_E_D2RN

MAKE_BASE=TRUE

TRUE

TP_SATA_D_D2RP NC_SATA_D_D2RP

MAKE_BASE=TRUE

TRUE

TP_SATA_D_D2RN NC_SATA_D_D2RN

MAKE_BASE=TRUE

TRUE

TP_SATA_C_R2D_CP NC_SATA_C_R2D_CP

MAKE_BASE=TRUE

TRUE

TP_SATA_D_R2D_CN NC_SATA_D_R2D_CN

MAKE_BASE=TRUE

TRUE

NC_SATA_D_R2D_CP

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_SATA_C_D2RN

TRUE

TP_SATA_C_D2RP NC_SATA_C_D2RP

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_SATA_C_R2D_CN

TRUE

TP_PCIE_CLK100M_PEBP NC_PCIE_CLK100M_PEBP

TRUE MAKE_BASE=TRUE

NC_PCIE_8_R2D_CP

MAKE_BASE=TRUE

TRUE

NC_PCIE_8_R2D_CN

MAKE_BASE=TRUE

TRUE

NC_PCIE_8_D2RN

MAKE_BASE=TRUE

TRUE

NC_PCIE_8_D2RP

MAKE_BASE=TRUE

TRUE

NC_PCIE_7_R2D_CP

MAKE_BASE=TRUE

TRUE

NC_PCIE_7_R2D_CN

MAKE_BASE=TRUE

TRUE

TP_PCIE_CLK100M_PEBN NC_PCIE_CLK100M_PEBN

MAKE_BASE=TRUE

TRUE

TP_PCIE_CLK100M_PE4P NC_PCIE_CLK100M_PE4P

TRUE MAKE_BASE=TRUE

TP_PCIE_CLK100M_PE4N NC_PCIE_CLK100M_PE4N

TRUE MAKE_BASE=TRUE

NC_PCIE_7_D2RN

MAKE_BASE=TRUE

TRUE

NC_PCIE_7_D2RP

MAKE_BASE=TRUE

TRUE

NC_PCIE_6_R2D_CP

MAKE_BASE=TRUE

TRUE

NC_PCIE_6_R2D_CN

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

NC_PCIE_CLK100M_CAMERAP

PCIE_CLK100M_EXCARD_P

NC_PCIE_CAMERA_R2D_CP

MAKE_BASE=TRUE TRUE

PCIE_EXCARD_R2D_C_P

MAKE_BASE=TRUE

TRUE

NC_PCIE_CLK100M_CAMERAN

PCIE_CLK100M_EXCARD_N

NC_PCIE_CAMERA_R2D_CN

MAKE_BASE=TRUE TRUE

PCIE_EXCARD_R2D_C_N

NC_PCIE_CAMERA_D2RN

MAKE_BASE=TRUE

TRUE

PCIE_EXCARD_D2R_P

NC_PCIE_CAMERA_D2RP

MAKE_BASE=TRUE

TRUE

PCIE_EXCARD_D2R_N

DMI_S2N_N<0>

WS_KBD11

TRUE

WS_KBD16_NUM

FAN_RT_TACH

TRUE

PM_SLP_S4_L

TRUE

AP_RESET_CONN_L

SMBUS_SMC_1_S0_SCL

TRUE

DMI_CLK100M_CPU_P DMI_CLK100M_CPU_N

PCIE_TBT_D2R_P<0> PCIE_TBT_D2R_N<0>

DMI_N2S_N<0>

PCIE_ENET_D2R_P

LPC_AD<0>

TRUE

WS_KBD14

WS_KBD9

TRUE

WS_KBD7

TRUE

WS_KBD5

TRUE

PP3V42_G3H

TRUE

PP5V_S4

TRUE

PP3V3_S4

TRUE

SMBUS_SMC_2_S3_SCL

TRUE

PP5V_S3_ALSCAMERA_F

TRUE

PP1V5_S0

TRUE

HDMI_IG_DDC_DATA

SD_PWR_EN

TRUE

PCIE_CLK100M_TBT_P

LPC_AD<1>

FDI_DATA_P<4>

FDI_DATA_N<4> PCIE_AP_D2R_P PCIE_AP_D2R_N

PPVBAT_G3H_CONN

TRUE

PP5V_S0

TRUE

ENET_CLKREQ_L

TRUE

SMBUS_SMC_1_S0_SDA

TRUE

KBDLED_CATHODE2

PCIE_ENET_D2R_N

DMI_N2S_P<0>

FDI_DATA_N<0>

SYSDET1

TRUE

AUD_DMIC_SDA1

LPC_CLK33M_SMC

LPC_FRAME_L

LPC_AD<3>

LPC_AD<2>

AUD_SPDIF_IN

TP_AUD_MIC_INRP

TP_DP_TBTSRC_ML_CP<3> TP_DP_TBTSRC_ML_CN<3>

PCIE_CLK100M_EXCARD_N

TP_XDP_PCH_OBSFN_A<0>

TP_AUD_CODEC_MICBIAS

TP_CLINK_CLK

TP_DP_TBTSRC_ML_CP<0>

TP_DP_TBTSRC_ML_CP<1>

TP_SPI_CS1_L TP_PCH_GPIO8 TP_PCH_STRP_BBS1

TP_PCI_CLK33M_OUT2

TP_PCIE_CLK100M_PEGAP

TP_PCIE_CLK100M_PEGAN

TP_PCH_STRP_ESI_L

TP_PM_SLP_A_L

TP_SMC_MPM5_LED_CHG

TP_PPVOUT_PCH_DCPSUSBYP TP_SMC_MPM5_LED_PWR

TP_DP_TBTSRC_ML_CN<1>

TP_DP_TBTSRC_ML_CN<2>

TP_TBT_PCIE_RESET3_L

TP_TBT_PCIE_RESET2_L

TP_TBT_MONDC1

TP_XDP_PCH_HOOK5 TP_XDP_PCH_OBSFN_B<0> TP_XDP_PCH_OBSFN_B<1>

TP_XDP_PCH_OBSFN_D<0>

TP_XDP_PCH_OBSFN_A<1>

TP_XDP_PCH_TRST_L

TP_XDP_PCH_OBSFN_D<1>

TP_1V05_S0_PCH_VCCAPLLEXP

TP_AUD_MIC_INRN

TP_BKL_FAULT

TP_LPC_DREQ0_L

TP_CLINK_RESET_L

TP_XDP_PCH_HOOK4

TP_DP_TBTSRC_AUXCH_CN

TP_DP_TBTSRC_AUXCH_CP

TP_CLINK_DATA

TP_DP_TBTSRC_ML_CN<0>

TP_TBT_XTAL25OUT

TP_TBT_MONDC0

TP_DP_TBTSRC_ML_CP<2>

TP_TBT_PCIE_RESET1_L

FDI_DATA_P<0>

PP0V75_S0_DDRVTT

TRUE

PP5V_S0_HDD_FLT

TRUE

SMC_OOB1_RX_L

TRUE

SMC_OOB1_TX_L

TRUE

PP3V3_S0_SSD_FLT

TRUE

PP3V3_WLAN_F

TRUE

PCIE_AP_D2R_N

TRUE

PCIE_AP_D2R_P

TRUE

PP5V_S3

DMI_N2S_P<3..1>

TRUE

TBTAPWRSW_ISET_S0

TRUE

TBT_A_R2D_P<1..0>

TRUE

TBT_A_D2R_N<0>

TBT_B_D2R_P<0>

TRUE

PCIE_AP_R2D_N

TRUE

PCIE_AP_R2D_P

TRUE MAKE_BASE=TRUE

NC_TBT_MONDC0

NC_DP_TBTSRC_AUXCH_CP

MAKE_BASE=TRUE

TRUE

SMC_ONOFF_L

TRUE

CON_DMIC_CLK

USB_LT1_P

TRUE

USB_LT1_N

TRUE

SMC_KBDLED_PRESENT_L

TRUE

SYSDET_3_4

TRUE

CON_DMIC_PWR

TRUE

CON_DMIC_SDA1

TRUE

SMBUS_SMC_5_G3_SDA

TRUE

SMBUS_SMC_5_G3_SCL

TRUE

PP5V_S3_LTUSB_A_F

TRUE

PCH_VSS_NCTF<19>

TRUE

WS_KBD10

TRUE

WS_KBD15_CAP

TRUE

PCIE_TBT_D2R_P<3..1>

NC_XDP_PCH_HOOK4

MAKE_BASE=TRUE

TRUE

USB_EXTB_N

TRUE

PP3V3_S3

TRUE

SMBUS_SMC_2_S3_SDA

WS_KBD4

TRUE

WS_KBD13

TRUE

PM_SLP_S3_L

TRUE

NC_PCH_GPIO8

TRUE

MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE

NC_SPI_CS1_L

TRUE

PSOC_MOSI

TRUE

MEM_A_DQ<63..58>

TRUE

TBT_A_D2R_P<1>

TBT_A_D2R_P<0>

TRUE

DMI_S2N_N<3..1>

DMI_S2N_P<3..1>

TRUE

PCIE_TBT_D2R_N<3..1>

PP5V_S5

TRUE

PPBUS_G3H

TRUE

PPDCIN_G3H

TRUE

WS_KBD_ONOFF_L

TRUE

WS_KBD23

TRUE

WS_KBD22

TRUE

WS_KBD21

TRUE

WS_KBD20

TRUE

SMC_TCK

TRUE

HDMI_IG_DATA_C_N<2..0>

TRUE

HDMI_IG_DATA_C_P<2..0>

TRUE

HDMI_IG_CLK_C_P

TRUE

HDMI_IG_CLK_C_N

TRUE

SPIROM_USE_MLB

TRUE

MEM_A_DQ<42..34>

TRUE

SDCONN_STATE_CHANGE_SMC

LPC_AD<3>

TRUE

NC_MEM_EVENT_L

TRUE

MEM_B_DQ<63..59>

TRUE

MEM_B_DQ<35..27> MEM_B_DQ<40..37>

TRUE TRUE

MEM_B_DQ<47..42>

TRUE

MEM_B_DQ<57..49>

TRUE

MEM_B_DQ<25..21>

TRUE

MEM_B_DQ<2..0>

TRUE

MEM_B_DQ<13..4>

TRUE

MEM_B_DQ<19..15>

MEM_A_DQ<54..44>

TRUE

MEM_A_DQ<56>

TRUE

MEM_A_DQ<32..26>

TRUE

MEM_A_DQ<19..14>

TRUE

MEM_A_DQ<12..2>

MEM_A_DQ<0>

TRUE

PCIE_TBT_D2R_C_N<3..1>

TRUE

PCIE_TBT_D2R_C_P<3..1>

TRUE

TBT_B_D2R_N<0>

TBT_B_D2R_N<1>

TRUE

TBT_B_D2R_P<1>

TBT_B_D2R_C_N<1>

TRUE

TBT_B_R2D_N<1..0>

TRUE

TBT_B_D2R_C_N<0> TBT_B_D2R_C_P<1>

TRUE

TBT_B_R2D_P<1..0>

TRUE

TBT_B_R2D_C_N<1..0>

TRUE

TBT_A_D2R_C_P<0> TBT_A_D2R_C_N<0>

TRUE

TBT_A_D2R_N<1>

TRUE

TBT_A_D2R_C_N<1>

TRUE

TBT_A_D2R_C_P<1>

TBT_A_R2D_N<1..0>

TRUE

TBT_A_R2D_C_N<1..0>

TRUE

TBT_A_R2D_C_P<1..0>

NC_LPC_DREQ0_L

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_BKL_FAULT

TRUE

AUD_SPDIF_IN

MAKE_BASE=TRUE

TRUE

NC_AUD_MIC_INRP

MAKE_BASE=TRUE

TRUE

NC_AUD_CODEC_MICBIAS

TRUE MAKE_BASE=TRUE

NC_1V05_S0_PCH_VCCAPLLEXP

NC_XDP_PCH_OBSFN_D<1>

TRUE MAKE_BASE=TRUE TRUE

NC_XDP_PCH_TRST_L

MAKE_BASE=TRUE

NC_XDP_PCH_OBSFN_A<1>

MAKE_BASE=TRUE

TRUE

NC_XDP_PCH_OBSFN_D<0>

TRUE MAKE_BASE=TRUE

NC_XDP_PCH_OBSFN_A<0>

MAKE_BASE=TRUE

TRUE

NC_XDP_PCH_OBSFN_B<1>

MAKE_BASE=TRUE

TRUE

NC_XDP_PCH_OBSFN_B<0>

TRUE MAKE_BASE=TRUE

TRUE

NC_XDP_PCH_HOOK5

MAKE_BASE=TRUE

DMI_N2S_N<3..1>

TRUE

PP5V_S3_ALSCAMERA_F

TRUE

PM_SYSRST_L

TRUE

LPC_AD<2>

TRUE

LPCPLUS_GPIO

TRUE

LPC_FRAME_L

TRUE

SMBUS_SMC_2_S3_SDA

TRUE

AP_RESET_CONN_L

TRUE

SMC_TDO

TRUE

TP_SMC_TRST_L

TRUE TRUE

TP_SMC_MD1

TRUE

SPI_ALT_MISO

PM_CLKRUN_L

TRUE

KBDLED_CATHODE1

TRUE

SMBUS_PCH_DATA

SPI_ALT_CS_L

TRUE

SPI_ALT_MOSI

TRUE

LPCPLUS_RESET_L

TRUE

PCIE_WAKE_L

TRUE

HDMI_IG_DDC_CLK

Z2_KEY_ACT_L

TRUE

Z2_MOSI

TRUE

Z2_HOST_INTN PP5V_S4_CUMULUS

TRUE

TBTAPWRSW_ISET_V3P3

TRUE

TBTBPWRSW_ISET_S3

TRUE

TBTBPWRSW_ISET_S0_R

TRUE

TBTBPWRSW_ISET_V3P3

TDM_ONEWIRE_MPM

TRUE

PSOC_SCLK

TRUE

WS_KBD8

PICKB_L

TRUE

PSOC_F_CS_L

TRUE

MAKE_BASE=TRUE

TRUE

NC_DP_TBTSRC_ML_CN<3>

TRUE MAKE_BASE=TRUE

NC_DP_TBTSRC_ML_CP<1>

MAKE_BASE=TRUE

TRUE

NC_DP_TBTSRC_ML_CN<2>

MAKE_BASE=TRUE

TRUE

NC_DP_TBTSRC_ML_CP<0>

MAKE_BASE=TRUE

TRUE

NC_DP_TBTSRC_ML_CN<1>

MAKE_BASE=TRUE

TRUE

NC_DP_TBTSRC_ML_CN<0>

NC_DP_TBTSRC_AUXCH_CN

MAKE_BASE=TRUE

TRUE

NC_PPVOUT_PCH_DCPSUSBYP

TRUE MAKE_BASE=TRUE

NC_PM_SLP_A_L

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_PCH_STRP_ESI_L

TRUE MAKE_BASE=TRUE

NC_PCIE_CLK100M_PEGAN

TRUE MAKE_BASE=TRUE

NC_PCIE_CLK100M_PEGAP

NC_PCH_STRP_BBS1

MAKE_BASE=TRUE

TRUE

PP3V3_S3

TRUE

PP3V3_S5_AVREF_SMC

TRUE

PP3V42_G3H

TRUE

PP5V_S0

TRUE

LED_RETURN_5

TRUE

Z2_CS_L

MAKE_BASE=TRUE

TRUE

NC_TBT_XTAL25OUT

MAKE_BASE=TRUE

TRUE

NC_TBT_PCIE_RESET3_L

MAKE_BASE=TRUE

NC_TBT_PCIE_RESET2_L

TRUE

MAKE_BASE=TRUE

TRUE

NC_TBT_PCIE_RESET1_L

MAKE_BASE=TRUE

TRUE

NC_TBT_PCIE_RESET0_L

MAKE_BASE=TRUE

TRUE

NC_TBT_MONDC1

LED_RETURN_6

TRUE

PP3V3_S0

TRUE

PCIE_CLK100M_AP_CONN_N

PP3V42_G3H

TRUE

PPVTTDDR_S3

TRUE

PP5V_S0

NC_LPC_DREQ1_L

MAKE_BASE=TRUE TRUE

WS_KBD1

TRUE

WS_LEFT_SHIFT_KBD

TRUE

MAKE_BASE=TRUE

NC_CLINK_RESET_L

TRUE

MAKE_BASE=TRUE

NC_CLINK_DATA

TRUE MAKE_BASE=TRUE

NC_CLINK_CLK

WS_KBD2

TRUE

WS_LEFT_OPTION_KBD

TRUE

PCIE_CLK100M_AP_CONN_P

AP_CLKREQ_Q_L

TRUE

PP3V3_WLAN_F

USB_CAMERA_CONN_N

TRUE

LPC_CLK33M_LPCPLUS

TRUE

LPC_AD<0>

TRUE

LPC_AD<1>

TRUE

SMC_TX_L

TRUE

SPI_ALT_CLK

TRUE

LPC_SERIRQ

SMC_TDI

TRUE

LPC_PWRDWN_L

TRUE

SMC_RESET_L

TRUE TRUE

SMC_ROMBOOT SMC_RX_L

TRUE

SMC_TMS

TRUE

ADAPTER_SENSE

TRUE

LED_RETURN_2

LED_RETURN_4

TRUE

PPVCORE_S0_CPU

TRUE

TBTAPWRSW_ISET_S3_R

TRUE

TBT_B_D2R_C_P<0>

TRUE

PCIE_ENET_R2D_C_N

TRUE

PCIE_ENET_R2D_C_P

TRUE

PCIE_AP_R2D_C_P

TRUE

PCIE_AP_R2D_C_N

TRUE

PCIE_AP_D2R_N

TRUE

PCIE_AP_D2R_P

TRUE

PCIE_AP_D2R_PI_P

TRUE

PCIE_AP_D2R_PI_N

TRUE

PCIE_AP_R2D_PI_P

TRUE

PCIE_AP_R2D_PI_N

TRUE

PCIE_CLK100M_PCH_N

TRUE

PCIE_CLK100M_PCH_P

TRUE

PCIE_CLK100M_TBT_N

TRUE

PCIE_CLK100M_TBT_P

TRUE

PCH_CLK100M_SATA_P

TRUE

PCH_CLK33M_PCIIN

TRUE

PCIE_CLK100M_SSD_P

TRUE

PEG_CLK100M_P

TRUE

PEG_CLK100M_N

TRUE

PCIE_CLK100M_ENET_N

TRUE

PCIE_CLK100M_ENET_P

TRUE

PCIE_CLK100M_AP_N

TRUE

PCIE_CLK100M_AP_P

TRUE

PCIE_CLK100M_FW_P

TRUE

PCIE_CLK100M_EXCARD_P

TRUE

PCIE_CLK100M_FW_N

TRUE

SATA_HDD_D2R_RDROUT_P

SATA_HDD_R2D_RDRIN_N

TRUE

SATA_HDD_D2R_RDROUT_N

TRUE

SATA_HDD_D2R_RDRIN_N

SATA_HDD_D2R_RDRIN_P

TRUE

SATA_HDD_R2D_RDROUT_N

TRUE TRUE

SATA_HDD_R2D_RDROUT_P

TRUE

SATA_HDD_D2R_RC_N

TRUE

SATA_HDD_R2D_RC_N

SATA_HDD_R2D_C_P

TRUE

SATA_HDD_D2R_N

TRUE

PP18V5_DCIN_FUSE

TRUE

BKLT_EN

TRUE

LCD_BKLT_PWM

TRUE

PM_CLKRUN_L

TRUE

PP3V3_S4

WS_CONTROL_KBD

TRUE

PCIE_TBT_R2D_N<3..0>

PCIE_TBT_R2D_P<3..0>

TRUE

PCIE_TBT_R2D_C_N<3..0>

TRUE

PCIE_TBT_R2D_C_P<3..0>

TRUE

MAKE_BASE=TRUE

NC_SMS_INT2

TRUE

MAKE_BASE=TRUE

NC_SMC_MPM5_LED_CHG

TRUE

MAKE_BASE=TRUE

NC_AUD_MIC_INRN

TRUE

NC_SMC_MPM5_LED_PWR

TRUE MAKE_BASE=TRUE

SATA_SSDRHDD_D2R_P

TRUE

SATA_SSDRHDD_R2D_P

TRUE

SATA_SSDRHDD_R2D_N

TRUE

USB_CAMERA_CONN_P

TRUE

SMBUS_SMC_2_S3_SCL

TRUE

WS_KBD6

TRUE

TBT_B_R2D_C_P<1..0>

TRUE

SATA_HDD_D2R_RC_P

SATA_HDD_R2D_RDRIN_P

TRUE

SATA_HDD_D2R_P

NC_DP_TBTSRC_ML_CP<2>

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

NC_DP_TBTSRC_ML_CP<3>

SATA_HDD_R2D_C_N

TRUE

USB3_EXTA_RX_F_P

TRUE

USB3_EXTA_RX_F_N

TRUE

USB3_EXTA_RX_N

TRUE

USB3_EXTA_RX_N

USB3_EXTA_TX_N

TRUE

USB3_EXTA_TX_C_N

TRUE

USB3_EXTB_RX_P

TRUE

USB3_EXTB_RX_RC_N

TRUE

USB3_EXTB_RX_RC_P

TRUE

USB3_EXTB_RX_N

TRUE

SATA_SSDRHDD_D2R_N

TRUE

SATA_HDD_R2D_RC_P

TRUE

USB3_EXTA_TX_C_P

TRUE

USB3_EXTA_RX_P

TRUE

PCIE_CLK100M_SSD_N

NC_PCI_CLK33M_OUT2

TRUE MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_PCH_TP23

TBTAPWRSW_ISET_S3

TRUE

PSOC_MISO

TRUE

USB_EXTB_P

TRUE

WIFI_EVENT_L

TRUE

AP_RESET_CONN_L

TRUE

AP_CLKREQ_Q_L

TRUE

PCIE_WAKE_L

ENET_RESET_L

TRUE

SMBUS_PCH_CLK

TRUE

PP_KBD_BOOST_VOUT

TRUE

WS_KBD17

TRUE

WS_KBD18

TRUE

WS_KBD19

PP3V3_S4

TRUE

FAN_RT_PWM

TRUE

AUD_CONN_SLEEVE

TRUE

AUD_CONN_MIC_XW

TRUE

AUD_CONN_SLEEVE_XW AUD_CONN_HP_LEFT

TRUE

PP3V3_S0

AUD_CONN_TIPDET_INV

TRUE

AUD_CONN_MIC

TRUE

AUD_CONN_HP_RIGHT AUD_CONN_TYPEDET

TRUE

SPKRCONN_L_ID

TRUE

SPKRCONN_L_OUT_N

SPKRCONN_L_OUT_P

TRUE

SPKRCONN_SL_OUT_P

TRUE TRUE

SPKRCONN_SL_OUT_N

TRUE

SPKRCONN_R_OUT_P

TRUE

SPKRCONN_R_OUT_N

TRUE

SPKRCONN_R_ID SPKRCONN_SR_OUT_P

TRUE

GND

TRUE

SPKRCONN_SR_OUT_N

TRUE

PP5VR3V3_SW_LCD

LED_RETURN_6

TRUE

PPVOUT_S0_LCDBKLT

TRUE

LED_RETURN_5 LED_RETURN_4

TRUE TRUE

LED_RETURN_3

TRUE

LED_RETURN_2 LED_RETURN_1

TRUE TRUE

LCD_HPD_CONN

TRUE

DP_INT_AUX_P

TRUE

DP_INT_AUX_N

SMBUS_SMC_2_S3_SDA

TRUE

SMBUS_SMC_2_S3_SCL

TRUE

Z2_CLKIN

TRUE

Z2_MISO

TRUE

FAN_LT_TACH

TRUE

FAN_LT_PWM

TRUE

AP_CLKREQ_Q_L

TRUE

PM_SLP_S3_L

TRUE

HDMI_HPD_L

TRUE

USB_EXTB_OC_L

TRUE

USB3_EXTB_TX_C_N

TRUE

USB3_EXTB_TX_C_P

TRUE

PCIE_CLK100M_ENET_N

PCIE_CLK100M_ENET_P

TRUE

TP_LPC_DREQ0_L

MAKE_BASE=TRUE

NC_LPC_DREQ0_L

TRUE

I1521

USB_BT_CONN_P USB_BT_CONN_N

PP0700

PP0701

PP0702

PP0703

PP0704

PP0705

PP0706

PP0707

PP0708

PP0709

PP0710

PP0711

PP0712

PP0713

PP0719

PP0718

PP0717

PP0716

PP0715

PP0714

PP0720

PP0721

PP0722

PP0723

PP0724

<SCH_NUM>

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17 36

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17 36 75

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69 76

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36 75

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38 74

39 42

33 75

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36 78

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17 39 41 75

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40 41

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Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

8 7 6 5 4 3

NOTICE OF PROPRIETARY PROPERTY:

PAGE

PAGE TITLE

SHEET

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

5V Rails

For PCH RTC Power

3.3V Rails

Backlight Rails

1.8V/1.5V/1.2V/1.05V Rails

2A max supply

Chipset "VCore" Rails

TBT Rails (off when no cable)

G3H Rails

I1709

SYNC_MASTER=MASTER

SYNC_DATE=MASTER

Power Aliases

MIN_LINE_WIDTH=0.2 mm

PP1V5R1V35_MEM

VOLTAGE=1.35V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.17 mm

=PP1V5R1V35_S3_MEM_B =PP1V5_S3_MEMRESET

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=0.2 mm VOLTAGE=1.35V

MAKE_BASE=TRUE

PP1V5R1V35_S3

=PP1V8_S0_REG

PP1V8_S0

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

VOLTAGE=1.8V

=PPVDDIO_S0_SBCLK

=PP1V8_S0_PCH_VCC_DFTERM

VOLTAGE=3.3V

PP3V3_S5

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 MM

=PP3V3_S5_PCH_VCCDSW

=PP3V3_S5_VMON

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM

MAKE_BASE=TRUE

VOLTAGE=3.3V

PP3V3_S3

VOLTAGE=3.3V

PP3V3_S0

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.075 mm

MIN_LINE_WIDTH=0.5 MM

=PP3V3_S0_BKL_VDDIO

=PP3V3_S0_LCD

=PP3V3_S0_PCH_GPIO

=PPBUS_G3H_T25

=PPBUS_SW_BKL

=PP3V3_S4_TBTBPWRSW

=PP3V3_S4_TBTAPWRSW

=PP18V5_DCIN_CONN

PPBUS_G3H

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

VOLTAGE=12.8V

MIN_NECK_WIDTH=0.25 mm

PP3V3_SUS

MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM

VOLTAGE=3.3V

=PP3V3_SUS_PCH_VCCSUS_USB

=PPVIN_S5_HS_COMPUTING_ISNS

=PPVIN_S0_CPUIMVP

=PPBUS_S0_VSENSE

=PP1V5_S0_REG

=PPVTT_S3_DDR_BUF

=PP1V5_S3RS0_FET

=PPVTT_S0_DDR_LDO

PP1V5_S0

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.15 MM

MAKE_BASE=TRUE

VOLTAGE=1.5V

=PP1V5_S0_AUDIO

=PPBUS_G3H

=PPVIN_S5_HS_COMPUTING_ISNS_R

=PP3V42_G3H_AUDIO =PP3V42_G3H_TDM

=PP3V3_S5_P1V5S0

=PP5V_S0_AUDIO

=PP3V3_S4_TPAD

=PP3V3_SUS_PCH_VCCSUS_GPIO

=PP3V3_SUS_PCH_VCC_SPI

=PP3V3_S5_PCHPWRGD

=PP3V3_S5_PCH

=PP3V3_TBT_PCH_GPIO

=PP1V05_TBTLC

=PP3V3_TBT_PCH_GPIO

=PP1V05_S0_P1V05TBTREG_R

=PP1V05_TBTLC_RTR

=PP1V05_TBTCIO_RTR

=PPVCORE_S0_CPU

=PP3V3_TBTLC_RTR =PPVDDIO_TBT_CLK

=PPVIN_S0_CPUAXG

=PP5V_S4_TPAD

=PPVIN_S3_DDRREG

=PP3V3_S3_P1V2S3

=PP1V5R1V35_S3_CPU_VCCDDR

=PP3V3_TBTLC_FET

=PPHV_SW_TBTAPWRSW =PPHV_SW_TBTBPWRSW

=PP15V_TBT_REG

=PP1V05_S0_P1V05TBTREG

=PP1V05_TBTCIO_FET

=PP3V3_S3_P3V3S3FET

=PP3V3_S0_P3V3S0FET

=PP3V3_S5_PWRCTL

=PP3V3_S0_FET

=PP3V3_S0_PCH_STRAPS

=PP5V_S0_BKL

=PP3V3_SUS_ROM

=PP3V3_S3_USBMUX

=PP3V3_S3_VREFMRGN

=PP3V3_S3_SMS

=PPVCORE_S0_AXG_REG

=PP3V3_S3_MEMRESET

=PP3V3_S3_SMBUS_SMC_3

=PP3V42_G3H_BMU

=PPVIN_S5_P5VP3V3

=PPVIN_S0_VCCSAS0

=PP3V3_S3_FET

=PP3V3_S0_CPUTHMSNS

=PP3V3_S3_USB_RESET

=PP3V3_S3_ISNS

=PP3V3_S5_XDP

=PPBUS_G3H_T25_R

=PPDCIN_S5_CHGR

=PP3V3_S5_LPCPLUS

=PPVRTC_G3_PCH

=PP3V3_S0_AUDIO_DIG

=PP3V3_S0_P1V5S0

=PP3V3_S0_FAN_RT

=PP3V3_S0_P3V3TBTFET

=PP3V3_S0_PCH_VCC3_3_CLK

=PP3V3_S0_PCH_VCCADAC =PP3V3_S0_PCH_VCC3_3

=PP3V3_S0_SYSCLK

=PP3V3_S0_SSD

=PP3V3_S0_SMBUS_SMC_1_S0

=PP3V3_S0_SMBUS_SMC_0_S0

=PP3V3_S0_SMBUS_PCH

=PP3V3_S0_PCH_VCC3_3_HVCMOS

=PP3V3_S0_PCH_VCC3_3_GPIO

=PP3V3_S0_CPU_VCCIO_SEL

=PP3V3_S0_GPUTHMSNS

=PP3V3_S0_FAN_LT

=PP3V3_S0_DDCMUX

=PP3V3_S0_BKLI2C

=PP3V3_S0_P1V8S0

=PP3V3_S0_AUDIO

=PP3V3_S3_BT

=PP3V3_S3_P1V8S3

=PP3V3_S3_CAMERA

=PP3V3_S3_SDBUF

=PP3V3_S3_WLAN =PP3V3_S3_GYRO

=PP3V3_S3_USB_HUB

=PP3V3_S3_SMBUS_SMC_2_S3

=PP3V3_S3_RIO

=PP3V3_S3_PCH_GPIO

=PPVBAT_G3_SYSCLK

=PP3V3_S5_SMCBATLOW

=PP3V3_S5_REG

=PP0V75_S0_MEM_VTT_B

=PP3V42_G3H_ONEWIREPROT

=PP3V42_G3H_SMCUSBMUX

=PP5V_S5_P1V5S3RS0FET

=PP3V3_S4_P3V3S4FET

=PP3V3_S5_P3V3SUSFET

=PP1V8_S0_CPU_VCCPLL_R

=PP3V3_S5_CPU_VCCDDR

=PP3V3_S5_PCH_GPIO

=PP18V5_DCIN_ISOL

=PP3V3_S5_SMC

=PP3V3_SUS_SMC

=PP3V3_SUS_PCH_VCCSUS

=PP3V3_SUS_P1V05SUSLDO

=PP5V_S0_HDD

=PP3V3_SUS_CNTRL

=PP3V42_G3H_PWRCTL

=PP5V_SUS_PCH

=PP3V42_G3H_CHGR

=PP3V3_S5_SYSCLK

=PP3V3_SUS_PCH_GPIO

=PP1V5_S3_CPU_VCCDQ

=PPVCORE_S0_CPU_VCCAXG

=PP3V42_S3_HALL

=PP5V_S0_FAN_RT

=PP5V_S0_LPCPLUS

=PP5V_S0_PCH

=PP5V_S0_VMON

=PPVCCSA_S0_REG

=PP1V05_S0_CPU_VCCPQE

=PP1V8_S0_CPU_VCCPLL

=PP1V8_S0_AUDIO

=PP1V8R1V5_S0_PCH_VCCVRM

=PP3V42_G3H_SMBUS_SMC_5

=PP5V_S4_P5VS0FET

=PPDDR_S3_REG

PPBUS_S0_LCDBKLT_PWR

=PPVIN_S3_MEM_ISNS

=PP1V5R1V35_S3_MEM_A

=PP1V5_S3RS0_VMON

=PP3V3R1V5_S0_PCH_VCCSUSHDA

=PP0V75_S0_MEM_VTT_A

=PPVCCIO_S0_SMC =PP1V05_S0_VMON

=PPVIN_S0_DDRREG_LDO

=PPVIN_S3_MEM_ISNS_R

=PP5V_S0_LCD

=PP5V_S0_KBDLED

=PPDDR_S3_MEMVREF =PPVIN_S3_P1V5S3RS0_FET

=PPDCIN_S5_VSENSE

=PPDCIN_S5_CHGR_ISOL

=PP3V3_SUS_PCH

=PP3V3_S4_FET

=PP3V3_S4_RIO

=PP3V3_S4_BT

=PP3V3_S4_SMC

=PP5V_S0_VCCSAS0

=PP5V_S0_RMC

=PP5V_S0_FAN_LT

=PP5V_S0_CPUVCCIOS0

=PP5V_S3_DEBUG_ISNS

=PP5V_S3_DEBUG_ADC_AVDD

=PP5V_S3_DDRREG

=PP5V_S3_ALSCAMERA

=PP1V5_S0_RDRVR

=PP5V_S0_CPUIMVP

=PP5V_S0_AUDIO_XW

=PP3V3_S0_HS_COMPUTING_ISNS

=PP5V_S3_DEBUG_ADC_DVDD

=PP3V3_S0_XDP =PP3V3_S0_DDR3THMSNS

=PP5V_S3_ISNS

=PPVIN_S5_HS_OTHER_ISNS

=PPVIN_S0_CPUVCCIOS0

=PPVIN_S5_HS_OTHER_ISNS_R

=PPBUS_S0_LCDBKLT

=PP3V3_S4_TBT

=PP5V_S4_REG

=PP3V3_SUS_FET

=PP5V_S4_RIO

=PP5V_S4_AUDIO

=PP5V_S4_P5VS3FET

=PP5V_S3_LTUSB

=PP5V_S3_MEMRESET

=PP3V3_S0_IMVPISNS

=PP3V3_S0_HS_ISNS

=PP3V3_S0_ISNS

=PP3V3_S0_PCH

=PP5V_S4_P1V05TBTS0

=PP5V_S0_FET

=PP3V42_G3H_REG

=PP3V3_S0_TBTI2C

=PP1V05_S0_PCH_VCCIO_SATA

=PP1V05_S0_PCH_VCCIO_USB

=PP1V05_S0_PCH_VCCIO_CLK

=PP1V05_S0_PCH_VCC_CORE =PP1V05_S0_PCH_VCCASW

=PP1V05_S0_PCH_VCCIO_PLLUSB =PP1V05_S0_PCH_VCC_DMI =PP1V05_S0_PCH_VCCIO_PLLFDI =PP1V05_S0_PCH_VCCDMI_FDI

=PP3V3_S0_SATAMUX

=PP3V3_S0_RSTBUF

=PP3V3_S0_PCH_VCC3_3_SATA

=PP3V3_S0_PCH_VCC3_3_PCI

=PPCPUVCCIO_S0_REG

=PP1V05_SUS_LDO

=PP1V05_S0_PCH

=PP1V05_S0_PCH_VCCDIFFCLK

=PP1V05_S0_PCH_VCCIO_CLK

=PP3V3_S0_SPKRTHMSNS

=PP3V3_S0_VMON

=PP3V3_S0_TPAD

=PP3V3_S0_SB_PM

=PP3V3_S0_PWRCTL

=PPVCCSA_S0_CPU

=PPVCCIO_S0_XDP

=PP3V3_S0_HS_OTHER_ISNS

=PP3V3_S0_HDMI

=PP3V3_S0_TBTPWRCTL

=PP1V05_S0_PCH_VCCSSC

=PP1V05_S0_RMC

=PP1V05_S0_CPU_VCCIO

=PP1V05_S0_PCH_V_PROC_IO

=PPVCORE_S0_CPU_REG

=PP5V_S3_FET

=PP5V_SUS_FET

=PP5V_S5_P5VSUSFET

=PP5V_S5_TPAD

=PPVIN_S5_SMCVREF

=PP3V42_G3H_TPAD

=PP5V_S5_LDO

=PPVRTC_G3_OUT

=PP1V05_S0_PCH_VCCIO_PCIE

=PP1V05_S0_PCH_VCCIO

=PP1V05_S0_PCH_VCCADPLL

=PP1V05_S0_PCH_VCCIO_PLLPCIE

=PPVCCIO_S0_CPUIMVP

=PP1V05_SUS_PCH_JTAG

=PPVTT_S0_VTTCLAMP

=PPVIN_SW_TBTBST

MAKE_BASE=TRUE

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V05_SUS

MAKE_BASE=TRUE

VOLTAGE=1.05V

PP1V05_S0

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.15 MM

MIN_NECK_WIDTH=0.1 MMMAKE_BASE=TRUE

PP5V_S5

VOLTAGE=5V

MIN_LINE_WIDTH=0.5 MM

PPVCCSA_S0_REG

VOLTAGE=0.9V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

MIN_NECK_WIDTH=0.17 mm MAKE_BASE=TRUE

VOLTAGE=0.675V

MIN_LINE_WIDTH=0.6 mm

PP0V75_S0_DDRVTT

PP5V_S4

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

VOLTAGE=5V MAKE_BASE=TRUE

PPVIN_S5_HS_COMPUTING_ISNS

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.8V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 mm

PP5V_S3

VOLTAGE=5V

PP3V3_S4

MIN_NECK_WIDTH=0.1 MM

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.3 MM

MAKE_BASE=TRUE

VOLTAGE=18.5V

PPDCIN_G3H_ISOL

PPVTTDDR_S3

MIN_LINE_WIDTH=0.3 MM

MAKE_BASE=TRUE

VOLTAGE=0.675V

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=12.8V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PPBUS_G3H_T25_PWR

PPBUS_SW_BKL

MIN_LINE_WIDTH=0.5 MMMAKE_BASE=TRUE

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.25 MM

PPVRTC_G3H

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MMMAKE_BASE=TRUE

VOLTAGE=3.42V

VOLTAGE=1.05V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_CPU_VCCPQE

PP5V_SUS

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

VOLTAGE=5V MAKE_BASE=TRUE

VOLTAGE=1.8V MAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

PP1V8_S0_CPU_VCCPLL_R

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.25 MM

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM

PPDCIN_G3H

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 mm

PPVIN_S5_HS_OTHER_ISNS

VOLTAGE=12.8V

MAKE_BASE=TRUE

PP3V42_G3H

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM

VOLTAGE=3.42V

PP1V5_S3_CPU_VCCDQ

VOLTAGE=1.5V

MAKE_BASE=TRUEMIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=12.8V

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

PPVIN_SW_TBTBST

MIN_NECK_WIDTH=0.2 MM

PP5V_S0

VOLTAGE=5V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 MM

PP15V_TBT

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

VOLTAGE=15V

PP1V05_TBTCIO

MIN_LINE_WIDTH=0.4 mm VOLTAGE=1.05V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

PPVCORE_S0_AXG

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE VOLTAGE=1.25V

PPVCORE_S0_CPU

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP3V3_TBTLC

PP1V05_S0_P1V05TBTREG

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=1.05V MAKE_BASE=TRUE

PP1V05_S0_P1V05TBTREG_R

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE

VOLTAGE=1.05V

MAKE_BASE=TRUE

VOLTAGE=1.5V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PP1V5_S3RS0_CPUDDR

<SCH_NUM>

8 OF 132

8 OF 80

20 21 23

21 23

17 18 19 20 25 35

21 23

61 62

31 60

56 57

21 23

17 20

64 80

10 13 15 43

33 34 35

11 13 16 27

35 80

17 18 21

51 54

21 23

51 55

36 66

19 25

13 15

39 40

21 23

57 66

17 18 19 20

13 16

10 13 16 43

23 25

58 80

13 15

21 23 25

25 36 40

61 62

33 34 35

43 80

17 23

21 23

17 23

17 21 23

25 66

13 16

21 23

10 11 13 15

21 23

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

8 7 6 5 4 3

NOTICE OF PROPRIETARY PROPERTY:

PAGE

PAGE TITLE

SHEET

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TH0904,5 for USB can gnd slot

APN:862-0118

Unused Memory Signals

Unused PGOOD signal

D1 POGO PINS (870-2451)

Digital Ground

CR SFF DG v1p0 Table 3-56 mapping for HDMI

Unused GPU signals

CPU signals

T29 Signals Through PEG

Unused SATA ODD Signals

USB SIGNALS

UNUSED USB SIGNALS

Unused PEG signals

D1 BMU MODULE STANDOFFS

APN:998-3975

Frame Holes

D1 THERMAL MODULE STANDOFF (860-1439)

APN: 860-1490

FAN BOSSES (4X 860-1327)

eDP signals

TH0903 for lower TBT can gnd slot

APN:860-1557

SH0963 is BMU standoff with flange. 860-1534

D1 ELIPTICAL SLOT HOLES

Bosses for limiting deflection

TH0900 for upper TBT can gnd slot

STDOFF-4.5OD2.15H-SM

STDOFF-4.5OD1.8H-SM

STDOFF-4.5OD2.15H-SM STDOFF-4.5OD2.15H-SM

STDOFF-4.5OD1.73H-SM

1/20W

201

RAMCFG0:L

RAMCFG1:L

1/20W

201

RAMCFG3:L

1/20W

201

5% MF

1/20W

STDOFF-4.5OD2.15H-SM

STDOFF-4.5OD1.8H-SM

POGO-2.3OD-5.5H-SM-LOW-FORCE

SM SM

POGO-2.3OD-5.5H-SM-LOW-FORCE

SL-3.9X2.3-4.2x2.6

TH-NSP TH-NSP

SL-2.8X1.8-3.1x2.1

SL-3.9X2.3-4.2x2.6

10K

201

1/20W

TH-NSP

SL-1.1X0.45-1.4x0.75

TH-NSP

SL-1.1X0.5-1.4x0.8

2.8OD1.2ID-2.25H-SM-D1

SHLD-D1-USB

SHLD-D1-MLB-T29

2.8OD1.2ID-2.25H-SM-D1

4P5R2P3-3P5B

STDOFF-4.5OD2.33H-SM

POGO-2.3OD-5.5H-SM-LOW-FORCE

TH-NSP

SL-1.1X0.5-1.4x0.8

4P5R2P3-3P5B

Signal Aliases

SYNC_MASTER=D1_MLB_TEST

SYNC_DATE=01/27/2012

GND

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0V

NC_PCH_GPIO65_CLKOUTFLEX1

TRUE

MAKE_BASE=TRUE

ENET_LOW_PWR_PCH

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB3_EXTD_RXN

MAKE_BASE=TRUE

DP_TBTSNK1_AUXCH_C_P

DP_TBTSNK1_ML_C_P<3..0>

MAKE_BASE=TRUE

DP_TBTSNK1_ML_C_N<3..0>

DP_TBTSNK1_DDC_CLK

MAKE_BASE=TRUE

NC_PCH_GPIO66_CLKOUTFLEX2

TRUE

MAKE_BASE=TRUE

NC_PCH_GPIO67_CLKOUTFLEX3

TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_USB3_EXTC_RXP

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_USB3_EXTC_RXN

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB_EXTCP

DP_TBTSNK1_HPD

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PEG_CLK100MN

VOLTAGE=5V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

PP5V_S0_AUDIO_AMP_R

DP_INT_AUX_C_P

MAKE_BASE=TRUE

DP_TBTSNK0_ML_C_P<3..0>

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_PCIE_CLK100M_FWN

TRUE

MAKE_BASE=TRUE

NC_PCIE_CLK100M_SSDN

TRUE

MAKE_BASE=TRUE

NC_PCIE_CLK100M_SSDP

MAKE_BASE=TRUE

TRUE

NC_PCIE_CLK100M_FWP

HDMI_IG_CLK_C_P

MAKE_BASE=TRUE

DP_TBTSNK0_AUXCH_C_P

MAKE_BASE=TRUE

DP_TBTSNK0_AUXCH_C_N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LCD_FSS

MAKE_BASE=TRUE

PCIE_TBT_R2D_C_P<3..0>

PP5V_S0_AUDIO_AMP_L

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=5V

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_FW_D2RN

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_FW_D2RP

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_FW_R2D_CN

SD_PWR_EN_PCH

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PEG_D2RN<15..12>

NC_PEG_R2D_CN<15..12>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MEM_A_CLKN<1>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MEM_B_CLKP<1>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MEM_A_CLKP<1>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MEM_B_CLKN<1>

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SATA_ODD_D2RN

NC_SATA_ODD_R2D_CP

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SATA_ODD_R2D_CN

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SATA_ODD_D2RP

NO_TEST=TRUE

SD_PWR_EN

MAKE_BASE=TRUE

PCIE_TBT_D2R_P<3..0>

NC_CPU_THERMDN

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_CPU_THERMDP

MAKE_BASE=TRUE

NO_TEST=TRUE

DP_TBTSNK1_DDC_DATA

MAKE_BASE=TRUE

TP_DDRREG_PGOOD

MAKE_BASE=TRUE

TP_P1V5S3RS0_RAMP_DONE

MAKE_BASE=TRUE

MEMVTT_EN

MAKE_BASE=TRUE

PCIE_TBT_R2D_C_N<3..0>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PEG_R2D_CN<7..0>

PCIE_TBT_D2R_N<3..0>

MAKE_BASE=TRUE

NC_DPA_IG_AUX_CHP

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_DPA_IG_AUX_CHN

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCIE_FW_R2D_CP

MAKE_BASE=TRUE

DP_TBTSNK1_AUXCH_C_N

DP_TBTSNK0_DDC_CLK

MAKE_BASE=TRUE

NC_PEG_D2RP<15..12>

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_FW_PWR_EN

MAKE_BASE=TRUE

HDMI_HPD

DP_TBTSNK0_DDC_DATA

MAKE_BASE=TRUE

LCD_PWR_EN

DP_INT_AUX_C_N

MAKE_BASE=TRUE

DP_INT_ML_C_P<3..0>

MAKE_BASE=TRUE

DP_INT_ML_C_N<3..0>

MAKE_BASE=TRUE

LCD_BKLT_EN

MAKE_BASE=TRUE

HDMI_IG_CLK_C_N

MAKE_BASE=TRUE

HDMI_IG_DATA_C_P<2..0>

MAKE_BASE=TRUE

HDMI_IG_DDC_CLK

MAKE_BASE=TRUE

DP_TBTSNK0_ML_C_N<3..0>

TRUE

NC_PCH_GPIO64_CLKOUTFLEX0

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB3_EXTC_TXN

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB_EXTD_EHCIP

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB_EXTD_EHCIN

NC_USB3_EXTD_RXP

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB3_EXTD_TXP

MAKE_BASE=TRUE

NC_USB3_EXTD_TXN

NO_TEST=TRUE

NC_USB_4N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB_4P

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_USB_SDP

NO_TEST=TRUE

NC_USB_SDN

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB_WLANP

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB_WLANN

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB_BT_HSN

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB_BT_HSP

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

USB_BT_P

MAKE_BASE=TRUE

USB_TPAD_P

MAKE_BASE=TRUE

USB_BT_N

MAKE_BASE=TRUE

USB_TPAD_N

MAKE_BASE=TRUE

USB_SMC_P

MAKE_BASE=TRUE

USB_SMC_N

MAKE_BASE=TRUE

PU_USBHUB_DN4_P

MAKE_BASE=TRUE

PU_USBHUB_DN4_N

NC_USB_12N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB_12P

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB_13P

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_USB_13N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB3_EXTC_TXP

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PEG_CLK100MP

NC_PEG_R2D_CP<15..12>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PEG_D2RP<7..0>

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PEG_D2RN<7..0>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PEG_R2D_CP<7..0>

MAKE_BASE=TRUE

LCD_BKLT_PWM

USB3_EXTC_RX_P

PEG_CLK100M_N

=PP3V3_S0_PWRCTL

CPUIMVP_AXG_PGOOD

TP_EDP_AUX_P

MLB_RAMCFG1

MLB_RAMCFG0

PCIE_CLK100M_SSD_P

PCIE_CLK100M_SSD_N

PCIE_CLK100M_FW_N PCIE_CLK100M_FW_P

TP_EDP_TX_P<3..0>

LCD_FSS

LVDS_IG_PANEL_PWR

=PP5V_S0_AUDIO_XW

DPB_IG_AUX_CH_P

TP_PCH_GPIO67_CLKOUTFLEX3

TP_PCH_GPIO64_CLKOUTFLEX0

=DDRVTT_EN

=PEG_R2D_C_P<11..8> =PEG_R2D_C_N<11..8>

=PEG_D2R_N<11..8>

CPU_THERMD_N

=PEG_R2D_C_N<7..0>

DPA_IG_HPD

PCIE_FW_R2D_C_N

MEM_B_CLK_P<1> MEM_B_CLK_N<1>

MEM_A_CLK_P<1> MEM_A_CLK_N<1>

SATA_ODD_D2R_N SATA_ODD_D2R_P

SATA_ODD_R2D_C_P

SATA_ODD_R2D_C_N

FW_PWR_EN

TP_DP_IG_D_AUXN

TP_PCH_GPIO66_CLKOUTFLEX2

CPU_THERMD_P

=PEG_D2R_P<11..8>

TP_DP_IG_D_CTRL_DATA

TP_PCH_GPIO65_CLKOUTFLEX1

DDRREG_PGOOD

P1V5S3RS0_RAMP_DONE

LVDS_IG_BKL_PWM LVDS_IG_BKL_ON

PCIE_FW_D2R_N PCIE_FW_D2R_P

PCIE_FW_R2D_C_P

TP_DP_IG_D_MLP<3..0>

DPA_IG_DDC_DATA

TP_DP_IG_C_MLP<3..0>

TP_DP_IG_D_CTRL_CLK

TP_DP_IG_D_HPD

DPA_IG_AUX_CH_N

DPA_IG_AUX_CH_P

ENET_LOW_PWR

PEG_CLK100M_P

TP_DP_IG_B_MLP<0..2>

DPA_IG_DDC_CLK

TP_DP_IG_B_MLN<0..2>

DPB_IG_AUX_CH_N

DPB_IG_DDC_CLK DPB_IG_DDC_DATA

DPB_IG_HPD

TP_DP_IG_B_MLN<3>

USB3_EXTC_TX_N

USB3_EXTC_TX_P

USB3_EXTD_TX_P

USB_EXTC_N

TP_USB_SDP

TP_USB_WLANP

TP_USB_WLANN

TP_USB_BT_HSN TP_USB_BT_HSP

TP_DP_IG_C_MLN<3..0>

USB3_EXTC_RX_N USB_EXTC_P

USBHUB_DN1_P

USBHUB_DN2_P

USBHUB_DN1_N

USBHUB_DN2_N USBHUB_DN3_P USBHUB_DN3_N USBHUB_DN4_P USBHUB_DN4_N

TP_USB_12N

TP_USB_13P

TP_USB_13N

TP_USB_12P

TP_USB_SDN

TP_USB_4P

TP_USB_4N

USB_EXTD_EHCI_P

USB3_EXTD_RX_N

USB3_EXTD_TX_N

TP_DP_IG_B_MLP<3>

=PEG_R2D_C_N<15..12>

=PEG_R2D_C_P<15..12>

=PEG_D2R_N<15..12>

=PEG_D2R_P<15..12>

=PEG_D2R_N<7..0> =PEG_R2D_C_P<7..0>

=PEG_D2R_P<7..0>

MLB_RAMCFG2

TP_EDP_AUX_N

TP_DP_IG_D_MLN<3..0>

USB3_EXTD_RX_P

TP_DP_IG_D_AUXP

USB_EXTD_EHCI_N

MAKE_BASE=TRUE

DP_TBTSNK0_HPD

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB_EXTCN

TP_EDP_TX_N<3..0>

MAKE_BASE=TRUE

HDMI_IG_DDC_DATA

MAKE_BASE=TRUE

HDMI_IG_DATA_C_N<2..0>

2.8OD1.2ID-2.25H-SM-D1

MLB_RAMCFG3

RAMCFG2:L

TH-NSP

POGO-2.3OD-5.5H-SM-LOW-FORCE

POGO-2.3OD-4.1H-SM-LOW-FORCE

STDOFF-4.5OD1.8H-SM

ZT0960

XW0902

1 2

XW0903

1 2

SH0921

SH0922

SH0925

SH0926

SH0927

SH0928

SH0924

R0910

R0911

R0913

R0912

SH0920

SH0923

SH0932

SH0933

SH0934

SH0935

SH0936

ZT0930

ZT0920

ZT0931

R0991

TH0905

TH0904

TH0900

SH0910

SH0911

SH0912

SH0950

SH0951

SH0913

ZT0940

SH0963

SH0937

TH0903

<SCH_NUM>

9 OF 132

9 OF 80

20 24 25

33 79

67 79

33 79

36 78

33 79

33 75

33 79

67 79

36 78

33 79

36 74

47 74

36 74

47 74

39 74

17 75

27 60

10 78

10 78 10

17 75

36 78

IN IN IN IN

OUT

IN IN IN IN IN

OUT

OUT OUT OUT

OUT

OUT OUT OUT OUT OUT

OUT OUT OUT OUT

OUT

IN IN IN IN IN

IN IN

OUT

OUT OUT OUT OUT

IN IN

NC NC

EDP_TX_3

EDP_TX_0 EDP_TX_1 EDP_TX_2

EDP_TX_2* EDP_TX_3*

EDP_TX_0* EDP_TX_1*

EDP_AUX

EDP_AUX*

EDP_COMPIO

EDP_HPD

EDP_ICOMPO

FDI1_LSYNC

DMI_TX_3*

FDI0_LSYNC

FDI0_TX_3

FDI1_TX_1

FDI1_TX_0

FDI1_TX_2 FDI1_TX_3

FDI0_FSYNC FDI1_FSYNC

FDI_INT

FDI1_TX_3*

FDI1_TX_2*

FDI0_TX_1

FDI0_TX_0

FDI0_TX_2

FDI1_TX_1*

FDI0_TX_3*

FDI1_TX_0*

FDI0_TX_2*

FDI0_TX_1*

DMI_TX_1* DMI_TX_2*

DMI_TX_0

DMI_TX_2

DMI_TX_1

DMI_TX_3

FDI0_TX_0*

DMI_RX_2*

DMI_RX_0 DMI_RX_1 DMI_RX_2 DMI_RX_3

DMI_TX_0*

DMI_RX_3*

DMI_RX_1*

DMI_RX_0*

PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO

PEG_RX_2*

PEG_RX_0* PEG_RX_1*

PEG_RX_3* PEG_RX_4* PEG_RX_5*

PEG_RX_7*

PEG_RX_6*

PEG_RX_8* PEG_RX_9*

PEG_RX_10*

PEG_RX_12*

PEG_RX_11*

PEG_RX_14*

PEG_RX_13*

PEG_RX_15*

PEG_RX_0 PEG_RX_1

PEG_RX_3

PEG_RX_2

PEG_RX_4

PEG_RX_6

PEG_RX_5

PEG_RX_7 PEG_RX_8

PEG_RX_10

PEG_RX_9

PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15

PEG_TX_1* PEG_TX_2*

PEG_TX_0*

PEG_TX_3* PEG_TX_4* PEG_TX_5*

PEG_TX_7*

PEG_TX_6*

PEG_TX_10*

PEG_TX_8* PEG_TX_9*

PEG_TX_11* PEG_TX_12* PEG_TX_13* PEG_TX_14* PEG_TX_15*

PEG_TX_1

PEG_TX_0

PEG_TX_2 PEG_TX_3 PEG_TX_4

PEG_TX_6

PEG_TX_5

PEG_TX_7 PEG_TX_8

PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12

PEG_TX_14

PEG_TX_13

PEG_TX_15

(1 OF 9)

PCI EXPRESS BASED INTERFACE SIGNALS

DMI

INTEL FLEXIBLE DISPLAY INTERFACE SIGNALS

EMBEDDED DISPLAY PORT

NC NC

RSVD_26 RSVD_27

RSVD_25

RSVD_23 RSVD_24

RSVD_22

RSVD_21

RSVD_19

RSVD_18

RSVD_16 RSVD_17

RSVD_15

RSVD_14

RSVD_13

RSVD_12

DC_TEST_BG1

DC_TEST_BD1

DC_TEST_BE1

DC_TEST_BG3 DC_TEST_BE3

DC_TEST_BG4

DC_TEST_BG58

DC_TEST_BG59

DC_TEST_BE59 DC_TEST_BG61

DC_TEST_BD61 DC_TEST_BE61

DC_TEST_D61

DC_TEST_A61 DC_TEST_C61

DC_TEST_A59 DC_TEST_C59

DC_TEST_A58

DC_TEST_D3 DC_TEST_D1

DC_TEST_C4

DC_TEST_A4

RSVD_45

RSVD_44

RSVD_41

RSVD_43

RSVD_42

RSVD_39 RSVD_40

RSVD_38

RSVD_36

RSVD_33

RSVD_31 RSVD_32

RSVD_30

CFG_3

CFG_2

CFG_1

CFG_0

CFG_9

CFG_8

CFG_7

CFG_6

CFG_14

CFG_12

CFG_10

CFG_16 CFG_17

VCC_VAL_SENSE

RSVD_8

RSVD_7

RSVD_6

CFG_15

CFG_13

CFG_11

CFG_5

CFG_4

VSS_VAL_SENSE

VAXG_VAL_SENSE

VCC_DIE_SENSE

VSSAXG_VAL_SENSE

RSVD_11

RSVD_9 RSVD_10

RSVD_20

RSVD_37

RSVD_35

RSVD_34

SB_DIMM_VREFDQ

SA_DIMM_VREFDQ

RESERVED

(5 OF 9)

NC NC NC

OUT OUT

SYM_VER_1

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

8 7 6 5 4 3

NOTICE OF PROPRIETARY PROPERTY:

PAGE

PAGE TITLE

SHEET

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED

FOR IVYBRIDGE PROCESSOR

CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4

If HPD is disabled while eDP interface is still enabled,

NOTE: The EDP_HPD processor input is a low voltage active low signal.

even if internal Graphics is disabled since they are

Note. VOLTAGE=1.25V Note. VOLTAGE=0V

Note. VOLTAGE=1.05V Note. VOLTAGE=0V

NOTE: Intel does not recommend to use

NOTE: Intel validation sense lines per

this alnalog sense due to accuracy concern.

doc 439028 rev1.0 HR_PPDG sections 6.2.1 and 6.3.1.

NOTE: Intel provides an internal pull-up OF 5-15k to VCCIO on all CFG signals.

CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

shared with other interfaces.

NOTE: eDP_COMPIO and eDP_ICOMPO can not be left floating

This signal can be left as no-connect if entire eDP interface is disabled.

connect it to CPU VCCIo via a 10-kOhm pull-up resistor on the motherboard.

to low voltage signals for the processor

to convert the active high signal from Embedded DisplayPort sink device

Therefore, an inverting level shifter is required on the motherboard

Intel Doc 460452 ChiefRiver Platform design guild rev1.0 section 2.2.12 recommendation.

CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

These can be Placed close to J2500 and Only for debug access

(refer to latest Processor EDS for DC specifications).

18 72

PLACE_NEAR=U1000.G3:12.7MM

24.9

402

MF-LF

1/16W

10 24 72

24 72

10 24 72

24 72

201

1/20W

NOSTUFF

201

1/20W

NOSTUFF

201

1/20W

NOSTUFF

201

1/20W

NOSTUFF

201

1/20W

NOSTUFF

18 72

24.9

MF-LF

1/16W

402

PLACE_NEAR=U1000.AF3:12.7MM

OMIT_TABLE

PLACE_NEAR=U1000.AG11:12.7MM

402

1/16W

10K

MF-LF

EDP:YES

201

1/20W

201

1/20W

NOSTUFF

201

1/20W

201

1/20W

NOSTUFF

PLACE_SIDE=TOP

NOSTUFF

PLACE_NEAR=U1000.H43:50.8MM

1/16W

402

MF-LF

49.9

PLACE_NEAR=U1000.H45:50.8MM PLACE_SIDE=TOP

49.9

1/16W

402

NOSTUFF

MF-LF

PLACE_SIDE=TOP

PLACE_NEAR=U1000.K43:50.8MM

49.9

1/16W MF-LF

402

NOSTUFF

PLACE_NEAR=U1000.K45:50.8MM

PLACE_SIDE=TOP

NOSTUFF

MF-LF 402

49.9

1/16W

2C-35W

IVY-BRIDGE

BGA

CRITICAL

OMIT_TABLE

2C-35W

IVY-BRIDGE

OMIT_TABLE

CRITICAL

BGA

31 72

SOT523

DMN5L06TK

EDP:YES

SYNC_DATE=07/14/2011

CPU DMI/PEG/FDI/RSVD

SYNC_MASTER=J30_MLB

RES,MTL FILM,1/16W,10K,0402,SMD,LF

EDP:NO

R1031

116S0090

116S0066

RES,MTL FILM,1/16W,1K,0402,SMD,LF

EDP:YES

R1031

=PEG_D2R_N<11>

=PEG_D2R_N<13> =PEG_D2R_N<14> =PEG_D2R_N<15>

LCD_HPD

EDP_HPD_L

TP_EDP_TX_P<3>

TP_EDP_TX_P<2>

TP_EDP_TX_N<1>

TP_EDP_AUX_P

TP_EDP_AUX_N

TP_EDP_TX_N<0>

TP_EDP_TX_P<0>

DMI_S2N_P<1>

FDI_DATA_P<3>

DMI_N2S_N<1>

DMI_N2S_N<0>

FDI_DATA_N<2>

FDI_DATA_N<4>

FDI_DATA_N<6>

=PEG_R2D_C_P<12>

=PEG_R2D_C_P<14>

DMI_S2N_N<1>

=PEG_D2R_P<7>

=PEG_D2R_P<5>

CPU_VCC_VALSENSE_N

CPU_CFG<6>

CPU_CFG<4>

CPU_CFG<0>

=PEG_R2D_C_P<1>

=PEG_R2D_C_N<12>

=PEG_D2R_N<6>

=PEG_D2R_N<5>

=PEG_R2D_C_P<0>

CPU_THERMD_N

CPU_THERMD_P

=PEG_D2R_P<12>

CPU_DC_TEST_C59_A59

CPU_VCC_VALSENSE_P

CPU_AXG_VALSENSE_P

=PEG_D2R_P<13>

=PEG_R2D_C_P<2>

=PEG_R2D_C_P<9>

CPU_CFG<17>

CPU_DC_TEST_C4_BE1_BG1

TP_CPU_DC_TEST_BD1

CPU_DC_TEST_C4_BE3_BG3

TP_CPU_DC_TEST_BG4

TP_CPU_DC_TEST_BG58

CPU_DC_TEST_BG59_BG61

CPU_DC_TEST_BE59_BE61

TP_CPU_DC_TEST_BD61

TP_CPU_DC_TEST_D61

CPU_DC_TEST_C61_A61

TP_CPU_DC_TEST_A58

CPU_DC_TEST_C4_D3

TP_CPU_DC_TEST_D1

TP_CPU_DC_TEST_A4

CPU_CFG<3>

CPU_CFG<2>

CPU_CFG<1>

CPU_CFG<9>

CPU_CFG<8>

CPU_CFG<7>

CPU_CFG<14>

CPU_CFG<12>

CPU_CFG<10>

CPU_CFG<16>

CPU_CFG<15>

CPU_CFG<13>

CPU_CFG<11>

CPU_CFG<5>

TP_CPU_VCC_DIE_SENSE

CPU_AXG_VALSENSE_N

CPU_CFG<4>

=PPVCORE_S0_CPU_VCCAXG

=PP1V05_S0_CPU_VCCIO

CPU_CFG<1> CPU_CFG<0>

CPU_CFG<3>

CPU_CFG<16>

=PPVCORE_S0_CPU

=PEG_R2D_C_P<13>

=PEG_R2D_C_P<11>

=PEG_R2D_C_P<10>

=PEG_R2D_C_P<8>

=PEG_R2D_C_P<7>

=PEG_R2D_C_P<5> =PEG_R2D_C_P<6>

=PEG_R2D_C_P<4>

=PEG_R2D_C_P<3>

=PEG_R2D_C_N<15>

=PEG_R2D_C_N<14>

=PEG_R2D_C_N<13>

=PEG_R2D_C_N<11>

=PEG_R2D_C_N<9>

=PEG_R2D_C_N<8>

=PEG_R2D_C_N<10>

=PEG_R2D_C_N<6> =PEG_R2D_C_N<7>

=PEG_R2D_C_N<5>

=PEG_R2D_C_N<4>

=PEG_R2D_C_N<3>

=PEG_R2D_C_N<0>

=PEG_R2D_C_N<2>

=PEG_R2D_C_N<1>

=PEG_D2R_P<15>

=PEG_D2R_P<14>

=PEG_D2R_P<9>

=PEG_D2R_P<8>

=PEG_D2R_P<6>

=PEG_D2R_P<4>

=PEG_D2R_P<2> =PEG_D2R_P<3>

=PEG_D2R_P<1>

=PEG_D2R_N<12>

=PEG_D2R_N<10>

=PEG_D2R_N<9>

=PEG_D2R_N<8>

=PEG_D2R_N<7>

=PEG_D2R_N<4>

=PEG_D2R_N<3>

=PEG_D2R_N<1>

CPU_PEG_COMP

DMI_S2N_N<3>

DMI_S2N_P<3>

FDI_DATA_N<0>

DMI_N2S_P<3>

DMI_N2S_P<2>

DMI_N2S_P<0>

FDI_DATA_N<1>

FDI_DATA_N<5>

TP_EDP_TX_N<3>

TP_EDP_TX_N<2>

=PEG_D2R_P<0>

=PEG_R2D_C_P<15>

CPU_CFG<2>

=PP1V05_S0_CPU_VCCIO

DMI_S2N_P<0>

DMI_N2S_N<2>

DMI_N2S_P<1>

FDI_DATA_N<3>

FDI_DATA_N<7>

FDI_DATA_P<1>

FDI_DATA_P<7>

FDI_DATA_P<5>

DMI_S2N_N<0>

FDI_LSYNC<1>

FDI_DATA_P<0>

=PEG_D2R_N<2>

=PEG_D2R_N<0>

DMI_S2N_P<2>

DMI_N2S_N<3>

DMI_S2N_N<2>

TP_EDP_TX_P<1>

FDI_LSYNC<0>

FDI_INT

FDI_FSYNC<1>

FDI_FSYNC<0>

CPU_EDP_COMP

CPU_CFG<5>

CPU_CFG<6>

CPU_CFG<7>

FDI_DATA_P<6>

FDI_DATA_P<4>

FDI_DATA_P<2>

=PEG_D2R_P<11>

=PEG_D2R_P<10>

VOLTAGE=0.75V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.3 MM

PPCPU_MEM_VREFDQ_B

MIN_LINE_WIDTH=0.3 MM VOLTAGE=0.75V

MIN_NECK_WIDTH=0.2 MM

PPCPU_MEM_VREFDQ_A

R1010

1 2

R1042

R1049

R1043

R1041

R1040

R1030

1 2

R1031

1 2

R1044

R1046

R1045

R1047

R1064

R1070

R1065

R1071

U1000

P11

P10

AF4

AG4

AF3

AG11

AD2

AC1

AC3

AA4

AC4

AE10

AE11

AE6

AE7

AA11

AA10

W10

W11

AA7

AA6

AC12

AG8

AA3

AC8

AC9

U11

G3 G1 G4

K22

H22

K19

J21

C21

B22

D19

D21

C19

A19

D16

D17

C13

B14

D12

D13

C11

A11

B10

F22

G22

A23

C23

K13

J14

G13

H13

K10

M10

G10

F10

D24

D23

E21

F21

G19

H19

B18

C17

K17

K15

G17

F17

E14

F14

C15

A15

U1000

B50 C51

K49 K53 F53 G53 L51 F51 D52 L53

B54 D53 A51 C53 C55 H49 A55 H51

A58 A59

A61

BD1

BD61

BE1

BE3

BE59

BE61

BG1

BG3

BG4

BG58

BG59

BG61

C59

C61

D61

AG13

AH2

AM14 AM15

AT21

AT49

AU19 AU21

AV19

AY21

AY22

BA19

BA22

BB19

BB21

BD21 BD22 BD25 BD26

BE22

BE24

BE26 BF23

BG22

BG26

H48

K24

K48

L42 L45 L47

M13 M14

N42

N50

P13

U14 W14

BE7 BG7

H45

F48

H43 K43

K45

Q1031

<SCH_NUM>

10 OF 132

10 OF 80

10 24 72

16 43

10 11 13 15

10 24 72

13 15 43

10 24 72

10 11

13 15

10 24 72

BI BI BI BI BI

OUT

IN IN

OUT

SM_RCOMP_2

SM_RCOMP_1

SM_RCOMP_0

SM_DRAMRST*

BCLK_ITP

BCLK_ITP*

DPLL_REF_CLK*

DPLL_REF_CLK

BCLK*

BCLK

RESET*

SM_DRAMPWROK

UNCOREPWRGOOD

PM_SYNC

PROC_SELECT*

PROC_DETECT*

PREQ*

TMS

TRST*

TDI TDO

DBR*

BPM_0* BPM_1* BPM_2* BPM_3* BPM_4* BPM_5* BPM_6* BPM_7*

TCK

PRDY*

THERMTRIP*

CATERR*

PROCHOT*

PECI

(2 OF 9)

CLOCKS

THERMAL

PWR MGMT

JTAG & BPM

DDR3 MISC

IN IN

OUT

IN IN

OUT

IN IN

OUT

BI BI BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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NOTICE OF PROPRIETARY PROPERTY:

PAGE

PAGE TITLE

SHEET

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(IPU) (IPU)

(IPU) (IPU) (IPU) (IPU) (IPU) (IPU)

(IPU)

24 72

10K

1/20W

201

18 27 72

20 24 72

17 72

20 72

20 40 72

39 40 61 72

20 40 72

MF-LF

402

1/16W

402

200

MF-LF

1/16W

MF-LF

1/16W

402

25.5

402

1/16W MF-LF

140

39 72

1/20W

201

BGA

2C-35W

CRITICAL

OMIT_TABLE

IVY-BRIDGE

17 72

NOSTUFF

201

4.99K

1/20W

201

NOSTUFF

1/20W

201

24 72

200

1/16W

402

MF-LF

130

402

MF-LF

1/16W

17 72

18 72

NOSTUFF

1/20W

201

43.2

1/20W

201

24 25

NOSTUFF

1/20W

201

24 25 72

24 72

CPU CLOCK/MISC/JTAG

SYNC_MASTER=J30_MLB

SYNC_DATE=07/14/2011

=MEM_RESET_L

=PP1V05_S0_CPU_VCCIO

PLT_RESET_LS1V1_L

=PP1V5R1V35_S3_CPU_VCCDDR

PM_MEM_PWRGD

=PP1V05_S0_CPU_VCCIO

CPU_RESET_L

CPU_PECI

PM_THRMTRIP_L

XDP_CPU_PRDY_L

XDP_CPU_TCK

XDP_BPM_L<7>

XDP_BPM_L<6>

XDP_BPM_L<5>

XDP_BPM_L<4>

XDP_BPM_L<3>

XDP_BPM_L<2>

XDP_BPM_L<1>

XDP_BPM_L<0>

XDP_DBRESET_L

XDP_CPU_TDO

XDP_CPU_TDI

XDP_CPU_TRST_L

XDP_CPU_TMS

XDP_CPU_PREQ_L

ITPCPU_CLK100M_N

ITPCPU_CLK100M_P

CPU_SM_RCOMP<0> CPU_SM_RCOMP<1> CPU_SM_RCOMP<2>

CPU_PROCHOT_L

CPU_PROC_SEL_L

DPLL_REF_CLK_P DPLL_REF_CLK_N

PM_MEM_PWRGD_R

CPU_PWRGD

PM_SYNC

CPU_PROCHOT_R_L

CPU_CATERR_L

DMI_CLK100M_CPU_P DMI_CLK100M_CPU_N

R1101

R1100

R1120

R1121

R1104

R1125

R1102

R1111

R1126

R1114

R1113

R1112

R1103

U1000

J3 H2

N59 N58

G58 E55 E59 G55 G59 H60 J59 J61

C49

K58

AG3 AG1

A48

C48

N53 N55

C57

F49

C45

D44

BE45

AT30

BF44 BE43 BG43

L56

M60 L59

D45

L55 J58

B46

R1115

<SCH_NUM>

11 OF 132

11 OF 80

10 11 13 15

13 16 27

10 11 13 15

BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI BI BI BI

OUT

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

OUT OUT OUT

OUT

OUT OUT

OUT

OUT OUT

OUT

OUT OUT

BI BI BI BI BI BI BI BI

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

OUT OUT

OUT

OUT OUT

OUT

OUT OUT

BI BI BI BI BI BI BI BI

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

SA_MA_14 SA_MA_15

SA_MA_12 SA_MA_13

SA_MA_11

SA_MA_9

SA_MA_10

SA_MA_8

SA_MA_7

SA_MA_6

SA_MA_5

SA_MA_4

SA_MA_3

SA_MA_2

SA_MA_1

SA_MA_0

SA_DQS_7

SA_DQS_5 SA_DQS_6

SA_DQS_3 SA_DQS_4

SA_DQS_2

SA_DQS_0 SA_DQS_1

SA_DQS_7*

SA_DQS_6*

SA_DQS_5*

SA_DQS_4*

SA_DQS_3*

SA_DQS_2*

SA_DQS_0* SA_DQS_1*

SA_ODT_1

SA_ODT_0

SA_CS_1*

SA_CS_0*

SA_CKE_1

SA_CK_1*

SA_CK_1

SA_CKE_0

SA_CK_0*

SA_CK_0

SA_WE*

SA_RAS*

SA_CAS*

SA_BS_0 SA_BS_1 SA_BS_2

SA_DQ_62 SA_DQ_63

SA_DQ_61

SA_DQ_60

SA_DQ_59

SA_DQ_58

SA_DQ_57

SA_DQ_56

SA_DQ_55

SA_DQ_54

SA_DQ_53

SA_DQ_52

SA_DQ_50 SA_DQ_51

SA_DQ_49

SA_DQ_48

SA_DQ_47

SA_DQ_46

SA_DQ_45

SA_DQ_44

SA_DQ_42 SA_DQ_43

SA_DQ_41

SA_DQ_39 SA_DQ_40

SA_DQ_38

SA_DQ_37

SA_DQ_36

SA_DQ_34 SA_DQ_35

SA_DQ_31

SA_DQ_33

SA_DQ_32

SA_DQ_29 SA_DQ_30

SA_DQ_26

SA_DQ_28

SA_DQ_27

SA_DQ_24 SA_DQ_25

SA_DQ_23

SA_DQ_22

SA_DQ_21

SA_DQ_19 SA_DQ_20

SA_DQ_18

SA_DQ_17

SA_DQ_16

SA_DQ_13 SA_DQ_14 SA_DQ_15

SA_DQ_11 SA_DQ_12

SA_DQ_9 SA_DQ_10

SA_DQ_8

SA_DQ_7

SA_DQ_6

SA_DQ_5

SA_DQ_4

SA_DQ_3

SA_DQ_2

SA_DQ_1

SA_DQ_0

(3 OF 9)

MEMORY CHANNEL A

SB_MA_15

SB_MA_14

SB_MA_12 SB_MA_13

SB_MA_11

SB_MA_10

SB_MA_9

SB_MA_7 SB_MA_8

SB_MA_6

SB_MA_5

SB_MA_4

SB_MA_3

SB_MA_2

SB_MA_1

SB_MA_0

SB_DQS_7

SB_DQS_6

SB_DQS_5

SB_DQS_4

SB_DQS_3

SB_DQS_2

SB_DQS_1

SB_DQS_0

SB_DQS_7*

SB_DQS_6*

SB_DQS_5*

SB_DQS_4*

SB_DQS_3*

SB_DQS_2*

SB_DQS_1*

SB_DQS_0*

SB_ODT_0 SB_ODT_1

SB_CS_1*

SB_CS_0*

SB_CKE_1

SB_CK_1

SB_CK_1*

SB_CK_0*

SB_CKE_0

SB_CK_0

SB_DQ_37

SB_DQ_36

SB_DQ_34 SB_DQ_35

SB_DQ_33

SB_DQ_31 SB_DQ_32

SB_DQ_30

SB_DQ_29

SB_DQ_26 SB_DQ_27 SB_DQ_28

SB_DQ_24 SB_DQ_25

SB_DQ_21 SB_DQ_22 SB_DQ_23

SB_DQ_20

SB_DQ_19

SB_DQ_18

SB_DQ_17

SB_DQ_16

SB_DQ_15

SB_DQ_14

SB_DQ_13

SB_DQ_12

SB_DQ_11

SB_DQ_10

SB_DQ_8 SB_DQ_9

SB_DQ_7

SB_DQ_6

SB_DQ_4 SB_DQ_5

SB_DQ_3

SB_DQ_2

SB_DQ_1

SB_DQ_0

SB_DQ_39

SB_DQ_38

SB_DQ_40 SB_DQ_41 SB_DQ_42

SB_DQ_44

SB_DQ_43

SB_DQ_46

SB_DQ_45

SB_DQ_47

SB_DQ_49

SB_DQ_48

SB_DQ_51

SB_DQ_50

SB_DQ_52

SB_DQ_54

SB_DQ_53

SB_DQ_56

SB_DQ_55

SB_DQ_57

SB_DQ_59

SB_DQ_58

SB_DQ_61

SB_DQ_60

SB_DQ_62

SB_BS_0

SB_DQ_63

SB_BS_2

SB_BS_1

SB_RAS*

SB_CAS*

SB_WE*

(4 OF 9)

MEMORY CHANNEL B

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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NOTICE OF PROPRIETARY PROPERTY:

PAGE

PAGE TITLE

SHEET

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

28 73

28 30 73

29 73

29 30 73

28 30 73

28 73

28 30 73

29 30 73

29 73

29 30 73

CRITICAL

OMIT_TABLE

BGA

IVY-BRIDGE

2C-35W

CRITICAL

OMIT_TABLE

2C-35W

IVY-BRIDGE

BGA

SYNC_MASTER=J30_MLB

SYNC_DATE=07/14/2011

CPU DDR3 INTERFACES

MEM_A_DQ<0> MEM_A_DQ<1> MEM_A_DQ<2>

MEM_A_DQ<4> MEM_A_DQ<5> MEM_A_DQ<6> MEM_A_DQ<7> MEM_A_DQ<8>

MEM_A_DQ<10>

MEM_A_DQ<9>

MEM_A_DQ<12>

MEM_A_DQ<11>

MEM_A_DQ<15>

MEM_A_DQ<14>

MEM_A_DQ<13>

MEM_A_DQ<16> MEM_A_DQ<17> MEM_A_DQ<18>

MEM_A_DQ<20>

MEM_A_DQ<19>

MEM_A_DQ<21> MEM_A_DQ<22> MEM_A_DQ<23>

MEM_A_DQ<25>

MEM_A_DQ<24>

MEM_A_DQ<27> MEM_A_DQ<28>

MEM_A_DQ<26>

MEM_A_DQ<30>

MEM_A_DQ<29>

MEM_A_DQ<32> MEM_A_DQ<33>

MEM_A_DQ<31>

MEM_A_DQ<35>

MEM_A_DQ<34>

MEM_A_DQ<36> MEM_A_DQ<37> MEM_A_DQ<38>

MEM_A_DQ<40>

MEM_A_DQ<39>

MEM_A_DQ<41>

MEM_A_DQ<43>

MEM_A_DQ<42>

MEM_A_DQ<44> MEM_A_DQ<45> MEM_A_DQ<46> MEM_A_DQ<47> MEM_A_DQ<48> MEM_A_DQ<49>

MEM_A_DQ<51>

MEM_A_DQ<50>

MEM_A_DQ<52> MEM_A_DQ<53> MEM_A_DQ<54> MEM_A_DQ<55> MEM_A_DQ<56> MEM_A_DQ<57> MEM_A_DQ<58> MEM_A_DQ<59> MEM_A_DQ<60> MEM_A_DQ<61>

MEM_A_DQ<63>

MEM_A_DQ<62>

MEM_A_BA<2>

MEM_A_BA<1>

MEM_A_BA<0>

MEM_A_CAS_L MEM_A_RAS_L MEM_A_WE_L

MEM_A_CLK_N<0> MEM_A_CKE<0>

MEM_A_CLK_P<1> MEM_A_CLK_N<1>

MEM_A_CKE<1>

MEM_A_CS_L<0> MEM_A_CS_L<1>

MEM_A_ODT<0> MEM_A_ODT<1>

MEM_A_DQS_N<1>

MEM_A_DQS_N<0>

MEM_A_DQS_N<2> MEM_A_DQS_N<3> MEM_A_DQS_N<4> MEM_A_DQS_N<5> MEM_A_DQS_N<6> MEM_A_DQS_N<7>

MEM_A_DQS_P<1>

MEM_A_DQS_P<0>

MEM_A_DQS_P<2>

MEM_A_DQS_P<4>

MEM_A_DQS_P<3>

MEM_A_DQS_P<6>

MEM_A_DQS_P<5>

MEM_A_DQS_P<7>

MEM_A_A<0> MEM_A_A<1> MEM_A_A<2> MEM_A_A<3> MEM_A_A<4> MEM_A_A<5> MEM_A_A<6> MEM_A_A<7> MEM_A_A<8>

MEM_A_A<10>

MEM_A_A<9>

MEM_A_A<11>

MEM_A_A<13>

MEM_A_A<12>

MEM_A_A<15>

MEM_A_A<14>

MEM_B_WE_L

MEM_B_CAS_L MEM_B_RAS_L

MEM_B_BA<1> MEM_B_BA<2>

MEM_B_DQ<63> MEM_B_BA<0>

MEM_B_DQ<62>

MEM_B_DQ<60> MEM_B_DQ<61>

MEM_B_DQ<58> MEM_B_DQ<59>

MEM_B_DQ<57>

MEM_B_DQ<55> MEM_B_DQ<56>

MEM_B_DQ<53> MEM_B_DQ<54>

MEM_B_DQ<52>

MEM_B_DQ<50> MEM_B_DQ<51>

MEM_B_DQ<48> MEM_B_DQ<49>

MEM_B_DQ<47>

MEM_B_DQ<45> MEM_B_DQ<46>

MEM_B_DQ<43> MEM_B_DQ<44>

MEM_B_DQ<42>

MEM_B_DQ<41>

MEM_B_DQ<40>

MEM_B_DQ<38> MEM_B_DQ<39>

MEM_B_DQ<0> MEM_B_DQ<1> MEM_B_DQ<2> MEM_B_DQ<3>

MEM_B_DQ<5>

MEM_B_DQ<4>

MEM_B_DQ<6> MEM_B_DQ<7>

MEM_B_DQ<9>

MEM_B_DQ<8>

MEM_B_DQ<10> MEM_B_DQ<11> MEM_B_DQ<12> MEM_B_DQ<13> MEM_B_DQ<14> MEM_B_DQ<15> MEM_B_DQ<16> MEM_B_DQ<17> MEM_B_DQ<18> MEM_B_DQ<19> MEM_B_DQ<20>

MEM_B_DQ<23>

MEM_B_DQ<22>

MEM_B_DQ<21>

MEM_B_DQ<25>

MEM_B_DQ<24>

MEM_B_DQ<28>

MEM_B_DQ<27>

MEM_B_DQ<26>

MEM_B_DQ<29> MEM_B_DQ<30>

MEM_B_DQ<32>

MEM_B_DQ<31>

MEM_B_DQ<33>

MEM_B_DQ<35>

MEM_B_DQ<34>

MEM_B_DQ<36> MEM_B_DQ<37>

MEM_B_CLK_P<0>

MEM_B_CKE<0>

MEM_B_CLK_N<0>

MEM_B_CLK_N<1>

MEM_B_CLK_P<1>

MEM_B_CKE<1>

MEM_B_CS_L<0> MEM_B_CS_L<1>

MEM_B_ODT<1>

MEM_B_ODT<0>

MEM_B_DQS_N<0> MEM_B_DQS_N<1> MEM_B_DQS_N<2> MEM_B_DQS_N<3> MEM_B_DQS_N<4> MEM_B_DQS_N<5> MEM_B_DQS_N<6> MEM_B_DQS_N<7>

MEM_B_DQS_P<0> MEM_B_DQS_P<1> MEM_B_DQS_P<2> MEM_B_DQS_P<3> MEM_B_DQS_P<4> MEM_B_DQS_P<5> MEM_B_DQS_P<6> MEM_B_DQS_P<7>

MEM_B_A<0> MEM_B_A<1> MEM_B_A<2> MEM_B_A<3> MEM_B_A<4> MEM_B_A<5> MEM_B_A<6>

MEM_B_A<8>

MEM_B_A<7>

MEM_B_A<9> MEM_B_A<10> MEM_B_A<11>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_A<14> MEM_B_A<15>

MEM_A_CLK_P<0>

MEM_A_DQ<3>

U1000

BD37 BF36 BA28

BE39

AU36 AV36

AT40 AU40

AY26

BB26

BB40 BC41

AG6 AJ6

AU6 AV9 AR6

AP8 AT13 AU13

BC7

BB7 BA13 BB11

AP11

BA7

BA9

BB9 AY13 AV14 AR14 AY17 AR19 BA14 AU14

AL6

BB14 BB17 BA45 AR43 AW48 BC48 BC45 AR45 AT48 AY48

AJ10

BA49 AV49 BB51 AY53 BB49 AU49 BA53 BB55 BA55 AV56

AJ8

AP50 AP53 AV54 AT54 AP56 AP52 AN57 AN53 AG56 AG53

AL8

AN55 AN52 AG55 AK56

AL7 AR11

AP6

AJ11

AL11

AR10

AR8

AY11

AV11

AU17

AT17

AW45

AV45

AV51

AY51

AT56

AT55

AK54

AK55

BG35 BB34

BE37 BA30 BC30 AW41 AY28 AU26

BE35 BD35 AT34 AU34 BB32 AT32 AY32 AV32

AY40 BA41

BD39 AT41

U1000

BG39 BD42 AT22

AV43

BA34 AY34

BA36 BB36

AR22

BF27

BE41 BE47

AL4 AL1

AV4 BA4 AU3 AR3 AY2 BA3 BE9

BD9 BD13 BF12

AN3

BF8 BD10 BD14 BE13 BF16 BE17 BE18 BE21 BE14 BG14

AR4

BG18 BF19 BD50 BF48 BD53 BF52 BD49 BE49 BD54 BE53

AK4

BF56 BE57 BC59 AY60 BE54 BG54 BA58 AW59 AW58 AU58

AK3

AN61 AN59 AU59 AU61 AN58 AR58 AK58 AL58 AG58 AG59

AN4

AM60 AL59 AF61 AH60

AR1

AU4

AT2

AM2

AL3

AV1

AV3

BE11

BG11

BD18

BD17

BE51

BG51

BA61

BA59

AR59

AT60

AK61

AK59

BF32 BE33

BD43 AT28 AV28 BD46 AT26 AU22

BD33 AU30 BD30 AV30 BG30 BD29 BE30 BE28

AT43 BG47

BF40 BD45

<SCH_NUM>

12 OF 132

12 OF 80

OUT OUT

OUT

VCCIO_29

VCCIO_28

VCCIO_27

VCCIO_26

VCCIO_25

VCCIO_24

VCCIO_23

VCCIO_22

VCCIO_21

VCCIO_20

VCCIO_19

VCCIO_18

VCCIO_17

VCCIO_16

VCCIO_15

VCCIO_14

VCCIO_13

VCCIO_12

VCCIO_11

VCCIO_10

VCCIO_9

VCCIO_8

VCCIO_7

VCCIO_6

VCCIO_49

VCCIO_48

VCCIO_5

VCCIO_4

VCCIO_3

VCCIO_47

VCCIO_46

VCCIO_45

VCCIO_44

VCCIO_43

VCCIO_1

VCCIO_42

VCCIO_41

VCCIO_40

VCCIO_39

VCCIO_38

VCCIO_37

VCCIO_36

VCCIO_35

VCCIO_34

VCCIO_33

VCCIO_32

VCCIO_31

VCCIO_30

VCCIO_51

VCCIO_50

VCC_76

VCC_75

VCC_74

VCC_73

VCC_72

VCC_71

VCC_70

VCC_69

VCC_68

VCC_67

VCC_66

VCC_64

VCC_63

VCC_62

VCC_61

VCC_60

VCC_59

VCC_58

VCC_57

VCC_56

VCC_55

VCC_54

VCC_53

VCC_52

VCC_51

VCC_50

VCC_49

VCC_48

VCC_47

VCC_46

VCC_45

VCC_44

VCC_43

VCC_42

VCC_41

VCC_40

VCC_39

VCC_38

VCC_37

VCC_36

VCC_35

VCC_34

VCC_33

VCC_32

VCC_31

VCC_30

VCC_29

VCC_28

VCC_27

VCC_26

VCC_25

VCC_24

VCC_23

VCC_22

VCC_21

VCC_20

VCC_19

VCC_18

VCC_17

VCC_16

VCC_15

VCC_14

VCC_13

VCC_12

VCC_11

VCC_10

VCC_9

VCC_8

VCC_7

VCC_6

VCC_5

VCC_4

VCC_3

VCC_2

VCC_1

VCCIO_SEL

VCCPQE_1 VCCPQE_2

VIDALERT*

VIDSCLK VIDSOUT

VCC_SENSE VSS_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

LINES

SENSE SVID QUIET

RAIL

PEG AND DDR

CORE SUPLLY

(6 OF 9)

(7 OF 9)

SENSE

LINE

1.8V

RAIL

SA RAIL

QUIET

RAIL

SENSE

LINE

DDR3-1.5V RAILS

GRPHICS

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8

VDDQ_10

VDDQ_9

VDDQ_11 VDDQ_12 VDDQ_13 VDDQ_14 VDDQ_15 VDDQ_16 VDDQ_17 VDDQ_18

VDDQ_20

VDDQ_19

VDDQ_21 VDDQ_22 VDDQ_23 VDDQ_24 VDDQ_25 VDDQ_26

VCCDQ_1 VCCDQ_2

VDDQ_SENSE

VSS_SENSE_VDDQ

VCCSA_SENSE

VCCSA_VID_0 VCCSA_VID_1

SM_VREF

VAXG_1 VAXG_2

VAXG_4

VAXG_3

VAXG_5 VAXG_6 VAXG_7 VAXG_8 VAXG_9 VAXG_10 VAXG_11 VAXG_12 VAXG_13 VAXG_14 VAXG_15 VAXG_16 VAXG_17 VAXG_18 VAXG_19 VAXG_20 VAXG_21 VAXG_22 VAXG_23 VAXG_24 VAXG_25

VAXG_28

VAXG_26 VAXG_27

VAXG_30

VAXG_29

VAXG_33

VAXG_31 VAXG_32

VAXG_35

VAXG_34

VAXG_36 VAXG_37 VAXG_38 VAXG_39 VAXG_40 VAXG_41 VAXG_42 VAXG_43

VAXG_45

VAXG_44

VAXG_46 VAXG_47 VAXG_48 VAXG_49 VAXG_50 VAXG_51 VAXG_52 VAXG_53 VAXG_54 VAXG_55 VAXG_56

VAXG_SENSE VSSAXG_SENSE

VCCPLL_1 VCCPLL_2 VCCPLL_3

VCCSA_2

VCCSA_1

VCCSA_3 VCCSA_4 VCCSA_5 VCCSA_6 VCCSA_7 VCCSA_8 VCCSA_9 VCCSA_10 VCCSA_11 VCCSA_12 VCCSA_13

VCCSA_15

VCCSA_14

VCCSA_16

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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NOTICE OF PROPRIETARY PROPERTY:

PAGE

PAGE TITLE

SHEET

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Note. VOLTAGE=0V

PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.

(IPU)

Fixed at 1.05V

PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.

Note. VOLTAGE=0V

Note. VOLTAGE=1.05V

(NOT controlled by VCCIO_SEL)

(IPU)

Note. VOLTAGE=1.25V

Note. VOLTAGE=0V Note. VOLTAGE=1.05V

VCCIO_SEL can be NC.

IVB supports 1.05V VCCIO.

PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.

61 72

63 72

58 72

1/16W

130

402

MF-LF

PLACE_NEAR=U1000.C44:2.54mm

201

1/20W MF

PLACE_NEAR=R1310.2:2.54mm

1/20W

MF435%

201

PLACE_NEAR=U1000.A44:38mm

1/20W

MF5%

201

1/20W

MF5%

61 72

100

MF-LF

402

1/16W

PLACE_NEAR=U1000.F43:50.8mm

PLACE_SIDE=TOP

100

1/16W

402

MF-LF

PLACE_NEAR=U1000.AN16:50.8mm PLACE_SIDE=TOP

402

100

1% 1/16W MF-LF

PLACE_NEAR=U1000.G43:50.8mm

PLACE_SIDE=TOP

402

100

MF-LF

1/16W

PLACE_NEAR=U1000.AN17:50.8mm

PLACE_SIDE=TOP

201

1/20W MF

10K

201

1/20W

10K

PLACE_NEAR=U1000.F45:50.8mm

1/16W

402

MF-LF

100

PLACE_SIDE=TOP

PLACE_NEAR=U1000.BC43:50.8mm

MF-LF

402

1/16W

100

PLACE_SIDE=TOP

PLACE_NEAR=U1000.G45:50.8mm

402

100

1% 1/16W MF-LF

PLACE_SIDE=TOP

402

100

1% 1/16W MF-LF

PLACE_NEAR=U1000.BA43:50.8mm

PLACE_SIDE=TOP

PLACE_NEAR=U1000.BJ44:2.54mm

MF-LF

402

1/16W

PLACE_NEAR=U1000.BJ44:2.54mm

MF-LF

402

1/16W

PLACE_NEAR=U1000.BJ44:2.54mm

10% 16V

0.1UF

X7R-CERM 0402

402

MF-LF

100

1/16W

PLACE_NEAR=U1000.U10:50.8mm

58 72

IVY-BRIDGE

2C-35W

BGA

OMIT_TABLE

CRITICAL

OMIT_TABLE

BGA

IVY-BRIDGE

2C-35W

10K

201

NOSTUFF

1/20W

SYNC_MASTER=J30_MLB

SYNC_DATE=07/14/2011

CPU POWER

=PP1V05_S0_CPU_VCCIO

CPU_VCCIO_SEL

=PP1V5_S3_CPU_VCCDQ

CPU_VDDQ_SENSE_P CPU_VDDQ_SENSE_N

CPU_VCCSASENSE

=PP1V8_S0_CPU_VCCPLL_R

=PP1V05_S0_CPU_VCCPQE

=PP1V05_S0_CPU_VCCIO

=PPVCORE_S0_CPU_VCCAXG

=PPVCORE_S0_CPU

CPU_VIDALERT_L

CPU_VIDSOUT

=PP1V5R1V35_S3_CPU_VCCDDR

=PPVCCSA_S0_CPU

CPU_SM_VREF

CPU_VCCSA_VID<0> CPU_VCCSA_VID<1>

CPU_VIDALERT_L_R

=PPVCCSA_S0_CPU

CPU_AXG_SENSE_N

CPU_AXG_SENSE_P

CPU_VIDSOUT_R

CPU_VCCSENSE_P CPU_VCCSENSE_N

CPU_VCCIOSENSE_N

CPU_VCCIOSENSE_P

=PP3V3_S0_CPU_VCCIO_SEL

=PPVCORE_S0_CPU_VCCAXG

=PP1V5R1V35_S3_CPU_VCCDDR

=PPVCORE_S0_CPU

CPU_VIDSCLK_R

CPU_VIDSCLK

VOLTAGE=0.75V

CPU_SM_VREF

R1302

R1300

R1310

1 2

R1311

1 2

R1312

1 2

R1360

R1362

R1361

R1363

R1314

R1313

R1370

R1380

R1371

R1381

R1331

R1330

C1330

R1382

U1000

A26 A29 A31 A34 A35 A38 A39 A42 C26 C27 C32 C34 C37 C39 C42 D27 D32 D34 D37 D39 D42 E26 E28 E32 E34 E37 E38 F25 F26 F28 F32 F34 F37 F38 F42 G42 H25 H26 H28 H29 H32 H34 H35 H37 H38 H40 J25 J26 J28 J29 J32 J34 J35 J37 J38 J40 J42 K26 K27 K29 K32 K34 K35 K37 K39 K42 L25 L28 L33 L36 L40 N26 N30 N34 N38

F43

AA14 AA15 AB17 AB20 AC13 AD16 AD18 AD21 AE14 AE15 AF16 AF18 AF20

AF46

AG15 AG16 AG17 AG20 AG21

AG48 AG50 AG51

AJ14 AJ15

AJ17 AJ21 AJ25 AJ43 AJ47 AK50 AK51 AL14 AL15 AL16 AL20 AL22 AL26 AL45 AL48 AM16 AM17 AM21 AM43 AM47 AN20 AN42 AN45 AN48

BC22

AN16

W16 W17

AM25 AN22

A44 B43 C44

G43

AN17

U1000

AY43

AA46 AB47 AB50 AB51 AB52 AB53 AB55 AB56 AB58 AB59 AC61 AD47 AD48 AD50 AD51 AD52 AD53 AD55 AD56 AD58 AD59 AE46

N45 P47 P48 P50 P51 P52 P53 P55 P56 P61

F45

T48 T58 T59 T61 U46 V47 V48 V50 V51 V52 V53 V55 V56 V58 V59 W50 W51 W52 W53 W55 W56 W61 Y48 Y61

AM28 AN26

BB3 BC1 BC4

L17 L21 N16 N20 N22 P17 P20 R16 R18 R21

U10

U15 V16 V17 V18 V21

D48 D49

W20

AJ28 AJ33 AJ36 AJ40 AL30 AL34 AL38 AL42 AM33 AM36 AM40 AN30 AN34 AN38 AR26 AR28 AR30 AR32 AR34 AR36 AR40 AV41 AW26 BA40 BB28 BG33

BC43 BA43

G45

R1320

<SCH_NUM>

13 OF 132

13 OF 80

10 11 13 15

10 13 16 43

10 13 15 43

11 13 16 27

13 16

58 72

13 16

10 13 16 43

11 13 16 27

10 13 15

(8 OF 9)

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS

VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS

VSS_NCTF VSS_NCTF

VSS_NCTF

VSS_NCTF VSS_NCTF

(9 OF 9)

VSS

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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NOTICE OF PROPRIETARY PROPERTY:

PAGE

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SHEET

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

BGA

2C-35W

IVY-BRIDGE

OMIT_TABLE

CRITICAL

IVY-BRIDGE

CRITICAL

OMIT_TABLE

2C-35W

BGA

SYNC_DATE=07/14/2011

SYNC_MASTER=J30_MLB

CPU GROUNDS

U1000

A13 A17 A21 A25 A28 A33 A37 A40 A45 A49 A53

AA1

AA13 AA50 AA51 AA52 AA53 AA55 AA56

AA8

AB16 AB18 AB21 AB48 AB61

AC10 AC14 AC46

AC6

AD17 AD20

AD4

AD61

AE13

AE8

AF1 AF17 AF21 AF47 AF48 AF50 AF51 AF52 AF53 AF55 AF56 AF58 AF59

AG10 AG14 AG18 AG47 AG52 AG61

AG7

AH4 AH58

AJ13 AJ16 AJ20 AJ22 AJ26 AJ30 AJ34 AJ38 AJ42 AJ45 AJ48

AJ7

AK1 AK52 AL10 AL13 AL17 AL21 AL25 AL28 AL33 AL36 AL40 AL43 AL47 AL61

AM13 AM20 AM22 AM26 AM30

AM34 AM38

AM4

AM42 AM45 AM48 AM58 AN1 AN21 AN25 AN28 AN33 AN36 AN40 AN43 AN47 AN50 AN54

AP10 AP51 AP55

AP7

AR13 AR17 AR21 AR41 AR48 AR61

AR7

AT14 AT19 AT36

AT4

AT45 AT52 AT58 AU1

AU11 AU28 AU32 AU51

AU7

AV17 AV21 AV22 AV34 AV40 AV48 AV55

AW13 AW43 AW61

AW7

AY14 AY19 AY30 AY36

AY4

AY41 AY45 AY49 AY55 AY58

AY9

BA1 BA11 BA17 BA21 BA26 BA32 BA48 BA51 BB53

BC13

BC5

BC57

BD12 BD16 BD19 BD23 BD27 BD32 BD36 BD40 BD44 BD48 BD52 BD56

BD8

BE5 BG9

U1000

BG13 BG17 BG21 BG24 BG28 BG37 BG41 BG45 BG49 BG53

C29 C35 C40

D10 D14 D18 D22 D26 D29 D35

D40 D43 D46 D50 D54 D58

E25 E29

E35 E40 F13 F15 F19 F29 F35 F40 F55

G48 G51

G61

H10 H14 H17 H21

H53 H58

J1 J49 J55

K11 K21 K51

L16 L20 L22 L26 L30 L34 L38 L43 L48 L61

M11 M15

M58

N1 N17 N21 N25 N28 N33 N36 N40 N43 N47 N48 N51 N52 N56 N61

A5 A57 BC61 BD3 BD59 BE4 BE58 BG5 BG57 C3 C58 D59 E1 E61

P14 P16 P18 P21 P58 P59

R17 R20

R46 T1 T47 T50 T51 T52 T53 T55 T56

U13

V20 V61

W13 W15 W18 W21 W46

Y4 Y47 Y58 Y59

<SCH_NUM>

14 OF 132

14 OF 80

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

8 7 6 5 4 3

NOTICE OF PROPRIETARY PROPERTY:

PAGE

PAGE TITLE

SHEET

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Intel recommendation (table 7-5): 2x 1uF, 1x 330uF

CPU VCCPLL DECOUPLING

PLACEMENT_NOTE (C1640-C1645):

Intel recommendation (Table 7-7): 26x 1uF, 10x 10uF, 2x 330uF

PLACEMENT_NOTE (C1684-C167F):

PLACEMENT_NOTE (C1672-C1681):

CPU VCCIO/VCCPQ DECOUPLING

CPU VCCPLL Low pass filter

PLACEMENT_NOTE (C1646-C1671):

Note:The smallest 10mOhm available in the library are 0805s

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

CPU VCORE DECOUPLING

PLACEMENT_NOTE (C1655-C1666):

All INTEL recommendations from Intel doc #458544 Chief River Platform Power Design Guide v0p9

Intel recommendation (Table 7-2): Option 2: 35x 2.2uF, 12x 22uF, 4x 470uF, or Option 3: 35x 2.2uF, 6x 22uF, 6x 330 uF

PLACEMENT_NOTE (C1667-C1679):

0603

1/4W

0.010

10%

X5R

10V

1UF

402

PLACE_NEAR=U1000.AK65:2.54 mm:NO_VIA

CRITICAL

20%

2.2UF

CERM 402-2

6.3V

CRITICAL

20% CERM

6.3V 402-2

2.2UF 2.2UF

20%

6.3V CERM 402-2

CRITICAL

402-2

20%

2.2UF

CERM

CRITICAL

6.3V

2.2UF

20%

CRITICAL

CERM

6.3V 402-2

2.2UF

20%

CRITICAL

CERM

6.3V 402-2

0402

10V X5R-CERM

1UF

10%

CRITICAL

20%

2.2UF

CERM

6.3V 402-2

20% CERM

6.3V 402-2

2.2UF

CRITICAL

2.2UF

CRITICAL

6.3V CERM

CRITICAL

2.2UF

20% CERM

6.3V 402-2

20%

2.2UF

6.3V 402-2

CRITICAL

CERM CERM

20%

6.3V 402-2

2.2UF

CRITICAL

20%

2.2UF

CERM

6.3V 402-2

0402

10V X5R-CERM

1UF

10%

20%

2.2UF

CERM

6.3V 402-2

CRITICAL CRITICAL

20%

2.2UF

CERM

6.3V 402-2

CRITICAL

20%

2.2UF

CERM

6.3V 402-2

CRITICAL

20%

2.2UF

CERM

6.3V 402-2

20%

CRITICAL

CERM

6.3V 402-2

2.2UF 2.2UF

CRITICAL

20% CERM

6.3V 402-2

20%

2.2UF

CERM

6.3V 402-2

CRITICAL CRITICAL

20%

2.2UF

CERM

6.3V 402-2

20%

2.2UF

CRITICAL

CERM

6.3V 402-2

20%

2.2UF

CRITICAL

CERM

6.3V 402-2

CASE-B2-SM

TANT

20% 2V

270UF

20% 2V TANT

270UF

CASE-B2-SM

PLACE_NEAR=U1000.AK61:5mm

270UF

20% TANT

CASE-B2-SM

Place near U1000 on bottom side

0402-1

20%

6.3V

10UF

CERM-X5R

Place near U1000 on bottom side

20%

10UF

CERM-X5R

6.3V

0402-1

Place near U1000 on bottom side

10UF

CERM-X5R

6.3V

20%

0402-1

Place near U1000 on bottom side

10UF

CERM-X5R

6.3V

20%

0402-1

0402

10V X5R-CERM

10%

1UF

6.3V

Place near U1000 on bottom side

10UF

CERM-X5R

20%

0402-1

Place near U1000 on bottom side

10UF

CERM-X5R

6.3V

20%

0402-1

Place near U1000 on bottom side

0402-1

10UF

CERM-X5R

6.3V

20%

Place near U1000 on bottom side

10UF

0402-1

20%

6.3V CERM-X5R

20%

270UF

TANT CASE-B2-SM

270UF

20%

CASE-B2-SM

TANT

PLACE_NEAR=U1000.AK61:5mm

CASE-B2-SM

TANT

270UF

20% 2V

10UF

CERM-X5R

6.3V

20%

0402-1

Place near U1000 on bottom side

20%

20UF

X6T-CERM

2V 0402

20%

Place close to U1000 on bottom side.

20UF

X6T-CERM

2V 0402

0402

10V X5R-CERM

1UF

10%

20%

Place close to U1000 on bottom side.

20UF

X6T-CERM

2V 0402

20%

Place close to U1000 on bottom side.

CRITICAL

20UF

X6T-CERM

2V 0402

CRITICAL

X6T-CERM

20%

CRITICAL

20UF

X6T-CERM

2V 0402

20%

CRITICAL

20UF

X6T-CERM

CRITICAL

20%

NO STUFF

2V 0402

CRITICAL

20%

20UF

X6T-CERM

2V 0402

20%

CRITICAL

X6T-CERM

2V 0402

20%

20UF

X6T-CERM

2V 0402

20% 2V

20%

CRITICAL

20UF

X6T-CERM

2V 0402

20%

20UF

X6T-CERM

2V 0402

20%

Place close to U1000 on bottom side.

CRITICAL

20UF

X6T-CERM

2V 0402

20%

Place close to U1000 on bottom side.

CRITICAL

20UF

X6T-CERM

2V 0402

20%

20UF

X6T-CERM

2V 0402

2V CASE-B2-SM

270UF

20% TANT

20%

270UF

CASE-B2-SM

TANT

0402

10V X5R-CERM

1UF

10%

CRITICAL

20%

20UF

X6T-CERM

2V 0402

20%

20UF

X6T-CERM

2V 0402

20%

20UF

X6T-CERM

2V 0402

20%

CRITICAL

20UF

X6T-CERM

2V 0402

20%

20UF

X6T-CERM

2V 0402

CRITICAL

2V 0402

20%

CRITICAL

20UF

X6T-CERM

2V 0402

20%

CRITICAL

20UF

X6T-CERM

2V 0402

20%

CRITICAL

20UF

X6T-CERM

2V 0402

20%

20UF

X6T-CERM

2V 0402

X5R-CERM 0402

10V

1UF

10%

Place on bottom side of U1000

CRITICAL

20% X6T-CERM

2V 0402

CRITICAL

20% X6T-CERM

2V 0402

CRITICAL

0402

20%

20UF

X6T-CERM

2V 0402

20%

NO STUFF

20UF

X6T-CERM

2V 0402

20%

CRITICAL

20UF

2V 0402

20%

POLY-TANT

2.0V

D2T-SM1

Place near inductors on bottom side.

470UF-4MOHM

0402

10V X5R-CERM

Place on bottom side of U100.

1UF

10%

0402

10V

1UF

Place on bottom side of U1000

10% X5R-CERM

POLY-TANT

20%

Place near inductors on bottom side.

2.0V

D2T-SM1

470UF-4MOHM

CRITICAL

20%

Place close to U1000 on top side.

20UF

X6T-CERM

2V 0402

NO STUFF

20%

CRITICAL

20UF

2V 0402

1UF

0402

10V X5R-CERM

Place on bottom side of U1000

10%

0402

10V X5R-CERM

10%

1UF

D2T-SM1

20%

Place near inductors on bottom side.

2.0V POLY-TANT

470UF-4MOHM

0402

10V X5R-CERM

1UF

10%

470UF-4MOHM

D2T-SM1

POLY-TANT

2.0V

Place near inductors on bottom side.

20%

20UF

X6T-CERM

2V 0402

20UF

X6T-CERM

CRITICAL

20% 2V

0402

20%

CRITICAL

20UF

X6T-CERM

2V 0402

10%

1UF

10V X5R 402

CRITICAL

NO STUFF

CRITICAL

20% 2V

0402

20%

2.2UF

6.3V 402-2

CERM

2.2UF

20% CERM

6.3V 402-2

CRITICAL

2.2UF

CERM 402-2

CRITICAL

20%

6.3V

2.2UF

20%

CRITICAL

CERM

6.3V 402-2

6.3V

20% CERM

402-2

2.2UF

CRITICAL

20% CERM

6.3V

402-2

2.2UF

20%

CRITICAL

CERM

6.3V

20%

CRITICAL

CERM

6.3V 402-2

2.2UF

CRITICAL

20%

402-2

CERM

6.3V

2.2UF

CRITICAL

20%

2.2UF

6.3V CERM

2.2UF

20% CERM

6.3V 402-2

CRITICAL

20%

6.3V

CRITICAL

2.2UF

CERM 402-2

0402

10V

1UF

10% X5R-CERM

0402

10V

1UF

0402

10V X5R-CERM

1UF

10%

0402

10V

1UF

10% X5R-CERM

0402

10V X5R-CERM

10%

1UF

10%

0402

10V X5R-CERM

1UF

10V X5R-CERM

1UF

10%

0402

10V X5R-CERM

10%

1UF

0402

10V X5R-CERM

1UF

10%

0402

10V X5R-CERM

1UF

10%

0402

X5R-CERM

10% 10V

1UF

0402

10V X5R-CERM

1UF

10%

20%

CRITICAL

20UF

X6T-CERM

2V 0402

CRITICAL2VCRITICAL

0402

10V X5R-CERM

10%

1UF

0402

10V X5R-CERM

1UF

10%

0402

10V X5R-CERM

1UF

10%

20%

20UF

2V 0402

10UF

CERM-X5R

6.3V

20%

0402-1

Place near U1000 on bottom side

NO STUFF

CRITICAL

20%

0402

CRITICAL

X6T-CERM 0402

20%

20UF

X6T-CERM

2V 0402

NO STUFF

CRITICAL

20% X6T-CERM

20%

CRITICAL

20UF

X6T-CERM

2V 0402

1/16W

MF-LF

402

10% 10V X5R

1UF

402

PLACE_NEAR=U1000.AK63:2.54 mm:NO_VIA

CPU DECOUPLING-I

SYNC_MASTER=MASTER

SYNC_DATE=MASTER

=PPVCORE_S0_CPU

=PP1V8_S0_CPU_VCCPLL_R

=PP1V05_S0_CPU_VCCPQE

=PP1V8_S0_CPU_VCCPLL

=PP1V05_S0_CPU_VCCIO

CRITICAL

402-2

2.2UF

CRITICAL

402-2

NO STUFF

NO STUFF NO STUFF

NO STUFF

NO STUFF NO STUFF

NO STUFF

402-2

20%

CRITICAL

20UF 20UF

NO STUFF

20UF

20% 2V X6T-CERM

CRITICAL CRITICAL

NO STUFF

CRITICAL

X6T-CERM

Place close to U1000 on bottom side.

CRITICAL CRITICAL

NO STUFF

CRITICAL

0402

X6T-CERM

20%

20UF 20UF

X6T-CERM

CRITICAL

NO STUFF

CRITICAL

0402

X6T-CERM

20%

20UF

NO STUFF NO STUFF

20UF

20% X6T-CERM

0402

CRITICAL

20UF

X6T-CERM

NO STUFF

CRITICAL

20%

20UF 20UF

2V 0402

CRITICAL

NO STUFF

20UF

NO STUFF

CRITICAL

20UF

X6T-CERM

CRITICAL

0402

X6T-CERM

20%

20UF

NO STUFF

0402

CRITICAL

NO STUFF

0402

20%

20UF

NO STUFF NO STUFF

20UF

20% X6T-CERM

CRITICAL

20UF

X6T-CERM 0402

X6T-CERM

R1601

1 2

C167F

C1697

C161F

C1698

C1699

C169A

C169B

C169C

C1684

C1680

C1685

C1686

C1681

C1655

C1656

C1687

C1688

C1682

C1689

C1683

C1670

C1658

C1671

C1659

C1660

C1650

C1625

C1600

C1651

C1652

C1627

C1653

C1628

C1654

C1604

C1631

C1606

C169D

C169E

C169F

C161A

C161B

C161C

C161D

C1690

C1691

C1692

C1693

C1661

C1662

C1663

C1694

C1695

C1696

C1676

C1664

C1665

C1678

C1666

C1679

R1600

1 2

C160X

C160Y

C1632

C1607

C1608

C1635

C1609

C1610

C1637

C1612

C1638

C1613

C1639

C1640

C1615

C1641

C1642

C1617

C1643

C1644

C1645

C1647

C1648

C1623

C1624

C167D

C167E

C160Z

C162A

C162B

C162C

C162D

C162E

C167A

C167B

C167C

C168B

C168A

C168C

C161E

C1668

C1669

C1672

C1673

C165B

C165A

C166F

C166E

C166D

C166C

C166B

C166A

C164C

C164B

C165F

C165E

C165C

C165D

C168D

C168E

C1657

C1649

C164A

C1677

C164E

C1667

C1674

C164D

C164F

C1675

C1646

C168F

C16A0

C16A3

C16A2

C16A1

<SCH_NUM>

16 OF 132

15 OF 80

10 13 43

10 11 13

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

8 7 6 5 4 3

NOTICE OF PROPRIETARY PROPERTY:

PAGE

PAGE TITLE

SHEET

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PLACEMENT_NOTE (C1711-C1716):

PLACEMENT_NOTE (C1717-C1722):

CPU VDDQ/VCCDQ DECOUPLING

VAXG DECOUPLING

Intel recommendation (Table 7-4) for GT2 3.9mOhm LL: 11x 1uF, 6x 10uF, 6x 22uF, 2x 470uF

PLACEMENT_NOTE (C1700-C1710):

PLACEMENT_NOTE (C1758-C1762):

CPU VCCSA DECOUPLING

Intel recommendation (Table 7-9): 5x 1uf, 5x 10uf, 1x 330uf

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

PLACEMENT_NOTE (C1738-C1747):

PLACEMENT_NOTE (C1723-C1724):

Intel recommendation (Table 7-11): 10x 1uF, 8x 10uF, 1x 330uF

0.010

1/4W

0603

0402

10V X5R-CERM

10%

1UF

Place on bottom side of U1000

20% TANT

CASE-B2-SM

270UF

CASE-B2-SM

TANT

270UF

20% 2V

6.3V

20%

0402-1

10UF

CERM-X5R

CRITICAL

0402-1

CRITICAL

10UF

20%

6.3V CERM-X5R

10UF

CERM-X5R

6.3V

CRITICAL

20%

0402-1

20%

0402-1

CRITICAL

10UF

CERM-X5R

6.3V

10UF

CRITICAL

6.3V CERM-X5R

20%

0402-1

2.0V

20%

Place near inductors on bottom side.

POLY-TANT D2T-SM1

470UF-4MOHM

CRITICAL

0402-1

20%

6.3V CERM-X5R

10UF

20%

Place close to U1000 on bottom side

0402-1

CERM-X5R

10UF

6.3V

0402

2V X6T-CERM

20UF

CRITICAL

20%

6.3V

Place close to U1000 on bottom side

10UF

CERM-X5R

20%

0402-1

CERM-X5R 0402-1

20%

6.3V

10UF

Place close to U1000 on bottom sidePlace close to U1000 on bottom side

10UF

CERM-X5R

6.3V

20%

0402-1 0402-1

CERM-X5R

6.3V

20%

Place close to U1000 on bottom side

10UF 10UF

0402-1

20%

6.3V CERM-X5R

Place close to U1000 on bottom side

10UF

CERM-X5R

6.3V

20%

0402-1

10UF

CERM-X5R

6.3V

20%

0402-1

10UF

6.3V

0402-1

CERM-X5R

20%

0402

2V X6T-CERM

20UF

20%

CRITICAL

10UF

CERM-X5R

6.3V

20%

0402-1 0402-1

20%

6.3V CERM-X5R

10UF

CASE-B2-SM

TANT

270UF

20% 2V

CASE-B2-SM

TANT

270UF

20% 2V

Place close to U1000 on bottom side

10UF

CERM-X5R

6.3V

20%

0402-1

Place close to U1000 on bottom side

10UF

CERM-X5R

6.3V

20%

0402-1

0402

2V X6T-CERM

20UF

NO STUFF

CRITICAL

20%

0402

2V X6T-CERM

20UF

NO STUFF

20%

CRITICAL

0402

2V X6T-CERM

20UF

NO STUFF

CRITICAL

20%

0402

2V X6T-CERM

20UF

NO STUFF

CRITICAL

20%

470UF-4MOHM

Place near inductors on bottom side.

POLY-TANT

2.0V

20%

D2T-SM1

0402

2V X6T-CERM

20UF

NO STUFF

CRITICAL

20% 2V X6T-CERM

NO STUFF

20%

CRITICAL

20UF

04020402

2V X6T-CERM

20UF

20%

CRITICAL

1UF

0402

10V X5R-CERM

10%

Place on bottom side of U1000

0402

10V X5R-CERM

10%

1UF

0402

10V X5R-CERM

10%

1UF

0402

10V X5R-CERM

10%

1UF

0402

2V X6T-CERM

20UF

20%

CRITICAL

0402

2V X6T-CERM

20UF

CRITICAL

20%

0402

2V X6T-CERM

20UF

20%

CRITICAL

10V

0402

X5R-CERM

10%

1UF

X5R-CERM 0402

10V

1UF

10%

0402

10V X5R-CERM

10%

1UF

0402

10V X5R-CERM

1UF

CRITICAL

10%

Place on bottom side of U1000

CRITICAL

0402

10V X5R-CERM

1UF

Place on bottom side of U100.

10%

0402

10V X5R-CERM

CRITICAL

10%

Place on bottom side of U1000

1UF

0402

10V X5R-CERM

CRITICAL

1UF

10%

0402

10V X5R-CERM

CRITICAL

1UF

10%

0402

10V X5R-CERM

CRITICAL

10%

1UF

X5R

10% 10V

402

1UF

0402

10V X5R-CERM

CRITICAL

1UF

10%

0402

10V X5R-CERM

1UF

10%

CRITICAL

0402

10V X5R-CERM

CRITICAL

1UF

10%

Place on bottom side of U1000

1UF

10V

10% X5R-CERM

0402

1UF

Place on bottom side of U100.

10V

10% X5R-CERM

0402

Place on bottom side of U1000

10V

1UF

10% X5R-CERM

0402

Place on bottom side of U1000

1UF

10V

10% X5R-CERM

0402

1UF

10% 10V X5R-CERM 0402

0402

10V X5R-CERM

CRITICAL

1UF

10%

0402

10V X5R-CERM

CRITICAL

10%

1UF

Place on bottom side of U1000

10%

0402

10V X5R-CERM

Place on bottom side of U1000

1UF

0402

10V X5R-CERM

10%

Place on bottom side of U100.

1UF

SYNC_DATE=MASTER

SYNC_MASTER=MASTER

CPU DECOUPLING-II

=PP1V5_S3_CPU_VCCDQ

=PPVCCSA_S0_CPU

=PP1V5R1V35_S3_CPU_VCCDDR

=PPVCORE_S0_CPU_VCCAXG

R1702

1 2

C1757

C1738

C1739

C1740

C1723

C1717

C1718

C1724

C1719

C1741

C1742

C1743

C1744

C1720

C1721

C1722

C1745

C1746

C1747

C1700

C1701

C1702

C1704

C1705

C1706

C1707

C1708

C1709

C1758

C1759

C1760

C1761

C1762

C1710

C1703

C1756

C1768

C1711

C1712

C1713

C1714

C1715

C1716

C1748

C1749

C1751

C1752

C1753

C1755

C1763

C1764

C1765

C1766

C1767

C1770

C1769

C1754

C1750

C172A

C1729

C1728

C1727

C1726

C1725

<SCH_NUM>

17 OF 132

16 OF 80

11 13 27

10 13 43

OUT

IN OUT OUT

IN IN OUT OUT

OUT

OUT OUT

OUT

OUT OUT

IN IN

IN OUT OUT

OUT OUT IN

OUT

BI BI

OUT

IHDA

(1 OF 10)

JTAG

SATA

LPC

RTCSPI

HDA_SDIN2

HDA_SDIN0

HDA_SYNC

SPI_CS1*

JTAG_TMS

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

FWH4/LFRAME*

HDA_DOCK_EN*/GPIO33 HDA_DOCK_RST*/GPIO13

HDA_SDIN1

HDA_SDIN3

HDA_SDO

JTAG_TCK

JTAG_TDI

JTAG_TDO

LDRQ0*

LDRQ1*/GPIO23

RTCX2

SATA0GP/GPIO21

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

SATA1GP/GPIO19

SATA1RXN SATA1RXP SATA1TXN SATA1TXP

SATA2RXN SATA2RXP SATA2TXN SATA2TXP

SATA3COMPI SATA3RBIAS

SATA3RCOMPO

SATA3RXN SATA3RXP SATA3TXN SATA3TXP

SATA4RXN SATA4RXP SATA4TXN SATA4TXP

SATA5RXN SATA5RXP SATA5TXN SATA5TXP

SATAICOMPI

SATAICOMPO

SATALED*

SERIRQ

SPI_CLK

SPI_CS0*

SPI_MISO

SPI_MOSI

HDA_RST*

SPKR

RTCX1

HDA_BCLK

INTVRMEN

INTRUDER*

SRTCRST*

RTCRST*

OUT

C-LINK

SMBUS

PCI-E*

CLOCKS

FLEX

CLOCKS

(2 OF 10)

XTAL25_OUT

XTAL25_IN

XCLK_RCOMP

SML1DATA/GPIO75

SML1CLK/GPIO58

SML1ALERT*/PCHHOT*/GPIO74

SML0DATA

SML0CLK

SML0ALERT*/GPIO60

SMBDATA

SMBCLK

SMBALERT*/GPIO11

REFCLK14IN

PETP8

PETP7

PETP6

PETP5

PETP4

PETP3

PETP1

PETN8

PETN7

PETN6

PETN5

PETN4

PETN3

PETN2

PETN1

PERP8

PERP7

PERP6

PERP5

PERP4

PERP3

PERP1

PERN8

PERN6

PERN5

PERN4

PERN3

PERN2

PERN1

PEG_B_CLKRQ*/GPIO56

PEG_A_CLKRQ*/GPIO47

PCIECLKRQ7*/GPIO46

PCIECLKRQ6*/GPIO45

PCIECLKRQ5*/GPIO44

PCIECLKRQ4*/GPIO26

PCIECLKRQ3*/GPIO25

PCIECLKRQ2*/GPIO20

PCIECLKRQ1*/GPIO18

PCIECLKRQ0*/GPIO73

CL_RST1*

CL_DATA1

CL_CLK1

CLKOUT_PEG_B_P

CLKOUT_PEG_B_N

CLKOUT_PEG_A_P

CLKOUT_PEG_A_N

CLKOUT_PCIE7P

CLKOUT_PCIE7N

CLKOUT_PCIE6P

CLKOUT_PCIE6N

CLKOUT_PCIE5P

CLKOUT_PCIE5N

CLKOUT_PCIE4P

CLKOUT_PCIE4N

CLKOUT_PCIE3P

CLKOUT_PCIE3N

CLKOUT_PCIE2P

CLKOUT_PCIE2N

CLKOUT_PCIE1P

CLKOUT_PCIE1N

CLKOUT_PCIE0P

CLKOUT_PCIE0N

CLKOUT_ITPXDP_P

CLKOUT_ITPXDP_N

CLKOUT_DP_P

CLKOUT_DP_N

CLKOUT_DMI_P

CLKOUT_DMI_N

CLKOUTFLEX3/GPIO67

CLKOUTFLEX2/GPIO66

CLKOUTFLEX1/GPIO65

CLKOUTFLEX0/GPIO64

CLKIN_SATA_P

CLKIN_SATA_N

CLKIN_PCILOOPBACK

CLKIN_GND1_P

CLKIN_GND1_N

CLKIN_DOT_96P

CLKIN_DOT_96N

CLKIN_DMI_P

CLKIN_DMI_N

PERN7

PETP2

PERP2

OUT

OUT OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

8 7 6 5 4 3

NOTICE OF PROPRIETARY PROPERTY:

PAGE

PAGE TITLE

SHEET

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(IPU)

(IPD-BOOT)

Connect to ENET_MEDIA_SENSE via alias if HDA = 3.3V. Connect to ENET_MEDIA_SENSE via 12K R if HDA = 1.5V. If HDA = S0, must also ensure that signal cannot be high in S3.

Unused clock terminations for FCIM Mode

(IPU-RSMRST#)

(IPD-PWROK)

(IPU/IPD)

(IPU)

(IPD)

(IPD-BOOT)

(IPD)

DOES THIS NEED LENGTH MATCH???

VSel strap not functional (VCCVRM = 1.8V)

(IPD)

(IPU)

(IPD-PWROK)

(IPU)

(IPD-PWROK)

1.8V -> 1.1V

(IPU-RSMRST#)

Controlled by PCIECLKRQ5#

(IPU/IPD)

(IPD-PLTRST#)

(IPD)

25 74

41 75

39 41

37 74

36 75

42 75

330K

201

1/20W

MF 201

5% 1/20W

20K

201

1/20W

20K

MF 201

5% 1/20W

PLACE_NEAR=U1800.AB10:2.54mm

37.4

1/20W MF 201

10K

MF 201

5% 1/20W

PLACE_NEAR=U1800.AC49:2.54mm

90.9

201

1/20W

42 75

NO STUFF

201

1/20W

NO STUFF

201

1/20W

MF 201

1% 1/20W

25 74

750

MF 201

1% 1/20W

PLACE_NEAR=U1800.AH4:2.54mm

PLACE_NEAR=U1800.AF12:2.54mm

MF 201

1% 1/20W

49.9

36 75

17 36

42 75

11 72

17 75

25 75

17 36

33 75

17 35

NO STUFF

10K

MF 2015%

1/20W

4.7K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

17 26

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

PLACE_NEAR=U1800.F35:1.27mm

MF 2015%

1/20W

PLACE_NEAR=U1800.K37:1.27mm

MF 2015%

1/20W

PLACE_NEAR=U1800.H35:1.27mm

MF 2015%

1/20W

PLACE_NEAR=U1800.H37:1.27mm

MF 2015%

1/20W

51 75

39 41 75

1/20W33MF 2015%

MF 2015%

1/20W

MF 2015%

1/20W

MF 2015%

1/20W

39 41 75

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

PCH-PPT-MB-SFF-ES1

QP8D-MM915462

BGA

OMIT_TABLE

41 75

17 20

51 75

OMIT_TABLE

PCH-PPT-MB-SFF-ES1

QP8D-MM915462

BGA

1.0UF

X5R

0201-MUR

20%

6.3V

1.0UF

X5R 0201-MUR

20%

6.3V

PLACE_NEAR=U1800.W49:5.1mm

604

MF201

1/20W

36 75

7 9

36 75

7 9

SYNC_MASTER=J13_MLB

PCH SATA/PCIe/CLK/LPC/SPI

SYNC_DATE=09/15/2011

XDP_PCH_TDI

RTC_RESET_L

PCH_INTVRMEN_L

=PP1V05_S0_PCH

PCH_SATA3RBIAS

XDP_DC3_PCH_GPIO19_SATARDRVR_EN

HDA_BIT_CLK

HDA_SYNC_R

PCH_SPKR

=PP3V3_SUS_PCH_GPIO =PP3V3_S0_PCH_GPIO

NC_PCIE_6_R2D_CP

NC_PCIE_5_D2RP

PCIE_AP_R2D_C_P

PCIE_AP_D2R_P

PCIE_ENET_R2D_C_N

PCIE_ENET_D2R_N PCIE_ENET_D2R_P

PCIE_ENET_R2D_C_P

PCIE_FW_D2R_N

ITPXDP_CLK100M_P

ITPXDP_CLK100M_N

HDA_SDOUT

HDA_RST_L

HDA_SYNC

XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL

PCH_SATALED_L

TP_SATA_F_D2RN

TP_SATA_D_D2RP

TP_SATA_D_D2RN

NC_PCIE_5_R2D_CP

NC_PCIE_5_R2D_CN

NC_PCIE_5_D2RN

PCIE_EXCARD_R2D_C_P

PCIE_EXCARD_R2D_C_N

PCIE_EXCARD_D2R_P

USB_EXTB_SEL_XHCI

SMBUS_PCH_CLK

DPLL_REF_CLK_P

DPLL_REF_CLK_N

TP_PCIE_CLK100M_PEGAP

DMI_CLK100M_CPU_N DMI_CLK100M_CPU_P

PCIE_CLK100M_FW_P

PCIE_CLK100M_FW_N

PCIE_CLK100M_ENET_P

PCIE_CLK100M_ENET_N

NC_PCIE_8_R2D_CP

FW_CLKREQ_L

PCIE_CLK100M_EXCARD_P

PCIE_CLK100M_EXCARD_N

SSD_CLKREQ_L

TP_PCIE_CLK100M_PEBN

ENET_CLKREQ_L

PCIE_CLK100M_SSD_P

TP_PCIE_CLK100M_PEBP

PEG_CLK100M_N PEG_CLK100M_P

PCIE_CLK100M_TBT_N

PCIE_CLK100M_SSD_N

PEG_CLKREQ_L

AP_CLKREQ_L

PEGCLKRQB_L_GPIO56

PCIE_CLK100M_AP_P

PCIE_CLK100M_AP_N

NC_PCIE_7_D2RP

JTAG_DPMUXUC_TRST_L

PCH_CLKIN_GNDN1

SML_PCH_0_DATA

NC_PCIE_6_D2RN NC_PCIE_6_D2RP NC_PCIE_6_R2D_CN

PCH_SPKR

AP_CLKREQ_L

JTAG_ISP_TMS

SYSCLK_CLK25M_SB_R

SYSCLK_CLK25M_SB

PCH_CLK96M_DOT_P

PCH_CLK96M_DOT_N

SML_PCH_1_CLK

PCH_SRTCRST_L PCH_INTRUDER_L

PCH_CLKIN_GNDP1

PCIE_CLK100M_PCH_P

PCH_CLK100M_SATA_N

PCH_CLK96M_DOT_P

=PP3V3_S0_PCH

ITPCPU_CLK100M_P

PCIE_CLK100M_PCH_N

PCH_CLK100M_SATA_P

PCH_CLK96M_DOT_N

PCH_CLK14P3M_REFCLK

LPC_AD<0>

LPC_AD<3>

LPC_AD<2>

NC_PCIE_8_D2RN NC_PCIE_8_D2RP

NC_PCIE_7_D2RN

NC_PCIE_7_R2D_CP

PCIE_AP_R2D_C_N

SML_PCH_0_CLK

USB_EXTD_SEL_XHCI

SML_PCH_1_DATA

TP_CLINK_CLK TP_CLINK_DATA TP_CLINK_RESET_L

PEGCLKRQA_L_GPIO47 TP_PCIE_CLK100M_PEGAN

PCIE_CLK100M_PCH_N

PCH_CLKIN_GNDN1 PCH_CLKIN_GNDP1

PCH_CLK100M_SATA_P

PCH_CLK100M_SATA_N

=PP1V05_S0_PCH_VCCDIFFCLK

PCH_XCLK_RCOMP

TP_PCH_GPIO64_CLKOUTFLEX0

TP_PCH_GPIO65_CLKOUTFLEX1

TP_PCH_GPIO66_CLKOUTFLEX2

=PPVRTC_G3_PCH

RTC_RESET_L

PCH_INTRUDER_L

PCH_INTVRMEN_L

HDA_BIT_CLK_R

HDA_RST_R_L

SPI_MOSI_R

SPI_MISO

TP_SATA_E_D2RN

TP_SATA_D_R2D_CN

TP_SATA_C_R2D_CP

TP_SATA_C_R2D_CN

TP_SATA_C_D2RP

TP_SATA_C_D2RN

SATA_ODD_R2D_C_P

SATA_ODD_R2D_C_N

SATA_ODD_D2R_P

SATA_ODD_D2R_N

SATA_HDD_R2D_C_P

SATA_HDD_R2D_C_N

SATA_HDD_D2R_P

SATA_HDD_D2R_N

TBT_PWR_EN_PCH

TP_LPC_DREQ0_L

XDP_PCH_TCK

HDA_SDOUT_R

TP_HDA_SDIN3

TP_HDA_SDIN1

ENET_MEDIA_SENSE_RDIV

JTAG_ISP_TMS

LPC_FRAME_R_L

LPC_AD_R<3>

LPC_AD_R<2>

LPC_AD_R<1>

LPC_AD_R<0>

HDA_SDIN0

TP_HDA_SDIN2

ITPCPU_CLK100M_N

SYSCLK_CLK25M_SB_R

LPC_FRAME_L

PCH_CLK33M_PCIIN

PCIE_FW_R2D_C_P

PCIE_FW_R2D_C_N

PCIE_FW_D2R_P

PCIE_EXCARD_D2R_N

=PP3V3_TBT_PCH_GPIO

TP_SATA_E_R2D_CP

PCIE_AP_D2R_N

SMBUS_PCH_DATA

SMBUS_PCH_ALERT_L

HDA_SDOUT_R

LPC_AD<1>

JTAG_DPMUXUC_TRST_L

TP_PCIE_CLK100M_PE4N TP_PCIE_CLK100M_PE4P

TBT_CLKREQ_L

HDA_SYNC_R

ENET_MEDIA_SENSE_RDIV

USB_EXTD_SEL_XHCI

USB_EXTB_SEL_XHCI

SMBUS_PCH_ALERT_L

EXCARD_CLKREQ_L

FW_CLKREQ_L

PCH_SATALED_L DP_AUXCH_ISOL

SATARDRVR_EN

SYSCLK_CLK32K_RTC

NC_PCIE_7_R2D_CN

PCIE_CLK100M_PCH_P

PCH_CLK14P3M_REFCLK

TP_PCH_GPIO67_CLKOUTFLEX3

PCIE_CLK100M_TBT_P

PCH_SRTCRST_L

EXCARD_CLKREQ_L

TP_SATA_E_D2RP TP_SATA_E_R2D_CN

LPC_AD_R<0> LPC_AD_R<1> LPC_AD_R<2>

HDA_BIT_CLK_R

LPC_FRAME_R_L

LPC_AD_R<3>

PEGCLKRQB_L_GPIO56

PEGCLKRQA_L_GPIO47

SSD_CLKREQ_L

TBT_CLKREQ_L

PEG_CLKREQ_L

ENET_CLKREQ_L

HDA_RST_R_L

XDP_PCH_TDO

XDP_PCH_TMS

SPI_CLK_R

SPI_CS0_R_L

TP_SPI_CS1_L

LPC_SERIRQ

=PP1V05_S0_PCH_VCCIO_SATA

TP_SATA_D_R2D_CP

PCH_SATAICOMP

NC_PCIE_8_R2D_CN

PCH_SATA3COMP

TP_SATA_F_R2D_CP

TP_SATA_F_D2RP TP_SATA_F_R2D_CN

R1800

R1801

R1802

R1803

R1830

R1820

R1890

R1840

1 2

R1841

1 2

R1886

R1832

R1831

R1876

1 2

R1877

1 2

R1878

1 2

R1834

1 2

R1842

1 2

R1869

1 2

R1844

1 2

R1845

1 2

R1847

1 2

R1814

2 1

R1815

1 2

R1843

1 2

R1833

1 2

R1879

1 2

R1846

1 2

R1853

1 2

R1848

1 2

R1854

1 2

R1855

1 2

R1812

1 2

R1813

1 2

R1810

1 2

R1811

1 2

R1861

1 2

R1862

1 2

R1863

1 2

R1864

1 2

R1860

1 2

R1891

1 2

R1892

1 2

R1893

1 2

R1894

1 2

R1895

1 2

R1896

1 2

R1897

1 2

R1870

1 2

R1871

1 2

U1800

A37 A39 C39 C37 K40

H35

K35 M35

F35

D36 B36 C35 A35

K37

H37

K22

C21

M17

U12

M12

M15

H40 F37

F19

A19 C19

AN3 AN1 AU3 AU1

AN6 AN8 AR3 AR1

AD4 AD2 AL3 AL1

AF12 AH4

AF10

AD8 AD6 AG3 AG1

AE3 AE1 AH8 AH6

AC3 AC1 AJ3 AJ1

AB12

AB10

W10

AD12

AB8

AB6

A23

U1800

L3 J1 M8

BD17 BF17

M24 K24

BB26 AY26

E51

AK8 AK6

BB24 AY24

AN10 AN12

AR12 AR10

AD48 AD50

AE49 AE51

AD40 AD42

AA49 AA51

Y48 Y50

AB40 AB42

AB44 AB46

W44 W46

AF44 AF46

AF40 AF42

H50

D48

G49

J51

M19

BJ33

BJ35

BH36

BJ37

BJ39

BH40

BJ41

BJ43

BL33

BL35

BK36

BL37

BL39

BK40

BL41

BL43

BB30

BB33

BF33

BD35

AY35

BD37

AY37

AY40

AY30

AY33

BD33

BF35

BB35

BF37

BB37

BB40

J49

H12 F17 F10

H22 K12 A9

C9 D12 C11

AC49

W49 W51

C1802

C1803

R1885

1 2

<SCH_NUM>

18 OF 132

17 OF 80

17 75

18 19 20

18 19 20 25 35

24 72

7 9

17 36

17 20

17 74

17 75

11 72

17 75

21 23

18 21

17 75

17 25 75

11 72

17 74

17 25 75

17 75

17 26

24 25

17 75

17 35

17 36

17 75

OUT

OUT OUT

OUT

OUT OUT OUT

OUT

IN IN IN IN

IN IN IN

OUT

FDI

(3 OF 10)

DMI

SYSTEM POWER

MANAGEMENT

DMI_ZCOMP

DMI3TXN

DMI2TXN

DMI1TXN

DMI0TXN

FDI_LSYNC1

DSWVRMEN

FDI_FSYNC1

FDI_FSYNC0

FDI_RXP5

FDI_RXP4

FDI_RXP3

FDI_RXP2

FDI_RXP1

FDI_RXP0

APWROK

CLKRUN*/GPIO32

DMI0RXN DMI1RXN DMI2RXN

DMI2RXP

DMI3RXN

DMI3RXP

DMI3TXP

DPWROK

DRAMPWROK

FDI_INT

FDI_LSYNC0

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP6 FDI_RXP7

PMSYNCH

PWROK

SLP_A*

SLP_LAN*/GPIO29

SLP_S3*

SLP_S4*

SLP_S5*/GPIO63

SLP_SUS*

SUSACK*

SUSCLK/GPIO62

SUS_STAT*/GPIO61

SYS_PWROK

SYS_RESET*

WAKE*

RI*

BATLOW*/GPIO72

ACPRESENT/GPIO31

PWRBTN*

SUSWARN*/SUSPWRDNACK/GPIO30

RSMRST*

DMI1RXP

DMI0RXP

DMI_IRCOMP

DMI2RBIAS

DMI0TXP DMI1TXP DMI2TXP

(4 OF 10)

LVDS

DIGITAL DISPLAY INTERFACE

CRT

LVDSA_DATA0* LVDSA_DATA1*

LVDSB_DATA3*

LVDSB_DATA2*

CRT_BLUE

CRT_DDC_CLK CRT_DDC_DATA

CRT_GREEN

CRT_HSYNC

CRT_IRTN

CRT_RED

CRT_VSYNC

DAC_IREF

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPB_AUXN DDPB_AUXP

DDPB_HPD

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPC_AUXN DDPC_AUXP

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_HPD

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

DDPD_AUXN DDPD_AUXP

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_HPD

LVDSA_CLK

LVDSA_CLK*

LVDSA_DATA2* LVDSA_DATA3*

LVDSA_DATA0 LVDSA_DATA1

LVDSA_DATA3

LVDSB_CLK

LVDSB_CLK*

LVDSB_DATA0* LVDSB_DATA1*

LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3

LVD_VREFH LVD_VREFL

L_DDC_CLK L_DDC_DATA

SDVO_CTRLCLK

SDVO_CTRLDATA

SDVO_INTN SDVO_INTP

SDVO_STALLN SDVO_STALLP

SDVO_TVCLKINN SDVO_TVCLKINP

L_BKLTEN L_VDD_EN

L_BKLTCTL

LVD_IBG LVD_VBG

LVDSA_DATA2

L_CTRL_CLK L_CTRL_DATA

NC NC NC NC

NC NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

8 7 6 5 4 3

NOTICE OF PROPRIETARY PROPERTY:

PAGE

PAGE TITLE

SHEET

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(IPU)

(IPD-PLTRST#)

(IPD) (IPD)

(IPD-DeepS4/S5)

(IPD-PLTRST#)

10 72

PLACE_NEAR=U1800.BF19:12.7mm

1/20W

201

49.9

10 72

1/20W

201

PLACE_NEAR=U1800.R51:2.54mm

201

750

PLACE_NEAR=U1800.BK20:2.54mm

1/20W

201

390K

1/20W

201

10K

1/20W

201

18 66

1/20W

201

100K

25 39

24 39 66

11 27 72

25 66

18 24 39

39 40 66

18 36

18 39 41

25 39 41

18 39 66

18 27 36 38 39 66

18 27 36 39 66

11 72

10 72

1/20W

5% 201MF

100K

1/20W

5% 201MF

1/20W

5% 201MF

8.2K

1/20W

5% 201MF

1/20W

5% 201MF

100K

1/20W

5% 201MF

100K

1/20W

5% 201MF

100K

1/20W

201

10K

1/20W

5% 201MF

10K

BGA

PCH-PPT-MB-SFF-ES1

OMIT_TABLE

QP8D-MM915462

BGA

QP8D-MM915462

PCH-PPT-MB-SFF-ES1

OMIT_TABLE

1/20W

201

100K

SYNC_DATE=09/15/2011

SYNC_MASTER=J13_MLB

PCH DMI/FDI/PM/Graphics

PCIE_WAKE_L

PM_SLP_S5_L PM_SLP_S4_L PM_SLP_S3_L

TP_PM_SLP_A_L

PM_SLP_SUS_L

PM_SYNC

PCH_GPIO29

LPC_PWRDWN_L

PCH_DSWVRMEN

FDI_INT

FDI_DATA_P<7>

SMC_ADAPTER_EN

PCH_DMI2RBIAS

FDI_DATA_N<1>

TP_CRT_IG_VSYNC

TP_DP_IG_D_MLP<1>

TP_DP_IG_D_MLN<1>

TP_DP_IG_D_MLN<0>

TP_DP_IG_D_AUXN

TP_DP_IG_C_MLP<1>

TP_DP_IG_C_MLN<1>

DPB_IG_DDC_DATA

TP_DP_IG_B_MLP<2>

TP_DP_IG_B_MLN<0> TP_DP_IG_B_MLP<0>

DPA_IG_HPD

DPA_IG_AUX_CH_P

LVDS_IG_BKL_PWM

LVDS_IG_PANEL_PWR

DPA_IG_DDC_DATA

DPA_IG_AUX_CH_N

PM_RSMRST_L

PM_SLP_SUS_L

=PP3V3_SUS_PCH_GPIO

PM_PWRBTN_L PM_CLKRUN_L PCH_GPIO29

PM_SLP_S5_L

PCH_SUSWARN_L

PCH_DMI_COMP

=PP3V3_SUS_PCH_GPIO

TP_CRT_IG_GREEN

PCH_DAC_IREF

TP_DP_IG_B_MLN<1>

TP_DP_IG_B_MLN<2>

TP_DP_IG_B_MLN<3> TP_DP_IG_B_MLP<3>

TP_DP_IG_C_MLN<0>

TP_DP_IG_C_MLN<2>

TP_DP_IG_C_MLN<3> TP_DP_IG_C_MLP<3>

DPB_IG_AUX_CH_N DPB_IG_AUX_CH_P

DPB_IG_DDC_CLK

DPB_IG_HPD

TP_DP_IG_D_MLP<0>

TP_DP_IG_D_MLN<2>

TP_DP_IG_D_MLN<3> TP_DP_IG_D_MLP<3>

TP_DP_IG_D_AUXP

TP_DP_IG_D_CTRL_CLK TP_DP_IG_D_CTRL_DATA

TP_DP_IG_D_HPD

DPA_IG_DDC_CLK

TP_SDVO_STALLN TP_SDVO_STALLP

TP_SDVO_TVCLKINN

PM_CLK32K_SUSCLK_R

FDI_DATA_P<6>

FDI_DATA_P<5>

FDI_FSYNC<1>

FDI_LSYNC<1>

FDI_LSYNC<0>

=PPVRTC_G3_PCH

DMI_S2N_N<3>

DMI_S2N_N<1>

DMI_S2N_N<0>

PM_PCH_APWROK

PM_CLKRUN_L

DMI_N2S_N<0> DMI_N2S_N<1> DMI_N2S_N<2>

DMI_N2S_P<2>

DMI_N2S_N<3>

DMI_N2S_P<3>

PM_MEM_PWRGD

FDI_DATA_N<0>

FDI_DATA_N<2> FDI_DATA_N<3> FDI_DATA_N<4>

FDI_DATA_N<6>

PM_PCH_PWROK

PCH_SUSACK_L

PM_PCH_SYS_PWROK

PM_SYSRST_L

PCIE_WAKE_L

PM_BATLOW_L

PM_PWRBTN_L

PCH_SUSWARN_L

DMI_N2S_P<1>

DMI_N2S_P<0>

DMI_S2N_P<0> DMI_S2N_P<1>

PM_DSW_PWRGD

=PP1V05_S0_PCH_VCCIO_PCIE

FDI_DATA_P<0>

DMI_S2N_N<2>

DMI_S2N_P<2> DMI_S2N_P<3>

FDI_FSYNC<0>

FDI_DATA_P<4>

FDI_DATA_N<7>

FDI_DATA_P<3>

FDI_DATA_P<2>

FDI_DATA_P<1>

FDI_DATA_N<5>

TP_CRT_IG_BLUE

TP_CRT_IG_RED

TP_CRT_IG_DDC_CLK

TP_CRT_IG_HSYNC

PM_SLP_S3_L PM_SLP_S4_L

=PP3V3_S0_PCH_GPIO =PP3V3_S5_PCH

=PP3V3_SUS_PCH_GPIO

PCH_SUSACK_L

TP_CRT_IG_DDC_DATA

TP_DP_IG_D_MLP<2>

TP_SDVO_TVCLKINP

TP_SDVO_INTP

LVDS_IG_BKL_ON

TP_DP_IG_B_MLP<1>

TP_DP_IG_C_MLP<2>

TP_DP_IG_C_MLP<0>

TP_SDVO_INTN

PCH_RI_L

R1900

R1951

R1920

R1915

R1905

R1986

R1909

R1923

2 1

R1925

1 2

R1991

1 2

R1985

1 2

R1922

2 1

R1921

2 1

R1924

2 1

R1983

R1982

1 2

U1800

H19

H10

BL21

BJ21

BD22

BF22

BL23

BJ23

BB22

AY22

BK20

BJ19

BL19

BB19

AY19

BL17

BJ17

BB17

AY17

BD19

BF19

A21

B12

F22

BH12 BK8

BB10

BK12 BH8

BL13 BJ15 BD12 BJ11 AY15 AY12 BJ9 BF10

BJ13 BL15 BF12 BL11 BB15 BB12 BL9 BD10

BB8

K19

M22

F12

B20

K10

A15

F15

C13

M10

U1800

M46

R49 N49

R46

M50

T48

U46

N51

R51

AY48 AY50 AY44 AY46 BB44 BB46 BA49 BA51

AW51 AW49 AY42

BC49 BC51 BD48 BD50 BF46 BF45 BE49 BE51

AU51 AU49

T50 U44

BE46

BG51 BG49 BF42 BD42 BJ47 BL47 BL45 BJ45

AU46 AU44

M48 U42

BK44

L49

M44

R42 M40

L51 K46

M42

AH42 AH40

AG51 AG49

AK46

AK44

AR44

AR46

AN51

AN49

AN46

AN44

AK42

AK40

AH44

AH46

AM48

AM50

AL51

AL49

AJ49

AJ51

AH48

AH50

W42 R44

AT50 AT48

AR51 AR49

AU40 AU42

R1955

<SCH_NUM>

19 OF 132

18 OF 80

18 36

18 66

17 18 19 20

18 24 39

18 39 41

18 39 66

17 18 19 20

17 21

18 27 36 39 66

18 27 36 38 39 66

17 19 20 25 35

17 18 19 20

NC NC

NC NC NC

BI BI

OUT

OUT OUT

IN IN IN

IN IN IN IN

OUT

(5 OF 10)

USB

PCI

PME*

PLTRSTB*

PIRQA*

TP2

TP5

TP4

TP11

USB3RN4

USB3RN2

CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4

GNT1*/GPIO51 GNT2*/GPIO53 GNT3*/GPIO55

OC0*/GPIO59 OC1*/GPIO40 OC2*/GPIO41 OC3*/GPIO42 OC4*/GPIO43

OC5*/GPIO9 OC6*/GPIO10 OC7*/GPIO14

PIRQB* PIRQC* PIRQD*

PIRQE*/GPIO2 PIRQF*/GPIO3 PIRQG*/GPIO4 PIRQH*/GPIO5

REQ1*/GPIO50 REQ2*/GPIO52 REQ3*/GPIO54

RSVD

TP1

TP3

TP6 TP7 TP8 TP9 TP10

TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20 TP21 TP22 TP23 TP24

TP41 TP42

USB3RN1

USB3RN3

USB3RP1 USB3RP2 USB3RP3 USB3RP4

USB3TN1 USB3TN2 USB3TN3 USB3TN4

USB3TP1 USB3TP2 USB3TP3 USB3TP4

USBP0N USBP0P

USBP10N USBP10P

USBP11N USBP11P

USBP12N USBP12P

USBP1N USBP1P

USBP2N USBP2P

USBP3N USBP3P

USBP4N USBP4P

USBP5N USBP5P

USBP6N USBP6P

USBP7N USBP7P

USBP8N USBP8P

USBP9N USBP9P

USBRBIAS

USBRBIAS*

USBP13P

USBP13N

NC NC

BI BI

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

8 7 6 5 4 3

NOTICE OF PROPRIETARY PROPERTY:

PAGE

PAGE TITLE

SHEET

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Ext A (XHCI/EHCI)

USB Hub (All LS/FS Devices)

RSVD: BT (HS)

(IPU-PCIERST#)

(IPU)

(IPD)

Unused

RSVD: SD

Ext B (EHCI)

Ext D (EHCI)

Unused

Redundant to pull-up on audio page

RSVD: WiFi

Ext B (XHCI)

Ext C (XHCI/EHCI)

Ext D (XHCI) (Mobiles: Trackpad)

Camera

Redundant to pull-up on audio page

26 74

38 74

36 74

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

NO STUFF

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

NO STUFF

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

19 55

19 33

19 54

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

NO STUFF

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

19 24

38 74

OMIT_TABLE

PCH-PPT-MB-SFF-ES1

QP8D-MM915462

BGA

38 74

32 74

PLACE_NEAR=U1800.A33:2.54mm

22.6

MF 201

1% 1/20W

25 27

25 75

SYNC_DATE=09/15/2011

PCH PCI/USB/TP/RSVD

SYNC_MASTER=J13_MLB

TP_PCI_CLK33M_OUT3

XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L

USB_EXTD_XHCI_P

USB_EXTB_XHCI_P

USB_EXTC_P

USB_EXTC_N

USB_EXTA_P

USB_EXTB_XHCI_N

USB_EXTD_XHCI_N

=PP3V3_SUS_PCH_GPIO =PP3V3_S3_PCH_GPIO =PP3V3_S0_PCH_GPIO

=PP3V3_S0_PCH_GPIO

AUD_IP_PERIPHERAL_DET TBT_PWR_REQ_L

AUD_I2C_INT_L

XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L

XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L

AP_PWR_EN

XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L

PCI_INTB_L

USB_EXTB_EHCI_P

USB_EXTD_EHCI_N

USE_HDD_OOB_L

BLC_I2C_MUX_SEL

TP_USB_WLANN

USB_EXTA_N

TP_USB_4N TP_USB_4P

TP_USB_SDN TP_USB_SDP

XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L

XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L

XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

XDP_DB2_PCH_GPIO10_AP_PWR_EN

TP_USB_13N TP_USB_13P

USB_EXTD_EHCI_P

USB_EXTB_EHCI_N

USB_CAMERA_N

USB_HUB_UP_N

TP_USB_12P

TP_USB_BT_HSN TP_USB_BT_HSP

TP_USB_12N

TP_PCH_TP23

USB3_EXTB_RX_N

USB3_EXTC_RX_N

USB3_EXTA_RX_N

USB3_EXTC_RX_P

USB3_EXTD_RX_P

USB3_EXTB_RX_P

USB3_EXTA_TX_N USB3_EXTC_TX_N USB3_EXTB_TX_N USB3_EXTD_TX_N

USB3_EXTB_TX_P

USB3_EXTC_TX_P

USB3_EXTA_TX_P

USB3_EXTD_TX_P

PCI_INTC_L

PCI_INTA_L

PCI_INTD_L

LPC_CLK33M_SMC_R

TP_PCI_CLK33M_OUT2

LPC_CLK33M_LPCPLUS_R

PCH_CLK33M_PCIOUT

TP_PCI_PME_L PLT_RESET_L

AUD_IP_PERIPHERAL_DET

AUD_I2C_INT_L

USB3_EXTD_RX_N

USB_HUB_UP_P

TP_USB_WLANP

USB3_EXTA_RX_P

USB_CAMERA_P

PCH_USB_RBIAS

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L

JTAG_GMUX_TMS

BLC_GPIO

XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L

TBT_PWR_REQ_L

BLC_GPIO

PCH_STRP_TOPBLK_SWP_L

TP_PCH_STRP_ESI_L

TP_PCH_STRP_BBS1

USE_HDD_OOB_L

BLC_I2C_MUX_SEL

JTAG_GMUX_TMS

R2070

R2067

2 1

R2068

1 2

R2061

1 2

R2062

1 2

R2033

1 2

R2060

1 2

R2030

1 2

R2018

1 2

R2016

1 2

R2017

1 2

R2014

1 2

R2031

1 2

R2010

1 2

R2011

1 2

R2012

1 2

R2013

1 2

R2054

2 1

R2069

1 2

U1800

G51 E49 H48 J43 G45

F42 H42 D44

C17 A17 A13 D16 A11 B16 C23 H15

D49 C48 C47 C45

A47 C41 F45 F40

G46 K44 F46

AU6 AU8

BB6 BC1 BC3 BD2 BD4 BE1 BE3 BE6 BF6 BF7

AW1

BG1 BG3 BH3 BH4 BJ4 BJ5 BJ7 BK6 BL5

AW3 AY2 AY4 AY6 AY8 BA1 BA3

BH24

D20 M30

E3 AM4 AT4 AT2

AD10

B24 D24

AD44

BK24

AD46 BJ48

BL7 W40 K30

BH20 BK16

BH49 BB42

BH16 AN42 AN40 AR40 AR42

BJ25 BJ27 BJ31 BJ29

BL25 BL27 BL31 BL29

BF26 BB28 BF28 BF30

BD26 AY28 BD28 BD30

F24 H24

C31 A31

H33 F33

H30 F30

M33 K33

C25 A25

C27 A27

H28 F28

M26 K26

D28 B28

H26 F26

D32 B32

M28 K28

C29 A29

A33

C33

<SCH_NUM>

20 OF 132

19 OF 80

19 24

17 18 20

17 18 19 20 25 35

19 55

19 33

19 54

19 24

24 36 66

19 24

OUTOUT

OUT

NCTF

CPU/MISC

(6 OF 10)

GPIO

GPIO1 GPIO6

VSS_NCTF

TS_VSS4

TS_VSS3

TS_VSS2

TS_VSS1

THRMTRIP*

STP_PCI*/GPIO34

SATA3GP/GPIO37

SATA2GP/GPIO36

RCIN*

PROCPWRGD

PECI

NC_1

INIT3_3V*

GPIO71

GPIO70

GPIO69

GPIO68

GPIO35

GPIO8

GPIO7

DF_TVS

A20GATE

GPIO24 GPIO27 GPIO28

BMBUSY*/GPIO0

LAN_PHY_PWR_CTRL/GPIO12 GPIO15 SATA4GP/GPIO16 GPIO17 SCLOCK/GPIO22

SLOAD/GPIO38 SDATAOUT0/GPIO39 SDATAOUT1/GPIO48 SATA5GP/GPIO49 GPIO57

OUT

S G

OUT

S G

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

8 7 6 5 4 3

NOTICE OF PROPRIETARY PROPERTY:

PAGE

PAGE TITLE

SHEET

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

THIS SIGNAL IS INTENDED FOR FIRMWARE HUB AND WE ARE NOT USING IT.

TBT_PWR_EN goes high for JTAG Programming

This has internal pull up and should not pulled low.

(IPD-PLTRST#)

(IPU-RSMRST#)

(IPD-PLTRST#?)

(IPU)

(IPU-DeepS4/S5)

(IPU)

(IPD)

DF_TVS:DMI & FDI Term Voltage Set to Vss when Low Set to Vcc when High

Must stuff R2197 when R2180 NO STUFFed.

(IPU-RSMRST#)

NOTE: TCK from PCH is Push-Pull CMOS NOTE: TMS/TDI from PCH is Open Drain NOTE: TDO from CR is Push-Pull CMOS

JTAG Isolation due to glitch in and out of sleep

Systems with chip-down memory should add pull-downs on another page and set straps per software.

Systems with no chip-down memory should pull all 4 RAMCFG GPIOs high.

R2574 is 1K series resistor between U2100 output and PCH input to reduce the current between the two drivers..

11 24 72 24

20 41

1/20W

201

NO STUFF

20 41 50

11 40 72

1/20W

RAMCFG3:H

10K

201

RAMCFG2:H

10K

MF 201

5% 1/20W

RAMCFG1:H

10K

201

1/20W

RAMCFG0:H

10K

MF 201

5% 1/20W

20 39

20 25

201

1/20W

2.2K

MF 201

5% 1/20W

20K

MF 2015%

1/20W

100K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

100K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

NO STUFF

10K

MF 2015%

1/20W

100K

MF 2015%

1/20W

10K

MF 2015%

1/20W

MF 2015%

1/20W

10K

MF 2015%

1/20W

201

20 24

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

NO STUFF

MF 201

1/20W

MF 201

1/20W

390

MF 201

1/20W

11 40 72

OMIT_TABLE

PCH-PPT-MB-SFF-ES1

QP8D-MM915462

BGA

10K

MF 201

5% 1/20W

201

1/20W

5% MF

10K

SSM6N15AFE

SOT563

CRITICAL

5% 1/20W

201

10K

SOT563

SSM6N15AFE

CRITICAL

10K

MF 201

5% 1/20W

201

10K

1/20W

201

10K

5% MF

1/20W 201

10K

CRITICAL

74LVC1G08

SOT891

X5R-CERM

0201

16V

10%

0.1UF

SSM6N15AFE

SOT563

CRITICAL

1/20W

201

10K

SSM6N15AFE

SOT563

CRITICAL

1/20W 201

5% MF

10K

33 24

RAMCFG_SLOT

RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H

SYNC_MASTER=J13_MLB

SYNC_DATE=09/15/2011

PCH GPIO/MISC/NCTF

FW_PWR_EN_PCH

SPIROM_USE_MLB

TBT_CIO_PLUG_EVENT_ISOL

LPCPLUS_GPIO

PCH_A20GATE

XDP_FC1_TBT_CIO_PLUG_EVENT

TBT_GO2SX_BIDIR

SMC_RUNTIME_SCI_L

WOL_EN

JTAG_ISP_TCK JTAG_TBT_TCK

=PP3V3_TBT_PCH_GPIO

JTAG_TBT_TDO

=PP3V3_TBT_PCH_GPIO

JTAG_TBT_TDI

TBT_SW_RESET_R_L

=PP3V3_S0_PCH_STRAPS

JTAG_ISP_TDO

=PP3V3_S0_PCH_STRAPS

=PP3V3_TBT_PCH_GPIO

JTAG_TBT_TMS

=PP3V3_S0_PCH_STRAPS

JTAG_ISP_TMS

=PP3V3_S0_PCH_STRAPS

JTAG_ISP_TDI

XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL

TBT_SW_RESET_L

LPCPLUS_GPIO

XDP_FC0_PCH_GPIO15_MEM_VDD_SEL_1V5_L

XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH

DPMUX_UC_IRQ

FW_PME_L

TP_PCH_GPIO8

PCH_RCIN_L

PCH_PROCPWRGD

PCH_INIT3V3_L

PCH_A20GATE

=PP3V3_S0_PCH_GPIO

=PP3V3_SUS_PCH_GPIO =PP3V3_S0_PCH_GPIO

WOL_EN

ENET_LOW_PWR_PCH

=PP3V3_S5_PCH_GPIO

SMC_RUNTIME_SCI_L

FW_PME_L

PCH_RCIN_L

=PP1V8_S0_PCH_VCC_DFTERM

CPU_PROC_SEL_L

CPU_PECI

CPU_PWRGD

ODD_PWR_EN_L

XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL

SMC_WAKE_SCI_L

TBT_GO2SX_BIDIR

XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L

XDP_DC1_PCH_GPIO35_MXM_GOOD

XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK JTAG_ISP_TDO JTAG_ISP_TDI

XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH

TBT_SW_RESET_R_L

ODD_PWR_EN_L

DPMUX_UC_IRQ AUD_IPHS_SWITCH_EN_PCH

SPIROM_USE_MLB

FW_PWR_EN_PCH

=PP3V3_S0_PCH_GPIO

PM_THRMTRIP_L_R

TBT_CIO_PLUG_EVENT

PM_THRMTRIP_L

PCH_DF_TVS

PCH_PECI

=PP3V3_TBT_PCH_GPIO

SMC_WAKE_SCI_L

MLB_RAMCFG0

MLB_RAMCFG1

MLB_RAMCFG2

MLB_RAMCFG3

R2130

R2172

R2173

R2174

R2175

R2178

R2179

R2111

2 1

R2195

2 1

R2191

1 2

R2192

1 2

R2193

1 2

R2194

1 2

R2184

1 2

R2197

1 2

R2190

1 2

R2196

1 2

R2185

1 2

R2112

2 1

R2180

1 2

R2198

2 1

R2116

2 1

R2150

1 2

R2155

1 2

R2170

1 2

R2140

1 2

R2156

1 2

U1800

BC7

B40

B44

K15 C15

W12

K17

C43

K42 A43

A45

D40 A41

H17

U40

AU12

AU10

W6 M6

AA3

AA1

U10

BC9

AK10 AH12 AK12 AH10

A4 A5

BJ51

BL1 BL3 BL4

BL48 BL49 BL51 C3 C49 C51

A48

D1 D51 E1

A49 A51 BH1

BH51

BJ1 BJ3

BJ49

R2186

R2199

Q2160

R2188

Q2160

R2162

R2161

R2163

R2160

U2100

C2113

Q2162

R2164

Q2162

R2113

<SCH_NUM>

21 OF 132

20 OF 80

20 41

20 33

17 20

17 18 19 20 25 35

17 18 19

17 18 19 20 25 35

24 25

20 39

21 23

11 72

20 24

20 39

20 33

24 25

20 41 50

20 25

17 18 19 20 25 35

17 20

VCC CORE

LVDS

(7 OF 10)

DMI

DFT/SPI

CRTFDI

VCCIO

VCCCORE

VCC3_3

VCCADAC

VCCADMI_VRM

VCCAFDIPLL VCCAFDI_VRM

VCCALVDS

VCCDFTERM

VCCDMI

VCCIO

VCCSPI

VCCTX_LVDS

VSSALVDS

VSSA_DAC

VCCAPLLEXP

VCCACLK

V_PROC_IO

VCCCLKDMI

VCCRTC

DCPSUSBYP

VCCDSW3_3

VCCAPLLDMI2

DCPRTC

VCCADPLLB

VCCADPLLA

VCCDIFFCLKN

DCPSST

V5REF

V5REF_SUS

VCCAPLL_SATA3

VCCASW

VCCIO

VCCPUSB

VCCSSC

VCCSUS3_3

VCCSUSHDA

VCCVRM

DCPSUS

USB

SATA

PCI/GPIO/LPC

(8 OF 10)

HDA

CLK/MISC

CPURTC

NC NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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NOTICE OF PROPRIETARY PROPERTY:

PAGE

PAGE TITLE

SHEET

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

55mA Max, 5mA Idle

PCH output, for decoupling only

VCCACLK pin left as NC per DG

10 mA Max, 1mA Idle

NC-ed per DG

PCH output, for decoupling only

1.44 A Max, 474mA Idle

AL24 left as NC per DG

VCCAPLLDMI2 pin left as NC per DG

BGA

QP8D-MM915462

OMIT_TABLE

pwrterm2gnd

PCH-PPT-MB-SFF-ES1

BGA

QP8D-MM915462

PCH-PPT-MB-SFF-ES1

OMIT_TABLE

PLACE_NEAR=U1800.N16:2.54mm

16V

10%

0201

X5R-CERM

0.1UF

PLACE_NEAR=U1800.N16:2.54mm

16V

10%

0201

X5R-CERM

0.1UF

PLACE_NEAR=U1800.U17:2.54mm

16V

10%

0201

X5R-CERM

0.1UF

PLACE_NEAR=U1800.N16:2.54mm

6.3V

20%

0201

X5R

1UF

PLACE_NEAR=U1800.R15:2.54mm

0.1UF

X5R-CERM

16V

10%

0201

SYNC_DATE=09/15/2011

SYNC_MASTER=J13_MLB

PCH POWER

=PP3V3_SUS_PCH_VCCSUS_USB

=PP5V_S0_PCH_V5REF

=PP3V3R1V5_S0_PCH_VCCSUSHDA

PP3V3_S0_PCH_VCC3_3_CLK_F

=PP1V05_S0_PCH_VCC_CORE

=PP3V3_SUS_PCH_VCCSUS

=PP3V3_S5_PCH_VCCDSW

=PP5V_SUS_PCH_V5REFSUS

PP1V05_S0_PCH_VCCADPLLB_F

PP1V05_S0_PCH_VCCADPLLA_F

PP3V3_S0_PCH_VCCA_DAC_F

=PP1V8R1V5_S0_PCH_VCCVRM

=PP1V05_S0_PCH_VCC_DMI

=PP1V8R1V5_S0_PCH_VCCVRM

=PP3V3_S0_PCH_VCC3_3

=PP1V8_S0_PCH_VCC_DFTERM

=PP1V8R1V5_S0_PCH_VCCVRM

=PP3V3_SUS_PCH_VCC_SPI

TP_1V05_S0_PCH_VCCAPLLEXP

=PP1V05_S0_PCH_VCCIO

TP_PPVOUT_PCH_DCPSUSBYP

=PP1V05_S0_PCH_VCCDIFFCLK

=PPVRTC_G3_PCH

=PP1V05_S0_PCH_VCCASW

=PP1V05_S0_PCH_V_PROC_IO

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm VOLTAGE=3.3V

PPVOUT_G3_PCH_DCPRTC

PP1V05_S0_PCH_VCCCLKDMI_F

PPVOUT_S0_PCH_DCPSST

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm VOLTAGE=3.3V

=PP1V05_S0_PCH_VCCSSC

U1800

AB19 AC19 AF6 BK28 R40 T39 U37 V37 V39

U51

AU21

AU19

AP13 AP15

AF33 AG33

AP19

AB21 AB23

AG25 AG27 AJ21 AJ23 AJ25 AJ27 AJ29 AJ31 AK29 AK31

AC21

AK33 AM33 AM35

AC23 AE21 AE23 AF21 AF23 AG21 AG23

AJ13 AJ15 AK15 AL13

AM23 AU15 AW16

AP27 AR15 AR23 AR25 AR27 AR29 AT13 AU23 AU25 AU27 AU29 AU35 AW34

AM21

Y19

AF37 AG37 AG39 AJ37

V50

AC33 AE33

U1800

R15 U15

U17

AR33 AU31 AU33 V13

R10

N36

M37

AM17

AC51

BF40 BD40

AM2

AW31

AB27 AB29

U19 U21 V19 V21 V23 V25 Y21 Y23

Y25

Y27

AB31

Y29 Y31

AC27 AC29 AC31 AE27 AE29 AE31

R19

AP39

AC37 AE37 AE39

R12

AA13 AB15 AC13

N18 R23 R25 U23 U25

AC15 AF15 AG13 AG15 AJ17 AK21

U27 U29

N16

AC35

AM27 N27 R27 R29 R33 R35 U33 U35

V31

AC39 AE19 AF17 AW18 AW21

C2232

C2233

C2222

C2231

C2210

<SCH_NUM>

22 OF 132

21 OF 80

23 25

20 23

21 23

17 23

17 18

(9 OF 10)

VSSVSS

(10 OF 10)

VSSVSS

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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NOTICE OF PROPRIETARY PROPERTY:

PAGE

PAGE TITLE

SHEET

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

BGA

PCH-PPT-MB-SFF-ES1

QP8D-MM915462

OMIT_TABLE

BGA

QP8D-MM915462

OMIT_TABLE

PCH-PPT-MB-SFF-ES1

PCH GROUNDS

SYNC_DATE=09/15/2011

SYNC_MASTER=J13_MLB

U1800

AA7 AA9

AB25

AP25 AP29 AP31 AP33 AP35 AP37 AP41 AP43 AP45 AP48

AB33

AP50 AR6 AR8 AR17 AR19 AR21 AR31 AR35 AR37 AT7

AB35

AT9 AT11 AT39 AT41 AT43 AT45 AU17 AU37 AV2 AV4

AB37

AV48 AV50 AW7 AW9 AW11 AW13 AW23 AW25 AW27 AW29

AB48

AW36 AW39 AW41 AW43 AW45 AY10 B6 B10 B14 B18

AB50

B22 B26 B30 B34 B38 B42 B46 BA7 BA9 BA11

AC7

BA13 BA16 BA18 BA21 BA23 BA25 BA27 BA29 BA31 BA34

AC9

BA36 BA39 BA41 BA43 BA45 BB2 BB4 BB48 BB50 BC11

AC11

BC13 BC16 BC18 BC21

AC17

AA11

AC25 AC41 AC43 AC45

AE7

AE9 AE11 AE13 AE15 AE17

AA39

AE25 AE35 AE41 AE43 AE45

AF2

AF4

AF8 AF19 AF25

AA41

AF27 AF29 AF31 AF35 AF48 AF50

AG7

AG9 AG11 AG17

AA43

AG19 AG29 AG31 AG35 AG41 AG43 AG45

AH2

AJ7

AJ9

AA45

AJ11 AJ19 AJ33 AJ35 AJ39 AJ41 AJ43 AJ45

AK2

AK4

AB2

AK17 AK19 AK23 AK25 AK27 AK35 AK37 AK48 AK50

AL7

AB4

AL9 AL11 AL39 AL41 AL43 AL45 AM15 AM19 AM25 AM29

AB17

AM31 AM37

AP2 AP4 AP7 AP9 AP11 AP17 AP21 AP23

U1800

BC23 BC25 BC27 BC29 BC31 BC34 BC36 BC39 BC41 BC43 BC45 BD15 BD24

BE7

BE9 BE11 BE13 BE16 BE18 BE21 BE23 BE25 BE27 BE29 BE31 BE34 BE36 BE39 BE41 BE43 BE45

BF2

BF4 BF15 BF24 BF48 BF50

BH6 BH10 BH14 BH18 BH22 BH26 BH28 BH30 BH32 BH34 BH38 BH42 BH44 BH46 BH48 BK10 BK14 BK18 BK22 BK26 BK30 BK32 BK34 BK38 BK42 BK46

D6 D10 D14 D18 D22 D26 D30 D34 D38 D42 D46

F4 F48 F50

G9 G11 G13 G16 G18 G21 G23 G25 G27 G29 G31 G34 G36

G39 G41 G43 J7 J9 J11 J13 J16 J18 J21 J23 J25 J27 J29 J31 J34 J36 J39 J41 J45 K2 K4 K48 K50 L7 L9 L11 L13 L16 L18 L21 L23 L25 L27 L29 L31 L34 L36 L39 L41 L43 L45 N7 N9 N11 N13 N21 N23 N25 N29 N31 N34 N39 N41 N43 N45 P2 P4 P48 P50 R17 R21 R31 R37 T7 T9 T11 T13 T41 T43 T45 U31 U49 V2 V4 V7 V9 V11 V15 V17 V27 V29 V33 V35 V41 V43 V45 V48 Y15 Y17 Y33 Y35 Y37

<SCH_NUM>

23 OF 132

22 OF 80

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

8 7 6 5 4 3

NOTICE OF PROPRIETARY PROPERTY:

PAGE

PAGE TITLE

SHEET

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(PCH 1.05V CORE PWR)

PCH VCCCORE BYPASS

PCH VCCSUSHDA BYPASS

PCH VCCIO BYPASS

(PCH USB 1.05V PWR)

NEED PWR CONSTRAINT

1 mA

NEED PWR CONSTRAINT

(PCH Reference for 5V Tolerance on USB)

1 mA S0-S5

PCH V5REF_SUS Filter & Follower

PCH V5REF Filter & Follower

<1 MA

(PCH Reference for 5V Tolerance on PCI)

(PCH HD Audio 3.3V/1.5V PWR)

PCH VCC3_3 BYPASS

(PCH PCI 3.3V PWR)

PCH VCCIO BYPASS

(PCH SUSPEND USB 3.3V PWR)

PCH VCCSUS3_3 BYPASS

69 mA

68 mA

PCH VCCADPLLA Filter (PCH DPLLA PWR)

(PCH DPLLB PWR)

PCH VCCADPLLB Filter

1/16W

MF-LF

402

1/16W

MF-LF

402

PLACE_NEAR=U1800.AB27:2.54mm

6.3V

X5R-CERM1

0603

20%

22UF

PLACE_NEAR=U1800.AB27:2.54mm

0603

X5R-CERM1

6.3V

20%

22UF

PLACE_NEAR=U1800.AB27:2.54mm

6.3V

20%

0201

X5R

1UF

PLACE_NEAR=U1800.AB27:2.54mm

0201

1UF

6.3V

20% X5R

PLACE_NEAR=U1800.AB27:2.54mm

0201

6.3V

20% X5R

1UF

PLACE_NEAR=U1800.AU27:2.54mm

CERM-X5R

6.3V

20%

0402-2

10UF

PLACE_NEAR=U1800.AR29:2.54mm

1UF

X5R 0201

20%

6.3V

PLACE_NEAR=U1800.AU29:2.54mm

X5R 0201

20%

6.3V

1UF

PLACE_NEAR=U1800.AU25:2.54mm

20%

1UF

0201

X5R

6.3V

PLACE_NEAR=U1800.AR25:2.54mm

6.3V

20%

0201

X5R

1UF

PLACE_NEAR=U1800.AB21:2.54mm

10UF

20%

6.3V

CERM-X5R

0402-2

PLACE_NEAR=U1800.AB21:2.54mm

6.3V

20%

0201

X5R

1UF

PLACE_NEAR=U1800.AB21:2.54mm

6.3V

20%

0201

X5R

1UF

PLACE_NEAR=U1800.AB21:2.54mm

6.3V

20% X5R

1UF

0201

PLACE_NEAR=U1800.AJ13:2.54mm

X5R-CERM 0201

10% 16V

0.1UF

PLACE_NEAR=U1800.V31:2.54mm

0.1UF

X5R-CERM 0201

10% 16V

PLACE_NEAR=U1800.AM17:2.54mm

0.1UF

16V 0201

10% X5R-CERM

PLACE_NEAR=U1800.N27:2.54mm

0.1UF

X5R-CERM 0201

10% 16V

PLACE_NEAR=U1800.AM17:2.54mm

10%

0.1UF

X5R-CERM 0201

16V

PLACE_NEAR=U1800.AM17:2.54mm

20%

4.7UF

402

X5R

6.3V

PLACE_NEAR=U1800.R27:2.54mm

X5R-CERM

16V

10%

0201

0.1UF

PLACE_NEAR=U1800.Y19:2.54mm

20%

1UF

6.3V 0201

X5R

PLACE_NEAR=U1800.R12:2.54mm

0.1UF

X5R-CERM

16V

0201

10%

PLACE_NEAR=U1800.AM23:2.54mm

6.3V

1UF

X5R 0201

20%

PLACE_NEAR=U1800.R33:2.54mm

1UF

X5R 0201

20%

6.3V

PLACE_NEAR=U1800.AG13:2.54mm

1UF

X5R 0201

20%

6.3V

PLACE_NEAR=U1800.AC35:2.54mm

1UF

X5R 0201

20%

6.3V

PLACE_NEAR=U1800.AB15:2.54mm

1UF

X5R 0201

20%

6.3V

PLACE_NEAR=U1800.AC37:2.54mm

1UF

X5R 0201

20%

6.3V

PLACE_NEAR=U1800.U27:2.54mm

20%

0201

X5R

1UF

6.3V

PLACE_NEAR=U1800.AJ17:2.54mm

1UF

X5R 0201

20%

6.3V

PLACE_NEAR=U1800.AP39:2.54mm

0402-2

CERM-X5R

6.3V

20%

10UF

0603

10UH-0.12A-0.36OHM

PLACE_NEAR=U1800.U51:2.54mm

0.01UF

0201

10% 16V

X5R-CERM

PLACE_NEAR=U1800.U51:2.54mm

X5R-CERM

16V

0.1UF

0201

10%

PLACE_NEAR=U1800.U51:2.54mm

CERM-X5R

6.3V

20%

10UF

0402-2

201

1/20W

SOT-363

BAT54DW-X-G

1/20W

201

100

PLACE_NEAR=U1800.N36:2.54mm

X5R 402

10V

10%

1UF

BAT54DW-X-G

SOT-363

1/20W

201

PLACE_NEAR=U1800.M37:2.54mm

10V

20%

CERM

0.1UF

402

PLACE_NEAR=U1800.AF6:2.54mm

X5R-CERM

16V

0.1UF

10% 0201

PLACE_NEAR=U1800.R40:2.54mm

16V

10% 0201

X5R-CERM

0.1UF

PLACE_NEAR=U1800.AC19:2.54mm

16V

10% 0201

X5R-CERM

0.1UF

PLACE_NEAR=U1800.BK28:2.54mm

10% X5R-CERM

0201

16V

0.1UF

PLACE_NEAR=U1800.T39:2.54mm

16V

10%

0201

X5R-CERM

0.1UF

PLACE_NEAR=U1800.BF40:2.54MM

6.3V 0201

X5R

20%

1UF

PLACE_NEAR=U1800.BD40:2.54MM

0201

X5R

6.3V

20%

1UF

PLACE_NEAR=U1800.AB19:2.54mm

0201

16V

10%

0.1UF

X5R-CERM

402

MF-LF

1/16W

0603

10UH-0.12A-0.36OHM

PLACE_NEAR=U1800.V37:2.54mm

6.3V

20%

10UF

0402-1

CERM-X5R

PLACE_NEAR=U1800.V37:2.54mm

X5R

10% 402

1UF

10V

PLACE_NEAR=U1800.AW16:2.54mm

1UF

X5R 0201

20%

6.3V

10UH-0.12A-0.36OHM

0603

10UH-0.12A-0.36OHM

0603

PLACE_NEAR=U1800.BD40:2.54MM

1206-1

6.3V CERM-X5R

100UF

20%

PLACE_NEAR=U1800.BD40:2.54MM

1206-1

6.3V CERM-X5R

100UF

20%

PLACE_NEAR=U1800.BF40:2.54MM

1206-1

6.3V CERM-X5R

100UF

20%

PLACE_NEAR=U1800.BF40:2.54MM

20%

100UF

CERM-X5R

6.3V 1206-1

SYNC_MASTER=J13_MLB

SYNC_DATE=09/15/2011

PCH DECOUPLING

=PP1V05_S0_PCH

=PP3V3_S0_PCH

MIN_NECK_WIDTH=0.2 MM

PP3V3_S0_PCH_VCC3_3_CLK_F

MIN_LINE_WIDTH=0.4 MM VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

PP3V3_S0_PCH_VCC3_3_CLK_R

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.25MM

PP5V_SUS_PCH_V5REFSUS

VOLTAGE=5V MAKE_BASE=TRUE

MAKE_BASE=TRUE

PP5V_S0_PCH_V5REF

MIN_LINE_WIDTH=0.3MM VOLTAGE=5V

MIN_NECK_WIDTH=0.25MM

PP1V05_S0_PCH_VCCADPLLA_R

MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM

PP1V05_S0_PCH_VCCADPLLB_R

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

VOLTAGE=3.3V

MAKE_BASE=TRUE MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP3V3_S0_PCH_VCCA_DAC_F

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V05_S0_PCH_VCCADPLLA_F

PP1V05_S0_PCH_VCCADPLLB_F

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

MAKE_BASE=TRUE

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM

PP1V05_S0_PCH_VCCCLKDMI_F

=PP1V05_S0_PCH_VCCADPLL

=PP1V05_S0_PCH_VCC_DMI

=PP3V3_S0_PCH_VCC3_3_CLK

=PP3V3_SUS_PCH_VCC_SPI

=PP1V05_S0_PCH_VCC_DMI

=PP1V05_S0_PCH_V_PROC_IO

=PP3V3R1V5_S0_PCH_VCCSUSHDA

=PP3V3_SUS_PCH_VCCSUS_USB

=PP1V05_S0_PCH_VCCASW

=PP1V05_S0_PCH_VCCIO_SATA

=PP1V05_S0_PCH_VCCDIFFCLK

=PP5V_S0_PCH_V5REF

=PP5V_SUS_PCH_V5REFSUS

=PP3V3_S5_PCH_VCCDSW

=PP3V3_SUS_PCH =PP5V_SUS_PCH

=PP3V3_S0_PCH_VCC3_3

=PP1V05_S0_PCH_VCCIO

=PP1V05_S0_PCH_VCCSSC

=PP3V3_SUS_PCH_VCCSUS

=PP1V05_S0_PCH_VCC_CORE

=PP1V05_S0_PCH_VCCIO

=PP3V3_S0_PCH_VCC3_3

=PP1V8_S0_PCH_VCC_DFTERM

=PP3V3_S0_PCH_VCC3_3

=PP5V_S0_PCH

=PP3V3_S0_PCH_VCCADAC

R2460

1 2

R2465

1 2

C2420

C2428

C2496

C2456

C2426

C2401

C2463

C2407

C2414

C2429

C2460

C2483

C2482

C2481

C2440

C2441

C2430

C2413

C2417

C2416

C2484

C2442

C2499

C2419

C2476

C2452

C2475

C2444

C2434

C2446

C2469

C2411

L2406

1 2

C2455

C2451

C2450

R2450

1 2

D2400

R2405

C2439

D2400

R2404

C2438

C2423

C2485

C2486

C2421

C2424

C2461

C2466

C2422

R2451

1 2

L2451

1 2

C2453

C2454

C2418

L2460

1 2

L2465

1 2

C2465

C2462

C2402

C2403

<SCH_NUM>

24 OF 132

23 OF 80

21 23

21 25

17 21

21 23

20 21

21 23

IN IN

IN IN IN

OUT

IN IN

OUT OUT

OUT

BI IN

OUT

OUT OUT

OUT

IN IN IN IN

OUT

IN IN IN IN IN IN

IN IN

OUT

OUT OUT

OUT

OUT OUT

OUT

OUTOUT

OUT

IN IN

BI IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

8 7 6 5 4 3

NOTICE OF PROPRIETARY PROPERTY:

PAGE

PAGE TITLE

SHEET

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

NOTE: This is not the standard XDP pinout. Use with 921-0133 Adapter Flex to support chipset debug.

518S0847

PCH Micro2-XDP

HOOK3

- ’Output’ non-XDP signals require pulls.

CPU Micro2-XDP

support chipset debug.

NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page

Non-XDP Signals

Use with 921-0133 Adapter Flex to

OBSFN_B1

PCH SIGNALS

- ’Output’ PCH/XDP signals require pulls.

and path to non-XDP signal destination.

needs to split between route from PCH to J2550

R252x, R253x, R257x and R259x should be placed where signal path

(R2564-R2567)

OBSDATA_A0 OBSDATA_A1

XDP SIGNALS

doc id 404081.

it is functional in that state, else add BOM options.

Initially, stuffing both 33 and 0 ohms and validate whether

- Following Intel’s Debug Prot Design Guid for HR and CR v1.3

PWRGD/HOOK0

OBSDATA_B0

OBSDATA_A2

OBSDATA_B1

TMS

TDI

PCH/XDP Signal Isolation Notes:

OBSDATA_B2

OBSDATA_D1

OBSDATA_D2 OBSDATA_D3

VCC_OBS_CD

DBR#/HOOK7

OBSDATA_D0

ITPCLK/HOOK4 ITPCLK#/HOOK5

XDP_PRESENT#

RESET#/HOOK6

OBSFN_B0

OBSDATA_A2

VCC_OBS_AB

HOOK2

PWRGD/HOOK0

OBSDATA_B2

OBSFN_B1

VCC_OBS_CD

OBSDATA_B3

OBSDATA_B1

OBSDATA_A1

OBSFN_A1

OBSDATA_A3

OBSDATA_B0

- For isolated GPIOs:

VCC_OBS_AB

HOOK2 HOOK3

SDA SCL

TCK1

OBSFN_C0

OBSDATA_C0

OBSFN_C1

TRSTn

TDO

OBSDATA_A3

OBSFN_B0

OBSFN_A1

OBSFN_A0

OBSFN_D0 OBSFN_D1

OBSDATA_C1

OBSDATA_C2 OBSDATA_C3

OBSDATA_C2

OBSFN_D0

ITPCLK/HOOK4

TCK0

SDA

HOOK1

TDI TMS

TDO TRSTn

DBR#/HOOK7

ITPCLK#/HOOK5

OBSFN_D1

OBSFN_C1

OBSDATA_C3

OBSDATA_C0

OBSDATA_D2

OBSDATA_D0 OBSDATA_D1

1K series R on PCH Support Page

XDP_PRESENT#

TCK0

OBSDATA_D3

TCK1

SCL

OBSDATA_B3

NOTE: This is not the standard XDP pinout.

NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page

OBSDATA_C1

OBSFN_C0

OBSDATA_A0

OBSFN_A0

518S0847

(R2520-R2537)

HOOK1

PCH SIGNALS

(R2560-R2563)

10 72

11 25

11 72

10 24 72

10 72

17 24

10 72

17 24

10 72

24 42

11 24 25 72

16V

10%

XDP

X7R-CERM

0.1UF

0402

16V

10%

XDP

X7R-CERM

0.1UF

0402

18 24 39

18 39 66

11 24 72

11 24 25 72

10 72

11 24 72

17 72

11 24 72

1/16W

402

MF-LF

NO STUFF

PLACE_NEAR=R1841.1:2.54mm

XDP

1/20W

5% 201MF

PLACE_NEAR=R1840.1:2.54mm

1/20W

5% 201MF

XDP

PLACE_NEAR=U1000.G3:2.54mm

201

1/20W

5% MF

XDP

PLACE_NEAR=J2550.52:2.54mm

1/20W

5% 201MF

XDP

PLACE_NEAR=U1800.K5:2.54mm

1/20W

XDP

5% 201MF

PLACE_NEAR=U1800.H7:2.54mm

1/20W

5% 201MF

XDP

PLACE_NEAR=U1800.J3:2.54mm

1/20W

5% 201MF

XDP

PLACE_NEAR=J2500.52:2.54mm

1/20W

5% 201MF

XDP

PLACE_NEAR=U1000.K61:2.54mm

1/20W

5% 201MF

XDP

PLACE_NEAR=U1000.H59:2.54mm

1/20W

5% 201MF

XDP

PLACE_NEAR=U1000.J58:2.54mm

1/20W

5% 201MF

XDP

PLACE_NEAR=U1000.H63:2.54mm

1/20W

5% 201MF

XDP

1/20W

5% 201MF

330

XDP

PLACE_NEAR=U1000.B57:2.54mm

1/20W

5% 201MF

XDP

PLACE_NEAR=U4900.P17:2.54mm

1/20W

201MF

XDP

PLACE_NEAR=U1000.C60:2.54mm

1/20W

5% 201MF

XDP

XDP_CPU:BPM

1/20W

5% 201

11 72

1/20W

5% 201MF

XDP_CPU:BPM

201

1/20W

5% MF

XDP_CPU:BPM

201

1/20W

5% MF

XDP_CPU:BPM

1/20W

5% 201MF

XDP_CPU:CFG

1/20W

5% 201

XDP_CPU:CFG

5% 201MF

XDP_CPU:CFG

1/20W

201

1/20W

5% MF

XDP_CPU:CFG

10 72

1/20W

5% 201MF

XDP

1/20W

5% 201MF

XDP

1/20W

5% 201MF

XDP

1/20W

5% 201MF

XDP

1/20W

5% 201MF

XDP

201

1/20W

5% MF

XDP

1/20W

5% 201MF

XDP

1/20W

5% 201MF

XDP

1/20W

5% 201MF

XDP

1/20W

5% 201MF

XDP

1/20W

5% 201MF

XDP

20 24

10 24 72

17 24

20 24

19 24

PLACE_NEAR=J2550.39:2.54mm

XDP

1/20W

5% 201MF

PLACE_NEAR=U4900.P17:2.54mm

1/20W

5% 201MF

XDP

39 66

18 24 39

DF40RC-60DP-0.4V

XDP_CONN

M-ST-SM1

CRITICAL

M-ST-SM1

XDP_CONN

DF40RC-60DP-0.4V

CRITICAL

1/20W

5% 201MF

XDP

17 25

20 25

1/20W

5% 201

1/20W

5% 201MF

1/20W

5% 201MF

1/20W

5% 201MF

1/20W

5% 201MF

20 25

1/20W

5% 201MF

19 24

20 24

0402

X7R-CERM

XDP

16V

10%

0.1UF

20 24

1/20W

5% 201MF

XDP

1/20W

5% 201MF

XDP

1/20W

5% 201MF

XDP

1/20W

5% 201MF

XDP

1/20W

5% 201MF

XDP

1/20W

201MF

XDP

20 24

1/20W

MF02015%

201

1/20W

5% MF

10 72

17 24

1/20W

5% 201MF

MF 2015%

1/20W

19 24

19 36 66

19 24

20 20 24

1/20W

201 MF

1/20W

201 MF

20 24

MF 2015%

1/20W

0402

10%

0.1UF

X7R-CERM

XDP

16V

PPDDR:1V5

1/20W

201MF

20 24 60

11 72

10 72

24 42

11 24 72

10 72

11 20 72

10 72

11 72

SYNC_MASTER=J30_MLB

CPU & PCH XDP

SYNC_DATE=07/14/2011

XDP_BPM_L<5> XDP_BPM_L<6> XDP_BPM_L<7>

CPU_CFG<12>

CPU_CFG<15>

CPU_CFG<14>

CPU_CFG<13>

XDP_OBSDATA_B<3>

XDP_OBSDATA_B<2>

XDP_CPU_CLK100M_P

CPU_RESET_L

XDP_CPU_TRST_L

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L

XDP_DC3_PCH_GPIO19_SATARDRVR_EN

XDP_CPURST_L XDP_DBRESET_L

XDP_CPU_TDO

TBT_CIO_PLUG_EVENT_ISOL

XDP_CPU_TMS

XDP_CPU_TDI

XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L

XDP_BPM_L<4>

XDP_PCH_TDO

XDP_PCH_TDI

XDP_DA0_USB_EXTA_OC_L

XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH

XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L

XDP_CPU_PRDY_L

XDP_DD1_JTAG_ISP_TCK

XDP_DA3_USB_EXTD_OC_L

XDP_DD0_DP_GPU_TBT_SEL

XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L

XDP_DD1_JTAG_ISP_TCK

XDPPCH_PLTRST_L XDP_DBRESET_L

XDP_PCH_TDO

XDP_PCH_TMS

=SMBUS_XDP_SDA

=PP3V3_S0_XDP

XDP_FC0_MEM_VDD_SEL_1V5_L

PM_PWRBTN_L

XDP_DC0_ISOLATE_CPU_MEM_L

CPU_CFG<6> CPU_CFG<7>

XDP_DC2_DP_AUXCH_ISOL

XDP_PCH_TCK

XDP_PCH_TMS

XDP_CPU_TCK

XDP_CPU_TRST_L

XDP_CPU_TMS

XDP_CPU_TDI

XDP_CPU_TDO

=PPVCCIO_S0_XDP

XDP_DB2_AP_PWR_EN

XDP_PCH_TCK

=SMBUS_XDP_SCL

TP_XDPPCH_HOOK2 TP_XDPPCH_HOOK3

XDP_DB1_USB_EXTD_OC_EHCI_L

XDP_PCH_TDI

XDP_DC1_MXM_GOOD

CPU_CFG<16>

ITPXDP_CLK100M_P

ITPXDP_CLK100M_N

XDP_CPU_PREQ_L

XDP_BPM_L<0>

CPU_CFG<10> CPU_CFG<11>

CPU_CFG<2>

=PP1V05_SUS_PCH_JTAG

XDP_BPM_L<1>

XDP_BPM_L<2>

PM_PCH_SYS_PWROK

XDP_DD3_ENET_LOW_PWR

XDP_DD0_DP_GPU_TBT_SEL

=SMBUS_XDP_SDA

XDP_DD2_AUD_IPHS_SWITCH_EN XDP_DD3_ENET_LOW_PWR

XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH

XDP_DC0_ISOLATE_CPU_MEM_L

XDP_DC3_SATARDRVR_EN

XDP_PCH_PWRBTN_L

XDP_DB0_USB_EXTB_OC_EHCI_L

XDP_DB3_SDCONN_STATE_CHANGE

XDP_PCH_S5_PWRGD

XDP_CPU_CLK100M_N

ISOLATE_CPU_MEM_L

DP_AUXCH_ISOL

USB_EXTB_OC_L

CPU_CFG<4>

AP_PWR_EN

XDP_DC2_DP_AUXCH_ISOL

XDP_DA1_USB_EXTB_OC_L

XDP_DB0_USB_EXTB_OC_EHCI_L

XDP_DC1_MXM_GOOD

XDP_DC3_SATARDRVR_EN

XDP_DB2_AP_PWR_EN

XDP_DA2_USB_EXTC_OC_L

XDP_DD2_AUD_IPHS_SWITCH_EN

XDP_FC1

XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK

XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH

XDP_DA1_USB_EXTB_OC_L

XDP_DA3_USB_EXTD_OC_L

XDP_DA2_USB_EXTC_OC_L

XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL

XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK

XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

XDP_DB2_PCH_GPIO10_AP_PWR_EN

XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L

CPU_PWRGD

XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L

XDP_DC1_PCH_GPIO35_MXM_GOOD

XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L

XDP_FC1_TBT_CIO_PLUG_EVENT

XDP_FC0_PCH_GPIO15_MEM_VDD_SEL_1V5_L

XDP_CPU_PWRGD

CPU_CFG<5>

XDP_DB1_USB_EXTD_OC_EHCI_L

ALL_SYS_PWRGD

XDP_DB3_SDCONN_STATE_CHANGE

XDP_DA0_USB_EXTA_OC_L

XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL XDP_DC3_PCH_GPIO19_SATARDRVR_EN

XDP_OBSDATA_B<0>

USB_EXTA_OC_L

CPU_CFG<9>

CPU_CFG<1>

MEM_VDD_SEL_1V5_L

TP_XDP_PCH_HOOK4 TP_XDP_PCH_HOOK5

PM_PWRBTN_L

TP_XDP_PCH_OBSFN_A<0> TP_XDP_PCH_OBSFN_A<1>

TP_XDP_PCH_OBSFN_B<0> TP_XDP_PCH_OBSFN_B<1>

TP_XDP_PCH_OBSFN_D<0> TP_XDP_PCH_OBSFN_D<1>

XDP_FC1

XDP_FC0_MEM_VDD_SEL_1V5_L

TP_XDP_PCH_TRST_L

XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L

XDP_FC0_PCH_GPIO15_MEM_VDD_SEL_1V5_L

XDP_FC1_TBT_CIO_PLUG_EVENT

XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL

XDP_OBSDATA_B<1>

XDP_BPM_L<3>

XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L

CPU_CFG<3>

CPU_CFG<0>

SATARDRVR_EN

SDCONN_STATE_CHANGE

CPU_CFG<8>

=PPVCCIO_S0_XDP

CPU_CFG<17>

ENET_LOW_PWR_PCH

AUD_IPHS_SWITCH_EN_PCH

JTAG_ISP_TCK

CPU_CFG<0>

XDP_VR_READY

XDP_CPU_CFG<0>

=SMBUS_XDP_SCL

=PP3V3_S5_XDP

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L

XDP_CPU_PWRBTN_L

XDP_CPU_TCK

C2501

C2500

C2580

C2581

R2540

R2515

1 2

R2516

1 2

R2505

1 2

R2550

2 1

R2551

2 1

R2552

2 1

R2556

2 1

R2510

2 1

R2511

2 1

R2512

2 1

R2513

2 1

R2514

2 1

R2504

1 2

R2501

1 2

R2502

1 2

R2500

1 2

R2560

1 2

R2561

1 2

R2562

1 2

R2563

1 2

R2566

1 2

R2565

1 2

R2564

1 2

R2567

1 2

R2524

1 2

R2525

1 2

R2526

1 2

R2527

1 2

R2530

1 2

R2532

1 2

R2533

1 2

R2534

1 2

R2535

1 2

R2536

1 2

R2537

1 2

R2584

1 2

R2585

1 2

J2500

1112 1314 1516 1718 19

2122 2324 2526 2728 29

3132 3334 3536 3738 39

4142 4344 4546 4748 49

5152 5354 5556 5758 59

6364

78 9

J2550

1112 1314 1516 1718 19

2122 2324 2526 2728 29

3132 3334 3536 3738 39

4142 4344 4546 4748 49

5152 5354 5556 5758 59

6364

78 9

R2521

1 2

R2597

1 2

R2596

1 2

R2572

1 2

R2570

1 2

R2576

1 2

R2577

1 2

R2528

1 2

R2529

1 2

R2520

1 2

R2522

1 2

R2523

1 2

R2531

1 2

R2575

1 2

R2573

1 2

R2591

1 2

R2590

1 2

R2580

1 2

R2581

1 2

R2574

1 2

R2595

1 2

<SCH_NUM>

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