Apple A1297 Schematic

TABLE_TABLEOFCONTENTS_ITEM

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

3

B

7

ECNREV

BRANCH

DRAWING NUMBER

REVISION

SIZE

D

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

DRAWING TITLE

THE POSESSOR AGREES TO THE FOLLOWING:

Apple Inc.

SHEET

R

DATE

D

A

C

THE INFORMATION CONTAINED HEREIN IS THE

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

C

3456

D

B

8 7 6 5 4 2 1

12

APPD

CK

DESCRIPTION OF REVISION

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_TABLEOFCONTENTS_ITEM

DRAWING

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

Schematic / PCB #’s

SCHEM,ANGEL_ISLAND,MLB,K17

Rev.A 02/23/10

ALIASES RESOLVED

1 OF 103

1 OF 132

2009-05-19

03/26/2009

48

45

K20A_MLB

Front Flex Support

03/26/2009

47

44

K20A_MLB

PROJECT SPECIFIC CONNS

06/09/2009

46

43

K17_WFERRY

External USB Connectors

03/26/2009

45

42

K20A_MLB

SATA Connectors

07/08/2009

43

41

K18_MLB

FireWire Ports

03/26/2009

42

40

K20A_MLB

FireWire Port Power

03/26/2009

41

39

K20A_MLB

FireWire LLC/PHY (FW643)

06/09/2009

40

38

K17_WFERRY

Ethernet Connector

10/28/2009

39

37

K18_MLB

Ethernet PHY (Caesar II/IV)

10/09/2009

37

36

K18_MLB

USB HUB 2

10/07/2009

36

35

K18_MLB

USB HUB 1

06/09/2009

35

34

K17_WFERRY

ExpressCard Connector

06/19/2009

34

33

K18_MLB

X16/ALS/CAMERA CONNECTOR

06/09/2009

33

32

K17_WFERRY

FSB/DDR3/FRAMEBUF Vref Margining

10/14/2009

32

31

K18_MLB

CPU Memory S3 Support

06/09/2009

31

30

K17_WFERRY

DDR3 SO-DIMM Connector B

06/19/2009

30

29

K18_MLB

DDR3 Byte/Bit Swaps

05/13/2009

29

28

K17_REF

DDR3 SO-DIMM Connector A

06/17/2009

28

27

K17_REF

Chipset Support

05/19/2009

27

26

K17_REF

Clock (CK505)

06/22/2009

26

25

K18_MLB

eXtended Debug Port (XDP)

06/09/2009

25

24

K17_WFERRY

CPU/PCH GFX Decoupling

06/09/2009

24

23

K17_WFERRY

PCH Non-GFX Decoupling

03/26/2009

23

22

T22_MLB

PCH Grounds

10/02/2009

22

21

K18_MLB

PCH Power

11/13/2009

21

20

K18_MLB

PCH MISC

10/07/2009

20

19

K18_MLB

PCH PCI/FlashCache/USB

06/09/2009

19

18

K17_WFERRY

PCH DMI/FDI/Graphics

08/24/2009

18

17

K17_REF

PCH SATA/PCIE/CLK/LPC/SPI

06/24/2009

17

16

K17_REF

CPU Non-GFX Decoupling (2 of 2)

06/09/2009

16

15

K17_WFERRY

CPU Non-GFX Decoupling (1 of 2)

04/29/2009

15

14

K17_REF

CPU Grounds

06/09/2009

14

13

K17_WFERRY

CPU Power (2 of 2)

06/09/2009

13

12

K17_WFERRY

CPU Power (1 of 2)

04/29/2009

12

11

K17_REF

CPU DDR3 Interfaces

10/14/2009

11

10

K18_MLB

CPU Clock/Misc/JTAG

06/09/2009

10

9

K17_WFERRY

CPU DMI/PEG/FDI/RSVD

06/17/2009

9

8

K17_REF

Signal Aliases

(MASTER)

8

7

(MASTER)

Power Aliases

06/17/2009

7

6

K17_REF

Functional / ICT Test

06/09/2009

5

K17_WFERRY

BOM Configuration

03/26/2009

4

K20A_MLB

Revision History

03/26/2009

3

K20A_MLB

Revision History

03/26/2009

2

K20A_MLB

Revision History

90

K20A_MLB

98

03/26/2009

LCD Backlight Support

89

K17_VEMURI

97

12/16/2009

LCD Backlight Driver (MC34845)

88

K17_REF

96

06/24/2009

Graphics MUX (GMUX)

87

K17_REF

95

06/17/2009

1.05V GPU / 1V8 FB Power Supply

86

K20A_MLB

94

03/26/2009

DisplayPort Connector

85

K17_REF

93

06/17/2009

Muxed Graphics Support

84

K20A_MLB

90

03/26/2009

LVDS Display Connector

83

K17_WFERRY

89

06/09/2009

GPU (GT216) CORE SUPPLY

82

K18_MLB

88

06/29/2009

NV GT216 VIDEO INTERFACES

81

K18_MLB

87

07/01/2009

GT216 GPIOS & STRAPS

80

K18_MLB

86

06/29/2009

NV GT216 GPIO/MIO/MISC

79

GT216

85

03/26/2009

GDDR3 Frame Buffer B (Top)

78

GT216

84

03/26/2009

GDDR3 Frame Buffer A (Top)

77

K18_MLB

82

06/29/2009

NV GT216 FRAME BUFFER I/F

76

GT216

81

03/26/2009

NV GT216 CORE/FB POWER

75

K18_MLB

80

06/29/2009

NV GT216 PCI-E

74

K17_WFERRY

79

06/09/2009

Power Control

73

K17_WFERRY

78

06/09/2009

Power FETs

72

K17_WFERRY

77

06/09/2009

Misc Power Supplies

71

T22_MLB

76

03/26/2009

CPUVTT (1.05V) Power Supply

70

T22_MLB

75

03/26/2009

GFX IMVP VCore Regulator

69

K18_POWER

74

06/29/2009

CPU IMVP VCore Regulator

68

K17_REF

73

06/24/2009

1.5V DDR3 Supply

67

K20A_MLB

72

03/26/2009

5V / 3.3V Power Supply

66

K17_REF

70

04/29/2009

PBus Supply & Battery Charger

65

K17_REF

69

04/29/2009

DC-In & Battery Connectors

64

K17_REF

68

05/30/2009

AUDIO: JACK TRANSLATORS

63

K17_LENGO

67

11/24/2009

AUDIO: JACKS

62

K17_REF

66

05/30/2009

AUDIO:SPEAKER AMP

61

K17_REF

65

05/30/2009

AUDIO: HEADPHONE OUT

60

K17_REF

63

05/30/2009

AUDIO: LINE IN

59

K17_REF

62

05/30/2009

AUDIO:CODEC

58

K17_WFERRY

61

06/09/2009

SPI ROM

57

K17_CHENGD

60

07/08/2009

DEBUG SENSORS AND ADC

56

K20A_MLB

59

03/26/2009

Sudden Motion Sensor (SMS)

55

K17_WFERRY

58

06/09/2009

WELLSPRING 2

54

K17_WFERRY

57

06/09/2009

WELLSPRING 1

53

K20A_MLB

56

03/26/2009

Fan Connectors

52

K17_CHENGD

55

07/08/2009

Thermal Sensors

51

K17_CHENGD

54

06/04/2009

Current Sensing

50

K17_REF

53

06/17/2009

Current & Voltage Sensing

49

K17_WFERRY

52

05/20/2009

K17 SMBus Connections

48

T22_MLB

51

03/30/2009

LPC+SPI Debug Connector

47

K17_REF

50

06/17/2009

SMC Support

05/20/2009

K17_WFERRY

132

103

T57 Card Connector

06/17/2009

K17_REF

122

102

Current Sensing

06/17/2009

K17_REF

121

101

Ibex Peak-M Power Aliases

06/09/2009

K17_WFERRY

109

100

PCB Rule Definitions

06/17/2009

K17_REF

108

99

Project Specific Constraints

06/09/2009

K17_WFERRY

107

98

GPU (GT216) CONSTRAINTS

06/09/2009

K17_WFERRY

106

97

SMC Constraints

06/09/2009

K17_WFERRY

105

96

FireWire Constraints

06/09/2009

K17_WFERRY

104

95

Ethernet Constraints

06/17/2009

K17_REF

103

94

PCH Constraints 2

06/09/2009

K17_WFERRY

102

93

PCH Constraints 1

06/09/2009

K17_WFERRY

101

92

Memory Constraints

SCHEM,TREASURE_ISLAND,MLB,K17

Page

(.csa)

Date

SyncContents

06/09/2009

K17_WFERRY

100

91

CPU Constraints

Sync

Date

(.csa)

Page Contents

PCBF,ANGEL_ISLAND,MLB,K17

820-2849

1

CRITICAL

PCB

04/01/2008

1

K20_MLB

Table of Contents

SCHEM,ANGEL_ISLAND,MLB,K17

051-8503 CRITICAL

SCH

1

LAST_MODIFIED=Tue Feb 23 21:52:40 2010

TITLE=MLB

ABBREV=DRAWING

(.csa)

Sync

Date

ContentsPage

46

K17_WFERRY

49

06/09/2009

SMC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Bluetooth

PWR

IBEX PEAK-MPCH

Conns

Audio

POWER SUPPLY

PG 28

J3400

GB

Amps

U6200

J6950

U6100

USB

DC/BATT

SPI

TEMP SENSOR

FanADC

B,0 BSB

CONN

Boot ROM

Amp

U4900

U2600

PG 25

DDR3-1067/1333MHZ

2 UDIMMs

J2900

DIMM

PG 28,30

U8000

INTEL CPU

ARRANDALE

2.X GHZ

NV GT216

PRAPHICS

PG 9

PG 73

RTC

LPC

CLK

DMIFDI

PG 17

GPIO

PG 20 PG 18 PG 18

0 1

CTRL

BUFFER

SATA

PG 17

RGB OUT

PG 20

PG 17

PG 56

PG 17

SMC

Prt

PG 44

Ser

J5100

U4900

PG 51

FAN CONN AND CONTROL

J5650,5660

POWER SENSE

PG 44

PG 63

LPC Conn

Port80,serial

PG 46

8 9

13121011

J3401 J3401 J3401

USB

PG 33 PG 52

J5713

TRACKPAD/

KEYBOARD

(UP TO 14 DEVICES)

PG 19

J4600,J4610,4720

EXTERNAL

Connectors

SMB

PG 41

SMB

PG 17

PG 47

DIMM’s

2

HDA

TMDS OUT

PG 18

PG 17

Codec

PG 57

SpeakerLine In

PG 60PG 59

Amp

Line Out

U6610,6620,6630,6640,6650

U6500

HEADPHONE

Amp

J6780,6781,6782,6700,6750

PG 61

PCI

PCI-E

PG 19

3 4 5 6 7

JTAG

(UP TO 16 LINES)

PG 17

PCI-E

PG 17 PG 17

PEG

E-NET

J3500

EXPRESSCARD

CONN

PG 34

U3900

J4000

BCM5764M

PG 35

E-NET

Conn

PG 36

PG 37

U4100

PG 39

AirPort

FW643

Mini PCI-E

J4310

Conn

Misc

XDP CONN

E-NET

IR

INTEL

U1800

PG 17

PG 33

SPI

CAMERA

PG 33

U2700

CLOCK CK505

P8 26

1.05V/3GHZ.

J4500

Conn

HD

P8 40

SATA

P8 40

ODD

Conn

SATA

J4501

HDMI OUT

DVI OUT

DP OUT

LVDS OUT

CONN

J9000

DISPLAY PORT

PG 84

LVDS CONN

PG 71

J9400

PG 85

XP25-5

GMUX

U9600

SYNC_DATE=03/26/2009

Revision History

SYNC_MASTER=K20A_MLB

2 OF 132 2 OF 103

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

ADAPTER

P1V1GPU_EN

1.8V(R/H)

POK2

POK1

SMC_DCIN_ISENSE

K17 POWER SYSTEM ARCHITECTURE

A

PBUS SUPPLY/

VIN

R7020

VIN

VOUT

8A FUSE

DDRREG_EN

(PAGE 66)

PP5V_S0_FET

P1V5DDR_EN

Q7860

P5VS0_EN

PP3V3_S5

VOUT2

3.3V

EN2

(PAGE 65)

PP5V_S3

P1V8FB_PGOOD

S5 S3

PP5V_S3_DDRREG

DDRREG_PGOOD

ON

VOUT

SLG5AP020

ISL8009B

U7760

(PAGE 70)

PP1V2_GMUX_FET

P1V2GMUX_EN

PP1V2_ENET

Q7850

PM_ALL_GPU_PGOOD

U7980

EN

VIN

P1V2ENET_EN

VOUT

ISL8009B

U7710

(PAGE 70)

PM_SLP_S3_L&&WOL_EN||SMC_ADAPTER_EN

VIN

ISL8014

U7720

(PAGE 70)

PP3V3_FW_FET

Q4291

Q7830

P1V8S0_PGOOD

FW_PWR_EN

P1V8_S0_EN

PP3V3_S0_FET

A

PPVCORE_S0_GFX

V

P3V3S0_EN

EN

PP1V8_S0

P3V3S3_EN

P1V5_EXP_S0_EN

PP3V3_ENET

PP1V5_EXP_S0

Q7922

Q7810

PGOOD

VOUT

Q3810

P3V3S5_PGOOD

P3V3GPU_EN

PP3V3_S0_GPU

OUT

EN

VIN

PP3V3_S3

Q7870

PPVOUT_S0_LCDBKLT

U7300

TPS51116

U7801

PGOOD

PP1V5_S0

VOUT2

PP3V3_S5

EN1

VOUT1

(L/H)

5V

VIN

TPS51980

BKLT_PLT_RST_L

P3V3S5_EN

P5VS3_PGOOD

LCD_BKLT_EN

BKLT_EN

APP001

PGOOD1 PGOOD2

&&

VIN

GFX_DPRSLPVR

VR_ON

PFWBOOST

VOUT

GFXIMVP_ISENSE

TPS51981

SMC_GFX_VSENSE

V

R7540

DPRSLPVR

(PAGE 68)

U7500

Q4260

A

GFXIMVP_PGOOD

PGOOD

GFX_VR_EN

(PAGE 70)

SMC_ADAPTER_EN&&PM_SLP_S3_L

VOUT

PM_SLP_S5_L

Q9806

DDRREG_EN

P3V3S3_EN

SLP_S3#(P12)

PM_SLP_S4_L

P5VS3_EN

SLP_S4#(H7)

(PAGE 87)

PM_SLP_S3_L

U9700

ENA

P5VS3_EN

U7201

LTC1872

P1V1GPU_PGOOD

ISL6236

U9500

(PAGE 85)

(R/H)

PP1V8_S0GPU

PPVTT_S0_DDR_LDO

A

SMC_DDR_ISENSE

R7350

R5388

A

CPUIMVP_VR_ON

(PAGE 67)

SMC_CPU_DDR_VSENSE

U5440

V

PP1V5_S3

U7400

PPDDR_S3_REG

SMC_GPU_1V8_ISENSE

0.75V

DDRVTT_EN

1.103V(L/H)

VOUT1

PP1V1_S0GPU

VIN

VOUT2

1.5V

VR_ON

ISL9522

VOUT

VOUT1

EN1

P1V8FB_EN

PPVBAT_G3H_CHGR_R

VIN

R5413

U7790

VIN

1.05V AUX

VOUT

VIN

R7050

SMC_CPU_VSENSE

PPVCORE_S0_CPU

CPUIMVP_GOOD

CPU VCORE

VIN

GPUVCORE_EN

SMC_CPU_HI_ISENSE

GPUVCORE_PGOOD

SMC_CPU_FSB_ISENSE

PPCPUVTT_S0

R7640

U7600

TPS51513

CPUVTTS0_EN

CPUVTTS0_PGOOD

(PAGE 69)

A

1.05V

PP5V_S0_CPUVTTS0

(PAGE 45)

VIN

VOUT

EN

PGOOD

SMC_GPU_ISENSE

ISL6263C

GPU VCORE

PP5V_S3_GPUVCORE

VDD

F7041

SMC_GPU_VSENSE

PPVCORE_GPU

V

U5410

PGOOD

(PAGE 81)

A

PP3V42_G3H

PBUSVSENS_EN

P3V3S0_EN

DELAY

CPUVTTS0_EN

P5VS0_EN

RC

DELAY

P1V2GMUX_EN

P1V5DDR_EN

RC

P1V8S0_EN

PM_SLP_S3_L_R

R7978

(PAGE 17~22)

CPU

PWRGD(P12)

RSMRST_IN(P13)

PM_SLP_S5_L PM_SLP_S4_L

U1800

IBEX_PEAK_M

SLP_S5#(E4)

RC

DELAY

RC

P3V3S5_EN

SMC_PM_G2_EN

(PAGE 44)

(PAGE 86)

XP25-5

PL32A

CHGR_BGATE

(6 TO 8.4V)

PPVBATT_G3H_CONN

SMC_PBUS_VSENSE

(PAGE 64)

BATTERY CHARGER

V

PPBUS_G3H

SMC_BATT_ISENSE

ISL6259HRTZ

IN

VOUT

PM_ALL_GPU_PGOOD

TRST = 200mS

(PAGE 72)

ISL88042IRTEZ

U7971

ADJ1

PM_SLP_S3_L

SLP_S5_L(P95)

IMVP_VR_ON(P16)

99ms DLY

RSMRST_OUT(P15)

(P64)

PM_MEM_PWRGD

CPU_PWRGD

ACPRESENT

RSMRST#

IBEX PEAK M

SMC AVREF SUPPLY

U1800

(PAGE 17~22)

SM_DRAMPWROK

VCCCPUPWRGD

(PAGE 9~14)

RSMRST_PWRGD

SMC_ONOFF_L

SLP_S4_L(P94)

SLP_S3_L(P93)

S0PGOOD_PWROK

PP1V5_S0

PP1V05_S0

PP3V3_S0_PWRCTL

P1V8S0_PGOOD

P5VS3_PGOOD

ALL_SYS_PWRGD

SMC

Q7055

RC

PM_PCH_PWRGD

PS_PWRGD

PROCPWRGD

PLTRST#

SYS_RERST#

DRAMPWROK

PM_RSMRST_L

SMC_ADAPTER_EN

PLT_RERST_L

PWR_BUTTON(P90)

PWRBTN#

IMVP_VR_ON

PM_SYSRST_L

PM_PWRBTN_L

U1000

PM_PWRBTN_L

RES*

P17(BTN_OUT)

RESET*

SYSRST(PA2)

SMC_RESET_L

U2850

VR5020

VOUT

SMC_TPAD_RST_L

SMC_ONOFF_L

(PAGE 44)

U4900

U5001

PP3V3_S5_AVREF_SMC

3.425V G3HOT

ENABLE

(PAGE 45)

VIN

NCP303LSN

SMC PWRGD

U5000

U6990

(PAGE 63)

R6905

F7040

F6905 6A FUSE

DCIN(16.5V)

PPDCIN_G3H_OR_PBUS_R

VLDOIN

J6900

AC

U8900

U9600

PB16B

P1V1GPU_EN

GPUVCORE_ENEG_RAIL3_EN

Q5315

SMC_RESET_L

EG_RAIL4_EN

EG_RAIL1_EN EG_RAIL2_EN

SMC

LT3470A

PB18A

PB17B

EN2

P1V8_S0GPU_EN

P3V3GPU_EN

GMUX

PB17A

P60

U4900

DELAY

RST*

VCC

ADJ2

RC

DELAY

VR_ON

PGOOD

A

U7000

2S4P

J6950

PP3V3_S0

PPVBAT_G3H_CHGR_REG

SMC_CPU_ISENSE

SYNC_MASTER=K20A_MLB

Revision History

SYNC_DATE=03/26/2009

3 OF 132 3 OF 103

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

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SIZE

D

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PAGE TITLE

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2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

02/23/10

csa. 5 Added K17_PVT BOM group

MLB_TI_IMVP65

Rev. A:

(For changes prior to Rev. A, refer to earlier schematics)

csa. 121 Changed ARB_ONLY sense Rs to XWs

csa. 74 Updated Symbol for U7400; new VPN is TPS51983

SYNC_DATE=03/26/2009

Revision History

SYNC_MASTER=K20A_MLB

4 OF 132 4 OF 103

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

DRAWING NUMBER

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D

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PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

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A

B

C

345678

D

B

8 7 5 4 2 1

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

BOM Variants

Bar Code Labels / EEEE #’s

K17 BOM GROUPS

Alternate Parts

Module Parts

[EEEE_DCMT]

LBL,P/N LABEL,PCB,28MM X 6 MM

EEEE_DCMT

CRITICAL

1

826-4393

[EEEE_DCMV]

EEEE_DCMV

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL826-4393

1

PCBA,2.66GHZ,512HYN_VRAM,K17

K17_COMMON,CPU_2_66GHZ,FB_512_HYNIX,EEEE_DCMQ,K17_PVT

639-0970

BCM5764M,DCI,GMUX_VSYNC,CPUPOC_IMAX_40_50,PCH_NAND_3V3,CPUMEM_S0,EXT_HP_AMP,VFRQ_SLPS3,SMC_DEBUG_YES,DPMUX_EN_PLD,FB1V35,USBHUB_2061

K17_COMMON1

341S2616

IC,TP PSOC,K17,K18

U5701

1

CRITICAL

TPAD_PROG

U4800

CRITICAL

1

341S2384

IR,ENCORE II, CY7C63833-LFXC

IC,EFI ROM,K17

BOOTROM_PROG

1

U6100

CRITICAL341T0244

IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP

CRITICAL

BOOTROM_BLANK

1

U6100

335S0610

IC,SMC,K17

SMC_PROG

CRITICAL

1

U4900

341T0229

337S3849

1

CRITICAL

U1800

IBEX (HM55),SLGZS,PRQ,B3

343S0493

1

CRITICAL

U3900

BCM5764M

IC,ASIC,BCM5764M,ENET CONTROLLER,8x8,64 QFN

338S0753

1

CRITICAL

IC,FW643-E,1394B PHY/OHCI LINK/PCI-E,12

U4100

1

J3100

516S0805 CRITICAL

CONN,204P,SODIMM,SOCKET,DDR3,RAM,NON/SC

CPU_2_66GHZ

1

U1000

CRITICAL337S3848

ARD,SLBPE,PRQ,2.66,35W,C2,4M,BGA

CPU_2_4GHZ

CRITICAL

U1000

1

337S3846

ARD,SLBNA,PRQ,2.40,35W,C2,3M,BGA

CRITICAL

U8000

1

337S3839

IC,GPU,NV GT216 LP++,969BGA,40NM,A03

IC,SGRAM,GDDR3,32MX32,1GHZ,D-DIE,136 FBGA

U8400,U8450,U8500,U8550

VRAM_512_SAMSUNG

4

333S0533 CRITICAL

SMC_OSC_YES

U5010

197S0350 CRITICAL

1

OSC,XTAL,32.768KHZ,9-3.6V,12P SOIC,HF

U8400,U8450,U8500,U8550

VRAM_512_HYNIX

333S0535

4

CRITICAL

IC,SDRAM,GDDR3,32MX32,900MHZ,TIVA,HF

CPU_2_53GHZ

CRITICAL

1

U1000

337S3847

ARD,SLBPF,PRQ,2.53,35W,C2,3M,BGA

085-1425

K17_DEVEL_ENG

K17 MLB DEVELOPMENT

ALL

Murata alt to Samsung

138S0603 138S0602

152S0896 152S0518

ALL

MAG LAYERS ALT TO CYNTEC

155S0457 155S0329

ALL

MAG LAYERS ALT TO MURATA

516S0805516S0806

ALL

FOXCONN ALT TO MOLEX

138S0602138S0612

Taiyo Yuden alt to Samsung

ALL

353S2603

ALL

353S2805

Fairchild 8 in alt to 6 in wafer

127S0060

ALL

127S0111

Rohm alt to Kemet

NEC/TOKIN alt to Sanyo

128S0218128S0299

ALL

152S0915 152S0796

ALL

MAG LAYERS ALT TO CYNTEC

Delta alt to TDK Magnetics

ALL

157S0058 157S0055

U9600

GMUX_PROG

1

341S2568 CRITICAL

IC,CPLD,LATTICE,132CSBGA,K17MLB

338S0563

IC,SMC,HS8/2117,9MMX9MM,TLP

SMC_BLANK

CRITICAL

1

U4900

ALL

337S3839337S3808

GT216 A02 alt to A03 part

ALL

376S0887 376S0749

Fairchild alt to Vishay

U3990

1

CRITICAL341S2731

IC,1MBIT,SPI FLASH K17/K18

336S0025

GMUX_5K_BLANK

U9600

1

CRITICAL

IC,XP2-5,HF,CPLD,BLANK

EEEE_DCMR

[EEEE_DCMR]

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

1

826-4393

XDP,XDP_CONN,XDP_CPU_BPM,XDP_NORMAL,XDP_PCH

CALPELLA_XDP

VRAM4,VRAM_512_HYNIX

FB_512_HYNIX

VRAM4,VRAM_512_SAMSUNG

FB_512_SAMSUNG

EEEE_DCMQ

[EEEE_DCMQ]

826-4393 CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

1

BMON_PROD,VREFMRGN_NOT,XDP,XDP_NORMAL,XDP_CPU_BPM

K17_PVT

GMUX_PROG,BOOTROM_PROG,SMC_PROG,TPAD_PROG

K17_PROGPARTS

ARB_ONLY,CALPELLA_XDP,DEBUG_ADC,LPCPLUS,VREFMRGN,GMUX_JTAG_CONN,EFI_DEBUG,BMON_ENG,SMC_OSC_YES

K17_DEVEL_ENG

GPUVID_0P90V,BKLT_PWR_PBUS,DP_ESD,DP_CA_DET_EG_PLD,SMC_EXCARD_NOT,GPU_SS_INT,RDRV_8515_A2,GMUXPLL_3V3,HUB1_2NONREM,HUB2_2NONREM,RAIL_MON

K17_COMMON2

ALTERNATE,COMMON,K17_COMMON1,K17_COMMON2,K17_PROGPARTS

K17_COMMON

PCBA,2.53GHZ,512HYN_VRAM,K17

K17_COMMON,CPU_2_53GHZ,FB_512_HYNIX,EEEE_DCMR,K17_PVT

639-0971

PCBA,2.66GHZ,512SAM_VRAM,K17

K17_COMMON,CPU_2_66GHZ,FB_512_SAMSUNG,EEEE_DCMT,K17_PVT

639-0972

PCBA,2.53GHZ,512SAM_VRAM,K17

K17_COMMON,CPU_2_53GHZ,FB_512_SAMSUNG,EEEE_DCMV,K17_PVT

639-0973

SYNC_MASTER=K17_WFERRY

SYNC_DATE=06/09/2009

BOM Configuration

5 OF 132 5 OF 103

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

J3500 (EXPRESS CARD CONN)

J6782 (RIGHT & SUB SPEAKER)

J5660 (RIGHT FAN CONN)

J3401, J3402 (AIRPORT/BT/CAMERA CONN)

per Fan

4 TPs

J5650 (LEFT FAN CONN)

J4800 (FRONT CABLE CONN)

4 TPs

5 TPs

FUNC_TEST

4 TPs

NO_TEST

NC NO_TESTs

2 TP needed

J6900 (DC POWER CONN)

J6950 (MAIN BATT CONN)

J6995 (BAT LED CONN)

5 TPs

2 TPs

5 TPs

J5800 (IPD FLEX CONN)

CPU NO_TESTs

NO_TEST

2 TPs

J5815 (KBD BACKLIGHT CONN)

4 TPs

3 TPs

FUNC_TEST

ICT Test Points

NO_TEST

6 TPs

NC NO_TESTs

3 TPs

USB PORTS

per Fan

J5713 (KEY BOARD CONN)

NO_TEST

NC NO_TESTs

J9000 (LVDS CONN)

J4501 (SATA HDD CONN)

FUNC_TEST

J4500 (SATA ODD CONN)

J6780 (MIC CONN)

J6781 (LEFT SPEAKER)

3 TPs

2 TPs

POWER RAILS

FUNC_TEST

NC NO_TESTs

Functional Test Points

I1000 I1001 I1002

I1003

I1004

I1005

I1006

I1007

I1008

I1009

I1010 I1011 I1012

I1013

I1014

I1015 I1016 I1017 I1018 I1019 I1020

I1021

I1022

I1024

I1025

I1026

I1027

I1028

I1029

I1031

I1032

I1033

I1034

I1035

I1038 I1039 I1040

I1042 I1043 I1044

I1046 I1047 I1048

I1050

I1051

I1052

I1053

I1054

I1055

I1056

I1057

I1058

I1059

I1060

I1061

I1062

I1063

I1064

I1065

I1066

I1067 I1068 I1069

I1070

I1071

I1072

I1073

I1074

I1075 I1076 I1077

I1078

I1079

I1080

I1081

I1082 I1083 I1084

I1085 I1086 I1087

I1088

I1089

I1090 I1091

I1092 I1093 I1094

I1095 I1096

I1097

I1098

I1099 I1100 I1101

I1102

I1103

I1104 I1105

I1106

I1107

I1108 I1109 I1110 I1111 I1112 I1113 I1114 I1115

I1116

I1117

I1118 I1119 I1120

I1121

I1122

I1123 I1124 I1125

I1126

I1127

I1128 I1129 I1130

I1131 I1132

I1134

I1135

I1136

I1137

I1140

I1141

I1142

I1143

I1145 I1146

I1148

I1149

I1150

I1151 I1152

I1156

I1160 I1161

I1273

I1288

I1296

I1297

I1436 I1437

I1438 I1439

I1440

I1441 I1442

I1443

I1444 I1445

I1446

I1447 I1448

I1449

I1450

I1451

I557

I558

I559

I600

I602 I603

I604

I605

I606

I607

I610

I611

I612

I614

I618

I625

I626

I627

I636

I637

I638

I639

I640

I709

I714

I720 I722

I723

I724

I725 I726 I727

I728

I729

I730

I731

I732

I733

I734

I735 I736 I737

I738

I739

I740 I741 I742 I743 I744 I751 I752

I756

I761 I762 I763 I764 I765

I766

I767

I768

I769

I770

I771

I772

I774

I985

I986

I987

I988

I989 I990

I991

I992

I993

I994

I995 I996 I997 I998

Functional / ICT Test

SYNC_DATE=06/17/2009

SYNC_MASTER=K17_REF

NC_FW643_TDI NC_FW643_TDI

MAKE_BASE=TRUE

TRUE

NC_FW643_AVREG

MAKE_BASE=TRUE

TRUE

USB_LT3_N

TRUE

WS_KBD20

WS_KBD19

TRUE

PP5V_S3_RTUSB_C_F

TRUE

NC_PCH_LVDS_VBG

NC_HDA_SDIN2 NC_HDA_SDIN3

TRUE

NC_HDA_SDIN3

MAKE_BASE=TRUE

TP_PCI_AD<31..0> TP_PCI_C_BE_L<3..0>

NC_PCI_GNT2_L

NC_PCI_PME_L

PP3V3_S3_BT_F

TRUE

PCH_VSS_NCTF<1>

TRUE

LVDS_CONN_A_DATA_N<1>

TRUE

PCIE_CLK100M_EXCARD_CONN_P

PLT_RESET_SWITCH_L

TRUE

SMBUS_PCH_CLK

PP3V3_S0

TRUE

PPVCORE_S0_CPU

TRUE

CONN_USB2_BT_P

SMBUS_SMC_A_S3_SCL

TRUE

INT_MIC_SHIELD

PP1V05_S0GPU

TRUE

PP1V8_S0GPU_ISNS

TRUE

PPVCORE_GPU

TRUE

PP1V8_S0GPU_ISNS_R

TRUE

PP3V3_S5_AVREF_SMC

TRUE

PP5V_S3_ALSCAMERA_F

TRUE

PP1V5_S0_EXCARD_SWITCH

TRUE

PP3V3_S3

TRUE

EXCARD_CLKREQ_CONN_L

TRUE

FAN_LT_PWM

TRUE

MAKE_BASE=TRUE

NC_SMC_P92TP_SMC_P92

TRUE

LVDS_CONN_A_CLK_F_N

TRUE

LVDS_DDC_DATA

TRUE

PPVOUT_S0_LCDBKLT

TRUE

INT_MIC_N

TRUE

INT_MIC_P

TRUE MAKE_BASE=TRUE

NC_PCI_GNT1_L

NC_LVDS_EG_BKL_PWM

TP_LVDS_EG_B_CLK_P

TP_LVDS_EG_B_CLK_N

TP_LVDS_IG_B_CLKN

NC_PCH_NC2

NC_PCH_NC1

NC_PCI_GNT2_L

MAKE_BASE=TRUE

TRUE

SMC_ONOFF_L

WS_KBD17

TRUE

EXCARD_CPUSB_L

TRUE

PPVP_FW

TRUE

NC_USB_EXTDP

MAKE_BASE=TRUE

PCH_VSS_NCTF<9>

TRUE

PCIE_EXCARD_D2R_N

SATA_HDD_R2D_P

TRUE

NC_PCIE_PE5_D2RP

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_PCIE_PE5_R2D_CN

TRUE

MAKE_BASE=TRUE

NC_PCIE_PE5_R2D_CP

TRUE

NC_PCIE_PE6_R2D_CN

MAKE_BASE=TRUE

TRUE

NC_PCIE_PE6_D2RP

MAKE_BASE=TRUE

NC_PCIE_PE7_D2RP

MAKE_BASE=TRUE

TRUE

NC_PCIE_PE6_D2RN

MAKE_BASE=TRUE

TRUE

NC_PCIE_PE7_R2D_CP

MAKE_BASE=TRUE

NC_PCIE_PE7_R2D_CN

MAKE_BASE=TRUE

TRUE

NC_PCIE_PE8_R2D_CP

MAKE_BASE=TRUE

TRUE

NC_PCIE_PE8_R2D_CN

MAKE_BASE=TRUE

TRUE

NC_PCIE_PE8_D2RP

MAKE_BASE=TRUE

TRUE

NC_PCIE_PE8_D2RN

MAKE_BASE=TRUE

NC_PCIE_PE5_R2D_CP

NC_PCIE_PE5_D2RN

NC_PCIE_PE5_R2D_CN

NC_PCIE_PE5_D2RP

NC_PCIE_PE6_R2D_CN

NC_PCIE_PE6_D2RP

NC_PCIE_PE7_D2RN NC_PCIE_PE7_D2RP

NC_PCIE_PE6_D2RN

NC_PCIE_PE7_R2D_CP

NC_PCIE_PE7_R2D_CN

NC_PCIE_PE8_R2D_CP

NC_PCIE_PE8_R2D_CN

NC_PCIE_PE8_D2RP

NC_PCIE_PE8_D2RN

TRUE

PP5V_S0

TRUE

USB_CAMERA_CONN_P

TRUE

PP5V_S3_RTUSB_B_F

PP5V_S0_HDD_FLT

TRUE

ISSP_SDATA_P1_0

NC_CRT_IG_DDC_CLK

TRUE MAKE_BASE=TRUE

NC_CRT_IG_BLUE

TRUE

LVDS_CONN_A_DATA_P<0>

TP_CPU_RSVD_NCTF<8..5>

NC_CRT_IG_BLUE

NC_CRT_IG_RED

NC_CRT_IG_HSYNC NC_CRT_IG_VSYNC

NC_LVDS_IG_CTRL_DATA

TRUE

WS_KBD9 WS_KBD10

TRUE

MAKE_BASE=TRUE

TRUE

NC_CRT_IG_HSYNC

MAKE_BASE=TRUE

TRUE

NC_CRT_IG_VSYNC

TRUE

WS_KBD12

WS_KBD22

TRUE

PP3V3_S3

TRUE

WS_KBD21

USB2_LT1_P

TRUE

SATA_HDD_R2D_N

TRUE

LED_RETURN_3

TRUE

LVDS_CONN_B_DATA_P<1>

TRUE

MAKE_BASE=TRUE

NC_TP_CPU_RSVD<27..26>

TRUE

MAKE_BASE=TRUE

NC_TP_CPU_RSVD<58..45>

PP3V42_G3H

TRUE

PP18V5_S3

TRUE

PPDCIN_G3H

PPCPUVTT_S0

TRUE

WS_KBD14

USB_LT2_N

TRUE

PM_CLKRUN_L

TRUE

LPC_AD<0..3>

TRUE

LVDS_CONN_B_DATA_N<0>

PP5V_SW_ODD

TRUE

USB_CAMERA_CONN_N

LPC_CLK33M_LPCPLUS

TRUE

PCIE_AP_D2R_N

PP5V_S3_RTUSB_A_F

TRUE TRUE

USB2_LT1_N

TRUE

LPCPLUS_RESET_L

TRUE

SPI_ALT_MISO

TRUE

WS_KBD2

WS_KBD1

TRUE

LED_RETURN_5

TRUE

WS_KBD8

TRUE

WS_KBD3

TRUE

WS_KBD13

TRUE

WS_KBD11

TRUE

LVDS_CONN_A_DATA_P<2>

TRUE

LVDS_CONN_A_CLK_F_P

TRUE

LVDS_CONN_B_DATA_P<0>

LVDS_CONN_B_DATA_N<1>

TRUE TRUE

LVDS_CONN_B_DATA_P<2>

TRUE

LVDS_CONN_B_CLK_F_P

TRUE

LVDS_CONN_B_CLK_F_N LED_RETURN_1

TRUE

LED_RETURN_2

TRUE

LED_RETURN_4

TRUE

SMC_ODD_DETECT

TRUE

SATA_ODD_D2R_UF_P SATA_ODD_D2R_UF_N

TRUE

PP5V_S3_IR_R

TRUE

WS_KBD23

TRUE

WS_KBD_ONOFF_L

TRUE

WS_KBD7

SMC_RESET_L

TRUE

SPI_ALT_MOSI

TP_CPU_RSVD<2..1>

TRUE

MAKE_BASE=TRUE

NC_TP_CPU_RSVD<2..1>

TP_CPU_RSVD<24..15>

TP_CPU_RSVD<27..26>

TP_CPU_RSVD<43..32>

TP_CPU_RSVD<58..45>

TP_CPU_RSVD<65..62>

TRUE

MAKE_BASE=TRUE

NC_TP_CPU_RSVD_NCTF<8..5>

TRUE

WS_LEFT_OPTION_KBD

LVDS_CONN_B_DATA_N<2>

TRUE

LVDS_CONN_A_DATA_N<2>

PP3V3_SW_LCD

TRUE

LVDS_CONN_BKL_SYNC

TRUE

PM_SYSRST_L

SMC_TCK

TRUE

LPC_PWRDWN_L

TRUE

LPC_SERIRQ

TRUE

SPI_ALT_CS_L

TRUE

SPI_ALT_CLK

TRUE

SPIROM_USE_MLB

TRUE

SMC_TX_L

TRUE

SMC_MD1

SMC_TRST_L

TRUE

SMC_TDO

TRUE

SMC_TMS

TRUE

LPC_FRAME_L

TRUE

PPVTTDDR_S3 PP1V8_GPUIFPX

TRUE

USB_LT3_P

TRUE

WS_KBD18

TRUE

SMC_RX_L

LPCPLUS_GPIO

TRUE TRUE

ISSP_SCLK_P1_1

NC_LVDS_IG_CTRL_CLK

TRUE

SYS_LED_ANODE

TRUE

KBDLED_ANODE

TRUE

SMC_KDBLED_PRESENT_L

TRUE

PCIE_CLK100M_AP_CONN_P

TRUE

NC_SMC_FAN_2_TACH

TRUE

NC_SMC_FAN_2_CTL

TRUE

NC_FW2_TPBN

NC_FW2_TPBP

TRUE

NC_FW2_TPBIAS

TRUE

NC_FW2_TPAP

TRUE TRUE

NC_FW2_TPAN

TRUE

NC_FW0_TPBN

NC_FW0_TPBP

TRUE

NC_FW0_TPAP NC_ESTARLDO_EN

TRUE

NC_ALS_GAIN

TRUE

NC_DP_IG_C_HPD

TRUE MAKE_BASE=TRUE

NC_DP_IG_C_CTRL_DATA

TRUE MAKE_BASE=TRUE

NC_DP_IG_C_CTRL_CLK

MAKE_BASE=TRUE

TRUE

NC_DP_IG_C_CTRL_CLK

NC_DP_IG_C_MLP<3..0>

MAKE_BASE=TRUE

TRUE

NC_DP_IG_C_MLN<3..0>

TRUE MAKE_BASE=TRUE

NC_DP_IG_C_AUXP

TRUE MAKE_BASE=TRUE

NC_DP_IG_C_AUXN

TRUE MAKE_BASE=TRUE

NC_DP_IG_C_AUXN

NC_DP_IG_D_HPD

TRUE MAKE_BASE=TRUE

NC_DP_IG_D_HPD

NC_DP_IG_D_CTRL_DATA

TRUE MAKE_BASE=TRUE

NC_DP_IG_D_CTRL_CLK

TRUE MAKE_BASE=TRUE

NC_DP_IG_D_MLP<3..0>

TRUE MAKE_BASE=TRUE

NC_DP_IG_D_MLN<3..0>TP_DP_IG_D_MLN<3..0>

MAKE_BASE=TRUE

TRUE

NC_DP_IG_D_AUXPNC_DP_IG_D_AUXP

NC_SDVO_TVCLKINN

MAKE_BASE=TRUE

TRUE

NC_DP_IG_D_AUXN

NC_SDVO_TVCLKINP

MAKE_BASE=TRUE

TRUE

NC_SDVO_TVCLKINP

TRUE MAKE_BASE=TRUE

NC_SDVO_INTNNC_SDVO_INTN

NC_SDVO_STALLP

TRUE MAKE_BASE=TRUE

NC_SDVO_INTP

TRUE

MAKE_BASE=TRUE

NC_PCH_SSTNC_PCH_SST

TRUE

MAKE_BASE=TRUE

NC_PCH_NC1

TRUE

MAKE_BASE=TRUE

NC_PCH_NC5

MAKE_BASE=TRUE

TRUE

NC_PCH_TP19

TRUE

MAKE_BASE=TRUE

NC_PCH_NC3

TRUE

MAKE_BASE=TRUE

NC_PCH_NC2

TRUE

MAKE_BASE=TRUE

NC_PCH_NC4

MAKE_BASE=TRUE

TRUE

NC_PCH_TP14

MAKE_BASE=TRUE

TRUE

NC_PCH_TP15

MAKE_BASE=TRUE

TRUE

NC_PCH_TP16

MAKE_BASE=TRUE

TRUE

NC_PCH_TP17

MAKE_BASE=TRUE

TRUE

NC_PCH_TP18

MAKE_BASE=TRUE

TRUE

NC_PCH_TP10

MAKE_BASE=TRUE

TRUE

NC_PCH_TP9

MAKE_BASE=TRUE

TRUE

NC_PCH_TP12

MAKE_BASE=TRUE

TRUE

NC_PCH_TP11

MAKE_BASE=TRUE

TRUE

NC_PCH_TP13

MAKE_BASE=TRUE

TRUE

NC_PCH_TP8

NC_USB_6N

NC_USB_7N NC_USB_7P

NC_HDA_SDIN1

TRUE MAKE_BASE=TRUE

NC_HDA_SDIN2

NC_PCI_GNT3_L

NC_PCI_GNT0_L

TRUE MAKE_BASE=TRUE

NC_PCI_GNT0_L

NC_PCI_GNT1_L

NC_PCI_PAR

MAKE_BASE=TRUE

TRUE

NC_PCI_PAR

NC_PCI_PME_L

MAKE_BASE=TRUE

TRUE

NC_PCI_RESET_L

MAKE_BASE=TRUE

TRUE

NC_PCI_CLK33M_OUT3NC_PCI_CLK33M_OUT3

TP_NV_DQS<1..0>

MAKE_BASE=TRUE

TRUE

NC_NV_DQ<15..0>TP_NV_DQ<15..0>

TP_NV_CE_L<3..0>

TRUE

NC_NV_ALE

MAKE_BASE=TRUE

NC_NV_ALE

NC_NV_CLE

TRUE MAKE_BASE=TRUE

NC_NV_CLE NC_NV_RB_L

NC_PCIE_CLK100M_PE4N

TRUE

NC_NV_WE_CK_L<1..0>

MAKE_BASE=TRUE

TP_NV_WE_CK_L<1..0>

TRUE

NC_NV_WR_RE_L<1..0>

MAKE_BASE=TRUE

TP_NV_WR_RE_L<1..0>

NC_PCIE_CLK100M_PE4P NC_PCIE_CLK100M_PE5N

TRUE

NC_PCIE_CLK100M_PE6P

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE6P

NC_PCIE_CLK100M_PE6N

NC_PCIE_CLK100M_PE5P

TRUE

NC_PCIE_CLK100M_PE7N

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE7N NC_PCIE_CLK100M_PE7P

NC_SATA_C_D2RP

NC_PSOC_P1_3 NC_SATA_C_D2RN

NC_SATA_C_R2D_CP

NC_SATA_C_R2D_CN

NC_SATA_D_R2D_CN

NC_SATA_D_D2RP

NC_SATA_D_D2RN

TRUE

MAKE_BASE=TRUE

NC_SATA_SSD2_R2D_CP

TRUE

MAKE_BASE=TRUE

NC_SATA_SSD2_R2D_CNNC_SATA_SSD2_R2D_CN

MAKE_BASE=TRUE

TRUE

NC_SATA_SSD2_D2RPNC_SATA_SSD2_D2RP

MAKE_BASE=TRUE

TRUE

NC_PCH_TP1

NC_PCH_TP2

MAKE_BASE=TRUE

TRUE

NC_PCH_TP6

TRUE

MAKE_BASE=TRUE

NC_PCH_TP7

TRUE

MAKE_BASE=TRUE

NC_PCH_TP5

TRUE

MAKE_BASE=TRUE

NC_PCH_TP4

TRUE

MAKE_BASE=TRUE

PP3V3_S5

TRUE

NC_PCH_TP10

MAKE_BASE=TRUE

TRUE

NC_USB_6N

MAKE_BASE=TRUE

TRUE

NC_USB_MINIP

NC_USB_EXTDP

NC_USB_EXTDN

TRUE MAKE_BASE=TRUE

NC_PCI_AD<31..0>

MAKE_BASE=TRUE

TRUE

NC_LVDS_IG_CTRL_DATA

NC_CRT_IG_GREEN

TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE

TRUE

NC_TP_CPU_RSVD<24..15>

NC_TP_CPU_RSVD<43..32>

MAKE_BASE=TRUE

TRUE

TRUE MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE7P

NC_SDVO_STALLN

NC_PCH_TP17

NC_PCH_TP14

NC_PCH_TP12

NC_PCH_TP2

NC_PCH_TP9

NC_PCH_TP15

NC_FW643_AVREG

TRUE MAKE_BASE=TRUE

NC_NV_CE_L<3..0>

MAKE_BASE=TRUE

TRUE

NC_NV_DQS<1..0>

NC_PCH_NC3 NC_PCH_NC4 NC_PCH_NC5 NC_PCH_TP19 NC_PCH_TP18

NC_PCH_TP16

NC_PCH_TP13

NC_PCH_TP11

NC_PCH_TP8

NC_PCH_TP3

NC_DP_IG_C_CTRL_DATA

NC_DP_IG_C_AUXP

TP_DP_IG_C_MLN<3..0>

TP_DP_IG_C_MLP<3..0>

NC_DP_IG_C_HPD

NC_SMC_FAN_3_CTL

TRUE

NC_SMC_FAN_3_TACH

TRUE

MAKE_BASE=TRUE

NC_SATA_D_R2D_CP

TRUE

MAKE_BASE=TRUE

NC_SATA_D_D2RP

PCH_VSS_NCTF<2>

TRUE TRUE

PCH_VSS_NCTF<5>

TRUE

PCH_VSS_NCTF<7>

PCH_VSS_NCTF<11>

TRUE

PCH_VSS_NCTF<12>

TRUE

PCH_VSS_NCTF<15>

TRUE

NC_PCH_TP1

NC_NV_RB_L

TRUE MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE4N NC_PCIE_CLK100M_PE4P

MAKE_BASE=TRUE

TRUE TRUE

NC_PCIE_CLK100M_PE5N

MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE5P NC_PCIE_CLK100M_PE6N

MAKE_BASE=TRUE

TRUE

NC_PSOC_P1_3

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

NC_SATA_C_D2RN

MAKE_BASE=TRUE

TRUE

NC_SATA_C_D2RP

TRUE

NC_SATA_C_R2D_CN

MAKE_BASE=TRUE

TRUE

NC_SATA_C_R2D_CP

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_SATA_D_D2RN

TRUE

MAKE_BASE=TRUE

NC_SATA_D_R2D_CN

NC_SATA_SSD2_D2RN

MAKE_BASE=TRUE

TRUE

NC_SATA_SSD2_D2RN

NC_SATA_D_R2D_CP

TRUE

LVDS_CONN_A_DATA_P<1>

TRUE

LVDS_CONN_A_DATA_N<0>

NC_PCIE_PE7_D2RN

TRUE

MAKE_BASE=TRUE

NC_PCIE_PE6_R2D_CP

TRUE

NC_PCIE_PE6_R2D_CP

MAKE_BASE=TRUE

NC_USB_6P

NC_USB_MINIP

NC_USB_MININ

NC_SATA_SSD2_R2D_CP

TRUE

SPKRAMP_LFE_OUT_P

TRUE

SPKRAMP_LFE_OUT_N

TRUE

SPKRAMP_FR_OUT_P

TRUE

SPKRAMP_FR_OUT_N SPKRAMP_BR_OUT_P

TRUE TRUE

SPKRAMP_BR_OUT_N

TRUE

SPKRAMP_BL_OUT_P SPKRAMP_BL_OUT_N

TRUE

SATA_ODD_R2D_N

LED_RETURN_6

TRUE

SATA_HDD_D2R_UF_P

TRUE

SATA_HDD_D2R_UF_N

PP1V8_S0

TRUE

PM_SLP_S3_L

TRUE

NC_USB_EXTDN

MAKE_BASE=TRUE

TRUE

NC_USB_7N

TRUE

WS_LEFT_SHIFT_KBD

NC_TP_CPU_RSVD<65..62>

MAKE_BASE=TRUE

TRUE

USB_LT2_P

TRUE

WS_KBD15_CAP

TRUE

SMC_NMI

MAKE_BASE=TRUE

NC_LVDS_IG_CTRL_CLK

TRUE

NC_PCI_GNT3_L

MAKE_BASE=TRUE

TRUE

TRUE MAKE_BASE=TRUE

NC_PCI_RESET_L

TRUE

PP3V3_S0

TRUE

PP3V3_WLAN

TRUE

AP_RESET_CONN_L

TRUE

SMC_LID_R

TRUE

IR_RX_OUT

TRUE

PP5V_S3

TRUE

PP3V42_G3H

TRUE

PPBUS_CPU_IMVP_ISNS

TRUE

PPBUS_G3H

PP5V_S0

TRUE

AP_CLKREQ_Q_L

TRUE

SMBUS_PCH_DATA

TRUE TRUE

PP3V3_S0_EXCARD_SWITCH

USB2_EXCARD_CONN_N

TRUE TRUE

USB2_EXCARD_CONN_P

TRUE

EXCARD_CPPE_L

PCIE_EXCARD_D2R_P

TRUE

PCIE_EXCARD_R2D_P

TRUE

PCIE_EXCARD_R2D_N

TRUE

PCIE_CLK100M_EXCARD_CONN_N

TRUE

PP3V3_S3

TPAD_GND_F

TRUE TRUE

Z2_CS_L

TRUE

Z2_DEBUG3

TRUE

Z2_MISO

TRUE

Z2_BOOT_CFG1

TRUE

Z2_BOOST_EN

Z2_CLKIN

TRUE

Z2_KEY_ACT_L

TRUE

Z2_RESET

TRUE

PICKB_L

TRUE

PSOC_F_CS_L

PSOC_MISO

TRUE

PSOC_MOSI

TRUE

PSOC_SCLK

TRUE

SMBUS_SMC_A_S3_SCL

TRUE TRUE

SMBUS_SMC_A_S3_SDA

TRUE

ADAPTER_SENSE PP18V5_DCIN_FUSE

TRUE

PPVBAT_G3H_CONN

TRUE

SMBUS_SMC_BSA_SCL

TRUE

SMBUS_SMC_BSA_SDA SMC_BS_ALRT_L

TRUE

PP3V42_G3H

TRUE

SMBUS_SMC_BSA_SCL

TRUE

SMBUS_SMC_BSA_SDA

TRUE

SMC_BIL_BUTTON_L

TRUE

CONN_USB2_BT_N

SMBUS_SMC_A_S3_SDA

TRUE

PP1V0_FW

TRUE

NC_CRT_IG_RED

TRUE MAKE_BASE=TRUE

TRUE

NC_CRT_IG_DDC_CLK

MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE

NC_CRT_IG_DDC_DATANC_CRT_IG_DDC_DATA

NC_CRT_IG_GREEN

TRUE

SMC_TDI

TRUE

WS_KBD4

WS_KBD16_NUM

TRUE

PP3V42_G3H_LIDSWITCH_R

TRUE

LCD_BKLT_PWM

TRUE

NC_PCIE_PE5_D2RN

MAKE_BASE=TRUE

TRUE

SATA_ODD_R2D_P

NC_PCH_TP6

NC_PCH_TP7

NC_PCH_TP5 NC_PCH_TP4

NC_PCH_TP3

TRUE

MAKE_BASE=TRUE

PCH_VSS_NCTF<17>

TRUE

PCH_VSS_NCTF<19>

TRUE TRUE

PCH_VSS_NCTF<19>

TRUE

PCH_VSS_NCTF<21> PCH_VSS_NCTF<25>

TRUE TRUE

PCH_VSS_NCTF<27>

TRUE

PCH_VSS_NCTF<29>

MAKE_BASE=TRUE

TRUE

NC_USB_6P

FAN_RT_PWM

TRUE

FAN_LT_TACH

FAN_RT_TACH

TRUE

SPKRAMP_FL_OUT_N

MAKE_BASE=TRUE

NC_SDVO_TVCLKINN

TRUE

NC_DP_IG_D_AUXN

TP_DP_IG_D_MLP<3..0>

NC_DP_IG_D_CTRL_CLK NC_DP_IG_D_CTRL_DATA

TRUE MAKE_BASE=TRUE

NC_HDA_SDIN1

TRUE

NC_PCI_C_BE_L<3..0>

MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE

NC_PCH_LVDS_VBG

PP18V5_S3

TRUE

WS_KBD5 WS_KBD6

TRUE

SYS_LED_ANODE_R

TRUE

LVDS_DDC_CLK

TRUE

PP3V3_S0GPU

TRUE

MAKE_BASE=TRUE

NC_GPU_MIOA_DE

TP_GPU_MIOA_D<9..0>

NC_SDVO_INTP

NC_GPU_BUFRST_L TP_GPU_GSTATE<0> TP_GPU_GSTATE<1>

TP_GPU_MIOA_DE

TP_LVDS_IG_B_CLKP TP_LVDS_IG_BKL_PWM NC_LVDS_IG_BKL_PWM

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

NC_LVDS_IG_B_CLKP

NC_LVDS_IG_B_CLKN

TRUE MAKE_BASE=TRUE

NC_LVDS_EG_BKL_PWM

TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE

TRUE

NC_LVDS_EG_B_CLKP

TRUE MAKE_BASE=TRUE

NC_LVDS_EG_B_CLKN

TRUE

NC_GPU_MIOA_D<9..0>

MAKE_BASE=TRUE

TRUE

NC_GPU_GSTATE<1>

MAKE_BASE=TRUE

TRUE

NC_GPU_GSTATE<0>

MAKE_BASE=TRUE

TRUE

NC_GPU_BUFRST_L

MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE

NC_SDVO_STALLP

NC_SDVO_STALLN

TRUE MAKE_BASE=TRUE

PP3V3_S3_EXCARD_SWITCH

TRUE

WS_CONTROL_KBD

PCIE_WAKE_L

TRUE

PCIE_CLK100M_AP_CONN_N

TRUE

PCIE_AP_R2D_P

TRUE

PCIE_AP_D2R_P

TRUE

PCIE_AP_R2D_N

TRUE

SPKRAMP_FL_OUT_P

PCIE_WAKE_L

TRUE

PP1V2_S0

MAKE_BASE=TRUE

TRUE

NC_USB_7P

TRUE

NC_USB_MININ

MAKE_BASE=TRUE

NC_USB_WMP

TRUE

MAKE_BASE=TRUE

NC_USB_WMP

TRUE

MAKE_BASE=TRUE

NC_USB_WMNNC_USB_WMN

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

7 OF 132 6 OF 103

6

39

6

39

6

39

44 99

54

44

6

18

6

17

6

17

6

17

6

19

6

19

33

20 94

84 85 98

34 99

34

17 25 26 28 30 32 34 42 48 49 64 94

6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52 53 55 59 63 64 69 70 71 72 73 74 81

84 85 86 88 99

101

7

12 15 50 69

33 99

6

33 46 49 55 97

63

7

51 75 77 80 82

7 8

51 76 77 78 79

7

50 76 83

7

51 87

46 47

33

34

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

34

53

46 47

84 98

84 85

57 84 89

63 99

6

19

6

81 82

8

18 93

6

20

6

20

6

19

46 47 54

54

34

7

40 41

6

20 94

17 34 94

42 93

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6 7 8

23 42

48 53 55 69

70 71 73 87

102

33 99

43

42

54

6

18

6

18

84 85 98

6

18

6

18

6

18

6

18

6

18

54

6

18

6

18

54

6 7

17 20 31

32 33 34 35

36 49 50 51

54 55 56 72

74 88

102 103

54

43 99

42 93

84 89

84 85 98

6 7

17 21 23 43 45 46 47 48 49 50 51 54 65 66 74

6

55

7

65 66

7

10 12 13 15 25 26 40 71 74

101

54

43 99

18 46 48

17 46 48 88 94

84 85 98

42 57

33 99

27 48 94

17 33 94

43

43 99

27 48 88 94

48

54

84 89

54

84 85 98

84 98

84 85 98

84 98

84 89

42 46

42 99

45

54

46 47 48 66

48

9

54

84 85 98

84

8

84

18 27 46

46 47 48

18 46 48

17 46 48

48

20 48 58

43 46 47 48

46 48

46 47 48

17 46 48 88 94

7

32 68

7

73 82

44 99

54

43 46 47 48

20 48

54

6

18

45 47

55

33 99

46 47

39 41

39 41 96

46 47

6

18

6

18

6

18

6

18

6

18

6

18

6

18

6

18

6

18

6

18

6

18

6

18

6

18

6

18

6

18

6

18

6

18

6

18

6

18

6

18

6

18

6

20

6

20

6

20

6

20

6

20

6

20

6

20

6

20

6

20

6

20

6

20

6

20

6

20

6

20

6

20

6

20

6

20

6

20

6

20

6

19

6

19

6

19

6

17

6

17

6

19

6

19

6

19

6

19

6

19

6

19

6

19

6

19

6

19

6

19

6

19

6

19

6

19

6

19

6

19

6

17

19

6

17

6

17

6

20

6

20

6

20

6

17

6

20

6

20

6

20

6

17

6

54

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

20

6

20

6

20

6

20

6

20

6

20

7

31 35

49 50 51

58 72 73

74 84

86 99

101

6

20

6

93

6

19

6

18

6

18

9

6

20

6

18

6

20

6

20

6

20

6

20

6

20

6

20

6

39

19

6

20

6

20

6

20

6

20

6

20

6

20

6

20

6

20

6

20

6

20

6

18

6

18

6

18

46 47

6

17

6

17

20 94

6

20

6

19

6

17

6

17

6

17

6

17

6

20

6

54

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

84 85 98

6

17

6

17

6

17

6

19

6

93

6

93

6

17

62 63 99

42 93

84 89

42 99

7

12 16 72 73 88

101

18 31 46 74 86

6

19

54

43 99

54

46 48

6

18

6

19

6

19

6 7 8

25 26 27 28 30 34 37 40 42 47

48 49 52 53 55 59 63 64 69 70 71 72

73 74 81 84 85 86 88 99

101

33

45

7

31 33 43 44 45 47 51 55 68 73 83

103

6 7

17 21 23 43 45 46 47 48 49

50 51 54 65 66 74

7

50 69

7 8

40 50 66 67 68 70 71 83 87

6 7 8

23 42 48 53 55 69 70 71 73 87

102

33

17 25 26 28 30 32 34 42 48 49

64 94 34

34 99

34

17 34 94

34 94

34 99

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

55

54 55

55

54 55

6

33 46 49 55 97

6

33 46 49 55 97

65

65 66

6

46 49 65 66 97

6

46 49 65 66 97

6 7

17 21 23 43

45 46 47 48 49 50 51 54

65 66 74

6

46 49 65 66 97

6

46 49 65 66 97

46 47 65

33 99

6

33 46 49 55 97

7

40 72

6

18

6

18

6

18

6

18

6

18

46 47 48

54

45

88 89

6

17

42 93

6

20

6

20

6

20

6

20

6

20

20 94

6

20 94

6

20 94

6

19

53

62 63 99

6

18

6

18

6

18

6

18

6

17

19

6

18

6

55

54

45

84 85

7

73 75 80 81 82 83 85

80 81

6

18

6

75

80 81

81

80 81

8

18 93

8

18

6

75

6

18

6

18

34

54

6

18 27 33 34

33 99

33 94

17 33 94

33 94

62 63 99

6

18 27 33 34

7

73 88

6

19

6

93

6 6

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

"G3Hot" (Always-Present) Rails

Chipset "VCore" Rails

2A max supply

5V Rails

? mA

ENET Rails

"GPU" Rails

"FW" (FireWire) RailsDDR Rails

1.5V/1.05V Rails

3.3V/1.8V Rails

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

Power Aliases

PP3V3_S5

PP3V3_S5 PP3V3_S5 PP3V3_S5

PP3V3_S5

PP5V_S0

VOLTAGE=5V

MIN_LINE_WIDTH=0.6 MM

PP5V_S0

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 MM

PP1V05_S0GPU_ISNS_R

PP1V8_S0GPU_ISNS_R

VOLTAGE=1.05V

PP1V05_S0GPU_ISNS_R

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

PP1V8_S0GPU_ISNS_R

PP1V5_S3

PP1V5_S3RS0

PPCPUDDR_ISNS

PP3V3_S5

PPVTTDDR_S3

PP1V5_S0

PP1V5_S3

PP1V5_S3 PP1V5_S3

MAKE_BASE=TRUE

VOLTAGE=1.5V

PP1V5_S3

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

PP0V75_S0_DDRVTT

PP1V2_S0

PP1V5_S0 PP1V5_S0

PP1V5_S0

PP1V2_S0

VOLTAGE=1.2V

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

VOLTAGE=1.5V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

PP1V5_S0

PP3V3_S5

PP1V8_S0

PP3V42_G3H

PP1V8_S0 PP1V8_S0

PP1V8_S0

MAKE_BASE=TRUE

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

PP1V8_S0

PP1V0_FW

MIN_NECK_WIDTH=0.2 MM

PPVIN_FW_FWPHY

VOLTAGE=1.0V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 MM

PP3V3_S5

PPBUS_G3H

PPBUS_FW_FWBOOST

MIN_LINE_WIDTH=0.4 MM

MAKE_BASE=TRUE

VOLTAGE=6V

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.4 MM VOLTAGE=10V

MAKE_BASE=TRUE

PP10V_FW

MIN_LINE_WIDTH=0.4 MM

PPVP_FW

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM VOLTAGE=10V

MAKE_BASE=TRUE

PP1V0_FW

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.3 MM

MAKE_BASE=TRUE

VOLTAGE=3.3V

PP3V3_S0GPU

PP1V8_GPUIFPX

MIN_NECK_WIDTH=0.15 MM

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

VOLTAGE=1.8V

PP1V8_S0GPU_ISNS

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

VOLTAGE=1.25V

PP1V8_S0GPU_ISNS_R

PPVCORE_GPU

VOLTAGE=1.2V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PP1V05_S0GPU

PPBUS_FW_FWBOOST

PP10V_FW

PPVP_FW

PP3V3_FW_FWPHY

PP1V0_FW

PPVIN_FW_FWPHY

PP3V3_S0GPU PP3V3_S0GPU PP3V3_S0GPU

PP3V3_S0GPU

PP1V8_GPUIFPX

PP1V8_S0GPU_ISNS PP1V8_S0GPU_ISNS

PP1V8_GPUIFPX

PP1V8_S0GPU_ISNS

PP1V05_S0GPU_ISNS_R

PP1V05_S0GPU PP1V05_S0GPU PP1V05_S0GPU PP1V05_S0GPU

PP1V05_S0GPU

PPVCORE_GPU

PPBUS_G3H

PP3V3_FW_FWPHY

PPBUS_FW_FWBOOST

PPVP_FW

MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

PP3V3_FW_FWPHY

MIN_LINE_WIDTH=0.4 MM

MAKE_BASE=TRUE

PP10V_FW

PP1V05_S5

VOLTAGE=1.05V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.25V

PPVCORE_S0_CPU

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

VOLTAGE=3.3V

PP3V3_ENET

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

VOLTAGE=1.2V

PP1V2_ENET

PP1V05_S5

PPCPUVTT_S0

PP1V05_S5

PPCPUVTT_S0

PPCPUVTT_S0 PPCPUVTT_S0

PPCPUVTT_S0

PPVCORE_S0_GFX

PPVCORE_S0_CPU_VCAP0

VOLTAGE=1.25V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM

PPVCORE_S0_CPU_VCAP1

VOLTAGE=1.25V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM

PPVCORE_S0_CPU_VCAP2

VOLTAGE=1.25V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM

PP3V3_ENET

PP1V2_ENET

PP1V2_ENET PP1V2_ENET

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 MM

PPDCIN_G3H

VOLTAGE=18.5V

MIN_LINE_WIDTH=0.6 MM

PPBUS_CPU_IMVP_ISNS

PPDCIN_G3H

PP3V42_G3H PP3V42_G3H PP3V42_G3H

PP3V42_G3H

PP5V_S5

PP3V42_G3H

PP3V42_G3H PP3V42_G3H

MIN_LINE_WIDTH=0.3 MM

PP3V42_G3H

VOLTAGE=3.42V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

PPDCIN_G3H

PP3V3_S5

PP3V42_G3H

PPVCORE_S0_CPU_VCAP2

PPVCORE_S0_CPU_VCAP1

PPVCORE_S0_CPU_VCAP0

PPVCORE_S0_GFX

PP5V_S0_ISNS_R

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 MM VOLTAGE=5V

MIN_LINE_WIDTH=0.5 MM

PP5V_S3_ISNS_R

PP5V_S0

PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0

PP5V_S0

PP5V_S0 PP5V_S0 PP5V_S0

PP5V_S0

PP5V_S0_ISNS_R

PP5V_S5

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.3 MM

MAKE_BASE=TRUE

VOLTAGE=5V

PP5V_S5

PPBUS_CPU_IMVP_ISNS

PP5V_S3_ISNS_R

PP3V42_G3H

PP5V_S0

MAKE_BASE=TRUE

PPVCORE_S0_GFX

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PPVCORE_S0_CPU

PPBUS_G3H

MIN_LINE_WIDTH=0.4 MM VOLTAGE=6V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 MM

PPBUS_CPU_IMVP_ISNS

VOLTAGE=5V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.25 MM

PP5V_S3_ISNS_R

PP5V_S5

PP5V_S3

PP5V_S3 PP5V_S3

PP5V_S3

PP5V_S3 PP5V_S3

PP5V_S3

MIN_NECK_WIDTH=0.25 mm

PP5V_S3

VOLTAGE=5V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 mm

PP5V_S3 PP5V_S3

PPBUS_G3H

PP3V42_G3H

PP3V3_S5 PP3V3_S5

PPBUS_G3H

PPBUS_G3H PPBUS_G3H

MAKE_BASE=TRUE

VOLTAGE=6V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.4 mm

PPBUS_G3H

PP3V3_S5

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PP3V3_S5

PP5V_S5

PP3V3_S5_ISNS_R

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

PP3V3_S5_ISNS_R

PP3V3_S3

PP3V3_S3 PP3V3_S3

PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3

PP3V3_S3 PP3V3_S3 PP3V3_S3

PP3V3_S3

PPCPUVTT_S0

VOLTAGE=1.05V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

PP1V5_S3

MIN_LINE_WIDTH=0.3 MM

PPVTTDDR_S3

VOLTAGE=0.75V

MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE

PP0V75_S0_DDRVTT

VOLTAGE=0.75V MAKE_BASE=TRUE

MIN_LINE_WIDTH=2 mm MIN_NECK_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

VOLTAGE=1.5V

PPCPUDDR_ISNS

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

VOLTAGE=1.5V

PP1V5_S3RS0

PP3V3_S3_ISNS_R

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=3.3V MAKE_BASE=TRUE

PP3V3_S0

PP3V3_S3_ISNS_R

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.20MM

PP3V3_S0

MIN_LINE_WIDTH=0.3 MM

PP3V3_S3_ISNS_R

PP3V3_S0

MIN_LINE_WIDTH=0.5 mm

PP3V3_S3

MIN_NECK_WIDTH=0.25 mm MAKE_BASE=TRUE

VOLTAGE=3.3V

PP3V3_S3

8 OF 132 7 OF 103

6 7

31 35 49 50 51 58 72 73 74 84 86 99

101

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72 73 74 84 86 99

101

6 7

31 35 49 50 51 58 72 73 74 84 86 99

101

6 7

31 35 49 50 51 58 72 73 74 84 86 99

101 6 7

31 35 49 50 51 58 72 73 74 84 86 99

101 6 7

31 35 49 50 51 58 72 73 74 84 86 99

101

6 7

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58 72 73 74 84 86 99

101

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101

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101

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23 42 48 53 55 69 70 71 73 87

102

6 7 8

23 42 48 53 55 69 70 71 73 87

102

7

51 87

6 7

51 87

7

51 87

6 7

51 87

7

28 30 31 68 73

7

57 73

7

57 73

7

13 16 31 57

7

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6 7

31 35 49 50

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101

6 7

32 68

7

34 42 59 72 74 99

7

28 30 31 68 73

7

28 30 31 68 73

7

28 30 31 68 73

7

28 30 31 68 73

7

28 30 31 68 73

7

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7

28 30 31 68

7

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7

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6 7

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6 7

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7

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7

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7

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7

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6 7

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7

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101

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101

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101

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50 51 54 65 66 74

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101

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101

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101

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101

6 7

40 72

7

39 40 72

6 7

31 35 49 50 51 58 72 73 74 84 86 99

101

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31 35 49 50 51 58 72 73 74 84 86 99

101

6 7 8

40 50 66 67 68 70 71 83

87

7

40 72

7 8

40 72

6 7

40 41

6 7

40 72

6 7

73 75 80 81 82

83 85

6 7

73 82

6 7 8

51 76 77 78

79

6 7

51 87

6 7

50 76 83

6 7

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7

40 72

7 8

40 72

7 8

40 72

6 7

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6 7

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7

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7

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6 7

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7

39 40 72

7

39 40 72

6 7

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83 85 6 7

73 75 80 81 82

83 85 6 7

73 75 80 81 82

83 85

6 7

73 75 80 81 82

83 85

6 7

73 75 80 81 82

83 85

6 7

73 75 80 81 82 83 85

6 7

73 82

6 7 8

51 76 77 78

79 6 7 8

51 76 77 78

79

6 7

73 82

6 7 8

51 76 77 78 79

6 7 8

51 76 77 78

79

6 7 8

51 76 77 78

79

7

51 87

6 7

51 75 77 80 82

6 7

51 75 77 80 82

6 7

51 75 77 80 82

6 7

51 75 77 80 82

6 7

51 75 77 80 82

6 7

51 75 77 80 82

6 7

51 75 77 80 82

6 7

51 75 77 80 82

6 7

51 75 77 80 82

6 7

51 75 77 80 82

6 7

50 76 83

6 7

50 76 83

6 7 8

40 50 66 67 68 70 71 83

87

7

39 40 41

7

40 72

6 7

40 41

7

39 40 41

7 8

40 72

7

17 72

6 7

12 15 50 69

7

27 37 74

7

37 72 73

7

17 72

6 7

10 12 13 15 25 26 40 71 74

101

7

17 72

6 7

10 12 13 15 25 26 40 71 74

101

6 7

10 12 13 15 25 26 40 71 74

101

6 7

10 12 13 15 25 26 40 71 74

101

6 7

10 12 13 15 25 26 40 71 74

101

6 7

10 12 13 15 25 26 40 71 74

101

6 7

10 12 13 15 25 26 40

71 74

101

6 7

10 12 13 15 25 26 40 71 74

101

6 7

10 12 13 15 25 26 40 71 74

101

6 7

10 12 13 15 25 26 40

71

74

101

7

13 24 50 70

7

12 16

7

12 16

7

13 24

7

27 37 74

7

27 37 74

7

37 72 73

7

37 72 73

6 7

65 66

6 7

50 69

6 7

65 66

6 7

17 21 23 43 45 46 47 48 49

50 51 54 65 66 74 6 7

17 21 23 43 45 46 47 48 49

50 51 54 65 66 74 6 7

17 21 23 43 45 46 47 48 49

50 51 54 65 66 74

6 7

17 21 23 43 45 46 47 48 49

50 51 54 65 66 74 6 7

17 21 23 43 45 46 47 48 49

50 51 54 65 66 74 6 7

17 21 23 43 45 46 47 48 49

50 51 54 65 66 74

6 7

17 21 23 43 45 46 47 48 49

50 51 54 65 66 74

6 7

17 21 23 43 45 46 47 48 49

50 51 54 65 66 74

6 7

17 21 23 43 45 46 47 48 49

50 51 54 65 66 74

7

23 57 67 73

102

7

23 57 67 73

102

6 7

17 21 23 43 45 46 47 48 49

50 51 54 65 66 74

6 7

17 21 23 43 45 46 47 48 49

50 51 54 65 66 74 6 7

17 21 23 43 45 46 47 48 49

50 51 54 65 66 74

6 7

17 21 23 43

45 46 47 48 49 50 51 54 65 66

74

6 7

65 66

6 7

31 35 49 50 51 58 72 73 74 84 86 99

101

6 7

17 21 23 43 45 46 47 48 49

50 51 54 65 66 74

6 7

17 21 23 43 45 46 47 48 49

50 51 54 65 66 74

7

13 24

7

12 16

7

12 16

7

13 24 50

70

7

73

102

7

51 67

6 7 8

23 42 48 53 55

69 70 71 73 87

102

6 7 8

23 42 48 53 55 69 70 71 73 87

102

6 7 8

23 42 48 53 55 69 70 71 73 87

102

6 7 8

23 42 48 53 55 69 70 71 73 87

102

6 7 8

23 42 48 53 55 69 70 71 73 87

102

6 7 8

23 42 48 53 55 69 70 71 73 87

102

6 7 8

23 42 48 53 55 69 70 71 73 87

102

6 7 8

23 42 48 53 55 69 70 71 73 87

102

6 7 8

23 42 48 53 55 69 70 71 73 87

102

6 7 8

23 42 48 53 55 69 70 71 73 87

102

6 7 8

23 42 48 53 55 69 70 71 73 87

102

6 7 8

23 42 48 53 55 69 70 71 73 87

102

6 7 8

23 42 48 53 55 69 70 71 73 87

102

7

73

102

7

73

102

7

23 57 67 73

102

7

23 57 67 73

102

7

23 57 67 73

102

6 7

50 69

7

51 67

6 7

17 21 23 43

45 46 47

48 49 50

51 54 65

66 74

6 7 8

23 42 48 53 55 69 70 71 73 87

102

7

13 24 50 70

6 7

12 15 50 69

6 7

12 15 50

69

6 7 8

40 50 66 67 68 70 71 83

87

6 7

50 69

7

51 67

7

23 57 67 73

102

6 7

31 33 43

44 45 47 51 55

68 73 83

103

6 7

31 33 43 44 45 47 51 55 68 73 83

103

6 7

31 33 43 44 45 47 51 55 68 73 83

103

6 7

31 33 43 44 45 47 51 55 68 73 83

103

6 7

31 33 43 44 45 47 51 55 68 73 83

103

6 7

31 33 43 44 45 47 51 55 68 73 83

103

6 7

31 33 43 44 45 47 51 55 68 73 83

103

6 7

31 33 43 44 45 47 51 55 68 73 83

103

6 7

31 33 43 44 45 47 51 55 68 73 83

103

6 7

31 33 43 44 45 47 51 55 68 73 83

103

6 7

31 33 43 44 45 47 51 55 68 73 83

103

6 7

31 33 43 44 45 47 51 55 68 73 83

103

6 7

31 33 43 44 45 47 51 55 68 73 83

103

6 7

31 33 43 44 45 47 51 55 68 73 83

103

6 7 8

40 50 66 67 68 70 71 83

87

6 7 8

40 50 66 67 68 70 71 83

87

6 7 8

40 50 66 67 68 70 71 83

87

6 7 8

40 50 66 67 68 70 71 83

87

6 7 8

40 50 66 67 68 70 71 83

87

6 7

17 21 23 43 45 46 47 48 49

50 51 54 65 66 74

6 7

31 35 49 50 51 58 72 73 74 84 86 99

101 6 7

31 35 49 50 51 58 72 73 74 84 86 99

101

6 7 8

40

50 66 67

68 70 71

83 87

6 7 8

40 50 66 67 68 70 71 83

87 6 7 8

40 50 66 67 68 70 71 83

87

6 7

31 35 49 50 51 58

72

73 74 84 86 99

101

6 7

31 35 49 50 51 58 72 73 74 84 86 99

101

7

23 57 67 73

102

7

23 57 67 73

102

7

51 67

7

51

67

7

51 67

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

6 7

17 20 31 32 33 34 35 36 49 50 51 54 55 56 72 74 88

102 103

6 7 17 20 31 32 33 34 35 36 49 50 51 54 55 56 72 74 88

102 103

6 7

10 12 13 15 25 26 40 71 74

101

7

28 30 31 68 73

6 7

32 68

7

28 30 31 68

7

13 16 31 57

7

57 73

7

73

102

7

73

102

6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52 53 55 59 63 64 69

70 71 72 73 74 81 84 85 86 88 99

101

7

73

102

6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52 53 55 59 63 64 69 70 71 72 73 74 81

84 85 86 88 99

101

6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52 53 55 59 63 64 69

70 71 72 73 74 81 84 85 86 88 99

101

6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52 53 55 59 63 64 69 70 71 72 73 74 81

84

85 86 88 99

101

6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52 53 55 59 63 64 69 70 71 72 73 74 81

84 85 86 88 99

101

6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52 53 55 59 63 64 69 70 71 72 73 74 81

84 85 86 88 99

101

6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52 53 55 59 63 64 69 70 71 72 73 74 81

84

85 86 88 99

101 6 7 8

25 26 27 28 30 34 37 40 42 47 48

49 52 53 55 59 63 64 69 70

71 72 73 74 81 84 85 86 88 99

101 6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52

53 55 59 63 64 69 70 71 72 73 74 81 84

85

86 88 99

101

6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52 53 55 59 63 64 69 70 71 72 73 74

81 84 85 86 88 99

101

6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52 53 55 59

63 64 69 70 71 72 73 74 81 84 85 86 88

99

101

6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52 53 55 59 63 64 69 70 71 72 73 74 81

84 85 86

88 99

101 6 7 8

25 26 27 28 30 34 37 40 42 47 48

49 52 53 55 59 63 64 69 70 71 72

73 74 81 84 85 86 88 99

101

6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52 53 55 59

63 64 69 70 71 72 73 74 81 84 85 86 88

99

101

6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52 53 55 59 63 64 69 70 71 72 73 74 81

84 85 86 88 99

101

6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52 53 55 59 63 64 69

70 71 72

73

74 81 84 85 86 88 99

101

6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52 53 55 59

63 64 69 70 71 72 73 74 81 84 85 86 88

99

101

6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52 53 55 59 63 64 69 70 71 72 73 74 81

84 85 86 88 99

101

6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52 53 55 59 63 64 69

70 71 72 73 74 81 84 85 86 88 99

101

6 7 8

25 26

27 28

30

34 37 40 42 47 48 49 52 53 55 59 63 64

69

70 71 72 73 74 81 84 85 86 88 99

101

6 7 8 25 26 27 28 30 34 37 40 42 47 48 49 52 53 55 59 63 64 69 70 71 72 73 74 81 84 85 86 88 99

101

6 7 8

25 26 27 28 30 34 37 40 42 47 48 49 52

53 55 59 63

64 69 70 71 72 73 74 81 84 85 86 88 99

101

6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52 53 55 59 63 64 69 70 71 72 73 74 81

84 85 86 88 99

101

6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52 53 55 59 63 64 69 70 71 72 73 74 81

84

85 86 88 99

101

6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52 53 55 59 63 64 69 70 71 72 73 74 81

84 85 86

88 99

101 6 7 8

25 26 27 28 30 34 37 40 42 47 48

49 52 53 55 59 63 64 69 70 71 72

73 74 81 84 85 86 88 99

101 6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52

53 55 59 63 64 69 70 71 72 73 74 81 84

85

86 88 99

101

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

6 7

17

20 31 32 33 34 35 36 49 50 51 54 55 56

72 74 88

102 103

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

** PEG LANES REVERSED. ARD STRAP REQ’D. **

TM Hole

Bosses for Flex Protector Bracket

GMUX ALIASES

Right CPU

GPU signals

Left CPU

Digital Ground

TM Hole

CPU signals

TM Hole

Bottom Left GPU

Frame Holes

Top GPU Right

AUDIO ALIASES

Thermal Module Holes

It will be removed from the design after proto1.

Per WF: R0914 can’t be stuffed, it will break CPU IMON Calculation.

USB Hub Aliases

Rev. A NCs

STDOFF-4.5OD.98H-1.1-3.48-TH

ZT0980

1

2 1

XW0900

SM

XW0901

2 1

SM

R0900

21

10

MF-LF

402

1%

1/16W

21

R0901

10

MF-LF

402

1%

1/16W

1

ZT0981

STDOFF-4.5OD.98H-1.1-3.48-TH

ZT0982

STDOFF-4.5OD.98H-1.1-3.48-TH

1

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0983

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0984

ZT0987

1

STDOFF-4.5OD.98H-1.1-3.48-TH

1

3R2P5

ZT0960

1

ZT0989

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0988

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0991

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0930

1

ZT0934

STDOFF-4.0OD3.0H-SM

1

ZT0931

STDOFF-4.0OD3.0H-SM

1

ZT0932

3R2P5

1

ZT0971

3R2P5

1

SM

SH0913

1.4DIA-SHORT-EMI-MLB-M97-M98

1

SH0910

1.4DIA-SHORT-EMI-MLB-M97-M98

SM

1

SH0914

SM

1.4DIA-SHORT-EMI-MLB-M97-M98

SH0911

1

SM

1.4DIA-SHORT-EMI-MLB-M97-M98

1

SH0900

SM

2.0DIA-TALL-EMI-MLB-M97-M98

1

SH0903

SM

2.0DIA-TALL-EMI-MLB-M97-M98

1

SH0902

SM

2.0DIA-TALL-EMI-MLB-M97-M98

1

SH0919

SM

1

SH0917

SM

2.0DIA-TALL-EMI-MLB-M97-M98

SH0916

SM

1

2.0DIA-TALL-EMI-MLB-M97-M98

1

SM

SH0918

1.4DIA-SHORT-EMI-MLB-M97-M98

1

SH0920

SM

1

SM

2.0DIA-TALL-EMI-MLB-M97-M98

SH0921

2.0DIA-TALL-EMI-MLB-M97-M98

1

SH0922

SM

1

SM

1.4DIA-SHORT-EMI-MLB-M97-M98

SH0923

ZT0957

4.0OD1.65H-M1.6X0.35

1

ZT0958

4.0OD1.65H-M1.6X0.35

1

SH0901

2.0DIA-TALL-EMI-MLB-M97-M98

SM

3R2P5

ZT0915

1

SH0924

SM

1

2.0DIA-TALL-EMI-MLB-M97-M98

1

SH0930

SM

2.0DIA-TALL-EMI-MLB-M97-M98

1

SM

2.0DIA-TALL-EMI-MLB-M97-M98

SH0931

1

SH0932

SM

2.0DIA-TALL-EMI-MLB-M97-M98

1

SH0933

SM

1

SH0935

2.0DIA-TALL-EMI-MLB-M97-M98

SM

1

SH0934

2.0DIA-TALL-EMI-MLB-M97-M98

SM

1

ZT0940

3R2P5

1

ZT0970

3R2P5

2 1

XW0902

SM

R0904

MF-LF

5%

1/10W

BKLT_PWR_PBUS

0

603

21

MF-LF

5%

0

BKLT_PWR_FW10V

603

1/10W

R0903

1 2

1.4DIA-SHORT-EMI-MLB-M97-M98

SM

SH0912

21

3.0K

5%

R0902

402

MF-LF

1/16W

1 2

402

1/16W

GMUX_VSYNC

R0906

MF-LF

5%

0

1 2

R0907

5%

0

PANEL_VSYNC

402

MF-LF

1/16W

Signal Aliases

SYNC_MASTER=K17_REF

SYNC_DATE=06/17/2009

NC_ISNS_PVTTS0PCH_P

NC_ISNS_PVTTS0PCH_NNC_ISNS_PVTTS0PCH_N

MAKE_BASE=TRUE

NC_ISNS_PVTTS0PCH_P

MAKE_BASE=TRUE

NC_ISNS_P3V3S0MPCH_P

NC_ISNS_P3V3S0MPCH_N

NC_ISNS_P3V3S0MPCH_P

MAKE_BASE=TRUE

NC_ISNS_P3V3S0MPCH_N

MAKE_BASE=TRUE

NC_ISNS_P1V05S0PCH_PNC_ISNS_P1V05S0PCH_P

MAKE_BASE=TRUE

NC_ISNS_P1V05S0PCH_N

MAKE_BASE=TRUE

NC_ISNS_P1V05S0PCH_N

USB_EXCARD_N USB_EXCARD_P

USB_EXTC_OC_L

EXCARD_OC_L

MAKE_BASE=TRUE

USB_EXCARD_P

MAKE_BASE=TRUE

USB_EXCARD_N

MAKE_BASE=TRUE

USB_EXTC_OC_L

MAKE_BASE=TRUE

EXCARD_OC_L

GPU_FB_A_VREF_DIV

MAKE_BASE=TRUE

TP_CPU_VTT_SELECT

NC_LVDS_IG_A_DATAN<3>

NC_LVDS_IG_B_DATAP<3>

TP_LVDS_IG_B_CLKN TP_LVDS_IG_BKL_PWMTP_LVDS_IG_BKL_PWM

MAKE_BASE=TRUE

TP_LVDS_IG_B_CLKP

MAKE_BASE=TRUE

TP_LVDS_IG_B_CLKN

TP_LVDS_IG_B_CLKP

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_XTALOUT

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_A_DATAP<3>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_A_DATAN<3>

NC_LVDS_IG_A_DATAP<3>

=PEG_D2R_N<0..15>

=PEG_D2R_P<0..15>

BKL_SYNC BKL_SYNC

MAKE_BASE=TRUE

DP_IG_ML_P<3..0>

MAKE_BASE=TRUE

DP_IG_ML_N<3..0>

MAKE_BASE=TRUE

DP_IG_B_ML_P<3..0>

=PEG_R2D_C_P<0..15>

MAKE_BASE=TRUE

TP_CPU_VTT_SELECT

NC_LVDS_IG_B_DATAN<3>

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_B_DATAP<3>

MAKE_BASE=TRUE

NC_GPU_XTALOUT

NC_LVDS_IG_B_DATAN<3>

LVDS_CONN_BKL_SYNC

GMUX_VSYNC

GND

PP3V3_S0

MAKE_BASE=TRUE

PP3V3_S0

PM_ENET_EN

LCD_BKLT_EN

MAKE_BASE=TRUE

PEG_CLKREQ_L PEG_CLKREQ_L

MAKE_BASE=TRUE

PEX_CLKREQ_L PEX_CLKREQ_L

CPU_VID<0..6>

MAKE_BASE=TRUE

MEMVTT_EN

MIN_LINE_WIDTH=0.5 mm

PP5V_S0_AUDIO_AMP_R

VOLTAGE=5V

MIN_NECK_WIDTH=0.25 mm

VOLTAGE=5V

PP5V_S0_AUDIO

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

PP5V_S0

LVDS_IG_PANEL_PWR

LVDS_IG_BKL_ON

MAKE_BASE=TRUE

GFX_VID<0..6>

GFXIMVP_VID<0..6>

CPUIMVP_VID<0..6>

FW643_WAKE_L

MAKE_BASE=TRUE

MEMVTT_EN

PP1V8_S0GPU_ISNS

GPU_FB_A_VREF_DIV

GPU_FB_B_VREF_DIV

GND

PM_ALL_GPU_PGOOD

MAKE_BASE=TRUE

PM_ALL_GPU_PGOOD

EG_RESET_L

MAKE_BASE=TRUE

EG_RESET_L

TP_LVDS_MUX_SEL_EGTP_LVDS_MUX_SEL_EG

MAKE_BASE=TRUE

LVDS_IG_PANEL_PWR

MAKE_BASE=TRUE

PEG_R2D_C_P<15..0>

MAKE_BASE=TRUE

PEG_R2D_C_N<15..0>

MAKE_BASE=TRUE

PPVIN_S0_LCDBKLT

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.4 mm

MAKE_BASE=TRUE

VOLTAGE=6V

PPVIN_S0_LCDBKLT

PP10V_FW

PPBUS_G3H

PM_ENET_EN

MAKE_BASE=TRUE

=PEG_R2D_C_N<0..15>

PEG_D2R_N<15..0>

MAKE_BASE=TRUE

PEG_D2R_P<15..0>

MAKE_BASE=TRUE

DP_IG_B_ML_N<3..0> DP_IG_AUX_CH_PDP_IG_AUX_CH_P

MAKE_BASE=TRUE

DP_IG_HPD

MAKE_BASE=TRUE

DP_IG_HPD

DP_IG_DDC_DATADP_IG_DDC_DATA

MAKE_BASE=TRUE

DP_IG_AUX_CH_N

MAKE_BASE=TRUE

DP_IG_AUX_CH_N

TP_SATA_EXTA_D2R_N

MAKE_BASE=TRUE

TP_SATA_EXTA_D2R_N

DP_IG_DDC_CLKDP_IG_DDC_CLK

MAKE_BASE=TRUE

TP_SATA_EXTA_R2D_C_P

MAKE_BASE=TRUE

TP_SATA_EXTA_R2D_C_P

TP_SATA_EXTA_D2R_P TP_SATA_EXTA_R2D_C_N

MAKE_BASE=TRUE

TP_SATA_EXTA_R2D_C_N

FW_PLUG_DET_L

FW643_WAKE_L

MIN_LINE_WIDTH=0.5 mm

PP5V_S0_AUDIO_AMP_L

MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V

MAKE_BASE=TRUE

FW_PLUG_DET_L

GND

MAKE_BASE=TRUE

GND GND

GND

MAKE_BASE=TRUE

TP_SATA_EXTA_D2R_P

LCD_BKLT_EN

LVDS_IG_BKL_ON

MAKE_BASE=TRUE

CPU_CFG<3>

GPU_FB_B_VREF_DIV

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2MM VOLTAGE=0V

MIN_LINE_WIDTH=0.6MM

GND

9 OF 132 8 OF 103

8

99

102

8

99

102

8

99

102

8

99

102

8

99

102

8

99

102

8

99

102

8

99

102

8

50 99

8

50 99

8

50 99

8

50 99

8

34 36 93

8

34 36 93

8

35 44

8

34 36 47

8

34 36 93

8

34 36 93

8

35 44

8

34 36 47

8

32 78

8

12 91

8

18 93

8

18 93

6 8

18 93

6 8

18

6 8

18

6 8

18 93

6 8

18 93

6 8

18 93

8

80

8

18 93

8

18 93

8

18 93

8

85 93

18

9

8

12 91

8

18 93

8

18 93

8

80

8

18 93

6

84

88

6 7 8

25 26 27 28

30 34 37 40 42 47

48 49 52 53

55 59 63 64

69 70 71 72

73 74 81 84

85 86 88 99

101

6 7 8

25 26 27 28 30 34 37 40 42 47 48

49 52 53 55 59 63 64 69 70 71 72 73 74

81 84 85 86 88 99

101

8

88 90

8

17 88

8

17 88

8

75 88

8

75 88

12 15 91

8

31 68

62

59 61

6 7

23 42 48 53 55 69 70 71 73 87

102

8

18 88

8

18 88

13 91

70

69

8

39 40

8

31 68

6 7

51 76 77 78 79

8

32 78

8

32 79

8

74 83 87 88

8

74 83 87 88

8

75 88

8

75 88

8

88

8

88

8

18 88

75 91

8

90

8

90

7

40 72

6 7

40 50 66 67 68 70 71 83

87

8

72 74

9

75 91

9

75 91

18

8

18 85 93

8

18 85 93

8

18 85

8

18 85

8

18 81 85

8

18 81 85

8

18 85 93

8

18 85 93

8

17 93

8

17 93

8

18 81 85

8

18 81 85

8

17 93

8

17 93

8

17 93

8

17 93

8

17 93

8

20 40

8

39 40

62

8

20 40

8

17 93

8

88 90

8

18 88

9

25 91

8

32 79

IN IN IN IN

IN

OUT

IN IN

IN

IN IN

IN

IN IN IN IN IN

OUT

OUT OUT OUT

OUT

OUT OUT OUT OUT OUT

OUT OUT OUT OUT

OUT

IN

FDI_TX1

DMI_RX0*

DMI_TX2*

DMI_RX1*

PEG_RX0* PEG_RX1* PEG_RX2* PEG_RX3* PEG_RX4* PEG_RX5*

PEG_RX7*

PEG_RX6*

PEG_RX9*

PEG_RX8*

PEG_RX10*

PEG_RX12*

PEG_RX11*

PEG_RX13* PEG_RX14* PEG_RX15*

PEG_RX0 PEG_RX1

PEG_RX3

PEG_RX2

PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8 PEG_RX9

PEG_RX11

PEG_RX10

PEG_RX13

PEG_RX12

PEG_RX15

PEG_RX14

PEG_TX0* PEG_TX1* PEG_TX2*

PEG_TX4*

PEG_TX3*

PEG_TX5* PEG_TX6* PEG_TX7* PEG_TX8*

PEG_TX9* PEG_TX10* PEG_TX11* PEG_TX12* PEG_TX13* PEG_TX14* PEG_TX15*

PEG_TX0 PEG_TX1

PEG_TX3

PEG_TX2

PEG_TX5

PEG_TX4

PEG_TX6

PEG_TX8

PEG_TX7

PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15

DMI_RX2

DMI_RX0 DMI_RX1

DMI_RX3

DMI_TX0* DMI_TX1*

DMI_TX3*

DMI_TX0 DMI_TX1 DMI_TX2 DMI_TX3

FDI_TX1*

FDI_TX0*

FDI_TX2* FDI_TX3*

FDI_TX5*

FDI_TX4*

FDI_TX6* FDI_TX7*

FDI_TX0

FDI_TX3

FDI_TX2

FDI_TX4 FDI_TX5 FDI_TX6 FDI_TX7

FDI_FSYNC0 FDI_FSYNC1

FDI_LSYNC0

FDI_INT

FDI_LSYNC1

PEG_ICOMPI PEG_ICOMPO

PEG_RBIAS

PEG_RCOMPO

DMI_RX3*

DMI_RX2*

(SYM 1 OF 11)

FLEXIBLE DISPLAY INTERFACE

DMI

PCI EXPRESS -- GRAPHICS

RSVD37

RSVD36

RSVD33

RSVD32

RSVD_NCTF5

RSVD_NCTF6

RSVD_NCTF8

RSVD_NCTF7

RSVD27

RSVD24

RSVD26

RSVD23

RSVD22

RSVD21

RSVD20

RSVD19

RSVD18

RSVD17

RSVD16

RSVD15

RSVD_TP0

CFG17

CFG16

CFG15

CFG14

CFG13

CFG11 CFG12

CFG10

CFG9

CFG8

CFG7

CFG6

CFG5

CFG3 CFG4

CFG2

CFG1

CFG0

DC_TEST_A5

DC_TEST_A69 DC_TEST_A68

DC_TEST_A71

DC_TEST_C3

DC_TEST_C69

DC_TEST_C71

DC_TEST_E1

DC_TEST_E71

DC_TEST_BR1

DC_TEST_BR71

DC_TEST_BT3 DC_TEST_BT1

DC_TEST_BT69

DC_TEST_BV1

DC_TEST_BT71

DC_TEST_BV3

DC_TEST_BV68

DC_TEST_BV5

DC_TEST_BV71 DC_TEST_BV69

RSVD64 RSVD65

RSVD62 RSVD63

RSVD_TP1

RSVD_TP2

RSVD57 RSVD58

RSVD56

RSVD54 RSVD55

RSVD52 RSVD53

RSVD51

RSVD50

RSVD49

RSVD48

RSVD46 RSVD47

RSVD45

RSVD_NCTF1

RSVD_NCTF2

RSVD39

RSVD_NCTF3

RSVD38

RSVD34

RSVD_NCTF4

RSVD35

(SYM 5 OF 11)

RESERVED

BI BI

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

WF: RSVD nets with red wires have 0-ohm resistors to GND in CRB schematic.

WF: RSVD nets with arrows have offpage marks on CRB schematic.

CFG3: PCIe Lane Reversal 1 = Normal Operation 0 = Lanes Reversed

and level-shifted for

NOTE: HPD must be inverted

eDP_TX<3> eDP_TX<2> eDP_TX<1> eDP_TX<0>

eDP_TX#<0>

eDP_TX#<1>

eDP_TX#<2>

eDP_TX#<3>

eDP_HPD# eDP_AUX

eDP_AUX#

Auburndale (1.05V).

(eDP) pins

Embedded DisplayPort

(Auburndale only):

CFG4: Display Port Presence 1 = eDP Disabled 0 = Embedded Display Port Enabled

CFG0: PCIe Configuration Select 1 = Single PEG 0 = Bifurcation Enabled

(IPU)

(IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU)

(IPU)

18 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

2

1

R1012

750

MF-LF

1/16W

402

1%

2

1

R1010

1/16W

1%

49.9

402

MF-LF

25 91

8

25 91

A31

B30

L30

J30

B35

D36

B33

A34

G32

H32

A38

B37

D40

B39

M32

N32

J20

L20

G21

F21

M24

N24

N26

M25

L28

N28

B32

D33

L38

N38

N40

L40

D26

B25

B26

A27

D29

B28

H24

K24

H25

G25

G28

J28

P34

M34

H34

G34

B14

D15

A17

B16

D19

B18

A20

B19

D22

B21

B23

A24

G38

J38

G40

F40

D12 B11

A13

B12

W8

W10

U7

U6

R7

R8

N10

N9

P1

R2

M4

N2

N7

N5

L2

K1

AB2

AA1

AB5

AC9

AC7

F10

J11

J13

G13

K15

M15

H17

G17

J4

J2

K8

K9

J8

J6

F7

F9

U1000

BGA

OMIT

ARRANDALE

AP2 AN7

AU1

A6

C5

E3 F1

BR5

BT5

BV6 BV8

BE71

BE69

AU2

AV4

AT67

AU69

AR69

AT70

AU71

AK69

AM66

AR71

AK66

AH66

AP66

AN69

AK71

AV69

R64

R66

AA69

AA71

AC71

AC69

W64

W66

B9

A10

B7

D8

BB69

AY69

AW70

AV71

V2

U1

T2

T4

E71 E1 C71 C69 C3

BV71 BV69 BV68 BV5 BV3 BV1 BT71 BT69 BT3 BT1 BR71 BR1

A71 A69 A68 A5

AG2

AF4

AG7

AT2

AJ2

AK4

AK2

AK1

AB7

AF6

AF8

AD1

AE2

AC4

AC2

AH1

AM2

AL4

U1000

BGA

ARRANDALE

OMIT

52 99

SYNC_DATE=06/09/2009

SYNC_MASTER=K17_WFERRY

CPU DMI/PEG/FDI/RSVD

CPU_CFG<0>

CPU_CFG<2>

=PEG_R2D_C_N<8>

=PEG_R2D_C_N<10> =PEG_R2D_C_N<11>

CPU_CFG<1>

CPU_CFG<4>

CPU_CFG<3>

CPU_CFG<5> CPU_CFG<6> CPU_CFG<7> CPU_CFG<8> CPU_CFG<9>

CPU_CFG<12> CPU_CFG<13> CPU_CFG<14> CPU_CFG<15> CPU_CFG<16>

TP_CPU_RSVD<15>

TP_CPU_RSVD<19>

TP_CPU_RSVD<26>

TP_CPU_RSVD<24>

TP_CPU_RSVD<27> NC_TP_CPU_RSVD_NCTF<7>

NC_TP_CPU_RSVD_NCTF<8> NC_TP_CPU_RSVD_NCTF<6>

NC_TP_CPU_RSVD_NCTF<5>

TP_CPU_RSVD<2> TP_CPU_RSVD<1>

TP_CPU_RSVD<64>

TP_CPU_RSVD<55>

TP_CPU_RSVD<54>

TP_CPU_RSVD<56> TP_CPU_RSVD<57>

TP_CPU_RSVD<45> TP_CPU_RSVD<46> TP_CPU_RSVD<47> TP_CPU_RSVD<48> TP_CPU_RSVD<49> TP_CPU_RSVD<50>

TP_CPU_RSVD<58>

TP_CPU_RSVD<52> TP_CPU_RSVD<53>

TP_CPU_RSVD<51>

NC_TP_CPU_RSVD<42>

NC_TP_CPU_RSVD<40>

NC_TP_CPU_RSVD<32> NC_TP_CPU_RSVD<33>

NC_TP_CPU_RSVD<36> NC_TP_CPU_RSVD<37>

NC_TP_CPU_RSVD<41>

NC_TP_CPU_RSVD<43>

NC_TP_CPU_RSVD<34>

NC_TP_CPU_RSVD<38> NC_TP_CPU_RSVD<39>

NC_TP_CPU_RSVD<35>

TP_CPU_TEST_BR1

TP_CPU_TEST_E1

TP_CPU_TEST_E71

TP_CPU_TEST_C3

TP_CPU_TEST_A5

TP_CPU_TEST_A68

CPU_TEST_C71_A71 CPU_TEST_C69_A69

FDI_LSYNC<1>

FDI_LSYNC<0>

FDI_INT

FDI_FSYNC<1>

FDI_FSYNC<0>

FDI_DATA_P<7>

FDI_DATA_P<6>

FDI_DATA_P<5>

FDI_DATA_P<4>

FDI_DATA_P<3>

FDI_DATA_P<2>

FDI_DATA_P<1>

FDI_DATA_P<0>

FDI_DATA_N<6> FDI_DATA_N<7>

FDI_DATA_N<5>

FDI_DATA_N<4>

FDI_DATA_N<3>

FDI_DATA_N<1> FDI_DATA_N<2>

FDI_DATA_N<0>

DMI_N2S_P<3>

DMI_N2S_P<2>

DMI_N2S_P<1>

DMI_N2S_P<0>

DMI_N2S_N<2> DMI_N2S_N<3>

DMI_N2S_N<1>

DMI_N2S_N<0>

DMI_S2N_P<3>

DMI_S2N_P<2>

DMI_S2N_P<0> DMI_S2N_P<1>

DMI_S2N_N<3>

DMI_S2N_N<2>

DMI_S2N_N<1>

DMI_S2N_N<0> CPU_PEG_COMP

CPU_PEG_RBIAS

PEG_D2R_N<15>

PEG_D2R_N<11> PEG_D2R_N<10>

PEG_D2R_N<13>

PEG_D2R_N<14>

PEG_D2R_N<12>

PEG_D2R_N<6>

PEG_D2R_N<8>

PEG_D2R_N<9>

PEG_D2R_N<7>

PEG_D2R_N<1> PEG_D2R_N<0>

PEG_D2R_N<2>

PEG_D2R_N<4>

PEG_D2R_P<12> PEG_D2R_P<11>

PEG_D2R_P<13>

PEG_D2R_P<14>

PEG_D2R_P<15>

PEG_D2R_P<7> PEG_D2R_P<6>

PEG_D2R_P<9>

PEG_D2R_P<10>

PEG_D2R_P<8>

PEG_D2R_P<1>

PEG_D2R_P<2>

PEG_D2R_P<3>

PEG_D2R_P<5> PEG_D2R_P<4>

=PEG_R2D_C_N<1> =PEG_R2D_C_N<2>

PEG_D2R_P<0>

=PEG_R2D_C_N<0>

=PEG_R2D_C_N<5> =PEG_R2D_C_N<6> =PEG_R2D_C_N<7>

=PEG_R2D_C_N<3> =PEG_R2D_C_N<4>

=PEG_R2D_C_N<13>

=PEG_R2D_C_N<12>

=PEG_R2D_C_N<9>

=PEG_R2D_C_N<15>

=PEG_R2D_C_N<14>

=PEG_R2D_C_P<0> =PEG_R2D_C_P<1>

=PEG_R2D_C_P<4>

=PEG_R2D_C_P<6>

=PEG_R2D_C_P<5>

=PEG_R2D_C_P<2> =PEG_R2D_C_P<3>

=PEG_R2D_C_P<9> =PEG_R2D_C_P<10> =PEG_R2D_C_P<11>

=PEG_R2D_C_P<7> =PEG_R2D_C_P<8>

=PEG_R2D_C_P<15>

=PEG_R2D_C_P<12> =PEG_R2D_C_P<13> =PEG_R2D_C_P<14>

PEG_D2R_N<5>

PEG_D2R_N<3>

TP_CPU_RSVD<21>

TP_CPU_RSVD<23>

TP_CPU_RSVD<22>

TP_CPU_RSVD<20>

TP_CPU_RSVD<65>

TP_CPU_TEST_BR71

TP_CPU_RSVD<18>

TP_CPU_RSVD_TP0

CPU_CFG<17>

CPU_CFG<11>

CPU_CFG<10>

CPU_TEST_BV1_BT1 CPU_TEST_BT71_BT69

CPU_TEST_BV3_BT3

TP_CPU_TEST_BV5

TP_CPU_RSVD<17>

TP_CPU_RSVD<16>

TP_CPU_TEST_BV68

CPU_TEST_BV71_BV69

CPU_THERMD_P CPU_THERMD_N

10 OF 132

9 OF 103

6

91

6

OUT

IN IN

IN

OUT

BI

OUT

IN

OUT

IN IN

IN

OUT

IN

OUT

IN

OUT OUT OUT

IN

OUT OUT OUT OUT

IN

BCLK_ITP

BCLK_ITP*

PEG_CLK

SM_RCOMP2

PM_EXT_TS1*

PRDY* PREQ*

THERMTRIP*

COMP1

COMP2

COMP3

COMP0

PROC_DETECT

PROCHOT*

PECI

CATERR*

RSTIN*

TAPPWRGOOD

VTTPWRGOOD

VCCPWRGOOD_0

SM_DRAMPWROK

VCCPWRGOOD_1

PM_SYNC

RESET_OBS*

BPM7*

BPM6*

BPM5*

BPM4*

BPM3*

BPM2*

BPM1*

BPM0*

TDO_M

DBR*

TDI_M

TDO

TDI

BCLK*

BCLK

TRST*

TMS

TCK

PM_EXT_TS0*

SM_RCOMP1

SM_RCOMP0

PEG_CLK*

DPLL_REF_SSCLK

DPLL_REF_SSCLK*

SM_DRAMRST*

PWR MANAGEMENTTHERMAL

JTAG & MBP

(SYM 2 OF 11)

MISC

DDR3

MISC

CLOCKS

IN

OUT OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(IPU)

(IPU) (IPU)

(IPU)

(IPD)

(IPU) (IPU)

(IPU)

(GND)

(IPU)

(IPD)

(IPU)

31

47 91

2

1

R1126

750

1/16W

1%

402

MF-LF

21

R1125

1.5K

1%

402

1/16W MF-LF

27

18 31 91

71 91

17 93

25 91

20 91

47 69 91

18 91

20 47 91

2

1

R1102

NO STUFF

402

1/16W MF-LF

5%

68

2

1

R1101

5%

68

MF-LF

1/16W

402

2

1

R1100

MF-LF

1/16W 402

1%

49.9

17 93

2

1

R1112

49.9

MF-LF

402

1%

1/16W

2

1

R1113

1% MF-LF

1/16W 402

49.9

2

1

R1110

20

MF-LF

1/16W

402

1%

2

1

R1111

20

1%

402

1/16W MF-LF

25 91

25

17 91

25

25 91

25 27 91

25 91

17 91

25 91

2

1

R1162

1%

100

MF-LF

1/16W

402

2

1

R1160

1%

MF-LF

1/16W

402

130

2

1

R1161

1%

24.9

402

1/16W MF-LF

2

1

R1150

MF-LF

5%

402

10K

1/16W

2

1

R1151

1/16W MF-LF

5%

402

10K

20 91

2

1

R1170

5%

51

MF-LF

1/16W

402

20 25 91

2

1

R1103

1K

5% MF-LF

402

1/16W

H15

AM7

Y67

P69

N65

N17

T70

T71

P71

T69

T67

Y70

BV40

BP39

BV33

BJ12

AM5

G3

N70

N67

M71

U69

U71

M17

AV64

AV66

J21

L21

N19

W4

Y2

W71

AD71 AC70 AD69 AE66

N61

M69

K69

J64

K62

K65

J62

J67

J69

J70

K71

AK8

AK7

U1000

OMIT

BGA

ARRANDALE

20 91

2

1

R1120

402

1K

5% MF-LF

1/16W

25 91

CPU Clock/Misc/JTAG

SYNC_MASTER=K18_MLB

SYNC_DATE=10/14/2009

PM_MEM_PWRGD

PPCPUVTT_S0

CPU_COMP3 CPU_COMP2

XDP_DBRESET_L

JTAG_CPU_TDO

XDP_CPUPWRGD

PM_SYNC

FSB_CPURST_L

CPU_COMP0

CPU_PROCHOT_L

CPU_PECI

PM_THRMTRIP_L

CPU_CATERR_L

XDP_BPM_L<6>

XDP_BPM_L<4>

PPCPUVTT_S0

PM_EXT_TS_L<0>

GFX_CLK120M_DPLLSS_N

CPU_MEM_RESET_L CPU_SM_RCOMP0

CPU_PWRGD

CPUVTTS0_PGOOD

CPU_SM_RCOMP2

CPU_SM_RCOMP1

PM_EXT_TS_L<1>

GFX_CLK120M_DPLLSS_P

FSB_CLK133M_ITP_N

FSB_CLK133M_CPU_N FSB_CLK133M_ITP_P

PCIE_CLK100M_CPU_P

XDP_PRDY_L XDP_PREQ_L

CPU_COMP1

PLT_RESET_LS1V1_L

XDP_BPM_L<7>

XDP_BPM_L<5>

XDP_BPM_L<0>

JTAG_GMCH_TDI

FSB_CLK133M_CPU_P

XDP_TMS

XDP_TCK

PCIE_CLK100M_CPU_N

PLT_RST_BUF_L

XDP_BPM_L<3>

XDP_BPM_L<2>

XDP_BPM_L<1>

JTAG_GMCH_TDO

JTAG_CPU_TDI

XDP_TRST_L

TP_CPU_SKTOCC_L

11 OF 132 10 OF 103

6 7

10 12 13 15 25 26 40 71 74

101

91

6 7

10 12 13 15 25 26 40 71 74

101

91

BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

OUT

BI

BI BI

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

OUT OUT OUT OUT OUT OUT OUT OUT

OUT OUT

OUT

OUT OUT

OUT

OUT OUT

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

OUT OUT OUT

OUT

OUT OUT

OUT

OUT OUT

OUT

OUT OUT

OUT OUT OUT OUT OUT OUT OUT OUT

BI BI BI BI BI

BI

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

SA_RAS* SA_WE*

SA_CAS*

SA_BS2

SA_BS1

SA_BS0

SA_DQ62 SA_DQ63

SA_DQ60 SA_DQ61

SA_DQ59

SA_DQ58

SA_DQ57

SA_DQ54

SA_DQ56

SA_DQ55

SA_DQ53

SA_DQ52

SA_DQ51

SA_DQ50

SA_DQ49

SA_DQ48

SA_DQ47

SA_DQ46

SA_DQ44 SA_DQ45

SA_DQ41 SA_DQ42 SA_DQ43

SA_DQ40

SA_DQ39

SA_DQ37

SA_DQ36

SA_DQ38

SA_DQ35

SA_DQ34

SA_DQ32

SA_DQ31

SA_DQ33

SA_DQ30

SA_DQ29

SA_DQ28

SA_DQ27

SA_DQ26

SA_DQ24 SA_DQ25

SA_DQ23

SA_DQ22

SA_DQ21

SA_DQ19 SA_DQ20

SA_DQ18

SA_DQ17

SA_DQ16

SA_DQ13

SA_DQ15

SA_DQ14

SA_DQ12

SA_DQ11

SA_DQ10

SA_DQ9

SA_DQ8

SA_DQ7

SA_DQ5 SA_DQ6

SA_DQ3 SA_DQ4

SA_DQ1 SA_DQ2

SA_DQ0

SA_MA15

SA_MA14

SA_MA13

SA_MA12

SA_MA11

SA_MA10

SA_MA9

SA_MA7 SA_MA8

SA_MA6

SA_MA5

SA_MA4

SA_MA3

SA_MA2

SA_MA1

SA_MA0

SA_DQS7

SA_DQS6

SA_DQS4 SA_DQS5

SA_DQS3

SA_DQS1 SA_DQS2

SA_DQS0

SA_DQS7*

SA_DQS6*

SA_DQS5*

SA_DQS4*

SA_DQS3*

SA_DQS2*

SA_DQS1*

SA_DQS0*

SA_DM7

SA_DM6

SA_DM5

SA_DM4

SA_DM3

SA_DM2

SA_DM1

SA_DM0

SA_ODT1

SA_ODT0

SA_CS1*

SA_CS0*

SA_CK1*

SA_CKE1

SA_CKE0

SA_CK1

SA_CK0

SA_CK0*

(SYM 3 OF 11)

DDR SYSTEM MEMORY A

SB_DQ0 SB_CK0 SB_DQ1

SB_CK0*

SB_DQ2

SB_CKE0

SB_DQ3 SB_DQ4

SB_CK1

SB_DQ5

SB_CK1*

SB_DQ6 SB_DQ7

SB_CKE1 SB_DQ8 SB_DQ9

SB_CS0* SB_DQ10 SB_CS1* SB_DQ11 SB_DQ12 SB_ODT0 SB_DQ13 SB_ODT1 SB_DQ14 SB_DQ15

SB_DM0

SB_DQ16

SB_DM1

SB_DQ17

SB_DM2

SB_DQ18

SB_DM3

SB_DQ19

SB_DM4

SB_DQ20

SB_DM5

SB_DQ21

SB_DM6

SB_DQ22

SB_DM7 SB_DQ23 SB_DQ24

SB_DQS0*

SB_DQ25

SB_DQS1*

SB_DQ26

SB_DQS2*

SB_DQ27

SB_DQS3*

SB_DQ28

SB_DQS4*

SB_DQ29

SB_DQS5*

SB_DQ30

SB_DQS6*

SB_DQ31

SB_DQS7* SB_DQ32 SB_DQ33 SB_DQS0 SB_DQ34 SB_DQS1 SB_DQ35 SB_DQS2 SB_DQ36 SB_DQS3 SB_DQ37 SB_DQS4 SB_DQ38 SB_DQS5 SB_DQ39 SB_DQS6 SB_DQ40 SB_DQS7 SB_DQ41 SB_DQ42

SB_MA0

SB_DQ43

SB_MA1

SB_DQ44

SB_MA2

SB_DQ45

SB_MA3

SB_DQ46

SB_MA4

SB_DQ47

SB_MA5

SB_DQ48

SB_MA6

SB_DQ49

SB_MA7

SB_DQ50

SB_MA8

SB_DQ51

SB_MA9 SB_DQ52 SB_MA10 SB_DQ53 SB_MA11 SB_DQ54 SB_MA12 SB_DQ55 SB_MA13 SB_DQ56 SB_MA14 SB_DQ57 SB_MA15 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

SB_BS0 SB_BS1 SB_BS2

SB_CAS* SB_RAS* SB_WE*

DDR SYSTEM MEMORY B

(SYM 4 OF 11)

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

29 92

28 29 92

29 92

28 92

29 92

28 29 92

29 92

28 29 92

29 92

28 92

28 29 92

29 92

28 92

29 92

29 30 92

29 92

30 92

29 30 92

29 92

29 30 92

29 92

29 30 92

29 92

30 92

OMIT

BGA

ARRANDALE

U1000

BT38 BH38 BF21

BK43

BM34 BP35

BK36 BH36

BF20

BK24

BH40 BJ47

BB10 BJ10 BM15 BN24 BG44 BG53 BN62 BH59

AT8 AT6

BK5

BH13

BF9 BF6 BK7 BN8

BN11

BN9 BG17 BK15

BB5

BK9 BG15 BH17 BK17 BN20 BN17 BK25 BH25 BJ20 BH21

BB9

BG24 BG25 BJ40 BM43 BF47 BF48 BN40 BH43 BN44 BN47

AV7

BN48 BN51 BH53 BJ55 BH48 BJ48 BM53 BN55 BF55 BN57

AV6

BN65 BJ61 BF57 BJ57 BK64 BK61 BJ63 BF64 BB64 BB66

BE6

BJ66 BF65 AY64 BC70

BE8 BF11 BE11

AY7

AY5

BJ5

BJ7

BL13

BN13

BN21

BL21

BK44

BH44

BH51

BK51

BM60

BP58

BE64

BE62

BT36 BP33

BH34 BH30 BJ28 BF40 BN28 BN25

BV36 BG34 BG32 BN32 BK32 BJ30 BN30 BF28

BF43 BL47

BL38 BF38

BGA

ARRANDALE

OMIT

U1000

BV43 BV41 BV24

BU46

BU33 BV34

BV38 BU39

BT26

BT24

BP46 BT43

BB4 BL4 BT13 BP22 BV47 BV57 BU65 BF67

BA2 AW2

BR6 BR8 BJ4 BK2

BU9 BV10 BR10 BT12 BT15 BV15

BD1

BV12 BP12 BV17 BU16 BP15 BU19 BV22 BT22 BP19 BV19

BE4

BV20 BT20 BT48 BV48 BV50 BP49 BT47 BV52 BV54 BT54

AY1

BP53 BU53 BT59 BT57 BP56 BT55 BU60 BV59 BV61 BP60

BC2

BR66 BR64 BR62 BT61 BN68 BL69 BJ71 BF70 BG71 BC67

BF2

BK70 BK67 BD71 BD69

BH2

BG4

BG1

BD4

BE2

BN4

BM3

BV13

BU12

BT17

BT19

BT50

BT52

BU56

BV55

BV62

BU63

BJ69

BG69

BT34 BP30

BU42 BU26 BT29 BT45 BV26 BU23

BV29 BU30 BV31 BT33 BT31 BP26 BV27 BT27

BV45 BU49

BT40 BT41

CPU DDR3 Interfaces

SYNC_MASTER=K17_REF

SYNC_DATE=04/29/2009

MEM_B_DQ<27>

MEM_B_DQ<0>

MEM_B_CLK_P<0>

MEM_B_DQ<1>

MEM_B_CLK_N<0>

MEM_B_DQ<2>

MEM_B_CKE<0>

MEM_B_DQ<3> MEM_B_DQ<4>

MEM_B_CLK_P<1>

MEM_B_DQ<5>

MEM_B_CLK_N<1>

MEM_B_DQ<6> MEM_B_DQ<7>

MEM_B_CKE<1> MEM_B_DQ<8> MEM_B_DQ<9>

MEM_B_CS_L<0> MEM_B_DQ<10>

MEM_B_CS_L<1> MEM_B_DQ<11> MEM_B_DQ<12> MEM_B_ODT<0> MEM_B_DQ<13> MEM_B_ODT<1> MEM_B_DQ<14> MEM_B_DQ<15>

MEM_B_DM<0> MEM_B_DQ<16>

MEM_B_DM<1> MEM_B_DQ<17>

MEM_B_DM<2> MEM_B_DQ<18>

MEM_B_DM<3> MEM_B_DQ<19>

MEM_B_DM<4> MEM_B_DQ<20>

MEM_B_DM<5> MEM_B_DQ<21>

MEM_B_DM<6> MEM_B_DQ<22>

MEM_B_DM<7> MEM_B_DQ<23> MEM_B_DQ<24>

MEM_B_DQS_N<0> MEM_B_DQ<25>

MEM_B_DQS_N<1> MEM_B_DQ<26>

MEM_B_DQS_N<2>

MEM_B_DQS_N<3> MEM_B_DQ<28>

MEM_B_DQS_N<4> MEM_B_DQ<29>

MEM_B_DQS_N<5> MEM_B_DQ<30>

MEM_B_DQS_N<6> MEM_B_DQ<31>

MEM_B_DQS_N<7> MEM_B_DQ<32> MEM_B_DQ<33>

MEM_B_DQS_P<0> MEM_B_DQ<34>

MEM_B_DQS_P<1> MEM_B_DQ<35>

MEM_B_DQS_P<2> MEM_B_DQ<36>

MEM_B_DQS_P<3> MEM_B_DQ<37>

MEM_B_DQS_P<4> MEM_B_DQ<38>

MEM_B_DQS_P<5> MEM_B_DQ<39>

MEM_B_DQS_P<6> MEM_B_DQ<40>

MEM_B_DQS_P<7> MEM_B_DQ<41> MEM_B_DQ<42>

MEM_B_A<0> MEM_B_DQ<43>

MEM_B_A<1> MEM_B_DQ<44>

MEM_B_A<2> MEM_B_DQ<45>

MEM_B_A<3> MEM_B_DQ<46>

MEM_B_A<4> MEM_B_DQ<47>

MEM_B_A<5> MEM_B_DQ<48>

MEM_B_A<6> MEM_B_DQ<49>

MEM_B_A<7> MEM_B_DQ<50>

MEM_B_A<8> MEM_B_DQ<51>

MEM_B_A<9> MEM_B_DQ<52>

MEM_B_A<10> MEM_B_DQ<53>

MEM_B_A<11> MEM_B_DQ<54>

MEM_B_A<12> MEM_B_DQ<55>

MEM_B_A<13> MEM_B_DQ<56>

MEM_B_A<14> MEM_B_DQ<57>

MEM_B_A<15> MEM_B_DQ<58> MEM_B_DQ<59> MEM_B_DQ<60> MEM_B_DQ<61> MEM_B_DQ<62> MEM_B_DQ<63>

MEM_B_BA<0> MEM_B_BA<1> MEM_B_BA<2>

MEM_B_CAS_L MEM_B_RAS_L MEM_B_WE_L

MEM_A_CLK_P<0>

MEM_A_DQ<4>

MEM_A_CS_L<1>

MEM_A_A<2>

MEM_A_CLK_N<0>

MEM_A_RAS_L MEM_A_WE_L

MEM_A_CAS_L

MEM_A_BA<2>

MEM_A_BA<1>

MEM_A_BA<0>

MEM_A_DQ<62> MEM_A_DQ<63>

MEM_A_DQ<60> MEM_A_DQ<61>

MEM_A_DQ<59>

MEM_A_DQ<58>

MEM_A_DQ<57>

MEM_A_DQ<54>

MEM_A_DQ<56>

MEM_A_DQ<55>

MEM_A_DQ<53>

MEM_A_DQ<52>

MEM_A_DQ<51>

MEM_A_DQ<50>

MEM_A_DQ<49>

MEM_A_DQ<48>

MEM_A_DQ<47>

MEM_A_DQ<46>

MEM_A_DQ<44> MEM_A_DQ<45>

MEM_A_DQ<41> MEM_A_DQ<42> MEM_A_DQ<43>

MEM_A_DQ<40>

MEM_A_DQ<39>

MEM_A_DQ<37>

MEM_A_DQ<36>

MEM_A_DQ<38>

MEM_A_DQ<35>

MEM_A_DQ<34>

MEM_A_DQ<32>

MEM_A_DQ<31>

MEM_A_DQ<33>

MEM_A_DQ<30>

MEM_A_DQ<29>

MEM_A_DQ<28>

MEM_A_DQ<27>

MEM_A_DQ<26>

MEM_A_DQ<24> MEM_A_DQ<25>

MEM_A_DQ<23>

MEM_A_DQ<22>

MEM_A_DQ<21>

MEM_A_DQ<19> MEM_A_DQ<20>

MEM_A_DQ<18>

MEM_A_DQ<17>

MEM_A_DQ<16>

MEM_A_DQ<13>

MEM_A_DQ<15>

MEM_A_DQ<14>

MEM_A_DQ<12>

MEM_A_DQ<11>

MEM_A_DQ<10>

MEM_A_DQ<9>

MEM_A_DQ<8>

MEM_A_DQ<7>

MEM_A_DQ<5> MEM_A_DQ<6>

MEM_A_DQ<3>

MEM_A_DQ<1> MEM_A_DQ<2>

MEM_A_DQ<0>

MEM_A_A<15>

MEM_A_A<14>

MEM_A_A<13>

MEM_A_A<12>

MEM_A_A<11>

MEM_A_A<10>

MEM_A_A<9>

MEM_A_A<7> MEM_A_A<8>

MEM_A_A<6>

MEM_A_A<5>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_A<1>

MEM_A_A<0>

MEM_A_DQS_P<7>

MEM_A_DQS_P<6>

MEM_A_DQS_P<4> MEM_A_DQS_P<5>

MEM_A_DQS_P<3>

MEM_A_DQS_P<1> MEM_A_DQS_P<2>

MEM_A_DQS_P<0>

MEM_A_DQS_N<7>

MEM_A_DQS_N<6>

MEM_A_DQS_N<5>

MEM_A_DQS_N<4>

MEM_A_DQS_N<3>

MEM_A_DQS_N<2>

MEM_A_DQS_N<1>

MEM_A_DQS_N<0>

MEM_A_DM<7>

MEM_A_DM<6>

MEM_A_DM<5>

MEM_A_DM<4>

MEM_A_DM<3>

MEM_A_DM<2>

MEM_A_DM<1>

MEM_A_DM<0>

MEM_A_ODT<1>

MEM_A_ODT<0>

MEM_A_CS_L<0>

MEM_A_CLK_N<1> MEM_A_CKE<1>

MEM_A_CKE<0>

MEM_A_CLK_P<1>

12 OF 132 11 OF 103

OUT OUT OUT OUT OUT OUT OUT

OUT

OUT OUT

IN

OUT

VCAP0_15

VCAP0_17

VCC_1 VCC_2 VCC_3 VCC_4 VCC_5

VCC_7

VCC_6

VCC_9

VCC_10

VCC_12

VCC_11

VCC_14

VCC_13

VCC_15

VCC_17

VCC_16

VCC_18 VCC_19 VCC_20 VCC_21 VCC_22

VCC_25

VCC_24

VCC_23

VCC_26 VCC_27

VCC_29 VCC_30

VCC_28

VCC_32

VCC_31

VCC_34

VCC_33

VCC_35

VCC_37

VCC_36

VCC_38

VCC_40

VCC_39

VCC_42

VCC_41

VCC_43 VCC_44 VCC_45 VCC_46 VCC_47

VCC_50

VCC_49

VCC_51 VCC_52 VCC_53

VCC_55

VCC_54

VCC_56

VCC_58

VCC_57

VCC_60

VCC_59

VCC_62

VCC_61

VCC_63 VCC_64 VCC_65 VCC_66 VCC_67 VCC_68 VCC_69 VCC_70 VCC_71 VCC_72 VCC_73 VCC_74 VCC_75 VCC_76 VCC_77 VCC_78

VCC_81

VCC_79 VCC_80

VCC_83

VCC_82

VCC_84 VCC_85 VCC_86 VCC_87

VCC_89

VCC_88

VCAP0_1 VCAP0_2

VCAP0_4

VCAP0_3

VCAP0_5 VCAP0_6 VCAP0_7 VCAP0_8 VCAP0_9

VCAP0_12

VCAP0_10 VCAP0_11

VCAP0_14

VCAP0_16

VCAP0_19

VCAP0_18

VCAP0_20 VCAP0_21 VCAP0_22 VCAP0_23 VCAP0_24 VCAP0_25 VCAP0_26 VCAP0_27

VCAP1_2

VCAP1_1

VCAP1_5

VCAP1_3 VCAP1_4

VCAP1_7

VCAP1_6

VCAP1_8

VCAP1_10

VCAP1_9

VCAP1_13

VCAP1_11 VCAP1_12

VCAP1_15

VCAP1_14

VCAP1_18

VCAP1_17

VCAP1_16

VCAP1_20

VCAP1_19

VCAP1_23

VCAP1_21 VCAP1_22

VCAP1_24 VCAP1_25

VCAP1_27

VCAP1_26

VCAP0_13

VCC_8

VCC_48

(SYM 8 OF 11)

CPU CORE SUPPLY

POWER

VSS_SENSE_VTT

VTT_SENSE

VSS_SENSE

VCC_SENSE

ISENSE

VID2 VID3 VID4

PSI*

VTT0_9

VTT0_22

VTT0_24

VTT0_23

VTT0_26

VTT0_25

VTT0_27 VTT0_28 VTT0_29 VTT0_30 VTT0_31 VTT0_32 VTT0_33 VTT0_34

VTT0_36

VTT0_35

VTT0_37 VTT0_38 VTT0_39 VTT0_40 VTT0_41 VTT0_42 VTT0_43 VTT0_44 VTT0_45 VTT0_46 VTT0_47 VTT0_48 VTT0_49 VTT0_50 VTT0_51 VTT0_52 VTT0_53 VTT0_54 VTT0_55 VTT0_56 VTT0_57 VTT0_58 VTT0_59

VTT0_62

VTT0_60 VTT0_61

VTT0_63 VTT0_64 VTT0_65

VTT0_67

VTT0_66

VTT0_68

VTT0_70

VTT0_69

VTT0_72

VTT0_71

VTT0_73

VTT0_4

VTT0_6

VTT0_5

VTT0_7 VTT0_8

VTT0_10 VTT0_11

VTT0_13

VTT0_12

VTT0_16

VTT0_15

VTT0_14

VTT0_17 VTT0_18 VTT0_19 VTT0_20 VTT0_21

VID5 VID6

VTT_SELECT1

PROC_DPRSLPVR

VTT0_1 VTT0_2 VTT0_3

VID1

VID0

VCCPLL1 VCCPLL2

VCCPLL4

VCCPLL3

VCCPLL5

VDDQ_CK1 VDDQ_CK2

1.8V

(SYM 6 OF 11)

1.1V RAIL POWER

CPU VIDS

SENSE LINES

POWER

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

VTT_SELECT: 1 = 1.05V, 0 = 1.1V

Do not connect to power supply,

Arrandale: 1.05V

(Controlled by VTT_SELECT pin)

Clarksfield: 1.1V

but provide bypass caps on PCB.

NOTE: VCAP1 is sourced by CPU

NOTE: VCAP0 is sourced by CPU Do not connect to power supply, but provide bypass caps on PCB.

8

15 91

8

15 91

8

15 91

8

15 91

8

15 91

8

15 91

8

15 91

8

91

15 69 91

71 91

50 69 91

2

1

R1301

1/16W

1%

100

402

MF-LF

PLACE_NEAR=U1000.F63:25.4MM

69 91

2

1

R1300

1/16W

1%

100

402

MF-LF

PLACE_NEAR=U1000.F64:25.4MM

2

1

R1305

1%

402

MF-LF

10

1/16W

PLACE_NEAR=U1000.N13:25.4MM

2

1

R1306

10

1/16W

1%

402

MF-LF

PLACE_NEAR=U1000.R12:25.4MM

AF42

A43

A47

A50

A54

A57

B42

B46

B49

B53

B56

AF44

B60

D43

D45

D47

D48

D50

D52

D54

D55

D57

AF46

D59

E42

E46

E50

E53

E57

E60

F55

G44

G51

AF48

G55

G60

H44

H51

H60

J55

K44

K51

K60

L55

AF50

M44

M51

M60

N42

N44

N48

N51

N55

P60

R41

AF51

R44

R48

R51

R55

U41

U44

U48

U51

U55

W41

AF53

W44

W48

W51

W55

AA41

AA44

AA48

AA51

AA55

AB41

AF55

AB44

AB48

AB51

AB55

AD41

AD44

AD48

AD51

AD55

AF41

AF57

AY39

AY42

AY46

BB37

BB41

BB44

BD37

AK39

AK42

AK46

AL39

AL42

AL46

AN39

AN42

BD41

AN46

AR37

AR41

AR44

AU37

AU41

AU44

AW39

AW42

AW46

BD44

AY50

AY53

AY57

BB48

BB51

BB55

BD48

AK50

AK53

AK57

AL50

AL53

AL57

AN50

AN53

BD51

AN57

AR48

AR51

AR55

AU48

AU51

AU55

AW50

AW53

AW57

BD55

U1000

OMIT

BGA

ARRANDALE

N13

AN1

AW35

AW60

AN9

AY10

R23

R24

AY60

R26

R28

R30

R32

R33

R35

U23

U24

U26

U28

BB59

U30

U32

U33

U35

W23

W24

W26

W28

W30

W32

BB60

W33

W35

AD30

AD32

AD33

AD35

AD37

AD39

AF30

AF32

BD59

AF33

AF35

AF37

AF39

AK33

AK35

AL12

AL14

AL15

AL17

BD60

AL59

AL60

AM10

AN12

AN14

AN15

AN17

AN33

AN35

AN59

BF59

AN60

AR12

AR59

AR60

AU12

AU59

AU60

AW12

AW14

AW33

BF60

R12

F63

D66

D64

B63

A62

D62

D61

A61

BB12

BB14

R37

R39

U37

W37

W39

F64

F68

F66

A41

U1000

ARRANDALE

BGA

OMIT

CPU Power (1 of 2)

SYNC_MASTER=K17_WFERRY

SYNC_DATE=06/09/2009

CPU_VCCSENSE_P

PPVCORE_S0_CPU_VCAP1

PPVCORE_S0_CPU

CPU_VID<0>

TP_CPU_VTT_SELECT

CPU_VID<6>

CPU_VID<5>

CPU_PSI_L

CPU_VID<4>

CPU_VCCSENSE_N

PP1V8_S0

PP1V5_S3_CPU_VCCDDR_CLK

MIN_LINE_WIDTH=0.4mm MIN_NECK_WIDTH=0.2mm VOLTAGE=1.5V

PPVCORE_S0_CPU_VCAP0

CPU_VTTSENSE_N

CPU_VTTSENSE_P

PPCPUVTT_S0

PM_DPRSLPVR

CPUIMVP_IMON

CPU_VID<3>

CPU_VID<2>

CPU_VID<1>

13 OF 132 12 OF 103

7

16

6 7

12 15 50 69

6 7

12 15 50 69

6 7

16 72 73 88

101

16

7

16

6 7

10 12 13 15 25 26 40 71 74

101

6 7

10 12 13 15 25 26 40 71 74

101

VAXG35

VTT1_7

VTT1_9 VTT1_10

VTT1_8

VTT1_5

VAXG3

VAXG2

VAXG1

VSSAXG_SENSE

VAXG_SENSE

VCAP2_19

VCAP2_17 VCAP2_18

VCAP2_16

VCAP2_14 VCAP2_15

VCAP2_12 VCAP2_13

VCAP2_11

VCAP2_10

VCAP2_9

VCAP2_8

VCAP2_6 VCAP2_7

VCAP2_5

VCAP2_4

VCAP2_3

VCAP2_1 VCAP2_2

VTT1_11

VTT1_6

VTT1_4

VTT1_3

VTT1_2

VTT1_1

VAXG37

VAXG36

VAXG33 VAXG34

VAXG32

VAXG31

VAXG30

VAXG27

VAXG29

VAXG28

VAXG25 VAXG26

VAXG23 VAXG24

VAXG22

VAXG20 VAXG21

VAXG19

VAXG17 VAXG18

VAXG14

VAXG16

VAXG15

VAXG13

VAXG12

VAXG11

VAXG10

VAXG9

VAXG8

VAXG7

VAXG6

VAXG5

VAXG4

VTT1_21

VTT1_20

VTT1_18 VTT1_19

VTT1_17

VTT1_16

VTT1_15

VTT1_14

VTT1_13

VTT1_12

VTT0_DDR9

VTT0_DDR8

VTT0_DDR7

VTT0_DDR6

VTT0_DDR5

VTT0_DDR4

VTT0_DDR3

VTT0_DDR2

VTT0_DDR1

VTT0_DDR

VDDQ36

VDDQ35

VDDQ34

VDDQ33

VDDQ31 VDDQ32

VDDQ30

VDDQ29

VDDQ28

VDDQ27

VDDQ26

VDDQ24 VDDQ25

VDDQ23

VDDQ21 VDDQ22

VDDQ20

VDDQ19

VDDQ18

VDDQ17

VDDQ16

VDDQ15

VDDQ13 VDDQ14

VDDQ12

VDDQ11

VDDQ10

VDDQ9

VDDQ8

VDDQ7

VDDQ6

VDDQ5

VDDQ4

VDDQ3

VDDQ2

GFX_IMON

VDDQ1

GFX_DPRSLPVR

GFX_VR_EN

GFX_VID6

GFX_VID5

GFX_VID4

GFX_VID3

GFX_VID2

GFX_VID1

GFX_VID0

(SYM 7 OF 11)

POWER

PEG & DMI

LINES

SENSE

GRAPHICS VIDS

GRAPHICS

DDR3 -1.5 V RAILS

OUT

OUT OUT

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Do not connect to power supply, but provide bypass caps on PCB.

NOTE: VCAP2 is sourced by CPU

OMIT

ARRANDALE

BGA

U1000

AL71

AL69

AF71 AG67 AG70 AH71 AN71 AM67 AM70

AH69

AN32

AL30 AL28 AL26 AL24 AL23 AL21 AL19 AK14 AK12 AJ10

AN30

AH14 AH12 AF28 AF26 AF24 AF23 AF21 AF19 AF17 AF15

AN28

AF14 AD28 AD26 AD24 AD23 AD21 AD19 AD17

AN26 AN24 AN23 AN21 AN19 AL32

AF12

AK62

AB60 AB59 AA60 AA59

W60 W59 U60 U59 R60 R59

AK60 AK59 AH60 AH59 AF60 AF59 AD60 AD59

BU40

BG43 BF16 BF15 BD35 BD33 BD32 BD30 BD28 BD26 BD24

BU35

BD23 BD21 BD19 BD17 BD15 BB35 BB33 BB32 BB30 BB28

BU28

BB26 BB24 BB23 BB21 BB19 BB17 BB15

BN38 BM25 BL30 BJ38 BH32 BH28

AF10

AW32 AW30 AW28 AW26 AW24 AW23 AW21 AW19 AW17 AW15

W21

R19 R17

AD15 AD14 AD12 AB12 AA12 W17 W15 W14

W19

W12 R15

U21 U19 U17 U15 U14 U12 R21

8

91

PLACE_NEAR=U1000.AF10:25.4MM

402

1%

100

1/16W MF-LF

R1401

1

2

MF-LF

402

1/16W

4.7K

5%

R1405

1

2

70 91

PLACE_NEAR=U1000.AF12:25.4MM

100

1/16W

1%

402

MF-LF

R1400

1

2

70 91

8

91

8

91

8

91

8

91

8

91

8

91

SYNC_DATE=06/09/2009

SYNC_MASTER=K17_WFERRY

CPU Power (2 of 2)

PPVCORE_S0_GFX

PPCPUVTT_S0

PPVCORE_S0_CPU_VCAP2

GFX_VID<3>

GFX_VID<5> GFX_VID<6>

GFX_VID<0> GFX_VID<1>

GFX_VSENSE_N

PPVCORE_S0_GFX

GFX_VSENSE_P

GFXIMVP_IMON

GFX_VID<2>

GFX_DPRSLPVR

GFX_VR_EN

GFX_VID<4>

PPCPUVTT_S0

PP1V1R1V05_S0_CPU_VTT0_DDR

PPCPUDDR_ISNS

14 OF 132 13 OF 103

7

13 24 50 70

6 7

10 12 13 15 25 26 40 71 74

101

7

24

7

13 24 50 70

6 7

10 12 13 15 25 26 40 71 74

101

15

7

16 31 57

VSS77

VSS11

VSS16

VSS110 VSS111

VSS113

VSS112

VSS114

VSS116

VSS115

VSS118

VSS117

VSS119

VSS121

VSS120

VSS122

VSS124

VSS123

VSS125 VSS126 VSS127 VSS128 VSS129

VSS131

VSS130

VSS133

VSS132

VSS134

VSS136

VSS135

VSS137 VSS138 VSS139

VSS141

VSS140

VSS142 VSS143 VSS144

VSS147

VSS145 VSS146

VSS149

VSS148

VSS150

VSS1 VSS2 VSS3

VSS5

VSS4

VSS6 VSS7 VSS8

VSS10

VSS9

VSS13

VSS12

VSS14 VSS15

VSS17 VSS18 VSS19 VSS20 VSS21

VSS23

VSS22

VSS25

VSS24

VSS26

VSS28

VSS27

VSS29 VSS30 VSS31

VSS33

VSS32

VSS34 VSS35 VSS36

VSS39

VSS37 VSS38

VSS41

VSS40

VSS43

VSS42

VSS44

VSS46

VSS45

VSS47

VSS49

VSS48

VSS51

VSS50

VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62

VSS64

VSS63

VSS66

VSS65

VSS67

VSS69

VSS68

VSS71

VSS70

VSS72 VSS73 VSS74 VSS75

VSS76

VSS80

VSS78 VSS79

VSS82

VSS81

VSS85

VSS83 VSS84

VSS87

VSS86

VSS90

VSS88 VSS89

VSS92

VSS91

VSS93

VSS95

VSS94

VSS96 VSS97 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106

VSS108

VSS107

VSS109

(SYM 9 OF 11)

VSS215 VSS216

VSS214

VSS213

VSS212

VSS210 VSS211

VSS207 VSS208 VSS209

VSS205 VSS206

VSS204

VSS203

VSS202

VSS200 VSS201

VSS199

VSS197 VSS198

VSS195 VSS196

VSS194

VSS192 VSS193

VSS190 VSS191

VSS189

VSS187 VSS188

VSS185

VSS184

VSS186

VSS182 VSS183

VSS181

VSS180

VSS179

VSS177 VSS178

VSS176

VSS175

VSS174

VSS172 VSS173

VSS171

VSS169 VSS170

VSS166 VSS167 VSS168

VSS164 VSS165

VSS163

VSS162

VSS161

VSS159 VSS160

VSS158

VSS156 VSS157

VSS154 VSS155

VSS153

VSS152

VSS151

VSS227

VSS226

VSS228

VSS230

VSS229

VSS231

VSS239 VSS240

VSS232 VSS233 VSS234 VSS235 VSS236

VSS238

VSS237

VSS241

VSS250 VSS251

VSS249

VSS247

VSS242 VSS243

VSS246

VSS245

VSS244

VSS248

VSS261

VSS260

VSS259

VSS253

VSS252

VSS254

VSS256

VSS255

VSS257 VSS258

VSS270 VSS271

VSS268

VSS264

VSS263

VSS262

VSS265 VSS266 VSS267

VSS269

VSS272

VSS280 VSS281

VSS273 VSS274

VSS276

VSS275

VSS277 VSS278 VSS279

VSS282

VSS292

VSS290 VSS291

VSS288

VSS284

VSS283

VSS286

VSS285

VSS287

VSS289

VSS294

VSS293

VSS296

VSS295

VSS297 VSS298 VSS299 VSS300

VSS217 VSS218

VSS220

VSS219

VSS222

VSS221

VSS223

VSS225

VSS224

(SYM 10 OF 11)

VSS358

VSS363

VSS301

VSS429

VSS428

VSS427

VSS426

VSS423

VSS425

VSS424

VSS421 VSS422

VSS420

VSS418 VSS419

VSS416 VSS417

VSS414

VSS413

VSS415

VSS411 VSS412

VSS408 VSS409 VSS410

VSS406 VSS407

VSS405

VSS403 VSS404

VSS400

VSS402

VSS401

VSS398 VSS399

VSS397

VSS396

VSS395

VSS393 VSS394

VSS392

VSS391

VSS390

VSS388 VSS389

VSS387

VSS385 VSS386

VSS383 VSS384

VSS382

VSS380 VSS381

VSS377

VSS379

VSS378

VSS375 VSS376

VSS372 VSS373 VSS374

VSS371

VSS370

VSS367

VSS369

VSS368

VSS366

VSS365

VSS364

VSS362

VSS360 VSS361

VSS357

VSS359

VSS355 VSS356

VSS352 VSS353 VSS354

VSS351

VSS350

VSS347

VSS349

VSS348

VSS345 VSS346

VSS342

VSS344

VSS343

VSS340 VSS341

VSS339

VSS337 VSS338

VSS334 VSS335 VSS336

VSS332 VSS333

VSS330 VSS331

VSS329

VSS327 VSS328

VSS326

VSS325

VSS324

VSS322 VSS323

VSS321

VSS319 VSS320

VSS318

VSS317

VSS316

VSS314 VSS315

VSS313

VSS312

VSS311

VSS309 VSS310

VSS308

VSS307

VSS306

VSS305

VSS304

VSS303

VSS302

VSS432 VSS433

VSS431

VSS430

(SYM 11 OF 11)

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

AY4

AY8

AY12

AY14

AY15

AY17

AY19

AY21

AY23

AY24

BU25

AY26

AY28

AY30

AY32

AY33

AY35

AY37

AY41

AY44

AY48

BU32

AY51

AY55

AY59

AY62

AY66

AY71

BA70

BB1

BB7

BB39

BU37

BB42

BB46

BB50

BB53

BB57

BB62

BB71

BD14

BD39

BD42

BU44

BD46

BD50

BD53

BD57

BE1

BE9

BE65

BE70

BF8

BF13

BU48

BF30

BF62

BG36

BG51

BH15

BH20

BH24

BH47

BH55

BH57

BU51

BH70

BJ1

BJ9

BJ21

BJ64

BK10

BK34

BK53

BK60

BK63

BU55

BL20

BL28

BL40

BL48

BL55

BL57

BM17

BM24

BM32

BM44

BU58

BM51

BM70

BN6

BN64

AR21

BP42

AR23

AR24

AR26

AR28

AR30

AR32

AR33

AR35

AR39

AR42

BU7

AR46

AR50

AR53

AR57

AR62

AT10

AT64

AU4

AU14

AU15

BU11

AU17

AU19

AU21

AU23

AU24

AU26

AU28

AU30

AU32

AU33

BU14

AU35

AU39

AU42

AU46

AU50

AU53

AU57

AU62

AU70

AV1

BU18

AV9

AW37

AW41

AW44

AW48

AW51

AW55

AW59

AW62

AW67

BU21

BU62

U1000

BGA

ARRANDALE

OMIT

AA30

AA32

AA33

AA35

AA37

AA39

AA42

AA46

AA50

AA53

AA57

AA62

AA64

AA66

AB9

AB14

AB15

AB17

AB19

AB21

AB23

AB24

AB26

AB28

AB30

AB32

AB33

AB35

AB37

AB39

AB42

AB46

AB50

AB53

AB57

AB62

AB70

AC1

AC5

AC10

AC64

AC67

AD4

AD42

AD46

AD50

AD53

AD57

AD62

AE64

AE70

AF1

AF62

AF69

AG6

AG9

AG64

AH4

AH15

AH17

AH19

AH21

C68

AH23

E5

AH39

AH24

A64

BN1

AH26

A66

AH41

AH28

E68

BN71

AH30

E69

AH42

AH32

F71

BR3

AH33

H71

AH44

AH35

R14

BR68

AH37

BL1

AH46

BL71

BR69

AH48

BT68

AH50

BV64

AH51

BV66

AH53

AH55

AH57

AH62

AJ70

AK15

AK17

AK19

AK21

AK23

AK24

AK26

AK28

AK30

AK32

AK37

AK41

AK44

AK48

AK51

AK55

AK64

AK70

AL1

AL33

AL35

AL37

AL41

AL44

AL48

AL51

AL55

AL62

AM8

AM64

AN4

AN5

AN37

AN41

AN44

AN48

AN51

AN55

AN62

AP64

AP70

AR1

AR4

AR14

AR15

AR17

AR19

U1000

OMIT

BGA

ARRANDALE

B40

A8

A12

A15

A19

A22

A26

A29

A33

A36

A40

A45

A48

A52

A55

A59

B44

B48

B51

B55

B58

B62

B65

D6

D10

D13

D17

D20

D24

D27

D31

D34

D38

D41

E12

E16

E30

E33

E37

F4

F20

F28

F47

F48

F61

G15

G20

G24

G30

G43

G47

G48

G53

G57

G70

H1

H36

H43

H53

J9

J40

J47

J48

J57

J65

K4

K6

K11

K17

K25

K32

K34

K36

K43

K53

K64

L13

L47

L48

L57

L70

M1

M36

M42

M53

N15

N21

N30

N46

N50

N53

N57

N63

P4

R5

R42

R46

R50

R53

R57

R62

R70

T1

U4

U9

U39

U42

U46

U50

U53

U57

U62

U64

V70

W1

W6

W42

W46

W50

W53

W57

W62

W69

AA4

AA14

AA15

AA17

AA19

AA21

AA23

AA24

AA26

AA28

U1000

OMIT

BGA

ARRANDALE

CPU Grounds

SYNC_MASTER=K17_REF

SYNC_DATE=04/29/2009

15 OF 132 14 OF 103

OUT OUT OUT OUT OUT OUT OUT OUT OUT

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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REVISION

DRAWING NUMBER

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PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PLACEMENT_NOTE (C1664-C1687):

3x 330uF 6 mOhm, 4x 22uF 0805, 7x 10uF 0603, 24x 1uF 0402

VTT (CPU Uncore) DECOUPLING

PLACEMENT_NOTE (C1625-C1634):

PLACEMENT_NOTE (C1653-C1656):

VTT0_DDR DECOUPLING

Instead call out appropriate BOM GROUP defined in tables above.

IMAX @ 900mV

22.5

40A

VID[2:0] = Reserved (111) VID[5:3] = GPU Gain Setting (See below)

NOTE: BOM Configurations should not call out CPUPOCnU/D BOMOPTIONs directly.

18

CPU Gain Setting

90A

70A

20A 30A

001

Intel recommends all option straps should be provided in layout

CPU Power On Configuration (POC) Straps

Equivalent Gain

45 30

15

12.857 10

PSI# = Reserved (0)

DPRSLPVR = 1 - IMVP-6.5 compliant controller

VID[6] = Reserved (0)

000

111

110

101

100

011

010

50A 60A

PLACEMENT_NOTE (C1635-C1648):

PLACEMENT_NOTE (C1695-C1697):

PLACEMENT_NOTE (C1657-C1663):

3x 1uF 0402

PLACEMENT_NOTE (C1600-C1624):

Design recommendations from Calpella Small Form Factor Design Guide Rev 1.5 (doc #407364) table 2-34 and Calpella Small Form Factor Schematic Check List Rev 1.1 (doc #395914) table 3.26.

CPU VCore HF and Bulk Decoupling

3x 470uF 4.5mOhm, 1x 330uF, 15x 22uF 0603, 25x 1uF 0402

MF-LF

1/16W

5%

402

1K

R1600

1

2

Place near inductors on bottom side.

NO STUFF

C1641

22UF

20%

6.3V

2

X5R-CERM 603

1

MF-LF

1/16W

5%

402

1K

R1602

1

2

MF-LF

1/16W

5%

402

1K

R1601

1

2

MF-LF

1/16W

5%

402

1K

CPUPOC3U

R1603

1

2

MF-LF

1/16W

5%

402

1K

NO STUFF

R1606

1

2

MF-LF

1/16W

5%

402

1K

R1607

1

2

5%

402

1K

CPUPOC4U

MF-LF

1/16W

R1604

1

2

MF-LF

1/16W

5%

402

1K

CPUPOC5U

R1605

1

2

MF-LF

402

1K

5%

1/16W

R1616

1

2

1K

402

5% 1/16W MF-LF

NO STUFF

R1617

1

2

MF-LF

1/16W

5%

1K

CPUPOC5D

402

R1615

1

2

MF-LF

1/16W

CPUPOC4D

402

5%

1K

R1614

1

2

NO STUFF

5%

1K

1/16W MF-LF

402

R1612

1

2

MF-LF

1/16W

5%

402

1K

CPUPOC3D

R1613

1

2

NO STUFF

MF-LF

402

1K

1/16W

5%

R1610

1

2

MF-LF

1/16W

5%

402

1K

NO STUFF

R1611

1

2

1K

402

5% 1/16W MF-LF

NO STUFF

R1608

1

2

1K

5% 1/16W MF-LF

402

R1618

1

2

8

12 91

8

12 91

8

12 91

8

12 91

8

12 91

8

12 91

8

12 91

12 69 91

6.3V X5R-CERM 603

Place near inductors on bottom side.

1

2

22UF

20%

C1635

NO STUFF

1UF

Place on bottom side of U1000..

10% X5R

16V 402

1

2

C1600 C1607

2

1

402

16V X5R

1UF

10%

C1606

1UF

402

2

1

16V X5R

10%

C1605

2

1

402

16V X5R

1UF

10%

C1604

1UF

2

1

402

16V X5R

10%

C1611

2

1

402

16V X5R

1UF

10%

C1610

2

1

402

16V X5R

1UF

10%

C1609

2

1

402

16V X5R

1UF

10%

C1608

2

1

402

16V X5R

1UF

10%

C1624

2

1

402

16V X5R

1UF

10%

C1623

2

1

402

16V X5R

10%

1UF

C1622

2

1

402

16V X5R

1UF

10%

C1621

2

1

402

16V X5R

1UF

10%

C1601

2

1

402

16V X5R

1UF

10%

Place on bottom side of U1000..

C1620

2

1

402

16V X5R

1UF

10%

C1619

16V 402

2

1

X5R

1UF

10%

C1618

2

1

402

16V X5R

1UF

10%

C1617

2

1

402

16V X5R

1UF

10%

2

1

402

16V X5R

1UF

10%

C1616C1615

2

1

402

16V X5R

1UF

10%

C1614

2

1

402

16V X5R

1UF

10%

C1613

2

1

402

16V X5R

1UF

10%

C1612

2

1

402

16V X5R

1UF

10%

Place on bottom side of U1000.

1UF

C1675

1

2

402

X5R

10V

10%

C1674

Place on bottom side of U1000.

1UF

1

2

402

X5R

10V

10%

Place on bottom side of U1000.

1UF

C1687

1

2

402

X5R

10V

10%

Place on bottom side of U1000.

1UF

C1686

1

2

402

X5R

10V

10%

Place on bottom side of U1000.

1UF

C1673

1

2

402

X5R

10V

10%

1UF

Place on bottom side of U1000.

C1685

1

2

402

X5R

10V

10%

Place on bottom side of U1000.

1UF

C1672

1

2

10% 402

X5R

10V

Place on bottom side of U1000.

1UF

C1671

1

2

402

X5R

10% 10V

Place on bottom side of U1000.

1UF

C1684

1

2

402

X5R

10V

10%

Place on bottom side of U1000.

1UF

C1683

1

2

402

X5R

10V

10%

Place on bottom side of U1000.

1UF

C1670

1

2

10% X5R

402

10V

C1682

402

Place on bottom side of U1000.

1UF

1

2

X5R

10V

10%

Place on bottom side of U1000.

1UF

C1669

1

2

402

X5R

10V

10%

C1681

Place on bottom side of U1000.

1UF

1

2

402

X5R

10V

10%

Place on bottom side of U1000.

1UF

C1668

1

2

402

X5R

10V

10%

Place on bottom side of U1000.

1UF

C1680

1

2

402

X5R

10V

10%

Place on bottom side of U1000.

1UF

C1667

1

2

402

X5R

10V

10%

Place on bottom side of U1000.

1UF

C1666

1

2

402

X5R

10V

10%

6.3V

22UF

603

Place near inductors on bottom side.

1

2

C1643

X5R-CERM

20%

Place on bottom side of U1000.

1UF

C1679

1

2

402

X5R

10V

10%

Place on bottom side of U1000.

1UF

C1678

1

2

402

X5R

10V

10%

Place on bottom side of U1000.

C1665

1

2

402

X5R

10V

1UF

10%

Place on bottom side of U1000.

1UF

C1677

1

2

402

X5R

10% 10V

10V

C1664

Place on bottom side of U1000.

1UF

1

2

10% X5R

402

2

1

Place on bottom side of U1000.

1UF

C1676

402

X5R

10% 10V

Place on bottom side of U1000.

1UF

C1697

1

2

402

X5R

10V

10%

Place on bottom side of U1000.

1UF

C1696

1

2

402

X5R

10V

10%

20%

603

6.3V

Place near inductors on bottom side.

1

2

X5R-CERM

C1644

22UF

Place on bottom side of U1000.

1UF

C1695

1

2

402

X5R

10V

10%

21

L1695

0603

30-OHM-5A

C1633

2

1

22UF

603

X5R-CERM

6.3V

20%

Place near U1000 on bottom side.

22UF

C1629

6.3V

2

1

603

X5R-CERM

20%

X5R-CERM

6.3V

20%

2

1

C1626

22UF

603

Place near U1000 on bottom side.

NO STUFF

C1637

Place near inductors on bottom side.

2

1

603

6.3V X5R-CERM

22UF

20%

C1638

Place near inductors on bottom side.

2

1

603

6.3V

20%

22UF

X5R-CERM

Place near inductors on bottom side.

2

1

603

6.3V X5R-CERM

20%

C1640

22UF

20%

Place near inductors on bottom side.

2

1

603

C1645

X5R-CERM

6.3V

22UF

20%

22UF

Place near inductors on bottom side.

2

1

X5R-CERM

6.3V 603

C1647

C1691

1

2

22UF

6.3V 603

X5R-CERM

20%

2

1

C1694

22UF

20%

6.3V X5R-CERM 603

20%

6.3V X5R-CERM 603

2

1

C1698

22UF

C1699

1

2

603

X5R-CERM

6.3V

20%

NO STUFF

C16A0

1

2

CASE-B2

11V ELEC

62UF

20%

NO STUFF

CASE-B2

ELEC

20%

C16A1

11V

62UF

1

2

C16A2

NO STUFF

1

2

CASE-B2

11V ELEC

62UF

20%

NO STUFF

C16A3

1

2

CASE-B2

11V ELEC

62UF

20%

NO STUFF

C16A4

1

2

CASE-B2

11V ELEC

62UF

20%

C1649

3 2

1

D2T-SM2

POLY-TANT

2.0V

20%

330UF

C1627

603

6.3V

20%

2

22UF

X5R-CERM

Place near U1000 on bottom side.

1

C1602

2

1

402

16V X5R

1UF

10%

Place on bottom side of U1000..

1

NO STUFF

C1628

22UF

X5R-CERM

20%

Place near U1000 on bottom side.

2

6.3V 603

C1603

Place on bottom side of U1000..

2

1

402

16V X5R

1UF

10%

X5R-CERM 603

Place near inductors on bottom side.

C1639

1

22UF

20%

6.3V

2

NO STUFF

C1634

2

1

22UF

X5R-CERM

6.3V

20% 603

20%

6.3V X5R-CERM 603

Place near inductors on bottom side.

C1646

1

2

22UF

NO STUFF

NO STUFF 22UF

603

X5R-CERM

6.3V

Place near U1000 on bottom side.

1

2

C1630

20%

NO STUFF

22UF

6.3V X5R-CERM 603

2

Place near U1000 on bottom side.

C1631

1

20%

22UF

C1648

NO STUFF

2

1

6.3V X5R-CERM 603

NO STUFF

C1632

22UF

6.3V X5R-CERM 603

20%

Place near U1000 on bottom side.

1

2

D2T-SM

POLY-TANT

C1650

1

23

2.0V

20%

470UF-4MOHM 470UF-4MOHM

C1651

D2T-SM

20%

2.0V POLY-TANT

1

23

D2T-SM

2.0V POLY-TANT

20%

C1652

1

23

470UF-4MOHM

X5R-CERM

22UF

C1653

6.3V

Place on bottom side of U1000.

603

20%

1

2

Place on bottom side of U1000.

X5R-CERM 603

20%

6.3V

C1654

1

2

22UF

Place on bottom side of U1000.

X5R-CERM 603

20%

6.3V

C1655

1

2

22UF

Place on bottom side of U1000.

X5R-CERM 603

20%

6.3V

1

2

22UF

C1656

Place on bottom side of U1000..

603

X5R

10UF

20%

6.3V

C1663

1

2

603

X5R

10UF

20%

6.3V

Place on bottom side of U1000..

C1662

1

2

603

X5R

10UF

20%

6.3V

Place on bottom side of U1000..

C1661

1

2

603

X5R

10UF

20%

6.3V

Place on bottom side of U1000..

C1660

1

2

603

X5R

10UF

6.3V

20%

Place on bottom side of U1000..

C1659

1

2

X5R 603

10UF

6.3V

20%

Place on bottom side of U1000..

C1658

1

2

10UF

603

6.3V

20%

Place on bottom side of U1000..

X5R

C1657

1

2

C1688

330UF

D2T-SM2

20%

2.0V POLY-TANT

3 2

1

D2T-SM2

POLY-TANT

2.0V

20%

330UF

C1689

1

23

330UF

D2T-SM2

POLY-TANT

2.0V

20%

C1690

1

23

SYNC_MASTER=K17_WFERRY

CPU Non-GFX Decoupling (1 of 2)

SYNC_DATE=06/09/2009

CPUPOC_IMAX_0_20

CPUPOC3D,CPUPOC4D,CPUPOC5U

CPUPOC_IMAX_20_30

CPUPOC3D,CPUPOC4U,CPUPOC5D

CPUPOC_IMAX_DIS

CPUPOC3D,CPUPOC4D,CPUPOC5D

CPUPOC3U,CPUPOC4U,CPUPOC5U

CPUPOC_IMAX_70_90

CPUPOC3U,CPUPOC4D,CPUPOC5U

CPUPOC_IMAX_50_60

CPUPOC3U,CPUPOC4U,CPUPOC5D

CPUPOC_IMAX_60_70

CPUPOC3D,CPUPOC4U,CPUPOC5U

CPUPOC_IMAX_30_40 CPUPOC_IMAX_40_50

CPUPOC3U,CPUPOC4D,CPUPOC5D

PPVCORE_S0_CPU

PP1V1R1V05_S0_CPU_VTT0_DDR

VOLTAGE=1.1V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

CPU_PSI_L

PM_DPRSLPVR

CPU_VID<4>

CPU_VID<3>

CPU_VID<2>

CPU_VID<1>

CPU_VID<0>

PPCPUVTT_S0

CPU_VID<5> CPU_VID<6>

PPCPUVTT_S0

16 OF 132 15 OF 103

6 7

12 50 69

13

6 7

10 12 13 15 25 26 40 71 74

101

6 7

10 12 13 15

25 26 40 71 74

101

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

VCAP1 (CPU BSC Package) DECOUPLING

12x 1uF 0402

PLACEMENT_NOTE (C1712-C1723):

Memory (CPU VCCDDR) DECOUPLING

5x 1uF 0402

NOTE: 19x 1uF 0402 caps per Apple SI for CMD and CNTRL lines.

1x 1uF 0402

actor Schematic Check List Rev 1.1 (doc #395914) table 3.26.

Design recommendations from Calpella Small Form Factor Design Guide Rev 1.5 (doc #407364) table 2-34 and Calpella Small Form F

DDR Clock (CPU VDDQ_CK) DECOUPLING

1x 22uF 0805, 1x 4.7uF 0603

PLL (CPU VCCSFR) DECOUPLING

NOTE: 3x 330uF 6 mOhm caps to be shared between CPU and SO-DIMMs. 2x330uF on CSA73. DG recommends 2x 22uF at SO_DIMM not provided. Decoupling caps at SO-DIMMs on CSA 29 and CSA 31.

PLACEMENT_NOTE (C1700-C1711):

12x 1uF 0402

VCAP0 (CPU BSC Package) DECOUPLING

10V 402

1UF

10% X5R

C1745

1

2

1UF

X5R

10%

402

10V

C1744

1

2

10V 402

1UF

10% X5R

C1743

1

2

1UF

X5R

10%

402

10V

C1742

1

2

10V 402

1UF

10% X5R

C1741

1

2

1UF

10% X5R

402

10V

C1740

1

2

X5R 402

1UF

10% 10V

C1739

1

2

1UF

X5R

10%

402

10V

C1738

1

2

10V 402

1UF

10% X5R

1

2

C1737

1UF

X5R

10%

402

10V

C1736

1

2

10V 402

1UF

10% X5R

C1735

1

2

1UF

X5R

10%

402

10V

C1753

1

2

10V 402

1UF

10% X5R

C1752

1

2

1UF

10% X5R

402

10V

C1751

1

2

X5R 402

1UF

10% 10V

C1750

1

2

1UF

X5R

10%

402

10V

C1749

1

2

402

X5R

10V

1UF

10%

C1748

1

2

1UF

X5R

10%

402

10V

C1747

1

2

402

10V

1UF

10% X5R

C1746

1

2

21

L1734

0603

30-OHM-5A

C1723

2

1

402

16V X5R

1UF

10%

Place on bottom side of U1000.

C1722

2

1

402

1UF

16V X5R

10%

Place on bottom side of U1000.

C1721

2

1

402

16V X5R

1UF

10%

Place on bottom side of U1000.

C1720

2

1

402

16V X5R

1UF

10%

Place on bottom side of U1000.

C1719

2

1

402

16V X5R

1UF

10%

Place on bottom side of U1000.

C1718

2

1

402

Place on bottom side of U1000.

16V X5R

1UF

10%

C1717

2

1

402

Place on bottom side of U1000.

16V X5R

1UF

10%

C1716

2

1

402

Place on bottom side of U1000.

16V X5R

1UF

10%

C1715

2

1

402

Place on bottom side of U1000.

16V X5R

1UF

10%

C1714

2

1

402

Place on bottom side of U1000.

16V X5R

1UF

10%

C1713

2

1

402

Place on bottom side of U1000.

16V X5R

1UF

10%

C1712

2

1

402

Place on bottom side of U1000.

16V X5R

1UF

10%

C1711

2

1

402

16V X5R

1UF

10%

Place on bottom side of U1000.

C1710

2

1

402

1UF

16V X5R

10%

Place on bottom side of U1000.

C1709

2

1

402

1UF

16V X5R

10%

Place on bottom side of U1000.

C1708

2

1

402

16V X5R

1UF

10%

Place on bottom side of U1000.

C1707

2

1

402

16V X5R

1UF

10%

Place on bottom side of U1000.

C1706

2

1

402

1UF

16V X5R

10%

Place on bottom side of U1000.

C1705

2

1

402

1UF

16V X5R

10%

Place on bottom side of U1000.

C1704

2

1

402

16V X5R

1UF

10%

Place on bottom side of U1000.

C1703

2

1

402

16V X5R

1UF

10%

Place on bottom side of U1000.

C1702

2

1

402

1UF

16V X5R

10%

Place on bottom side of U1000.

C1701

2

1

402

1UF

16V X5R

10%

Place on bottom side of U1000.

C1700

1UF

2

1

402

16V X5R

10%

Place on bottom side of U1000.

1UF

10V X5R 402

1

2

10%

C1728

X5R 402

10V

C1727

1

2

1UF

10%

10V 402

1UF

10% X5R

C1726

1

2

1UF

10% 10V

402

X5R

C1725

1

2

X5R

1UF

10%

402

10V

C1724

1

2

X5R-CERM 603

10%

6.3V

4.7UF

C1733

1

2

805

CERM-X5R

22uF

6.3V

20%

C1732

1

2

10V 402

10% X5R

1UF

C1734

1

2

POLY-TANT

2.0V

20%

D2T-SM2

330UF

C1729

1

23

SYNC_DATE=06/24/2009

CPU Non-GFX Decoupling (2 of 2)

SYNC_MASTER=K17_REF

PPCPUDDR_ISNS

PP1V8_S0

PP1V5_S3_CPU_VCCDDR_CLK

PPCPUDDR_ISNS

PPVCORE_S0_CPU_VCAP1

PPVCORE_S0_CPU_VCAP0

17 OF 132 16 OF 103

7

13 16 31 57

6 7

12 72 73 88

101

12

7

13 16 31 57

7

12

7

12

IN

OUT

IN

BI BI BI BI

OUT

BI

IN

IN OUT OUT

IN

IN OUT OUT

IN IN

OUT

OUT OUT

OUT

IN

OUT

OUT OUT

IN

OUT OUT

IN

OUT OUT

OUT

IN

OUT

IN

IN IN

IN

OUT

BI

OUT

BI

IN IN OUT OUT

FWH4/LFRAME*

SATA1GP/GPIO19

INTVRMEN

SATAICOMPI

SATAICOMPO

SATA0TXN

SATA0RXN

SATA0TXP

SATA0RXP

SATA1TXP

SATA1RXP

SATA1RXN

SATA1TXN

SATA2TXN

SATA2RXN

SATA2TXP

SATA2RXP

SATA5TXN

SATA5RXN

SATA4TXN

SATA4RXN

SATA3TXN

SATA3RXN

SATA5TXP

SATA5RXP

SATA4TXP

SATA4RXP

SATA3TXP

SATA3RXP

FWH1/LAD1

LDRQ0*

LDRQ1*/GPIO23

SERIRQ

FWH3/LAD3

FWH2/LAD2

FWH0/LAD0

SATALED*

SATA0GP/GPIO21

HDA_SYNC

SPKR

SPI_MISO

SPI_MOSI

SPI_CS1*

SPI_CS0*

SPI_CLK

JTAG_TDO

JTAG_RST*

JTAG_TDI

JTAG_TMS

JTAG_TCK

HDA_DOCK_RST*/GPIO13

HDA_DOCK_EN*/GPIO33

HDA_SDO

HDA_SDIN2 HDA_SDIN3

HDA_SDIN1

HDA_SDIN0

HDA_RST*

HDA_BCLK

INTRUDER*

SRTCRST*

RTCRST*

RTCX2

RTCX1

(1 OF 10)

RTC

LPC

IHDAJTAG

SPI

SATA

CLKOUT_DMI_N CLKOUT_DMI_P

CLKOUT_DP_N/CLKOUT_BCLK1_N CLKOUT_DP_P/CLKOUT_BCLK1_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_BCLK_N CLKIN_BCLK_P

CLKIN_DOT_96N CLKIN_DOT_96P

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

CLKOUT_PEG_A_P

CLKOUT_PEG_A_N

PEG_A_CLKRQ*/GPIO47

CL_RST1*

CL_DATA1

CL_CLK1

SML1DATA/GPIO75

SML1CLK/GPIO58

SML1ALERT*/GPIO74

SML0DATA

SML0CLK

SML0ALERT*/GPIO60

SMBDATA

CLKOUTFLEX1/GPIO65

CLKOUTFLEX0/GPIO64

XCLK_RCOMP

CLKOUTFLEX2/GPIO66

CLKOUTFLEX3/GPIO67

CLKOUT_PCIE0N CLKOUT_PCIE0P

CLKOUT_PCIE1N

CLKOUT_PCIE2N

PCIECLKRQ1*/GPIO18

PCIECLKRQ2*/GPIO20

CLKOUT_PCIE2P

CLKOUT_PCIE3P

CLKOUT_PCIE3N

PCIECLKRQ3*/GPIO25

CLKOUT_PCIE4N

PCIECLKRQ4*/GPIO26

CLKOUT_PCIE4P

CLKOUT_PCIE5P

CLKOUT_PCIE5N

PCIECLKRQ5*/GPIO44

CLKOUT_PEG_B_P

CLKOUT_PEG_B_N

PEG_B_CLKRQ*/GPIO56

PETP8

PETN8

PERP8

PERN8

PETP7

PETN7

PERP7

PERN7

PETP6

PERP6 PETN6

PETP5

PERN6

PERP5

PERN5

PETN5

PETP4

PETN4

PERP4

PERN4

PETP3

PETN3

PERP3

PERN3

PETP2

PERP2 PETN2

PETP1

PERN2

PERP1

PERN1

PETN1

SMBCLK

SMBALERT*/GPIO11

CLKIN_SATA_N/CKSSCD_N CLKIN_SATA_P/CKSSCD_P

REFCLK14IN

CLKOUT_PCIE1P

PCIECLKRQ0*/GPIO73

FROM CLK BUFFER

(2 OF 10)

SMBUS

C-LINKPEG

CLOCK

FLEX

PCI-E*

OUT OUT

IN

OUT

BI

OUT

IN

IN IN

OUT OUT

OUT

IN

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

CLKOUTFLEX3 also supports 48 MHz.

Default: 24.576 MHz (unsupported)

Default: 48 MHz

Default: 0V

All 4 CLKOUTFLEX outputs support

(IPD)

port multipliers

support FIS-based

(IPU)

Unused

(IPD)

Not available on

eSATA

SSD

ODD

HDD

(IPD)

(IPU)

(IPD)

(IPU)

(IPD)

(IPU)

(IPD)

Default: 14.31818 MHz

33.333 MHz and 14.31818 MHz,

Unused

(IPU/NO)

Only ports 4 & 5

(IPD)

(IPU)

some IbexPeak SKUs

(IPU)

27

59 94

17 25

48 94

17 25

48 94

6

46 48 88 94

6

46 48 88 94

6

46 48 88 94

6

46 48 88 94

6

46 48 88 94

6

46 48

42 93

37 94

6

33 94

6

33 94

39 94

37 94

33 94

39 94

37 94

17 37

37 94

33 94

17 25 33

39 94

17 25 40

10 91

75 94

8

17 88

10 93

26 93

27 93

27

49 94

6

25 26 28 30

32 34 42 48 49

64 94

6

25 26 28 30

32 34 42 48 49 64

94

6

34 94

6

34 94

R1800

330K

402

MF-LF

1/16W

5%

1

2

R1801

1/16W MF-LF

1M

402

5%

1

2

R1802

5%

20K

402

1/16W MF-LF

1

2

R1803

2

20K

402

5% 1/16W MF-LF

1

X5R

10V

2

10%

1UF

402

C1803

1

2

10V X5R 402

1UF

10%

C1802

1

R1830

1%

402

MF-LF

37.4

1/16W

1

2

R1820

10K

1/16W

5% MF-LF

402

1

2

J4

BA2

AY1

AV1

AK11

P1

A16

IBEX_PEAK_M

FCBGA

OMIT

U1800

D33 B33 C32 A32

C34

A30

H32 J30

C30

G30 F30 E32 F32

B29

D29

A14

M3

K1

J2

K3

A34 F34

C14

B13 D13

Y9

AK7 AK6

AK9

V1

AH6 AH5 AH9 AH8

AF11 AF9 AF7 AF6

AH3 AH1 AF3 AF1

AD9 AD8 AD6 AD5

AD3 AD1 AB3 AB1

AF15

AF16

T3

AB9

AV3

AY3

D17

AU30

FCBGA

OMIT

IBEX_PEAK_M

U1800

T13

T11

T9

AP3 AP1

AW24 BA24

F18 E18

J42

AH13 AH12

AN4 AN2

AT1 AT3

AK48 AK47

AM43 AM45

AM47 AM48

AH42 AH41

AM51 AM53

AJ50 AJ52

AD43 AD45

AK53 AK51

T45

P43

T42

N50

P9

U4

N4

A8

M9

H6

H1

P13

BG30

AW30

BA32

BF33

BA34

AT34

BG34

BJ30

BA30

AT30

BB32

BH33

AW34

AU34

BJ34

BF29

BC30

AU32

BD32

BG32

BC34

AU36

BG36

BH29

BD30

AV32

BE32

BJ32

BD34

AV36

BJ36

P41

B9

H14 C8

J14

C6 G8

M14

E10 G12

AF38

AH51 AH53

34 94

17 34

R1890

MF-LF

1/16W

402

1%

90.9

1

2

R1810

MF-LF

1/16W

5%

402

33

1 2

R1811

33

402

5% 1/16W MF-LF

1 2

R1812

33

402

5% 1/16W MF-LF

1 2

R1813

402

MF-LF

1/16W

5%

33

1 2

59 94

49 94

8

93

8

93

8

93

8

93

17 46

17 37

17 25 42

17 25

17

103

6

17 46

R1853

10K

MF-LF

4025%

1/16W

1 2

R1854

10K

5%

1/16W

402

MF-LF

1 2

R1855

10K

MF-LF

402

1/16W

5%

1 2

R1852

402

10K

MF-LF1/16W

5%

1 2

R1851

1/16W

402

MF-LF

10K

5%

1 2

MF-LF

402

R1850

1/16W

10K

5%

1 2

R1880

10K

402

MF-LF1/16W

5%

1 2

R1860

100K

21

5%

1/16W

402

MF-LF

R1870

10K

MF-LF

402

1/16W

5%

1 2

R1871

10K

MF-LF

402

1/16W

5%

1 2

R1872

10K

402

MF-LF1/16W

5%

1 2

R1898

402

10K

5%

1/16W MF-LF

1 2

R1897

1/16W

5% 402

MF-LF

10K

1 2

R1896

MF-LF

5%

1/16W

402

10K

1 2

R1895

10K

MF-LF

402

1/16W

5%

1 2

MF-LF

R1840

1/16W

5% 402

10K

1 2

MF-LF

R1841

10K

402

1/16W

5%

1 2

1/16W

R1816

10K

5% 402

MF-LF

1 2

1/16W

R1815

5% 402

MF-LF

10K

21

R1828

1/16W

402

51

MF-LF

5%

1

2

R1826

XDP_PCH

402

1/16W MF-LF

5%

51

1

2

R1827

XDP_PCH

5% MF-LF

1/16W 402

51

1

2

R1825

XDP_PCH

51

MF-LF

402

1/16W

5%

1

2

1 2

402

2.2K

5%

1/16W MF-LF

R1899

PCH SATA/PCIE/CLK/LPC/SPI

SYNC_DATE=08/24/2009

SYNC_MASTER=K17_REF

SPI_CS0_R_L

NC_PCIE_PE5_D2RN NC_PCIE_PE5_D2RP NC_PCIE_PE5_R2D_CN

NC_PCIE_PE6_D2RN

PP1V05_S0_PCH

PCH_INTRUDER_L

SATA_ODD_D2R_N SATA_ODD_D2R_P

TP_SPI_CS1_L

SPI_MISO

HDA_SDOUT_R

HDA_RST_L

HDA_RST_R_L

HDA_SDOUT

HDA_SDOUT_R

HDA_SYNC

HDA_SYNC_R

HDA_BIT_CLK

HDA_BIT_CLK_R

TP_SATA_EXTA_R2D_C_N

NC_SATA_C_D2RN

TP_LPC_DREQ0_L

PCH_SML0ALERT_L SML_PCH_0_CLK

SML_PCH_0_DATA

PCH_SML1ALERT_L

PCIE_CLK100M_FW_P

PCIE_CLK100M_FW_N

PCIE_CLK100M_ENET_N

NC_PCIE_PE8_D2RP

NC_PCIE_PE7_R2D_CP

SMBUS_PCH_CLK SMBUS_PCH_DATA

PCH_CLK33M_PCIIN

PCH_CLK25M_XTALIN PCH_CLK25M_XTALOUT

HDA_BIT_CLK_R

NC_SATA_SSD2_D2RP

PCIE_CLK100M_AP_N

PCIE_CLK100M_ENET_P

SMC_WAKE_SCI_L

NC_PCIE_PE6_R2D_CP

NC_PCIE_PE6_D2RP

FW_CLKREQ_L

NC_PCIE_CLK100M_PE4N

PCIE_EXCARD_D2R_P

NC_PCIE_CLK100M_PE5N

NC_SATA_SSD2_R2D_CN NC_SATA_SSD2_R2D_CP

NC_SATA_SSD2_D2RN

TP_PCIE_CLK100M_PEBP

PCH_INTVRMEN_L

PCIE_CLK100M_EXCARD_P

NC_PCIE_PE8_D2RN

BRCRYPT_RESET

MLB_RAM_VENDOR

PCH_CLK100M_SATA_P

PCH_CLK14P3M_REFCLK

MLB_RAM_SIZE

PP1V05_S0_PCH

PCH_CLK96M_DOT_P

TP_CLINK_RESET_L

TP_CLINK_DATA

TP_CLINK_CLK

PCH_CLK100M_SATA_N

PCIE_EXCARD_R2D_C_P

NC_PCIE_PE6_R2D_CN

NC_PCIE_PE7_D2RN NC_PCIE_PE7_D2RP NC_PCIE_PE7_R2D_CN

NC_PCIE_PE8_R2D_CP

NC_PCIE_CLK100M_PE4P

PCIE_CLK100M_EXCARD_N

LPC_SERIRQ

SATA_HDD_R2D_C_P

SML_PCH_1_CLK SML_PCH_1_DATA

TP_SATA_EXTA_D2R_N

NC_SATA_D_R2D_CN

PCH_PEB_CLKREQ_L

ENET_CLKREQ_L

PCIE_CLK100M_AP_P

PCH_PE4_CLKREQ_L

TP_PCIE_CLK100M_PEBN

PCH_INTVRMEN_L

HDA_RST_R_L

NC_HDA_SDIN1 NC_HDA_SDIN2

PCH_CLK32K_RTCX2

PCH_CLK32K_RTCX1

SPI_DESCRIPTOR_OVERRIDE_L ENET_ENERGY_DET

JTAG_PCH_TCK JTAG_PCH_TMS

SATARDRVR_A_EN

PCH_SPKR

HDA_SYNC_R

SATA_ODD_R2D_C_N

NC_SATA_D_R2D_CP

TP_SATA_EXTA_D2R_P

TP_PCH_SATALED_L

PCH_INTRUDER_L

NC_HDA_SDIN3

LPC_AD<2> LPC_AD<3>

LPC_FRAME_L

SATA_HDD_R2D_C_N

SATA_ODD_R2D_C_P

NC_SATA_C_R2D_CN

NC_SATA_D_D2RN

TP_SATA_EXTA_R2D_C_P

GFX_CLK120M_DPLLSS_P

PCH_CLK96M_DOT_N

GFX_CLK120M_DPLLSS_N

PCIE_CLK100M_CPU_P

FSB_CLK133M_PCH_P

FSB_CLK133M_PCH_N

PCIE_CLK100M_PCH_P

PCIE_CLK100M_PCH_N

PCIE_CLK100M_CPU_N

PEG_CLK100M_P

PEG_CLK100M_N

PEG_CLKREQ_L

NC_SATA_C_D2RP

SATARDRVR_A_EN

AP_CLKREQ_L

PCH_SML1ALERT_L

ARB_DETECT

MLB_RAM_VENDOR

JTAG_PCH_TDO JTAG_PCH_TCK

JTAG_PCH_TMS

PCH_SRTCRST_L

SATARDRVR_B_EN

AP_CLKREQ_L

BRCRYPT_PWR_EN

NC_PCIE_CLK100M_PE5P

EXCARD_CLKREQ_L

BRCRYPT_RESET

PEG_CLKREQ_L

SMC_WAKE_SCI_L

EXCARD_CLKREQ_L

FW_CLKREQ_L

NC_PCIE_PE5_R2D_CP

PCH_SATAICOMP

NC_SATA_C_R2D_CP

NC_SATA_D_D2RP

TP_LPC_DREQ1_L

PP3V3_S0_PCH

LPC_AD<0> LPC_AD<1>

PCIE_FW_R2D_C_P

PCIE_FW_R2D_C_N

PCIE_EXCARD_R2D_C_N

PCIE_EXCARD_D2R_N

PCIE_FW_D2R_P

JTAG_PCH_TDI

NC_PCIE_PE8_R2D_CN

PCH_XCLK_RCOMP

ARB_DETECT

PCH_SML0ALERT_L

BRCRYPT_PWR_EN

PCH_PEB_CLKREQ_L

PCH_PE4_CLKREQ_L

RTC_RESET_L

SATA_HDD_D2R_P

SATA_HDD_D2R_N

PCIE_FW_D2R_N

PCIE_AP_R2D_C_P

PCIE_AP_R2D_C_N

PCIE_AP_D2R_P

PCIE_AP_D2R_N

PCIE_ENET_R2D_C_P

PCIE_ENET_R2D_C_N

PCIE_ENET_D2R_P

PCIE_ENET_D2R_N

RTC_RESET_L

HDA_SDIN0

PCH_SRTCRST_L

MLB_RAM_SIZE

PP3V42_G3H

PCH_SPKR

PP3V3_S5_PCH

JTAG_PCH_TDI JTAG_PCH_TDO TP_JTAG_PCH_TRST_L

PP3V3_S3 PP3V3_S0_PCH

SPI_MOSI_R

SPI_CLK_R

PP1V05_S5

ENET_CLKREQ_L

SATARDRVR_B_EN

ENET_ENERGY_DET

SPI_DESCRIPTOR_OVERRIDE_L

18 OF 132 17 OF 103

6

17 18 21 23 24

101

17

17 94

6

17

6

17 94

6

17

6

17

103

17

17 18 21 23 24

101

6

17

17 94

6

17

17 94

6

17

6 6

6

17 25 42

17 25 33

17

17 25

17

6

17

103

8

17 88

17 46

17 34

17 25 40

6

17 18 19 20 21 23 24

101

17 25

6

17

103

17

6 7

21 23 43 45

46 47 48 49 50 51

54 65 66 74

17

18 19 20 21 23

101

6 7

20 31 32 33 34 35 36 49 50 51 54 55

56 72 74 88

102 103

17 18 19 20 21 23 24

101

7

72

17 37

17 25

17 37

17 46

IN IN

IN

OUT

OUT OUT

IN IN

OUT OUT

OUT OUT OUT OUT

OUT

OUT OUT

OUT

OUT BI

BI BI

IN

OUT OUT

OUT

BI

OUT OUT

OUT

IN

BI

OUT

BI

OUT

IN

FDI_RXN0

DMI3RXN

RI*

BATLOW*/GPIO72

ACPRESENT/GPIO31

PWRBTN*

SUS_PWR_ACK/GPIO30

RSMRST*

LAN_RST*

DRAMPWROK

MEPWROK

PWROK

SYS_PWROK

SYS_RESET*

SLP_M*

SLP_S4*

SLP_S3*

SUSCLK/GPIO62

SLP_S5*/GPIO63

CLKRUN*/GPIO32

SUS_STAT*/GPIO61

WAKE*

DMI_ZCOMP DMI_IRCOMP

FDI_FSYNC1

FDI_FSYNC0

FDI_LSYNC0 FDI_LSYNC1

DMI3TXP

DMI2TXP

DMI0TXP DMI1TXP

DMI3TXN

DMI2TXN

DMI1TXN

DMI0TXN

DMI3RXP

DMI2RXP

DMI0RXP DMI1RXP

FDI_INT

FDI_RXP7

FDI_RXP6

FDI_RXP5

FDI_RXP4

FDI_RXP1 FDI_RXP2 FDI_RXP3

FDI_RXP0

FDI_RXN7

FDI_RXN6

FDI_RXN5

FDI_RXN4

FDI_RXN3

FDI_RXN2

FDI_RXN1

DMI2RXN

DMI1RXN

DMI0RXN

SLP_LAN*

PMSYNCH

TP23

(3 OF 10)

DMI

FDI

SYSTEM POWER

MANAGEMENT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

CRT_IRTN

DAC_IREF

CRT_VSYNC

CRT_HSYNC

CRT_DDC_CLK CRT_DDC_DATA

CRT_RED

CRT_GREEN

CRT_BLUE

DDPD_3N DDPD_3P

DDPD_2P

DDPD_2N

DDPD_1P

DDPD_1N

DDPD_0N DDPD_0P

DDPD_HPD

DDPD_CTRLDATA

DDPD_CTRLCLK

DDPC_3P

DDPC_2P DDPC_3N

DDPC_2N

DDPC_1P

DDPC_1N

DDPC_0N DDPC_0P

DDPC_HPD

DDPC_CTRLDATA

DDPC_CTRLCLK

DDPB_3N

DDPB_2P

DDPB_3P

DDPB_2N

DDPB_1P

DDPB_0P DDPB_1N

DDPB_0N

DDPB_HPD

SDVO_CTRLDATA

SDVO_CTRLCLK

LVDSB_DATA3

LVDSB_DATA2

LVDSB_DATA1

LVDSB_DATA0

LVDSB_DATA3*

LVDSB_DATA2*

LVDSB_CLK

LVDSB_CLK*

LVDSA_DATA3

LVDSA_DATA1 LVDSA_DATA2

LVDSA_DATA3*

LVDSA_DATA1*

LVDSA_DATA0*

LVDSA_CLK

LVDSA_CLK*

LVD_VREFH

LVD_IBG LVD_VBG

L_CTRL_DATA

L_CTRL_CLK

L_DDC_DATA

L_DDC_CLK

L_BKLTCTL

L_BKLTEN L_VDD_EN

LVD_VREFL

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_INTN SDVO_INTP

DDPB_AUXP

DDPB_AUXN

DDPC_AUXN DDPC_AUXP

DDPD_AUXN DDPD_AUXP

LVDSB_DATA1*

LVDSB_DATA0*

LVDSA_DATA0

LVDSA_DATA2*

DIGITAL DISPLAY INTERFACE

CRT

LVDS

(4 OF 10)

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(IPU)

(IPD)

(IPU)

(IPD)

(IPU)

(IPD)

0.5% recommended, Intel okay with 5% when CRTDAC not used.

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

88 93

6 8

93

6 8

93

88 93

8

93

88 93

8

93

88 93

8

93

88 93

8

93

8

88

8

88

6 8

85

2

1

R1950

1/16W MF-LF 402

1%

2.37K

8

85 93

8

85 93

8

85

8

81 85

8

81 85

8

2

1

R1951

1K

402

MF-LF

1/16W

5%

2

1

R1900

402

1% 1/16W MF-LF

49.9

6

18 27 33 34

6

18 46 48

47 94

46 47

31 43 46 47 73 74

6

31 46 74 86

10 91

18

10 31 91

18 46

25 46

46 47 74

18 46

27

6

27 46

J12

N2

T6

M6

F3

P8

M1

E4

H7

P12

K8

F6

C16

F14

B17

P5

BJ10

K5

A10

BD12

BB14

BD14

AW16

BG16

BC16

BF17

BB18

BC12

BA14

BE14

BA16

BJ16

BD16

BH17

BA18

BG14

BJ12

BJ14

BH13

BF13

D9

BH25 BF25

BD18

BE18

BG20

BJ20

BC20

BD20

BA20

AW20

BH21

BF21

BG22

BJ22

BD22

BE22

BD24

BC24

Y1

A6

P7

U1800

IBEX_PEAK_M

FCBGA

OMIT

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

BG46

BJ46

BG48

BJ48

BH45

BF45

T53

T51

AT53

AT51

AU52

AU50

AT49

AT48

AY53

AY51

AP48 AP47

AV47

AV48

AY48

AY49

BA52

BA50

BB47

BB48

AV53 AV51

AT42

AT43

AP41

AP39

T47

Y45

AB48

V48

AB46

T48

Y48

AT38

U52

U50

BD46

BC46

BD36

BE36

BH37

BF37

BG38

BJ38

BG40

BJ40

AV40

AB49

Y49

BD44

BE44

BA36

BB36

BC38

BD38

BH41

BF41

BD40

BE40

AU38

BJ44

BG44

BA38

AW38

BA40

BB40

BG42

BJ42

BC42

BD42

AD48

Y51

AD53

AB51

Y53

AB53

V53

V51

AA52

U1800

FCBGA

IBEX_PEAK_M

OMIT

6

18 46 48

2

1

R1905

1/16W

1%

10K

402

MF-LF

2

1

R1920

10K

402

1/16W MF-LF

5%

2

1

R1921

5% MF-LF

1/16W 402

10K

2

1

R1930

10K

402

1/16W MF-LF

5%

2

1

R1931

5% MF-LF

1/16W 402

10K

2

1

R1925

10K

402

1/16W MF-LF

5%

2

1

R1906

10K

402

1/16W MF-LF

5%

PCH DMI/FDI/Graphics

SYNC_MASTER=K17_WFERRY

SYNC_DATE=06/09/2009

PCH_DAC_IREF

NC_LVDS_IG_B_DATAP<3>

LVDS_IG_B_DATA_P<2>

FDI_DATA_P<3>

FDI_DATA_N<7>

FDI_FSYNC<0> FDI_FSYNC<1>

NC_SDVO_TVCLKINN

LVDS_IG_A_DATA_P<1>

FDI_LSYNC<1>

PM_SYNC

NC_DP_IG_C_AUXN

NC_DP_IG_C_CTRL_DATA

NC_DP_IG_C_CTRL_CLK

DP_IG_B_ML_P<3>

DP_IG_B_ML_N<3>

NC_LVDS_IG_B_DATAN<3>

PM_SLP_S3_L

PP3V3_S5_PCH PP1V05_S0_PCH

DP_IG_B_ML_N<1>

NC_DP_IG_C_MLP<2>

NC_SDVO_STALLN NC_SDVO_STALLP

NC_CRT_IG_HSYNC

NC_CRT_IG_DDC_DATA

NC_CRT_IG_DDC_CLK

NC_CRT_IG_GREEN

NC_CRT_IG_BLUE

LVDS_IG_B_DATA_P<1>

LVDS_IG_B_DATA_P<0>

LVDS_IG_B_DATA_N<1> LVDS_IG_B_DATA_N<2>

LVDS_IG_B_DATA_N<0>

NC_LVDS_IG_A_DATAP<3>

TP_LVDS_IG_B_CLKN

LVDS_IG_A_DATA_N<2>

LVDS_IG_A_DATA_N<0>

LVDS_IG_A_CLK_P

LVDS_IG_A_CLK_N

NC_DP_IG_D_AUXP

NC_DP_IG_D_AUXN

NC_DP_IG_C_AUXP

DP_IG_AUX_CH_N DP_IG_AUX_CH_P

NC_SDVO_INTP

NC_SDVO_INTN

LVDS_IG_PANEL_PWR

LVDS_IG_DDC_DATA NC_LVDS_IG_CTRL_CLK

NC_LVDS_IG_CTRL_DATA

NC_PCH_LVDS_VBG

DP_IG_DDC_CLK DP_IG_DDC_DATA

DP_IG_HPD DP_IG_B_ML_N<0>

DP_IG_B_ML_P<0>

DP_IG_B_ML_P<2>

NC_DP_IG_C_MLP<0>

NC_DP_IG_C_MLN<0>

NC_DP_IG_C_MLN<1> NC_DP_IG_C_MLP<1> NC_DP_IG_C_MLN<2>

NC_DP_IG_D_CTRL_CLK NC_DP_IG_D_CTRL_DATA

NC_DP_IG_D_HPD

NC_DP_IG_D_MLN<1>

NC_DP_IG_D_MLN<2> NC_DP_IG_D_MLP<2>

NC_DP_IG_D_MLP<3>

NC_DP_IG_D_MLN<3>

TP_PM_SLP_DSW_L

FDI_DATA_N<1>

FDI_DATA_N<4>

FDI_DATA_N<6>

FDI_DATA_P<5>

FDI_DATA_P<7>

FDI_INT

TP_PM_SLP_M_L

FDI_DATA_N<0>

NC_CRT_IG_VSYNC

LPC_PWRDWN_L

MAKE_BASE=TRUE

PCH_LVDS_IBG

PM_BATLOW_L

SMC_ADAPTER_EN

PM_SUS_PWR_ACK PM_PWRBTN_L

PM_RSMRST_L

PM_MEM_PWRGD

PM_SYSRST_L

DMI_S2N_P<3>

DMI_S2N_P<2>

DMI_S2N_N<3>

DMI_S2N_N<2>

DMI_S2N_N<0>

DMI_N2S_P<2>

DMI_N2S_P<1>

DMI_N2S_N<3>

DMI_N2S_N<2>

DMI_N2S_N<0> DMI_N2S_N<1>

TP_SLP_LAN_L

FDI_LSYNC<0>

PM_CLKRUN_L

PCIE_WAKE_L

FDI_DATA_P<2>

FDI_DATA_P<0>

DMI_N2S_P<0>

DMI_N2S_P<3>

FDI_DATA_N<5>

FDI_DATA_P<4>

FDI_DATA_P<6>

PM_CLK32K_SUSCLK

PM_SLP_S4_L

PM_SLP_S5_L

NC_CRT_IG_RED

PM_CLKRUN_L

PM_SUS_PWR_ACK

PP3V3_S0_PCH

PM_BATLOW_L PCIE_WAKE_L

PP3V3_S5_PCH

PM_RSMRST_L

PM_PCH_PWRGD

PCH_LAN_RST_L

NC_DP_IG_D_MLP<1>

DMI_S2N_P<1>

DMI_S2N_N<1>

LVDS_IG_DDC_CLK

PCH_RI_L

TP_LVDS_IG_BKL_PWM

NC_SDVO_TVCLKINP

NC_DP_IG_D_MLN<0> NC_DP_IG_D_MLP<0>

DP_IG_B_ML_P<1>

LVDS_IG_A_DATA_P<0>

NC_LVDS_IG_A_DATAN<3>

FDI_DATA_P<1>

FDI_DATA_N<3>

FDI_DATA_N<2>

NC_DP_IG_C_MLP<3>

NC_DP_IG_C_MLN<3>

TP_LVDS_IG_B_CLKP

NC_DP_IG_C_HPD

LVDS_IG_A_DATA_N<1>

LVDS_IG_BKL_ON

DP_IG_B_ML_N<2>

LVDS_IG_A_DATA_P<2>

DMI_S2N_P<0>

PCH_DMI_COMP

19 OF 132 18 OF 103

6

17 18 19 20 21 23

101

17 21 23 24

101

6

18 46 48

6

18 46 48

18

17 19 20 21 23 24

101

18 46

6

18 27 33 34

17 18 19 20 21 23

101

18 46

6

BI

OUT OUT

OUT

IN

OC7*/GPIO14

OC6*/GPIO10

OC5*/GPIO9

OC4*/GPIO43

OC3*/GPIO42

OC1*/GPIO40

OC0*/GPIO59

USBRBIAS

USBRBIAS*

USBP13N

USBP12N

USBP11N

USBP10N

USBP9N

USBP8N

USBP7N

USBP6N

USBP5N

USBP4N

USBP3N

USBP2N

USBP1N

USBP0N

USBP13P

USBP12P

USBP11P

USBP10P

USBP8P

USBP9P

USBP7P

USBP6P

USBP5P

USBP4P

USBP3P

USBP2P

USBP1P

USBP0P

AD2

NV_WE_CK1*

NV_WE_CK0*

NV_WR1_RE*

NV_RB*

NV_WR0_RE*

NV_RCOMP

NV_CLE

NV_ALE

NV_DQ15/NV_IO15

NV_DQ13/NV_IO13 NV_DQ14/NV_IO14

NV_DQ10/NV_IO10 NV_DQ11/NV_IO11 NV_DQ12/NV_IO12

NV_DQ8/NV_IO8 NV_DQ9/NV_IO9

NV_DQ7/NV_IO7

NV_DQ6/NV_IO6

NV_DQ5/NV_IO5

NV_DQ3/NV_IO3 NV_DQ4/NV_IO4

NV_DQ1/NV_IO1 NV_DQ2/NV_IO2

NV_DQ0/NV_IO0

NV_DQS0 NV_DQS1

NV_CE2* NV_CE3*

NV_CE1*

NV_CE0*

AD9

AD3

AD20

AD28 AD29

SERR* PERR*

GNT1*/GPIO51

REQ1*/GPIO50

PIRQC* PIRQD*

REQ0*

AD30

AD21 AD22

PIRQG*/GPIO4 PIRQH*/GPIO5

PCIRST*

AD0 AD1

AD4 AD5 AD6 AD7 AD8

AD10 AD11 AD12 AD13 AD14

AD24 AD25 AD26

CLKOUT_PCI2

C/BE0*

C/BE2* C/BE3*

DEVSEL* FRAME*

GNT0*

GNT2*/GPIO53 GNT3*/GPIO55

IRDY* PAR

PIRQA* PIRQB*

PIRQE*/GPIO2 PIRQF*/GPIO3

PLOCK*

PME*

REQ2*/GPIO52 REQ3*/GPIO54

STOP* TRDY*

AD15 AD16 AD17 AD18 AD19

AD27

AD31

C/BE1*

AD23

OC2*/GPIO41

PLTRST*

CLKOUT_PCI1

CLKOUT_PCI3

CLKOUT_PCI0

CLKOUT_PCI4

(5 OF 10)

USB

PCI

NVRAM

OUT

OUT OUT

IN IN IN

IN

BI BI

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(IPD) (IPD)

EHCI2

(DPD)

(IPU)

(DPD)

EHCI1

NOTE: Internal pull-downs on all USB pins

(IPU)

T57

External Hub 1

External Hub 2

36 93

35 93

402

1/16W MF-LF

5%

10K

R2060

1

2

402

1/16W MF-LF

5%

10K

R2062

1

2

MF-LF

10K

402

1/16W

5%

R2061

1

2

5% MF-LF

1/16W 402

10K

R2064

1

2

MF-LF

1/16W

402

22.6

1%

R2070

1

2

27 94

27

27 31 40

19 25

10K

MF-LF1/16W

5% 402

R2024

1 2

10K

5%

1/16W MF-LF

402

R2023

1 2

10K

MF-LF1/16W

4025%

R2022

1 2

10K

5%

MF-LF

402

1/16W

R2020

1 2

10K

5%

MF-LF

402

1/16W

R2021

1 2

10K

4025%

1/16W MF-LF

R2027

1 2

402

1/16W MF-LF

10K

5%

R2026

1 2

10K

402

MF-LF1/16W

5%

R2010

1 2

10K

402

MF-LF1/16W

5%

R2011

1 2

402

10K

1/16W MF-LF

5%

R2012

1 2

10K

MF-LF

5%

1/16W

402

R2013

1 2

10K

402

MF-LF1/16W

5%

R2014

1 2

H18

IBEX_PEAK_M

OMIT

FCBGA

U1800

H40 N34

E40 C40 M48 M45 F53 M40 M43 J36 K48 F40

C44

C42 K46 M51 J52 K51 L34 F42 J40 G46 F44

A38

M47 H36

C36 J34 A40 D45 E36 H48

J50 G42 H47 G34

N52 P53 P46 P51 P48

F46 C46

F48 K45 F36 H53

A42

BD3

AY9 BD1 AP15 BD8

AY6

AP7

BD6 BB7 BC8 BJ8 BJ6 BG6

AP6 AT6 AT9 BB1 AV6 BB3 BA4 BE4 BB6

AV9 BG8

AV7

AU2

AV11 BF5

AY8 AY5

N16 J16 F16 L16 E14 G16 F12 T15

H44

K6

E50

G38 H51 B37 A44

B41 K53 A36 A48

D49

D5

M7

F51 A46 B45 M53

E44

D41 C48

J18

A22 C22 G24 H24 L24 M24 A24 C24

A18 C18 N20 P20 J20 L20 F20 G20 A20 C20 M22 N22 B21 D21 H22 J22 E22 F22

D25

B25

27

5% MF-LF

1/16W 402

10K

R2066

1

2

402

1/16W MF-LF

5%

10K

R2065

1

2

5%

10K

MF-LF1/16W

402

R2025

1 2

19 88

10K

MF-LF

402

1/16W

5%

R2030

1 2

10K

MF-LF

402

1/16W

5%

R2031

1 2

10K

MF-LF

402

1/16W

5%

R2032

1 2

402

10K

MF-LF1/16W

5%

R2036

1 2

10K

MF-LF

402

1/16W

5%

R2035

1 2

5%

1/16W

402

MF-LF

10K

R2037

1 2

19 64

19

19 64

10K

MF-LF

402

1/16W

5%

R2038

1 2

5%

1/16W

402

MF-LF

10K

R2081

1 2

10K

MF-LF

402

1/16W

5%

R2080

1 2

19 25

93

103

93

103

SYNC_DATE=10/07/2009

PCH PCI/FlashCache/USB

SYNC_MASTER=K18_MLB

NC_NV_WR_RE_L<0> NC_NV_WR_RE_L<1>

USB_HUB1_UP_N USB_HUB1_UP_P NC_USB_1N

NC_NV_RB_L

NC_NV_WE_CK_L<1>

PCI_INTC_L

PP3V3_S0_PCH

NC_USB_11P

NC_USB_9P

NC_PCI_AD<27>

NC_USB_11N

NC_USB_13P

NC_USB_1P

NC_USB_3P

NC_USB_4P NC_USB_5N NC_USB_5P

NC_USB_13N

PCH_USB_RBIAS

NC_USB_7N

NC_USB_3N

NC_USB_4N

NC_USB_6N

NC_USB_10N

NC_USB_12P

NC_USB_10P

NC_USB_6P

USB_BRCRYPT_P

USB_BRCRYPT_N

PP3V3_S5_PCH

NC_PCI_AD<17>

NC_PCI_AD<20>

NC_PCI_AD<30>

NC_PCI_AD<29>

NC_PCI_C_BE_L<0>

NC_PCI_GNT1_L

AUD_IP_PERIPHERAL_DET

PCI_REQ3_L PCH_GPIO2

JTAG_GMUX_TMS

AUD_I2C_INT_L

NC_PCI_AD<12>

PP3V3_S5_PCH

PCH_GPIO59 PM_LATRIGGER_L

PCI_PLOCK_L

PCH_CLK33M_PCIOUT

LPC_CLK33M_SMC_R

PLT_RESET_L

PCI_IRDY_L

PCI_SERR_L

PCI_INTD_L PCI_REQ0_L

PCI_INTA_L PCI_INTB_L

MIKEY_MIC_LOAD_DET

AUD_IP_PERIPHERAL_DET

AUD_I2C_INT_L

JTAG_GMUX_TMS

PM_LATRIGGER_L

NC_PCI_CLK33M_OUT3

NC_PCI_AD<23>

NC_PCI_C_BE_L<1>

NC_PCI_AD<31>

NC_PCI_AD<19>

NC_PCI_AD<18>

NC_PCI_AD<16>

NC_PCI_AD<15>

PCH_GPIO2

NC_PCI_PAR

NC_PCI_GNT2_L

NC_PCI_GNT0_L

NC_PCI_C_BE_L<3>

NC_PCI_C_BE_L<2>

LPC_CLK33M_GMUX_R

NC_PCI_AD<26>

NC_PCI_AD<25>

NC_PCI_AD<24>

NC_PCI_AD<14>

NC_PCI_AD<13>

NC_PCI_AD<11>

NC_PCI_AD<10>

NC_PCI_AD<8>

NC_PCI_AD<7>

NC_PCI_AD<6>

NC_PCI_AD<5>

NC_PCI_AD<4>

NC_PCI_AD<1>

NC_PCI_AD<0>

NC_PCI_RESET_L

NC_PCI_AD<22>

NC_PCI_AD<21>

NC_PCI_AD<28>

NC_PCI_AD<9>

NC_NV_CE_L<0> NC_NV_CE_L<1>

NC_NV_CE_L<3>

NC_NV_CE_L<2>

NC_NV_DQS<1>

NC_NV_DQS<0>

NC_NV_DQ<0>

NC_NV_DQ<2>

NC_NV_DQ<1>

NC_NV_DQ<4>

NC_NV_DQ<3>

NC_NV_DQ<6>

NC_NV_ALE NC_NV_CLE

NC_NV_WE_CK_L<0>

NC_PCI_AD<2>

PCI_TRDY_L

LPC_CLK33M_LPCPLUS_R

PCI_STOP_L

PCI_PERR_L

MIKEY_MIC_LOAD_DET

PCI_FRAME_L

PCI_DEVSEL_L

NC_PCI_GNT3_L

JTAG_GMUX_TDI PCI_REQ3_L

NC_PCI_PME_L

USB_HUB2_UP_N USB_HUB2_UP_P

NC_NV_DQ<9>

NC_NV_DQ<5>

NC_USB_7P

NC_NV_DQ<15>

NC_NV_DQ<8>

NC_NV_DQ<7>

NC_NV_DQ<14>

NC_NV_DQ<13>

NC_NV_DQ<12>

NC_NV_DQ<11>

NC_NV_DQ<10>

NC_USB_9N

NC_USB_12N

PCH_GPIO59

PCH_GPIO41

USB_HUB_SOFT_RESET_L

PCH_GPIO42 PCH_GPIO43 PCH_GPIO9 PCH_GPIO10

TP_PCH_NV_RCOMP

NC_PCI_AD<3>

JTAG_GMUX_TDI

20 OF 132 19 OF 103

6

17 18 20 21 23 24

101

6

93

6

17 18 19 20 21 23

101

6

19 64

19

19 88

19 64

6

17 18 19 20 21 23

101

19 25

6

19

6

27

6

19

6

19

6

25

25 35

25

6

19 88

IN

OUT OUT

BI

OUT

IN

OUT

NC_5

NC_3 NC_4

NC_1 NC_2

TP8

TP19

TP18

TP17

TP15

TP16

TP14

TP13

TP12

TP11

TP9

TP10

TP6

TP7

TP4

TP5

TP2

TP1

INIT3_3V*

TP24

VSS_NCTF31

VSS_NCTF30

VSS_NCTF28 VSS_NCTF29

VSS_NCTF25 VSS_NCTF26 VSS_NCTF27

VSS_NCTF24

VSS_NCTF23

VSS_NCTF22

VSS_NCTF21

VSS_NCTF20

VSS_NCTF19

VSS_NCTF18

VSS_NCTF17

VSS_NCTF16

VSS_NCTF15

VSS_NCTF14

VSS_NCTF13

VSS_NCTF12

VSS_NCTF10 VSS_NCTF11

VSS_NCTF8 VSS_NCTF9

VSS_NCTF7

VSS_NCTF6

VSS_NCTF5

VSS_NCTF2 VSS_NCTF3 VSS_NCTF4

VSS_NCTF1

GPIO57

SATA5GP/GPIO49

SDATAOUT1/GPIO48

PCIECLKRQ7*/GPIO46

SDATAOUT0/GPIO39

PCIECLKRQ6*/GPIO45

SLOAD/GPIO38

SATA3GP/GPIO37

SATA2GP/GPIO36

SATACLKREQ*/GPIO35

STP_PCI*/GPIO34

GPIO27

GPIO28

MEM_LED/GPIO24

TACH0/GPIO17

SCLOCK/GPIO22

SATA4GP/GPIO16

GPIO15

LAN_PHY_PWR_CTRL/GPIO12

GPIO8

TACH3/GPIO7

TACH1/GPIO1

TACH2/GPIO6

BMBUSY*/GPIO0

THRMTRIP*

PROCPWRGD

RCIN*

PECI

CLKOUT_BCLK0_P/CLKOUT_PCIE8P

CLKOUT_BCLK0_N/CLKOUT_PCIE8N

A20GATE

CLKOUT_PCIE7N

CLKOUT_PCIE6P

CLKOUT_PCIE6N

TP3

CLKOUT_PCIE7P

(6 OF 10)

CPU

NCTF

RSVD

GPIO

MISC

IN

BI

OUT

BI

OUT

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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REVISION

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Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(IPU)

(IPU*)

(IPD)

(IPU*)

(DPL_B_MON2_P)

(SATA_OB_ANA)

(DPL_B_MON2_N)

(DPL_B_MON1_P)

(DPL_B_MON1_N)

(XCKPLL_MON1_P)

(XCKPLL_MON1_N)

(IPU)

IPU* = Only on TACH function.

(IPU*)

(IPD)

20 46

10 91

10 25 91

56

5%

MF-LF

1/16W

402

R2161

1 2

10 47 91

56

5%

402

1/16W MF-LF

R2160

1

2

10K

402

5% 1/16W MF-LF

R2155

1

2

20

OMIT

FCBGA

IBEX_PEAK_M

U1800

U2

Y3

AM3 AM1

AH45 AH46

AF48 AF47

T7

AB12

V13

F8

F10

P6

K9

H10

AB45 AB38 AB42 AB41 T39

H3

F1

BG10

BE10

T1

AB7

AB13

AA2

AA4

V6

Y7

P3

AB6

V3

M11

F38

C38

D37

J32

BD10

BA22

N18

AJ24

AK41

AK42

M32

N32

M30

N30

H12

AA23

AW22

C10

BB22

AY45

AY46

AV43

AV45

AF13

M18

A4

A49

BE1

BE53

BF1

BF53

BH1

BH2 BH52 BH53

BJ1

BJ2

A5

BJ4 BJ49

BJ5 BJ50 BJ52 BJ53

D1 D2

D53

E1

A50

E53

A52

A53

B2

B4 B52 B53

10K

MF-LF

1/16W

5%

402

R2150

1

2

5%

1/16W

402

MF-LF

10K

R2116

1 2

2.2K

5%

1/16W MF-LF

R2115

402

21

5%

1/16W

402

MF-LF

10K

R2113

1 2

1/16W

402

MF-LF

20K

R2112

1 2

5%

1/16W

5% 402

MF-LF

10K

R2114

1 2

10K

402

1/16W

5%

R2110

1 2

MF-LF

10K

402

R2111

1

1/16W

2

5%

MF-LF

20 25 46 47

8

20 40

20 88

6

20 48

20 25 64

20 42

6

20 48 58

20 25

20 40

20 33 74

20 74

20 25 88

20 88

25 31

5%

1/16W

402

MF-LF

10K

R2121

1 2

5%

1/16W

402

MF-LF

10K

R2120

1 2

10K

MF-LF1/16W

5% 402

R2122

1 2

10K

MF-LF

5%

1/16W

402

R2123

1 2

10K

402

1/16W5%MF-LF

R2124

1 2

20 25

10K

5%

1/16W

402

MF-LF

R2130

1 2

5%

1/16W

402

MF-LF

10K

R2131

1 2

5%

1/16W

402

MF-LF

10K

R2133

1 2

5%

1/16W

402

10K

MF-LF

R2132

1 2

5%

1/16W

402

MF-LF

10K

R2134

1 2

5% 402

MF-LF

10K

1/16W

R2135

1 2

10K

MF-LF

402

1/16W

5%

R2136

1 2

5% 402

MF-LF1/16W

R2137

1 2

10K

5% 402

MF-LF1/16W

1 2

10K

R2138

5% 402

MF-LF

100K

1/16W

R2139

1 2

20 37

PCH MISC

SYNC_MASTER=K18_MLB

SYNC_DATE=11/13/2009

FW_PLUG_DET_L GMUX_INT

SMC_IG_THROTTLE_L

PP3V3_S0_PCH

ENET_LOW_PWR

PP3V3_S3

PP3V3_S5_PCH

AUD_IPHS_SWITCH_EN LPCPLUS_GPIO

PCH_VSS_NCTF<27>

PCH_VSS_NCTF<15>

GMUX_INT SMC_RUNTIME_SCI_L

CPU_PWRGD

PCH_GPIO15

NC_PCH_TP19

NC_PCH_NC1 NC_PCH_NC2

PCH_THRMTRIP_L

NC_PCH_TP2

NC_PCH_TP3

NC_PCH_TP4

NC_PCH_TP1

NC_PCH_TP5

NC_PCH_TP6

NC_PCH_TP7

NC_PCH_TP10

NC_PCH_TP16

NC_PCH_TP15

NC_PCH_TP13

NC_PCH_TP12

NC_PCH_TP17

NC_PCH_NC3

NC_PCH_NC5

NC_PCH_TP18

NC_PCH_NC4

NC_PCH_SST

PCH_VSS_NCTF<1> PCH_VSS_NCTF<2>

PCH_VSS_NCTF<5>

TP_PCH_VSS_NCTF<7>

PCH_VSS_NCTF<9>

PCH_VSS_NCTF<11> PCH_VSS_NCTF<12>

PCH_VSS_NCTF<17>

PCH_VSS_NCTF<29>

PCH_VSS_NCTF<25>

PCH_VSS_NCTF<21>

SPIROM_USE_MLB

PCH_VSS_NCTF<19>

PCH_VSS_NCTF<22>

PCH_VRM_EN

PCH_GPIO24

SPIROM_USE_MLB

PCH_GPIO39

JTAG_GMUX_TDO

SDCARD_RESET

PCH_RCIN_L

PPVTT_S0_PCH

PP3V3_S0_PCH

PCH_A20GATE

NC_PCH_TP8

NC_PCH_TP14

NC_PCH_TP11

NC_PCH_TP9

TP_PCH_INIT3V3_L

PCH_GPIO39

TP_PCH_STP_PCI_L

PCH_VRM_EN

PCH_GPIO15

CPU_PECI

FSB_CLK133M_CPU_P

FSB_CLK133M_CPU_N

NC_PCIE_CLK100M_PE7N

NC_PCIE_CLK100M_PE6P

NC_PCIE_CLK100M_PE6N

NC_PCIE_CLK100M_PE7P

PCH_FCIM_EN_L

AUD_IPHS_SWITCH_EN

ODD_PWR_EN_L PCH_GPIO24

ME_TEMP_ALERT_L

AP_PWR_EN

WOL_EN

JTAG_GMUX_TCK JTAG_GMUX_TDO

ISOLATE_CPU_MEM_L

LPCPLUS_GPIO

SDCARD_RESET

FW_PWR_EN

PCH_FCIM_EN_L

SMC_RUNTIME_SCI_L

ODD_PWR_EN_L

JTAG_GMUX_TCK

ME_TEMP_ALERT_L

FW_PWR_EN

AP_PWR_EN

WOL_EN

MXM_GOOD

FW_PLUG_DET_L

SMC_IG_THROTTLE_L

ENET_LOW_PWR

PM_THRMTRIP_L

21 OF 132 20 OF 103

8

20 40

20 88

20 25 46 47

17 18 19 20 21 23 24

101

20 37

6 7

17 31 32 33 34 35 36 49 50 51 54 55

56 72 74 88

102 103

17 18 19 21 23

101

20 25 64

6

20 48

6

94

6

94

20

6

94

6

94

6

94

6

94

6

94

6

94

6

94

6

94

6

94

6

94

6

94

20

6

20 48 58

20

20 88

20 25

21 23

101

17 18 19 20 21 23 24

101

6

20

6

20

20 46

20 42

20 25 88

20 25

20 40

20 33 74

20 74

20

VCCIO24

VCCIO55

VCCIO54

VCCIO53

VCCIO52

VCCIO51

VCCIO50

VCCIO49

VCCIO48

VCCIO47

VCCIO46

VCCIO45

VCCIO44

VCCIO43

VCCIO42

VCCIO41

VCCIO40

VCCIO39

VCCIO38

VCCIO37

VCCIO36

VCCIO35

VCCIO34

VCCIO33

VCCIO32

VCCIO31

VCCIO29

VCCIO28

VCCIO27

VCCIO26

VCCIO25

VCCVRM2

VCCFDIPLL

VCCAPLLEXP

VCCALVDS

VCCADAC1 VCCADAC2

VSSA_DAC1 VSSA_DAC2

VCCTX_LVDS1 VCCTX_LVDS2 VCCTX_LVDS3 VCCTX_LVDS4

VCC3_3_2

VCC3_3_4

VCC3_3_3

VCCPNAND1 VCCPNAND2 VCCPNAND3 VCCPNAND4 VCCPNAND5 VCCPNAND6 VCCPNAND7 VCCPNAND8 VCCPNAND9

VCCME3_3_1 VCCME3_3_2 VCCME3_3_3 VCCME3_3_4

VCC3_3_1

VCCVRM1

VSSA_LVDS

VCCCORE1 VCCCORE2 VCCCORE3 VCCCORE4 VCCCORE5 VCCCORE6 VCCCORE7 VCCCORE8 VCCCORE9 VCCCORE10 VCCCORE11 VCCCORE12 VCCCORE13 VCCCORE14 VCCCORE15

VCCDMI1 VCCDMI2

VCCIO30

VCCIO1

CRT

PCI-E*

NAND / SPI

HVCMOS

(7 OF 10)

VCC CORE

LVDS

FDI

DMI

VCCSUS3_3_23

VCCSUS3_3_28

VCCSUS3_3_27

VCCSUS3_3_26

VCCSUS3_3_25

VCCSUS3_3_24

VCCSUS3_3_22

VCCSUS3_3_21

VCCSUS3_3_20

VCCSUS3_3_19

VCCSUS3_3_18

VCCSUS3_3_17

VCCSUS3_3_16

VCCSUS3_3_15

VCCSUS3_3_14

VCCSUS3_3_13

VCCSUS3_3_12

VCCSUS3_3_11

VCCSUS3_3_10

VCCSUS3_3_9

VCCSUS3_3_8

VCCSUS3_3_7

VCCSUS3_3_6

VCCSUS3_3_5

VCCSUS3_3_4

VCCSUS3_3_3

VCCSUS3_3_2

VCCSUS3_3_1

VCCSUS3_3_29

VCCME3

V5REF

V5REF_SUS

VCC3_3_8 VCC3_3_9

VCC3_3_11

VCC3_3_10

VCC3_3_12 VCC3_3_13

VCC3_3_14

VCCSATAPLL1 VCCSATAPLL2

VCCVRM4

VCCME13 VCCME14 VCCME15 VCCME16

VCCSUSHDA

VCCRTC

V_CPU_IO1 V_CPU_IO2

DCPSST

DCPSUS

VCCSUS3_3_30

VCCSUS3_3_32

VCC3_3_6 VCC3_3_7

VCCACLK1 VCCACLK2

VCCLAN1 VCCLAN2

VCCME1

DCPSUSBYP

VCCME2

VCCME6

VCCME5

VCCME4

VCCME7 VCCME8 VCCME9

VCCME11

VCCME10

DCPRTC

VCCME12

VCCVRM3

VCCADPLLA1 VCCADPLLA2

VCCADPLLB2

VCCADPLLB1

VCC3_3_5

VCCSUS3_3_31

VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20

VCCIO9

VCCIO56VCCIO21 VCCIO22 VCCIO23

VCCIO2 VCCIO3 VCCIO4

VCCIO5 VCCIO6 VCCIO7 VCCIO8

PCI/GPIO/LPC

USB

CPU

RTC

HDA

(10 OF 10)

CLOCK AND MISCELLANEOUS

PCI/GPIO/LPC

SATA

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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345678

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8 7 5 4 2 1

(VCCIO[1-56] total)

3062 mA

115 mA

GPIO27 HDA_SYNC VccVRM PLLs

31 mA (if GPIO27 is low)

< 1 mA

PCH output, for decoupling only

(VCCSUS3_3[1-32] total)

164 mA (VCCVRM[1-4] total)

68 mA

3062 mA (VCCIO[1-56] total)

164 mA (VCCVRM[1-4] total)

357 mA (VCC3_3[1-14] total)

PCH output, for decoupling only

69 mA

PCH output, for decoupling only

3062 mA (VCCIO[1-56] total)

59 mA

52 mA

Verify S0 okay

(VCCME[1-16] total)

< 1 mA

< 1 mA S0-S5

357 mA

(VCCSUS3_3[1-32] total)

61 mA (1.1V) 58 mA (1.05V)

320 mA S0, 67 mA M-on

1849 mA S0, 700 mA M-on

163 mA S0, 65 mA S3-S5

357 mA

2 mA S0-S5, ~6 uA G3

6 mA S0, < 1 mA S3-S5

1849 mA S0, 700 mA M-on

3062 mA (VCCIO[1-56] total)

40 mA (if GPIO27 is low)

5 mA (if GPIO27 is low)

3062 mA (VCCIO[1-56] total)

69 mA

85 mA S0, 22 mA M-on

< 1 mA

156 mA (1.8V) NOTE: Connect to 3.3V if NAND not used.

357 mA (VCC3_3[1-14] total)

3062 mA (VCCIO[1-56] total)

(VCC3_3[1-14] total)

Note: 1.5V option consumes more current than 1.8V

1 (IPU) 1 1.5V Float

(VCC3_3[1-14] total)

357 mA

1432 mA

3062 mA (VCCIO[1-56] total)

(VCC3_3[1-14] total)

(VCCME[1-16] total)

PLLs = VccAClk, VccSATAPLL, VccAPLLEXP & VccFDIPLL

0 X 1.05V 1.05V

1 (IPU) 0 (IPD) 1.8V Float

163 mA S0, 65 mA S3-S5

Current numbers from Ibex Peak EDS Spec Update rev 0.71, doc #386904 (Table 8-3). Pre-Silicon Mobile Estimates.

IBEX_PEAK_M

FCBGA

OMIT

U1800

AN35

AB34 AB35 AD35

AE50 AE52

AH38

BJ24

AB24

AH26 AH28 AH30 AH31 AJ30 AJ31

AB26 AB28 AD26 AD28 AF26 AF28 AF30 AF31

AT16 AU16

BJ18

AM23

AK24

AN20 AN22 AN23 AN24 AN26 AN28 BJ26 BJ28 AT26 AT28 AU26 AU28 AV26 AV28 AW26 AW28 BA26 BA28 BB26 BB28 BC26 BC28 BD26 BD28 BE26 BE28 BG26 BG28 BH27

AN30 AN31

AM8 AM9 AP11 AP9

AM16 AK16 AK20 AK19 AK15 AK13 AM12 AM13 AM15

AP43 AP45 AT46 AT45

AT22

AT24

AF53 AF51

AH39

IBEX_PEAK_M

FCBGA

OMIT

U1800

V9

V12

Y22

Y20

K49

F24

AT18 AU18

M36 N36 P36 U35

AD13

V15 V16 Y16

J38 L38

AP51 AP53

BB51 BB53

BD51 BD53

AH19 AD20 AF22 AD19 AF20 AF19 AH20 AB19 AB20 AB22

AF34

AD22

AH23 AJ35 AH35

AH34 AF32

V24

V23

V26 Y24 Y26

AH22

AF23 AF24

AD38

Y39 Y41 Y42

AA34 Y34 Y35 AA35

AD39 AD41 AF43 AF41 AF42

V39 V41 V42

A12

AK3 AK1

V28

M26 L28 L26 J28 J26 H28 H26 G28 G26 F28

U28

F26 E28 E26 C28 C26 B27 A28 A26 U23

P18

U26

U19 U20 U22

U24 P28 P26 N28 N26 M28

L30

AU24

AT20

20% CERM

10V

0.1UF

402

PLACE_NEAR=U1800.Y20:2.54MM

C2200

1

2

402

0.1UF

20% 10V CERM

PLACE_NEAR=U1800.V9:2.54MM

C2210

1

2

402

0.1UF

20% 10V CERM

PLACE_NEAR=U1800.V12:2.54MM

C2220

1

2

402

0.1UF

20% 10V CERM

PLACE_NEAR=U1800.Y22:2.54MM

C2230

1

2

20%

4.7UF

X5R

4V

402

C2225

1

2

402-HF

1%

0.2

1/6W

MF

R2225

1 2

SYNC_MASTER=K18_MLB

PCH Power

SYNC_DATE=10/02/2009

PP1V05_S0_PCH

PPVTT_S0_PCH

PP3V3_S0_PCH

PP5V_S5_PCH_V5REFSUS

GND

PP5V_S0_PCH_V5REF

PP1V05_S0_PCH_VCCA_CLK

PP1V8_S0_PCH

PP1V05_S0_PCH

PP3V42_G3H

PP3V3R1V5_S0_PCH

PP1V05_S0_PCH

PP1V8_S0_PCH

PP1V05_S0_PCH_VCCAPLL_SATA

PP3V3_S5_PCH

PP1V05_S0_PCH

PP1V05_S0_PCH_VCCAPLL_FDI

PP1V05_S0_PCH

PP1V05_S0_PCH_VCCAPLL_EXP

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

VOLTAGE=X.XV

PPVOUT_S0_PCH_DCPSST

PPVOUT_S5_PCH_DCPSUSBYP

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 mm

PPVOUT_S5_PCH_DCPSUS

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=X.XV

PP3V3_S0_PCH

PP1V05_S0_PCH

PP1V05_S0_PCH_VCCADPLLA

PP3V3_S5_PCH

PP3V3_S0_PCH

PP1V8_S0_PCH

PPVTT_S0_PCH

PP1V8_S0_PCH_VCCTX_LVDS

PP3V3_S0_PCH_VCCALVDS

PP3V3_S0_PCH_VCCA_DAC

PP3V3R1V8_S0_PCH_VCCPNAND

PP3V3_S0M_PCH

PP1V05_S0_PCH_VCCADPLLB

PP1V8_S0_PCH

PP3V3_S0_PCH

MIN_NECK_WIDTH=0.2 mm

PPVOUT_G3_PCH_DCPRTC

VOLTAGE=X.XV

MIN_LINE_WIDTH=0.2 mm

PP3V3_S0_PCH

PP1V05_S0_PCH

MIN_LINE_WIDTH=0.2 mm VOLTAGE=1.05V

MIN_NECK_WIDTH=0.1 mm

PP1V05_S0_PCH_VCCIO_SSC_FLT

22 OF 132 21 OF 103

17 18 21 23 24

101

17 18 21 23 24

101

17 18 21 23 24

101

20 21 23

101

17 18 19 20 21 23 24

101

23

21 24

101

17 18 21 23 24

101

6 7

17 23 43 45 46 47 48 49

50 51 54 65 66 74

23

101

17 18 21 23 24

101

21 24

101

23

17 18 19 20 21 23

101

17 18 21 23 24

101

23

17 18 21 23 24

101

17 18 21 23 24

101

23

17 18 19 20 21 23 24

101

17 18 21 23 24

101

24

17 18 19 20 21 23

101

17 18 19 20 21 23 24

101

21 24

101

20 21 23

101

24

101

24

23

101

23

101

24

21 24

101

17 18 19 20 21 23 24

101

17 18 19 20 21 23 24

101

17 18 21 23 24

101

VSSVSS

(8 OF 10)

VSSVSS

(9 OF 10)

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

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R

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PAGE TITLE

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A

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

IBEX_PEAK_M

OMIT

FCBGA

U1800

AB16 AA19

AA32

AM28 BA42 AM30 AM31 AM32 AM34 AM35 AM38 AM39 AM42

AB11

AU20 AM46 AV22 AM49 AM7 AA50 BB10 AN32 AN50 AN52

AB15

AP12 AP42 AP46 AP49 AP5 AP8 AR2 AR52 AT11 BA12

AB23

AH48 AT32 AT36 AT41 AT47 AT7 AV12 AV16 AV20 AV24

AB30

AV30 AV34 AV38 AV42 AV46 AV49 AV5 AV8 AW14 AW18

AB31

AW2 BF9 AW32 AW36 AW40 AW52 AY11 AY43 AY47

AB32 AB39 AB43 AB47

AA20

AB5 AB8

AC2 AC52 AD11 AD12 AD16 AD23 AD30 AD31

AA22

AD32 AD34 AU22 AD42 AD46 AD49

AD7

AE2

AE4 AF12

AM19

Y13 AH49

AU4 AF35 AP13 AN34 AF45 AF46 AF49

AF5

AA24

AF8

AG2 AG52 AH11 AH15 AH16 AH24 AH32 AV18 AH43

AA26

AH47

AH7 AJ19

AJ2 AJ20 AJ22 AJ23 AJ26 AJ28 AJ32

AA28

AJ34

AT5

AJ4 AK12 AM41 AN19 AK26 AK22 AK23 AK28

AA30

AK30 AK31 AK32 AK34 AK35 AK38 AK43 AK46 AK49 AK5

AA31

AK8 AL2 AL52 AM11 BB44 AD24 AM20 AM22 AM24 AM26

OMIT

IBEX_PEAK_M

FCBGA

U1800

AY7 B11 B15 B19 B23 B31 B35 B39 B43 B47

B7 BG12 BB12 BB16 BB20 BB24 BB30 BB34 BB38 BB42 BB49

BB5 BC10 BC14 BC18

BC2 BC22 BC32 BC36 BC40 BC44 BC52

BH9 BD48 BD49

BD5 BE12 BE16 BE20 BE24 BE30 BE34 BE38 BE42 BE46 BE48 BE50

BE6

BE8

BF3 BF49 BF51 BG18 BG24

BG4 BG50 BH11 BH15 BH19 BH23 BH31 BH35 BH39 BH43 BH47

BH7

C12

C50

D51

E12

E16

E20

E24

E30

E34

E38

E42

E46

E48

E6 E8

F49

F5 G10 G14 G18

G2 G22 G32 G36 G40 G44 G52

AF39

H16 H20 H30 H34 H38 H42

H49 H5 J24 K11 K43 K47 K7 L14 L18 L2 L22 L32 L36 L40 L52 M12 M16 M20 N38 M34 M38 M42 M46 M49 M5 M8 N24 P11 AD15 P22 P30 P32 P34 P42 P45 P47 R2 R52 T12 T41 T46 T49 T5 T8 U30 U31 U32 U34 P38 V11 P16 V19 V20 V22 V30 V31 V32 V34 V35 V38 V43 V45 V46 V47 V49 V5 V7 V8 W2 W52 Y11 Y12 Y15 Y19 Y23 Y28 Y30 Y31 Y32 Y38 Y43 Y46 P49 Y5 Y6 Y8 P24 T43 AD51 AT8 AD47 Y47 AT12 AM6 AT13 AM5 AK45 AK39 AV14

PCH Grounds

SYNC_MASTER=T22_MLB

SYNC_DATE=03/26/2009

23 OF 132 22 OF 103

NCNC

NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

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8 7 5 4 2 1

PCH V5REF Filter & Follower

PCH VCC3_3 BYPASS

(PCH Misc PLL PWR)

PCH VCCACLK Filter

(VCCSUS3_3 Total)

PCH USB/VCCSUS3_3 BYPASS

(PCH HD Audio 3.3V/1.5V PWR)

6 uA G3

2 mA S0-S5 /

1 mA S0-S5

PCH VCCIO BYPASS (PCH DMI 1.05V PWR)

(PCH 1.05V LAN Core PWR)

PCH V_CPU_IO BYPASS (PCH 1.1V/1.05V CPU I/O PWR)

(PCH SUSPEND USB 3.3V PWR)

1 mA S0-S5

(PCH Reference for 5V Tolerance on USB)

PCH V5REF_SUS Filter & Follower

(PCH MISC 3.3V PWR)

1 mA

Current numbers from Ibex Peak EDS Spec Update rev 0.71, doc #386904 (Table 8-3). Pre-Silicon Mobile Estimates.

(PCH CLK/HVCMOS 3.3V PWR)

(PCH PCI 3.3V PWR)

PCH CORE/VCC3_3 BYPASS

(PCH PCIE 1.05V PWR)

PCH VCCIO BYPASS

(PCH SATA 1.05V PWR)

PCH VCCIO BYPASS

(PCH USB 1.05V PWR)

PCH VCCIO BYPASS

PCH VCCCORE BYPASS

(PCH RTC 3.3V PWR)

1 mA

(PCH CLK 1.05V PWR)

PCH VCCSUSHDA BYPASS

PCH VCCPNAND BYPASS (PCH NAND 1.8V/3.3V PWR)

(PCH 1.05V CORE PWR)

PCH VCCSUS3_3 BYPASS (PCH SUSPEND PCI 3.3V PWR)

PCH VCCME3_3 BYPASS (PCH ME 3.3V PWR)

(PCH SATA 3.3V PWR)

PCH VCC3_3 BYPASS

163 mA S0 /

65 mA S3-S5

PCH VCCME BYPASS (PCH 1.05V ME Core PWR)

PCH VCC3_3 BYPASS

(PCH PCIe/DMI 3.3V PWR)

PCH VCCFDIPLL Filter (PCH FDI PLL PWR)

WF: C2413 not in DG or CRB

WF: C2311 not in DG or CRB

PCH VCCAPLLEXP Filter (PCH PCIe PLL PWR)

PCH VCCLAN BYPASS

(PCH Reference for 5V Tolerance on PCI)

PCH VCCSATAPLL Filter (PCH SATA PLL PWR)

PCH VCCRTC BYPASS

402

10V

10% X5R

1UF

PLACE_NEAR=U1800.K49:2.54MM

C2401

1

2

NO STUFF

PLACE_NEAR=U1800.AP51:2.54MM

2

1

C2419

1UF

CERM 402

10%

6.3V

5%

1/16W

402

MF-LF

100

R2401

2

1

2

1

402

10%

1UF

X5R

PLACE_NEAR=U1800.F24:2.54MM

10V

C2400

BAT54DW-X-G

SOT-363

D2400

1

6

5

1/16W

10

5%

402

R2400

2

1

MF-LF

D2400

BAT54DW-X-G

SOT-363

2

3

4

16V

10% 402

X5R

0.1UF

PLACE_NEAR=U1800.A12:2.54MM

C2421

1

2

0.1UF

X5R 402

10% 16V

PLACE_NEAR=U1800.P18:2.54MM

C2425

1

2

16V

10% 402

X5R

0.1UF

PLACE_NEAR=U1800.A12:2.54MM

C2422

1

2

C2413

6.3V

10%

402

CERM

1UF

OMIT

PLACE_NEAR=U1800.BJ24:2.54MM

1

2

6.3V

10% 402

1UF

OMIT

CERM

PLACE_NEAR=U1800.BJ18:2.54MM

C2415

1

2

NO STUFF

PLACE_NEAR=U1800.AK1:2.54MM

2

1

C2417

1UF

CERM 402

10%

6.3V

X5R 402

16V

0.1UF

10%

PLACE_NEAR=U1800.U23:2.54MM

C2427

1

2

0.1UF

X5R 402

10% 16V

PLACE_NEAR=U1800.A26:2.54MM

C2426

1

2

0.1UF

X5R 402

10% 16V

PLACE_NEAR=U1800.AM8:2.54MM

C2430

1

2

0.1UF

X5R 402

10% 16V

PLACE_NEAR=U1800.V15:2.54MM

C2435

1

2

0.1UF

X5R 402

10% 16V

PLACE_NEAR=U1800.J38:2.54MM

C2436

1

2

PLACE_NEAR=U1800.AD13:2.54MM

0.1UF

X5R 402

10% 16V

C2437

1

2

0.1UF

X5R 402

10% 16V

PLACE_NEAR=U1800.AN35:2.54MM

C2438

1

2

0.1UF

X5R 402

10% 16V

PLACE_NEAR=U1800.AB34:2.54MM

C2439

1

2

16V

10%

402

X5R

0.1UF

C2440

1

2

PLACE_NEAR=U1800.AK13:2.54MM

1UF

CERM 402

10%

6.3V

PLACE_NEAR=U1800.L30:2.54MM

C2445

1

2

16V

10%

402

X5R

0.1UF

PLACE_NEAR=U1800.AT18:2.54MM

C2452

1

2

16V

10%

402

X5R

0.1UF

PLACE_NEAR=U1800.AT18:2.54MM

C2451

1

2

6.3V

20%

603

X5R

4.7UF

PLACE_NEAR=U1800.AT18:2.54MM

C2450

1

2

6.3V

10% 402

CERM

1UF

PLACE_NEAR=U1800.V39:2.54MM

C2469

1

2

6.3V

X5R-CERM

603

22UF

20%

PLACE_NEAR=U1800.V39:2.54MM

C2467

1

2

6.3V

X5R-CERM

603

22UF

20%

PLACE_NEAR=U1800.AD38:2.54MM

C2466

1

2

NO STUFF

C2460

1UF

10%

6.3V 402

CERM

PLACE_NEAR=U1800.AF23:2.54MM

1

2

6.3V

10% 402

CERM

1UF

PLACE_NEAR=U1800.AH35:2.54MM

C2477

1

2

6.3V

10% 402

CERM

1UF

PLACE_NEAR=U1800.AH23:2.54MM

C2476

1

2

6.3V

10% 402

CERM

1UF

PLACE_NEAR=U1800.AF32:2.54MM

C2475

1

2

6.3V

10% 402

CERM

1UF

PLACE_NEAR=U1800.V24:2.54MM

C2480

1

2

6.3V

10%

402

CERM

1UF

PLACE_NEAR=U1800.AB19:2.54MM

C2485

1

2

6.3V

10% 402

CERM

1UF

PLACE_NEAR=U1800.AN20:2.54MM

C2494

1

2

6.3V

10% 402

CERM

1UF

PLACE_NEAR=U1800.AN20:2.54MM

C2493

1

2

6.3V

10% 402

CERM

1UF

PLACE_NEAR=U1800.AN20:2.54MM

C2492

1

2

402

6.3V

10% CERM

1UF

PLACE_NEAR=U1800.AN20:2.54MM

C2491

1

2

10UF

6.3V

20% 603

X5R

PLACE_NEAR=U1800.AN20:2.54MM

C2490

1

2

402

6.3V

10% CERM

1UF

PLACE_NEAR=U1800.AT16:2.54MM

C2455

1

2

6.3V

10% 402

CERM

1UF

PLACE_NEAR=U1800.AD38:2.54MM

C2468

1

2

6.3V

X5R-CERM

603

22UF

20%

PLACE_NEAR=U1800.AD38:2.54MM

C2465

1

2

402

2

6.3V CERM

10%

PLACE_NEAR=U1800.AB24:2.54MM

1

1UF

C2471

10UF

C2470

PLACE_NEAR=U1800.AB24:2.54MM

6.3V X5R 603

1

2

20%

6.3V

10% 402

CERM

1UF

PLACE_NEAR=U1800.A12:2.54MM

C2420

1

2

PCH Non-GFX Decoupling

SYNC_MASTER=K17_WFERRY

SYNC_DATE=06/09/2009

PP1V05_S0_PCH_VCCA_CLK

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM

PP1V05_S0_PCH_VCCAPLL_SATA

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM VOLTAGE=1.05V

PP5V_S5

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM

PP1V05_S0_PCH_VCCAPLL_EXP

PP1V05_S0_PCH_VCCAPLL_FDI

MIN_LINE_WIDTH=0.5MM VOLTAGE=1.05V

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.3MM VOLTAGE=5V

MIN_NECK_WIDTH=0.25MM

PP5V_S5_PCH_V5REFSUS

PP3V3_S0_PCH

PP1V05_S0_PCH

PP3V3_S5_PCH

PP3V3_S0M_PCH

PP3V3_S0_PCH

PP3V3R1V5_S0_PCH

PP3V3R1V8_S0_PCH_VCCPNAND

GND

PP1V05_S0_PCH

PPVTT_S0_PCH

PP1V05_S0_PCH

PP3V3_S0_PCH

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.3MM

PP5V_S0_PCH_V5REF

VOLTAGE=5V

PP5V_S0

PP3V42_G3H

PP3V3_S5_PCH

24 OF 132 23 OF 103

21

7

57 67 73

102

21

17 18 19 20 21 23

24

101

17 18 21 23 24

101

17 18 19 20 21 23

101

21

101

17 18 19 20 21 23 24

101

17 18 19 20 21 23 24

101

17 18 19 20 21 23 24

101

17 18 19 20 21 23 24

101

21

101

21

101

17 18 21 23 24

101

17 18 21 23 24

101

17 18 21 23 24

101

17 18 21 23 24

101

20 21 23

101

20 21 23

101

17 18 21 23 24

101

17 18 19 20 21 23 24

101

21

6 7 8

42

48 53 55 69 70

71 73

87

102

6 7

17 21 43 45 46 47 48 49

50 51 54 65 66 74

17 18 19 20 21 23

101

17 18 19 20 21 23

101

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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A

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345678

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8 7 5 4 2 1

PCH VCCTX_LVDS Filter

69 mA

68 mA

(PCH DPLLB PWR)

(PCH DAC PLL PWR)

Design recommendations from Calpella Design Guide Rev 1.5 (doc #398905) Section 3.25.3 tables 161 and 162.

Current numbers from Ibex Peak EDS Spec Update rev 0.71, doc #386904 (Table 8-3). Pre-Silicon Mobile Estimates.

69 mA

59 mA

(PCH LVDS TX PWR)

PCH VCCADAC Filter

69 mA

68 mA

59 mA

69 mA

137 mA

actor Schematic Check List Rev 1.1 (doc #395914) table 3.26.

GFX (CPU VCCAXG) DECOUPLING

3x 330uF 6 mOhm (2 stuffed), 3x 22uF 0603, 16x 1uF 0402

PLACEMENT_NOTE (C2510-C2514):

5x 1uF 0402

PLACEMENT_NOTE (C2500-C2506):

PLACEMENT_NOTE (C2524-C2539):

VCAP2 (CPU BSC Package) DECOUPLING

Design recommendations from Calpella Small Form Factor Design Guide Rev 1.5 (doc #407364) table 2-34 and Calpella Small Form F

PCH VCCADPLLA Filter (PCH DPLLA PWR)

PCH VCCADPLLB Filter

0805

0.1UH

PLACE_NEAR=U1800.AP43:2.54MM

L2570

1 2

PLACE_NEAR=U1800.AP43:2.54MM

16V 402

0.01UF

20% CERM

C2572

1

2

NO STUFF

PLACE_NEAR=U1800.BB51:2.54MM

402

CERM

1UF

6.3V

10%

C2561

1

2

0

402

5%

MF-LF

1/16W

R2560

1 2

CASE-B2-SM1

220UF

POLY-TANT

2.5V

20%

PLACE_NEAR=U1800.BB51:2.54MM

C2560

1

2

NO STUFF

PLACE_NEAR=U1800.BD51:2.54MM

402

6.3V CERM

1UF

10%

C2566

1

2

PLACE_NEAR=U1800.BD51:2.54MM

220UF

POLY-TANT

CASE-B2-SM1

20%

2.5V

C2565

1

2

MF-LF

402

1/16W

0

5%

R2565

1 2

PLACE_NEAR=U1800.AE50:2.54MM

CERM

20% 16V

402

0.01UF

C2552

1

2

PLACE_NEAR=U1800.AE50:2.54MM

20%

6.3V X5R 603

10UF

C2550

1

2

X5R-CERM

22UF

Place on bottom side of U1000.

20%

603

6.3V

C2500

1

2

PLACE_NEAR=U1800.AE50:2.54MM

0603

180-OHM-1.5A

L2550

1 2

MF-LF

1/16W

5%

402

0

R2550

1 2

16V 402

20% CERM

PLACE_NEAR=U1800.AP43:2.54MM

0.01UF

C2571

1

2

PLACE_NEAR=U1800.AE50:2.54MM

10% 402

0.1UF

16V X5R

C2551

1

2

Place on bottom side of U1000.

10V 402

1UF

10% X5R

C2514

1

2

Place on bottom side of U1000.

1UF

X5R

10% 402

10V

C2513

1

2

402

Place on bottom side of U1000.

X5R

10%

1UF

10V

C2512

1

2

Place on bottom side of U1000.

1UF

X5R

10% 402

10V

C2511

1

2

Place on bottom side of U1000.

10V 402

1UF

10% X5R

C2510

1

2

D2T-SM2

20% POLY-TANT

2.0V

330UF

C2505

1

23

330UF

D2T-SM2

2.0V

20% POLY-TANT

C2506

1

23

603

X5R-CERM

PLACE_NEAR=U1800.AP43:2.54MM

22UF

20%

6.3V

C2570

1

2

10UH-0.12A-0.36OHM

0603

L2560

1 2

Place on bottom side of U1000.

6.3V X5R-CERM 603

22UF

20%

C2501

1

2

10UH-0.12A-0.36OHM

0603

L2565

1 2

402

10% X5R

1UF

10V

C2535

1

2

402

10% X5R

10V

1UF

C2534

1

2

402

10% X5R

1UF

10V

C2533

1

2

402

10% X5R

1UF

10V

C2532

1

2

402

10% X5R

1UF

10V

C2531

1

2

402

10% X5R

10V

1UF

C2530

1

2

402

10% X5R

1UF

10V

C2529

1

2

402

10% X5R

1UF

10V

C2528

1

2

Place on bottom side of U1000.

402

10% X5R

1UF

10V

C2527

1

2

Place on bottom side of U1000.

402

10% X5R

10V

1UF

C2526

1

2

1UF

Place on bottom side of U1000.

402

10V

10% X5R

C2525

1

2

Place on bottom side of U1000.

402

10% X5R

1UF

10V

C2524

1

2

402

10V

10% X5R

1UF

C2539

1

2

402

10V X5R

10%

1UF

C2538

1

2

402

10% X5R

1UF

10V

C2537

1

2

402

10% X5R

1UF

10V

C2536

1

2

20%

22UF

603

X5R-CERM

6.3V

Place on bottom side of U1000.

C2502

1

2

CPU/PCH GFX Decoupling

SYNC_MASTER=K17_WFERRY

SYNC_DATE=06/09/2009

PPVCORE_S0_GFX

PPVCORE_S0_CPU_VCAP2

PP3V3_S0_PCH

PP1V8_S0_PCH

PP3V3_S0_PCH_VCCA_DAC_F

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM VOLTAGE=3.3V

PP1V8_S0_PCH_VCCTX_LVDS

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V05_S0_PCH

MIN_NECK_WIDTH=0.2 MM

PP3V3_S0_PCH_VCCA_DAC

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM

MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_PCH_VCCADPLLA

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM

PP1V05_S0_PCH_VCCADPLLA_F

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM

PP1V05_S0_PCH_VCCADPLLB_F

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V05_S0_PCH_VCCADPLLB

VOLTAGE=1.05V

25 OF 132 24 OF 103

7

13 50 70

7

13

17 18 19 20 21 23

101

21

101

21

17 18 21 23

101

21

BI

OUT

NC

BI

OUT

IN

IN IN

IN

OUT

NC

BI

OUT

IN

OUT

IN

IN IN

OUT

IN

OUT

IN

IN IN

IN

IN IN IN IN

IN

IN IN

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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REVISION

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

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NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

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8 7 5 4 2 1

PCH OC6#

PCH OC5#

PCH OC4#

PCH OC3#

OBSFN_A0

HOOK3

SDA

NOTE: This is not the standard XDP pinout.

USE WITH 920-0782 ADAPTER FLEX TO SUPPORT PCH DEBUGGING.

OBSDATA_C2

OBSFN_B0

OBSDATA_D0

Calpella PCH mini XDP

OBSFN_D1

OBSDATA_A1

OBSDATA_A2

PCH OC0#

OBSDATA_A0

PCH GPIO16

PCH GPIO37

PCH GPIO36

ITPCLK/HOOK4 ITPCLK#/HOOK5

998-2515

1K series R on PCH Support Page

NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.

OBSFN_C0 OBSFN_C1

OBSDATA_C0 OBSDATA_C1

OBSDATA_D1

OBSDATA_D2 OBSDATA_D3

OBSFN_D0

OBSDATA_C3

DBR#/HOOK7

RESET#/HOOK6

VCC_OBS_CD

XDP_PRESENT#

TRSTn

TDO

TDI TMS

OBSDATA_B0 OBSDATA_B1

OBSDATA_D1

OBSDATA_D2

HOOK2

PCH OC2#

PCH OC7#

PCH OC1#

PCH GPIO28

PCH GPIO18

PCH GPIO20

PCH GPIO21 PCH GPIO19

PCH GPIO49

PCH GPIO0

RESET#/HOOK6 DBR#/HOOK7 NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.

TRSTn

TCK1

OBSDATA_A3

OBSDATA_B3

HOOK1

HOOK2

OBSDATA_B2

SCL

OBSFN_A1

OBSFN_B1

OBSDATA_A0 OBSDATA_A1

OBSFN_B0

OBSDATA_A3

OBSDATA_A2

OBSFN_A0 OBSFN_A1

OBSDATA_B3

PWRGD/HOOK0

HOOK1

VCC_OBS_AB

OBSDATA_B2

HOOK3

TCK1 TCK0

OBSFN_B1

OBSDATA_B0 OBSDATA_B1

SDA SCL

OBSDATA_C1

OBSDATA_C3

OBSDATA_C2

OBSFN_D1

OBSFN_D0

OBSFN_C1

OBSFN_C0

OBSDATA_D0

ITPCLK/HOOK4 ITPCLK#/HOOK5

OBSDATA_D3

XDP_PRESENT#

VCC_OBS_CD

TDO

TDI TMS

998-1571

OBSDATA_C0

PWRGD/HOOK0

TCK0

VCC_OBS_AB

Calpella Processor mini XDP

6

17 25 26 28 30 32 34 42 48 49 64 94

17

10 91

17

27 46 74 88

19

19 35

19

17

402

MF-LF

1/16W

2

1

R2615

5%

XDP

51

CRITICAL XDP_CONN

F-ST-SM

59

57

51 53 55

47 49

45

41 43

35

39

37

31 33

25 27

21 23

17

15

19

13

11

9

7

5

1 34

2

6

8 10 12 14

20

16 18

22 24 26

30

28

34

32

38 40

36

42 44 46 48 50

56

54

52

58 60

J2600

LTH-030-01-G-D-NOPEGS

29

DF40C-60DS-0.4V

J2650

F-ST-SM

7

41

39

37

35

20

36

CRITICAL XDP_CONN

3

1

5

11

9

13

17

15

23

19 21

25 27 29

33

31

43 45 47 49 51 53

59

57

55

38 40

32 34

30

28

26

24

22

16 18

10

14

12

6 8

2 4

56 58 60

54

52

50

48

46

44

42

2

1

XDP

X5R

10%

402

16V

0.1uF

C2600

2

1

C2601

XDP

X5R

0.1uF

10%

402

16V

6

17 25 26 28 30 32 34 42 48 49 64 94

10 91

10 25 27 91

10 91

21

R2611

PLACE_NEAR=U1000.N70:1.00MM

5%

MF-LF

1/16W

402

XDP

1K

10 20 91

10 91

18 25 46

10 91

XDP_NORMAL&XDP_CPU

21

R2690

MF-LF

1/16W

402

0

5%

XDP

R2610

402

1/16W MF-LF

21

5%

1K

XDP_CPU

R2695

21

5%

0

402

1/16W MF-LF

402

XDP_GMCH

21

R2696

MF-LF

1/16W

0

5%

XDP_NORMAL&XDP_GMCH

21

R2692

MF-LF

1/16W

402

0

5%

R2691

2

1

XDP_NORMAL

MF-LF

1/16W

402

0

5%

10

9

91

9

91

10 91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

8 9

91

9

91

9

91

9

91

9

91

8

1/16W SM-LF

5

6

7

4

3

2

1

RP2600

5%

0

XDP_CPU_BPM

RP2601

5

6

7

8

4

3

2

1

1/16W SM-LF

5%

0

XDP_CPU_CFG

PLACEMENT_NOTE=Place R2601 close to R2600 to minimize stubs.

10 91

9

91

9

91

9

91

9

91

20 46 47

20 31

17 40

17 33

17 42

17

27

20 88

20

20 64

SYNC_DATE=06/22/2009

SYNC_MASTER=K18_MLB

eXtended Debug Port (XDP)

CPU_CFG<15>

CPU_CFG<13>

XDP_BPM_L<3>

PCH_GPIO59

SMBUS_PCH_DATA SMBUS_PCH_CLK

TP_XDP_HOOK3

XDP_CPUPWRGD

PPCPUVTT_S0

PM_PWRBTN_L

XDP_BPM_L<7>

XDP_BPM_L<6>

XDP_BPM_L<4> XDP_BPM_L<5>

CPU_CFG<16>

CPU_CFG<17>

XDP_OBSDATA_A<3>

XDP_OBSDATA_A<2>

XDP_OBSDATA_A<1>

XDP_OBSDATA_A<0>

XDP_PRDY_L

XDP_PREQ_L CPU_CFG<8>

CPU_CFG<9>

CPU_CFG<0> CPU_CFG<1>

CPU_CFG<2> CPU_CFG<3>

CPU_CFG<11>

CPU_CFG<10>

CPU_CFG<5>

CPU_CFG<4>

CPU_CFG<6>

FSB_CLK133M_ITP_P

CPU_CFG<7>

FSB_CLK133M_ITP_N

XDP_CPURST_L XDP_DBRESET_L

XDP_TDI

XDP_TRST_L

XDP_TDO

XDP_TMS

XDP_BPM_L<0>

XDP_BPM_L<2>

XDP_BPM_L<1>

CPU_CFG<12>

CPU_CFG<14>

CPU_PWRGD

JTAG_GMCH_TDI

JTAG_CPU_TDO

JTAG_GMCH_TDO

JTAG_CPU_TDI

FSB_CPURST_L

XDPPCH_PLTRST_L XDP_DBRESET_L

TP_XDPPCH_TRST_L JTAG_PCH_TDI

ISOLATE_CPU_MEM_L SMC_IG_THROTTLE_L

AP_CLKREQ_L

FW_CLKREQ_L

SATARDRVR_A_EN

JTAG_GMUX_TCK

AUD_IPHS_SWITCH_EN ME_TEMP_ALERT_L

TP_XDPPCH_HOOK4

TP_XDPPCH_HOOK3

TP_XDPPCH_HOOK2

PCH_GPIO9

PCH_GPIO43

PCH_GPIO41

USB_HUB_SOFT_RESET_L

TP_XDPPCH_OBSFN_A<1>

TP_XDPPCH_HOOK5

JTAG_PCH_TDO

JTAG_PCH_TMS

PM_LATRIGGER_L

PCH_GPIO42

XDP_TDI

TP_XDPPCH_OBSFN_D<0>

SDCARD_RESET

TP_XDPPCH_OBSFN_D<1>

SATARDRVR_B_EN

SMBUS_PCH_DATA SMBUS_PCH_CLK

JTAG_PCH_TCK

PM_PWRBTN_L

ALL_SYS_PWRGD

PCH_GPIO10

TP_XDPPCH_OBSFN_B<1>

TP_XDPPCH_OBSFN_B<0>

PP3V3_S0

TP_XDPPCH_OBSFN_A<0>

XDP_TDO

XDP_TCK

XDP_PWRGD

26 OF 132 25 OF 103

6 7

10 12 13 15 26 40 71 74

101

91

25 91

10 25 27 91

25 91

6

17 25 26 28 30 32 34 42 48

49 64 94 6

17 25 26 28 30 32 34 42 48

49 64 94

18 25 46

6 7 8

26 27 28 30 34 37 40 42 47 48 49

52 53 55 59 63 64 69 70 71 72 73 74 81

84 85 86 88 99

101

25 91

IN

BI

IN

OUT

CPU0*

CPU0

REF_FS

USB

CPU1

CPU1*

SRC1*

SRC1

SRC0*/SATA*

SRC0/SATA

27M_NSS

27M_SS

DOT96*

XOUT

XIN

SCLK

SDATA

CK_PWRGD/PWRDWN*

VDD_SRC

VDD_CPU

VDD_REF

VDD_DOT

VDD_27

VDD_SRC_IO

VDD_CPU_IOVSS_CPU

VSS_27

VSS_DOT

THRM

VSS_SRC

VSS_REF

DOT96

27MHZ_OE*

PAD

OUT OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

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PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

NOTE: REF/FS pin is input until first CK_PWRGD rising edge. FS=0 => 133MHz BCLKs, FS=1 => 100MHz BCLKs All other output frequencies are fixed.

PCH DMI/PCIe 100MHz

GPU 27MHz Clocks (Single-Ended)

PCH SATA 100MHz

PCH BCLK 133MHz

Unused BCLK 133MHz

PCH REFCLK 14.31818MHz Unused 48MHz

PCH USB Clock 96MHz

(IPD)

Must be strapped appropriately or connected to logic for Muxed Graphics implementations.

No internal pull.

0.1UF

CERM

402

20% 10V

BYPASS=U2790::5 mm

C2790

1

2

69

74HC1G00GWDG

SC70-5

U2790

3

2

1

4

5

18pF

402

CERM

50V

5%

PLACE_NEAR=Y2730.1:2 mm:NO_VIA

C2730

1

2

14.31818

5X3.2-SM

CRITICAL

Y2730

1 2

PLACE_NEAR=Y2730.2:2 mm:NO_VIA

5% 50V CERM 402

18pF

C2731

1

2

0402

FERR-120-OHM-1.5A

L2710

1 2

FERR-120-OHM-1.5A

0402

L2700

1 2

20%

6.3V X5R 603

10UF

PLACE_NEAR=L2700.2:2 mm:NO_VIA

C2700

1

2

10UF

603

X5R

6.3V

20%

PLACE_NEAR=L2710.2:2 mm:NO_VIA

C2710

1

2

6

17 25 28 30 32 34 42 48 49 64 94

6

17 25 28 30 32 34 42 48 49 64 94

17 93

0.1UF

402

X5R

16V

10%

PLACE_NEAR=U2700.15:2 mm

C2715

1

2

0.1UF

402

X5R

16V

10%

PLACE_NEAR=U2700.18:2 mm

C2716

1

2

10% 16V X5R 402

0.1UF

PLACE_NEAR=U2700.1:2 mm

C2705

1

2

10% 16V X5R 402

0.1UF

PLACE_NEAR=U2700.5:2 mm

C2706

1

2

SL28776

QFN

CRITICAL

U2700

6

7

16

25

23

22

20

19

3

4

30

32

31

11 10

13

14

33

8

5

24

18

1

29

17

15

9212

26

12

28 27

10% 16V X5R 402

0.1UF

PLACE_NEAR=U2700.17:2 mm

C2707

1

2

10% 16V X5R 402

0.1UF

PLACE_NEAR=U2700.24:2 mm

C2708

1

2

10% 16V X5R 402

0.1UF

PLACE_NEAR=U2700.29:2 mm

C2709

1

2

17 93

74

1

2

402

R2790

10K

5% 1/16W MF-LF

Clock (CK505)

SYNC_MASTER=K17_REF

SYNC_DATE=05/19/2009

PP3V3_S0

CPUIMVP_CLK_EN_L

TP_CK505_CPU1P

PCH_CLK100M_SATA_P CK505_CLK27M TP_CK505_CLK27M_SS

CK505_27MHZ_EN_L

SMBUS_PCH_DATA

SMBUS_PCH_CLK

CK505_CLK14P3M_XOUT

CK505_CLK14P3M_XIN

CK505_CKPWRGD

TP_CK505_USB

TP_CK505_CPU1N

FSB_CLK133M_PCH_P

FSB_CLK133M_PCH_N

PPCPUVTT_S0

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

PP1V05_S0_CK505_F

MIN_LINE_WIDTH=0.3 mm

VOLTAGE=3.3V

PP3V3_S0_CK505_F

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PCIE_CLK100M_PCH_N PCIE_CLK100M_PCH_P

PCH_CLK100M_SATA_N

PCH_CLK96M_DOT_N PCH_CLK96M_DOT_P

PCH_CLK14P3M_REFCLK

27 OF 132 26 OF 103

6 7 8

25 27 28 30 34 37 40 42 47 48 49

52 53 55 59 63 64 69 70 71 72 73 74 81

84 85 86 88 99

101

27

6 7

10 12 13 15 25 40 71 74

101

IN

OUT

IN

OUT

IN

OUT

NC NC

OUT

IN

OUT

IN

NC NC

OUT

IN

OUT

IN

OUT

IN

OUT

BI

OUT

D

GS

OUT

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PCH RTC Crystal

PCH 25MHz Crystal

Ethernet WAKE# Isolation

PCH S0 PWRGD

Platform Reset Connections

Unbuffered

VTT voltage divider on CPU page

Series R is R4283

PCH Reset Button

Buffered

Caesar II (ENET) 25MHz Crystal

10 25 91

5%

402

50V

CERM

12pF

C2810

1 2

CERM

5%

402

50V

12pF

C2811

1 2

32.768K

CRITICAL

SM-2

Y2810

2 4

1 3

402

MF-LF

0

1/16W

5%

R2810

1 2

402

MF-LF

10M

5%

R2811

1

2

1/16W

XDP

MF-LF

5%

0

1/16W

R2896

1 2

402

MF-LF

402

1/16W

33

5%

R2883

1 2

1/16W

33

MF-LF

402

5%

R2881

1 2

6

27 48 88 94

46

33

17

19 27 31 40

22

5%

MF-LF

1/16W

402

R2826

1 2

PLACE_NEAR=U1800.P53:5mm

22

402

1/16W MF-LF

5%

R2825

1 2

PLACE_NEAR=U1800.N52:5mm

19 94

12pF

50V 402

5%

CERM

C2815

1 2

5%

50V

12pF

CERM

402

C2816

1 2

SM-3.2X2.5MM

25.0000M

CRITICAL

Y2815

2 4

1 3

MF-LF

1/16W

5%

0

402

R2815

1 2

DCI

402

1/16W MF-LF

10M

5%

R2816

1

2

17

32

0

MF-LF

5%

402

1/16W

R2871

1 2

C2850

402

20% CERM

0.1UF

10V

1

2

25 46 74 88

69

6

48 94

46 94

18

MC74VHC1G08

SC70-HF

U2850

3

2

1

4

5

19

CERM

50V

5%

402

27pF

C2820

1 2

50V

5%

CERM

402

27pF

C2821

1 2

CRITICAL

25.0000M

SM-3.2X2.5MM

Y2820

2 4

1 3

1/16W

402

5%

MF-LF

200

R2820

1 2

402

NO STUFF

5%

MF-LF

10M

R2821

1

2

1/16W

37 95

88

22

5% 1/16W MF-LF

402

R2827

1 2

PLACE_NEAR=U1800.P46:5mm

25

5%

MF-LF

402

1/16W

XDP

1K

R2889

1 2

5%

0

1/16W MF-LF

402

R2888

1 2

34

0

5%

MF-LF

1/16W

402

R2884

1 2

CERM

20% 10V

402

0.1UF

C2880

1

2

SC70-HF

MC74VHC1G08

U2880

3

2

1

4

5

402

100K

5% MF-LF

1/16W

R2880

1

2

R2850

10K

5%

402

1/16W MF-LF

2

1

37 95

0

5% MF-LF

402

1/16W

R2882

1 2

17 93

22

402

MF-LF

1/16W

5%

R2829

1 2

PLACE_NEAR=U1800.P48:5mm

19

19 27

27 88

MF-LF

1/16W

5%

402

0

R2887

1 2

SILK_PART=SYS RESET

MF-LF

1/16W 402

5%

0

OMIT

R2897

1

2

6

27 48 88 94

0

1/16W

5% MF-LF

402

1 2

R2824

PLACE_NEAR=U2700.6:5mm

26 27

90

402

1/16W MF-LF

5%

0

R2893

1 2

10K

MF-LF

1/16W 402

5%

R2895

1

2

80 81 98

6

18 46

19 27 31 40

SSM3K15FV

SOD-VESM-HF

Q2830

3

1

2

6

18 33 34 27 37

10K

5%

402

1/16W MF-LF

R2830

1

2

10 27

SYNC_DATE=06/17/2009

SYNC_MASTER=K17_REF

Chipset Support

MAKE_BASE=TRUE

ENET_WAKE_L

XDP_DBRESET_L

PM_SYSRST_L

PP3V3_S0

GMUX_RESET_L

MAKE_BASE=TRUE

BKLT_PLT_RST_L

PLT_RESET_L

MAKE_BASE=TRUE

GMUX_RESET_L

PCH_CLK32K_RTCX1

ENET_RESET_L

AP_RESET_L

LPCPLUS_RESET_L

MAKE_BASE=TRUE

PLT_RST_BUF_L

EXCARD_RESET_L

PLT_RESET_L

PCA9557D_RESET_L

XDPPCH_PLTRST_L

PLT_RST_BUF_L

MAKE_BASE=TRUE

PM_PCH_PWRGD

ALL_SYS_PWRGD

CPUIMVP_PGOOD

PP3V3_S0

SMC_LRESET_L

LPC_CLK33M_SMC

LPC_CLK33M_LPCPLUS

PCH_CLK33M_PCIIN

GPU_CLK27M

MAKE_BASE=TRUEMAKE_BASE=TRUE

CK505_CLK27M

LPC_CLK33M_GMUX_R

CK505_CLK27M

PCH_CLK32K_RTCX2_R

BCM5764_CLK25M_XTALO_R

PCH_CLK32K_RTCX2

PCH_CLK25M_XTALOUT

BCM5764_CLK25M_XTALO

ENET_WAKE_L

BCM5764_CLK25M_XTALI

PP3V3_ENET

PCIE_WAKE_L

LPC_CLK33M_GMUX

LPC_CLK33M_LPCPLUS_R

LPC_CLK33M_SMC_R

PCH_CLK25M_XTALIN

PCH_CLK25M_XTALOUT_R

PCH_CLK33M_PCIOUT

MAKE_BASE=TRUE

LPC_CLK33M_GMUX_R

28 OF 132 27 OF 103

27 37

6 7 8

25 26 27 28 30 34 37 40 42 47 48

49 52 53 55 59 63 64 69 70 71 72 73 74

81 84 85 86 88 99

101

27 88

10 27

6 7 8

25 26 27 28 30 34 37 40 42 47

48 49 52 53 55 59 63 64 69 70 71 72

73 74 81 84 85 86 88 99

101

6 7 8

25 26 27 28 30 34 37 40 42 47 48

49 52 53 55 59 63 64 69 70 71 72 73 74

81 84 85 86 88 99

101

26 27

7

37 74

19 27

A6

A7

A11

A5

DQ33

VDD A10/AP

VDD

VSS

SA1 VTT

VSS

DQS4* DQS4 VSS

DQ35

VSS

CK0*

SA0

VSS DQ58 DQ59

DM7

VSS

DQ57

DQ56

DQ50 DQ51

VSS

DQS6* DQS6

VSS

DQ49

DQ48

DQ43 VSS

DM5 VSS DQ42

SDA SCL

VTT

VSS

EVENT*

DQ62

VSS

DQ63

DQS7*

DQS7

DQ60 DQ61

VSS

DQ55

DQ54

DM6

VSS

DQ53

VSS

DQ52

DQ47

VSS

DQS5

VSS

DQ46

DQ41

VSS DQ40

DQ34

VSS

DQ32

TEST

VDD

S1*

A13

CAS*

WE*

BA0 VDD

VDD CK0

A1

A3

VDD

VDD A8

A9

A12/BC*

VDD

BA2

NC

VDD

CKE0

VSS

DQS5*

VSS DQ44 DQ45

DQ39

DQ38

VSS

DM4

VSS

DQ37

DQ36

VREFCA

VDD ODT1

NC

S0*

ODT0

BA1

RAS*

VDD

CK1*

VDD

A0

CK1

A2

VDD

A4

VDD

A14

A15

CKE1

VDD

VSS

VDDSPD

KEY

(SYMBOL 2 OF 2)

BI BIBI

BI

IN

BI BI

IN

BI

IN

BI

BI BI

IN

BI BI

DQ16

DM3

DQ26 DQ27

DQ4

DQ31

DQ30

DQS3

DQS3*

DQ29

DQ28

DQ23

DQ22

DM2

DQ21

DQ20

DQ15

DQ14

RESET*

DM1

DQ13

DQ12

DQ7

DQ6

DQS0

DQS0*

DQ5

DQ24 DQ25

DQ19

DQ18

DQS2

DQS2*

DQ17

DQ11

DQ10

DQS1

DQS1*

DQ8 DQ9

DM0

DQ0 DQ1

VREFDQ

DQ3

DQ2

VSS

KEY

VSS

(SYMBOL 1 OF 2)

IN

BI BI

BI

BI BI

BI

IN IN

IN

IN IN

IN

BI BI

IN

BI BI

IN

BI

IN

BI BI

BI

IN

BI BI

BI

OUT

BI IN

IN

IN IN

BI BI

BI

IN

BI

BI BI

IN

BI BI

NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)

- =PP1V5_S3_MEM_A

Signal aliases required by this page:

SPD ADDR=0xA0(WR)/0xA1(RD)

BOM options provided by this page:

- =PPSPD_S0_MEM_A (2.5 - 3.3V)

- =PP1V5_S0_MEM_A

- =PP0V75_S0_MEM_VTT_A

(NONE)

"Factory" (top) slot

Power aliases required by this page:

- =I2C_SODIMMA_SCL

- =I2C_SODIMMA_SDA

Page Notes

516-0229

J2900

DDR3-SODIMM-DUAL-K6

F-RT-THB

199

185

76

74

78 80 82

88

92 94 96

102

98 100

106

104

112

110

108

116

114

122

120

118

126

130 132

128

136

134

138 140 142

148

146

144

152

150

73 75 77 79 81 83 85

89

87

93 95 97

101

99

111

109

113 115

119 121

117

123 125

129

133

141

147

145

149

158

156

154

162

160

164

168

166

172

170

174 176 178

184

182

180

188

186

194

190 192

198

196

204

202

200

157

155

153

161

159

163 165 167

171

169

173

177

175

181 183

179

187

193

191

189

197

103

151

143

139

137

135

127

203

201

195

124

107

105

131

91

84 86

90

29

C2931

2

1

0.1UF

CERM 402

20% 10V

2

1

C2930

6.3V CERM 402-LF

20%

2.2UF

29

11 92

11 29 92

29

30 31

29

CRITICAL

J2900

DDR3-SODIMM-DUAL-K6

F-RT-THB 15 17

3

1

7

5

9 11 13

19

23

21

25 27 29

33

31

35

43

41

45

49

47

51 53 55

59

57

2

6 8 10 12 14 16 18 20 22 24 26 28 30

34

32

36 38 40

44

42

46 48 50

54

52

56 58 60 62 64 66 68 70 72

4

71

69

67

65

63

61

39

37

11 29 92

29

11 92

29

11 92

11 29 92

29

2

1

C2936

10V

20%

402

CERM

0.1UF

2

1

402-LF

20%

6.3V CERM

2.2UF

C2935

29

30 46 47

6

17 25 26 30 32 34 42 48 49 64

94

6

17 25 26 30 32 34 42 48 49 64

94

11 92

29

2

1

R2941

10K

5%

402

1/16W MF-LF

2

1

R2940

MF-LF

1/16W

5%

10K

402

2

1

2.2UF

20%

CERM 402-LF

6.3V

C2940

2

1

603

X5R

20%

10UF

C2900

6.3V

1

6.3V

20%

2

C2901

10UF

X5R 603

2

1

C2910

CERM 402

10V

20%

0.1UF

2

1

C2911

0.1UF

402

CERM

20% 10V

2

1

C2912

CERM

0.1UF

20% 10V

402

2

1

C2913

402

CERM

10V

20%

0.1UF

2

1

C2914

10V 402

CERM

20%

0.1UF

2

1

C2915

0.1UF

20%

402

CERM

10V

2

1

C2916

10V

0.1UF

20%

402

CERM

2

1

C2917

10V

0.1UF

20%

402

CERM

2

1

C2918

10V

0.1UF

20%

402

CERM

2

1

C2919

10V

0.1UF

20%

402

CERM

2

1

C2920

10V

20%

402

CERM

0.1UF

2

1

C2921

10V

0.1UF

20%

402

CERM

2

1

C2922

10V

0.1UF

20%

402

CERM

2

1

C2923

10V

0.1UF

20%

402

CERM

SYNC_MASTER=K17_REF

SYNC_DATE=05/13/2009

DDR3 SO-DIMM Connector A

PP1V5_S3

=MEM_A_DQ<11>

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=MEM_A_DQ<21>

=MEM_A_DQS_N<1>

=MEM_A_DQ<9>

=MEM_A_DQ<32>

=MEM_A_DQ<25>

=MEM_A_DQ<60>

PP3V3_S0

=MEM_A_DQS_N<4>

MEM_A_SA<0>

=MEM_A_DQ<13>

=MEM_A_DQ<4>

=MEM_A_DQ<2>

PP0V75_S3_MEM_VREFCA_A

=MEM_A_DQ<3>

MEM_A_DM<0>

=MEM_A_DQ<10>

=MEM_A_DQ<17>

=MEM_A_DQS_N<2>

=MEM_A_DQ<18> =MEM_A_DQ<19>

=MEM_A_DQ<24>

=MEM_A_DQ<5>

MEM_A_DQS_N<0> MEM_A_DQS_P<0>

=MEM_A_DQ<6> =MEM_A_DQ<7>

=MEM_A_DQ<12>

=MEM_A_DM<1> MEM_RESET_L

=MEM_A_DQ<14> =MEM_A_DQ<15>

=MEM_A_DQ<20>

=MEM_A_DQ<22> =MEM_A_DQ<23>

=MEM_A_DQ<28> =MEM_A_DQ<29>

=MEM_A_DQS_N<3> =MEM_A_DQS_P<3>

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=MEM_A_DQ<16>

MEM_A_A<15> MEM_A_A<14>

MEM_A_A<4>

MEM_A_A<2>

MEM_A_CLK_P<1>

MEM_A_A<0>

MEM_A_CLK_N<1>

MEM_A_RAS_L

MEM_A_BA<1>

MEM_A_ODT<0>

MEM_A_CS_L<0>

MEM_A_ODT<1>

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MEM_A_A<8>

MEM_A_A<3> MEM_A_A<1>

MEM_A_WE_L MEM_A_CAS_L

MEM_A_CS_L<1>

=MEM_A_DQ<34>

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MEM_EVENT_A_L

SMBUS_PCH_CLK

SMBUS_PCH_DATA

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MEM_A_CLK_N<0>

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MEM_A_SA<1>

MEM_A_A<10>

=MEM_A_DQ<33>

MEM_A_A<5>

MEM_A_A<11> MEM_A_A<7>

MEM_A_A<6>

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MEM_A_CKE<1>

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MEM_A_A<12>

MEM_A_BA<2>

MEM_A_CKE<0>

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MEM_A_BA<0>

MEM_A_CLK_P<0>

MEM_A_A<9>

MEM_A_A<13>

PP0V75_S0_DDRVTT

=MEM_A_DM<7>

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PP0V75_S3_MEM_VREFDQ_A

29 OF 132 28 OF 103

7

30 31 68 73

6 7 8

25 26 27

30 34 37 40 42 47 48 49

52 53 55 59 63

64 69 70 71 72 73 74 81

84 85 86 88 99

101

32

7

30 31 68

32

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

CPU CHANNEL B DQS 3 -> DIMM B DQS 3

CPU CHANNEL B DQS 4 -> DIMM B DQS 4

CPU CHANNEL B DQS 5 -> DIMM B DQS 5

CPU CHANNEL A DQS 0 -> DIMM A DQS 0

CPU CHANNEL B DQS 2 -> DIMM B DQS 2

CPU CHANNEL B DQS 1 -> DIMM B DQS 1

CPU CHANNEL B DQS 0 -> DIMM B DQS 0

CPU CHANNEL B DQS 7 -> DIMM B DQS 7

CPU CHANNEL A DQS 1 -> DIMM A DQS 1

CPU CHANNEL A DQS 4 -> DIMM A DQS 4

CPU CHANNEL A DQS 7 -> DIMM A DQS 7

CPU CHANNEL A DQS 6 -> DIMM A DQS 6

CPU CHANNEL A DQS 3 -> DIMM A DQS 3

CPU CHANNEL A DQS 2 -> DIMM A DQS 2

CPU CHANNEL A DQS 5 -> DIMM A DQS 5

CPU CHANNEL B DQS 6 -> DIMM B DQS 6

SYNC_DATE=06/19/2009

SYNC_MASTER=K18_MLB

DDR3 Byte/Bit Swaps

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MEM_B_DQ<42>

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MEM_B_DQ<47>MEM_A_DQ<47>

MAKE_BASE=TRUE

=MEM_B_DQ<58>

MEM_A_DQ<35>

MAKE_BASE=TRUE

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=MEM_A_DQ<18>

MAKE_BASE=TRUE

MEM_A_DQ<24>

MEM_A_DQ<39>

MAKE_BASE=TRUE

MEM_B_DQ<5>

MAKE_BASE=TRUE

MEM_B_DQ<13>

MAKE_BASE=TRUE

MEM_B_DQ<45>

MEM_A_DQ<25>

MAKE_BASE=TRUE

MEM_A_DM<3> MEM_A_DQ<31>

MAKE_BASE=TRUE

MEM_A_DQ<28>

MAKE_BASE=TRUE

MEM_A_DQ<34>

MAKE_BASE=TRUE

MEM_A_DQ<43>

MAKE_BASE=TRUE

MEM_A_DQ<45>

MAKE_BASE=TRUE

MEM_A_DQ<46>

MAKE_BASE=TRUE

MEM_A_DQS_N<6>

MAKE_BASE=TRUE

MEM_A_DQS_N<7>

MAKE_BASE=TRUE

MEM_A_DQ<18>

MAKE_BASE=TRUE

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MAKE_BASE=TRUE

MEM_B_DQ<30>

=MEM_B_DQ<29>

=MEM_B_DM<4>

MAKE_BASE=TRUE

MEM_B_DM<6>

MEM_A_DQ<30>

MAKE_BASE=TRUE

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=MEM_A_DQ<16>

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MEM_A_DQ<21>

MAKE_BASE=TRUE

MEM_A_DQ<22>

MEM_A_DM<2>

MAKE_BASE=TRUE

MEM_A_DQS_P<2>

MAKE_BASE=TRUE

MEM_B_DQ<28>

MEM_A_DQS_N<0>

MEM_A_DQ<53>

MAKE_BASE=TRUE

MEM_A_DQS_P<7>

MEM_A_DQ<62>

MAKE_BASE=TRUE

MEM_A_DM<7>

MEM_A_DQ<61>

MAKE_BASE=TRUE

MEM_A_DQ<60>

MAKE_BASE=TRUE

MEM_A_DQ<57>

MAKE_BASE=TRUE

MEM_A_DQ<56>

MAKE_BASE=TRUE

MEM_A_DQ<58>

MAKE_BASE=TRUE

MEM_A_DQ<59>

MAKE_BASE=TRUE

MEM_A_DQ<63>

MAKE_BASE=TRUE

MEM_A_DQ<48>

MEM_A_DM<5>

MAKE_BASE=TRUE

MEM_A_DQ<44>

MAKE_BASE=TRUE

MEM_A_DQ<42>

MAKE_BASE=TRUE

MEM_A_DQ<41>

MAKE_BASE=TRUE MAKE_BASE=TRUE

MEM_A_DQ<40>

MEM_A_DQS_P<6>

MAKE_BASE=TRUE MAKE_BASE=TRUE

MEM_A_DM<6> MEM_A_DQ<55>

MAKE_BASE=TRUE

MEM_A_DQ<52>

MAKE_BASE=TRUE

MEM_A_DQ<54>

MEM_A_DQ<50>

MAKE_BASE=TRUE

MEM_A_DQ<51>

MAKE_BASE=TRUE

MEM_A_DQ<49>

MEM_A_DQ<26>

MAKE_BASE=TRUE

MEM_A_DQ<27>

MAKE_BASE=TRUE

MEM_A_DQS_N<4>

MAKE_BASE=TRUE

MEM_A_DM<4>

MAKE_BASE=TRUE

MEM_A_DQS_P<4>

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MEM_A_DQ<37>

MAKE_BASE=TRUE

MEM_A_DQ<38>

MAKE_BASE=TRUE

MEM_A_DQ<36>

MAKE_BASE=TRUE

MEM_A_DQ<32>

MAKE_BASE=TRUE

MEM_A_DQ<33>

MAKE_BASE=TRUE

MEM_A_DQS_N<5> MEM_A_DQS_P<5>

MAKE_BASE=TRUE

MEM_A_DQS_N<2>

MEM_A_DQ<23>

MAKE_BASE=TRUE

MEM_A_DQ<20>

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MEM_A_DQ<19>

MAKE_BASE=TRUE

MEM_A_DQ<16>

MAKE_BASE=TRUE

MEM_A_DQS_N<3> MEM_A_DQS_P<3>

MAKE_BASE=TRUE

MEM_A_DQ<29>

MAKE_BASE=TRUE

MEM_A_DQ<17>

MAKE_BASE=TRUE

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MEM_A_DQ<37>

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MEM_A_DQ<3>

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MEM_A_DQ<0>

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MEM_A_DM<1>

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MEM_A_DQS_P<1>

MAKE_BASE=TRUE

MEM_A_DQ<15>

MAKE_BASE=TRUE

MEM_A_DQ<12>

MAKE_BASE=TRUE

MEM_A_DQ<10>

MAKE_BASE=TRUE

MEM_A_DQ<9>

MAKE_BASE=TRUE

MEM_A_DQS_N<1>

MAKE_BASE=TRUE

MEM_A_DQ<8>

MEM_A_DQ<13>

MAKE_BASE=TRUE

MEM_A_DQ<14>

MAKE_BASE=TRUE

MEM_A_DQ<2>

MAKE_BASE=TRUE

MEM_A_DQ<7> MEM_A_DQ<6>

MAKE_BASE=TRUE

MEM_A_DQ<5>

MAKE_BASE=TRUE

MEM_A_DQ<11>

MEM_A_DQ<1>

MAKE_BASE=TRUE

MEM_A_DQS_P<0>

MAKE_BASE=TRUE

MEM_A_DQS_N<0>

MAKE_BASE=TRUE

MEM_A_DM<0>

MEM_A_DQS_P<0> MEM_A_DM<0>

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=MEM_A_DQ<9>

=MEM_A_DQ<8>

=MEM_A_DQ<14>

=MEM_A_DQ<12>

=MEM_A_DQ<10>

=MEM_A_DQ<0> =MEM_A_DQ<2>

=MEM_A_DQ<5>

=MEM_A_DQS_P<1> =MEM_A_DM<1> =MEM_A_DQ<11>

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MEM_B_DQS_P<0>

=MEM_B_DQ<2>

=MEM_B_DQ<3> =MEM_B_DQ<1> =MEM_B_DQ<5> =MEM_B_DQ<0>

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MEM_B_DQ<11>

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MEM_B_DQ<10>

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MEM_B_DQ<18>

MAKE_BASE=TRUE

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MEM_B_DQ<17>

MAKE_BASE=TRUE

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MEM_B_DQ<31>

MAKE_BASE=TRUE

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MAKE_BASE=TRUE

MEM_B_DQ<26>

=MEM_B_DQ<30>

MAKE_BASE=TRUE

MEM_B_DQ<27>

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MAKE_BASE=TRUE

MEM_B_DQ<25>

=MEM_B_DQS_N<4>

MAKE_BASE=TRUE

MEM_B_DQS_N<4>

=MEM_B_DQ<35>

MAKE_BASE=TRUE

MEM_B_DQ<39>

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MEM_B_DQS_P<4>

MAKE_BASE=TRUE

=MEM_B_DQ<38>

MEM_B_DQ<38>

MAKE_BASE=TRUE

MEM_B_DQ<37>

MAKE_BASE=TRUE

MEM_B_DQ<37>

MAKE_BASE=TRUE

MEM_B_DQ<34>

MAKE_BASE=TRUE

MEM_B_DQ<35>

=MEM_B_DQ<32>

MAKE_BASE=TRUE

MEM_B_DQ<36>

MAKE_BASE=TRUE

MEM_B_DQ<33>

=MEM_B_DQ<36>

MAKE_BASE=TRUE

MEM_B_DQ<32>

=MEM_B_DQS_N<5> =MEM_B_DQS_P<5>

MAKE_BASE=TRUE

MEM_B_DQS_P<5>

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MEM_B_DM<5>

MAKE_BASE=TRUE

MEM_B_DQ<46>

MEM_B_DQ<44>

MAKE_BASE=TRUE MAKE_BASE=TRUE

MEM_B_DQ<43>

MAKE_BASE=TRUE

MEM_B_DQ<40>

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MEM_B_DQ<41>

MAKE_BASE=TRUE

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MEM_B_DQS_N<6>

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MEM_B_DQS_P<6>

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MEM_B_DQ<55>

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MEM_B_DQ<54>

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MEM_B_DQ<53>

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MEM_B_DQ<52>

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MEM_B_DQ<51>

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MEM_B_DQ<50>

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MEM_B_DQ<49>

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MEM_B_DQS_P<7>

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MEM_B_DQS_N<7>

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MEM_B_DQ<62>

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MEM_B_DQ<57>

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MEM_A_DQ<4>

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MEM_B_DQ<6>

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MEM_B_DM<0>

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MEM_B_DQ<0>

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MEM_B_DQS_P<1>

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MEM_B_DQ<2>

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MEM_B_DQ<3>

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MEM_B_DQS_N<1>

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MEM_B_DQ<1>

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MEM_B_DQ<14>

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MEM_B_DQ<20>

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MEM_B_DM<1>

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MEM_B_DQ<15>

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MEM_B_DQS_N<2>

MEM_B_DQ<9>

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MEM_B_DQ<12>

MEM_B_DQ<8>

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MEM_B_DQ<19>

MEM_B_DQS_P<3>

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MEM_B_DM<3>

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MEM_B_DQ<22>

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MEM_B_DQ<23>

MEM_B_DM<0>

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MEM_B_DQS_P<0>

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MEM_B_DQS_N<0>

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MEM_B_DQS_N<3>

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MEM_B_DQ<24>

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MEM_B_DM<4>

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MEM_B_DQS_N<5>

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MEM_B_DQ<29>

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30 OF 132 29 OF 103

30

30 11 92

11 92 11 92

30

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28

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30

11 92

30

11 92

28

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11 28 29 92

11 92

11 28 29 92

11 92

28

11 28 29 92

28

11 92

11 28 29 92

28

11 29 30 92

30

30 11 92

30

11 92

30 11 92

30

11 92

30

11 92

30

11 92

30

11 92

30 11 92

11 29 30 92 11 29 30 92

11 92

30 11 92

11 92

30 11 92

30

30 11 92

30

30 11 92

11 92

30 11 92

30

30 11 92

11 92

30 11 92

11 92

30 11 92

11 92

30 11 92

30

11 92

30

11 92

30

11 29 30 92

11 92

11 29 30 92

11 92

30

11 92

30

11 92

30

11 92

30

11 92

11 29 30 92

11 92

30

11 92

28

IN

BI

BI BI

OUT

BI IN

IN

IN IN

IN

IN IN

BI BI

BI

IN

BI BI

IN

BI BI

NC

IN

VDD

A1

A3

VDD

A5

A8

VDD

A9

VDD

A12/BC*

VSS

DQ42 DQ43

DQ48 DQ49

VSS

DQ41

DQS4*

DM5

VDD

CKE1

A15 A14

VDD

A11

A7

A6

VDD

A4

A2

CK1

A0

VDD

CK1*

VDD

RAS*

BA1

ODT0

S0*

NC

ODT1

VDD

VREFCA

VDD

DQ36 DQ37

VSS

DM4

VSS

VSS DQ38 DQ39

DQ45

DQ44

VSS

DQS5*

VSS

CKE0

VDD NC

BA2

CK0

VDD

BA0

WE*

A13 S1*

VDD

TEST

DQ33

DQ32

VSS

DQ34

DQ40

VSS

DQ46

VSS

DQS5

VSS

DQ47

DQ52

VSS

DQ53

VSS

DM6

DQ54 DQ55

VSS

DQ61

DQ60

DQS7

DQS7*

DQ63

VSS DQ62

EVENT*

VSS

VTT

SCL

SDA

VSS

DQS6

DQS6*

VSS

DQ51

DQ50

A10/AP

VDD

CK0*

DQ35

VSS

DQS4

VSS

CAS*

VDD

DM7

VSS

DQ56

MTG PIN

MTG PIN MTG PIN MTG PIN MTG PIN

MTG PIN

VSS

DQ57

VTT

SA1

SA0

DQ58

VSS

DQ59

VSS

VDDSPD

MTG PIN

MTG PINS

KEY

(2 OF 2)

BI BI

IN

BI

IN

BI

BI BI

IN

BI BI

BI

DQ2 DQ3

VREFDQ

DQ1

DQ0

DM0

DQ9

DQ8

DQS1* DQS1

DQ10 DQ11

DQ17

DQS2* DQS2

DQ18 DQ19

DQ25

DQ24

DQ5

DQS0*

DQS0

DQ6 DQ7

DQ12 DQ13

DM1

RESET*

DQ14 DQ15

DQ20 DQ21

DM2

DQ22 DQ23

DQ28 DQ29

DQS3*

DQS3

DQ30 DQ31

DQ4

DQ27

DQ26

DM3

DQ16

(1 OF 2)

VSS

KEY

VSS

IN

BI BI

BI

BI BI

IN IN

IN

BI

IN

IN IN

BI BI

IN

BI BI

IN

BI BI

IN

BI

BI BI

BI

IN

BI

BI BI

BI

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

516s0806

Power aliases required by this page:

DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)

Page Notes

- =PP0V75_S0_MEM_VTT_B

(NONE)

BOM options provided by this page:

- =I2C_SODIMMB_SDA

- =I2C_SODIMMB_SCL

Signal aliases required by this page:

"Expansion" (bottom) slot

- =PP1V5_S0_MEM_B

- =PP1V5_S3_MEM_B

- =PPSPD_S0_MEM_B (2.5 - 3.3V)

SPD ADDR=0xA4(WR)/0xA5(RD)

11 92

29

28 46 47

6

17 25 26 28 32 34 42 48 49 64

94

6

17 25 26 28 32 34 42 48 49 64

94

2

1

C3131

0.1UF

CERM 402

20% 10V

11 92

29

11 29 92

29

2

1

C3130

2.2UF

20%

6.3V

402-LF

CERM

1 2

402

5%

MF-LF

1/16W

10K

R3141

10K

5% 1/16W MF-LF 402

R3140

1

2

20%

CERM 402-LF

6.3V

2.2UF

C3140

1

2

1

C3100

10UF

20% X5R

603

6.3V 2

1

C3101

6.3V

10UF

X5R 603

20%

2

1

C3110

CERM 402

10V

20%

0.1UF

2

1

C3111

0.1UF

402

CERM

10V

20%

2

1

C3112

CERM

0.1UF

20% 10V

402

2

1

C3113

CERM 402

0.1UF

10V

20%

29

2

1

C3114

0.1UF

10V 402

CERM

20%

2

1

C3115

10V CERM

0.1UF

20%

402

2

1

C3116

10V

0.1UF

20%

402

CERM

2

1

C3117

10V

0.1UF

20%

402

CERM

2

1

C3118

10V

0.1UF

20%

402

CERM

2

1

C3119

10V

0.1UF

20%

402

CERM

2

1

C3120

10V

20%

402

CERM

0.1UF

2

1

C3121

10V

0.1UF

20%

402

CERM

2

1

C3122

10V

0.1UF

20%

402

CERM

2

1

C3123

10V

0.1UF

20%

402

CERM

29

11 92

DDR3-SODIMM

F-RT-BGA6

205

199

195

193

189 191

197

201 203

183

179

206

212211

210209

207 208

181

185 187

94

115

127

137 139

143

103 105 107

175 177

173

169 171

155

200 202 204

196 198

192

190

194

186 188

180 182 184

178

176

174

170 172

166 168

164

160 162

154 156 158

145 147

141

133

129 131

125

123

117

121

119

113

109 111

101

79

77

75

73

150 152

144 146 148

142

140

138

134 136

128

132

130

124 126

118 120 122

114 116

108 110 112

104 106

100

98

102

96

92

88 90

86

84

82

80

78

74 76

153

135

149 151

167

165

163

159

157

161

83

81

85 87 89 91 93 95 97 99

J3100

OMIT

11 29 92

29

28 31

29

CRITICAL

DDR3-SODIMM

J3100

F-RT-BGA6

37 39

61 63 65 67 69 71

4

72

70

68

66

64

62

60

58

56

52 54

50

48

46

42 44

40

38

36

32 34

30

28

26

24

22

20

18

16

14

12

10

8

6

2

57 59

55

53

51

47 49

45

41 43

35

31 33

29

27

25

21 23

19

13

11

9

5 7

1 3

17

15

OMIT

11 29 92

29

11 92

29

11 92

29

11 92

29

2

1

C3136

20%

0.1UF

10V

402

CERM

2

1

C3135

402-LF

20%

CERM

6.3V

2.2UF

29

DDR3 SO-DIMM Connector B

SYNC_DATE=06/09/2009

SYNC_MASTER=K17_WFERRY

MEM_B_SA<1>

=MEM_B_DQS_P<4>

MEM_B_DQ<37> =MEM_B_DQ<35>

=MEM_B_DM<5>

PP1V5_S3

MEM_B_ODT<0>

PP0V75_S3_MEM_VREFCA_B

=MEM_B_DQ<24>

=MEM_B_DQ<18> =MEM_B_DQ<19>

=MEM_B_DM<3>

=MEM_B_DQ<27>

=MEM_B_DQ<36>

=MEM_B_DQ<9>

MEM_B_ODT<1>

=MEM_B_DQS_P<6>

=MEM_B_DQ<50>

=MEM_B_DQ<57>

=MEM_B_DQ<47>

=MEM_B_DQ<48> =MEM_B_DQ<49>

=MEM_B_DQS_N<6>

=MEM_B_DQ<51>

=MEM_B_DQ<54> =MEM_B_DQ<55>

=MEM_B_DQ<60>

=MEM_B_DQS_N<7>

PP0V75_S0_DDRVTT

MEM_RESET_L

=MEM_B_DQ<23>

=MEM_B_DQ<22>

=MEM_B_DQ<31>

=MEM_B_DQ<30>

=MEM_B_DQS_P<3>

=MEM_B_DQS_N<3>

=MEM_B_DQ<29>

=MEM_B_DQ<28>

=MEM_B_DQ<21>

=MEM_B_DQ<13>

=MEM_B_DQ<15>

=MEM_B_DQ<14>

=MEM_B_DQ<20>

=MEM_B_DQ<25>

=MEM_B_DQS_P<2>

=MEM_B_DQS_N<2>

=MEM_B_DQ<16>

=MEM_B_DQ<37>

=MEM_B_DQS_N<5> =MEM_B_DQS_P<5>

=MEM_B_DQ<46>

=MEM_B_DQ<43>

=MEM_B_DQ<42>

=MEM_B_DQ<53>

=MEM_B_DQ<61>

=MEM_B_DQ<62>

=MEM_B_DQ<45>

SMBUS_PCH_DATA

=MEM_B_DQ<59>

=MEM_B_DQ<56>

=MEM_B_DQ<33>

=MEM_B_DQS_N<4>

=MEM_B_DQ<32>

MEM_B_A<5>

=MEM_B_DQS_P<7>

MEM_B_A<1>

MEM_B_CLK_N<0>

MEM_B_A<3> MEM_B_A<2>

MEM_B_A<4>

MEM_B_A<0>

MEM_B_BA<1> MEM_B_RAS_L

MEM_B_A<10>

SMBUS_PCH_CLK

MEM_EVENT_A_L

=MEM_B_DQ<63>

=MEM_B_DM<6>

=MEM_B_DQ<52>

=MEM_B_DQ<40>

MEM_B_WE_L

MEM_B_CLK_P<0>

=MEM_B_DQ<44>

=MEM_B_DQ<39>

=MEM_B_DQ<38>

=MEM_B_DM<4>

MEM_B_CS_L<0>

MEM_B_CLK_P<1>

MEM_B_A<6>

MEM_B_A<7>

MEM_B_A<11>

MEM_B_A<14>

MEM_B_A<15>

MEM_B_CKE<1>

=MEM_B_DQ<26>

=MEM_B_DQ<4>

=MEM_B_DM<1>

=MEM_B_DQ<7>

=MEM_B_DQ<6>

MEM_B_DQS_P<0>

MEM_B_DQS_N<0>

=MEM_B_DQ<5>

=MEM_B_DQ<10>

=MEM_B_DQS_P<1>

=MEM_B_DQS_N<1>

MEM_B_DM<0>

=MEM_B_DQ<0> =MEM_B_DQ<1>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_BA<2>

MEM_B_CS_L<1>

MEM_B_A<13>

MEM_B_CAS_L

MEM_B_BA<0>

MEM_B_A<8>

=MEM_B_DQ<41>

MEM_B_CKE<0>

=MEM_B_DQ<12>

=MEM_B_DM<2>

=MEM_B_DQ<17>

MEM_B_CLK_N<1>

MEM_B_A<9>

MEM_B_A<12>

=MEM_B_DQ<2>

=MEM_B_DQ<11>

=MEM_B_DQ<8>

=MEM_B_DQ<3>

=MEM_B_DM<7>

=MEM_B_DQ<58>

MEM_B_SA<0>

PP3V3_S0

31 OF 132 30 OF 103

7

28 31 68 73

32

7

28 31 68

32

6 7 8

25 26 27 28

34 37 40 42 47 48 49 52 53

55 59 63 64 69 70

71 72 73 74 81 84 85 86 88

99

101

IN IN

IN

OUT

D

SG

D

S G

D

SG

D

S G

D

SG

D

S G

D

S G

D

SG

OUT

IN

D

SG

D

SG

IN

G

D

S

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

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PAGE TITLE

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D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Ensures CKE signals are held low in S3

60mW max power

S0 to S3 to S0

P1V5CPU_EN = (ISOLATE_CPU_MEM_L + PM_SLP_S3_L) * PM_SLP_S4_L

must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.

transition. Rails will power-up as if from S3, but MEM_RESET_L will not properly assert. Software

NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0

(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO.

1 0 1 1 1 1 1 1 1

Step ISOLATE_CPU_MEM_L PLT_RESET_L PM_SLP_S3_L PM_SLP_S4_L CPU_MEM_RESET_L MEM_RESET_L MEMVTT_EN P1V5CPU_EN 0 1 1 1 1 1 CPU_MEM_RESET_L 1 1

2 0 0 1 1 1 1 0 1 3 0 0 0 1 X 1 0 0

4 0 0 1 1 X 1 0 1 5 0 1 1 1 0 (*) 1 1 1 6 0 1 1 1 1 1 1 1 7 1 1 1 1 1 CPU_MEM_RESET_L 1 1

MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L

WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.

75mA max load @ 0.75V

MEMVTT_EN = (ISOLATE_CPU_MEM_L + PLT_RST_L) * PM_SLP_S3_L

PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page

ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.

as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.

MEMVTT Clamp

1V5 S0 "PGOOD" for CPU

WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated.

The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well

20 25

6

18 46 74 86

19 27 40

2

1

R3202

1/16W

5%

MF-LF

CPUMEM_S0

100K

402

8

31 68

2

1

R3210

10K

1/16W

5%

402

MF-LF

CPUMEM_S0

2

1

R3215

CPUMEM_S0

100K

MF-LF

402

5%

1/16W

28 30

2

1

R3216

CPUMEM_S0

20K

MF-LF 402

5% 1/16W

4

5

3

Q3200

SOT563

SSM6N15FEAPE

CPUMEM_S0

4

5

3

Q3205

SOT563

CPUMEM_S0

SSM6N15FEAPE

1

2

6

Q3210

SOT563

CPUMEM_S0

SSM6N15FEAPE

4

5

3

Q3210

SSM6N15FEAPE

CPUMEM_S0

SOT563

1

2

6

Q3200

SOT563

SSM6N15FEAPE

CPUMEM_S0

1

2

6

Q3215

SOT563

SSM6N15FEAPE

CPUMEM_S0

4

5

3

Q3215

CPUMEM_S0

SSM6N15FEAPE

SOT563

1

2

6

Q3205

SOT563

SSM6N15FEAPE

CPUMEM_S0

73

2

1

R3205

10K

1/16W

5%

402

MF-LF

CPUMEM_S0

18 43 46 47 73 74

2

1

R3201

100K

5%

402

MF-LF

CPUMEM_S0

1/16W

8

31 68

4

5

3

Q3250

SSM6N15FEAPE

SOT563

CPUMEM_S0

2

1

R3251

1/16W MF-LF

5%

100K

402

CPUMEM_S0

2

1

C3251

402

NO STUFF

50V

0.001UF

20%

CERM

1

2

6

Q3250

SSM6N15FEAPE

SOT563

CPUMEM_S0

2

1

R3250

MF-LF

10

5%

603

1/10W

CPUMEM_S0

21

R3217

MF-LF

1/16W

5%

402

0

CPUMEM_S3

10 31

2

1

R3221

MF-LF

1%

33.2K

402

1/16W

2

1

R3220

402

27.4K

1% 1/16W MF-LF

4

3

5

Q3220

SOT-563

DMB53D0UV

CRITICAL

2

1

R3222

MF-LF

1/16W

5%

10K

402

1

2

6

Q3220

SOT-563

CRITICAL

DMB53D0UV

10 18 91

2

1

C3220

CERM

NO STUFF

402

50V

20%

0.001UF

SYNC_MASTER=K18_MLB

SYNC_DATE=10/14/2009

CPU Memory S3 Support

P1V5_S0_DIV

PM_MEM_PWRGD

PM_MEM_PWRGD_L

PP3V3_S5

PPCPUDDR_ISNS

PP3V3_S3

PM_SLP_S4_L

PP5V_S3

ISOLATE_CPU_MEM_L

MEMRESET_ISOL_LS5V_L

MEMVTT_EN_L

MEMVTT_EN

PP5V_S3

VTTCLAMP_EN

VTTCLAMP_L

PP0V75_S0_DDRVTT

P1V5CPU_EN_L

P1V5CPU_EN

PM_SLP_S3_L

MEMVTT_EN

PLT_RESET_L

PP1V5_S3

MEM_RESET_L

CPU_MEM_RESET_L

MAKE_BASE=TRUE

CPU_MEM_RESET_L

32 OF 132 31 OF 103

6 7

35 49 50 51 58 72 73 74 84 86 99

101

7

13 16 57

6 7

17 20 32 33 34 35 36 49 50 51 54 55

56 72 74 88

102 103

6 7

31 33 43 44 45 47 51 55 68 73 83

103

6 7

31 33 43 44 45 47 51 55 68 73 83

103

7

28 30 68

7

28 30 68 73

OUT

V-

V+

V-

V+

V-

V+

V-

V+

V-

V+

V-

V+

IN

RESET*

A0 A1 A2

SCL SDA

P0 P1 P2

P5 P6 P7

P3 P4

THRM

VCC

GND

PAD

NC

IN BI

VDD

VOUTD

VOUTC

VOUTB

VOUTA

SCL

SDA

A0

A1

GND

IN

BI

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

DRAWING NUMBER

SIZE

D

R

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PAGE TITLE

C

A

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

1.056V - 1.442V (+/- 180mV)

1.51mV / step @ output

+33uA - -33uA (- = sourced) +6.0mA - -5.0mA (- = sourced)

0.000V - 3.300V (0x00 - 0xFF)

1.267V (DAC: 0x8B)

6

D

GPU Frame Buffer (1.8V, 70% VRef)

0.75V (DAC: 0x3A) 1.5V (DAC: 0x3A)

MEM B VREF CA

NOTE: Must not enable more than two SO-DIMM margining buffers at once or VRef source may be overloaded.

0.000V - 1.501V (0x00 - 0x74)

1.998V - 1.002V (+/- 498mV)

8.59mV / step @ output

MEM VREG

5

D

DAC Channel: PCA9557D Pin:

DAC range:

Nominal value

DAC step size:

VRef current:

Margined target:

MEM A VREF DQ

B 21

A

MEM B VREF DQ

0.300V - 1.200V (+/- 450mV)

+3.4mA - -3.4mA (- = sourced)

0.000V - 1.501V (0x00 - 0x74)

7.69mV / step @ output

C 3

MEM A VREF CA

4

C

- =PP3V3_S3_VREFMRGN

- =I2C_VREFDACS_SCL

- =I2C_VREFDACS_SDA

- =I2C_PCA9557D_SCL

- =I2C_PCA9557D_SDA

Circuitry.

- =PPVTT_S3_DDR_BUF

Page Notes

Power aliases required by this page:

BOM options provided by this page: VREFMRGN - Stuffs VREF Margining

VREFMRGN_NOT - Bypasses VREF Margining

Signal aliases required by this page:

10mA max load

RST* on ’platform reset’ so that system watchdog will disable margining.

NOTE: Margining will be disabled across all soft-resets and sleep/wake cycles.

Addr=0x30(WR)/0x31(RD)

both at the same time!

NOTE: MEMVREG and FRAMEBUF share a DAC output, cannot enable

(OD)

Addr=0x98(WR)/0x99(RD)

Required zero ohm resistors when no VREF margining circuit stuffed

8

78

21

R3316

VREFMRGN

1/16W

1%

402

MF-LF

49.9

PLACE_NEAR=R0900.2:1mm

68

2

1

C3302

VREFMRGN

0.1UF

CERM

402

20% 10V

21

R3314

22.6K

VREFMRGN

1/16W

1%

402

MF-LF

PLACE_NEAR=R7320.2:1mm

2

1

R3313

402

MF-LF

1/16W

5%

100K

VREFMRGN

2

1

R3315

VREFMRGN

5% 1/16W MF-LF 402

100K

8

79

21

R3317

VREFMRGN

1/16W

1%

402

MF-LF

49.9

PLACE_NEAR=R0901.2:1mm

B4

B1

C4

C1

C2

C3

U3302

VREFMRGN MAX4253

UCSP

B4

B1

A4

A1

A2

A3

U3303

VREFMRGN

UCSP

MAX4253

B4

B1

A4

A1

A2

A3

U3302

MAX4253

UCSP

VREFMRGN

B4

B1

C4

C1

C2

C3

U3303

UCSP

MAX4253

VREFMRGN

B4

B1

A4

A1

A2

A3

U3304

VREFMRGN

UCSP

MAX4253

B4

B1

C4

C1

C2

C3

U3304

VREFMRGN

UCSP

MAX4253

21

R3309

PLACE_NEAR=J2900.126:2.54mm

1/16W

1%

402

MF-LF

200

VREFMRGN

21

R3311

PLACE_NEAR=J3100.126:2.54mm

200

MF-LF

402

1%

1/16W

VREFMRGN

21

R3318

SHORT

NONE

402

NONE NONE

OMIT

21

R3319

NONE

402

NONE

SHORT

NONE

OMIT

27

21

R3303

200

MF-LF

402

1%

1/16W

VREFMRGN

PLACE_NEAR=J2900.1:2.54mm

21

R3304

133

PLACE_NEAR=R3303.2:1mm

1/16W

1%

402

MF-LF

VREFMRGN

21

R3305

VREFMRGN

200

MF-LF

402

1%

1/16W

PLACE_NEAR=J3100.1:2.54mm

21

R3306

133

PLACE_NEAR=R3305.2:1mm

VREFMRGN

1/16W

1%

MF-LF

402

2

1

R3302

5% 1/16W MF-LF 402

VREFMRGN

100K

2

1

R3301

MF-LF

1/16W

5%

100K

402

VREFMRGN

21

R3310

133

PLACE_NEAR=R3309.2:1mm

VREFMRGN

MF-LF

402

1%

1/16W

2

1

R3307

402

MF-LF

1/16W

5%

100K

VREFMRGN

16

17

2

1

15

14

13

12

11

10

9

7

6

8

5

4

3

U3301

PCA9557

QFN

VREFMRGN

CRITICAL

2

1

C3304

VREFMRGN

0.1UF

CERM

402

20% 10V

21

R3312

133

MF-LF

402

1%

VREFMRGN

1/16W

PLACE_NEAR=R3311.2:1mm

2

1

R3308

MF-LF 402

1/16W

100K

5%

VREFMRGN

6

17 25 26 28 30 32 34 42 48 49 64 94

6

17 25 26 28 30 32 34 42 48 49 64 94

5

4

2

1

8

7

6

3

10

9

U3300

CRITICAL

MSOP

DAC5574

VREFMRGN

6

17 25 26 28 30 32 34 42 48 49 64 94

6

17 25 26 28 30 32 34 42 48 49 64 94

2

1

C3301

10V

20% 402

CERM

0.1UF

VREFMRGN

2

1

C3300

6.3V

20%

402-LF

CERM

2.2UF

VREFMRGN

2

1

C3305

VREFMRGN

0.1UF

CERM

402

10V

20%

2

1

C3303

VREFMRGN

402

CERM

20% 10V

0.1UF

116S0004

RES,MTL FILM,0,5%,0402,SM,LF

R3303,R3305

2

VREFMRGN_NOT

SYNC_DATE=06/09/2009

SYNC_MASTER=K17_WFERRY

FSB/DDR3/FRAMEBUF Vref Margining

116S0004

RES,MTL FILM,0,5%,0402,SM,LF

R3309,R3311

2

VREFMRGN_NOT

VREFMRGN_MEMVREG_EN

VREFMRGN_DQ_SODIMMA_EN

VREFMRGN_CA_SODIMMA_EN

PCA9557D_RESET_L

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP3V3_S3_VREFMRGN_DAC

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP3V3_S3_VREFMRGN_CTRL

SMBUS_PCH_CLK SMBUS_PCH_DATA

VREFMRGN_SODIMMB_DQ

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm VOLTAGE=0.75V

PP0V75_S3_MEM_VREFDQ_A

MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V

MIN_LINE_WIDTH=0.3 mm

PP0V75_S3_MEM_VREFDQ_B

PP0V75_S3_MEM_VREFCA_A

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V

PPVTTDDR_S3

PP0V75_S3_MEM_VREFCA_B

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V

DDRREG_FB

GPU_FB_A_VREF_DIV

GPU_FB_B_VREF_DIV

VREFMRGN_FRAMEBUF_BUF

VREFMRGN_DQ_SODIMMA_BUF

VREFMRGN_DQ_SODIMMB_BUF

VREFMRGN_CA_SODIMMA_BUF

VREFMRGN_CA_SODIMMB_BUF

VREFMRGN_FRAMEBUF_EN

VREFMRGN_SODIMMA_DQ

VREFMRGN_MEMVREG_FBVREF

VREFMRGN_DQ_SODIMMB_EN

VREFMRGN_SODIMMS_CA

PP3V3_S3

VREFMRGN_MEMVREG_BUF

VREFMRGN_CA_SODIMMB_EN

33 OF 132 32 OF 103

28

30

28

6 7

68

30

6 7

17 20 31 33 34 35 36 49 50

51 54 55 56 72 74 88

102 103

BI

IN

BI

SYM_VER-1

IN

S

G

D

OUT

IN IN

IN

BI

SYM_VER-1

NC

IN

Y

B

A

D

S G

OUT

OUT OUT

OUT

NC NC

D

S G

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

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PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

606 MA NOMINAL MAX

RC (R3453 AND C3453)VALUE IS CHOSEN TO MEET THE 100 MS DELAY REQUIREMENT BETWEEN

3.3 WLAN POWER GETTING STABLE AND AIRPORT CARD COMING OUT OF RESET

AIRPORT

CHANNEL

516S0582

0.727 A (EDP)

MOSFET

LOADING

RDS(ON)

155S0367

206 mA nominal max

275 mA peak

ALS

727 MA PEAK

CAMERA

20-30 MOHM @2.5V

P-TYPE

TPCP8102

3V S3 WLAN FET

BLUETOOTH

518S0767

PLACEMENT_NOTE=Place close to J3402

L3408

FERR-120-OHM-1.5A

0402-LF

12

C3452

0.1uF

10V

20% CERM

402

2

1

35 93

6

46 49 55 97

6

46 49 55 97

PLACE_NEAR=J3402.6:2.54MM

CRITICAL

L3407

90-OHM DLP0NS

4

1

3

2

PLACEMENT_NOTE=Place close to J3402

74

R3451

1/16W

10K

402

5% MF-LF

2

1

1 2

402

33K

5%

MF-LF

1/16W

R3450

20 74

C3451

0.033UF

402

16V X5R

10%

2

1

CRITICAL

Q3450

23V1K-SM

TPCP8102

5 6 87

4

1 32

C3450

0.1UF

X5R

16V

10%

402

1 2

57 99

1/4W

R3452

CRITICAL

4

1%

0.002

1206

MF

3

1 2

C3420

X5R

10UF

805

20% 10V

2

1

PLACEMENT_NOTE=Place close to Q3450.

L3404

21

FERR-120-OHM-3A

0603

C3421

20% 10V

0.1uF

CERM

1

PLACEMENT_NOTE=Place close to Q3450.

402

2

5%

1/16W

402

MF-LF

112

R3455

CERM

402

20% 10V

2

PLACEMENT_NOTE=Place close to J3401.

1

C3422

0.1uF

17 94

36 93

PLACEMENT_NOTE=Place close to J3401.

402

0.1uF

10%

C3431

16V

1 2

X5R

402

C3430

16V X5R10%

1 2

0.1uF

PLACEMENT_NOTE=Place close to J3401.

90-OHM-100MA

CRITICAL

4

1

DLP11S

2

3

PLACEMENT_NOTE=Place close to J3401.

L3401

PLACEMENT_NOTE=Place close to J3401.

PLACE_NEAR=J3401.21:2.54MM

CRITICAL

90-OHM DLP0NS

4

L3403

1

3

2

MF-LF

1/16W

110K

R3453

402

5%

2

1

SOT353-1

3 1

5

4 2

U3402

74LVC1G17

NOSTUFF

402

MF-LF

1/16W

62K

R3454

5%

2

1

402

1UF

CERM

6.3V

10%

C3453

2

1

27

TC7SZ08AFEAPE

U3401

SOT665

4

3

5

2

1

SOT563

SSM6N15FEAPE

6

2

1

Q3401

17 25

6

17 94

6

17 94

12

0402-LF

FERR-120-OHM-1.5A

PLACEMENT_NOTE=PLACE L3406 NEAR J3401.

L3406

6

18 27 34

33

34

21

19

11

32

31

6

13 15

29

30

28

24 26

22

20

18

14 16

27

23 25

17

12

10

8

4

2

7 9

3 5

1

J3401

500913-0302

F-ST-SM

CRITICAL

SSM6N15FEAPE

Q3401

SOT563

3

4

5

PLACEMENT_NOTE=PLACE C3432 NEAR J3401

C3432

0.01UF

CERM

10%

402

1

16V

2

J3402

F-RT-SM

6 5 4

1

2

3

8

7

819Q-3506-K281

CRITICAL

X16/ALS/CAMERA CONNECTOR

SYNC_MASTER=K18_MLB

SYNC_DATE=06/19/2009

PP5V_S3_ALSCAMERA_F

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA

USB_CAMERA_CONN_P

PCIE_AP_D2R_N

PCIE_AP_D2R_P

PCIE_AP_R2D_P PCIE_AP_R2D_N

PCIE_CLK100M_AP_CONN_N

PCIE_CLK100M_AP_CONN_P

AP_CLKREQ_L

PCIE_WAKE_L

MIN_NECK_WIDTH=0.5 mm

PP3V3_WLAN

MIN_LINE_WIDTH=1 mm

PP3V3_S3

PCIE_AP_R2D_C_P PCIE_AP_R2D_C_N

USB_CAMERA_N

USB_CAMERA_P

AP_RESET_L

WLAN_SMIT_BUF

PP3V3_WLAN_F

WLAN_SMIT_RC

PP5V_S3

WLAN_SMIT_DISCHRG

AP_PWR_EN

PP3V3_S3

PCIE_CLK100M_AP_P

MIN_LINE_WIDTH=1 mm

MIN_NECK_WIDTH=0.5 mm

PP3V3_WLAN_R

USB_BT_P

USB_CAMERA_CONN_N

PCIE_CLK100M_AP_N

P3V3WLAN_SS

ISNS_AIRPORT_P

ISNS_AIRPORT_N

USB_BT_N

PP3V3_S3

PP3V3_S3_BT_F

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

CONN_USB2_BT_P CONN_USB2_BT_N

PP3V3_WLAN_F

MIN_NECK_WIDTH=0.5 mm

MIN_LINE_WIDTH=1 mm

AP_CLKREQ_Q_L

AP_RESET_CONN_L

PM_WLAN_EN_L

34 OF 132 33 OF 103

6

99

6

94

6

94

6

99

6

99

6

6 7

17 20

31 32 33 34 35 36

49 50 51 54 55 56

72 74 88

102 103

33 57

6 7

31 43 44 45 47 51 55 68 73 83

103

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

6

99

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

6

99

6

99

33 57

6

NC NC

NC

NC NC

OUT

IN

IN IN

SYM_VER-1

BI

IN

IN IN

OUT

NC

BI

OUT

THRML_PAD

RCLKEN

GND

NC4

NC3

NC2

NC1

VOUT1P5

CPPE*

PERST*

NC0

OC*

SYSRST*

STBY*

AUXOUT

VOUT3P3

VIN1P5

VIN3P3

CPUSB*

SHDN*

AUXIN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

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SIZE

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R

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PAGE TITLE

C

A

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

518S0647

INPUT DECOUPLING

EXPRESSCARD/34 FLEX CONNECTOR

All pull-ups to AUXIN rail

(IPU)

OUTPUT DECOUPLING

6.3V

2

1

C3505

X5R 603

20%

10uF

17

46

27

8

36 47

2

16V

1

C3502

0.1uF

X5R 402

10%

4 3

21

L3502

90-OHM DLP0NS

PLACE_NEAR=J3500.3:4mm

2

1

C3503

10uF

6.3V X5R 603

20%

21

C3571

402X5R16V10%

0.1uF

PLACE_NEAR=J3500.24:4mm

4 3

21

L3503

90-OHM-100MA

DLP11S

PLACE_NEAR=J3500.19:4mm

21

C3570

10% X5R 402

0.1uF

16V

PLACE_NEAR=J3500.25:4mm

8

34 36 93

8

34 36 93

17 94

6

17 94

2

1

C3500

402

20% 10V

0.1uF

CERM

6

17 94

6

18 27 33

6

17 25 26 28 30 32 42 48 49 64

94

6

17 25 26 28 30 32 42 48 49 64 94

5

4

1

2

3

U3551

74HC1G00GWDG

SC70-5

9

8

7

6

5

4

3

29

28

27

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

J3500

F-RT-SM

502250-8627

CRITICAL

21

R3504

SHORT

NONE NONE

NONE

402

OMIT

21

R3503

SHORT

NONE NONE

NONE

402

OMIT

21

R3502

OMIT

402

NONE NONE

NONE

SHORT

21

R3551

SMC_EXCARD

MF-LF

1/16W

402

0

5%

2

1

R3550

SMC_EXCARD_NOT

MF-LF

1/16W

402

0

5%

46 47

3 11

2

12

21

6

1

20

18

8

19

16

14

13

5

4

7

9

10

15

17

U3500

TPS2231

CRITICAL

QFN

2

1

C3535

6.3V

20% 603

X5R

10uF

2

1

C3534

10V

20% 402

CERM

0.1uF

2

1

C3531

6.3V

20% 603

10uF

X5R

2

1

C3530

10V

20% 402

CERM

0.1uF

2

1

C3550

CERM

0.1uF

402

20% 10V

2

1

R3561

1/16W

1%

MF-LF

100K

402

2

1

C3560

10V

20% 402

CERM

0.1uF

R3500

21

SMC_EXCARD

402

MF-LF

0

5%

1/16W

2

1

C3501

0.1uF

16V X5R

10% 402

C2

A2

C1

B1

U3561

BGA

SN74LVC1G04YZPR

2

1

C3504

20% 603

X5R

6.3V

10uF

5

4

1

2

3

U3560

SC70-5

74HC1G00GWDG

SYNC_MASTER=K17_WFERRY

SYNC_DATE=06/09/2009

ExpressCard Connector

EXCARD_CLKREQ_L

EXCARD_RCLKEN

SMC_EXCARD_CP

EXCARD_RCLKEN

EXCARD_CP

EXCARD_CPPE_L

EXCARD_CPUSB_L

PP3V3_S3_EXCARD_SWITCH

MIN_LINE_WIDTH=.3mm MIN_NECK_WIDTH=0.2mm

VOLTAGE=3.3V

PP3V3_S0_EXCARD_SWITCH

MIN_LINE_WIDTH=.6mm MIN_NECK_WIDTH=0.2mm

VOLTAGE=3.3V

PP3V3_S0

MIN_NECK_WIDTH=0.11mm

PP1V5_S0_EXCARD_SWITCH

MIN_LINE_WIDTH=.6mm

VOLTAGE=1.5V

EXCARD_CLKREQ_CONN_L

PP3V3_S3

EXCARD_CLKREQ_CONN

MIN_LINE_WIDTH=0.5mm MIN_NECK_WIDTH=0.25mm VOLTAGE=3.3V

PP3V3_S3_EXCARD_R

PP3V3_S0_EXCARD_R

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.3mm MIN_NECK_WIDTH=0.2mm

PP1V5_S0_EXCARD_R

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.2mm VOLTAGE=1.5V

PLT_RESET_SWITCH_L

PP3V3_S0

PP1V5_S0

PCIE_CLK100M_EXCARD_P

PP1V5_S0

PP3V3_S3

PCIE_CLK100M_EXCARD_N

USB_EXCARD_N

USB_EXCARD_P

MAKE_BASE=TRUE

USB_EXCARD_N

USB_EXCARD_P

MAKE_BASE=TRUE

PCIE_EXCARD_R2D_C_N

PCIE_CLK100M_EXCARD_CONN_N

PCIE_CLK100M_EXCARD_CONN_P

USB2_EXCARD_CONN_P

USB2_EXCARD_CONN_N

PP3V3_S0_EXCARD_SWITCH

PP1V5_S0_EXCARD_SWITCH

PLT_RESET_SWITCH_L

PCIE_EXCARD_R2D_P

EXCARD_CPPE_L

PCIE_CLK100M_EXCARD_CONN_P

PCIE_EXCARD_D2R_N

PCIE_WAKE_L

PP3V3_S0_EXCARD_SWITCH

PCIE_CLK100M_EXCARD_CONN_N EXCARD_CLKREQ_CONN_L

PP3V3_S3_EXCARD_SWITCH

PCIE_EXCARD_R2D_N

PP1V5_S0_EXCARD_SWITCH

EXCARD_CPUSB_L USB2_EXCARD_CONN_N

PCIE_EXCARD_D2R_P

SMBUS_PCH_DATA

PCIE_EXCARD_R2D_C_P

PCIE_EXCARD_R2D_N PCIE_EXCARD_R2D_P

SMBUS_PCH_CLK

USB2_EXCARD_CONN_P

PP3V3_S3

SMC_EXCARD_PWR_EN TP_EXCARD_STBY_L EXCARD_RESET_L EXCARD_OC_L

EXCARD_SHDN_L_R

EXCARD_CPUSB_L

EXCARD_CPPE_L

35 OF 132 34 OF 103

34

6

34

6

34

6

34

6

34

6 7 8

25 26 27 28 30 34 37 40 42 47 48

49 52 53 55 59 63 64 69 70 71 72 73 74

81 84 85 86 88 99

101

6

34

6

34

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

6

34

6 7 8

25 26 27 28 30 34 37 40 42 47 48

49 52 53 55 59 63 64 69 70 71 72 73 74

81 84 85 86 88 99

101

7

34 42 59 72 74 99

7

34 42 59 72 74 99

6 7

17 20 31 32

33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

6

34 99

6

34 99

6

34 99

6

34 99

6

34

6

34

6

34

6

34 94

6

34

6

34 99

6

34

6

34 99

6

34

6

34

6

34 94

6

34

6

34

6

34 99

6

34 94

6

34 94

6

34 99

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

6

34

6

34

G

D

S

G

D

S

BI

IN

WP

SDA SCL

GND

VCC

IN

THRML_PAD

VDD18PLL

VDD18

VDD33

VDD33CR

VDD33PLL

OCS1*

PRTPWR4

OCS2*

USBUP_DM USBUP_DP

RESET*

XTAL1/CLKIN XTAL2

SUSP_IND/LOCAL_PWR/NON_REM0

USBDN1_DM/PRT_DIS_M1 USBDN1_DP/PRT_DIS_P1

USBDN2_DM/PRT_DIS_M2

PRTPWR2 PRTPWR3

VBUS_DET

RBIAS

OCS3* OCS4*

SDA/SMBDATA/NON_REM1

USBDN4_DM/PRT_DIS_M4 USBDN4_DP/PRT_DIS_P4

TEST

SCL/SMBCLK/CFG_SEL0

HS_IND/CFG_SEL1

PRTPWR1

USBDN3_DP/PRT_DIS_P3

USBDN3_DM/PRT_DOS_M3

USBDN2_DP/PRT_DIS_P2

VDDA33

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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PAGE TITLE

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A

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_5_ITEM

SEL1 SEL0 DESCRIPTION

0 1 SMBUS Slave Config

1 1 EEPROM Supported

NON_REM1 NON_REM0 DESCRIPTION

1 0 Port 1 and 2 are non removable

BOM TABLE

IPU

1 1 Port 1, 2 and 3 are non Removable

0 1 Port 1 is non removable

0 0 Internal Default with Self powered Operation

1 0 Internal Default with Bus powered Operation

IR Receiver

External C

External B

0 0 All ports are Non removable

Camera

USB HUB-1

2

1

R3641

MF-LF

1/16W 402

10K

5%

4

5

3

Q3640

SOT-363

2N7002DW-X-G

R3640

20K

1/16W MF-LF

5%

402

1

2N7002DW-X-G

Q3640

SOT-363

6

2

50V

C3641

NOSTUFF

100PF

402

2

1

5% CERM

10%

2

1

C3640

6.3V 402

0.47UF

CERM-X5R

402

X5R

0.1UF

10% 16V

C3634

1

2

402

MF-LF

1/16W

5%

10K

R3604

1

2

CRITICAL

402

1

CERM

50V

C3619

18PF

5%

2

1

R3665

MF-LF 402

1/16W

5%

10K

HUB1_NONREM1_0

MF-LF

2

1

R3666

402

1/16W

5%

10K

5%

10K

402

MF-LF

1/16W

1

2

HUB1_NONREM1_1

R3692

2

1

10K

5% 1/16W MF-LF 402

NOSTUFF

R3694

1M

402

MF-LF

R3691

1 2

CRITICAL

5%

1/16W

CRITICAL

24.000M-60PPM-16PF

5X3.2X1.4-SM

Y3600

1 2

CERM

50V

5% 402

1

2

18PF

C3620

CRITICAL

6.3V

20%

10UF

X5R 603

C3618

1

2

0.01UF

10% 16V CERM 402

C3642

1

2

100PF

5% 50V

402

CERM

C3643

1

2

CERM

16V

10% 402

1

2

0.01UF

C3636

L3629

FERR-120-OHM-1.5A

1

0402

2

6.3V

20% 603

X5R

C3644

1

2

10UF

C3637

CERM

100PF

5% 50V

402

1

2

L3658

FERR-120-OHM-1.5A

1 2

0402

HUB1_NONREM0_0

1/16W

5%

10K

R3667

402

MF-LF

1

2

R3698

10K

5% 1/16W MF-LF 402

1

2

MF-LF

402

1

2

NOSTUFF

R3697

10K

5%

1/16W

R3699

HUB1_NONREM0_1

5% 1/16W MF-LF

10K

1

2

402

CRITICAL

12K

402

1% MF

1/16W

1

2

R3600

44 93

43 93

19 93

43 93

45 93

33 93

45 93

33 93

2

1

C3624

0.1UF

X7R-CERM

16V

10% 402

2

1

C3627

10% 402

16V X5R

1UF

2

1

R3682

5%

402

MF-LF

10K

1/16W

X7R-CERM

0.1UF

C3628

2

1

10% 402

16V

C3630

402

2

1

10% 16V X5R

1UF

X7R-CERM 402

0.1UF

10%

1

2

16V

C3645

10UF

20% X5R

6.3V 603

1

2

C3638

C3646

402

0.1UF

10% X7R-CERM

1

2

16V

X7R-CERM

0.1UF

10% 16V

402

C3647

1

2

402

10% 16V X7R-CERM

C3639

1

2

0.1UF

C3623

10% 402

16V

1

2

0.1UF

X7R-CERM

0.1UF

10% 402

16V X7R-CERM

1

2

C3625

0.01UF

10% 16V CERM 402

C3626

1

2

0.01UF

C3629

10% 402

CERM

16V

1

2

43

19 25

AT24C02B

NOSTUFF

SOT23-5

U3614

2

1

3

4

5

8

44

100K

R3642

1/16W 402

2

MF-LF

5%

1

2

402

R3668

100

1/16W

5% MF-LF

USX2061

QFN

37

34

14

23

15

362910

5

1

3

2

4

6 7

8

12

9

16 18

13

20

17 19 21

35

27

30 31

11

26

33 32

25

24

22

28

OMIT

U3600

SOD-523

D3645

BAT54XV2T1

2 1

IC,ASSP,USB2.0,HUB CNTROL,4 PRT,36QFN

338S0720

U3600,U3700

CRITICAL

2

USBHUB_2514

CRITICAL

IC,USB2514B,USB 2.0,HUB CNTRL,4 PRT,36QFN

U3600,U3700

338S0824

2

USBHUB_2514B

USBHUB_2061

IC,USX2061,USB 2.0,HUB CNTRL,4 PRT,36QFN

338S0721

U3600,U3700

CRITICAL

2

HUB1_NONREM1_1,HUB1_NONREM0_1

HUB1_3NONREM

HUB1_2NONREM

HUB1_NONREM1_1,HUB1_NONREM0_0

HUB1_1NONREM

HUB1_NONREM1_0,HUB1_NONREM0_1

HUB1_NONREM1_0,HUB1_NONREM0_0

HUB1_ALLREM

USB HUB 1

SYNC_MASTER=K18_MLB

SYNC_DATE=10/07/2009

VOLTAGE=1.8V

MIN_LINE_WIDTH=0.4MM

PPUSB_HUB1_VDD1V8PLL

MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.8V

PPUSB_HUB1_VDD1V8

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.4MM

NC_USB_HUB1_OCS2

NC_USB_HUB1_PRTPWR4

NC_USB_HUB1_PRTPWR2

PP3V3_S3

WP_HUB1

PP3V3_S3

PPUSB_HUB1_VDDPLL3V3

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

PPUSB_HUB1_VDDA3V3

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

USB_CAMERA_N

USB_IR_N

USB_CAMERA_P

USB_IR_P USB_EXTB_N

USB_EXTB_P USB_EXTC_N

USB_EXTC_P

USB_EXTB_OC_L USB_EXTC_OC_L

USB_HUB1_RBIAS USB_HUB1_VBUS_DET USB_HUB1_UP_N

USB_HUB1_UP_P

USB_HUB1_TEST

USB_HUB_RESET_L

USB_HUB1_XTAL1 USB_HUB1_XTAL2

USB_HUB1_SMBCLK

USB_HUB1_SMBDATA

USB_HUB1_LOCAL_PWR

NC_USB_HUB1_PRTPWR3

TP_USB_HUB1_PRTPWR1

TP_USB_HUB1_OCS1

PP3V3_S3

USB_HUB_RESET_L

USB_HUB_SOFT_RESET_L

USB_HUB1_CFG_SEL1

PP3V3_S3

PP3V3_S5

USB_HUB_RESET

PP3V3_S3

P3V3S3_EN_RC

36 OF 132 35 OF 103

6 7

17 20

31 32 33 34

35 36 49 50

51 54 55 56

72 74 88

102 103

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

6 7

17 20 31 32 33 34

35 36 49 50 51 54 55 56

72 74 88

102 103

35 36

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

6 7

31 49 50 51 58 72 73 74 84 86 99

101

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

BI

IN

BI

IN

WP

SDA SCL

GND

VCC

IN

THRML_PAD

VDD18PLL

VDD18

VDD33

VDD33CR

VDD33PLL

OCS1*

PRTPWR4

OCS2*

USBUP_DM USBUP_DP

RESET*

XTAL1/CLKIN XTAL2

SUSP_IND/LOCAL_PWR/NON_REM0

USBDN1_DM/PRT_DIS_M1 USBDN1_DP/PRT_DIS_P1

USBDN2_DM/PRT_DIS_M2

PRTPWR2 PRTPWR3

VBUS_DET

RBIAS

OCS3* OCS4*

SDA/SMBDATA/NON_REM1

USBDN4_DM/PRT_DIS_M4 USBDN4_DP/PRT_DIS_P4

TEST

SCL/SMBCLK/CFG_SEL0

HS_IND/CFG_SEL1

PRTPWR1

USBDN3_DP/PRT_DIS_P3

USBDN3_DM/PRT_DOS_M3

USBDN2_DP/PRT_DIS_P2

VDDA33

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

External A

0 0 All ports are removable

1 1 Port 1, 2, and 3 are non removable

1 0 Port 1 and 2 are non removable

0 1 Port 1 is non removable

NON_REM1 NON_REM0 DESCRIPTION

IPU

IPU IPU

USB HUB-2

Bluetooth

1 0 Internal Default with Bus powered Operation

K17/K18 configuration: 0 0 Internal Default with Self powered Operation

0 1 SMBUS Slave Config

1 1 EEPROM Supported

SEL1 SEL0 DESCRIPTION

SD Card/Express Card

Trackpad/Keyboard

2

1

C3720

CERM

50V

5% 402

18PF

CRITICAL

21

R3791

402

1/16W MF-LF

CRITICAL

5%

1M

2

1

C3719

18PF

50V

5%

CERM

CRITICAL

402

2

1

C3734

16V 402

X5R

10%

0.1UF

CERM

100PF

2

1

C3737

402

50V

5%

2

1

C3743

100PF

50V

5% 402

CERM

2

1

10% 402

16V X7R-CERM

0.1UF

C3739

0.1UF

2

1

C3745

402

X7R-CERM

16V

10%

2

1

C3746

0.1UF

16V 402

10% X7R-CERM

0.1UF

2

1

C3747

402

10% 16V X7R-CERM

2

1

C3725

0.1UF

10% 402

16V X7R-CERM

2

1

C3723

X7R-CERM

0.1UF

402

10% 16V

2

1

C3724

0.1UF

X7R-CERM

16V

10% 402

2

1

C3728

0.1UF

10% 402

16V X7R-CERM

2

1

C3736

CERM

10% 16V

402

0.01UF

2

1

C3742

0.01UF

CERM

16V

10% 402

2

1

C3729

10%

0.01UF

402

CERM

16V

2

1

C3726

0.01UF

402

CERM

16V

10%

19 93

35

2

1

C3718

10UF

6.3V X5R 603

20%

2

1

R3797

NOSTUFF

1/16W MF-LF

10K

5%

402

1

2

1/16W

10K

5% MF-LF

402

R3798

FERR-120-OHM-1.5A

21

L3729

0402

2

1

R3792

HUB2_NONREM1_1

10K

5%

MF-LF

402

1/16W

2

1

R3794

5%

10K

402

MF-LF

1/16W

NOSTUFF

2

1

R3704

10K

402

MF-LF

1/16W

5%

1

R3782

5%

1/16W

10K

2

402

MF-LF

2

1

402

MF-LF

1/16W

5%

10K

R3766

2

1

1/16W

5% 402

10K

MF-LF

HUB2_NONREM1_0

R3765

2

1

10K

5% 1/16W MF-LF 402

R3767

HUB2_NONREM0_0

19 93

43 93

8

34 93

8

34 93

54 93

33 93

8

34 47

5

4

3 1

2

U3714

NOSTUFF

SOT23-5

AT24C02B

43

21

Y3700

CRITICAL

5X3.2X1.4-SM

24.000M-60PPM-16PF

2

1

R3799

5%

10K

402

1/16W MF-LF

HUB2_NONREM0_1

1/16W

5% MF-LF

R3768

100

402

2

1

37

34

14

23

15

362910

5

13

20

17

30 31

26

33 32

28

1 2

3

16 18

27

35

19 21

22

8 9

11

24

25 12

7

6

4

QFN

OMIT

U3700

USX2061

2

1

C3730

1UF

402

X5R

16V

10%

2

1

C3727

X5R

1UF

16V 402

10%

2

1

C3738

10UF

603

X5R

20%

6.3V

2

1

C3744

10UF

6.3V X5R 603

20%

21

L3758

FERR-120-OHM-1.5A

0402

402

2

1

R3700

CRITICAL

MF

12K

1/16W

1%

SYNC_DATE=10/09/2009

SYNC_MASTER=K18_MLB

USB HUB 2

HUB2_2NONREM

HUB2_NONREM1_1,HUB2_NONREM0_0

HUB2_ALLREM

HUB2_NONREM1_0,HUB2_NONREM0_0

HUB2_3NONREM

HUB2_NONREM1_1,HUB2_NONREM0_1

HUB2_1NONREM

HUB2_NONREM1_0,HUB2_NONREM0_1

TP_USB_HUB2_OCS1

TP_USB_HUB2_PRTPWR1

USB_BT_P

USB_BT_N

PPUSB_HUB2_VDD1V8PLL

VOLTAGE=1.8V

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

PPUSB_HUB2_VDDPLL3V3

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

PP3V3_S3

NC_USB_HUB2_OCS2

NC_USB_HUB2_PRTPWR4

NC_USB_HUB2_PRTPWR3

NC_USB_HUB2_PRTPWR2

USB_HUB_RESET_L

USB_HUB2_LOCAL_PWR

USB_HUB2_SMBDATA USB_HUB2_SMBCLK

USB_HUB2_CFG_SEL1

USB_HUB2_XTAL2

USB_HUB2_XTAL1

USB_HUB2_TEST

USB_HUB2_UP_P

USB_HUB2_UP_N

USB_HUB2_VBUS_DET

USB_HUB2_RBIAS

USB_EXTA_OC_L

EXCARD_OC_L

USB_EXTA_P

USB_EXTA_N

USB_EXCARD_P

USB_EXCARD_N

USB_TPAD_P

USB_TPAD_N

MIN_NECK_WIDTH=0.2MM

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4MM

PPUSB_HUB2_VDDA3V3

PP3V3_S3

VOLTAGE=1.8V

PPUSB_HUB2_VDD1V8

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.4MM

PP3V3_S3

WP_HUB2

37 OF 132 36 OF 103

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

IN

OUT

IN

IN OUT

OUT

IN

BI

BI BI

BI BI BI BI BI

NC

AVDDH

BIASVDDH

VDDC

VDDIO

XTALVDDH

VDDIO

VDDC

AVDDL

SI SO CS*

RDAC

VDDC UART_MODE

SCLK

LOW_PWR

LINKLED*

CLKREQ*

PERST*

PCIE_REFCLK_N

PCIE_REFCLK_P

PCIE_TXD_P

PCIE_RXD_P

VDDC

VDDIO

PCIE_PLLVDDL

GPHY_PLLVDDL

DC2 DC1

NC

VMAIN_PRSNT

VAUX_PRSNT

ENERGY_DET

DC3

DC4

NC

GPIO_2

TRD1_N

TRD1_P

TRD0_N

SMB_DATA

TRD0_P

TRD2_N

TRD2_P

TRD3_P

THRM_PAD

XTALI XTALO

SPD100LED* TRAFFICLED*

TRD3_N

DC5

PCIE_TXD_N

SPD1000LED*

DC0

WAKE*

PCIE_VDDL

REGCTL12

VDDIO

PCIE_RXD_N

GPIO_0/SERIAL_DO GPIO_1/SERIAL_DI

SMB_CLK

VDDC

VERSION 2

OUT

NC NC

NC NC NC NC

NC

RESET*

CS*

SCK

SO

WP*

SI

GND

VCC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

BCM5764M Support

All parts below BOMOPTIONed BCM5764M

86mA (1000base-T, Caesar II)

If unused: Okay to float all 4 pins. (Broadcom not so sure now) If used: VDD/VDDP connect to =PP3V3_ENET_PHY (add bypassing), LX connects to inductor, VFB to =PP1V2_ENET_PHY

CR_BUS_PWR is not for SD Card power, just decoupling for BCM57765 CR I/Os.

BCM57765 SR pins are internal 1.2V switching regulator.

(IPD-BCM5764M)

(IPD)

(OD)

If PHY is always powered then alias

N-channel FET isolation suggested.

(IPD)

BCM5764M pin-function 60-ENERGY_DET

13-WAKE*

14-VDDC 06-VDDC

17-VDDC

55-VDDC

396mA (1000base-T, Caesar II)

(See note)

with no stubs.

Keep net short,

26-PCIE_VDDL

20-XTALVDDH

59-SMB_CLK

(IPD)

53-VMAIN_PRSNT

16-VDDIO

ROM is used then the straps must change.

NOTE: Pull-down on SO plus internal pull-ups on

ROM contains MAC address, PCIe config

Required for proper PHY operation.

(Required ROM size TBD)

PHY Non-Volatile Memory

info as well as code for Bonjour proxy.

WAKE#

is powered-down in S3/S5. Standard

(IPU)

(IPD)

54-VAUX_PRSNT

58-SMB_DATA

NOTE: BCM5764M requires SI pull-down instead of SO.

Atmel AT45DB011D (1Mbit) ROM. If a different

other 3 SPI pins configures BCM57765 for the

=ENET_WAKE_L to PCIE_WAKE_L.

Must isolate from PCIe WAKE# if PHY

(See note)

2

1

C3921

0.1UF

X7R-CERM

402

16V

10%

2

1

C3935

10UF

805

10%

6.3V X5R

2

1

C3925

4.7UF

X5R-CERM 603

10%

6.3V

21

L3925

FERR-600-OHM-0.5A

SM

CRITICAL

2

1

C3920

603

6.3V

10% X5R-CERM

4.7UF

21

L3920

FERR-600-OHM-0.5A

SM

CRITICAL

21

L3900

CRITICAL

SM

FERR-600-OHM-0.5A

21

L3905

SM

CRITICAL

FERR-600-OHM-0.5A

2

1

R3942

BCM57765

402

MF-LF

5%

1K

1/16W

17 94

27 95

17

27 37

20

27 95

21

C3951

0.1uF

402

X5R

16V

10%

21

C3950

402

0.1uF

X5R

16V

10%

21

C3956

16V

10%

0.1uF

X5R 402

21

C3955

0.1uF

402

X5R

16V

10%

2

1

R3965

1.24K

402

1% 1/16W MF-LF

17 94

38 95

2

1

R3941

MF-LF

1/16W

5%

4.7K

402

BCM57765

2

1

R3940

MF-LF

5%

402

1/16W

4.7K

BCM57765

21

R3980

402

MF-LF

5%01/16W

BCM5764M

21

R3984

402

MF-LF1/16W

5%

4.7K

BCM5764M

21

R3999

0

5%

1/16W MF-LF

402

BCM5764M

21

R3983

402

MF-LF1/16W

5%

4.7K

BCM5764M

21

R3982

1K

5%

1/16W MF-LF

402

BCM5764M

PLACE_NEAR=U3900.26:4 mm

21

L3999

CRITICAL

SM

BCM5764M

FERR-600-OHM-0.5A

PLACE_NEAR=L3999.1:4 mm

2

1

C3998

6.3V

4.7UF

X5R-CERM 603

10%

BCM5764M

PLACE_NEAR=U3900.26:4 mm

2

1

C3999

0.1UF

X7R-CERM

402

10% 16V

BCM5764M

21

R3943

5%

MF-LF

1/16W

402

BCM57765

0

21

R3981

402

1/16W

5%

0

BCM5764M

MF-LF

21

R3986

402

MF-LF1/16W

5%

0

BCM5764M

21

R3985

5%

1/16W MF-LF

402

1K

BCM5764M

21

R3989

402

MF-LF1/16W

5%

0

BCM5764M

21

R3987

402

MF-LF1/16W

5%

0

BCM5764M

21

R3988

402

MF-LF1/16W

5%

0

BCM5764M

21

R3900

BCM57765

0

402

1/16W MF-LF

5%

21

R3915

BCM57765

0

402

1/16W MF-LF

5%

2

1

R3990

BCM57765

1/16W

5%

402

MF-LF

4.7K

21

R3998

402

MF-LF1/16W

5%

0

BCM5764M

20

19

18

13

53

62

56

16

7

615535

17

14

6

54

10

49

46 47

44 43

40 41

67

69

2

68

65

58

59

64

66

15

38

11

26

28

27

33 34

31 30

32

29

52

1

4

3

9

8

5

36

60 57

25 24 23 22

21

63

12

37

514539

48

42

U3900

QFN-8X8

BCM5764M

OMIT

CRITICAL

50

2

1

C3970

4.7UF

603

X5R-CERM

6.3V

10%

BCM57765

2

1

C3971

BCM57765

X7R-CERM 402

10% 16V

0.1UF

2

1

C3972

BCM57765

X7R-CERM 402

10% 16V

0.1UF

21

R3972

402

MF-LF1/16W

5%

0

BCM57765

17 37

2

1

R3910

MF-LF

1/16W

402

4.7K

5%

21

L3910

SM

FERR-600-OHM-0.5A

CRITICAL

2

1

C3910

16V

10%

402

X7R-CERM

0.1UF

2

1

C3911

X7R-CERM

16V

10%

402

0.1UF

2

1

C3990

X7R-CERM

0.1UF

402

10% 16V

2

1

C3900

X7R-CERM

0.1UF

402

10% 16V

2

1

C3905

X7R-CERM

0.1UF

402

10% 16V

2

1

C3930

10%

6.3V X5R-CERM 603

4.7UF

2

1

C3931

0.1UF

16V

10%

402

X7R-CERM

21

L3930

FERR-600-OHM-0.5A

SM

CRITICAL

2

1

C3915

X5R-CERM

603

6.3V

10%

4.7UF

2

1

C3916

402

10% X7R-CERM

0.1UF

16V

5

6

8

12

3

7

4

U3990

OMIT

SOIC-8S1

AT45DB011D

BCM5764M

2

1

R3997

4.7K

MF-LF 402

5% 1/16W

2

1

C3936

10%

402

0.1UF

16V

X7R-CERM

2

1

C3926

16V

10%

X7R-CERM

0.1UF

402

SYNC_DATE=10/28/2009

SYNC_MASTER=K18_MLB

Ethernet PHY (Caesar II/IV)

PCIE_ENET_D2R_N

PCIE_ENET_D2R_P

PCIE_ENET_R2D_C_N

PCIE_ENET_R2D_C_P

ENET_WAKE_L

BCM5764_SCLK

BCM5764_CS_L

PP3V3_ENET

BCM5764_MISO

BCM5764_MOSI

BCM57765_SR_VFB

BCM57765_CR_DATA<6>

PP3V3_ENET_PHY_XTALVDDH

BCM57765_SR_LX

BCM57765_CR_DATA<7> BCM57765_XTALVDDH

BCM57765_VDDO_PIN20

BCM57765_VMAIN_PRSNT

PP3V3_S0

PP3V3_ENET_PHY_XTALVDDH

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm

BCM57765_CR_CMD

BCM57765_SMB_CLK

BCM57765_SR_VDD

BCM57765_CE_L_MS_INS_L

BCM57765_CR_DATA<5>

BCM57765_CR_LED

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

BCM57765_XTALVDDH

BCM57765_VDDO_PIN20

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

BCM57765_SR_VDD

BCM5764_MISO BCM5764_MOSI BCM5764_CS_L

BCM5764_RDAC

BCM57765_SMB_CLK BCM57765_SMB_DATA

BCM5764_SCLK

BCM57765_WAKE_L

PCIE_CLK100M_ENET_N

PCIE_CLK100M_ENET_P

PCIE_ENET_R2D_N

PCIE_ENET_D2R_C_P

PP1V2_ENET

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.2V

PP1V2_ENET_PHY_GPHYPLL

ENET_MDI_N<1>

BCM57765_VMAIN_PRSNT

ENET_MDI_N<2>

ENET_MDI_P<2>

ENET_MDI_P<3>

BCM5764_CLK25M_XTALI BCM5764_CLK25M_XTALO

TP_BCM5764_SPD100LED_L TP_BCM5764_TRAFFICLED_L

PCIE_ENET_D2R_C_N

BCM57765_SR_VFB

ENET_RESET_L ENET_CLKREQ_L

BCM57765_CE_L_MS_INS_L

TP_BCM57765_XD_DET

BCM57765_CR_LED

ENET_LOW_PWR

PCIE_ENET_R2D_P

ENET_MDI_P<1>

ENET_MDI_N<0>

BCM57765_SR_LX

MIN_LINE_WIDTH=0.4 mm

PP1V2_ENET_PHY_PCIEPLL

VOLTAGE=1.2V

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=1.2V

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm

PP1V2_ENET_PHY_AVDDL

TP_BCM57765_SR_VDDP

BCM57765_MEDIA_SENSE

ENET_MDI_P<0>

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.3 mm

PP3V3R1V8_SW_SD_VIO

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

PP3V3_ENET_PHY_BIASVDDH

PP3V3_ENET_PHY_AVDDH

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

PP3V3_ENET

PP1V2_ENET

PP3V3_ENET

PP3V3_S0

ENET_WAKE_L

ENET_ENERGY_DET

ENET_MDI_N<3>

BCM57765_CR_CMD

BCM57765_CR_DATA<5> BCM57765_CR_DATA<6> BCM57765_CR_DATA<7>

39 OF 132 37 OF 103

37

7

27 37 74

37

6 7 8

25 26 27 28 30 34 37 40 42 47 48

49 52 53 55 59 63 64 69 70 71 72 73 74

81 84 85 86 88 99

101

37

94

7

37 72 73

37

94

37

94

37

7

27 37 74

7

37 72 73

7

27 37 74

6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52 53 55 59 63 64 69 70 71 72 73 74 81

84 85 86 88 99

101

27 37

17 37

37

BI

RX

TX

BI

RX

TX

BI

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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REVISION

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A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Power aliases required by this page:

Signal aliases required by this page:

sides of the board

mirrored on opposite

Transformers should be

Place one of 0.1uf cap close to each centertap pin of transformer

Page Notes

(NONE)

BOM options provided by this page:

(NONE)

514-0636

37 95

TLA-6T213HF

SM

CRITICAL

T4000

1

10

11

12

2

3

4

5

6 7

8

9

1/16W

5%

402

MF-LF

75

R4000

1

2

1/16W

5%

402

MF-LF

75

R4001

1

2

1/16W

5% 402

MF-LF

75

R4002

1

2

1/16W

5% 402

MF-LF

75

R4003

1

2

21

C4008

2KV

10%

1206

CERM

CRITICAL

1000PF

37 95

0.1UF

10% 16V

402

X5R

C4006

1

2

16V

10% 402

X5R

0.1UF

C4004

1

2

16V

10% X5R

0.1UF

402

C4002

1

2

TLA-6T213HF

CRITICAL

SM

T4001

1

10

11

12

2

3

4

5

6 7

8

9

0.1UF

16V

10% 402

X5R

C4000

1

2

37 95

HDMIULC64F3

CRITICAL

WLCSP

D4000

C1

A1

F1

D1

C3

A3

F3

D3

B2

E2

PLACE_NEAR=T4001.2:5mm

HDMIULC64F3

WLCSP

CRITICAL

D4001

C1

A1

F1

D1

C3

A3

F3

D3

B2

E2

PLACE_NEAR=T4000.2:5mm

9

8

7

6

5

4

3

2

12

11

10

1

J4000

RJ45-M97-3

CRITICAL

F-RT-TH

37 95

Ethernet Connector

SYNC_MASTER=K17_WFERRY

SYNC_DATE=06/09/2009

ENET_CTAP3

ENETCONN_CTAP

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

ENET_BOB_SMITH_CAP

ENET_CTAP0

ESD_HOT=True

ENETCONN_N<0>

ENET_CTAP1

ESD_HOT=TRUE

ENETCONN_N<1>

ESD_HOT=TRUE

ENETCONN_P<1>

ESD_HOT=TRUE

ENETCONN_N<2>

ESD_HOT=TRUE

ENETCONN_P<2>

ESD_HOT=TRUE

ENETCONN_N<3>

ESD_HOT=TRUE

ENETCONN_P<3>

ENET_CTAP2

ENET_MDI_P<3>

ENET_MDI_P<1>

ENET_MDI_N<1>

ENET_MDI_P<2>

ENET_MDI_P<0>

ENET_MDI_N<3>

ENET_MDI_N<2>

ENET_MDI_N<0>

ESD_HOT=True

ENETCONN_P<0>

40 OF 132 38 OF 103

99

DS2

ATBUSH ATBUSN

VP25

OCR_CTL_V10

VAUX_DETECT

TMS

TCK

REFCLKN

PCIE_TXD0P

TRST*

ATBUSB

TDI

DS1

TPA0N TPA0P

AVREG

CE

CLKREQN

FW_RESET*

FW620* JASI_EN

MODE_A

NAND_TREE

OCR_CTL_V12

PCIE_RXD0N PCIE_RXD0P PCIE_TXD0N

PERST*

R0

REFCLKP

REGCLT

REXT

SCIFCLK SCIFDAIN SCIFDOUT

SCIFMC

SCL SDA

SE SM

TDO

TPA1N

TPA2N TPA2P TPB0N TPB0P TPB1N TPB1P TPB2N TPB2P

TPBIAS0 TPBIAS1 TPBIAS2

TPCPS

VAUX_DISABLE

VBUF

VDDH

VP

VREG_PWR

WAKE*

XI

XO

DS0

TPA1P

VDD33

VDD10

VREG_VSS

VSS

SERIAL EEPROM

MISCELLANEOUS

CONTROLLER

POWER MANAGEMENT

TEST CONTROLLER

PCI EXPRESS PHY

CHIP RESET

SCIF

1394 PHY

NC NC NC

NC

IN IN

IN

OUT

IN IN IN

BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI

IN

NC NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

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SIZE

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PAGE TITLE

C

A

D

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

FIXME!!! - TYPO IN SYMBOL REGCTL

110 mA Digital Core

NT-15 (IPD)

(IPD) NT-11

(IPU) NT-8

(IPD)

138 mA

7 mA I/O

114 mA FireWire PHY

0 mA VReg PWR

17 mA PCIe SerDes25 mA PCIe SerDes

135 mA

NT-1 (IPU)

NT-3 (IPU)

NT-4 (IPU)

(OD)

NT-2 (IPU)

NT-16 (IPD)

NT-7 NT-6

NT-17

NT-5

NT-14 (IPD)

NT-OUT

NT-9 (IPD)

(IPD) NT-19 (IPD) NT-20

(IPU)

(IPD) NT-21

(IPU)

NT-13

NT-12 (IPD)

(IPD) NT-18

NT-10 (IPD)

NOTE: NT-xx notes show NAND tree order.

(Reserved)

2

1

R4170

402

MF-LF

1/16W

1%

191

2

1

C4162

10% 402

6.3V

0.33UF

CERM-X5R

2

1

R4162

402

470K

MF-LF

5%

1/16W

C13

E4

D10

D4

F13 G13

C2

F6F4E9

E5

K10

K6L7K9

K8D9K7K5K4

J10

J9J5J4

H10

H8

H7D7H6

H4

G10

G8G7G6

G4

F10

F8

F7

B2

L12

K12

L9

L6

L10

L5

D8D6D5

A12

M2

L11

L3J1G12

F1

C12

C1

L1K2H12

H2

E10

E2

B12

N11

N3

M12

B1

A1

H13

D2

E1

N1

B10

A2

C3

B7

A4

B4

A6

B6

A9

B9

A3

B3

A5

B5

A8

B8

M3

M1

N2

M4

N13

M13

M11

N12

F2

H1

G1

G2

L8

D13

N10

N9

B11

N4

N6

N5

N7

N8

J13

J12

K1

J2

D1

K13

D12

E13

E12

F12

L2

L13

A10

A11

A13

B13

U4100

CRITICAL

OMIT

FW643

BGA

21

C4151

402

50V

5%

22PF

CERM

21

C4150

402

CERM

22PF

5%

50V

2

1

R4160

402

1/16W MF-LF

1%

200K

21

R4150

402

1/16W

1%

MF-LF

412

2

1

R4163

402

1/16W

5% MF-LF

10K

2

1

R4164

402

1/16W

5% MF-LF

10K

2

1

R4165

402

10K

MF-LF

5%

1/16W

FW643_LDO

PLACE_NEAR=U4100.N6:3mm

21

C4176

10%

402X5R

16V

0.1UF

PLACE_NEAR=U4100.N5:3mm

21

C4175

10%

402X5R

16V

0.1UF

2

1

R4166

402

1/16W

5% MF-LF

10K

PLACE_NEAR=U1800.AV32:3mm

21

C4171

10%

402X5R

16V

0.1UF

PLACE_NEAR=U1800.AU32:3mm

16V21

C4170

10%

402X5R

0.1UF

2

1

C4130

10%

1UF

402

6.3V CERM

2

1

C4131

10%

1UF

402

6.3V CERM

C4100

2

1

10%

1UF

402

6.3V CERM

2

1

C4101

10%

1UF

402

6.3V CERM

2

1

C4132

10%

1UF

402

6.3V CERM

2

1

C4102

10%

1UF

402

6.3V CERM

2

1

C4103

10%

1UF

402

6.3V CERM

2

1

C4135

10%

1UF

402

6.3V CERM

2

1

C4136

10%

1UF

402

6.3V CERM

2

1

C4104

10%

1UF

402

6.3V CERM

2

1

C4110

10%

1UF

402

6.3V CERM

2

1

C4105

10%

1UF

402

6.3V CERM

2

1

C4106

10%

1UF

402

6.3V CERM

2

1

C4120

10%

1UF

402

6.3V CERM

2

1

C4121

10%

1UF

402

6.3V CERM

2

1

C4122

10%

1UF

402

6.3V CERM

2

1

C4123

10%

1UF

402

6.3V CERM

2

1

C4124

10%

1UF

402

6.3V CERM

2

1

C4141

10V 402

0.1UF

CERM

20%

2

1

C4111

10%

1UF

402

6.3V CERM

402

2

1

C4140

10%

1UF

6.3V CERM

17 94

8

40

2

1

R4161

402

1/16W

1%

MF-LF

2.94K

41

41 96

6

41 96

40 41 96

6

41

6

41

6

41 96

6

41 96

40 41 96

6

41

6

41

40 41

6

41

21

L4130

120-OHM-0.3A-EMI

0402-LF

21

L4135

0402-LF

120-OHM-0.3A-EMI

40

21

L4110

120-OHM-0.3A-EMI

0402-LF

Y4150

31

42

CRITICAL

SM-3.2X2.5MM

24.576MHZ

FireWire LLC/PHY (FW643)

SYNC_MASTER=K20A_MLB SYNC_DATE=03/26/2009

FW_P1_TPBIAS NC_FW2_TPBIAS

FW643_SCL

FW_CLKREQ_PHY_L

TP_FW643_VAUX_ENABLE

FW643_VAUX_DETECT

FW643_TRST_L

TP_FW643_TMS

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP3V3_FW_FWPHY_VP25

PPVP_FW_CPS

FW643_TPCPS

FW643_PU_RST_L

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP3V3_FW_FWPHY_VDDA

PCIE_FW_D2R_C_P

PCIE_FW_D2R_P

PCIE_FW_D2R_C_N

PCIE_FW_D2R_N

PCIE_FW_R2D_P

PCIE_FW_R2D_N

NC_FW0_TPAN NC_FW0_TPAP

NC_FW0_TPBP

FWPHY_DS1

PP3V3_FW_FWPHY

FWPHY_DS0

FWPHY_DS2

FW643_REXT

FW643_R0

FW_CLK24P576M_XO_R

NC_FW0_TPBIAS

NC_FW2_TPBP

NC_FW2_TPBN

FW_PORT1_TPB_P

FW_PORT1_TPB_N

NC_FW0_TPBN

NC_FW2_TPAP

NC_FW2_TPAN

FW_PORT1_TPA_N FW_PORT1_TPA_P

FW643_WAKE_L

TP_FW643_VBUF

TP_FW643_TDO

TP_FW643_SM

TP_FW643_SE

TP_FW643_SDA

TP_FW643_SCIFDOUT

TP_FW643_SCIFDAIN

TP_FW643_SCIFCLK

PCIE_CLK100M_FW_P

FW_RESET_L

TP_FW643_NAND_TREE

TP_FW643_MODE_A

TP_FW643_JASI_EN

TP_FW643_FW620_L

TP_FW643_CE

NC_FW643_AVREG

NC_FW643_TDI

PCIE_CLK100M_FW_N

TP_FW643_TCK

TP_FW643_OCR10_CTL

FW643_REGCTL

FW_CLK24P576M_XI

FW_CLK24P576M_XO

PP3V3_FW_FWPHY

TP_FW643_SCIFMC

PPVIN_FW_FWPHY

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.0V

PP1V0_FW_FWPHY_AVDD

PCIE_FW_R2D_C_P

PCIE_FW_R2D_C_N

41 OF 132 39 OF 103

41

94

7

39 40 41

6

7

39 40 41

7

40 72

VCC

VCLMP

D1-

GND

D2-

D2+

D1+

FWPWR_EN

G

S

(SYM-VER1)

D

S

G

D

(SYM-VER2)

D

SG

BI BI

IN

GND

VOUT

ON

VIN

D

SG

OUT

GND

VOUT

ON

VIN

IN

G

D

S

G

D

S

OUT

IN

G

D

S

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

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SIZE

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PAGE TITLE

C

A

D

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Late-VG Protection

- =PP3V3_FW_LATEVG_ACTIVE

Signal aliases required by this page:

BOM options provided by this page:

(NONE)

PP1V05_FW PGOOD/FW_RESET_L

FireWire Port Power Switch

- FW_PORT_FAULT_PU

3.3V FW FET

I(max) = 1.7A (85C)

1.05V FW FET

- =PPVP_FW_SUMNODE (power passthru summation node)

- =PPBUS_S5_FWPWRSW (system supply for bus power)

Power aliases required by this page:

Page Notes

2

1

0.1UF

10% 16V X5R 402

C4276

NOSTUFF

PLACE_NEAR=U4200.1:4mm

0.1UF

16V X5R

10%

402

C4200

1

2

PLACE_NEAR=J4310.4:4mm

LLP

TPD4S1394

U4200

7

8

5

4

2

1

3

6

CRITICAL

402

MF-LF

1/16W

5%

100K

R4201

1

2

BSS8402DW

SOT-363

Q4262

6

2

1

402

MF-LF

1/16W

5%

10

R4263

1

2

402

1/16W

5%

MF-LF

10K

R4262

1

2

SOT-363

BSS8402DW

Q4262

3

5

4

SSM6N15FEAPE

SOT563

Q4261

6

2

1

402

NOSTUFF

25V X5R

0.1UF

10%

C4261

1

2

330K

1/16W 402

5%

1

2

MF-LF

R4261

MF-LF

1/16W

5%

470K

402

R4260

1

2

39 41 96

20 40

39 40

C4202

10%

2

1

CERM

1UF

6.3V 402

B1

A1

B2

A2

C2

C1

U4202

CSP

TPS22924

CRITICAL

4

5

3

Q4261

SSM6N15FEAPE

SOT563

17 25

2

1

C4201

CERM

10%

1UF

6.3V 402

B1

A1

B2

A2

C2

C1

U4201

TPS22924

CSP

CRITICAL

2

10K

MF-LF

5%

1/16W

402

R4277

1

2

1

R4276

402

5% 1/16W MF-LF

100K

3

5

Q4276

DMB53D0UV

CRITICAL

SOT-563

4

39 41

20 40

2

1

R4275

402

1K

5% MF-LF

1/16W

0.1UF

1

2

10% X5R

25V 402

C4260

CRITICAL

5

6

8

4

1

2

3

Q4260

7

SOI-HF

NDS9407

DMB53D0UV

1

2

6

Q4275

CRITICAL

SOT-563

2

1

1K

5%

402

MF-LF

PLACE_NEAR=C4360.1:4mm

R4272

1/16W

BC847CDXV6TXG

4

3

5

Q4270

CRITICAL

SOT563

R4270

2

1

330K

1/16W 402

5% MF-LF

2

1

R4273

12K

402

MF-LF

1/16W

5%

1

6

2

CRITICAL

BC847CDXV6TXG SOT563

Q4270

R4271

1

56K

MF-LF 402

5% 1/16W

2

1

C4270

16V X5R 402

0.1UF

10%

1

2

6

Q4299

DMB53D0UV

SOT-563

CRITICAL

2

1

C4281

6.3V

10%

CERM

402

1UF

21

R4280

10K

1/16W

1%

MF-LF

402

4

3

5

Q4299

SOT-563

DMB53D0UV

CRITICAL

2

1

R4281

402

100K

5% MF-LF

1/16W

4

3

5

Q4275

CRITICAL

SOT-563

DMB53D0UV

8

20 40

21

R4283

402

5%

MF-LF

1/16W

10K

39

19 27

31

SOT-563

CRITICAL

2

6

Q4276

1

DMB53D0UV

CRITICAL

CRS08-1.5A-30V

D4260

2

SM

1

1.5A-24V

CRITICAL

F4260

1812L15024HF

1 2

FireWire Port Power

SYNC_MASTER=K20A_MLB SYNC_DATE=03/26/2009

FW_PORT1_TPA_P FW_PORT1_TPA_N

FW_PORT1_TPB_P FW_PORT1_TPB_N

PP3V3_FW_FWPHY

PP3V3_S0

PP1V0_FW

PPCPUVTT_S0

FW_CLKREQ_L

FW_CLKREQ_PHY_L

MAKE_BASE=TRUE

FW_CLKREQ_PHY_L

PPBUS_FW_FWBOOST

FW_PLUG_DET_L

P1V0_RESET_GATE

VOLTAGE=10V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PP10V_FW_D

PLT_RESET_L

FW_PLUG_DET_L

P1V0_FW_RC

PP3V3_S0

PPVIN_FW_FWPHY

FW_RESET_L

FW_PLUG_DET

FW_DET_EMIT

FW_P1_TPBIAS_R

PPCPUVTT_S0

FW_PWR_EN

FW_WAKE

FW_DET_MIRROR

PP10V_FW

FW_PWR_EN_L

FW_P1_TPBIAS

FW643_WAKE_L

PPVP_FW

PP3V3_FW_FWPHY

TP_FW_LATEVG_VCLMP

FWPWR_EN_TRI_R

FWPWR_EN_TRI

FWPWR_EN

FWPWR_EN_L

FWPWR_EN_L_DIV

PPBUS_G3H

FW_PWR_EN

PP3V3_S0

42 OF 132 40 OF 103

7

39 40 41

6 7 8

25 26 27 28 30 34 37 40 42 47 48

49 52 53 55 59 63 64 69 70 71 72 73 74

81 84 85 86 88 99

101

6 7

72

6 7

10

12 13 15 25 26 40 71 74

101

39

40

7

72

8

20 40

6 7 8

25 26 27 28 30 34 37 40 42 47 48

49 52 53 55 59 63 64 69 70 71 72 73 74

81 84 85 86 88 99

101

7

39 72

6 7

10 12 13 15 25 26 40 71 74

101

7 8

72

8

39

6 7

41

7

39 40 41

6 7 8

50 66 67 68 70 71 83 87

6 7 8

25 26 27 28 30 34 37 40 42 47

48 49 52 53 55 59 63 64 69 70 71 72

73 74 81 84 85 86 88 99

101

SC/NC

TPA+

TPA(R)

VG

VPTPB+

TPB(R)

TPB-

TPA-

CHASSIS

GND

SGD

(SYM-VER2)

G

S

(SYM-VER1)

D

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Signal aliases required by this page:

- =GND_CHASSIS_FW_PORT1

- =PP3V3_FW_LATEVG

- =GND_CHASSIS_FW_EMI_R

- =PPVP_FW_PORT1

local grounds per 1394b spec

Note: Trace PPVP_FW_PORT1 must handle up to 5A

When a bilingual device is connected to a

TPA<R>

VG

TPB+ VP

NC

properly terminate unused signals.

BOM options provided by this page:

PORT 1

FireWire TPA/TPB pairs to their

the necessary aliases to map the

1394b implementation based on Apple FireWire Design Guide (FWDG 0.6, 5/14/03)

(NONE)

BILINGUAL

OUTPUT

(NONE)

TPA+

TPA-

TPBTPB<R>

NC

INPUT

AREF needs to be isolated from all

(FW_PORT1_BREF)

(GND_FW_PORT1_VG)

Cable Power

NOTE: FireWire TPA/TPB pairs are NOT

appropriate connectors and/or to

ground for speed signaling and connection

BREF should be hard-connected to logic

between them (to avoid ground offset issue)

beta-only device, there is no DC path

514S0605

Place close to FireWire PHY

FW spec calls out 0.33uF

Termination

to apply to entire TPA/TPB XNets.

assumed that FireWire PHY page will

Power aliases required by this page:

- Port "1" Bilingual (1394B)

- 1-port Portable Power Class (0)

NOTE: This page is expected to contain

Configures PHY for:

provide the appropriate constraints

constrained on this page. It is

TI PHYs require 1uF even though

Page Notes

FireWire PHY Config Straps

PLACE_NEAR=U4100.A6:4mm

1/16W MF-LF

56.2

SIGNAL_MODEL=EMPTY

402

1%

R4363

1

2

4.99K

MF-LF

402

1%

1/16W

R4364

1

2

1/16W

56.2

SIGNAL_MODEL=EMPTY

MF-LF 402

1%

PLACE_NEAR=U4100.B6:4mm

R4362

1

2

220pF

CERM 402

5% 25V

C4364

1

2

PLACE_NEAR=U4100.B5:2mm

SIGNAL_MODEL=EMPTY

56.2

MF-LF

402

1%

1/16W

R4361

1

2

0.33UF

CERM-X5R 402

10%

6.3V

C4360

1

2

402

SIGNAL_MODEL=EMPTY

56.2

MF-LF

1% 1/16W

R4360

1

2

PLACE_NEAR=J4310.5:3mm

0.1uF

X7R

603-1

10% 50V

C4319

1

2

1M

MF-LF 402

5% 1/16W

R4319

1

2

0.01UF

X7R 402

10% 50V

C4314

1

2

CRITICAL

FERR-250-OHM

SM

L4310

1 2

CRITICAL

1394B-M97

F-RT-TH

J4310

1

10 11 12 13

2

3

4

5

6

7

8

9

10K

MF-LF

402

1%

1/16W

R4381

1

2

10K

MF-LF

402

1%

1/16W

R4382

1

2

10K

MF-LF

402

1%

1/16W

R4380

1

2

Q4300

BSS8402DW

SOT-363

3

5

4

BSS8402DW

SOT-363

Q4300

6

2

1

330K

MF-LF

402

5%

1/16W

R4312

1

2

470K

MF-LF

402

5%

1/16W

R4311

1

2

SYNC_DATE=07/08/2009

SYNC_MASTER=K18_MLB

FireWire Ports

ESD_HOT=TRUE

FW_PORT1_TPA_P

ESD_HOT=TRUE

FW_PORT1_TPB_N

ESD_HOT=TRUE

FW_PORT1_TPB_P

ESD_HOT=TRUE

FW_PORT1_AREF

PP3V3_FW_FWPHY

PLACE_NEAR=U4100.A5:2mm

FW_PORT1_TPA_P FW_PORT1_TPA_N FW_PORT1_TPB_P FW_PORT1_TPB_N

PPVP_FW

CPS_EN_L_DIV

CPS_EN_L

PP3V3_FW_FWPHY

PPVP_FW_CPS

NC_FW2_TPBP

MAKE_BASE=TRUE

NC_FW2_TPBP

NC_FW2_TPBN

MAKE_BASE=TRUE

NC_FW0_TPAP NC_FW2_TPAN

NC_FW0_TPBP

MAKE_BASE=TRUE

FWPHY_DS0

FWPHY_DS1

FWPHY_DS2

FWPHY_DS0

MAKE_BASE=TRUE

FWPHY_DS2

MAKE_BASE=TRUE

FWPHY_DS1

MAKE_BASE=TRUE

PPVP_FW

FW_PORT1_TPB_C

FW_PORT1_TPB_N

MAKE_BASE=TRUE

FW_PORT1_TPA_P

MAKE_BASE=TRUE

FW_PORT1_TPA_N

MAKE_BASE=TRUE

NC_FW0_TPBP NC_FW2_TPBN

NC_FW0_TPBN

NC_FW2_TPBIAS

MAKE_BASE=TRUE

NC_FW0_TPBIAS

MAKE_BASE=TRUE

NC_FW0_TPAP

MAKE_BASE=TRUE

NC_FW2_TPAN

MAKE_BASE=TRUE

NC_FW2_TPAP

NC_FW0_TPAN

NC_FW2_TPBIAS

NC_FW0_TPBIAS

NC_FW0_TPAN

MAKE_BASE=TRUE

NC_FW2_TPAP

MAKE_BASE=TRUE

NC_FW0_TPBN

MAKE_BASE=TRUE

FW_PORT1_TPB_P

MAKE_BASE=TRUE

FW_P1_TPBIAS

MIN_LINE_WIDTH=0.4 mm

PPVP_FW_CPS

VOLTAGE=12.6V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

PPVP_FW_PORT1_F

VOLTAGE=33V

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

ESD_HOT=TRUE

FW_PORT1_TPA_N

43 OF 132 41 OF 103

39 40 41 96

7

39 40 41

39 40 41 96

6 7

40 41

7

39 40 41

39 41

6

39 41

6

39 41

6

39 41

6

39 41 96

6

39 41

6

39 41 96

39 41

6 7

40 41

39 40 41 96

6

39 41 96

6

39 41

6

39 41 96

6

39 41

6

39 41 96

6

39 41

6

39 41

39 41 96

6

39 41

39 41 96

6

39 41

6

39 41 96

39 40 41 96

39 40

39 41

39 40 41 96

SYM_VER-1

OUT OUT

OUT

SYM_VER-1

IN

OUT

IN

B_SD

A_SD

A_INP A_INN

A_OUTN

A_OUTP

VDD

GND

THRM

I2C_ADDR

I2C_EN

B_INN B_INP

B_OUTN B_OUTP

EN AUTOPW_EN

SCL_CTL SDA_CTL

PAD

OUT

IN

S

G

D

BI

IN

SYM_VER-1

D

SG

D

SG

SYM_VER-1

NC

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

SATA HDD Port

SATA ODD Port

NOTE: 3.3V must be S0 if 5V is S3 or S5 to ensure the drive is unpowered in S3/S5.

ODD Power Control

Indicates disc presence

SATA REDRIVER

338S0778

516S0350

516S0617

NO STUFF

1 2

402

1/16W

MF-LF

5%

0

R4511

2

402

10%

6.3V

1

CERM-X5R

1UF

C4514

PLACE_NEAR=U4510.6:3mm

16V

2

1

402

CERM

C4519

0.01UF

10%

PLACE_NEAR=U4510.6:3mm

10%

0.01UF

1

C4516

402

CERM

16V

2

0.01UF

C4515

CERM

10% 16V 402

21

CRITICAL

4

PLACE_NEAR=J4501.6:4mm

DLP11S

90-OHM-100MA

FL4502

3

21

C4511

0.01UF

16V10%

CERM

402

21

CERM

C4510

40210% 16V

0.01UF

21

R4599

CRITICAL

1%

43

21

1206

0.002

MF

1/4W

57 99

CRITICAL

1/4W

1%

1206

MF

0.002

R4598

123

4

57 99

10%

C4526

21

0.01UF

16V

CERM

402

CERM

C4525

0.01UF

21

40210% 16V

4 3

2

DLP11S

1

90-OHM-100MA

CRITICAL

PLACE_NEAR=J4500.11:4mm

FL4525

17 93

17 42 93

1 2

16V10%

CERM

402

0.01UF

C4518

C4517

16V10%

21

402

CERM

0.01UF

C4513

402

CERM

1 2

16V10%

0.01UF

C4512

1 2

40210%

CERM

16V

OMIT

8

15

7

12

14

PS8515A

17

4

2

9

20

6

16

13321

10

19 18

5

1

CRITICAL

11

TQFN

U4510

RDRV_8515_A1&RDRV_8515_A2

402

1 2

1/16W

MF-LF

5%

0

R4512

6

46

R4510

0

1 2

402

1/16W

MF-LF

5%

17 25

MF-LF

R4590

1/16W

5%

33K

402

1

2

CRITICAL

Q4590

TPCP8102

23V1K-SM

21 3

4

65 87

1/16W

R4516

NO STUFF

21

5%

0

MF-LF

402

RDRV_8515_A1&RDRV_8515_A2

21

R4515

0

5%

1/16W MF-LF

402

6

17 25 26 28 30 32 34 48 49 64 94

402

RDRV_8515_A1&RDRV_8515_A2

2 1

R4514

5%

MF-LF

1/16W

0

6

17 25 26 28 30 32 34 48 49 64 94

RDRV_8515_A1&RDRV_8515_A2

402

5%

MF-LF

1/16W

0

R4513

12

NO STUFF

2

1

R4519

100K

5% 1/16W MF-LF 402

21

R4518

NO STUFF

1/16W MF-LF

402

5%

0

5%

21

R4517

1/16W

0

MF-LF

402

NO STUFF

2

1

R4520

402

100K

5% 1/16W MF-LF

SIGNAL_MODEL=EMPTY

0.01UF

CERM

10% 16V

RDRV_BYPASS

C4531

402

21

SIGNAL_MODEL=EMPTY

0.01UF

CERM

10% 16V

RDRV_BYPASS

C4522

402

21

SIGNAL_MODEL=EMPTY

0.01UF

CERM

10% 16V

RDRV_BYPASS

C4523

402

21

SIGNAL_MODEL=EMPTY

0.01UF

CERM

10% 16V

RDRV_BYPASS

C4524

402

21

SIGNAL_MODEL=EMPTY

RDRV_BYPASS

51.1

1%

MF-LF

1/16W

R4521

402

2 1

SIGNAL_MODEL=EMPTY

51.1

1% 1/16W MF-LF

RDRV_BYPASS

R4522

402

2 1

R4523

SIGNAL_MODEL=EMPTY

5%

MF-LF

1/16W

0

RDRV_BYPASS

402

2 1

R4524

0

5% 1/16W MF-LF

SIGNAL_MODEL=EMPTY

RDRV_BYPASS

402

2 1

C4541

SIGNAL_MODEL=EMPTY

50V

5%

402

CERM

10PF

RDRV_BYPASS

SIGNAL_MODEL=EMPTY

402

CERM

10PF

RDRV_BYPASS

C4542

5%

50V

12

13

CRITICAL

55560-0168

9

15

14

8 7

6 5

4 3

2

16

11

10

1

J4500

M-ST-SM-LF

20

CRITICAL

FL4520

PLACE_NEAR=J4500.5:4mm

DLP11S

90-OHM-100MA

12

3 4

SOT563

Q4596

3

5

4

SSM6N15FEAPE

1/16W

100K

5%

402

R4597

1

2

MF-LF

SOT563

Q4596

6

2

1

SSM6N15FEAPE

5%

1/16W

100K

402

MF-LF

R4596

1

2

100K

R4595

MF-LF

1/16W

5%

402

21

C4595

10%

402

CERM

10V

2

1

0.068UF

16V

10%

CERM

402

0.01UF

C4596

1 2

C4521

CERM

402

0.01UF

10%2116V

40216V

CERM

0.01UF

C4520

10%

21

L4500

PLACE_NEAR=J4501.1:3mm

FERR-70-OHM-4A

1

0603

2

CRITICAL

PLACE_NEAR=L4500.1:3mm

402

C4501

0.1UF

CERM

2

10V

20%

1

PLACE_NEAR=J4501.12:4mm

FL4501

90-OHM-100MA

43

2 1

CRITICAL

DLP11S

PLACE_NEAR=L4500.2:3mm

1

C4502

2

CERM

0.1UF

10V 402

20%

QT500166-L020

M-ST-SM

9

13

87

65

43

2

1615

14

1211

10

1

CRITICAL

J4501

SYNC_DATE=03/26/2009

SATA Connectors

SYNC_MASTER=K20A_MLB

SATA 3GB/S REDRIVER, LOW POWER

RDRV_8511

CRITICALU45101338S0769

338S0778

RDRV_8515_A1

SATA 3GB/S REDRIVER, LOW POWER

CRITICALU45101

338S0848

RDRV_8515_A2

1 U4510 CRITICAL

SATA 3GB/S REDRIVER, LOW POWER

SATA_ODD_R2D_C_P

SATA_HDD_D2R_C_N

SATA_HDD_R2D_BYPASS_N

SATA_HDD_R2D_BYPASS_P

SATA_HDD_D2R_N

SATA_HDD_D2R_P

SATA_HDD_R2D_C_N

SATA_HDD_R2D_C_P

SATA_HDD_D2R_BYPASS_P

SATA_HDD_D2R_C_P

SATA_HDD_D2R_BYPASS_N

SATA_HDD_R2D_RDRV_IN_P

SATA_HDD_R2D_RDRV_IN_N

SATA_HDD_D2R_RDRV_OUT_P

SATA_HDD_D2R_RDRV_OUT_N

SATA_HDD_D2R_N

SATA_HDD_R2D_C_N

SATA_HDD_R2D_UF_N

SATA_HDD_R2D_C_P

SATA_HDD_R2D_UF_P

SATA_HDD_D2R_P

SATA_ODD_D2R_P

SATA_ODD_D2R_UF_N

PP5V_S0_HDD_FLT

MIN_LINE_WIDTH=0.6mm VOLTAGE=5V

MIN_NECK_WIDTH=0.4mm

SATA_HDD_D2R_RDRV_IN_P

SATARDRVR_A_I2C_ADDR

SATA_HDD_D2R_RDRV_IN_N

ISNS_HDD_N

ODD_PWR_EN_L

SATA_ODD_D2R_C_P

PP1V5_S0

SATA_HDD_D2R_UF_P

ISNS_HDD_P

SATA_HDD_D2R_C_N

SATA_HDD_R2D_RDRV_OUT_N

PP3V3_S0

SATARDRVR_A_EN

SATARDRVR_A_I2C_SCL

SATA_HDD_D2R_C_P

SATA_HDD_D2R_UF_N

SATA_HDD_R2D_UF_P

SATA_HDD_R2D_N SATA_HDD_R2D_P

PP3V3_S0

PP5V_S0

ISNS_ODD_N

PP5V_S0_HDD_R

VOLTAGE=5V

MIN_NECK_WIDTH=0.4mm

MIN_LINE_WIDTH=0.6mm

SATARDRVR_A_I2C_SDA

SATA_HDD_R2D_UF_N

ISNS_ODD_P

PP5V_S0

ODD_PWR_SS

SATA_ODD_D2R_N

SATA_ODD_R2D_UF_N

SATA_ODD_R2D_C_N

SATARDRVR_A_I2C_EN

SATARDRVR_A_A_SD SATARDRVR_A_B_SD

PP1V5_S0

SATARDRVR_A_B_SD SATARDRVR_A_A_SD

PP1V5_S0

SATARDRVR_A_I2C_SDA

PP1V5_S0

SATARDRVR_A_I2C_SCL

SMBUS_PCH_CLK

SMBUS_PCH_DATA

SATA_ODD_R2D_UF_P

SATA_ODD_D2R_C_N

VOLTAGE=5V

MIN_NECK_WIDTH=0.4mm

MIN_LINE_WIDTH=0.6mm

PP5V_SW_ODD_R

ODD_PWR_EN_LS5V_L

SATA_ODD_D2R_UF_P

SATARDRVR_A_AUTOPWR_EN

SATA_HDD_R2D_RDRV_OUT_P

PP5V_SW_ODD

VOLTAGE=5V

MIN_NECK_WIDTH=0.4mm

MIN_LINE_WIDTH=0.6mm

ODD_PWR_EN

SATARDRVR_A_I2C_EN

PP1V5_S0

SATA_ODD_R2D_P SATA_ODD_R2D_N

SMC_ODD_DETECT

45 OF 132 42 OF 103

42 93

99

17 42 93

17 42 93 42 99

17 42 93 42

99

17 42 93

6

99

6

99

93

7 34 42 59 72 74 99

6

99

42 93

99

6 7 8

25 26 27 28 30 34 37 40 42 47 48

49 52 53 55 59 63 64 69 70 71 72 73 74

81 84 85 86 88 99

101

42

42 93

6

99

42 99

6

93

6

93

6 7 8

25 26 27 28 30 34 37 40 42 47 48

49 52 53 55 59 63 64 69 70 71 72 73 74

81 84 85 86 88 99

101

6 7 8

23 42 48 53 55 69

70 71 73 87

102

42

42 99

6 7 8

23 42 48 53 55 69 70 71 73 87

102

99

42 42

42

7

34 42 59 72 74 99

42

7

34 42 59 72 74 99

42

7

34 42 59 72 74 99

42

99

93

6

99

6

57

42

7

34 42 59 72 74 99

6

93

6

93

OUT

BI

SYM_VER-1

IN

OUT

IN

SYM_VER-1

BI

OUT

IOIONC

GND

VBUS

NC

IOIONC

GND

VBUS

NC

OUT2

TPAD

GND

OUT1

OC1*

EN2

EN1

OC2*

IN

VCC

GND

SELOE*

D+ D-

Y+ Y-

M+ M-

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

USB/SMC Debug Mux

SEL=1 Choose USB

SEL=0 Choose SMC

Port Power Switch

Left USB Port B

Left USB Port A

PLACE_NEAR=J4600.1:8mm

CRITICAL

0603

FERR-220-OHM-2.5A

L4605

1 2

6.3V

CRITICAL

20%

100UF

POLY-TANT CASE-B2-SM

C4696

1

2

6.3V X5R 603

20%

10UF

C4695

1

2

20% 10V CERM 402

0.1UF

C4691

1

2

35

36 93

20%

SMC_DEBUG_YES

0.1UF

10V 402

CERM

C4650

1

2

1/16W 402

10K

5% MF-LF

R4650

1

2

PLACE_NEAR=J4600.2:8mm

90-OHM-100MA

DLP11S

CRITICAL

L4600

1 2

34

6

46 47 48

6

46 47 48

46

SMC_DEBUG_NO

1/16W MF-LF

0

5%

402

R4651

1 2

MF-LF

1/16W

5%

402

0

SMC_DEBUG_NO

R4652

1 2

20%

CERM

0.01uF

402

16V

C4605

1

2

20%

0.01uF

16V CERM 402

C4615

1

2

PLACE_NEAR=J4610.1:8mm

FERR-220-OHM-2.5A

0603

CRITICAL

L4615

1 2

PLACE_NEAR=J4610.2:8mm

DLP11S

CRITICAL

90-OHM-100MA

L4610

1 2

34

20%

603

10UF

X5R

6.3V

C4617

1

2

CASE-B2-SM

20%

CRITICAL

100UF

6.3V POLY-TANT

C4616

1

2

35 93

36

SLP1210N6

RCLAMP0502N

CRITICAL

D4600

1

5 42 3

6

CRITICAL

RCLAMP0502N

SLP1210N6

D4610

1

5 42 3

6

6.3V

20% X5R

10UF

603

C4690

1

2

J4600

USB

4

CRITICAL

F-RT-TH-M97-4

1 2 3

5 6

7 8

USB

CRITICAL

F-RT-TH-M97-4

J4610

1 2 3 4

5 6

7 8

Q4690

TPS2064DGN

MSOP

CRITICAL

3

4

1

2

8

5

7

6

9

5% MF-LF

5.1K

1/16W 402

R4690

1

2

0.47UF

X5R 402

10V

10%

C4692

1

2

PI3USB102ZLE

SIGNAL_MODEL=USB_MUX

CRITICAL

SMC_DEBUG_YES

TQFN

U4650

6

7

3

4

5

8

10

9

2

1

External USB Connectors

SYNC_DATE=06/09/2009

SYNC_MASTER=K17_WFERRY

MIN_NECK_WIDTH=0.375 mm

MIN_LINE_WIDTH=0.5 mm

PP5V_S3_RTUSB_B_ILIM

VOLTAGE=5V

USB2_EXTA_MUXED_P

USB2_EXTA_MUXED_N

PM_SLP_S4_L

VOLTAGE=5V

MIN_LINE_WIDTH=0.5 mm

PP5V_S3_RTUSB_A_F

MIN_NECK_WIDTH=0.375 mm

USB2_LT1_P

USB2_LT1_N

PP5V_S3_RTUSB_B_F

MIN_NECK_WIDTH=0.375 mm

MIN_LINE_WIDTH=0.5 mm VOLTAGE=5V

USB_LT2_N USB_LT2_P

MIN_NECK_WIDTH=0.375 mm VOLTAGE=5V

MIN_LINE_WIDTH=0.5 mm

PP5V_S3_RTUSB_A_ILIM

PP5V_S3

USB_PWR_EN

PP3V42_G3H

USB_EXTA_N

USB_EXTA_P

USB_EXTB_N

USB_EXTB_P

USB_EXTA_OC_L

USB_EXTB_OC_L

USB_DEBUGPRT_EN_L

SMC_RX_L SMC_TX_L

46 OF 132 43 OF 103

99

18 31 46 47 73 74

6

99

6

99

6

99

6

99

6 7

31 33 44 45 47 51 55 68 73 83

103

6 7

17 21 23 45 46 47 48 49

50 51 54 65 66 74

OUT

BI

SYM_VER-1

BI

IOIONC

GND

VBUS

NC

TPAD

OUT1

GND

OC* EN*

IN2

IN1

OUT2

OUT3

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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REVISION

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SIZE

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PAGE TITLE

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A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

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PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

ENABLE TIED LOW SO INPUT POWER SOURCE MUST BE S3!!!

Port Power Switch

LEFT USB PORT C

2

1

C4780

603

10UF

X5R

20%

6.3V

2

1

C4781

402

CERM

10V

20%

0.1UF

8

35

2

1

C4785

10UF

6.3V X5R 603

20%

2

1

C4786

CRITICAL

20%

100UF

POLY-TANT

6.3V CASE-B2-SM

35 93

PLACE_NEAR=J4720.2:8mm

CRITICAL

4 3

21

L4720

90-OHM-100MA

DLP11S

2

1

C4725

20%

0.01uF

CERM

402

16V

35 93

PLACE_NEAR=J4720.1:8mm

21

L4725

FERR-220-OHM-2.5A

0603

CRITICAL

6

32 45

1

D4720

CRITICAL

RCLAMP0502N

SLP1210N6

9

8

7

6

5

3

2

1

4

U4780

CRITICAL

MSOP

TPS2068

F-RT-TH-M97-4

8

7

6

5

3 4

2

1

J4720

USB

CRITICAL

PROJECT SPECIFIC CONNS

SYNC_MASTER=K20A_MLB SYNC_DATE=03/26/2009

USB_EXTC_P

USB_EXTC_N

VOLTAGE=5V

MIN_NECK_WIDTH=0.375 mm

MIN_LINE_WIDTH=0.5 mm

PP5V_S3_RTUSB_C_F

USB_LT3_P

USB_LT3_N

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.375 mm VOLTAGE=5V

PP5V_S3_RTUSB_C_ILIM

PP5V_S3

USB_EXTC_OC_L

47 OF 132 44 OF 103

6

99

6

99

6 7

31 33 43 45 47 51 55 68 73 83

103

BI BI

VCC

P1.0/D+ P1.1/DP1.2/VREG P1.3/SSEL P1.4/SCLK

P1.5/SMOSI

P1.6/SMISO

P0.0

P0.1 INT0/P0.2 INT1/P0.3

TIO1/P0.6

NC

TIO0/P0.5

INT2/P0.4

VSSPAD

THRML

IN

NC NC NC NC

NC NC NC NC NC NC NC NC

NC NC NC NC NC

NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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REVISION

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SIZE

D

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PAGE TITLE

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A

D

2 1

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PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

35 93

2

1

C4803

402-1

1UF

10% 10V X5R

11

14

1

2

25

19

18

17

16

15

13

12

6

7

24

23

22

21

20

10

9

8

3

4

5

U4800

QFN

CRITICAL

OMIT

CY7C63803-LQXC

2

1

C4801

0.1UF

402

16V

10% X7R-CERM

2

1

C4804

CERM

0.001UF

50V 402

10%

21

R4800

402

1/16W

100

5%

MF-LF

6

45

6

5

4

3

2

1

J4800

F-RT-SM

CRITICAL

FF18-6A-R11AD-B-3H

2

1

C4805

16V 402

0.1UF

X7R-CERM

10%

PLACE_NEAR=J4800.1:5mm

1

402

0.1UF

16V

10% X7R-CERM

C4806

2

PLACE_NEAR=J4800.2:5mm

1

402

CERM

0.001UF

50V

C4807

10%

2

PLACE_NEAR=J4800.4:5mm

MF-LF

1/16W

402

10

5%

R4805

1 2

PLACE_NEAR=J4800.1:5mm

21

R4806

10

5%

402

1/16W

MF-LF

PLACE_NEAR=J4800.2:5mm

2

1

C4808

402

CERM

0.001UF

50V

10%

PLACE_NEAR=J4800.5:5mm

5%

100

1/16W

MF-LF

402

R4807

1 2

PLACE_NEAR=J4800.4:5mm

21

R4808

5%

1/16W

MF-LF

402

4.7

PLACE_NEAR=J4800.5:5mm

21

R4801

OMIT

402

NONE NONE

NONE

SHORT

Front Flex Support

SYNC_DATE=03/26/2009SYNC_MASTER=K20A_MLB

PP5V_S3

PP5V_S3_IR_R

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

VOLTAGE=5V

SMC_LID

SMC_LID_R

SYS_LED_ANODE

SYS_LED_ANODE_R

PP3V42_G3H

MIN_LINE_WIDTH=0.3 mm

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=3.42V

PP3V42_G3H_LIDSWITCH_R

IR_RX_OUT

PP5V_S3

USB_IR_P

DIFFERENTIAL_PAIR=USB2_IR

IR_VREF_FILTER

IR_RX_OUT

IR_RX_OUT_RC

VOLTAGE=5V

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.25 mm

PP5V_S3_IR_USB

DIFFERENTIAL_PAIR=USB2_IR

USB_IR_N

48 OF 132

P/N 338S0633

518S0692

45 OF 103

6 7

31 33 43 44 45 47 51 55 68 73 83

103

6

46 47 54

6

47

6

6 7

17 21 23 43 46 47 48 49 50

51 54 65 66 74

6

45

6 7

31 33 43 44 45 47 51 55 68 73 83

103

IN

OUT

IN

OUT

IN IN IN IN IN IN IN IN

IN

OUT IN

OUT

BI

IN

OUT

BI OUT

IN

OUT

IN

OUT OUT OUT OUT

IN

IN IN

IN

IN IN

IN

OUT

IN

BI BI BI BI BI BI

OUT OUT

OUT

IN

OUT

IN

BI

OUT

IN

OUT

NC

OUT

NC

NC NC NC

NC

NC NC

NC NC NC

NC

NC NC

NC

NC NC

IN

OUT

P13 P14 P15 P16 P66

P10 P11 P12

P17

P20 P21 P22 P23 P24 P25 P26 P27

P30 P31 P32 P33 P34

P36 P37

P40 P41 P42 P43 P44 P45 P46 P47

P50 P51 P52

P60 P61 P62 P63 P64 P65

P67

P70 P71 P72 P73 P74 P75 P76 P77

P80 P81

P84 P85 P86

P90 P91 P92 P93 P94 P95 P96 P97

P35

P83

P82

(1 OF 3)

PA5

PA4

PA0 PA1 PA2 PA3

PA6 PA7

PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7

PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7

PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7

PE0 PE1 PE2 PE3 PE4 PF0

PF1 PF2 PF3 PF4 PF5 PF6 PF7

PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7

PH0 PH1 PH2 PH3 PH4 PH5

(2 OF 3)

RES*

NMI

VSS

VCLVCC

NC

MD2

MD1

ETRST

AVSS

AVREF

AVCC

EXTAL

XTAL

(3 OF 3)

OUT

NC

INBI

BI BI BI BI

IN IN IN

OUT

BI

IN IN IN IN

BI

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

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345678

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B

8 7 5 4 2 1

SMC_IG_THROTTLE_L for MG systems.

SMC_PB3:

NOTE: SMS Interrupt can be active high or low, rename net accordingly. If SMS interrupt is not used, pull up to SMC rail.

(OC)

(OC) (OC) (OC)

(OC) (OC)

(See below)

(OC)

(DEBUG_SW_1)

(OC)

Otherwise, TP/NC okay (was ISENSE_CAL_EN)

those designated as inputs require pull-ups.

(OC)

NOTE: P94 and P95 are shorted, P95 could be spare.

pins designed as outputs can be left floating,

NOTE: Unused pins have "SMC_Pxx" names. Unused

2

1

C4902

22UF

CERM

805

20%

6.3V

6

18 48

6

47 48 66

6

47 54

2

1

C4907

0.47UF

CERM-X5R

402

10%

6.3V

PLACE_NEAR=U4900.E1:3mm

2

1

C4903

402

20% 10V CERM

0.1UF

PLACE_NEAR=U4900.M12:10mm

2

1

C4920

0.1UF

CERM

402

20% 10V

PLACE_NEAR=U4900.M12:10mm

21

R4999

4.7

MF-LF

5%

1/16W

402

2

1

C4904

0.1UF

CERM 402

20% 10V

2 1

XW4900

PLACE_NEAR=U4900.L3:4mm

SM

18 25

69

2

1

C4905

0.1UF

CERM 402

20% 10V

18

74

25 27 74 88

47

2

1

C4906

0.1UF

CERM 402

20% 10V

50

51

50

47 50

47 65 66

6

43 46 47 48

6

43 46 47 48

74

49 57 97

102

2

1

R4909

10K

MF-LF

5%

1/16W

402

6

48

6

48

2

1

R4901

10K

MF-LF 402

5% 1/16W

2

1

R4902

10K

MF-LF 402

5% 1/16W

2

1

R4903

NO STUFF

0

MF-LF 402

5% 1/16W

2

1

R4998

10K

MF-LF 402

5% 1/16W

43

47 65

18

6

42

34 47

20

47

53

6

47

6

47

6

47

6

47

53

56

47 51

56

47 50

47 51

6

47 48

47

6

47 48

6

47 48

6

47 48

45 47 54

6

49 65 66 97

6

49 65 66 97

6

33 49 55 97

6

33 49 55 97

49 52 97

47

6

47

47 51

6

43 46 47 48

6

43 46 47 48

47

81

6

17 48

28 30 47

6

18 27

6

48

17

6

18 48

81

56

18 47 74

6

47 65

6

47

34

H8S2117

F1

F4

G4

H4

G1

H2

G3

J4

C6

B5

A6

D5

C7

B6

A7

L12

N13

M13

N12

N11

L10

M11

N10

H12

J11

J10

K13

J12

K11

K12

L13

E4

F3

G2

C3

C1

B2

C2

A1

B4

A5

D4

D6

D7

D8

A8

B7

C8

D9

A9

E10

F13

E12

E13

F11

D12

E11

D13

D10

C12

C13

D11

B13

A12

A13

B12

U4900

OMIT

LGA-HF

C4

B3

A4

J2

F2

E2

L6

M7

N6

K6

K7

K8

N7

M8

M4

L4

N4

M5

L5

M6

N5

K5

K4

J1

K2

J3

K1

L7

K9

N8

M9

L8

K10

N9

M10

J13

H11

G12

G10

H13

F12

G13

G11

A11

C11

B10

C10

A10

B9

C9

B8

L2

K3

L1

N2

M2

M3

N1

N3

U4900

OMIT

H8S2117

LGA-HF

M12

A3

C5

B11

F10

L3

D2

E1

H10

M1

B1

D3

E3

E5

H1

D1

A2

H3

L9

L11

U4900

H8S2117

LGA-HF

OMIT

17

47 47

6

17 48 88 94

6

17 48 88 94

6

17 48 88 94

6

17 48 88 94

6

17 48 88 94

27

27 94

55

49 52 82

6

18 31 74 86

18 31 43 47 73 74

18 47

47

49 52 82

49 57 97

102

47

SYNC_DATE=06/09/2009

SYNC_MASTER=K17_WFERRY

SMC

PP3V3_S5_SMC_AVCC

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

TP_SMC_P92

PM_SLP_S4_L PM_SLP_S5_L SMC_CLK32K SMBUS_SMC_0_S5_SDA

SMC_BC_ACOK

SMC_ONOFF_L

PM_SLP_S3_L

SMC_RX_L

SMC_TDI

SMC_LID

SMC_FAN_0_TACH

SMS_Z_AXIS

SMC_CPUVTT_ISENSE

GND_SMC_AVSS

PM_BATLOW_L

MEM_EVENT_A_L

G3_POWERON_L

SMC_TMS

NC_ALS_GAIN

SMC_IG_THROTTLE_L

SMC_GFX_OVERTEMP_L

NC_SMC_FAN_2_CTL NC_SMC_FAN_3_CTL

SMS_X_AXIS SMS_Y_AXIS

SMS_PWRDN

LPC_AD<1>

NC_ESTARLDO_EN

PM_PWRBTN_L

CPUIMVP_VR_ON

RSMRST_PWRGD

SMC_EXCARD_PWR_EN

PP3V3_S5_AVREF_SMC

SMC_VCL

SMC_MD1

PP3V42_G3H

SMC_GFX_ISENSE

SMC_BATT_ISENSE

LPC_CLK33M_SMC

SMC_RESET_L SMC_XTAL

SMC_EXTAL

SMC_KBC_MDE

SMC_TRST_L

SMC_NMI

SMC_THRMTRIP

SMBUS_SMC_B_S0_SCL

SMBUS_SMC_B_S0_SDA

SMBUS_SMC_A_S3_SDA

SMBUS_SMC_BSA_SCL

SMBUS_SMC_BSA_SDA

SMS_INT_L

SMC_SYS_LED

SMC_TDO

SMC_TCK

SMC_CASE_OPEN

SMC_CPU_HI_ISENSE

SMC_GFX_VSENSE

SMC_1V5_S3_ISENSE

SMC_GPU_1V8_ISENSE

NC_SMC_FAN_3_TACH

NC_SMC_FAN_2_TACH

SMC_FAN_1_TACH

SMC_FAN_1_CTL

SMC_FAN_0_CTL

SMC_RUNTIME_SCI_L

USB_DEBUGPRT_EN_L

SMC_PA0

PM_CLKRUN_L LPC_PWRDWN_L

SMC_LRESET_L

SMBUS_SMC_MGMT_SCL

SMC_TX_L

SMC_WAKE_SCI_L

SMC_PBUS_VSENSE

SMC_DCIN_ISENSE

SMC_GPU_VSENSE

SMC_GPU_ISENSE

SMC_CPU_VSENSE

SMC_CPU_ISENSE

SMC_BIL_BUTTON_L

SMC_ADAPTER_EN

SMC_PM_G2_EN

SMBUS_SMC_0_S5_SCL

SMC_RX_L

SMC_TX_L

SMC_SYS_KBDLED

SMC_GFX_THROTTLE_L

SMBUS_SMC_MGMT_SDA

SMC_BATT_ULP_L

LPC_SERIRQ

LPC_FRAME_L

LPC_AD<3>

LPC_AD<2>

LPC_AD<0>

SMC_BMON_MUX_SEL

TP_SMC_P24

ALL_SYS_PWRGD

TP_SMC_RSTGATE_L

SMC_PROCHOT_3_3_L

PM_RSMRST_L

SPI_DESCRIPTOR_OVERRIDE_L

SMC_EXCARD_OC_L

SMC_EXCARD_CP

SMC_ODD_DETECT

SYS_ONEWIRE

PM_SYSRST_L

MEM_EVENT_B_L

SMC_PROCHOT

SMBUS_SMC_A_S3_SCL

TP_SMC_PF5

49 OF 132 46 OF 103

6

47

47 50 51

20 25 47

6

47

6 7

17 21 23 43 45 47 48 49

50 51 54 65 66 74

47

47 65

47 50

47

D

S G

CD

GND

NC

OUT

IN

OUT

IN

OUT

BI

IN

D

S G

GND

OUT

IN

OUT

IN

02

D

SG

NC

IN

E

Q2

C

BD

Q1

GS

OUT

G

D

S

OUT

IN

G

D

S

G

D

S

BI

OUT

NC7

NC6

NC5

NC4

NC2 NC3

OUT

VDD

NC0 NC1

VIO

GND

IN

NC NC NC NC

OUT

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

SMC G3Hot 32kHz Oscillator

To support timed wake-up events in G3Hot

Debug Power "Buttons"

TO SMC

TO CPU

SMC Crystal Circuit

TO CPU

FROM DIMMS

TO/FROM SMC

SMC AVREF Supply

SMC FSB to 3.3V Level Shifting

SMC Reset "Button" / Brownout Detect

System (Sleep) LED Circuit

CPU PM_EXTTS_L / MEM_EVENT_L Level Shifting

2

1

C5000

0.1uF

CERM

402

20% 10V

4

5

3

Q5059

SSM6N15FEAPE

SOT563

2

1

C5020

0.47UF

CERM-X5R 402

10%

6.3V

2

1

C5026

0.01UF

CERM 402

10% 16V

2

1

C5025

10uF

X5R 603

20%

6.3V

R5095

21

SMC_EXCARD

5% 1/16W MF-LF

402

0

21

R5070

10K

MF-LF

4025%

1/16W

21

R5071

100K

MF-LF

4025%

1/16W

21

R5073

10K

MF-LF

4025%

1/16W

21

R5074

100K

MF-LF

4025%

1/16W

R5075

21

2.0K

MF-LF

4025%

1/16W

NO STUFF

R5077

21

1/16W

5% 402

MF-LF

10K

R5078

21

1/16W

5% 402

MF-LF

10K

21

R5079

MF-LF1/16W

5% 402

10K

21

R5080

1/16W

5% 402

MF-LF

10K

21

R5085

10K

5%

1/16W

402

MF-LF

21

R5086

10K

MF-LF

4025%

1/16W

21

R5088

10K

MF-LF

4025%

1/16W

U5000

CRITICAL

1

4

2

3

5

NCP303LSN

SOT23-5-HF

21

R5090

100K

MF-LF

4025%

1/16W

6

46 48 66

46

10 20 91

2

1

R5001

OMIT

0

MF-LF 603

5%

SILK_PART=SMC_RST

1/10W

2

1

R5015

PLACEMENT_NOTE=Place R5015 on top side

OMIT

0

603

SILK_PART=PWR_BTN

MF-LF

1/10W

5%

21

R5062

3.3K

MF-LF

402

5%

1/16W

10 69 91

46

1

2

6

Q5059

SSM6N15FEAPE

SOT563

100K

21

R5091

1/16W

5% 402

MF-LF

21

3

VR5020

CRITICAL

REF3333

SOT23-3

46 47

8

34 36

2

1

1K

402

5% 1/16W MF-LF

R5000

21

R5089

10K

MF-LF

4025%

1/16W

R5081

21

1/16W

5% 402

MF-LF

10K

21

R5010

1/16W

5%

402

MF-LF

0

2

1

Y5010

CRITICAL

20.00MHZ

5X3.2-SM

21

C5011

50V

5%

402

CERM

15pF

21

C5010

5%

402

15pF

CERM

50V

R5087

21

1/16W

5% 402

MF-LF

470K

4

5

3

2

1

U5001

SN74LVC1G02

SOT553-5

4

5

3

Q5032

SSM6N15FEAPE

SOT563

R5093

21

1/16W

5% 402

MF-LF

10K

R5094

21

100K

MF-LF

4025%

1/16W

21

R5072

10K

MF-LF

4025%

1/16W

54

6

46 47 54

46

2

1

1%

402

MF-LF

R5032

1.47K

1/16W

R5031

2

1

1/16W

1%

402

MF-LF

523

2

1

R5030

1/16W

1%

402

MF-LF

20

1 2463

5

Q5030

SOT-563

DMB54D0UV

CRITICAL

6

45

4

3

5

Q5060

DMB53D0UV

SOT-563

2

1

R5061

100K

MF-LF 402

5% 1/16W

1

2

6

Q5060

DMB53D0UV

SOT-563

2

1

R5060

10K

MF-LF 402

5% 1/16W

46

2

1

R5016

PLACEMENT_NOTE=Place R5016 on bottom side

SILK_PART=PWR_BTN

0

MF-LF

603

5%

1/10W

OMIT

28 30 46 47

4

5

3

Q5040

SOT-363

2N7002DW-X-G

R5040

2

1

10K

MF-LF

402

5%

1/16W

2N7002DW-X-G

1

2

6

Q5040

SOT-363

1

2

R5042

1/16W

5%

402

MF-LF

10K

21

R5044

0

MF-LF

402

5%

1/16W

28 30 46 47

10 91

SMC_OSC_YES

2

1

6.3V CERM

4.7UF

603

C5002

20%

SMC_OSC_YES

2

1

C5003

10V

20% 402

CERM

0.1UF

OMIT

1

12

7

11

10

9

8

5

4

3

2

6

U5010

32.768KHZ-9-3.6V SG-3040LC-SM

CRITICAL

FERR-120-OHM-0.2A

SMC_OSC_YES

21

L5010

0603

NO STUFF

21

R5011

22

1/16W

5%

402

MF-LF

21

R5012

1/16W

5%

402

MF-LF

0

18 94

SMC_EXCARD_NOT

100K

21

MF-LF

4025%

1/16W

R5092

46

R5096

100K

21

1/16W

5% 402

MF-LF

6

46 47 54

C5001

1

0.01UF

CERM

402

10% 16V

2

SMC Support

SYNC_MASTER=K17_REF

SYNC_DATE=06/17/2009

353S1912353S1381

ALL

Intersil ISL60002-33

SMS_INT_L

PP3V3_S0

SMC_EXTAL

PP3V42_G3H

SMC_ONOFF_L G3_POWERON_L SMC_LID SMC_TX_L SMC_RX_L

SMC_TDI

SMS_INT_L

SMC_BATT_ULP_L

SMC_PA0

PP3V3_S0

SMC_THRMTRIP

PP3V42_G3H

TP_SMC_P24

SMC_CPUVTT_ISENSE

MAKE_BASE=TRUE

SMC_IG_THROTTLE_L

TP_SMC_PF5

MAKE_BASE=TRUE

SMC_BATT_ULP_L

MAKE_BASE=TRUE

SMC_BATT_ULP_L SMC_IG_THROTTLE_L

SMS_INT_L

MAKE_BASE=TRUE

SMC_GFX_VSENSE SMC_CPU_HI_ISENSE

SMC_GPU_1V8_ISENSE

TP_SMC_P92

MAKE_BASE=TRUE

SMC_CPU_HI_ISENSE

NC_SMC_FAN_2_CTL

SMC_BMON_MUX_SEL

MAKE_BASE=TRUE

SMC_RESET_L

MAKE_BASE=TRUE

SMC_GFX_VSENSE

SMC_GFX_ISENSE

MAKE_BASE=TRUE

SYS_ONEWIRE

MEM_EVENT_B_L

PM_SLP_S4_L

PM_SLP_S5_L

SMC_EXCARD_CP

SMC_CASE_OPEN

SMC_ADAPTER_EN

SMC_EXCARD_OC_L

PP3V3_S0

PP3V42_G3H

MIN_LINE_WIDTH=0.4 mm

GND_SMC_AVSS

VOLTAGE=0V

MIN_NECK_WIDTH=0.2 mm

PP3V3_S5_AVREF_SMC

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm

SMC_ONOFF_L

MEM_EVENT_A_L

MAKE_BASE=TRUE

MEM_EVENT

PM_EXT_TS_L<1>

MEM_EVENT_A_L

PP3V3_S0

SMC_XTAL

SMC_XTAL_R

NC_ESTARLDO_EN NC_ESTARLDO_EN

MAKE_BASE=TRUE

NC_SMC_FAN_3_CTL NC_SMC_FAN_3_CTL

MAKE_BASE=TRUE

NC_SMC_FAN_2_TACH NC_SMC_FAN_2_TACH

MAKE_BASE=TRUE

NC_SMC_FAN_2_CTL

MAKE_BASE=TRUE

PM_THRMTRIP_L

CPU_PROCHOT_L_R

CPU_PROCHOT_L

CPU_PROCHOT_BUF

SMC_PROCHOT

SMC_PROCHOT_3_3_L

NC_ALS_GAIN

SMC_MANUAL_RST_L

SMC_TPAD_RST

SMC_TPAD_RST_L

SMC_ONOFF_L

NC_SMC_FAN_3_TACH

MAKE_BASE=TRUE

NC_SMC_FAN_3_TACH

NC_ALS_GAIN

MAKE_BASE=TRUE

SYS_LED_ILIM

SYS_LED_L

PP5V_S3

SYS_LED_L_VDIV

SYS_LED_ANODE

SMC_SYS_LED

PP3V42_G3H

SMC_CLK32K_R

PM_CLK32K_SUSCLK

SMC_CLK32K

SMC_TMS SMC_TDO

SMC_TCK SMC_BIL_BUTTON_L SMC_BC_ACOK

EXCARD_OC_L

SMC_EXCARD_OC_L

TP_SMC_RSTGATE_L

MAKE_BASE=TRUE

TP_SMC_RSTGATE_L

SMC_BC_ACOKSMC_BC_ACOK

MAKE_BASE=TRUE

SMC_BMON_MUX_SEL

SMC_1V5_S3_ISENSE

MAKE_BASE=TRUE

SMC_CPUVTT_ISENSE

SMC_GPU_1V8_ISENSE

MAKE_BASE=TRUE

TP_SMC_P24

MAKE_BASE=TRUE

TP_SMC_PF5

SMC_GFX_ISENSE

SMC_1V5_S3_ISENSE

TP_SMC_P92

MAKE_BASE=TRUE

PM_EXT_TS_L<0>

VOLTAGE=3.425V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.2 MM

PP3V42_G3H_SMC_CLK_F

50 OF 132 47 OF 103

46 47

6 7 8

25 26 27 28 30 34 37 40 42 47 48

49 52 53 55 59 63 64 69 70 71 72 73 74

81 84 85 86 88 99

101

46

6 7

17 21 23 43 45 46 47 48

49 50 51 54 65 66 74

6

46 47 54

46

45 46 54

6

43 46 48

6

43 46 48

6

46 48

46 47

46 47 65

46

6 7 8

25 26 27 28 30 34 37 40 42 47 48

49 52 53 55 59 63 64 69 70 71 72 73 74

81 84 85 86 88 99

101

6 7

17 21 23 43 45 46 47 48

49 50 51 54 65 66 74

46 47

46 47 51

20 25 46 47

46 47

46 47 65 46 47 65

20 25 46 47

46 47

46 47 50

46 47 51

6

46 47

46 47 50

46 65

46

18 31 43 46 73 74

18 46

34 46

46

18 46 74

46 47

6 7 8

25 26 27 28 30 34 37 40 42 47 48

49 52 53 55 59 63 64 69 70 71 72 73 74

81 84 85 86 88 99

101

6 7

17 21 23 43 45 46 47

48 49 50 51 54 65 66 74

46 50 51

6

46

6 7 8

25 26 27 28 30 34 37 40 42 47 48

49 52 53 55 59 63 64 69 70 71 72 73 74

81 84 85 86 88 99

101

46

6

46 47

6

46 47

6

46 47

6

46 47

6

46 47

6

46 47

6

46 47

6

46 47

6

46 47

6

46 47

6

46 47

6 7 31 33 43 44

45 51 55 68

73 83

103

6 7

17 21 23 43 45 46 47 48

49 50 51 54 65 66 74

6 7

17 21 23 43 45 46 47 48

49 50 51 54 65 66 74

6

46 48

6

46 48

6

46 48

6

46 65

46 47 65 66

46 47 46 47

46 47 65 66 46 47 65 66

46 47 50

46 47 51

46 47

46 47 50

46 47 51

6

46 47

OUT

IN

E0/NC0

SCL

SDA

E2 E1

WC*

VCC

VSS

IN

BI

NC

IN

IN OUT

OUT

OUT IN

OUT IN OUT

IN

BI BI

OUT

IN

BI

IN

OUT

BI

IN

OUT

IN

OUT

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

516S0573

SPI Bus Series Termination

EFI Debug ROM

LPC+SPI Connector

Write: 0xAC 0xAE

Read: 0xAD 0xAF

LPCPLUS

2

1

R5126

5% 1/16W MF-LF 402

47

PLACE_NEAR=J5100.12:5mm

58

21

402

1/16W

5%

MF-LF

47

R5122

PLACE_NEAR=R5127.2:5mm

PLACE_NEAR=U1800.AY1:5mm

21

R5112

15

402

MF-LF

5%

1/16W

17 94

2

1

R5127

402

MF-LF

1/16W

5%

LPCPLUS

47

PLACE_NEAR=J5100.9:5mm PLACE_NEAR=J5100.11:5mm

LPCPLUS

2

1

R5128

5% 1/16W MF-LF 402

0

CRITICAL

1

2

7

8

4

3

SO8N

M24M01-R

5

EFI_DEBUG

U5101

6

EFI_DEBUG

0

402

2

1

1/16W

5%

R5101

MF-LF

NO STUFF

0

402

2

1

R5104

1/16W

5% MF-LF

NO STUFF

0

402

2

1

R5102

1/16W

5% MF-LF

EFI_DEBUG

R5103

1

0

402

2

MF-LF

5% 1/16W

EFI_DEBUG

C5101

2

1

402

0.1UF

CERM

10V

20%

6

17 25 26 28 30 32 34 42 49 64

94

6

17 25 26 28 30 32 34 42 49 64

94

6

43 46 47

6

46

6

46

6

46 47

14

9

8

7

6

5

4

34

33

32

31

30

3

29

28

27

26

25

24

23

22

21

20

2

19

18

17

16

15

13

12

11

10

1

J5100

M-ST-SM

LPCPLUS

CRITICAL

55909-0374

6

20

6

43 46 47

6

46

6

46 47 66

6

46 47

6

46 47

6

27 88 94

6

48

6

17 46 88 94

6

18 46

6

48

6

17 46 88 94

6

17 46 88 94

6

46 47

6

18 46

6

17 46

6

48

6

48

6

20 58

6

17 46 88 94

6

17 46 88 94

6

27 94

58

R5110

21

15

5% 1/16W MF-LF

402

PLACE_NEAR=U1800.AV3:5mm

17 94

58

21

R5111

15

402

MF-LF

5%

1/16W

PLACE_NEAR=U1800.BA2:5mm

17 94

58

21

R5123

1/16W

5%

MF-LF

402

15

PLACE_NEAR=U6100.2:5mm

17 94

21

R5120

MF-LF

5%

1/16W

402

47

PLACE_NEAR=R5125.2:5mm

2

1

R5125

LPCPLUS

5% 1/16W MF-LF 402

47

PLACE_NEAR=J5100.14:5mm

21

R5121

402

5%

MF-LF

47

1/16W

PLACE_NEAR=R5126.2:5mm

SYNC_MASTER=T22_MLB

SYNC_DATE=03/30/2009

LPC+SPI Debug Connector

DEBUGROM_E1

SPI_MOSI_R

SPI_MLB_MISO

SPI_MLB_CS_L

SPI_MLB_CLK

SPI_MLB_MOSI

SPI_ALT_CS_L

SPI_ALT_CLK

SPI_ALT_MOSI

SPI_ALT_MISO

SPI_CS0_L

SPI_CS0_R_L

SPI_CLK_R

SMBUS_PCH_DATA

DEBUGROM_E2

SPI_CLK

SPI_MISO

SPI_MOSI

SMBUS_PCH_CLK

PP3V3_S0

PP3V42_G3H PP5V_S0

LPC_CLK33M_LPCPLUS LPC_AD<2> LPC_AD<3>

SPI_ALT_CS_L LPC_SERIRQ LPC_PWRDWN_L SMC_TDI SMC_TCK SMC_RESET_L SMC_NMI SMC_RX_L LPCPLUS_GPIO

LPC_AD<0> LPC_AD<1>

SPI_ALT_MOSI SPI_ALT_MISO

PM_CLKRUN_L

LPC_FRAME_L

SMC_TMS

SMC_TDO

LPCPLUS_RESET_L

SMC_MD1

SMC_TRST_L

SMC_TX_L

SPIROM_USE_MLB

SPI_ALT_CLK

51 OF 132 48 OF 103

6

48

6

48

6

48

6

48

94

6 7 8

25 26 27 28 30 34 37 40 42 47 49

52 53 55 59 63 64 69 70 71 72 73 74 81

84 85 86 88 99

101

6 7

17 21 23 43 45 46 47 49

50 51 54 65 66 74 6 7 8

23 42 53 55 69 70 71 73 87

102

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(Write: 0x98 Read: 0x99)

EMC1414: U5570

(Write: 0x98 Read: 0x99)

(Write: 0xA0 Read: 0xA1)

(Write: 0xA4 Read: 0xA5)

(Read: 0xAD 0xAF)

(Write: 0xAC 0xAE)

(Write: 0xD2 Read: 0xD3)

CK505 (Clock)

U5101

Margin Control

(Write: 0x30 Read: 0x31)

ExpressCard Slot

U2901

J2600 & J2650

U4900

The bus formerly known as "Battery B"

SMC

Battery Manager - (Write: 0x16 Read: 0x17)

U4900

XDP Connectors

(MASTER)

SMC "Battery A" SMBus Connections

SMC

(MASTER)

U2700

J3100

(Address via ARP)

Mikey

U6800

J3500

U1800

J2900

U4900

(MASTER)

(Write: 0x12 Read: 0x13)

Battery Charger

Battery

(See Table)

ISL6258 - U7000

J6955

U4900

(MASTER)

SMC

Battery

SO-DIMM "A"

CPU Temp

SMC

(MASTER)

U4900

J5800

SMC

(MASTER)

EFI Debug Serial

U2900

(MASTER)

GPU Temp (Ext)

GPU Temp (Int)

GT216: U8000

(Write: 0x9E Read: 0x9F)

ALS

(Write: 0x72 Read: 0x73)

U5930

UC210

NOTE: SMC RMT bus remains powered and may be active in S3 state

SMC "Management" SMBus Connections

(Write: 0x90 Read: 0x91)

J3401

SO-DIMM "B"

Battery LED Driver - (Write: 0x36 Read: 0x37) Battery Temp - (Write: 0x90 Read: 0x91)

(Write: 0x10 Read: 0x11)

(Write: 0x32 Read: 0x33)

Sensor ADC A

Sensor ADC B

(Write: 0x98 Read: 0x99)

(Write: 0x94 Read: 0x95)

U4510

(Write: 0x72 Read: 0x73)

SMC "B" SMBus Connections

VRef DACs

Ibex Peak-M

access PCH & CPU via PECI.

SMLink 1 is slave port to

PCH "SMLink 1" Connections

PCH "SMLink 0" Connections

(MASTER)

Ibex Peak-M

U1800

Ibex Peak-M

(Write: 0x90 Read: 0x91)

U1800

HDD Re-driver Control

SMC "0" SMBus Connections

Trackpad

SMC "A" SMBus Connections

PCH SMBus "0" Connections

EMC1414: U5550

402

5%

R5200

1

2

1/16W

1K

MF-LF

R5201

MF-LF

1

2

1K

5% 1/16W

402

4.7K

MF-LF 402

5% 1/16W

R5291

1

2

4.7K

MF-LF

402

5%

1/16W

R5290

1

2

4.7K

2

1

1/16W

5%

402

MF-LF

R5261

4.7K

2

1

R5260

1/16W

5%

402

MF-LF

5%

1/16W

R5280

2.0K

402

2

1

1/16W

R5281

5% MF-LF

2.0K

402

2

1

2

1

R5270

1K

MF-LF

402

5%

1/16W

R5271

402

MF-LF

1/16W

5%

1K

1

2

R5251

4.7K

5% 1/16W

402

MF-LF

1

2

4.7K

402

5%

MF-LF

1/16W

R5250

1

2

R5210

2

1

8.2K

1/16W

5%

402

MF-LF

2

1

R5211

8.2K

1/16W

5%

402

MF-LF

2

1

R5221

NO STUFF

8.2K

1/16W

5%

402

MF-LF

2

1

R5220

NO STUFF

8.2K

1/16W

5%

402

MF-LF

1 2

402

R5223

0

5% 1/16W MF-LF

1 2

402

R5222

MF-LF

1/16W

5%

0

SYNC_DATE=05/20/2009

SYNC_MASTER=K17_WFERRY

K17 SMBus Connections

SMBUS_SMC_0_S5_SCL SMBUS_SMC_0_S5_SDA

MAKE_BASE=TRUE

SMBUS_SMC_0_S5_SDA

SMBUS_PCH_CLK

SMBUS_SMC_A_S3_SDA

SMBUS_SMC_B_S0_SCL

MAKE_BASE=TRUE

SMBUS_SMC_B_S0_SDA

MAKE_BASE=TRUE

SML_PCH_1_DATA

MAKE_BASE=TRUE

SML_PCH_1_CLK

PP3V3_S0

MAKE_BASE=TRUE

SML_PCH_0_DATA

SML_PCH_0_CLK

MAKE_BASE=TRUE

SMBUS_PCH_CLK

MAKE_BASE=TRUE

SMBUS_PCH_DATA

SMBUS_PCH_CLK

SMBUS_PCH_CLK SMBUS_PCH_DATA

SMBUS_PCH_DATA

SMBUS_SMC_MGMT_SCL

SMBUS_SMC_MGMT_SDA

SMBUS_SMC_BSA_SDA

MAKE_BASE=TRUE

SMBUS_SMC_BSA_SDA SMBUS_SMC_BSA_SDA

SMBUS_SMC_MGMT_SCL

MAKE_BASE=TRUE

SMBUS_PCH_DATA

PP3V3_S5PP3V3_S3

SMBUS_SMC_MGMT_SDA

MAKE_BASE=TRUE

SMBUS_SMC_MGMT_SDA

SMBUS_SMC_MGMT_SCL

SMBUS_SMC_0_S5_SCL

MAKE_BASE=TRUE

SMBUS_SMC_A_S3_SCL

SMBUS_SMC_0_S5_SDA

SMBUS_SMC_0_S5_SCL

SMBUS_PCH_DATA

SMBUS_PCH_CLK SMBUS_PCH_CLK

SMBUS_PCH_DATA

SMBUS_SMC_A_S3_SCL

SMBUS_SMC_B_S0_SDA SMBUS_SMC_B_S0_SDA

SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SCL

SMBUS_SMC_0_S5_SCL

SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SCL

SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA

PP3V42_G3H

SMBUS_PCH_DATA

SMBUS_PCH_CLK

SMBUS_PCH_CLK SMBUS_PCH_DATA

SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA

PP3V3_S0

SMBUS_PCH_DATA

SMBUS_PCH_CLK

SMBUS_SMC_A_S3_SDA

MAKE_BASE=TRUE

SMBUS_SMC_BSA_SCL

SMBUS_SMC_0_S5_SDA

SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA

SMBUS_PCH_CLK

SMBUS_PCH_CLK SMBUS_PCH_DATA

PP3V3_S0

MAKE_BASE=TRUE

SMBUS_SMC_A_S3_SDA

MAKE_BASE=TRUE

SMBUS_SMC_A_S3_SCL

PP3V3_S0

52 OF 132 49 OF 103

46 49 52 82

46

49 52

82

6

17 25

26 28 30

32 34 42

48 49 64

94

6

33

46 49 55

97

46

49 52

97

46

49 52

97

17 94

6 7 8

25 26 27 28 30 34 37 40 42 47 48

49 52 53 55 59 63 64 69 70 71 72 73 74

81 84 85 86 88 99

101

6 7 8

25 26 27 28 30 34 37 40 42 47 48

49 52 53 55 59 63 64 69 70 71 72 73 74

81 84 85 86 88 99

101

17 94

6

17 25 26 28 30 32

34 42 48

49 64 94

6

17 25 26 28 30 32

34 42 48

49 64 94

6

17 25 26 28

30 32 34 42 48

49 64 94

6

17 25 26 28

30 32 34

42 48 49

64 94 6

17 25 26 28

30 32 34

42 48 49

64 94

6

17 25 26 28

30 32 34 42 48

49 64 94

6

17 25 26 28

30 32 34 42 48

49 64 94

46 49 57 97

102

46 49 57 97

102

6

46 49 65

66 97

6

46 49

65 66 97

46

49 57

97

102

6

17 25

26 28 30

32 34 42

48 49 64 94

6 7

31 35 50 51 58 72 73 74 84 86 99

101

6 7

17 20 31 32 33 34 35 36 50 51 54 55

56 72 74 88

102 103

46

49 57

97

102

46 49 57 97

102

46 49 57 97

102

46

49 52

82

6

33

46 49 55

97

46 49

52

82

46 49

52

82

6

17 25 26 28

30 32 34 42 48

49 64 94

6

17 25 26 28

30 32 34 42 48

49 64 94

6

17 25

26 28 30

32 34 42

48 49 64

94

6

17 25

26 28 30

32 34 42

48 49 64 94

6

33

46 49 55

97

46 49 52 97

46 49 52 97 46 49 52

97

46 49 52 82

6

46 49 65

66 97

6

46 49

65 66 97

6

46 49

65 66 97

6

46 49

65 66 97

6 7

17 21 23 43 45 46 47 48

50 51 54 65 66 74

6

17 25

26 28 30

32 34 42

48 49 64

94

6

17 25

26 28 30

32 34 42

48 49

64 94

6

17 25

26 28 30

32 34 42

48 49 64

94

6

17 25

26 28 30

32 34 42

48 49 64 94

6

33 46 49

55 97

6

33 46 49

55 97

6 7 8

25 26 27 28 30 34 37 40 42 47 48

49 52 53 55 59 63 64 69 70 71 72 73 74

81 84 85 86 88 99

101

6

17 25 26

28 30 32 34

42 48 49

64 94

6

17 25 26

28 30 32 34

42 48 49

64 94

6

33

46 49 55

97

46 49 52 82

46 49 57 97 102

6

17 25 26 28

30 32 34 42 48

49 64 94

6

17 25

26 28 30

32 34 42

48 49 64

94

6

17 25

26 28 30

32 34 42

48 49 64 94

6 7 8

25 26 27 28 30 34 37 40 42 47 48

49 52 53 55 59 63 64 69 70 71 72 73 74

81 84 85 86 88 99

101

6 7 8

25 26 27 28 30 34 37

40 42 47 48 49 52 53 55 59 63

64 69 70 71 72 73 74 81 84 85 86 88

99

101

OUT

N-CHN

S

D

G

P-CHN

G

D

S

OUT

IN

OUT

IN

VER 1

VCC

A

1

0

B1

GND

B0

SEL

IN

OUT

IN

OUT

IN

V+

REFIN+

IN-

OUT

GND

V+

REFIN+

IN-

OUT

GND

OUT

IN-

IN+ REF

V+

GND

IN

OUT

V-

V+

+

-

OUT

IN

V-

V+

+

-

OUT

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

CPU Voltage Sense / Filter

CPU VCore Load Side Current Sense / Filter

U5303 only senses current up to 6.6A

PCH VCore Current Sense

GAIN: 200X

BMON Current Sense - Entire circuit must be near SMC (U4900)

Gain: 3x

GPU Voltage Sense / Filter

current from battery to PBUS

INA214 has gain of 100V/V

GFX/AXG Current Sense

Monitors battery discharge

PBUS Voltage Sense & Filter

PCH VCore Current Sense Filter

LOAD SIDE:

Rthevenin = 4504 ohms

REGULATOR SIDE:

GFX Voltage Sense / Filter

DCIN Current Sense Filter

GAIN: 100X

GAIN: 150X

GAIN: 50X

CPU VCore High Side Current Sensor

Place short near U1000 center

Place short near U8000 center

Enables PBUS VSense divider when high.

1/16W MF-LF

5%

100K

402

R5315

1

2

46

PLACE_NEAR=U4900.M13:10mm

R5385

1%

1

2

402

MF-LF

1/16W

12.7K

0.22UF

PLACE_NEAR=U4900.M13:10mm

6.3V

402

X5R

20%

C5385

1

2

PLACE_NEAR=U4900.M13:10mm

MF-LF

1%

1/16W

402

6.98K

R5386

1

2

FDG6332CG

SC70-6

Q5315

6

2

1

SC70-6

FDG6332CG

Q5315

3

5

4

R5316

100K

1/16W

5%

MF-LF

402

1

2

PLACE_NEAR=U4900.K9:10mm

X5R

20%

6.3V 402

0.22UF

C5399

1

2

PLACEMENT_NOTE=Place near U1000

SM

XW5399

1 2

PLACE_NEAR=U4900.K9:10mm

402

1/16W

4.53K

MF-LF

1%

R5399

1 2

46 47

PLACE_NEAR=U4900.L7:10mm

0.22UF

402

X5R

6.3V

20%

C5335

1

2

PLACE_NEAR=U4900.L7:10mm

1%

1/16W

402

MF-LF

4.53K

R5335

1 2

6 7 8

40 50 66 67 68 70 71 83

87

6 7

69

402

CERM

10V

0.1UF

20%

C5388

1

2

402

CERM

20%

0.1uF

1

2

10V

BMON_ENG

C5369

46

PLACE_NEAR=U4900.N13:10mm

2

1

402

10%

0.022UF

CERM-X5R

16V

C5390

46 47

PLACE_NEAR=U4900.N13:10mm

1 2

402

45.3K

1/16W

1%

MF-LF

R5391

R5371

100K

1/16W 402

MF-LF

BMON_ENG

5%

1

2

5

U5313

NC7SB3157P6XG

BMON_ENG

SC70

43

1

2

6

0

402

5% 1/16W MF-LF

R5330

BMON_PROD

2 1

66

BMON_ENG

402

10V

0.1uF

20% CERM

C5318

1

2

66 99

102

DEBUG_ADC

PLACE_NEAR=UC210.23:10mm

402

6.3V

20%

X5R

0.22UF

C5370

1

2

PLACE_NEAR=UC210.23:10mm

DEBUG_ADC

4.53K

MF-LF

1/16W

1%

402

R5370

1 2

DEBUG_ADC

402

CERM

10V

20%

0.1UF

C5320

1

2

8

99

8

99

U5305

INA210

SC70

CRITICAL

DEBUG_ADC

2

5

4

6

1

3

INA213

6

SC70

U5388

5

4 1

3

2

OMIT

0.001

MF

3

1% 1W

R5388

1

2

1206

4

U5323

INA214

BMON_ENG

6

5

4 1

3

2

SC70

70 99

1/16W MF-LF

402

21

1M

SIGNAL_MODEL=EMPTY

1%

R5343

R5341

MF-LF

6.65K

1%

1/10W

603

21

R5342

1

603

1/10W

1%

6.65K

MF-LF

2

470PF

21

50V

CERM

402

10%

C5343

SIGNAL_MODEL=EMPTY

NO STUFF

2

1

CERM

10V

20%

402

0.1UF

C5344

PLACE_NEAR=U4900.L12:10mm

21

R5379

MF-LF

1/16W

1%

4.53K

402

PLACE_NEAR=U4900.L12:10mm

2

1

C5379

X5R

6.3V

20%

0.22UF

402

46 47

470PF

10%

1

CERM

2

402

50V

NO STUFF

C5340

SIGNAL_MODEL=EMPTY

1M

402

2

MF-LF

1/16W

1%

1

R5340

SIGNAL_MODEL=EMPTY

CRITICAL

4

5

3

1

2

SC70-5

U5340

OPA333DCKG4

CASE-D2E-SM

20%

68UF

POLY-TANT

16V

1

2

CRITICAL

C5303

CRITICAL

20%

68UF

POLY-TANT

16V

1

2

CASE-D2E-SM

C5304

20%

100UF

TANT

16V D-HF

C5300

CRITICAL

1

2

CRITICAL

20%

68UF

POLY-TANT

16V

1

2

CASE-D2E-SM

C5305

20%

68UF

POLY-TANT

16V

1

2

CASE-D2E-SM

C5306

CRITICAL

1

2

D-HF

C5301

CRITICAL

16V TANT

100UF

20%

46

POLY-TANT

1

2

C5302

CRITICAL

20%

68UF

16V CASE-D2E-SM

12 69 91

10%

SIGNAL_MODEL=EMPTY

1 2

402

CERM

50V

470PF

C5357

NO STUFF

402

1/16W

R5351

1 2

MF-LF

1%

10K

6.65K

MF-LF

1/16W

1%

402

1

R5350

2

20.0K

R5352

1/16W MF-LF

1%

402

1

SIGNAL_MODEL=EMPTY

CRITICAL

U5350

OPA333DCKG4

5

4

3

1

2

SC70-5

2

1

402

0.1UF

20% 10V CERM

C5354

21

1%

PLACE_NEAR=U4900.N10:5mm

R5353

4.53K

1/16W MF-LF

402

PLACE_NEAR=U4900.N10:5mm

2

1

402

6.3V

0.22UF

X5R

20%

C5353

46

PLACE_NEAR=U4900.N11:10mm

C5359

6.3V

0.22UF

X5R 402

20%

1

2

R5359

1/16W

402

1%

MF-LF

4.53K

1 2

PLACE_NEAR=U4900.N11:10mm

46

PLACE_NEAR=U4900.N12:10mm

20%

0.22UF

6.3V X5R 402

C5380

1

2

PLACE_NEAR=U4900.N12:10mm

1/16W

402

1%

MF-LF

4.53K

R5380

1 2

66

SM

XW5359

1 2

46

PLACE_NEAR=U4900.M11:10mm

MF-LF

402

1%

1/16W

4.53K

R5309

1 2

PLACE_NEAR=U4900.M11:10mm

20%

402

6.3V X5R

0.22UF

C5309

1

2

1

XW5309

SM

2

1

R5388

RES,1/2W,1%,0.010 OHM,SMD

102S0858

SYNC_DATE=06/17/2009

SYNC_MASTER=K17_REF

Current & Voltage Sensing

CPUISENS_N

PP3V3_S3

PPVCORE_S0_GFX

VOLTAGE=6V

MIN_LINE_WIDTH=0.20 mm MIN_NECK_WIDTH=0.20 mm

PPBUS_G3H_VSENSE

SMC_PBUS_VSENSE

SMC_BATT_ISENSE

PPVCORE_S0_CPU

PBUSVSENS_EN_DIV

SMC_GPU_VSENSE

GND_SMC_AVSS

PPBUS_CPU_IMVP_ISNS

CPUVSENSE_IN

BMON_AMUX_OUT

GPUVSENSE_IN

GND_SMC_AVSS

PP3V42_G3H

GND_SMC_AVSS

ISNS_CPU_P

SMC_GFX_ISENSE

GFXIMVP_CS_R_N

PP3V3_S5

CHGR_CSO_R_P

CHGR_CSO_R_N

PCHCORE_IOUT

CHGR_BMON

GFXVSENSE_IN

SMC_GFX_VSENSE

GND_SMC_AVSS

SMC_BMON_MUX_SEL

SMC_CPU_VSENSE

PPBUS_G3H

CHGR_AMON

SMC_DCIN_ISENSE

NC_ISNS_P1V05S0PCH_N

NC_ISNS_P1V05S0PCH_P

PPVCORE_GPU

SMC_CPU_HI_ISENSE

GND_SMC_AVSS

ADC2_CH1

GND_SMC_AVSS

PM_SLP_S3_L_R

ISNS_CPU_N

PP3V3_S3

GFXIMVP_ISNS_IOUT

GFX_ISNS_R_N

GFX_ISNS_R_P

GFXIMVP_CS_R_P

PPBUS_G3H

CPUVCORE_HISIDE_IOUT

CPUISENS_P

GND_SMC_AVSS

CPUIMVP_IMON

SMC_CPU_ISENSE

CPUVCORE_IOUT

PP3V42_G3H

BMON_INA_OUT

PBUSVSENS_EN_L

53 OF 132 50 OF 103

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

7

13 24 70

6 7

12 15 69

46 47 50 51

6 7

17 21 23 43 45 46 47 48

49 50 51 54 65 66 74

46 47 50 51

99

6 7

31 35 49 51

58 72 73 74 84 86

99

101

46 47 50 51

6 7 8

40 50 66 67 68 70 71 83

87

6 7

76 83

46 47 50 51

73 74

99

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

99

46 47 50 51

6 7

17 21 23 43 45 46 47 48

49 50 51 54 65 66 74

IN

OUT

IN

OUT

V+

REFIN+

IN-

OUT

GND

OUT

IN

OUT

IN

V+

REFIN+

IN-

OUT

GND

OUT

IN-

IN+ REF

V+

GND

IN

OUT

V-

V+

+

-

V+ V-

THRM

V+ V-

THRM

IN

OUT

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

1.5V S3 Current Sense

PP5V_S3 Current Sense Filter

dual package opamp U5410

PP3V3_S5 Current Sense

CPUVTT 1.05V Current Sense

Gain: 294x

GPU 1.05V Current Sense

PP3V3_S5 Current Sense Filter

Gain: 100x

GPU VCore Current Sense Filter

GPU VCore Current Sense

Gain: 50x

Gain: 1.4x

Gain: 324x

Gain: 50x

PP5V_S3 Current Sense

GPU VCore Current Sense and GPU 1.8V Current Sense share

1.5V S3 Current Sense Filter

GPU 1.8V Current Sense

GPU 1.8V Current Sense Filter

4.53K

2

MF-LF

1/16W

1%

402

1

R5411

PLACE_NEAR=U4900.L10:10mm

7

87

6 7

75 77 80 82

102

PLACE_NEAR=UC210.24:5mm

402

MF-LF

1/16W

1

R5402

4.53K

2

1%

DEBUG_ADC

402

10V

0.1UF

2

CERM

20%

1

C5401

DEBUG_ADC

C5402

PLACE_NEAR=UC210.24:5mm

6.3V

0.22UF

2

X5R

1

20%

402

DEBUG_ADC

7

67

6 7

31 35 49 50 51 58 72 73 74 84

86 99

101

102

PLACE_NEAR=UC210.1:5mm

0.22UF

1

X5R

20%

C5404

402

2

DEBUG_ADC

6.3V

R5404

4.53K 1%

PLACE_NEAR=UC210.1:5mm

1/16W

21

402

MF-LF

DEBUG_ADC

C5403

0.1UF

2

1

20% 10V CERM 402

DEBUG_ADC

SC70

U5421

6

CRITICAL

2

5

4

3

1

INA213

DEBUG_ADC

6 7

31 33 43 44 45 47 55 68 73

83

103

7

67

MF

1

R5401

0612

0.002

CRITICAL

1% 1W

3

42

CRITICAL

1%

2

1 3

4

R5403

1/4W

MF

1206

0.002

46 47

PLACE_NEAR=U4900.M9:10mm

2

1

402

10%

0.022UF

CERM-X5R

16V

C5499

PLACE_NEAR=U4900.M9:10mm

1 2

402

0

1/16W MF-LF

5%

R5499

71

CRITICAL

R5419

2

1 3

4

1206

1/4W

MF-HF

1%

0.005

INA213

5

4 1

2

SC70

3

6

U5423

DEBUG_ADC

CRITICAL

102

402

MF-LF

1%

4.53K

R5430

1/16W

21

PLACE_NEAR=UC210.22:5mm

DEBUG_ADC

C5430

X5R 402

6.3V

20%

1

2

0.22UF

PLACE_NEAR=UC210.22:5mm

DEBUG_ADC

MF-LF

1 2

402

1%

1/16W

1M

R5417

SIGNAL_MODEL=EMPTY

C5440

2

1

0.1UF

20%

CERM 402

10V

C5441

21

470PF

402

CERM

50V

10%

NO STUFF

SIGNAL_MODEL=EMPTY

21

1M

1%

402

1/16W MF-LF

R5441

SIGNAL_MODEL=EMPTY

R5442

SIGNAL_MODEL=EMPTY

2

1

402

MF-LF

1%

1M

1/16W

C5442

NO STUFF

470PF

50V

CERM

SIGNAL_MODEL=EMPTY

2

1

402

10%

1 2

402

R5415

1% 1/16W MF-LF

3.09K

402

CERM

10V

20%

2

1

C5423

0.1UF

DEBUG_ADC

CRITICAL

INA214

U5405

6

5

4 1

3

2

SC70

DEBUG_ADC

2

1 3

4

1206

0.001

R5413

MF

1W

1%

68 99

1 2

402

3.40K

MF-LF

1/16W

1%

R5443

1 2

402

3.40K

1% 1/16W MF-LF

R5444

68 99

PLACE_NEAR=U4900.L8:10mm

4.53K

1 2

1%

MF-LF

402

R5440

1/16W

46 47

PLACE_NEAR=U4900.L8:10mm

C5490

0.22UF

20%

X5R 402

2

1

6.3V

OPA333DCKG4

U5440

CRITICAL

SC70-5

4

5

3

1

2

CRITICAL

2

9

4

8

1

3

DFN

U5410

OPA2333

6

9

4

8

7

5

DFN

CRITICAL

U5410

OPA2333

R5409

21

1/16W

1%

2.87K

MF-LF

402

R5410

10K

21

402

1% 1/16W MF-LF

1

1%

MF-LF

1/16W

4.02K

402

2

R5412

SIGNAL_MODEL=EMPTY

PLACE_NEAR=U4900.L8:10mm

C5411

6.3V

1

2

402

X5R

20%

0.22UF

NO STUFF

2

402

1

CERM

50V

10%

470PF

C5407

SIGNAL_MODEL=EMPTY

83

46 47

PLACE_NEAR=U4900.L8:10mm

4.53K

1 2

MF-LF

402

1/16W

R5418

1%

NO STUFF

470PF

C5412

402

50V

10%

CERM

1 2

SIGNAL_MODEL=EMPTY

1

402

CERM

C5410

20%

0.1UF

10V

2

SIGNAL_MODEL=EMPTY

MF-LF

1% 1/16W

1

2

402

1M

R5416

R5414

1

1/16W MF-LF

3.09K

1%

402

2

NO STUFF

C5409

50V 402

2

CERM

1

10%

470PF

SIGNAL_MODEL=EMPTY

6 7

87

6 7 8

76 77 78 79

46

PLACE_NEAR=U4900.L10:10mm

C5408

1

402

6.3V

20%

2

0.22UF

X5R

Current Sensing

SYNC_MASTER=K17_CHENGD

SYNC_DATE=06/04/2009

ISNS_1V5_S3_R_N

SMC_1V5_S3_ISENSE

GND_SMC_AVSS

ISNS_1V5_S3_N

ISNS_1V5_S3_P

5V_S3_IOUT

PP5V_S3

PP1V8_S0GPU_ISNS_R

ISNS_P1V8GPU_P

PP1V8_S0GPU_ISNS

PP3V3_S5

ISNS_PP3V3_S5_P

PP5V_S3_ISNS_R

SMC_CPUVTT_ISENSE

GND_SMC_AVSS

SMC_GPU_ISENSE

GND_SMC_AVSS

1V05_GPU_IOUT

ISNS_PP1V05_P

GFXIMVP6_IMON

ADC2_CH0

ISNS_PP5V_S3_N

CPUVTTS0_IMON

ISNS_PP3V3_S5_N

ADC2_CH2

3V3_S5_IOUT

PP3V3_S5_ISNS_R

ISNS_PP5V_S3_P

ISNS_PP1V05_N

PP1V05_S0GPU_ISNS_R

PP3V3_S5

ISNS_P1V8GPU_N

PP3V3_S5

PP1V05_S0GPU

ADC2_CH3

PP3V42_G3H

SMC_GPU_1V8_ISENSE

GND_SMC_AVSS

GPUVCORE_IOUT

GPUISENS_N

GPUISENS_P

ISNS_P1V8GPU_R_P

1V8_S0GPU_IOUT

PP3V3_S5

ISNS_P1V8GPU_R_N

PP3V3_S3

ISNS_1V5_S3_IOUT

ISNS_1V5_S3_R_P

54 OF 132 51 OF 103

99

46 47 50 51

6 7

31 35 49 50 51 58 72 73 74 84 86 99

101

99

46 47 50 51

99

6 7

31 35 49 50 51 58 72 73 74 84 86 99

101

99

6 7

17 21 23 43 45 46 47 48

49 50 54 65 66 74

46 47 50 51

99

6 7

31 35 49 50 51 58 72 73 74 84 86 99

101

99

6 7

17 20 31 32 33 34 35 36 49 50 54 55

56 72 74 88

102 103

99

BI

ALERT*

THERM*/ADDR

DP1

SMCLK

SMDATA

VDD

DN1

DP2/DN3

DN2/DP3

GND

BI

ALERT*

THERM*/ADDR

DP1

SMCLK

SMDATA

VDD

DN1

DP2/DN3

DN2/DP3

GND

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Detect Battery Charger Proximity Temperature

Place Q5502 on bottom side

Placement note:

close to battery charger circuit

Detect CPU Die Temperature

Placement note:

GPU Proximity/GPU Die/Left Heat Pipe/Right Fin Stack

Place U5570 under CPU

Placement note:

Detect Right Fin Stack Temperature

close to the right fin stack

Place Q5501 on bottom side

Detect Left Heat Pipe Temperature

Place on top side under left heat pipe near GPU

Placement note:

Place Q5504 under PCH

Place U5550 near GPU

Placement note:

Read Address: 0x99

Write Address: 0x98

Detect GPU Die Temperature

Compensation for External Diode 1 only

Note: EMC1414 can perform Beta

Read Address: 0x99

Write Address: 0x98

Placement note:

Detect PCH Proximity Temperature

CPU Proximity/CPU Die/PCH Proximity/Battery Charger Proximity

46 49 97

10K

5% 1/16W MF-LF 402

R5572

1

2

402

5%

MF-LF

10K

1/16W

R5571

1

2

0.1uF

20% 10V CERM 402

C5570

1

2

1

7

9

10

6

4

2

5

3 8

U5570

CRITICAL

MSOP

EMC1414-A

1/16W MF-LF

402

5%

47

R5570

1 2

CERM

402

50V

10%

0.0022uF

PLACE_NEAR=U5570.3:5mm

PLACE_NEAR=U5570.2:5mm

SIGNAL_MODEL=EMPTY

C5571

1

2

PLACE_NEAR=U5570.5:5mm

0.0022uF

402

10% 50V

CERM

PLACE_NEAR=U5570.4:5mm

SIGNAL_MODEL=EMPTY

C5590

1

2

9

99

9

99

SOT732-3

BC846BMXXH

Q5504

1

3

2

3

1

Q5503

SOT732-3

BC846BMXXH

80 81 99

2

1

10% 50V

402

CERM

SIGNAL_MODEL=EMPTY

PLACE_NEAR=U5550.5:5mm

PLACE_NEAR=U5550.4:5mm

0.0022uF

C5552

21

R5550

47

1/16W

5%

MF-LF

402

2

1

C5551

0.0022uF

50V 402

CERM

10%

SIGNAL_MODEL=EMPTY

PLACE_NEAR=U5550.2:5mm

PLACE_NEAR=U5550.3:5mm

2

1

C5550

CERM

10V

20%

0.1uF

402

46 49 82

2

1

R5552

MF-LF

10K

1/16W 402

5%

2

1

R5551

5%

402

10K

1/16W MF-LF

2

3

1

SOT732-3

BC846BMXXH

Q5501

U5550

EMC1414-A

CRITICAL

MSOP

6

5

4

3

1

9

10

2 7

8

2

3

1

SOT732-3

BC846BMXXH

Q5502

SYNC_MASTER=K17_CHENGD

SYNC_DATE=07/08/2009

Thermal Sensors

PP3V3_S0

CPUTHMSNS_THM_L CPUTHMSNS_ALERT_L

SMBUS_SMC_B_S0_SDA

CPU_THERMD_N

CPU_THERMD_P

PP3V3_S0

GPUTHMSNS_D_N

GPUTHMSNS_D_P

GPU_TDIODE_N

VOLTAGE=3.3V

PP3V3_S0_GPUTHMSNS_R

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

SMBUS_SMC_0_S5_SDA SMBUS_SMC_0_S5_SCL

GPU_TDIODE_P

GPUTHMSNS_THM_L GPUTHMSNS_ALERT_L

SMBUS_SMC_B_S0_SCL

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm

PP3V3_S0_CPUTHMSNS_R

CPUTHMSNS_D2_N

CPUTHMSNS_D2_P

55 OF 132 52 OF 103

6 7 8

25 26 27 28 30 34 37 40 42 47 48

49 52 53 55 59 63 64 69 70 71 72 73 74

81 84 85 86 88 99

101

6 7 8

25 26 27 28 30 34 37 40 42 47 48

49 52 53 55 59 63 64 69 70 71 72 73 74

81 84 85 86 88 99

101

99

G

S D

G

S D

IN

OUT OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Right Fan

Left Fan

518S0521518S0521

2

1

R5650

1/16W

47K

402

5%

MF-LF

21

R5655

1/16W

5%

MF-LF

402

47K

2

1

R5660

402

MF-LF

47K

5%

1/16W

21

R5665

402

47K

MF-LF

1/16W

5%

2

1

R5651

402

MF-LF

5%

1/16W

100K

4

5

3

Q5660

2N7002DW-X-G

SOT-363

2

1

R5661

100K

5%

MF-LF

402

1/16W

1

2

6

Q5660

2N7002DW-X-G

SOT-363

4

3

2

1

6

5

J5650

M-RT-SM

CRITICAL

78171-0004

4

3

2

1

6

5

J5660

78171-0004

CRITICAL

M-RT-SM

46

46 46

46

Fan Connectors

SYNC_MASTER=K20A_MLB SYNC_DATE=03/26/2009

FAN_LT_PWM

SMC_FAN_1_CTL

SMC_FAN_1_TACH

SMC_FAN_0_CTL

FAN_RT_PWM

PP5V_S0

FAN_RT_TACH

PP3V3_S0

FAN_LT_TACH

PP5V_S0 PP3V3_S0

SMC_FAN_0_TACH

56 OF 132 53 OF 103

6 6

6 7 8

23 42 48 53 55 69 70 71 73 87

102

6

6 7 8

25 26 27 28 30 34 37 40 42 47 48

49 52 53 55 59 63 64 69 70 71 72 73 74

81 84 85 86 88 99

101

6

6 7 8

23 42 48 53 55 69 70 71 73 87

102

6 7 8

25 26 27 28 30 34 37 40 42 47 48

49 52 53 55 59 63 64 69 70 71 72 73 74

81 84 85 86 88 99

101

D

G S

P2_4

P2_6

VDD

P0_4

P0_2

P2_0

P2_2

P0_0

P2_3 P2_1 P4_7 P4_5 P4_3 P4_1 P3_7 P3_5 P3_3 P3_1 P5_7 P5_5 P5_3 P5_1

P1_1

P1_3

P1_5

P1_7

P7_7

VSSD+D-

VDD

P7_0

P1_0

P1_2

P1_4

P1_6

P5_0

P5_2

P5_4

P5_6

P3_0

P3_2

P3_4

P4_0

P4_2

P4_4

P4_6

P3_6

P2_5

P2_7

P0_3

VSS

P0_5

P0_7

P0_6

PAD

THRML

(SYM-VER2)

P0_1

Y

C

B

A

IN

Y

B

A

Y

B

A

Y

B

A

NC

OUT

BI

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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REVISION

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SIZE

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PAGE TITLE

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

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8 7 5 4 2 1

PLACE C5704, C5705 & C5706

PIN NAME

2.55 KOHM

KEYBOARD CONNECTOR

SMC_MANUAL_RESET LOGIC

TPAD BUTTONS DISABLE

R_SNS

0.204 V

294E-6 W

0.0188 V

SPI HOST TO Z2

ISSP SCLK/I2C SCL

ISSP CLOCK

18V BOOSTER

IC

V+

VDD

VIN

14MA (MAX)

8MA (TYP)

60MA MAX

80UA

10UA

10 OHM

0.2 OHM

1.5 OHM

V_SNS POWER

0.021 V

0.012 V

0.6 V

0.0255 V

0.255E-6 W

16.32E-6 W 36E-3 W

0.72E-3 W 96E-6 W

APN 518S0637

LID CLOSE => SMC_LID_LC < 0.50V

LID OPEN => SMC_LID_LC ~ 3.42V

WHEN THE LID IS CLOSED

THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB

THE TPAD BUTTONS WILL BE DISABLE

TMP102

PLACE THESE COMPONENTS CLOSE TO J5800

USB INTERFACES TO MLB

APN 311S0406

APN 337S2983

KEYBOARD SCANNER

VOUT

TRACKPAD PICK BUTTONS

TO MLB CONNECTOR

CLOSE TO U5701

VDD PIN 22

CLOSE TO U5701

VDD PIN 49

PSOC USB CONTROLLER

ISOLATION CIRCUIT

TEST POINTS ARE FOR ON BOARD PROGRAMMING

PSOC PROGRAMMING CONNECTOR

ISSP DATA

75.2E-6 W

CURRENT

4.7 OHM

4MA (MAX)

APN 518S0430

ISSP SDATA/I2C SDA

PSOC

3V3 LDO

U5701 CHIP DECOUPLING PLACE C5701, C5702 & C5703

2

1

3

Q5701

SOD-VESM-HF

SSM3K15FV

2

1

C5758

402

10% 16V

0.1UF

X7R-CERM

2

1

R5771

33K

402

1/16W MF-LF

5%

2

1

R5770

33K

402

1/16W

5%

MF-LF

2

1

R5769

33K

1/16W

5%

402

MF-LF

2

1

C5706

603

X5R

6.3V

20%

4.7UF

2

1

C5705

10% 16V X7R-CERM

0.1UF

402

2

1

C5704

402

CERM

50V

100PF

5%

2

1

C5703

16V X7R-CERM

10%

0.1UF

402

2

1

C5702

402

CERM

50V

5%

100PF

2

1

C5701

6.3V 603

X5R

4.7UF

20%

21

R5702

24

MF-LF

1/16W

5%

402

50194922

57

23

24

11 32 12 31 13 30 14 29

3

40

4

39

5

38

6

37

7

36

8

35

9

34

10 33

554456

43

1

42

2

41

15281627172618

25

51485247534654

45

21

20

U5701

MLF

CY8C24794

OMIT

CRITICAL

21

R5701

402

MF-LF

5%

24

1/16W

5

4

6

3

1

2

U5703

SC70

SN74LVC1G10

CRITICAL

21

R5704

402

1/16W

1.5

5%

MF-LF

45 46 47

2

1

C5710

PLACE_NEAR=R5710.1:2mm

CERM

20%

0.1UF

10V 402

21

R5710

PLACE_NEAR=J5713.5:2mm

402

MF-LF

1/16W

5%

1K

21

R5714

470

1/16W

402

MF-LF

1%

21

R5715

1/16W MF-LF

10K

1%

402

4

3

2

1

6

5

J5702

F-RT-SM1

FH19C-4S-0.5SH25

CRITICAL

TPAD_DEBUG

9 8 7 6 5 4

30

3

29 28 27 26 25 24 23 22 21 20

2

19 18 17 16 15 14 13 12 11 10

1

32

31

J5713

CRITICAL

FF14-30A-R11B-B-3H

F-RT-SM

4

5

3

1

2

U5726

TC7SZ08AFEAPE

SOT665

CRITICAL

4

5

3

1

2

U5727

SOT665

TC7SZ08AFEAPE

CRITICAL

4

5

3

1

2

U5725

CRITICAL

TC7SZ08AFEAPE

SOT665

2 1

C5725

402

10V

20%

CERM

0.1UF

2 1

C5726

20% 10V

CERM

402

0.1UF

2 1

C5727

0.1UF

10V

20%

402

CERM

6

46 47

36 93

SYNC_DATE=06/09/2009

SYNC_MASTER=K17_WFERRY

WELLSPRING 1

SMC_ONOFF_L

WS_KBD16N

WS_KBD_ONOFF_L

WS_LEFT_SHIFT_KBD

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM

VOLTAGE=3.3V

PP3V3_S3_PSOC

PP3V3_S3

WS_LEFT_OPTION_KEY

PP3V3_S3

PP3V42_G3H

PP3V3_S3

PP3V42_G3H

WS_CONTROL_KBD

WS_LEFT_OPTION_KBD

WS_LEFT_SHIFT_KBD

WS_CONTROL_KEY

WS_KBD1

WS_KBD15_CAP WS_KBD16_NUM

WS_LEFT_SHIFT_KEY

WS_KBD15_C

WS_KBD12

WS_KBD2 WS_KBD3 WS_KBD4 WS_KBD5 WS_KBD6

WS_KBD18

WS_KBD17

WS_KBD14

WS_KBD13

WS_KBD11

WS_KBD10

WS_KBD9

WS_KBD21

WS_KBD20

WS_KBD19

WS_KBD22 WS_KBD23

PP3V42_G3H

WS_LEFT_OPTION_KBD WS_CONTROL_KBD

WS_KBD7 WS_KBD8

PP3V42_G3H

PP3V3_S3

USB_TPAD_P

USB_TPAD_N

PP3V3_S3

ISSP_SDATA_P1_0

ISSP_SCLK_P1_1

USB_TPAD_R_N

WS_LEFT_OPTION_KEY

WS_LEFT_SHIFT_KEY

Z2_HOST_INTN

BUTTON_DISABLE

WS_KBD18

WS_KBD21

WS_KBD20

Z2_MOSI Z2_SCLK

Z2_CS_L

Z2_MISO

PSOC_SCLK

PSOC_MOSI

PSOC_F_CS_L

Z2_RESET

Z2_DEBUG3

PSOC_MISO

Z2_BOOT_CFG1

TP_P4_5

Z2_KEY_ACT_L

WS_CONTROL_KEY

TP_PSOC_SCL

TP_PSOC_SDA

NC_PSOC_P1_3

ISSP_SCLK_P1_1

USB_TPAD_R_P

PP3V3_S3_PSOC

TP_P7_7

Z2_CLKIN

ISSP_SDATA_P1_0

WS_KBD5 WS_KBD6

WS_KBD4

WS_KBD3

WS_KBD2

WS_KBD1

WS_KBD7

WS_KBD8

WS_KBD9

WS_KBD10

WS_KBD11

WS_KBD13 WS_KBD12

WS_KBD15_C WS_KBD14

WS_KBD16N

WS_KBD17

PP3V3_S3_PSOC

PICKB_L

WS_KBD23

WS_KBD22

WS_KBD19

BUTTON_DISABLE

SMC_LID

SMC_TPAD_RST_L

PP3V42_G3H

WS_LEFT_SHIFT_KBD WS_LEFT_OPTION_KBD WS_CONTROL_KBD

57 OF 132 54 OF 103

54

6

54

6 7

17 20 31 32 33 34 35 36 49

50 51 54 55 56 72 74 88

102

103

54

6 7

17 20 31 32 33 34 35 36 49 50

51 54 55 56 72 74 88

102

103

6 7

17 21 23 43 45 46 47 48 49

50 51 54 65 66 74

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

6 7

17 21 23 43 45 46 47 48

49 50 51 54 65 66 74

6

54

6

54

6

54

6

54

6

54

6

54

6

54

6

54

6

54

6

54

6

54

6

54

6

54

6

54

6

54

6

54

6

54

6

54

6

54

6

54

6

54

6

54

6

54

6 7

17 21 23 43 45 46 47

48 49 50 51 54 65 66 74

6

54

6

54

6

54

6

54

6 7

17 21 23 43 45 46 47 48 49

50 51 54 65 66 74

6 7

17 20 31 32 33 34 35 36 49

50 51 54 55 56 72 74 88

102 103

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

6 7

17 20 31 32 33 34 35 36

49 50 51 54 55 56 72 74 88

102

103

6

54

6

54

55

54

6

54

6

54 6 54

55

6

55

6

55

6

55

6

55

6

55

6

55

6

55

6

55

6

55

6

55

54

6

54

6

55

6

54

6

54

6

54

6

54

6

54

6

54

6

54

6

54

6

54

6

54

6

54

6

54

6

54

6

54

6

54

6

54

6

55

6

54 6 54 6 54

54

47

6 7

17 21 23 43 45 46 47 48

49 50 51 54 65 66 74

6

54

6

54

6

54

IN

THRML

CAP

SW

LED

VIN

CTRL

PAD

GND

CTRL

PGND

THRML

L

VIN

DO

FB

SW

PAD

GND

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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PAGE TITLE

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A

D

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

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B

8 7 5 4 2 1

- R5812,R5813,C5818 MODIFIED

- STARTUP TIME LESS THAN 2MS

- 100-300 KHZ CLEAN SPECTRUM

- RIPPLE TO MEET ERS

- DROOP LINE REGULATION

- POWER CONSUMPTION

BOOSTER DESIGN CONSIDERATION:

J5815 pin 1 is grounded

Keyboard LED Driver

BOOSTER +18.5VDC FOR SENSORS

HIGH= keyboard backlight not present

APN 518S0691

APN 353S1401

To detect Keyboard backlight, SMC will

LOW = keyboard backlight present

on keyboard backlight flex

IPD FLEX CONNECTOR

APN 516S0689

BOM OPTION: KBDLED_YES

tristate SMC_SYS_KBDLED:

R5853 ALWAYS PRESENT

APN 152S0504

KBD BACKLIGHT CONNECTOR

APN 371S0313

HF APN 152s0898

M-ST-SM

55560-0228

CRITICAL

J5800

1

10

1112 1314 1516 1718 19

2

20

2122

34 56 78 9

46

1/16W MF-LF

5%

4.7K

402

R5854

1

2

MF-LF

1/16W

5%

470K

402

R5853

1

2

1

7

3

5

2

6

4

U5850

CRITICAL

LT3491

DFN

5%

MF-LF

402

1/16W

10K

NO STUFF

R5852

1

2

1/16W

MF-LF

402

10

1%

R5855

1

2

1UF

10% 35V

603

X5R

C5855

1

2

CRITICAL

F-RT-SM

FF18-4A-R11AD-B-3H

J5815

1 2 3 4

PLACE_NEAR=J5800.2:5mm

0

1/10W

5%

MF-LF

603

R5801

1 2

1/16W MF-LF

0

5%

402

R5806

1 2

402

1%

1M

MF-LF

1/16W

R5812

1

2

5% 50V CERM

39PF

402

C5818

1

2

SOD-323

B0520WSXG

D5802

1 2

1UF

X5R

25V

10%

603-1

C5819

1

2

402

71.5K

1%

MF-LF

1/16W

R5813

1

2

1/16W MF-LF

1%

100K

402

R5811

1

2

3.3UH-870MA

VLF3010AT-SM-HF

CRITICAL

L5801

1 2

5%

0

1/16W

402

MF-LF

R5805

1 2

TPS61045

CRITICAL

QFN

U5805

53

4

6

1

7

8

9

2

2.2UF

10% 16V X5R 603

C5817

1

2

1

2

X7R-CERM 402

10% 16V

0.1UF

C5816

10UH-0.58A-0.35OHM

1098AS-SM

CRITICAL

L5850

1 2

X5R

16V

1UF

10% 603

C5850

1

2

10V

402

CERM

20%

0.1UF

C5800

1

2

SYNC_DATE=06/09/2009

SYNC_MASTER=K17_WFERRY

WELLSPRING 2

MIN_NECK_WIDTH=0.20MM

TPAD_GND_F

VOLTAGE=0V MIN_LINE_WIDTH=0.50MM

SMC_KDBLED_PRESENT_L

Z2_BOOST_EN

BOOST_FB

VOLTAGE=5V

MIN_LINE_WIDTH=0.50MM

PP5V_S3_BOOSTER

MIN_NECK_WIDTH=0.20MM

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM

PP18V5_S3

SMC_KDBLED_PRESENT_L

INPUT_SW

0.50MM

0.20MM

PP3V3_S0

PP5V_S3

MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM

BOOST_SW

SWITCH_NODE=TRUE

SMC_SYS_KBDLED

PP5V_S0

KBDLED_ANODE

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.25 MM

KBDLED_SW

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.3 MM SWITCH_NODE=TRUE

KBDLED_CAP

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.25 MM

Z2_RESET

PSOC_F_CS_L

PICKB_L

PSOC_MISO

PSOC_MOSI

PSOC_SCLK

SMBUS_SMC_A_S3_SDA

SMBUS_SMC_A_S3_SCL

PP18V5_S3

Z2_KEY_ACT_L

TPAD_GND_F

Z2_CS_L

Z2_MOSI Z2_SCLK Z2_HOST_INTN

Z2_DEBUG3 Z2_MISO

Z2_BOOST_EN Z2_BOOT_CFG1

Z2_CLKIN

PP3V3_S3

PP18V5_S3_SW

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM

58 OF 132 55 OF 103

6

55

6

55

6

55

6

55

6

55

6 7 8

25 26 27 28 30 34 37 40 42 47 48

49 52 53 59 63 64 69 70 71 72 73 74 81

84 85 86 88 99

101

6 7

31 33 43 44 45 47 51 68 73 83

103

6 7 8

23 42 48 53 69 70 71 73 87

102

6

54

6

54

6

54

6

54

6

54

6

54

6

33 46 49 97

6

55

6

54

6

55

6

54

6

54

6

54

6

55

6

54

6

54

6 7

17 20 31 32 33 34 35 36 49 50 51 54

56 72 74 88

102 103

OUT

FS PD ST

RES RES

GND

NC

NC NC

NC

NC NC

VOUTX

VOUTY

VOUTZ

VDD

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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REVISION

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Front of system

+X

+Y

+Z (up)

placed on board top-side:

Desired orientation when

in correct orientation

Circle indicates pin 1 location when placed

Analog SMS

NC NC NC

R5921 PULLS UP SMS_PWRDN TO TURN OFF SMS WHEN PIN IS NOT BEING DRIVEN BY SMC

NC NC

46

0.01UF

402

16V

10% CERM

C5925

1

2

0.01UF

10% CERM

16V 402

C5924

1

2

16V

10% CERM

0.01UF

402

C5923

1

2

10K

5% 1/16W MF-LF

402

R5921

1

2

CRITICAL

LGA

AP344ALH

U5920

1

7

3 6 9

11 13 16

5

15

4

2

14

12 10 8

5% MF-LF

402

10K

1/16W

R5922

1

2

46 56

603

20%

10UF

4V X5R

C5926

1

2

402

X5R

16V

10%

0.1UF

C5922

1

2

46

SYNC_MASTER=K20A_MLB

Sudden Motion Sensor (SMS)

SYNC_DATE=03/26/2009

SMS_PWRDN

SMS_Z_AXIS

SMS_Y_AXIS

SMS_X_AXIS

SMS_SELFTEST

MAKE_BASE=TRUE

SMS_PWRDN

PP3V3_S3

59 OF 132 56 OF 103

46 56

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 72 74 88

102 103

IN

BI

V+

REFIN+

IN-

OUT

GND

OUT

IN

V-

V+

+

-

V-

V+

+

-

V+ V-

THRM

V+ V-

THRM

IN

ININ

COM

GND

THRM

DVDDAVDD

AD0 AD1

SDA SCL

CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7

VREF

REFCOMP

PAD

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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REVISION

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PAGE TITLE

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

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345678

D

B

8 7 5 4 2 1

DIVIDER: ~ 2/5

DIVIDER: ~ 2/3

GAIN: 845X

LSB: 0.001V

DIVIDER: ~ 1/20

GAIN: 1239X

GAIN: 561X

GAIN: 200X

GAIN: 549X

U6030 is dual package for CPU MEM VDD and AIRPORT sensors

ADC RANGE: 0V TO 4.096V

I2C ADDRESS: 0X10 / 0X11

89 99

MF-LF

1/16W

1%

402

DEBUG_ADC

21

R6030

243

46 49 97 102

1/16W

5%

MF-LF

402

10

R6004

DEBUG_ADC

10

402

MF-LF

5%

1/16W

R6003

DEBUG_ADC

4

5

INA210

DEBUG_ADC

U6050

SC70

6

1

3

2

C6041

DEBUG_ADC

0.1UF

CERM 402

10V

20%

57

7

13 16

31

7

73

R6045

3

CRITICAL

214

1206

1%

0.001

MF

1W

DEBUG_ADC

R6041

1% 1/16W MF-LF

1.82K

402

21

DEBUG_ADC

R6040

1% 1/16W MF-LF

1.82K

402

21

2

1

3

5

4

SC70-5

DEBUG_ADC

U6040

OPA333DCKG4

DEBUG_ADC

OPA333DCKG4

U6041

SC70-5

2

1

3

5

4

2

9

4

8

1

3

DEBUG_ADC

U6030

OPA2333

DFN

OPA2333

U6030

DFN

5

7

8

4

9

6

NO STUFF

402

CERM

50V

470PF

10%

C6042

1

2

SIGNAL_MODEL=EMPTY

DEBUG_ADC

402

MF-LF

1/16W

1%

1M

1

2

R6042

SIGNAL_MODEL=EMPTY

50V

NO STUFF

2

C6043

CERM

402

1

SIGNAL_MODEL=EMPTY

10%

470PF

1/16W MF-LF

402

1M

1%

DEBUG_ADC

R6043

1 2

SIGNAL_MODEL=EMPTY

PLACE_NEAR=U6000.4:5mm

21

226K

1/16W

DEBUG_ADC

402

1%

R6074

MF-LF

DEBUG_ADC

1

2

C6050

402

10V

20%

0.1UF

CERM

89 99

SIGNAL_MODEL=EMPTY

2

1

C6032

50V

10%

CERM

402

470PF

NO STUFF

SIGNAL_MODEL=EMPTY

DEBUG_ADC

R6032

1

2

MF-LF 402

1% 1/16W

301K

SIGNAL_MODEL=EMPTY

21

470PF

CERM

10% 50V

402

C6033

NO STUFF

R6033

301K

21

1%

1/16W

402

MF-LF

DEBUG_ADC

SIGNAL_MODEL=EMPTY

DEBUG_ADC

R6044

MF-LF

1%

402

1/16W

2

PLACE_NEAR=U6000.1:5mm

1

226K

2

1

C6030

20% CERM

402

10V

DEBUG_ADC

0.1UF

21

R6034

DEBUG_ADC

1%

402

1/16W

226K

MF-LF

PLACE_NEAR=U6000.24:5mm

1M

DEBUG_ADC

402

1% 1/16W MF-LF

R6011

1

2

1/16W MF-LF 402

1%

R6010

1

2

DEBUG_ADC

649K

21

SM

PLACE_NEAR=R3452.1:3mm

XW6010

DEBUG_ADC

21

402

1% 1/16W MF-LF

R6012

226K

PLACE_NEAR=U6000.22:8mm

PLACE_NEAR=U6000.22:10mm

C6012

DEBUG_ADC

2

1

X5R 402

10%

6.3V

2.2UF

1

R6021

681K

DEBUG_ADC

2

402

MF-LF

1/16W

1%

2

1

R6020

1M

MF-LF 402

1/16W

1%

DEBUG_ADC

PLACE_NEAR=R4598.2:3mm

21

XW6020

SM

2

1

C6074

2.2UF

X5R

DEBUG_ADC

6.3V

10% 402

PLACE_NEAR=U6000.4:5mm

402

2

1

DEBUG_ADC

52.3K

1% 1/16W MF-LF

R6081

SM

XW6080

1 2

PLACE_NEAR=D9710.2:3mm

2

1

R6080

MF-LF

1/16W

DEBUG_ADC

1M

1%

402

33 99

2

1

X5R

10%

402

2.2UF

6.3V

C6044

DEBUG_ADC

PLACE_NEAR=U6000.1:5mm

42 99

2

1

C6034

10% 402

2.2UF

X5R

6.3V

PLACE_NEAR=U6000.24:5mm

DEBUG_ADC

42 99

412

1%

MF-LF

1/16W

402

DEBUG_ADC

R6061

1 2

412

MF-LF

1/16W

1%

DEBUG_ADC

R6060

21

402

499

21

402

MF-LF

1/16W

1%

DEBUG_ADC

R6050

33 99

2

R6051

499

402

MF-LF

1%

DEBUG_ADC

1/16W

1

PLACE_NEAR=U6000.5:5mm

2

1

C6082

2.2UF

X5R

DEBUG_ADC

6.3V 402

10%

PLACE_NEAR=U6000.5:5mm

21

R6082

DEBUG_ADC

226K

MF-LF

1/16W

402

1%

SIGNAL_MODEL=EMPTY

402

CERM

470PF

50V

10%

C6062

1

2

NO STUFF

SIGNAL_MODEL=EMPTY

348K

1/16W

1%

402

MF-LF

DEBUG_ADC

1

2

R6062

SIGNAL_MODEL=EMPTY

348K

1/16W

1%

402

MF-LF

DEBUG_ADC

R6063

1 2

SIGNAL_MODEL=EMPTY

470PF

CERM

10%

402

50V

C6063

1 2

NO STUFF

SIGNAL_MODEL=EMPTY

2

1

C6052

CERM

10% 50V

402

470PF

NO STUFF

SIGNAL_MODEL=EMPTY

2

1

R6052

280K

DEBUG_ADC

MF-LF 402

1% 1/16W

SIGNAL_MODEL=EMPTY

21

R6053

280K

MF-LF

402

1%

1/16W

DEBUG_ADC

SIGNAL_MODEL=EMPTY

21

470PF

10%

CERM

50V

C6053

402

NO STUFF

1/16W

1%

402

DEBUG_ADC

226K

R6064

1 2

MF-LF

PLACE_NEAR=U6000.3:5mm

2

1

C6040

DEBUG_ADC

0.1UF

CERM 402

10V

20%

PLACE_NEAR=U6000.2:5mm

21

R6054

226K

1/16W

1%

402

MF-LF

DEBUG_ADC

21

R6022

226K

1/16W

1%

MF-LF

402

DEBUG_ADC

PLACE_NEAR=U6000.23:8mm

PLACE_NEAR=U6000.23:10mm

2

1

C6022

2.2UF

X5R

10%

402

DEBUG_ADC

6.3V

2

1

C6000

DEBUG_ADC

0.1UF

CERM 402

20% 10V

DEBUG_ADC

7

25

16

8

2019181110

9

21

6

5

4

3

2

1

24

23

22

13

12

15

14

QFN

U6000

17

LTC2309

2

1

C6001

10UF

X5R 603

20%

6.3V

DEBUG_ADC

2

1

C6004

0.1UF

CERM 402

20% 10V

PLACE_NEAR=U4900.F1:10mm

33

DEBUG_ADC

21

R6001

402

MF-LF

5%

1/16W

R6031

DEBUG_ADC

243

1%

MF-LF

402

21

1/16W

10V

20% 402

CERM

0.1UF

DEBUG_ADC

C6002

1

2

DEBUG_ADC

2

1

C6005

10UF

X5R 603

20%

6.3V

PLACE_NEAR=U4900.E4:10mm

33

21

R6002

402

DEBUG_ADC

MF-LF

5%

1/16W

2

1

C6003

DEBUG_ADC

20%

6.3V X5R 603

10UF

10% X5R

C6064

2

1

2.2UF

6.3V 402

PLACE_NEAR=U6000.3:5mm

DEBUG_ADC

2

1

C6054

2.2UF

X5R

10%

DEBUG_ADC

6.3V 402

PLACE_NEAR=U6000.2:5mm

2

1

C6006

2.2UF

DEBUG_ADC

20%

6.3V CERM 402-LF

46 49 97 102

SYNC_DATE=07/08/2009

SYNC_MASTER=K17_CHENGD

DEBUG SENSORS AND ADC

DDRISNS_R_N

CPUDDR_IOUT

DDRISNS_R_P

ISNS_AIRPORT_R_N

PP5V_S5

ISNS_AIRPORT_IOUT

ISNS_AIRPORT_R_P

ISNS_LCDBKLT_P

DDRISNS_N

DDRISNS_P

PP1V5_S3RS0

PPCPUDDR_ISNS

ADC_CH3

PP5V_S5

ISNS_LCDBKLT_N

ISNS_LCDBKLT_IOUT

5V_SW_ODD_XW

SMBUS_SMC_MGMT_SCL

ADC_VREF

ADC_REFCOMP

ADC_SDA

ADC_CH2

ADC_CH7

ADC_CH6

ADC_CH0

ADC_CH4 ADC_CH5

ADC_CH3

ADC_CH1

ISNS_ODD_N

ADC_CH2

5V_SW_ODD_DIV

PP5V_SW_ODD

3V3_WLAN_F_XW

ISNS_AIRPORT_N

ADC_CH0

ADC_CH7ADC_CH6

VOUT_S0_LCDBKLT_DIV

PP5V_S5PP5V_S5

VOLTAGE=5V

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.25MM

PP5V_S5_DEBUG_ADC_AVDD_FILT PP5V_S5_DEBUG_ADC_DVDD_FILT

MIN_LINE_WIDTH=0.3MM

VOLTAGE=5V

MIN_NECK_WIDTH=0.25MM

SMBUS_SMC_MGMT_SDA

ADC_SCL

ISNS_ODD_P

ADC_CH5

ISNS_HDD_P

ISNS_HDD_N

VOUT_S0_LCDBKLT_XW

ADC_CH4

3V3_WLAN_F_DIV

PP3V3_WLAN_F

ISNS_AIRPORT_P

ISNS_ODD_IOUT

ISNS_ODD_R_N

ISNS_ODD_R_P

PP5V_S5

ISNS_HDD_IOUT

ISNS_HDD_R_N

ISNS_HDD_R_P

ADC_CH1

PPVOUT_S0_LCDBKLT

60 OF 132 57 OF 103

99

7

23 57 67 73

102

99

7

23 57 67 73

102

57

6

42

57

57 57

7

23 57 67 73

102

7

23 57 67 73

102

102 102

57

33

99

7

23 57 67 73

102

99

57

6

84 89

OUT

IN

IN IN

IN

GND

VCC

WP*/ACC

CE*

SI/SIO0

HOLD*

SCLK

SO/SIO1

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

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THE INFORMATION CONTAINED HEREIN IS THE

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A

B

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345678

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8 7 5 4 2 1

NOTE: If HOLD* is asserted ROM will ignore SPI cycles.

2

1

C6100

402

20%

CERM

0.1UF

10V

2

1

R6101

402

3.3K

5% MF-LF

1/16W

48

48 48

6

20 48

3

8

2

5

6

7

4

1

U6100

32MBIT

SOP

MX25L3205DM2I-12G

OMIT

CRITICAL

SPI ROM

SYNC_MASTER=K17_WFERRY

SYNC_DATE=06/09/2009

SPI_WP_L

PP3V3_S5

SPI_MLB_CLK

SPI_MLB_CS_L

SPIROM_USE_MLB

SPI_MLB_MISO

SPI_MLB_MOSI

61 OF 132 58 OF 103

6 7

31 35 49 50 51 72 73 74 84 86 99

101

IN

OUT

VL_HD

SENSE_A

GPIO1/DMIC_SDA2

GPIO0/DMIC_SDA1

VHP_FILT+

GPIO2

RESET*

LINEOUT_L1-

VBIAS_DAC

FLYP

VA_REF

VD

GPIO3

VHP_FILT-

LINEOUT_R1-

LINEOUT_R1+

LINEOUT_R2-

SPDIF_OUT

LINEIN_C-

FLYC FLYN

SPDIF_IN

LINEOUT_L1+

THRM_PAD

VA_HP

HPOUT_R

HPREF

VCOM

AGND

VA

LINEIN_R+

LINEIN_L+

MICIN_L+ MICIN_L-

MICBIAS

SYNC

DGND

DMIC_SCL

HPOUT_L

SDI SDO

VL_IF

BITCLK

MICIN_R-

MICIN_R+

VREF+_ADC

LINEOUT_L2+ LINEOUT_L2LINEOUT_R2+

/SPDIF_OUT2

IN IN

IN

OUT OUT

OUT

IN

BP

NC

SHDN*

IN OUT

GND

OUT

IN

OUT OUT

IN IN

OUT

OUT OUT

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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8 7 5 4 2 1

AUDIO 4.5V REGULATOR

MAC SPKR AMP CNTRL

HP AMP CNTRL

WIN SPKR AMP CNTRL

APPLE P/N 353S2234

INTERNAL MIC INPUT

DAC2/3 FSOUTPUTSE= 1.34VRMS

SE FSINPUT= 1.22VRMS

EXTERNAL MIC INPUT

DAC1 FSOUTPUT= 1.34VRMS

APPLE P/N 353S2592

AUDIO CODEC

NC

WFR SPKR AMPS (L2/R2)

LFE SPKR AMP (FC/LFE)

DIFF FSINPUT= 2.45VRMS

NC

DAC2/3 FSOUTPUTDIFF= 2.67VRMS

64

17 94

CERM

6.3V

402-LF

20%

2.2UF

C6211

1

2

C6212

6.3V CERM 402-LF

20%

2.2UF

1

2

59 60

2.67K

1% 1/16W

402

MF-LF

R6200

1

2

20%

4V X5R 402

4.7UF

C6200

1

2

62

10% 10V X5R 402

0.47UF

C6201

1

2

20%

6.3V X5R

603-3

10UF

C6209

1

2

20%

10UF

X5R

6.3V 603-3

C6210

1

2

R6203

100K

1/16W MF-LF

402

1%

1

2

NOSTUFF

1/16W 402

MF-LF

5%

0

R6204

1

2

CS4206ACNZC

QFN

CRITICAL

U6200

26

6

7

4

43 42

45

2

12

14 15

38 40

39

22

21

23

34

35

30

31

37

36

33

32

16

17

18

20

19

11

8 5

13

47 48

10

49

25

46

24

29

28

9

41

44

3

1

27

1UF

CASE-R-HF

20V

TANT

10%

CRITICAL

C6213

1

2

CASE-B2-SM

CRITICAL

POLY-TANT

10UF

20% 16V

C6214

1

2

SM

XW6201

1 2

64

60

62

10UF

20% 16V

CASE-B2-SM

POLY-TANT

C6202

1

2

63

0.47UF

10% 10V X5R 402

C6203

1

2

16V

10UF

20% POLY-TANT

CASE-B2-SM

C6204

1

2

X5R

10% 10V

0.47UF

402

C6205

1

2

402-1

10% 10V X5R

1UF

C6206

1

2

10% 10V X5R 402

0.47UF

C6207

1

2

CRITICAL

20% 10V X5R

10UF

805

C6208

1

2

60 61

61 62

63

59 60

8

59 61

6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52 53 55 59 63 64 69 70 71 72 73 74 81

84 85 86 88 99

101

59 60

63

0.1UF

10% 16V X5R 402

C6250

1

2

0402

FERR-220-OHM

L6250

1 2

17 94

SM

XW6200

1 2

10% 10V X5R 402

1UF

C6251

1

2

10% 50V CERM 402

0.001UF

C6252

1

2

10% 16V

CERM

402

0.01UF

C6253

1 2

C6255

CRITICAL

20% 10V TANT 1206-LLP

2

1

47UF

C6254

10% 10V X5R 402

1UF

1

2

CRITICAL

MAX8840-4.5V

UDFN

U6201

4

2

1

5

6

3

1/16W MF-LF

5%

402

1K

R6250

1 2

62

17 94

62

64

61

1/16W 402

MF-LF

5%

EXT_HP_AMP

0

R6206

1

2

R6201

5% 1/16W MF-LF

402

33

1 2

5%

MF-LF

1/16W

33

402

R6202

1 2

60 62

17 94

BAT54XV2T1

SOD-523

D6200

2

1

17 94

AUDIO:CODEC

SYNC_DATE=05/30/2009

SYNC_MASTER=K17_REF

AUD_GPIO_2

AUD_GPIO_3

AUD_SENSE_A

HDA_SDIN0

HDA_SYNC

CS4206_SPDIF_OUT

HDA_SDOUT

AUD_SPDIF_OUT

AUD_SDI_R

AUD_REG_SHDN_L

PP5V_S0_AUDIO

AUD_MIC_INL_N

AUD_LI_P_L

AUD_MIC_INR_P

TP_AUD_LO2_L_P TP_AUD_LO2_L_N

CS4206_VCOM

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.20MM

AUD_LO2_R_P

CS4206_FLYP

MIN_NECK_WIDTH=0.15MM

MAX8840_BP

MIN_LINE_WIDTH=0.20MM

MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.20MM VOLTAGE=5V

AUD_4V5_REG_IN

CS4206_FP

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.20MM

CS4206_VREF_ADC

AUD_LI_N

PP3V3_S0

CS4206_FN

TP_AUD_DMIC_CLK

AUD_LI_N

MAKE_BASE=TRUE

AUD_LI_N

GND_AUDIO_CODEC

GND_AUDIO_HPAMP

PP4V5_AUDIO_ANALOG

MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM

AUD_HP_PORT_L

VBIAS_DAC

GND_AUDIO_HPAMP

HDA_BIT_CLK

AUD_SPDIF_IN

CS4206_FLYC

TP_AUD_GPIO_0 AUD_GPIO_1

AUD_LO2_R_N AUD_LO3_L_P

AUD_LO3_L_N AUD_LO3_R_P AUD_LO3_R_N

AUD_CODEC_MICBIAS

AUD_LI_P_R

AUD_MIC_INL_P

AUD_MIC_INR_N

MIN_NECK_WIDTH=0.15MMMIN_LINE_WIDTH=0.20MM

AUD_INT_HP_REF

MIN_LINE_WIDTH=0.30MM

AUD_HP_PORT_R

MIN_NECK_WIDTH=0.20MM

PP1V5_S0

PP4V5_AUDIO_ANALOG

VOLTAGE=4.5V MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.40MM

PP5V_S0_AUDIO

PP3V3_S0

GND_AUDIO_CODEC

VOLTAGE=0V MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.60MM

GND_AUDIO_HPAMP

GND_AUDIO_CODEC

VOLTAGE=0V MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM

HDA_RST_L

CS4206_FLYN

PP4V5_AUDIO_ANALOG

62 OF 132 59 OF 103

8

59 61

6 7 8

25 26 27 28 30 34 37 40 42 47 48

49 52 53 55 59 63 64 69 70 71 72 73 74

81 84 85 86 88 99

101

59 60

59 60 61 64

59 61 62

7

34 42 72 74 99

59 60

59 60 61 64

59 61 62

59 60 61 64

IN

OUT

IN

OUT

IN

V-

V+

V-

V+

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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8 7 5 4 2 1

SE-TO-DIFF CONVERTER

CODEC Nom SE RIN = 20K OHMS VIN = 2VRMS, CODEC VIN = 1.14 VRMS

NET RIN = 18K OHMS

FC = 5 HZ Max

60 63

7.87K

1/16W MF-LF

1%

402

R6306

1 2

1%

MF-LF

21.5K

1/16W

402

R6305

1

2

10% 50V CERM 402

820PF

NOSTUFF

C6304

1

2

CRITICAL

3.3UF

10% 16V

TANT

SMA-HF1

C6305

12

10% 16V

TANT

SMA-HF1

CRITICAL

3.3UF

C6303

12

7.87K

1/16W MF-LF

1%

402

R6300

1 2

402

MF-LF

1/16W

1%

21.5K

R6301

1

2

10% 16V

TANT

SMA-HF1

3.3UF

CRITICAL

C6302

12

63

10% 16V

TANT

SMA-HF1

3.3UF

CRITICAL

C6300

12

59 60

59

59 60

59

59 60 61 64

10% 50V CERM 402

820PF

NOSTUFF

C6301

1

2

59 62

6.3V

2

1

C6350

402

4.7UF

20% X5R

10% 10V X5R 402

0.47UF

C6351

1

2

402

MF-LF

1/16W

1%

10

R6303

1

2

62

3.3UF

16V

SMA-HF1

CRITICAL

TANT

10%

C6353

12

60 63

1/16W MF-LF

2.21K

1%

402

R6355

1 2

2.21K

1%

402

MF-LF

1/16W

R6357

1 2

MF-LF

402

1%

1/16W

2.21K

R6358

1 2

MF-LF

1%

402

1/16W

2.21K

R6356

1 2

3.3UF

10% 16V TANT SMA-HF1

CRITICAL

C6352

1

2

63

402

MF-LF

1/16W

1%

21K

R6350

1

2

402

MF-LF

1/16W

1%

21K

R6351

1

2

1%

402

1/16W MF-LF

10.5K

R6354

1 2

21K

1/16W MF-LF

1%

402

R6353

1 2

CRITICAL

UCSP

MAX4253

U6350

C3

C2

C1

C4

B1

B4

CRITICAL

UCSP

MAX4253

U6350

A3

A2

A1

A4

B1

B4

SYNC_DATE=05/30/2009

AUDIO: LINE IN

SYNC_MASTER=K17_REF

AUD_LI_GND

MIN_LINE_WIDTH=.3MM

MIN_NECK_WIDTH=.2MM

AUD_LI_LF

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

AUD_LI_GND

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

AUD_LI_P_L

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

AUD_LI_N

MIN_LINE_WIDTH=0.3MM

AUD_LI_P_R

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

AUD_LI_N

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

AUD_LI_INL

GND_AUDIO_CODEC

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

AUD_LI_INR

AUD_HP_PORT_R

AUD_SE_DIFF_IN

MIN_NECK_WIDTH=.2MM MIN_LINE_WIDTH=.3MM

AUD_LI_RF

GND_AUDIO_CODEC

PP4V5_AUDIO_ANALOG

AUD_SE_DIFF_N_INV

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM

AUD_SE_DIFF_VBIAS

AUD_LO1_R_N

AUD_SE_DIFF_P_INV

AUD_SE_DIFF_IN_R

AUD_LO1_R_P

AUD_GPIO_2

63 OF 132 60 OF 103

59 61

59 60 61 64

59

IN

OUT

IN

IN IN

LIN

PVEE

CN CP

ROUT

LOUT

VSS2

VSS1

THRM

AVDD

PVDD

RIN

PDN*

PAD

IN

OUT

IN

OUT

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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8 7 5 4 2 1

1ST ORDER DAC FILTER

LP:42.10 KHZ

CS4206A HP OUT ZOBEL NETWORK &

1ST ORDER DAC FILTER PLACEHOLDER

NC

APN:353S2347

VOLTAGE GAIN:1.53

HEADPHONE AMPLIFIER (AK4201)

RUN PP5V_AUDIO_HPAMP_* NETS OVER GND

PLACE XW5802 & XW5803 NEAR PP5V_S0_AUDIO

PLACE XW5800 NEAR U5800 PINS 1/12

59 60 61

INT_HP_AMP

603

5%

MF-LF

1/10W

0

R6552

1 2

61 63

NOSTUFF

5%

2200PF

50V C0G-CERM 603

CRITICAL

C6552

1

2

50V 603

5% C0G-CERM

2200PF

NOSTUFF CRITICAL

C6553

1

2

SM

XW6500

1 2

59

59 62

61

EXT_HP_AMP

5%

MF-LF

1/16W

0

402

R6501

1 2

SM

XW6503

1 2

402

100K

EXT_HP_AMP

MF-LF

1/16W

5%

R6500

1

2

SM

XW6502

1 2

EXT_HP_AMP

10UF

805

X5R

20% 10V

C6502

1

2

0.1UF

10% 16V

402

EXT_HP_AMP

X5R

C6503

1

2

EXT_HP_AMP

CRITICAL

AK4201EU

USON

U6500

3

6 7

1 2

8

5

10

12 11

13

4

9

CRITICAL

EXT_HP_AMP

1UF

402

X5R

10V

10%

C6504

1

2

59 61 62

EXT_HP_AMP

13.7K

1% 1/16W MF-LF 402

R6531

1

2

1UF

10V

CRITICAL

X5R 402

10%

EXT_HP_AMP

C6505

1

2

MF-LF

EXT_HP_AMP

21K

402

1%

1/16W

R6530

1 2

0603

FERR-220-OHM-2.5A

EXT_HP_AMP

L6535

1 2

EXT_HP_AMP

603

MF-LF

1/10W

5%

0

R6515

1 2

EXT_HP_AMP

603

5%

MF-LF

1/10W

0

R6525

1 2

805

X5R

10V

20%

10UF

EXT_HP_AMP

C6500

1

2

EXT_HP_AMP

402

50V CERM

10%

0.001UF

C6501

1

2

61 63

402

MF-LF

1/16W

5%

39

R6551

1

2

61 63

59 60 61

61

59 61 62

EXT_HP_AMP

1%

1/16W

13.7K

402

MF-LF

R6520

1 2

MF-LF

13.7K

1/16W

1%

402

EXT_HP_AMP

R6510

1 2

EXT_HP_AMP

1%

1/16W

21K

402

MF-LF

R6521

1 2

NOSTUFF CRITICAL

180PF

402

CERM

50V

5%

C6521

1 2

10% 16V

X7R-CERM

402

0.1UF

C6551

1

2

NOSTUFF CRITICAL

180PF

402

CERM

50V

5%

C6511

1 2

EXT_HP_AMP

402

1%

MF-LF

1/16W

21K

R6511

1 2

603

5%

MF-LF

1/10W

0

INT_HP_AMP

R6554

1 2

0

1/10W MF-LF

5%

603

INT_HP_AMP

R6553

1 2

61 63

21K

1% 1/16W MF-LF

402

R6516

1

2

402

MF-LF

1/16W

21K

1%

R6526

1

2

SM

XW6501

1 2

61 63

16V

X7R-CERM

402

10%

0.1UF

C6550

1

2

1/16W

39

402

MF-LF

5%

R6550

1

2

SYNC_DATE=05/30/2009

SYNC_MASTER=K17_REF

AUDIO: HEADPHONE OUT

AUD_HPAMP_INL_M

AUD_LO_GND_R

AUD_HPAMP_OUTR_R

AUD_HP_PORT_R

AUD_HPAMP_INR_M

AUD_HPAMP_OUTR_R

MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM

AUD_HPAMP_OUTL_R

MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM

AUD_HPAMP_OUTL

MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM

AUD_HPAMP_OUTR

MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM

AK4201_CN

MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.20MM

MIN_NECK_WIDTH=0.20MM

AK4201_CP

MIN_LINE_WIDTH=0.40MM

AUD_HPAMP_MUTE_L

AUD_HPAMP_INL_M AUD_HPAMP_INR_M

AUD_GPIO_1

PP5V_S0_AUDIO

AUD_HP_PORT_L

MIN_NECK_WIDTH=0.20MM

AK4201_PVEE

MIN_LINE_WIDTH=0.40MM

GND_AUDIO_CODEC

PP5V_S0_AUDIO

MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM

AUD_Z_L

MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM

AUD_Z_R

MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM

AUD_HP_PORT_L

GND_AUDIO_HPAMP

AUD_HP_PORT_R

AUD_HPAMP_OUTL_R

AUD_HPAMP_OUTR

PP5V_AUDIO_HPAMP_PVDD_F

MIN_NECK_WIDTH=0.20MM

VOLTAGE=5V MIN_LINE_WIDTH=0.40MM

MIN_NECK_WIDTH=0.20MM

PP5V_AUDIO_HPAMP_AVDD_F

MIN_LINE_WIDTH=0.40MM

VOLTAGE=5V

GND_AUDIO_HPAMP_PGND

VOLTAGE=0V MIN_LINE_WIDTH=0.60MM MIN_NECK_WIDTH=0.20MM

AUD_HPAMP_OUTL

MIN_NECK_WIDTH=0.20 MM

AUD_LO_GND_R

MIN_LINE_WIDTH=0.60 MM

VOLTAGE=0V

AUD_LO_GND_R

AUD_LO_FDBKAK4201_VSS2

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.40MM

65 OF 132 61 OF 103

61

8

59 61

59 60 64

8

59 61

61

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

SD*

OUT+

PVDD

GND

VDD

IN+

IN-

OUT_

SD*

OUT+

PVDD

GND

VDD

IN+

IN-

OUT_

SD*

OUT+

PVDD

GND

VDD

IN+

IN-

OUT_

SD*

OUT+

PVDD

GND

VDD

IN+

IN-

OUT_

SD*

OUT+

PVDD

GND

VDD

IN+

IN-

OUT_

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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8 7 5 4 2 1

GND_AUDIO_CODEC & DIGITAL GND

PLACE C6645 CLOSE TO VDD PIN

PLACE C6641/C6642 CLOSE TO PVDD PIN

PLACE C6651/C6652 CLOSE TO PVDD PIN

PLACE C6635 CLOSE TO VDD PIN

PLACE C6625 CLOSE TO VDD PIN

PLACE C6655 CLOSE TO VDD PIN

GAIN = +6 DB

5X MONO SPEAKER AMPLIFIERS (SSM2315)

APN: 353S2500

PLACE C6621/C6622 CLOSE TO PVDD PIN

PLACE C6615 CLOSE TO VDD PIN

L6602 SHOULD BRIDGE SPLIT BETWEEN

GND_AUDIO_CODEC & DIGITAL GND

L6602 SHOULD BRIDGE SPLIT BETWEEN

FC (SPEAKERS BL/BR) = ~737 HZ FC (SPEAKERS FL/FR/LFE) = ~90 HZ

PLACE C6611/C6612 CLOSE TO PVDD PIN

PLACE C6631/C6632 CLOSE TO PVDD PIN

100K

402

MF-LF

1/16W

5%

R6600

1

2

0402

FERR-1000-OHM

L6601

1 2

59 61

59 60

FERR-1000-OHM

0402

L6610

1 2

6

63 99

6

63 99

6

63 99

CERM 402

50V

0.001UF

10%

CRITICAL

C6611

1

2

10%

0.001UF

50V 402

CERM

CRITICAL

C6621

1

2

FERR-1000-OHM

0402

L6620

1 2

59

6

63 99

CRITICAL

402

50V CERM

10%

0.001UF

C6631

1

2

FERR-1000-OHM

0402

L6630

1 2

60

6

63 99

6

63 99

0.001UF

CRITICAL

402

50V

10% CERM

C6641

1

2

FERR-1000-OHM

0402

L6640

1 2

59

6

63 99

6

63 99

CRITICAL

TANT

20%

6.3V

100UF

CASE-AL1

C6622

1

2

CASE-AL1

TANT

100UF

6.3V

20%

CRITICAL

C6642

1

2

CASE-AL1

100UF

20%

6.3V TANT

CRITICAL

C6652

1

2

0.001UF

10% 50V CERM 402

CRITICAL

C6651

1

2

0402

FERR-1000-OHM

L6650

1 2

59

6

63 99

6

63 99

X5R

1UF

10% 10V

402

C6615

1

2

10% 10V X5R 402

1UF

C6625

1

2

10%

402

1UF

X5R

10V

C6635

1

2

1UF

402

X5R

10V

10%

C6645

1

2

402

X5R

10V

10%

1UF

C6655

1

2

0402

FERR-1000-OHM

L6611

1 2

59 61

SSM2315

WLCSP

CRITICAL

U6610

A2

B3

C1 A1

A3

C3

B2

C2

B1

SSM2315

CRITICAL

WLCSP

U6620

A2

B3

C1 A1

A3

C3

B2

C2

B1

WLCSP

SSM2315

CRITICAL

U6630

A2

B3

C1 A1

A3

C3

B2

C2

B1

SSM2315

WLCSP

CRITICAL

U6640

A2

B3

C1 A1

A3

C3

B2

C2

B1

WLCSP

SSM2315

CRITICAL

U6650

A2

B3

C1 A1

A3

C3

B2

C2

B1

0402

FERR-1000-OHM

L6621

1 2

59

1/16W

402

0

5%

MF-LF

R6611

1 2

402

1/16W MF-LF

0

5%

R6612

1 2

402

MF-LF

5%

0

1/16W

R6621

1 2

MF-LF

R6622

1/16W

0

5%

402

1 2

402

0

5%

MF-LF

1/16W

R6631

1 2

402

0

MF-LF

5%

1/16W

R6632

1 2

FERR-1000-OHM

0402

L6631

1 2

60

FERR-1000-OHM

0402

L6641

1 2

59

402

1/16W MF-LF

5%

0

R6641

1 2

1/16W

402

MF-LF

5%

0

R6642

1 2

0402

FERR-1000-OHM

L6651

1 2

59

402

0

5% 1/16W MF-LF

R6652

1 2

402

0

5% MF-LF

1/16W

R6651

1 2

402

CRITICAL

0.0027UF

CERM

50V

10%

C6613

1 2

402

10% 50V

CRITICAL

0.0027UF

CERM

C6614

1 2

CRITICAL

0.0027UF

402

CERM

50V

10%

C6633

1 2

10% 50V

CERM

402

0.0027UF

CRITICAL

C6634

1 2

X7R

C6623

25V

10%

0.022UF

CRITICAL

0402

21

X7R

C6624

0.022UF

25V

10%

CRITICAL

0402

21

X7R

C6643

CRITICAL

0.022UF

10% 25V

0402

21

X7R

C6644

CRITICAL

10% 25V

0.022UF

0402

21

X7R

C6653

CRITICAL

0.022UF

10% 25V

0402

21

X7R

C6654

0.022UF

CRITICAL

25V

10%

0402

21

100K

5% 1/16W MF-LF

402

R6601

1

2

FERR-1000-OHM

0402

L6602

1 2

59

1/16W

402

MF-LF

5%

0

R6602

1 2

NOSTUFF

1UF

10% X5R

10V 402

C6600

1

2

1

2

2012-LLP

CRITICAL

47UF

20%

C6612

6.3V

POLY-TANT

1

2

2012-LLP

6.3V

C6632

CRITICAL

47UF

20%

BAT54XV2T1

D6600

12

SOD-523

NOSTUFF

SYNC_DATE=05/30/2009

SYNC_MASTER=K17_REF

AUDIO:SPEAKER AMP

AUD_GPIO_2_L

AUD_SPKRAMP_MAC_SHDN_L

PP5V_S0_AUDIO_AMP_L

SPKRAMP_FL_IN_C_N

PP5V_S0_AUDIO_AMP_L

SPKRAMP_BL_IN_L_P

SSM2315FL_IN_N SSM2315FL_IN_P

AUD_LO2_R_N

AUD_GPIO_2

AUD_HP_PORT_L

SPKRAMP_FL_IN_L_P

GND_AUDIO_HPAMP

SSM2315BL_IN_N SSM2315BL_IN_P

SPKRAMP_BR_IN_C_N

SSM2315BR_IN_N

AUD_SPKRAMP_MAC_SHDN_L

SPKRAMP_BL_IN_L_N

AUD_LO3_L_P

SPKRAMP_BR_IN_L_N

SPKRAMP_BL_IN_C_N

SPKRAMP_FL_IN_L_N

AUD_LO3_R_P

SPKRAMP_BL_OUT_P

MIN_LINE_WIDTH=0.50 MM MIN_NECK_WIDTH=0.20 MM

SPKRAMP_BL_OUT_N

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.50 MM

SPKRAMP_FL_OUT_P

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.50 MM

SPKRAMP_FL_OUT_N

MIN_LINE_WIDTH=0.50 MM MIN_NECK_WIDTH=0.20 MM

AUD_LO3_L_N

SPKRAMP_BL_IN_C_P

SPKRAMP_LFE_OUT_P

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.50 MM

SPKRAMP_LFE_OUT_N

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.50 MM

SSM2315LFE_IN_N

AUD_SPKRAMP_WIN_SHDN_L

SSM2315LFE_IN_P

SPKRAMP_LFE_IN_C_P

SPKRAMP_LFE_IN_C_N

SPKRAMP_LFE_IN_L_N

SPKRAMP_LFE_IN_L_P

AUD_LO2_R_P

SPKRAMP_BR_OUT_P

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.50 MM

SSM2315BR_IN_P

SPKRAMP_BR_IN_C_PSPKRAMP_BR_IN_L_P

AUD_LO1_R_N

AUD_LO1_R_P

PP5V_S0_AUDIO_AMP_R

AUD_LO3_R_N

SPKRAMP_FR_IN_L_P SPKRAMP_FR_IN_C_P

SPKRAMP_FR_IN_C_N

SPKRAMP_FR_IN_L_N

SSM2315FR_IN_P

PP5V_S0_AUDIO_AMP_R

AUD_SPKRAMP_WIN_SHDN_L

SPKRAMP_FR_OUT_P

MIN_LINE_WIDTH=0.50 MM MIN_NECK_WIDTH=0.20 MM

SPKRAMP_FR_OUT_N

MIN_LINE_WIDTH=0.50 MM MIN_NECK_WIDTH=0.20 MM

SSM2315FR_IN_N

AUD_GPIO_3

SPKRAMP_BR_OUT_N

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.50 MM

PP5V_S0_AUDIO_AMP_R

SPKRAMP_FL_IN_C_P

AUD_SPKRAMP_WIN_SHDN_L

66 OF 132 62 OF 103

62

8

62

99

8

62

99

62

99

62

99

8

62

99

8

62

99

8

62

99

62

IN IN

OUT

IN

IN IN

OUT

IN IN

AUDIO

MICROPHONE

DETECT FOR PT

GROUND

RIGHT

LEFT

SWITCH

POF

SHIELD

SHELL

PINS

C - GND

A - VIN B - VCC

OPERATING VOLTAGE 3.3

GROUND

RIGHT

LEFT

SWITCH

DETECT FOR PT

AUDIO

PINS

SHELL

SHIELD

POF

A - VDD B - GND

C - VOUT

OPERATING VOLTAGE 3.3

OUT

IN

OUT

BI

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

RETURN FOR HF NOISE

APN: 514-0632

SPEAKER CONNECTORS

APN: 518S0521

MIC CONNECTOR

APN: 518S0520

APN: 518S0672

APN: 514-0633

AUDIO JACK 2 LINE IN JACK, SPDIF RX

AUDIO JACK 1 LO/HP JACK, SPDIF TX

6

62 99

6

62 99

6

62 99

6

62 99

402

5%

MF-LF

10

1 2

1/16W

R6755

402

6.8V-100PF

DZ6704

1

2

CRITICAL

6.8V-100PF

CRITICAL

402

2

DZ6752

1

0402

21

600-OHM-300MA

L6754

CRITICAL

402

6.8V-100PF

DZ6705

1

2

402

CRITICAL

6.8V-100PF

DZ6702

1

2

6.8V-100PF

402

CRITICAL

DZ6703

1

2

CRITICAL

DZ6750

ESDALC5-1BM2

1

2

SOD882

2

1

DZ6751

CRITICAL

6.8V-100PF

402

61

0402

FERR-1000-OHM

L6706

1 2

0402

FERR-1000-OHM

L6700

1 2

CRITICAL

402

6.8V-100PF

DZ6701

1

2

0402

FERR-1000-OHM

L6703

1 2

FERR-1000-OHM

0402

L6751

1 2

CRITICAL

78171-0003

M-RT-SM

J6780

4

5

1 2 3

6

62 99

6

62 99

1

FERR-1000-OHM

0402

L6752

2

NOSTUFF

5% 50V CERM 402

100PF

C6786

1

2

5%

50V

CERM

402

100PF

NOSTUFF

C6785

1

2

NOSTUFF

5% 50V CERM 402

100PF

C6788

1

2

NOSTUFF

5%

50V

CERM

402

100PF

C6787

1

2

78171-0004

M-RT-SM

CRITICAL

J6781

5

6

1 2 3 4

0402

FERR-1000-OHM

L6753

1 2

6

62 99

6

62 99

64

5%

50V

CERM

402

100PF

NOSTUFF

C6781

1

2

CERM

100PF

5%

402

50V

NOSTUFF

C6782

1

2

5%

50V

CERM

402

100PF

NOSTUFF

C6783

1

2

5% 50V CERM 402

NOSTUFF

100PF

C6784

1

2

6

62 99

6

62 99

5%

50V

CERM

402

100PF

NOSTUFF

C6789

1

2

5% 50V CERM 402

100PF

NOSTUFF

C6790

1

2

78171-6006

M-RT-SM

CRITICAL

J6782

7

8

1 2 3 4 5 6

F-RT-TH

CRITICAL

1

10 11 12 13

2

3 4

5

6

7 8 9

SPDIF-TX-K20

J6700

CRITICAL

SPDIF-RX-K20

F-RT-TH

J6750

1

10 11 12

2

3 4

5

9

6 7 8

FERR-1000-OHM

0402

L6702

1 2

64

59

CRITICAL

402

6.8V-100PF

DZ6700

1

2

1UF

10% 10V X5R

C6700

1

2

402

1UF

402

X5R

10V

10%

C6750

1

2

64

0

402

MF-LF

1/16W

5%

R6780

1

2

FERR-1000-OHM

0402

L6781

1 2

0402

FERR-1000-OHM

L6780

1 2

64 99

5% 1/16W MF-LF

0

402

R6750

1 2

402

MF-LF

0

5%

INT_HP_AMP

1/16W

R6709

1 2

60

DZ6753

CRITICAL

ESDALC5-1BM2

1

2

SOD882

59

60

61

CRITICAL

0603

FERR-220-OHM-2.5A

L6707

1 2

CRITICAL

0402

FERR-220-OHM

L6705

1 2

0402

FERR-220-OHM

CRITICAL

L6704

1 2

64

1/16W

402

MF-LF

5%

10K

R6701

1 2

SYNC_DATE=11/24/2009

AUDIO: JACKS

SYNC_MASTER=K17_LENGO

MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.20MM

AUD_CONNJ2_TIP

AUD_CONNJ2_RING

MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.20MM

AUD_CONNJ1_SLEEVE2

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.40MM

AUD_CONNJ1_RING

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.40MM

GND_CHASSIS_AUDIO_JACK

VOLTAGE=0V

MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.10MM

AUD_LI_INL

AUD_LI_GND

AUD_LI_INR

PP3V3_S0

AUD_LO_GND_R

AUD_J2_TIPDET_R

SPKRAMP_FR_OUT_P SPKRAMP_FR_OUT_N

AUD_HPAMP_OUTL_R

AUD_J1_TIPDET_R

INT_MIC_F_P

HS_MIC_HI

AUD_HPAMP_OUTR_R

AUD_INT_HP_REF

INT_MIC_F_N

INT_MIC_N

SPKRAMP_LFE_OUT_P SPKRAMP_LFE_OUT_N

SPKRAMP_BR_OUT_N

SPKRAMP_BR_OUT_P

HS_MIC_LO

AUD_J1_SLEEVEDET_R

SPKRAMP_BL_OUT_P

INT_MIC_SHIELD

INT_MIC_P

AUD_J1_PERIPHDET_R

SPKRAMP_BL_OUT_N

SPKRAMP_FL_OUT_N

SPKRAMP_FL_OUT_P

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.40MM

AUD_CONNJ1_SLEEVE

MIN_LINE_WIDTH=0.40MM

AUD_CONNJ1_TIPDET

MIN_NECK_WIDTH=0.20MM

PP3V3_S0

AUD_SPDIF_IN

AUD_CONNJ2_TIPDET

AUD_SPDIF_OUT

AUD_CONNJ1_TIP

MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.20MM

AUD_CONNJ1_SLEEVEDET

MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.20MM

GND_CHASSIS_AUDIO_JACK

AUD_J2_OPT_OUT

AUD_CONNJ2_SLEEVE

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.40MM

67 OF 132 63 OF 103

63

6 7 8

25 26 27 28

30 34 37 40 42 47 48 49 52

53 55 59 63 64 69

70 71 72 73 74 81 84 85 86

88 99

101

59

6

99

6 7 8

25 26 27 28

30 34 37 40 42 47

48 49 52 53 55

59 63 64 69 70 71

72 73 74 81 84

85 86 88 99

101

63

OUT

IN

D

SG

D

SG

D

SG

D

SG

D

G S

OUT

IN

OUT

IN

BI

OUT

IN

OUT

GND THM

ENABLE

AVDD

SDA

MICBIAS

DETECT

BYPASS

INT*

SCL

IN

D

SG

D

SG

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

N/A N/A GPIO_3 GPIO_3 N/A

N/A 0X0D (13,B,RIGHT) 0X0D (13,V22,B,LEFT)

0X06 (6)

0X07 (7)

CODEC INPUT SIGNAL PATHS

VOLUME/MUTE

CODEC OUTPUT SIGNAL PATHS

0X02 (2)

0X03 (3)

SPDIF OUT

HP/LINE OUT

FUNCTION

0X02 (2)

0X0A (10,D)

SPEAKERS BL/BR SPEAKERS FL/FR

0X04 (4)

CONVERTER 0X05 (5)

SPEAKER LFE

0X03 (3)

PORT A DETECT

MIKEY

PORT B DETECT

0X09 (9,A)

0x10 (16)

GPIO_2

PIN COMPLEX

0X04 (4)

0X02 (2)

0X09 (9,V23) 0X0B (11)

CONVERTER

MAC OS SHDN

EXTRACTION NOTIFICATION CKT

VREF

PORT C DETECT (LINE IN)

KEEP DET TRACE AS SHORT AS POSS

INTERNAL MICROPHONE

"MIKEY"/EXTERNAL MICROPHONE

LINE IN

NC

FUNCTION

NC

(LINE OUT)

N/A

EXTERNAL MIC

PLACE L6800/C6800 CLOSE TO Q6800/01/02

INTERNAL MIC

SPDIF IN

MIKEY

PIN COMPLEX

0X08 (8)

0X12 (12,C)

(SPDIF DELEGATE)

NC

0x0F (15)

DET ASSIGNMENT 0X09 (A) N/A N/A N/A 0X0D (B)

DET ASSIGNMENT 0X12 (C) N/A N/A

N/A

WIN SHDN

MICBIAS (80%)

N/A

GPIO_2

2

1

C6801

0.1UF

20% CERM

10V 402

21

R6802

1/16W

402

MF-LF

5%

47K

59 64

63

2

1

C6800

0.1UF

X5R 402

10% 16V

21

L6800

0402

FERR-1000-OHM

21

R6803

1/16W

100K

5%

MF-LF

402

2

1

R6804

220K

5% 1/16W MF-LF 402

2

1

C6802

CERM

10% 16V

402

0.01UF

63 64

2

1

C6811

CERM

402

20%

10V

0.1UF

2

1

R6811

270K

MF-LF 402

5% 1/16W

21

R6812

47K

MF-LF

402

5%

1/16W

63

4

5

3

Q6800

SOT563

SSM6N15FEAPE

1

2

6

Q6800

SSM6N15FEAPE

SOT563

4

5

3

Q6801

SOT563

SSM6N15FEAPE

1

2

6

Q6801

SSM6N15FEAPE

SOT563

2

1

3

Q6802

SOD-VESM-HF

SSM3K15FV

59 64

21

R6855

MF-LF

1/16W

402

2.2K

5%

2

1

C6853

NOSTUFF

5% 50V CERM 402

15PF

2

1

R6852

402

100K

5% 1/16W MF-LF

59

59 63 99

2

1

C6854

CRITICAL

TANT-POLY

16V 2012-LLP

20%

10UF

2

1

C6882

10% 25V

402

X7R

0.01UF

21

L6880

FERR-1000-OHM

0402

2

1

C6880

10UF

CRITICAL

20%

6.3V X5R 603

21

R6890

0

1/16W MF-LF

5%

402

21

R6891

5%

0

1/16W MF-LF

402

21

R6892

0

1/16W MF-LF

5%

402

21

R6893

1/16W

0

MF-LF

5%

402

2

1

R6880

1/16W MF-LF

5%

402

100K

2

1

R6882

402

MF-LF

1/16W

5%

2.2K

2

1

C6883

4.7UF

20%

6.3V TANT 603-HF

CRITICAL

6

17 25 26 28 30 32 34 42 48 49 94

20 25

6

17 25 26 28 30 32 34 42 48 49 94

19

2

1

C6887

5% 50V CERM 402

NOSTUFF 15PF

2

1

R6883

5%

402

100K

1/16W MF-LF

63

59

2

1

C6881

10% 50V CERM 402

0.001UF

2

1

R6884

NOSTUFF

0

402

MF-LF

1/16W

5%

11

5

6

1

7

4

9

8

2

10

3

U6800

CRITICAL

CD3275

DRC

21

R6885

402

5%

MF-LF

1/16W

2.2K

2

1

R6881

1K

5% 1/16W MF-LF 402

64

21

R6860

402

5%

MF-LF

1/16W

15K

2

1

C6860

0.1UF

402

CERM

10V

20%

4

5

3

Q6803

SOT563

SSM6N15FEAPE

2

1

R6861

5% MF-LF

402

220K

1/16W

1

2

6

Q6803

SOT563

SSM6N15FEAPE

2

1

R6862

5% 1/16W MF-LF 402

100K

21

R6863

5%

1/16W

402

MF-LF

0

19

2

1

C6886

0.0082UF

402

X7R

25V

10%

59

21

XW6800

SM

21

XW6850

SM

59

2

1

R6851

3.40K

MF-LF

1% 1/16W

402

2

1

R6850

3.40K

1% 1/16W MF-LF 402

2

1

C6852

10%

0.0082UF

402

X7R

25V

63 99

21

C6850

CRITICAL

10% 10V X5R 402

0.47UF

21

C6851

402

0.47UF

X5R

10V

10%

CRITICAL

21

C6884

CRITICAL

0.47UF

10% 10V X5R 402

21

C6885

0.47UF

402

X5R

10V

10%

CRITICAL

2

1

R6813

402

MF-LF

1%

10K

1/16W

2

1

R6806

1/16W

39.2K

MF-LF 402

1%

2

1

R6805

1%

402

MF-LF

1/16W

20.0K

2

1

R6801

MF-LF

270K

5% 1/16W

402

SYNC_MASTER=K17_REF

SYNC_DATE=05/30/2009

AUDIO: JACK TRANSLATORS

HS_RST_L

GND_AUDIO_CODEC

PP3V3_S0_AUDIO_F

AUD_J1_TIPDET_R

GND_AUDIO_CODEC

PP3V3_S0_AUDIO_F

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM

VOLTAGE=3.3V

AUD_J2_TIPDET_R

AUD_IPHS_SWITCH_EN

HS_MIC_HI_R

HS_MIC_LO

AUD_J1_SLEEVEDET_INV

AUD_PORTD_DET_L

AUD_I2C_INT_L

VOLTAGE=3.3V

PP3V3_S0_HS_RX

MIN_NECK_WIDTH=0.10MM

MIN_LINE_WIDTH=0.15MM

HS_MIC_HI

AUD_MIC_INR_N

AUD_PERIPH_DET_R

AUD_J1_PERIPHDET_INV

HS_SCL HS_SDA

HS_MIC_BIAS HS_SW_DET HS_RX_BPHS_INT_L

PP3V3_S0

SMBUS_PCH_DATA

SMBUS_PCH_CLK

INT_MIC_F_P

AUD_MIC_INL_N

GND_AUDIO_CODEC

INT_MIC_F_N

AUD_MIC_INR_P

GND_AUDIO_CODEC

AUD_CODEC_MICBIAS

GND_AUDIO_CODEC

AUD_J1_SLEEVEDET_R

PP3V3_S0_AUDIO_F

AUD_J2_DET_RC

GND_AUDIO_CODEC

PP3V3_S0_AUDIO_F

PP3V3_S0

GND_AUDIO_CODEC

AUD_MIC_INL_P

AUD_J1_PERIPHDET_R

PERIPHDET_FILT

GND_AUDIO_CODEC

AUD_INJACK_INSERT_L

AUD_SENSE_A

AUD_J1_SLEEVEDET_R

INT_MIC_BIAS

INT_MIC_RET

AUD_IP_PERIPHERAL_DET

PP3V3_S0_AUDIO_F

GND_AUDIO_CODEC

AUD_J1_DET_RC

AUD_PORTG_DET_L

AUD_OUTJACK_INSERT_L

AUD_SENSE_A

68 OF 132 64 OF 103

59 60 61 64

64

59 60 61 64

64

6 7 8

25 26 27 28 30 34 37 40 42 47 48

49 52 53 55 59 63 64 69 70 71 72 73 74

81 84 85 86 88 99

101

59 60 61 64

64

59 60 61 64

64

6 7 8

25 26 27 28 30 34 37 40 42 47

48 49 52 53 55 59 63 64 69 70 71 72 73

74 81 84 85 86 88 99

101

59 60 61 64

63

59 60 61 64

63 64

59 60 61 64

IN

BI

OUT

Y

B

A

IN

VCC

EXT INT

NC

GND

NC

IN

BI

IN

D

G S

G

S

D

L1 L2

SYNC

MODE/

FREQ

FB

ITH

INTVCC

GND

GATE

RUN

VIN

SENSE

BI

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

353S2800

Vout = 3.426V

Vout = 1.230V * (1 + Ra / Rb)

<Ra>

<Rb>

350mA max output

MagSafe DC Power Jack

3.425V "G3Hot" Supply

Supply needs to guarantee 3.31V delivered to SMC VRef generator

SIG

518S0694

518S0720

GND

PWR

1-Wire OverVoltage & ESD Protection

BIL Connector

Battery Connector

6

46 49 65 66 97

1206-1

F6905

CRITICAL

21

6AMP-24V

0.01UF

603

C6905

CERM

20%

2

1

50V

46 47

6

46 47

2

1

0.001UF

CERM

402

10% 50V

C6954

2

1

C6953

50V

5% CERM

47PF

402

C6952

2

1

50V

5%

CERM

402

47PF

0.001UF

2

1

C6955

10% 402

50V CERM

3

5

4

2

1

CRITICAL

78048-0573

M-RT-SM

J6900

M-RT-SM

4

9

8

6

5

3

2

13

12

11

10

15

14

CRITICAL

7

1

J6950

GS731301047E7H

PLACE_NEAR=J6950.6:5mm

CRITICAL

SC-75

D6950

3

2

1

RCLAMP2402B

F-RT-SM

J6995

CRITICAL

5

4

3

2

1

FF18-5A-R11AD-B-3H

0.001UF

402

2

1

50V

10% CERM

C6950

CERM

C6951

402

1

2

10% 50V

0.001UF

1/16W

R6929

1

2

2.0K

MF-LF 402

5%

4

5

3

1

2

U6901

TC7SZ08AFEAPE

SOT665

10V

20%

402

CERM

0.1UF

C6908

PLACE_NEAR=U6901.5:3mm

1

2

46 47 66

MAX9940

1

U6900

SC70-5

3

45

2

CRITICAL

NO STUFF

SC-75

RCLAMP2402B

CRITICAL

2

1

3

D6900

6

46 49 65 66 97

6

46 49 65 66 97

46 47

1%

100K

R6900

1

1/16W MF-LF 402

2

NO STUFF

R6912

2

MF-LF

5%

100K

1/16W 402

1

Q6910

SOD-VESM-HF

3

1

2

SSM3K15FV

2

805

1%

MF

1/3W

47

1

R6905

10%

10UF

25V

C6900

X5R 805

1

2

3

1

2

SOT-323

BAT30CWFILM

D6905

CRITICAL

2

1

805

C6901

10V X5R

10%

4.7UF

MF-LF

1% 1/16W

80.6K

R6901

402

2

1

10%

12

402

C6902

0.0047UF

CERM

25V

107K

R6902

1

2

402

1/16W

1% MF-LF

10K

5% 1/16W MF-LF

R6903

402

2

1

Q6991

SOT23

3

2

1

CRITICAL

FDN337N-G

1206

12

C6903

20%

4.7UF

CERM

25V

50V

NP0-C0G

5%

C6904

402

2 1

470PF

1/16W MF-LF

R6904

402

21

191K

1%

10UH

SDQ25

4

3

2

1

L6991

CRITICAL

CASE-B3-SM1

2

1

CRITICAL

C6907

47UF

20%

6.3V POLY

DFLS120LXG

1 2

POWERDI-123

CRITICAL

D6907

4.7UF

20%

6.3V

X5R-CERM

1

C6906

402

2

1 2

POWERDI-123

CRITICAL

D6906

DFLS130

U6991

LTC1871

10

9

1

7

6

8

2

5

3

4

MSOP

CRITICAL

1

2

402

1%

274K

MF-LF

1/16W

R6906

6

46 49 65 66 97

SYNC_MASTER=K17_REF

SYNC_DATE=04/29/2009

DC-In & Battery Connectors

PPVIN_G3H_P3V42G3H

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.3 mm VOLTAGE=18.5V

PP3V42_G3H

P3V42G3H_EN

P3V42G3H_ITH_RC

P3V42G3H_SENSE

P3V42G3H_FREQ

DIDT=TRUE

MIN_NECK_WIDTH=0.3 mm

MIN_LINE_WIDTH=0.3 mm

SWITCH_NODE=TRUE

VOLTAGE=3.42V

P3V42G3H_SW

PPVBAT_G3H_CONN

PP3V42_G3H

MIN_NECK_WIDTH=0.20mm VOLTAGE=18.5V

PP18V5_DCIN_FUSE

MIN_LINE_WIDTH=1mm

PPDCIN_G3H

SYS_ONEWIRE

SMC_BC_ACOK

SMC_BC_ACOK_BUF

ADAPTER_SENSE

SMC_BATT_ULP_L

PP3V42_G3H

SMC_BIL_BUTTON_L

SMBUS_SMC_BSA_SDA

GND

SYSTEM_DETECT_L

SMBUS_SMC_BSA_SCL

PPDCIN_G3H

MIN_NECK_WIDTH=0.3 mm VOLTAGE=18.5V

MIN_LINE_WIDTH=0.3 mm

PPDCIN_S5_P3V42G3H

PPVBAT_G3H_CONN

MIN_NECK_WIDTH=0.4 mm

MIN_LINE_WIDTH=0.6 mm VOLTAGE=8.4V

SMBUS_SMC_BSA_SDA

P3V42G3H_INTVCC

P3V42G3H_GATE

P3V42G3H_FB

P3V42G3H_ITH

69 OF 132 65 OF 103

6 7

17 21 23 43 45 46 47 48 49

50 51 54 65 66 74

6

65 66

6 7

17 21 23 43 45 46 47 48

49 50 51 54 65 66 74

6

6 7

65 66

6

6 7

17 21 23 43 45 46 47 48 49

50 51 54 65 66 74

6 7

65 66

6

65 66

OUT

IN BI

OUT

AMON BMON ACOK

LGATE

PHASE

BOOT

SGATE AGATE

CSIP CSIN

DCIN

VNEG CSOP CSON

THRM_PAD

PGND

VDDP

VDD

BGATE

UGATE ICOMP VCOMP

ACIN

SDA VFRQ CELL

VHST

SCL

SMB_RST_N

IN

D

G

S

D1

D3

D4

S3 S2

GATE

S1

D2

D1

D3

D4

S3 S2

GATE

S1

D2

IN

D

G

S

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

TO/FROM BATTERY

Reverse-Current Protection

sparkitecture requirements

Input impedance of ~40K meets

Divider sets ACIN threshold at 13.55V

ACIN pin threshold is 3.2V, +/- 50mV

Float CELL for 1S

(PPVBAT_G3H_CHGR_R)

(CHGR_CSO_N)

(PPVBAT_G3H_CHGR_R)

353S2392

36V/V

(AGND)

(CHGR_SGATE)

(CHGR_CSO_P)

(GND)

f = 400 kHz

Max Current = 15A

(OD)

20V/V

TO SYSTEM

(CHGR_AGATE)

Inrush Limiter

(CHGR_DCIN)

(L7030/L7031 limit)

30mA max load

FROM ADAPTER

(CHGR_BGATE)

1% MF-LF

1/16W 402

R7011

1

2

9.31K

2

1

C7042

10%

402

10V CERM

0.068UF

10% 402

CERM

50V

470PF

C7016

1

2

R7016

3.01K

1/16W MF-LF

1

402

2

1%

10% 50V

CERM

402

C7015

1

2

470PF

5%

220K

2

1

R7015

MF-LF

1/16W 402

1UF

402

X5R

10% 10V

1

2

C7002

2

1

C7000

10V

10%

1UF

402-1

X5R

R7001

402

5%

MF-LF

4.7

1/16W

21

30.1K

1% MF-LF

1/16W

1

2

R7010

402

1

2

16V

0.01uF

CERM

402

10%

C7057C7056

402

2

1

16V

0.1UF

X5R

10%

SM

XW7000

1 2

PLACE_NEAR=U7000.29:1mm PLACE_NEAR=U7000.22:1mm

10V X5R

1UF

10%

402

C7001

1

2

10%

402

X5R

25V

0.1UF

1

2

C7021C7022

0.1UF

25V X5R 402

10%

1

2

CERM

10V

10%

C7020

1

2

0.047UF

402

C7025

1

2

402

CERM

10V

10%

0.22UF

RJK0305DPB

LFPAK-HF

Q7035

5

4

1 2 3

CRITICAL

1/16W

5%

1 2

402

MF-LF

10

R7022

1 2

10

MF-LF

1/16W

R7021

402

5%

LFPAK-HF

5

4

1 2 3

CRITICAL

Q7030

RJK0305DPB

22UF

CASE-D2-SM

20%

CRITICAL

25V POLY-TANT

C7030

1

2

CRITICAL

20%

22UF

25V CASE-D2-SM

POLY-TANT

C7031

1

2

X5R

25V

C7035

10%

1UF

603-1

1

2

16V

CRITICAL

POLY-TANT

20%

C7040

33UF

CASED2E-SM

2

1

8AMP-24V

CRITICAL

F7040

2

1206

1

21

R7051

5%

1/16W

402

MF-LF

2.2 0

1/16W

402

R7052

15%2

MF-LF

25V X5R

C7036

10%

1UF

603-1

1

2

1

R7086

402

1/16W MF-LF

332K

1%

2

1

603-1

1UF

C7055

10% 25V X5R

2

1

62K

5%

402

MF-LF

1/16W

R7081

2

1

25V

CERM

805

0.22UF

20%

C7005

50

6

46 49 65 97

6

46 49 65 97

2

1

C7011

10%

402

CERM

0.01UF

16V

402

2

1

C7050

16V X5R

10%

1UF

10%

402

CERM

0.001UF

50V

1

2

C7026

46 47 65

0612

1W

1%

CRITICAL

2

MF

3

1

4

0.005

R7050

CRITICAL

0612

0.5% MF-LF

123

4

1W

0.020

R7020

CRITICAL

LFPAK-HF

5

4

1 2 3

RJK0305DPB

Q7031

5

4

1 3

CRITICAL

2

LFPAK-HF

RJK0305DPB

Q7036

CASE-D2-SM

22UF

CRITICAL

25V POLY-TANT

C7032

1

2

20% 20%

CRITICAL

25V CASE-D2-SM

POLY-TANT

C7033

1

2

22UF

50V

0.001UF

10%

402

X7R

C7037

1

2

L7031

SM

1 2

CRITICAL

2.2UH-20A-5.5M-OHM

NO STUFF

C7039

0.001UF

X7R 402

10% 50V

1

2

10

NO STUFF

5%

MF-LF

1

2

603

1/10W

R7039

CRITICAL

L7030

2.2UH-20A-5.5M-OHM

SM

1 2

1206

1 2

8AMP-24V

CRITICAL

F7041

CASED2E-SM

2

1

C7041

33UF

20%

CRITICAL

POLY-TANT

16V

0.001UF

X7R 402

10% 50V

C7045

1

2

27

11

23

13

12

U7000

TQFN

3

1

9 15

25

6

28

17

18

2

5

21

22

10

26

19

20

4

8

14

29

7

16

ISL6259HRTZ

24

CRITICAL

MF-LF

1/16W 402

5%

100K

R7002

1

2

NO STUFF

74

CRITICAL

SI7137DP

SO-8

Q7055

5

4

1 2 3

100

1/16W MF-LF

402

1%

R7013

1

2

CRITICAL

BAT30CWFILM

SOT-323

D7005

1

2

3

Q7085

CRITICAL

2

SOI

5

6

7

8

4

1

3

HAT1128R01

SOI

Q7080

5

6

7

8

4

1

2

3

CRITICAL

HAT1128R01

0.1UF

2

X5R

1

402

25V

10%

C7085

1

2

402

MF-LF

1/16W

100K

5%

R7080 R7085

470K

2

1

402

MF-LF

1/16W

1%

MF-LF

5%

1/16W

402

20

R7003

PLACE_NEAR=Q7055.4:1mm

3

U7090

ASMCC0178

SOT-363

251

46

CRITICAL

1 2

5%

1/16W MF-LF

402

R7092

1K

5%

1/16W MF-LF

402

1 2

220K

R7093

MF-LF

402

5%

1/16W

1 2

1K

R7094

PLACE_NEAR=U7090.5:1mm

2

1

402

50V CERM

C7090

5%

100PF

1

1/16W

2

R7090

20K

5% MF-LF

402

6

46 47 48

1 2

402

R7000

0

5%

MF-LF

1/16W

CRITICAL

SI7137DP

Q7056

4

5

21

SO-8

3

1M

1% MF-LF

1/16W

R7058

1

2

402

R7059

MF-LF

1/16W

5%

1

2

402

20K

10%

C7058

2

1

402

1UF

X5R

10V

SYNC_DATE=04/29/2009

SYNC_MASTER=K17_REF

PBus Supply & Battery Charger

PP5V1_CHGR_VDD

MIN_LINE_WIDTH=0.2 mm VOLTAGE=5.1V

MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

GATE_NODE=TRUE

CHGR_UGATE

MIN_NECK_WIDTH=0.4 mm

MIN_LINE_WIDTH=0.6 mm VOLTAGE=8.4V

PPVBAT_G3H_CHGR_REG

CHGR_CSO_P CHGR_BGATE

CHGR_ACIN

PP3V42_G3H

CHGR_CSO_N

VOLTAGE=0V

MIN_NECK_WIDTH=0.2 mm

GND_CHGR_AGND

MIN_LINE_WIDTH=0.2 mm

PPVBAT_G3H_CONN

GATE_NODE=TRUE

DIDT=TRUE

CHGR_LGATE

CHGR_CSI_N

CHGR_AGATE

MIN_NECK_WIDTH=0.3 mm

MIN_LINE_WIDTH=0.3 mm

CHGR_AGATE_DIV

MIN_LINE_WIDTH=0.6 mm

PPDCIN_G3H_OR_PBUS

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.4 mm

CHGR_DCIN_R

CHGR_SGATE_DIV

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.3 mm

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

PP5V1_CHGR_VDDP

VOLTAGE=5.1V

PPDCIN_G3H_INRUSH

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=18.5V

CHGR_VNEG

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=8.4V

CHGR_PHASE_MID

PPBUS_G3H

CHGR_CSI_R_P

CHGR_CSI_R_N

CHGR_VCOMP_R

CHGR_AMON

PPDCIN_G3H_CHGR

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=18.5V

CHGR_VNEG_R

CHGR_VCOMP

CHGR_ICOMP

CHGR_CSI_P

CHGR_CELL

CHGR_VFRQ

SMBUS_SMC_BSA_SDA

DIDT=TRUE

CHGR_PHASE_RC

CHGR_CSO_R_P

SMC_BC_ACOK

CHGR_BMON

CHGR_DCIN

CHGR_CSO_R_N

CHGR_OVP_B

CHGR_OVP_A

SMBUS_SMC_BSA_SCL

DIDT=TRUE

CHGR_BOOT

CHGR_RST_L

SMC_RESET_L

CHGR_SGATE

DIDT=TRUE

SWITCH_NODE=TRUE

CHGR_PHASE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

CHGR_BGATE_R

GND

CHGR_OVP_G_C

PPVBAT_G3H_FET

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=8.4V

BATT_POS_GATE

PPVBAT_G3H_CHGR_R

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=8.4V

PPDCIN_G3H

70 OF 132 66 OF 103

97

6 7

17 21 23 43 45 46 47 48

49 50 51 54 65 74

97

6

65

97

6 7 8

40 50 67 68 70 71

83 87

99

97

50 99

6 7

65

OUT

IN IN

EN

EN2EN1

DRVL2

SKIPSEL1 SKIPSEL2

DRVL1

V5SW

VBST2VBST1

VREG5

VREF2

VIN

THRM_PAD

SW2SW1

RF

PGOOD2PGOOD1

GND

DRVH2DRVH1

CSP2 CSN2CSN1

COMP2COMP1

VREG3

VFB1 VFB2

OCSEL

MODE

CSP1

S

D

G

D

S

G

D

S

G

D

S

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

F=400KHZ

Vout = 5.0V 12A MAX OUTPUT

100mA MAX OUTPUT

Vout = 5V

9A MAX OUTPUT

Vout = 3.3V

F=400KHZ

.

353S2678

C7200

603-1

X5R

1UF

25V

10%

2

1

21

L7260

IHLP2525CZ-SM1

2.2UH-14A

CRITICAL

1UF

X5R

10%

C7241

1

2

16V 402

10%

0.1UF

50V X7R

603-1

C7264

1

2

C7290

10UF

6.3V

20%

603

X5R

1

2

10%

0.1UF

603-1

X7R

50V

C7224

1

2

330UF

CRITICAL

6.3V

20%

CASE-D3L-SM1

POLY-TANT

1

2

C7252

10UF

10V

20%

X5R 805

C7250

1

2

1

2

C7281

1UF

10% 25V X5R 603-1

CRITICAL

21

PIMB103T4R7MS-SM

4.7UH-13A-22.5MOHM

L7220

1UF

6.3V CERM

10%

1

2

402

C7203

6.3V

603

X5R

20%

10UF

C7205

1

2

R7206

249K

402

MF-LF

1% 1/16W

1

2

74

PLACE_NEAR=L7260.2:3mm

SM

XW7261

1

2

1

C7201

10V

10%

CERM

0.22UF

402

1/16W

402

MF-LF

1%

23.2K

R7260

1

2

1%

MF-LF 402

1/16W

10K

R7261

1

2

1%

40.2K

402

MF-LF

1/16W

R7220

1

2

10K

MF-LF 402

1/16W

1%

R7221

1

2

1

2

CASE-D2E-SM

68UF

POLY-TANT

16V

CRITICAL

20%

C7280

CRITICAL

C7240

68UF

1

2

CASE-D2E-SM

POLY-TANT

16V

20%

SM

PLACE_NEAR=U7201.28:1mm

1 2

XW7200

4.02K

2

1

R7216

1/16W MF-LF 402

1%

0.1UF

X5R402

21

C7288

25V10%

1.27K

21

R7246

1% 1/16W MF-LF

402

PLACE_NEAR=L7260.1:3mm

SM

XW7260

1

2

1 2

16V

10%

0.1UF

402 X5R

C7218

21

3.16K

MF-LF

1%

R7247

1/16W

402

1/16W

1

2

402

8.87K

R7256

1%

MF-LF

PLACE_NEAR=L7220.1:3mm

XW7220

1

2

SM

PLACE_NEAR=L7220.2:3mm

XW7221

1

2

SM

6.04K

402

2

1

R7236

MF-LF

1% 1/16W

NO STUFF

20.0K

1%

402

1/16W MF-LF

R7237

1

2

X7R

2

1

10%

C7236

0.047UF

16V

402

5%

CERM

402

50V

100PF

C7237

1

2

PLACE_NEAR=L7260.2:3mm

SM

XW7262

1

2

PLACE_NEAR=L7220.1:3mm

SM

XW7222

1

2

CRITICAL

6.3V

20%

CASE-D3L-SM1

330UF

POLY-TANT

C7292

1

2

NO STUFF

1/16W MF-LF

20.0K

1%

402

1

R7239

C7239

CERM

402

5%

100PF

50V

1

2

402

MF-LF

6.04K

2

1

R7238

1/16W

1%

C7238

1

0.047UF

X7R

16V

2

10%

402

74 74

5%

NO STUFF

R7248

0

402

MF-LF

1/16W

1 2

R7249

MF-LF

1/16W

402

0

5%

1

2

C7299

50V

NO STUFF

CERM

0.0033UF

402

10%

1

2

NO STUFF

R7299

1

1/10W

603

1

MF-LF

2

5%

50V

0.001UF

X7R 402

10%

NO STUFF

C7298

1

2

1

R7298

10

5%

1/10W

603

MF-LF

NO STUFF

50V

0.001UF

X7R 402

10%

C7272

1

2

1

10% 402

X7R

0.001UF

50V

C7283C7270

0.001UF

50V X7R 402

10%

1

2

402

0.001UF

X7R

50V

10%

C7271

1

5

QFN

CRITICAL

U7201

10

8

17

7

18

1

24

30

27

12

4

21

28

11

20

3

6

32

25

33

2

31

26

9

16

23

13

22

29

15

TPS51980

14

19

5

123

4

CRITICAL

RJK0332DPB-01

LFPAK-SM

Q7220

Q7225

PWRPK-12128

SIS426DN

CRITICAL

4

13 2

5

4

1 32

5

PWRPK-12128

CRITICAL

Q7260

SIS426DN

241 3

PWRPK-12128

CRITICAL

SIS426DN

Q7261

5

POLY-TANT

CASE-D2E-SM

1

2

68UF

16V

20%

C7242

CRITICAL

1

2

CASE-D2E-SM

68UF

POLY-TANT

16V

CRITICAL

20%

C7282

402

R7245

1/16W MF-LF

5%

0

21

R7251

1

2

402

MF-LF

1/16W

0

5%

PLACE_NEAR=U7201.4:2mm

5%

0

1/16W MF-LF

R7252

402

2

1

PLACE_NEAR=U7201.21:2mm

21

R7264

402

0

5%

MF-LF

1/16W

74

SYNC_DATE=03/26/2009SYNC_MASTER=K20A_MLB

5V / 3.3V Power Supply

GND_P5VP3V3_SGND

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V

P3V3S5_EN_R

P3V3S5_PGOOD

P5VS3_FUNC

P5VS3_EN_R

P5VS3_PGOOD

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

P5VS3_DRVH

GATE_NODE=TRUE

P5VS3_CSP1 P5VS3_CSN1

P5VP3V3_VREG3

P5VS3_VFB1

P3V3S5_VFB2

P3V3S5_CSN2

P3V3S5_CSP2

MIN_LINE_WIDTH=0.6 mm

GATE_NODE=TRUE

P3V3S5_DRVL

MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

PPBUS_G3H

P5VP3V3_VREG3

P3V3S5_COMP2

P3V3S5_RF

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

P3V3S5_VBST

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

P3V3S5_LL

SWITCH_NODE=TRUE

P3V3S5_EN

PP5V_S3_ISNS_R

P3V3S5_LL_RC

DIDT=TRUE

P3V3S5_VFB2_R

P5VS3_VFB1-R

P3V3S5_COMP2_R

P5VP3V3_VREF2

P5VS3_COMP1_R

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

P5VS3_DRVL

DIDT=TRUE

GATE_NODE=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

P5VS3_VBST_R

P5VS3_VBST

P5VS3_LL_RC

DIDT=TRUE

P5VS3_EN

P3V3S5_VBST_R

P3V3S5_DRVH

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

GATE_NODE=TRUE

P3V3S5_CSP2_R

PP3V3_S5_ISNS_R

P5VP3V3_VREF2

P5VS3_CSP1_R

P5VP3V3_VREF2

PP5V_S5

P5VS5_EN

PP5V_S3_ISNS_R

P5VS3_COMP1

DIDT=TRUE

SWITCH_NODE=TRUE

P5VS3_LL

72 OF 132 67 OF 103

67

6 7 8

40

50 66 68

70 71 83

87

67

7

51 67

67

7

51

67

7

23 57 73

102

7

51 67

MODE

VDDQSNS

COMP

NC0 NC1

VTTSNS

VTT

VTTREF

PGOOD

S3 S5

VTTGND

THRM_PAD

GND

CS_GND

PGND

CS

LL

DRVL

DRVH

VDDQSET

VBST

VLDOINV5FILT

V5IN

SYM (2 OF 2)

IN IN OUT

NC NC

S

D

G

S

D

G

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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REVISION

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SIZE

D

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PAGE TITLE

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A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

VDDQ PGOOD

VDDQ/VTTREF Enable

(Q7335 limit)

18A MAX OUTPUT

Vout = 1.50V

f = 400 kHz

(DDRREG_DRVH)

(DDRREG_LL)

(DDRREG_DRVL)

(DDRREG_CSGND)

Vout = VTTREF

(DDRREG_FB)

Vout = VDDQSNS/2

(DDRREG_VDDQSNS)

10mA max load

VTT Enable

353S1491

<Ra>

<Rb>

Vout = 0.75V * (1 + Ra / Rb)

21

C7325

603-1

X7R

50V

10%

0.1UF

R7320

2

1

402

1%

15.0K

1/16W MF-LF

2

1

R7321

1/16W MF-LF

1%

402

15.0K

1

C7332

1UF

10% 25V

603-1

2

X5R

2

7

CRITICAL

5

1

24

23

8

9

22

15

14

25

11

10

13

18

12

4

20

3

19

21

17

16

6

U7300

QFN

TPS51116

2

1

C7305

10% X5R

10V

1UF

402

21

R7305

402

4.7

5% 1/16W MF-LF

2

1

C7361

22UF

6.3V

20%

CRITICAL

X5R-CERM 603

2

1

C7360

X5R-CERM

6.3V

20% 603

22UF

CRITICAL

21

XW7360

SM

PLACE_NEAR=C7361.1:3mm

21

XW7335

SM

PLACE_NEAR=Q7335.1:3mm

2

1

C7350

0.033UF

10% X5R

16V 402

8

31

2

1

C7300

4.7UF

20%

603

CERM

6.3V

74

2

1

R7310

6.81K

1/16W

402

MF-LF

1%

74

21

L7330

CRITICAL

1.0UH-20A

IHLP4040DZ11-SM

PLACE_NEAR=L7330.2:3mm

XW7345

2

1

SM

2

1

C7355

20% 603

6.3V X5R

10UF

2

1

XW7300

SM

PLACE_NEAR=U7300.25:2mm PLACE_NEAR=U7300.3:2mm

2

1

C7345

20%

6.3V X5R

10UF

603

X7R 402

C7333

2

1

50V

10%

0.001UF

2

1

C7346

402

X7R

10% 50V

0.001UF

C7330

CRITICAL

D-HF

2

1

16V

TANT

100UF

20%

321

4

5

Q7330

CRITICAL

CSD58850Q5A

MLP5X6-LFPAK-Q5A

321

4

5

Q7335

CSD58857Q5

MLP5X6-LFPAK-Q5

CRITICAL

1

2

POLY-TANT

16V

20%

CASE-D2E-SM

68UF

C7331

CRITICAL

2

1

C7370

NP0-C0G

1000PF

NO STUFF

402

25V

5%

2

1

R7370

1/10W MF-LF

NO STUFF

1

5%

603

21

R7325

0

402

5% 1/16W MF-LF

4 2

3 1

CRITICAL

R7350

0.001

1%

0612

MF-1

1W

51 99

C7341

3 2

1

2.0V

20% POLY-TANT

D2T-SM2

330UF

C7340

3 2

1

330UF

20%

2.0V POLY-TANT D2T-SM2

SYNC_DATE=06/24/2009

SYNC_MASTER=K17_REF

1.5V DDR3 Supply

PP0V75_S0_DDRVTT

DDRREG_FB

DDRREG_CSGND

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

TP_DDRREG_PGOOD

PP5V_S3

PPVTTDDR_S3

DDRREG_VTTSNS

DDRREG_EN

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

SWITCH_NODE=TRUE

DDRREG_LL

DIDT=TRUE

DDRREG_LL_RC

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

DDRREG_DRVL

GATE_NODE=TRUE

DDRREG_VBST

DDRREG_VBST_R

DIDT=TRUE

GATE_NODE=TRUE

DDRREG_DRVH

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

DDRREG_CS

VOLTAGE=0V

GND_DDRREG_SGND

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

MEMVTT_EN

DDRREG_VDDQSNS

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

ISNS_1V5_S3_P

ISNS_1V5_S3_N

PP1V5_S3

VOLTAGE=1.5V

PPDDR_S3_REG_R

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

PP1V5_S3

PP5V_S3_DDRREG_V5FILT

VOLTAGE=5V

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

PPBUS_G3H

73 OF 132 68 OF 103

7

28 30 31

32

6 7

31 33 43 44 45 47 51 55 73 83

103

6 7

32

7

28 30 31 68 73

7

28 30 31 68 73

6 7 8

40 50 66 67 70 71 83 87

D

S

G

D

S

G

D

G

S

D

G

S

OSRSEL

TRIPSEL

IMON

TONSEL

PGND

GND

THRM

CSP2 CSN2

CSN1

SLEW

CSP1

VID5 VID6

VID3 VID4

VID2

VID0 VID1

VREF

VSNS GNDSNS

DROOP

PSI*

CLK_EN*

DRVL2

PGOOD

LL2

DRVH2

VBST2

DRVL1

LL1

VBST1 DRVH1

V5IN

V5FILT

VR_ON

DPRSLPVR

MODE

THERM

VR_TT*

PAD

IN

IN IN

IN

OUT OUT

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

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PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

BOM TABLE

K = (R7417 || (R7418 + R7419)) / (R7417 || (R7418 + R7419) + R7416) = 0.787

50 A = 1.049 V

Loadline = DCR * K * 5.95 / (R7403 * 2uA/mV)

Loadline = 1.83 mohm

VIMON = Io * DCR * K * 2uA/mV * R7450

BOM: 150K 402

48A max current

(CPUIMVP_PHASE2)

BOM: 150K 402

(CPUIMVP_PHASE1)

353S2942

1

10%

0.22UF

CERM

10V

2

402

C7402

C7403

5%

33PF

1 2

50V

CERM

402

5.11K

1 2

402

MF-LF

1/16W

1%

R7403

1/16W

1

2

402

12.7K

MF-LF

1%

R7450

10% CERM

50V

C7450

1

2

402

0.0033UF

0.022UF

CERM-X5R

16V 402

21

10%

C7420

R7416

23.7K

1

2

402

MF-LF

1/16W

1%

162K

402

21

1/16W

1%

MF-LF

R7417

R7419

402

21

1%

41.2K

1/16W MF-LF

R7418

2 1

0402

150KOHM-5%

R7429

MF-LF

1/16W

1%

1 2

402

41.2K

162K

1

402

R7427

2

MF-LF

1/16W

1%

0.022UF

CERM-X5R

16V

C7430

402

21

10%

23.7K

MF-LF

1%

R7426

402

2

1

1/16W

12

R7428

0402

150KOHM-5%

SM

2 1

XW7400

C7440

NONE NONE

NOSTUFF

NONE

OMIT

402

1

2

C7441

OMIT

NONE

NOSTUFF

NONE

402

1

2

OMIT

C7442

NONE NONE

NOSTUFF

NONE 402

1

2

OMIT

NONE NONE

NONE 402

1

2

NOSTUFF

C7443

402

0

5% 1/16W MF-LF

R7430

1

2

MF-LF

1/16W

5%

0

402

2

1

R7431

R7421

0

5% 1/16W MF-LF

402

2

1

402

0

5% 1/16W MF-LF

2

1

R7422

402

10% X7R

50V

C7425

1

2

0.001UF

1

2

CRITICAL

CASE-B2

C7416

11V

ELEC

20%

62UF

PLACE_NEAR=Q7490.5:8mm

CASE-B2

CRITICAL

20%

C7415

2

1

ELEC

11V

PLACE_NEAR=Q7490.5:8mm

62UF

C7409

CRITICAL

20%

62UF

ELEC

11V

2

1

PLACE_NEAR=Q7490.5:8mm

CASE-B2

CRITICAL

11V

62UF

C7407

2

1

ELEC

20%

CASE-B2

PLACE_NEAR=Q7490.5:8mm

62UF

20%

CASE-B2

C7406

1

PLACE_NEAR=Q7490.5:8mm

ELEC

11V

2

CRITICALCRITICAL

ELEC

CASE-B2

2

1

PLACE_NEAR=Q7490.5:8mm

11V

20%

62UF

C7404

R7445

100K

1/16W

1

2

402

MF-LF

5%

DIRECTFET-MA

IRF6723M2DPBF

Q7490

CRITICAL

78

1

2

IRF6723M2DPBF

Q7490

CRITICAL

DIRECTFET-MA

56

4

3

DIRECTFET-MX

62 7

43

5

IRF6795

1

Q7415

CRITICAL

CPUIMVP_PHASE1_NC

DIRECTFET-MX

621 7

43

5

CRITICAL

IRF6795

Q7425

PLACE_NEAR=Q7490.5:8mm

CRITICAL

11V

ELEC

20%

62UF

C7405

CASE-B2

2

11

2

CASE-D2E-SM

PLACE_NEAR=Q7490.5:8mm

C7408

20%

POLY-TANT

CRITICAL

68UF

16V

402

2

1

R7441

0

5% 1/16W MF-LF

NO STUFF

R7442

1

2

402

MF-LF

1/16W

5%

0

PMEG2010AEB

1

2

SOD523

NO STUFF CRITICAL

D7401

1

2

SOD523

NO STUFF CRITICAL

D7400

PMEG2010AEB

32

31

11

36

25241

3 4

5

37

6

15 14

17 16

18

20 19

40

8 7

39

13

34

27

33

28

30

29

24

23

22 21

26

38

35 12

1

9 10

QFN

CRITICAL

U7400

TPS51983

SM

2

XW7427

1

PLACE_NEAR=L7425.2:4mm

2

PLACE_NEAR=L7415.2:4mm

SM

1

XW7417

C7414

X5R25V10%

21

603-2

1UF

68UF

20%

C7410

CASE-D2E-SM

POLY-TANT

CRITICAL

16V

PLACE_NEAR=Q7490.5:8mm

1

2

X5R

25V

2

10%

1

805

PLACE_NEAR=Q7490.5:8mm

C7411

10UF

XW7426

1

2

PLACE_NEAR=L7425.1:4mm

SM

PLACE_NEAR=L7415.1:4mm

2

1

SM

XW7416

C7421

10% X5R

25V 805

1

2

PLACE_NEAR=Q7490.7:8mm

10UF

2

20%

2.2UF

X5R-CERM

10V 402

1

C7401

0.001UF

2

1

10% 50V

402

X7R

PLACE_NEAR=Q7490.5:8mm

C7412

10%

0.001UF

1

C7422

50V X7R 402

PLACE_NEAR=Q7490.7:8mm

2

8

20%

C7413

POLY-TANT

1

2

16V

PLACE_NEAR=Q7490.5:8mm

CASE-D2E-SM

68UF

CRITICAL

MF-LF

12

5%

1/16W

R7414

402

0

21

PIMA104E-SM

0.36UH-20%-40A-0.00075OHM

L7425

CRITICAL

OMIT

PIMA104E-SM

1 2

0.36UH-20%-40A-0.00075OHM

L7415

CRITICAL

12 91

12 69 91

12 15 91

46

C7424

1

603-2

10%

1UF

25V X5R

2

0

MF-LF1/16W

5%

402

2 1

R7424

10 47 91

12 50 91

5%

1/16W

R7440

0

402

MF-LF

2 1

26

27

MF-LF

402

2

1

249K

1%

1/16W

R7400

C7400

805

1

2

10V X5R

10%

4.7UF

2

CRITICAL

152S1177

L7415,L7425

IND,PWR,0.36uH,1.05MO,12x10x4mm

SYNC_DATE=06/29/2009

CPU IMVP VCore Regulator

SYNC_MASTER=K18_POWER

MIN_LINE_WIDTH=0.25 mm

PP5V_S0_CPUIMVP_V5FILT

VOLTAGE=5V

MIN_NECK_WIDTH=0.2 mm

CPUIMVP_TRIPSEL

CPUIMVP_IMON

CPUIMVP_VREF

MIN_NECK_WIDTH=0.15 mm VOLTAGE=0V

MIN_LINE_WIDTH=0.6 mm

CPUIMVP_AGND

CPUIMVP_ISEN2P CPUIMVP_ISEN2N

CPUIMVP_ISEN1N

CPUIMVP_SLEW

CPUIMVP_ISEN1P

CPUIMVP_VID<5> CPUIMVP_VID<6>

CPUIMVP_VID<3> CPUIMVP_VID<4>

CPUIMVP_VID<2>

CPUIMVP_VID<0> CPUIMVP_VID<1>

CPU_VCCSENSE_P CPU_VCCSENSE_N

CPUIMVP_DROOP

CPU_PSI_L

CPUIMVP_CLK_EN_L

CPUIMVP_LGATE2

DIDT=TRUE

GATE_NODE=TRUE

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

CPUIMVP_PGOOD

SWITCH_NODE=TRUE

DIDT=TRUE

MIN_LINE_WIDTH=1.5 MM

CPUIMVP_PHASE2

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

CPUIMVP_UGATE2

DIDT=TRUE

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 MM

CPUIMVP_BOOT2

CPUIMVP_LGATE1

DIDT=TRUE

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

GATE_NODE=TRUE

CPUIMVP_PHASE1

MIN_LINE_WIDTH=1.5 MM

DIDT=TRUE

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2 MM

CPUIMVP_BOOT1 CPUIMVP_UGATE1

GATE_NODE=TRUE

MIN_LINE_WIDTH=0.5 MM

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

PP5V_S0

CPUIMVP_VR_ON PM_DPRSLPVR

CPUIMVP_NTC CPUIMVP_VR_TT_L

CPUIMVP_BOOT1_RC

CPUIMVP_BOOT2_RC

CPU_PROCHOT_L

CPUIMVP_PHASE2_NC

MIN_LINE_WIDTH=0.25 MM

CPUIMVP_ISEN1N_R

MIN_NECK_WIDTH=0.15 MM

MIN_LINE_WIDTH=0.25 MM

CPUIMVP_ISEN1P_R

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.15 MM

CPUIMVP_ISEN1N

MIN_NECK_WIDTH=0.15 MM

MIN_LINE_WIDTH=0.25 MM

CPUIMVP_ISEN1P

MIN_NECK_WIDTH=0.15 MM

MIN_LINE_WIDTH=0.25 MM

CPUIMVP_ISEN2NCPUIMVP_ISEN2P

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.15 MM

MIN_NECK_WIDTH=0.15 MM

MIN_LINE_WIDTH=0.25 MM

CPUIMVP_PHASE2X

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.15 MM

CPUIMVP_ISEN2N_R

CPUIMVP_ISEN2P_R

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.15 MM

CPUIMVP_ISEN1_NTC

CPUIMVP_ISEN2_NTC

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.15 MM

CPUIMVP_PHASE1X

PPVCORE_S0_CPU

PP3V3_S0

CPU_VCCSENSE_N

PPBUS_CPU_IMVP_ISNS

74 OF 132 69 OF 103

69

6 7 8

23 42 48 53 55 70 71 73 87

102

69 69

6 7

12

15 50

6 7 8

25 26 27 28 30 34 37 40 42

47 48 49 52 53 55 59 63 64

70 71 72 73 74 81 84 85 86

88 99

101

12 69 91

6 7

50

PGND

GND

TRIPSEL

IMON

MODE

DPRSLPVR

VR_ON

CLK_EN*

PGOOD

DRVL

LL

DRVH

CSN

CSP

ISLEW

VID6

VID5

VID4

VID3

VID2

VID1

VID0

VREF

GNDSNS

VSNS

VBST

V5FILT

DROOP TONSEL

V5IN

THERM

VR_TT*

IMONC

IN IN IN IN IN

IN

IN IN

IN

OUT

NC

S

D

G

S

D

G

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

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PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

353S2664

(GND_GFXIMVP_AGND)

22A max output

Imon = Io x R7540 x 2uA/mV x R7515

Vout = VID controlled

(GFX_VSENSE_N)

Imon = Io x 45.2 mV/A 22A => 995mV

f = 350KHz

CRITICAL

U7500

TPS51981

QFN

28

7 6

21

27

31 30

18 5 4

32

16 15 14 13 12 11 10

29

2 3

17

19

20

23

24

25

9

22

8

26

1

33

8

13 91

1%

MF-LF

1/16W

R7513

402

21

46.4K

MF-LF

1

1%

R7511

2

402

1/16W

1.69K

5%

2

CERM

50V

33PF

1

C7511

402

R7512

2

1

402

MF-LF

1/16W

1%

1K

13 91

R7510

MF-LF

402

1/16W

1 2

0

5%

C7512

CERM

10V

10%

0.22UF

402

2

1

2.2UF

16V X5R

10%

1

2

603

C7513

MF-LF

1/16W

21

R7542

402

5%

0

21

MF-LF

1/16W

5%

0

402

R7541

SIGNAL_MODEL=EMPTY

OMIT

402

NONE

NOSTUFF

NONE

C7541

1

2

SIGNAL_MODEL=EMPTY

2

1

NONE NONE NONE

402

OMIT

NOSTUFF

C7542

SIGNAL_MODEL=EMPTY

C7515

0.0033UF

2

1

402

10% 50V

CERM

22.6K

1

1/16W MF-LF 402

2

1%

SIGNAL_MODEL=EMPTY

R7515

74

402

MF-LF

1/16W

5%

0

R7514

1

2

1UF

402

X5R

10%

C7514

1

2

16V

C7510

10%

1

2

603

X5R

16V

2.2UF

1

2

C7523

603-1

1UF

X5R

10% 25V

2

68UF

POLY-TANT

16V

CRITICAL

20%

CASE-D2E-SM

C7520

1

CRITICAL

20%

100UF

TANT

16V

D-HF

2

1

C7521

43

21

0612

MF-1

R7540

0.001

1% 1W

CRITICAL

2

C7556

10UF

X5R

20%

6.3V 603

1

D7514

2

SOT-323

3

BAT30CWFILM

PLACE_NEAR=U7500.33:1mm

2SM1

PLACE_NEAR=U7500.1:1mm

XW7500

MLP5X6-LFPAK-Q5A

CSD58850Q5A

4

321

5

CRITICAL

Q7530

4

321

5

CRITICAL

Q7535

CSD58857Q5

MLP5X6-LFPAK-Q5

2

1

402

5%

10PF

50V

C7549

CERM

402

R7516

MF-LF

1/16W

1%

150K

10% 16V

C7517

0.022UF

CERM-X5R

402

1

2

13 91

0.47UH-26A

L7530

CRITICAL

1 2

IHLP2525CZERR47M01

NP0-C0G

1000PF

25V

5%

C7570

402

1

2

NO STUFF

1/10W MF-LF

1

5%

R7570

603

2

1

NO STUFF

MF-LF

1/16W

402

R7517

1%

100K

402

R7518

MF-LF

1/16W

1%

200K

10%

C7524

1

CERM

50V

0.001UF

402

2

10%

C7557

50V CERM

0.001UF

402

1

2

GFX IMVP VCore Regulator

SYNC_MASTER=T22_MLB

SYNC_DATE=03/26/2009

PPBUS_G3H

MIN_LINE_WIDTH=0.6MM VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2MM

PPVCORE_S0_GFX_REG_R

PPVCORE_S0_GFX

GFXIMVP_CS_R_P

GFXIMVP_CS_R_N

VOLTAGE=0V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

GND_GFXIMVP_AGND

GFXIMVP_VID<0>

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

VOLTAGE=5V

PP5V_S0_GFXIMVP_V5FILT

PP5V_S0

DIDT=TRUE

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

GFXIMVP_LGATE

GFXIMVP_VBST

GFXIMVP_PHASE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE

DIDT=TRUE

PP3V3_S0

GFXIMVP_THERM

GFXIMVP_ISLEW

GFXIMVP_CS_N

GFXIMVP_VID<4>

PP3V3_S0

GFXIMVP_TONSEL

GFXIMVP_CS_P

GFXIMVP_VID<6>

GFXIMVP_VID<5>

GFXIMVP_VID<3>

GFXIMVP_VID<2>

GFXIMVP_VBST_R

GFXIMVP_DROOP

DIDT=TRUE

GFXIMVP_LL_RC

GFXIMVP_VREF

GFXIMVP_OSRSEL

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

GFXIMVP_UGATE

GATE_NODE=TRUE

GFXIMVP_VREF

GFX_VSENSE_P

GFXIMVP_VID<1>

GFX_VSENSE_N

GFXIMVP_IMON

GFXIMVP_TRIPSEL

GFX_DPRSLPVR

GFX_VR_EN

TP_GFXIMVP_PGOOD

75 OF 132 70 OF 103

6 7 8

40 50 66 67 68 71 83 87

7

13 24 50

50 99

6 7 8

23 42 48 53 55 69 71 73 87

102

6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52 53 55 59 63 64 69 70 71 72 73 74 81

84 85 86 88 99

101

99

6 7 8

25 26 27 28 30 34 37 40 42 47 48

49 52 53 55 59 63 64 69 70 71 72 73 74

81 84 85 86 88 99

101

99

70

IN

OUT

IN

NC NC NC

NC

VSNS

PGOOD

IMON

OSRSEL

TRIPSEL

ISLEW

DROOP

VREF REF

IMON2

LL

VBST

DRVH

TONSEL

CSP

CSN

GSNS

DRVL

THRM_PADPGND

GND

SLP

PG*

V5IN

V5FILT

VID1 VID2

EN

VID0

IMONC

(SYM-VER3)

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

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PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

353S2705

Imon = Io x R7640 x 2uA/mV x R7610

1.7V, 250uA max

Vout = VID controlled

1 1 0 1.0750V

-1 step

+2 steps

+1 step

VID2 VID1 VID0 Vout

0 1 1 1.1125V

0 1 0 1.0625V

<Rimon>

1 0 1 1.0875V

1 0 0 1.0375V

1 1 1 1.1250V

26A max output f = 350 kHz

30A => 2.994V

Imon = Io x 99.8mV/A

0 0 0 1.1000V 0 0 1 1.0500V

CPU VTT (1.05V S0) Regulator

Internal 3 ohm path to V5IN

12 91

51

10 91

PLACE_NEAR=U7600.1:1mm PLACE_NEAR=U7600.33:1mm

SM

12

XW7600

R7616

OMIT

NONE

NONE NONE

402

NOSTUFF

1

2

1

SIGNAL_MODEL=EMPTY

R7610

49.9K

1/16W MF-LF

2

1%

402

NO STUFF

0.0033UF

SIGNAL_MODEL=EMPTY

402

C7610

1

10%

2

50V CERM

74

16V

2.2UF

10% X5R

1

2

C7601

603

OMIT

NONE

402

NONE

NOSTUFF

NONE

C7642

1

2

5%

0

21

402

1/16W

R7642

MF-LF

RJK0328DPB

Q7636

CRITICAL

5

1 2 3

LFPAK-HF

4

CRITICAL

LFPAK-HF

Q7630

5

1 342

RJK0305DPB

0

402

5%

1/16W

R7641

2

MF-LF

1

0.6UH-30A-1.5MOHM

2

1

L7630

MPL104-SM

CRITICAL

MF-1

0.001

1% 1W

R7640

0612

2 1 4 3

1UF

C7631

402

16V

1

X5R

10%

2

402

1/16W

5%

1

0

MF-LF

R7631

2

CRITICAL

20% 16V

2

1

CASE-D2E-SM

POLY-TANT

68UF

C7620

OMIT

2

1

C7641

402

NONE

NOSTUFF

NONE

1

2

3

SOT-323

BAT30CWFILM

D7631

NO STUFF

6.3V 402

CERM-X5R

0.22UF

10%

C7619

1

2

R7615

1/16W

4.02K

1%

402

MF-LF

1

2

0.001UF

402

10% 50V

CERM

C7615

12

10%

603

X5R

16V

1

2

2.2UF

C7600

90.9K

MF-LF

1%

402

1/16W

R7614

1

2

1/16W

0

402

MF-LF

5%

R7613

1

2

21

402

R7611

23.7K

MF-LF

1%

1/16W

1%

402

MF-LF

10K

R7618

1

2

10K

1/16W

1%

402

MF-LF

R7617

1

2

10% X7R

0.001UF

50V

C7622

1

2

402

20%

6.3V

C7647

2

1

603

10UF

X5R

1K

402

21

R7612

1%

MF-LF

1/16W

0.1UF

402

C7643

16V X5R

10%

1

2

1

2

402

C7644

5%

10PF

CERM

50V

R7619

0

5% 1/16W MF-LF 402

12

16

25

14

15

30

21

24

9

1

22

33

20

4

3

2

27

17

18

19

7

6

32

31

29

26

28

8

5

10 11 13

QFN

SN0808088

U7600

23

CRITICAL

2

402

5% 25V

NO STUFF

1000PF

NP0-C0G

1

C7670

NO STUFF

603

5%

1

MF-LF

1/10W

1

2

R7670

20%

62UF

ELEC

11V CASE-B2

2

1

C7621

CRITICAL CRITICAL

20%

100UF

TANT

16V D-HF

2

1

C7623

CPUVTT (1.05V) Power Supply

SYNC_MASTER=T22_MLB

SYNC_DATE=03/26/2009

PP5V_S0

PPBUS_G3H

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

CPUVTTS0_LL

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm

PPCPUVTT_S0

CPUVTTS0_BOOT_RC

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

MIN_NECK_WIDTH=0.2 mm

PP5V_S0_CPUVTTS0_V5FILT

VOLTAGE=5V

MIN_LINE_WIDTH=0.25 mm

CPUVTTS0_VID<2>

VOLTAGE=0V

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

GND_CPUVTTS0_AGND

CPUVTT_LL_RC

DIDT=TRUE

VOLTAGE=1.05V

PPCPUVTT_S0_REG_R

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.09 mm

MIN_LINE_WIDTH=0.3 mm

CPUVTTS0_CS_R_P

MIN_NECK_WIDTH=0.09 mm

MIN_LINE_WIDTH=0.3 mm

CPUVTTS0_CS_R_N

PP3V3_S0

CPUVTTS0_DROOP_RC

CPU_VTTSENSE_P

CPUVTTS0_TRIPSEL CPUVTTS0_ISLEW

CPUVTTS0_DROOP

CPUVTTS0_VREF

CPUVTTS0_IMON2

CPUVTTS0_VBST

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

CPUVTTS0_DRVH

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE

DIDT=TRUE

CPUVTTS0_TONSEL

CPU_VTTSENSE_N

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm GATE_NODE=TRUE

DIDT=TRUE

CPUVTTS0_DRVL

CPUVTTS0_EN CPUVTTS0_VID<0>

CPUVTTS0_CS_N

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

CPUVTTS0_CS_P

PP3V3_S0

CPUVTTS0_VID<1>

CPUVTTS0_IMON

CPUVTTS0_PGOOD

TP_CPUVTTS0_PG_L

76 OF 132 71 OF 103

6 7 8

23 42 48 53 55 69 70 73 87

102

6 7 8

40 50 66 67 68 70 83 87

6 7

10 12 13 15 25 26 40 74

101

99

6 7 8

25 26 27 28 30 34 37 40 42 47

48 49 52 53 55 59 63 64 69 70 71 72

73 74 81 84 85 86 88 99

101

99

6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52 53 55 59 63 64 69 70 71 72 73 74 81

84 85 86

88

99

101

G

D

S

GND

VIN

VFB

ITH/RUN SENSE-

NGATE

IN

VIN

LX

VFB

RSI

EN

POR

SKIP

GND

THRM_PAD

NC

VIN

LX

VFB

RSI

EN

POR

SKIP

GND

THRM_PAD

IN

NC

VFB

LX

SYNCH

PG

EN

SGND

PGND

THRM_PAD

VIN

VDD

LX

NC NC NC

IN

OUT

IN

BIAS

NC

OUT

THRM

EN

PADGND

NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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REVISION

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PAGE TITLE

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Vout = 1.229V

<Rb>

Vout = 0.8V * (1 + Ra / Rb)

70mA is required to support pull-ups. Alternative is strong voltage

Pull-ups (3) must be 51 ohms to support XDP (not required in production).

Ibex Peak-M requires JTAG pull-ups to be powered at 1.05V in S5.

Vout = 0.8V * (1 + Ra / Rb)

<Ra>

Vout = 10V

Vout = 1.794V

Freq = 1.6MHZ

1.2V ENET Regulator

1.05V to 1.0V FW Drop

<Ra>

Max Current = 0.35A

Vout = 1.05V

<Rb>

Vout = 0.8V * (1 + Ra / Rb)

<Ra>

dividers (200/100) to 3.3V S5, which burns 100mW in all S-states.

<Rb>

Freq = 550KHz

FW 10V Boost Regulator

Vout = 1.508V

Vout = 0.8V * (1 + Ra / Rb)

<Ra>

Freq = 1.6MHZ

Max Current = 0.6A

<Rb>

Max Current = 2A

1.05V S5 LDO

Max Current = 0.8A

1.8V S0 Regulator

1.5V S0 Regulator

Max Current = 2A Freq = 1 MHz

PCMC063T-SM

4.7UH-10A

CRITICAL

L7795

1 2

1UF

X5R 402

10% 16V

1

2

C7794

CRITICAL

1.00M

1% 1/4W MF-LF 1206

R7795

1

2

NO STUFF

50V

5%

402

CERM

33PF

C7795

1

2

R7796

1/16W

1%

402

MF-LF

86.6K

1

2

10UF

X5R

1206

10% 16V

C7790

1

2

16V

20%

CASE-D2E-SM

POLY-TANT

68UF

C7799

1

2

SUPERSOT-6

CRITICAL

FDC796NG

Q7790

7

4

12356

1W

0.5%

0612

MF

0.02

R7790

1 2 3 4

MF-LF 402

1

2

1/16W

1%

38.3K

R7797

50V

10%

402

CERM

0.0012UF

1

2

C7797

LTC1872

SOT23-6

U7790

2

1

6

4

3

5

CRITICAL

STPS1L30MF

DO222-SM

D7790

1 2

6 7 8

25 26 27 28 30 34 37 40 42

47 48 49 52 53 55 59 63 64 69 70

71 72 73 74 81 84 85 86 88 99

101

U7710

CRITICAL

DFN

ISL8009B

2

7

8

3

54

9

6

1

CERM

6.3V 805

22UF

20%

CRITICAL

1

2

C7750

2

1

C7776

47PF

CERM

402

5%

50V

IHLP1616BZ-SM

1 2

L7770

CRITICAL

2.2UH-3.25A

1%

113K

R7781

1

2

1/16W MF-LF 402

402

MF-LF

1/16W

1%

100K

1

2

R7780

20%

1

2

CERM

6.3V

22UF

C7771

805

CRITICAL

20%

6.3V CERM 805

22UF

CRITICAL

C7761

1

2

1

R7760

402

MF-LF

1/16W

1%

52.3K

CERM

1

2

402

50V

5%

47PF

C7766

1 2

IHLP1616BZ-SM

2.2UH-3.25A

L7760

CRITICAL

22UF

CRITICAL

805

CERM

6.3V

20%

C7760

1

2

R7761

1/16W

1%

100K

1

2

402

MF-LF

ISL8009B

DFN

CRITICAL

U7760

2

7

8

3

54

9

6

1

8

74

QFN

5

7

11

12

9

10

17

1

2

6

8

3

4

ISL8014

U7720

14 15

CRITICAL

13

16

6.3V

20%

1

805

2

22UF

CRITICAL

CERM

C7720

2

2.2UH-3.25A

L7720

CRITICAL

1

IHLP1616BZ-SM

1%

402

MF-LF

1

R7720

113K

1/16W

2

MF-LF

1/16W

402

2

1

1%

R7721

90.9K

2

1

805

CERM

6.3V

20%

CRITICAL

C7721

22UF

2

1

CRITICAL

22UF

805

6.3V

20%

C7722

CERM

74

1%

402

MF

0.475

R7700

1 2

1/16W

XDP_PCH

2.2UF

10%

6.3V 402

X5R

C7741

1

2

CRITICAL

SON

TPS720105

U7740

4

3

5

6

2

1

7

XDP_PCH

10%

6.3V CERM

402

1UF

C7740

1

2

50V 402

CERM

1

47PF

5%

2

C7723

SYNC_DATE=06/09/2009

SYNC_MASTER=K17_WFERRY

Misc Power Supplies

PP10V_FW

P1V8S0_PGOOD

1V5_S0_SW

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.4 mm

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

PP3V3_S0

PP3V3_S3

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE DIDT=TRUE

1V2ENET_SW

1V2ENET_FB

PP1V2_ENET

PM_ENET_EN

PP3V3_S3

PFWBOOST_NGATE

DIDT=TRUE

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PFWBOOST_SW

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PFWBOOST_BOOST

SWITCH_NODE=TRUE DIDT=TRUE

PFWBOOST_ITH_R

PFWBOOST_SENSE

PP1V0_FW

PPVIN_FW_FWPHY

PP1V8_S0

PP3V3_S5

PP1V05_S5

PPBUS_FW_FWBOOST

1V8S0_FB

SWITCH_NODE=TRUE DIDT=TRUE

1V8S0_SW

P1V8S0_EN

PFWBOOST_FB

1V5_S0_FB

PFWBOOST_ITH

PP1V5_S0

77 OF 132 72 OF 103

7 8

40

6 7 8

25 26 27 28 30 34 37 40 42

47 48 49 52 53 55 59 63 64 69 70 71 72

73 74 81 84 85 86 88 99

101

6 7

17 20 31 32 33 34 35 36

49 50 51 54 55 56 72 74 88

102 103

7

37 73

6 7

17 20 31 32 33 34 35 36 49

50 51 54 55 56 72 74 88

102 103

6 7

40

7

39 40

6 7

12 16 73 88

101

6 7

31 35 49 50 51 58 73 74 84 86 99

101

7

17

7

40

7

34 42 59 74 99

IN

D

SG

D

SG

D

G S

D

S

G

D

S

G

IN

D

G S

D

G

S

D

G

S

IN

OUT

THRM

GND

G

PG

SHDN*

D

VCC

S

ON

PAD

S

D

G

IN

OUT

THRM

GND

G

PG

SHDN*

D

VCC

S

ON

PAD

G

S

D

IN

OUT

THRM

GND

G

PG

SHDN*

D

VCC

S

ON

PAD

D

S

G

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Green FET drives gate to D+4.7V.

5.0V S0 FET

SiA417

23 mOhm @4.5V

1.1 A (EDP)

SiA417 P-TYPE 8V/5V

3.3V GPU FET

CHANNEL

RDS(ON)

LOADING

MOSFET

5.0V S0 FET

P-TYPE 8V/5V

23 mOhm @4.5V

P-TYPE 8V/5V

SiA417

3.3V S0 FET

CHANNEL

RDS(ON)

LOADING

CHANNEL

RDS(ON)

MOSFET

3.3V S3 FET

LOADING

CHANNEL

RDS(ON)

LOADING 9.866 A (EDP)

2.096 A (EDP)

23 mOhm @4.5V

5.182 A (EDP)

N-TYPE

0.3 A (EDP)

SI2312BDS

31 mOhm @4.5V

1.8V GPU_IFPX FET

MOSFET

LOADING

CHANNEL

RDS(ON)

376S0683

1.8V GPU_IFPX FET

SI7108DN

1.5V S3/S0 FET

MOSFET CHANNEL

N-TYPE 6 mOhm @4.5V

3.2A (EDP)

RDS(ON) LOADING

1.2V S0 FET

SI7615DN

5.5 MOHM @4.5V

P-TYPE 20V/12V

Green FET drives gate to D+4.7V.

0.124 A (EDP)

1.2V S0 FET

SI2306BDS-GE3

65 mOhm @4.5V

N-TYPE

RDS(ON)

CHANNEL

LOADING

MOSFET

376S0651

376S0748

3.3V GPU FET

3.3V S0 FET

MOSFET

3.3V S3 FET

1.5V S3/S0 FET

2

1

C7871

402

10% 10V

1UF

X5R

21

C7870

402

0.01UF

10% 16V

CERM

R7870

21

1/16W

402

5%

MF-LF

1K

402

2

1

R7872

1/16W MF-LF

51K

5%

74 88

CERM

21

C7810

10% 16V

402

0.01UF

2

1

10% 16V

402

X5R

0.033UF

C7811

47K

5%

1/16W

402

MF-LF

R7810

1 2

10K

2

1

MF-LF

402

5%

1/16W

R7812

402

CERM

10%

21

0.01UF

16V

C7830

2

1

402

16V

0.033UF

10%

X5R

C7831

21

R7830

47K

5% 1/16W MF-LF

402

2

1

R7832

MF-LF

100K

402

1/16W

5%

18 31 43 46

47 74

50 73 74

Q7812

1

6

2

SSM6N15FEAPE

SOT563

4

5

3

Q7812

SOT563

SSM6N15FEAPE

Q7872

2

1

3

SOD-VESM-HF

SSM3K15FV

SC70-6L

74

3

1

SIA417DJ

Q7810

CRITICAL

74

3

1

Q7870

SIA417DJ

SC70-6L

CRITICAL

50 73 74

2

1

3

Q7865

SOD-VESM-HF

SSM3K15FV

2

1

R7862

5%

402

MF-LF

1/16W

47K

21

R7860

402

MF-LF

47K

1/16W

5%

2

1

C7861

X5R 402

0.033UF

10% 16V

21

C7860

0.01UF

10%

402

CERM

16V

4

3

5

21

CRITICAL

SI7615DN

Q7860

PWRPK-1212-8

Q7830

4

3

5

21

PWRPK-1212-8

SI7615DN

CRITICAL

31

74

2

0.1UF

1

402

20%

CERM

10V

C7801

TDFN

U7801

SLG5AP020

CRITICAL

2

6

1

5

3

8

7

9

4

1

Q7801

5

2

4

PWRPK-1212-8-HF

CRITICAL

SI7108DN

3

74

C7850

10V

20%

402

1

2

CERM

0.1UF

U7850

SLG5AP020

9

7

8

3

5

1

6

2

CRITICAL

TDFN

4

1

2

3

SOT23

Q7850

CRITICAL

SI2306BDS-GE3

74 87 88

C7880

2

0.1UF

1

402

20%

CERM

10V

74

U7880

SLG5AP020

TDFN

CRITICAL

6

1

5

3

8

7

4

9

2

3

SI2312BDS

Q7880

CRITICAL

2

1

SOT23

402

21

R7801

0

5% 1/16W MF-LF

5%

1 2

402

R7850

0

1/16W MF-LF

NO STUFF

2

1

402

C7802

X5R

1UF

10V

10%

SYNC_DATE=06/09/2009

SYNC_MASTER=K17_WFERRY

Power FETs

PP1V2_ENET

PP1V5_S3

PP1V5_S3RS0

PP3V3_S5

P1V5CPU_EN

TP_P1V5S3RS0_PGOOD

PP5V_S5

1V5S3RS0FET_GATE_R

1V5S3RS0FET_GATE

PP1V2_S0

1V2S0FET_GATE_R

1V2S0FET_GATE

TP_P1V2S0_PGOOD

EG_RAIL4_EN

TP_GPUIFPX_PGOOD

PM_SLP_S4_L

1V8GPUIFPXFET_GATE

PP5V_S0

PP1V8_S0

PP1V8_GPUIFPX

P3V3S3_EN_L

P3V3S0_EN_L

PP3V3_S0

PP3V3_S5

P3V3S0_SS

PP5V_S0_ISNS_R

P5V0S0_SS

PP5V_S3

PP3V3_S3_ISNS_R

PM_SLP_S3_L_R

PP3V3_S5

PP3V3_S0GPU

PM_SLP_S3_L_R

P5V0S0_EN_L

EG_RAIL2_EN

P3V3GPU_EN_L

P3V3GPU_SS

P3V3S3_SS

P1V2GMUX_EN

78 OF 132 73 OF 103

7

37 72

7

28 30 31 68

7

57

6 7

31 35 49 50 51 58 72 73

74 84 86 99

101

7

23 57 67 73

102

7

23 57 67 73

102

6 7

88

6 7 8

23 42 48 53 55 69 70 71 87

102

6 7

12 16 72 88

101

6 7

82

6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52 53 55 59 63 64 69 70 71 72 74 81 84

85 86 88 99

101

6 7

31 35 49 50 51 58 72 73 74 84 86 99

101

7

102

6 7

31 33 43 44 45 47 51 55 68 83

103

7

102

6 7

31 35 49 50 51 58 72 73 74 84 86

99

101

6 7

75 80 81 82 83 85

OUT

IN

OUT

IN

OUT

Y

B

A

NC

G

D

S

IN

G

D

S

G

D

S

G

D

S

OUT

G

D

S

G

D

S

IN

OUT

G

DS

OUT

IN

IN IN

D

G S

OUT

IN

OUT

D

G S

IN

OUT

IN

THRM_PAD

GND

V3MON V4MON

RST*

MR*

VDD

VDDA

V2MON

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

3.3V ENET FET

3.3V S5 ENABLE

S0 ENABLE

3) GPUVcore

4) GDDR3 1.8V

3.3V,5V S3 ENABLE

1

Other S0 RAILS

PM_SLP_S3_L

1

2) GPU_3.3V

(PM_SLP_S3_L)

(AC_EN_L)

Sleep (S3)

Run (S0)

State

0

1

0

1

PM_SLP_S4_L

0 0

0

(PM_S4_STATE_L)

1) 1.1V

1

"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))

EXT GPU PWRGD Pullup

NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.

WLAN Enable Generation

V2MON THRESHOLD IS 2.866V V3MON THRESHOLD IS 0.6V V4MON THRESHOLD IS 0.6V

EG PM_ALL_GPU_PGOOD

1

NOTE: S3 term is guaranteed by source of R7920 & Q7920, MUST BE S3 RAIL.

IG HIGH

PM_ALL_GFX_PGOOD

27MHZ OE EN Generation

"ENET" = "S0" || ("S3" && "AC" && "WOL_EN")

CHGR VFRQ Generation

SMC_PM_G2_ENABLE

Battery Off (G3Hot)

Soft-Off (S5)

Unused PGOOD signal

S5 rail PWRGD

3.3V 1.05V AND 1.5V S0 RAILS MONITOR CIRCUIT

GPU Rail Sequencing

GT216 GPU requires rails to come up in the following order:

ENET Enable Generation

VFRQ Low: Fix Frequency VFRQ High: Variable Frequency

(PM_SLP_S3_L)

2

1

R7992

402

5%

MF-LF

10K

1/16W

18 31 43 46 47 73 74 18 31 43 46 47 73 74

2

1/16W MF-LF

PLACE_NEAR=U7980.1:2mm

5%

402

100

1

R7991

NO STUFF

MF-LF

100

1/16W

402

5%

R7902

12

NO STUFF

CERM 402

0.068UF

10% 10V

PLACE_NEAR=R7252.2:2mm

C7902

1

2

5%

1/16W

402

MF-LF

100K

PLACE_NEAR=U4900.L13:3mm

R7958

1

2

46

72

50 73 74

71 74

67

33K

1/16W

402

MF-LF

5%

PLACE_NEAR=U7600.25:6mm

R7981

1

2

1/16W

402

5%

100K

MF-LF

R7990

1

2

R7979

MF-LF

1/16W

100K

PLACEMENT_NOTE=Near U1800

5%

402

1

2

6

18 31 46 74 86

C7981

0.47UF

10%

CERM-X5R

6.3V

402

PLACE_NEAR=U7600.25:6mm

1

2

67 74

2

1/16W

402

1

PLACE_NEAR=U7300.11:3mm

5%

R7911

MF-LF

5.1K

PLACE_NEAR=U7300.11:3mm

0.47UF

CERM-X5R 402

10%

6.3V

C7910

1

2

PLACE_NEAR=R7251.2:3mm

0.47UF

NO STUFF

C7912

10%

CERM-X5R 402

6.3V

1

2

PLACE_NEAR=U7980.1:4mm

1/16W MF-LF

R7994

402

0

5%

1

2

1/16W

5%

MF-LF 402

100K

R7940

1

2

NOSTUFF

OMIT

402

NONE NONE

NONE

C7941

1

2

8

74 83 87 88

402

5%

10K

MF-LF

1/16W

R7985

1

2

PLACE_NEAR=U7850.1:6mm

1/16W 402

MF-LF

5%

5.1K

PLACE_NEAR=U7720.5:6mm

1

2

R7986

0.47UF

402

6.3V

10%

CERM-X5R

C7985

1

2

PLACE_NEAR=U7850.1:6mm

402

10%

0.47UF

CERM-X5R

6.3V

PLACE_NEAR=U7720.5:6mm

C7986

1

2

73 74

72 74

MF-LF

1/16W

100

5%

402

R7978

1 2

TC7SZ08AFEAPE

SOT665

U7980

2

1

3

5

4

SOT-363

2N7002DW-X-G

Q7920

6

2

1

18 46 47

20

6

18 31 46 74 86

2N7002DW-X-G

SOT-363

Q7921

3

5

4

10V

0.22UF

10%

CERM

402

C7920

1

2

SOT-363

2N7002DW-X-G

Q7920

3

5

4

SOT-363

2N7002DW-X-G

Q7921

6

2

1

8

72

R7920

MF-LF

402

10K

1/16W

5%

1

2

MF-LF

402

1/16W

5%

10K

R7921

1

2

402

100K

MF-LF

5%

1/16W

R7922

1 2

2N7002DW-X-G

SOT-363

Q7925

3

5

4

SOT-363

2N7002DW-X-G

Q7925

6

2

1

20 33

33

0.033UF

X5R 402

16V

10%

C7921

1

2

SOT-23-HF

CRITICAL

NTR4101P

Q7922

3

1

2

402

0.01UF

CERM

16V

10%

C7922

12

25 27 46 88

PLACE_NEAR=U7971.7:2mm

20%

CERM

10V

0.1uF

402

C7971

1

2

67

8

74 83 87 88

8

74 83 87 88

2

100

1

R7997

5%

MF-LF

1/16W

402

1

402

MF-LF

1/16W

5%

100

2

R7996

2

100

402

1

R7995

1/16W MF-LF

5%

0

MF-LF

1/16W

402

R7941

1 2

SOD-VESM-HF

SSM3K15FV

Q7995

3

1

2

402

5%

10K

MF-LF

1/16W

R7999

1 2

26

8

74 83 87 88

66

10K

402

5%

MF-LF

1/16W

R7931

1 2

SOD-VESM-HF

SSM3K15FV

Q7931

3

1

2

VFRQ_SLPS4

402

1/16W

5%

MF-LF

0

R7933

1 2

VFRQ_SLPS3

21

R7932

402

1/16W

5%

MF-LF

0

18 31 43 46 47 73 74

1/16W

5%

MF-LF

0

NO STUFF

402

R7935

1 2

100

402

5%

MF-LF

1/16W

R7901

12

C7901

10V

10%

NO STUFF

0.068UF

402

CERM

1

2

67

73 74

70 74

U7971

CRITICAL

ISL88042IRTJJZ

RAIL_MON

9

4

5 6 8

1

2

7

3

TDFN

68 74

5% MF-LF

1/16W

402

R7912

0

PLACE_NEAR=R7251.2:3mm

20% 10V

0.1UF

402

CERM

C7989

1

2

SYNC_DATE=06/09/2009

SYNC_MASTER=K17_WFERRY

Power Control

PM_SLP_S3_L

CHGR_VFRQ

VFRQ_EN_GATE

EG_RAIL1_EN

ALL_SYS_PWRGD

ALL_GFX_PGOOD_R

S0_PWR_PGOOD

MAKE_BASE=TRUE

PM_SLP_S4_L

P5VS3_EN

MAKE_BASE=TRUE

DDRREG_EN

TP_P1V5S3RS0_PGOOD TP_GFXIMVP_PGOOD TP_DDRREG_PGOOD

MAKE_BASE=TRUE

TP_DDRREG_PGOOD

TP_GFXIMVP_PGOOD

MAKE_BASE=TRUE

RSMRST_PWRGD

PP3V3_S0

P3V3S5_EN

PP3V3_S0

PP1V5_S0

PPCPUVTT_S0

S0PGOOD_PWROK

PP3V3_S0

PM_SLP_S4_L

WOL_EN

MAKE_BASE=TRUE

TP_P1V5S3RS0_PGOOD

PM_SLP_S3_L_R

PM_SLP_S3_L

P3V3S5_PGOOD

PP3V42_G3H

P5VS3_PGOOD

PM_SLP_S3_L_R

MAKE_BASE=TRUE

CPUVTTS0_EN

P1V2GMUX_EN

P1V8S0_EN

PP3V42_G3H

PP3V3_S5

PP3V3_S0

CK505_27MHZ_EN_L

PM_ALL_GPU_PGOOD

MAKE_BASE=TRUE

PM_ALL_GPU_PGOOD

PP3V3_S0

PP3V3_S3

PM_ENET_EN_L

EG_RAIL3_EN

EG_RAIL2_EN

EG_RAIL1_EN

MAKE_BASE=TRUE

SMC_ADAPTER_EN

P3V3ENET_SS

PP3V3_ENET

PM_ENET_EN

AP_PWR_EN

PM_WLAN_EN_L

EG_RAIL4_EN

AC_EN_L

P5VS3_EN

PM_SLP_S4_L

DDRREG_EN

P1V8S0_EN

MAKE_BASE=TRUE

SMC_PM_G2_EN

TP_P1V2S0_PGOOD TP_GPUIFPX_PGOOD

P1V8S0_PGOOD

PM_SLP_S3_L_R

S0PGOOD_PWROK

MAKE_BASE=TRUE

TP_GPUIFPX_PGOOD

TP_P1V2S0_PGOOD

MAKE_BASE=TRUE

PM_ALL_GPU_PGOOD

EG_RAIL4_EN

MAKE_BASE=TRUE

EG_RAIL3_EN

MAKE_BASE=TRUE

EG_RAIL2_EN

P5VS5_EN

MAKE_BASE=TRUE

P1V2GMUX_EN

CPUVTTS0_EN

MAKE_BASE=TRUE

79 OF 132 74 OF 103

74 87 88

67 74

68 74

70 74

46

6 7 8

25 26 27 28 30 34 37 40 42 47 48

49 52 53 55 59 63 64 69 70 71 72 73 74

81 84 85 86 88 99

101

67

6 7 8

25 26 27 28 30 34 37 40 42 47 48

49 52 53 55 59 63 64 69 70 71 72 73 74

81 84 85 86 88 99

101

7

34 42 59 72 99

6 7

10 12 13 15 25 26 40 71

101

74

6 7 8

25 26 27 28 30 34 37 40 42 47 48

49 52 53 55 59 63 64 69 70 71 72 73 74

81 84 85 86 88 99

101

73 74

6 7

17 21 23 43 45 46 47 48 49

50 51 54 65 66 74

50 73 74

6 7

17 21

23 43 45 46

47 48 49 50

51 54 65 66

74

6 7

31 35 49 50 51 58 72 73

84 86 99

101

6 7 8

25 26 27 28 30 34 37 40 42 47 48

49 52 53 55 59 63 64 69 70 71 72 73 74

81 84 85 86 88 99

101

6 7 8

25 26 27 28 30 34 37 40 42 47 48

49 52 53 55 59 63 64 69 70 71 72 73 74

81 84 85 86 88 99

101

6 7

17 20 31 32 33 34 35 36 49

50 51 54 55 56 72 88

102 103

74 83 88

73 74 88

74 87 88

7

27 37

73 74 87 88

72 74

74

73 74

8

74 83 87 88

73 74 87 88

74 83 88

73 74 88

73 74

71 74

OUT

PEX_RX2*

PEX_TX15*

PEX_TX15

PEX_TX14*

PEX_TX14

PEX_TX13*

PEX_TX13

PEX_TX12*

PEX_TX12

PEX_TX11*

PEX_TX10*

PEX_TX10

PEX_TX9*

PEX_TX9

PEX_TX8*

PEX_TX8

PEX_TX7*

PEX_TX7

PEX_TX6*

PEX_TX6

PEX_TX5*

PEX_TX4*

PEX_TX4

PEX_TX3*

PEX_TX3

PEX_TX2*

PEX_TX2

PEX_TX1*

PEX_TX1

PEX_TX0*

PEX_TX0

PEX_TSTCLK_OUT

PEX_SVDD_3V3

PEX_RX15*

PEX_RX15

PEX_RX14*

PEX_RX14

PEX_RX13*

PEX_RX13

PEX_RX12*

PEX_RX12

PEX_RX11*

PEX_RX11

PEX_RX10

PEX_RX9*

PEX_RX9

PEX_RX8*

PEX_RX8

PEX_RX7*

PEX_RX7

PEX_RX6*

PEX_RX6

PEX_RX5*

PEX_RX5

PEX_RX4*

PEX_RX4

PEX_RX2

PEX_RX0*

PEX_RX0

PEX_RST*

PEX_REFCLK*

PEX_REFCLK

PEX_CLKREQ*

PEX_TX5

PEX_RX3 PEX_RX3*

PEX_TX11

PEX_RX10*

PEX_RX1 PEX_RX1*

PEX_TERMP

PEX_TSTCLK_OUT*

(1 OF 9)

BUFRST*

VDD_SENSE

PEX_PLLVDD

PEX_IOVDDQ25

PEX_IOVDDQ24

PEX_IOVDDQ23

PEX_IOVDDQ22

PEX_IOVDDQ21

PEX_IOVDDQ20

PEX_IOVDDQ19

PEX_IOVDDQ18

PEX_IOVDDQ10

PEX_IOVDDQ9

PEX_IOVDDQ8

PEX_IOVDDQ7

PEX_IOVDDQ6

PEX_IOVDDQ5

PEX_IOVDDQ4

PEX_IOVDDQ3

PEX_IOVDDQ2

PEX_IOVDDQ1

PEX_IOVDD5

PEX_IOVDD4

PEX_IOVDD3

PEX_IOVDD2

VDD_SENSE

GND_SENSE

NC

PEX_IOVDD1

PEX_IOVDDQ17

PEX_IOVDDQ16

PEX_IOVDDQ15

PEX_IOVDDQ14

PEX_IOVDDQ13

PEX_IOVDDQ12

PEX_IOVDDQ11

GND_SENSE

(2 OF 9)

BI

IN

IN IN

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

- =PP1V2_GPU_PEX_PLLXVDD

Signal aliases required by this page:

(NONE)

120 mA: GT216 A01 DG v3 01/09

- =PP1V2_GPU_PEX_IOVDD

250mA

- =PP1V2_GPU_PEX_IOVDDQ

1500mA

BOM options provided by this page:

PEX 1.05V Current = 2A

Page Notes

Power aliases required by this page:

8 9

91

16V10% 402X5R

0.1uF

21

C8081

16V10% 402X5R

0.1uF

21

C8082

8 9

91

8 9

91

402X5R

0.1uF

10% 16V

21

C8079

16V10% 402X5R

0.1uF

21

C8080

8 9

91

8 9

91

16V10% 402X5R

0.1uF

21

C8077

16V10% 402X5R

0.1uF

21

C8078

8 9

91

8 9

91

16V10% 402X5R

0.1uF

21

C8075

16V10% 402X5R

0.1uF

21

C8076

8 9

91

8 9

91

16V10% 402X5R

0.1uF

21

C8073

16V10% 402X5R

0.1uF

21

C8074

8 9

91

10% 402

0.1uF

X5R16V

21

C8020

8 9

91

16V10% 402X5R

0.1uF

21

C8071

16V10% 402X5R

0.1uF

21

C8072

8 9

91

8 9

91

16V10% 402X5R

0.1uF

21

C8069

16V10% 402X5R

0.1uF

21

C8070

8 9

91

8 9

91

16V10% 402X5R

0.1uF

21

C8067

16V 402X5R

0.1uF

10%

21

C8021

16V10% 402X5R

0.1uF

21

C8068

8 9

91

8 9

91

16V10% 402X5R

0.1uF

21

C8065

16V10% 402X5R

0.1uF

21

C8066

8 9

91

8 9

91

16V10% 402X5R

0.1uF

21

C8063

16V10% 402X5R

0.1uF

21

C8064

8 9

91

0.1uF

40210% 16V X5R

21

C8050

8 9

91

16V10% 402X5R

0.1uF

21

C8061

16V10% 402X5R

0.1uF

21

C8062

8 9

91

8 9

91

16V10% 402X5R

0.1uF

21

C8059

16V10% 402X5R

0.1uF

21

C8060

8 9

91

8 9

91

16V10% 402X5R

0.1uF

21

C8057

0.1uF

16V10% 402X5R

21

C8051

16V10% 402X5R

0.1uF

21

C8058

10% 402X5R

0.1uF

16V

21

C8048

16V10% 402X5R

0.1uF

21

C8049

10%

0.1uF

16V 402X5R

21

C8046

6.3V

20%

603

CERM

4.7UF

2

1

C8001

6.3V

10%

402

CERM

1UF

2

1

C8003

10V

20%

402

CERM

0.1UF

2

1

C8004

402

0.1uF

X5R16V10%

21

C8047

CERM

10V

0.1UF

20%

402

2

1

C8005

603

4.7UF

6.3V

20% CERM

2

1

C8016

4.7UF

20%

6.3V 603

CERM

2

1

C8015

CERM-X5R

6.3V

20%

805

22UF

2

1

C8000

0.1uF

40216V X5R10%

21

C8044

1UF

6.3V

10%

402

CERM

2

1

C8002

CERM-X5R 805

6.3V

20%

22UF

2

1

C8006

6.3V

20% 603

CERM

4.7UF

2

1

C8007

CERM

6.3V

10% 402

1UF

2

1

C8008

1UF

6.3V

10% 402

CERM

2

1

C8009

20% 10V

402

CERM

0.1UF

2

1

C8010

20% 10V CERM 402

0.1UF

2

1

C8011

0.1uF

10% 40216V X5R

21

C8045

0603

100NH-700MA-0.14OHM

21

L8015

0.1uF

16V10% X5R402

21

C8042

1/16W

1%

402

MF-LF

2.49K

21

R8050

1/16W

1%

402

MF-LF

200

NO STUFF

21

R8060

1/16W

0

MF-LF

402

5%

21

R8020

402

0.1uF

16V10% X5R

21

C8043

402X5R10%

0.1uF

16V

21

C8040

40216V10% X5R

0.1uF

21

C8041

16V10% 402X5R

0.1uF

21

C8038

16V10% 402X5R

21

C8039

0.1uF

16V10% 402X5R

0.1uF

21

C8036

16V10% 402X5R

0.1uF

21

C8037

10% 402X5R16V

0.1uF

21

C8034

X5R 40210% 16V

0.1uF

21

C8035

6

BGA

NV-GT216

OMIT

AM26

AL26

AK25

AL25

AM25

AM24

AM23

AL23

AK22

AL22

AM22

AM21

AM20

AL20

AK19

AL19

AP32

AN32

AM32

AM31

AM30

AM29

AL29

AK29

AK28

AL28

AM28

AM27

AM19

AM18

AM17

AL17

AJ18

AJ17

AG21

F7

AG19

AN26

AP26

AR26

AR25

AP25

AN25

AN23

AP23

AR23

AR22

AP22

AN22

AN20

AP20

AR20

AR19

AP34

AR34

AR32

AR31

AP31

AN31

AN29

AP29

AR29

AR28

AP28

AN28

AP19

AN19

AN17

AP17

AM16

AR17

AR16

AR13

U8000

10% X5R

0.1uF

16V 402

21

C8032

M7

BGA

NV-GT216

OMIT

P7

D35

AD20

AG14

AG23

AG22

AG18

AG17

AG16

AG15

AG13

AL16

AK26

AK23

AK20

AK18

AJ27

AG12

AJ25

AJ24

AJ22

AJ21

AJ19

AJ15

AJ14

AG26

AG25

AG24

AG11

AK27

AK24

AK21

AK17

AK16

AB7

V6

U7

AG20

Y4

AC5

AB4

AA4

J26

J25

J19

A5

J18

G5

P6

F4

E5

D7

D6

D5

C7

C5

B7

A7

A2

E7

AL7

AK15

AJ5

AG6

AF6

AD6

H32

R7

E35

AD19

A4

U8000

10%

402

X5R

16V

0.1UF

2

1

C8012

NO STUFF

1/16W

402

5%

MF-LF

0

21

R8012

402

1/16W

5%

MF-LF

0

21

R8013

10K

402

5%

MF-LF

1/16W

21

R8021

X5R-CERM

10%

6.3V

4.7UF

603

2

1

C8013

1UF

6.3V 402

10%

2

1

C8017

CERM

16V10% 402X5R

0.1uF

21

C8033

8

88

20%

10UF

X5R

6.3V 603

2

1

C8018

16V10%

0.1uF

402X5R

21

C8030

16V10% X5R

0.1uF

402

21

C8031

16V10% 402

0.1uF

X5R

21

C8028

16V10%

0.1uF

402X5R

21

C8029

10% 402X5R

0.1uF

16V

21

C8026

10% 402X5R

0.1uF

16V

21

C8027

16V10% 402X5R

0.1uF

21

C8024

16V10% 402X5R

0.1uF

21

C8025

16V10% 402X5R

0.1uF

21

C8022

16V 402X5R

0.1uF

10%

21

C8023

8

91

8

91

8

91

8

91

8

91

8

91

8

91

8

91

8

91

8

91

8

91

8

91

8

91

8

91

8

91

8

91

8

91

8

91

8

91

8

91

8

91

8

91

8

91

8

91

8

91

8

91

8

91

8

91

8

91

8

91

8

91

8

91

17 94

8

88

16V10% 402X5R

0.1uF

21

C8055

16V10% 402X5R

0.1uF

21

C8056

8 9

91

8 9

91

8 9

91

8 9

91

16V10% 402X5R

0.1uF

21

C8085

40216V10% X5R

0.1uF

21

C8086

8 9

91

8 9

91

16V10% 402X5R

0.1uF

21

C8083

16V10% 402X5R

0.1uF

21

C8084

8 9

91

NV GT216 PCI-E

SYNC_MASTER=K18_MLB

SYNC_DATE=06/29/2009

GPU_RESET_R_L

PEG_CLK100M_P

GPU_GND_SENSE

PP3V3_S0GPU

PEG_R2D_P<14>

PEG_R2D_P<13>

PEG_R2D_C_P<9>

PEG_R2D_C_N<7>

PEG_R2D_C_N<8>

PP1V05_S0GPU

PEG_R2D_C_N<14>

PEG_R2D_N<13>

PEG_R2D_P<15>

PEX_CLKREQ_L

PEG_R2D_C_N<9>

PEG_R2D_P<12>

PEG_R2D_N<11>

PEG_R2D_C_P<2>

PEG_R2D_C_P<1>

PEG_D2R_P<0>

PEG_D2R_C_N<0>

PEG_R2D_P<2>

PEG_R2D_N<3>

PEG_R2D_C_P<0>

PEG_R2D_C_N<0>

PEG_R2D_P<5> PEG_R2D_N<5>

PEG_R2D_P<6> PEG_R2D_N<6>

PEG_D2R_P<12>

PEG_D2R_C_N<13>

PEG_D2R_C_P<14>

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.30MM

PP3V3R1V05_GPU_PEX_SVDD

MIN_NECK_WIDTH=0.20MM

PEG_R2D_C_P<10>

PEG_R2D_P<10>

PEG_D2R_C_N<7>

PEG_R2D_C_P<8>

PEG_R2D_C_N<6>

PEG_R2D_P<1>

PEG_R2D_N<2>

PEG_D2R_C_N<15>

PEG_D2R_C_N<14>

PEG_D2R_C_P<13>

PEG_D2R_C_P<12>

PEG_D2R_C_N<8>

PEG_D2R_C_P<8>

PEG_D2R_C_P<7>

PEG_D2R_C_N<6>

PEG_D2R_C_P<6>

PEG_D2R_C_N<5>

PEG_D2R_C_N<4>

PEG_D2R_C_P<4>

PEG_D2R_C_N<3>

PEG_D2R_C_P<3>

PEG_D2R_C_N<2>

PEG_D2R_C_P<2>

PEG_D2R_C_N<1>

PEG_D2R_C_P<1>

PEG_D2R_C_P<0>

PEX_TSTCLK_P

PEG_R2D_N<4>

PEG_R2D_P<4>

PEG_R2D_N<0>

PEG_D2R_C_P<5>

PEG_R2D_P<3>

PEG_D2R_N<8>

PEG_D2R_P<8>

PEG_D2R_P<10>

PEG_R2D_C_N<1>

PEG_R2D_C_N<5>

PEG_D2R_P<15>

PEG_D2R_N<13>

PEG_D2R_P<14>

PEG_D2R_P<11>

PEG_D2R_N<11>

PEG_D2R_N<10>

PEG_D2R_N<12>

PEG_D2R_P<13>

PEG_D2R_N<14>

PEG_D2R_N<9>

PEG_D2R_N<7>

PEG_D2R_P<7>

PEG_D2R_P<6>

PEG_D2R_N<6>

PEG_D2R_P<9>

PEG_D2R_N<5>

PEG_D2R_P<5>

PEG_D2R_P<4>

PEG_D2R_N<4>

PEG_D2R_P<3>

PEG_D2R_N<3>

PEG_D2R_P<2>

PEG_D2R_N<2>

PEG_D2R_P<1>

PEG_D2R_N<1>

PEG_D2R_N<0>

PEG_R2D_C_N<2>

PEG_R2D_C_N<4>

PEG_R2D_C_P<3>

PEG_R2D_C_P<4>

PEG_D2R_C_P<15>

PEG_R2D_P<0>

PEG_R2D_C_N<3>

NC_GPU_DFM

NO_TEST=TRUE

PEG_R2D_P<9>

PEG_R2D_C_P<12>

PEG_R2D_C_P<7>

PEX_TSTCLK_N

PEX_TERMP_PD

PEG_R2D_C_P<5>

PEG_R2D_C_N<15>

PEG_R2D_P<11>

PEG_R2D_C_P<6>

PEG_R2D_N<14>

PEG_R2D_N<15>

PEG_R2D_C_P<11>

PEG_R2D_C_N<10>

PEG_D2R_N<15>

PP1V05_S0GPU

PEG_R2D_C_N<11>

PEG_R2D_P<8>

PEG_R2D_N<7>

PEG_R2D_P<7>

PEG_D2R_C_P<11>

PEG_D2R_C_N<12>

PEG_D2R_C_N<11>

PEG_D2R_C_N<10>

PEG_D2R_C_P<9>

PEG_D2R_C_P<10>

PEG_D2R_C_N<9>

PEG_R2D_N<1>

PEG_R2D_N<8>

PEG_R2D_N<9>

PEG_R2D_N<10>

PEG_R2D_N<12>

NC_GPU_BUFRST_L

EG_RESET_L

PEG_R2D_C_P<13>

PEG_R2D_C_N<12>

PEG_CLK100M_N

PEG_R2D_C_P<15>

PEG_R2D_C_P<14>

PEG_R2D_C_N<13>

PP1V05_S0GPU

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm VOLTAGE=1.05V

PP1V05_GPU_PEX_PLLVDD_F

GPU_VDD_SENSE

PP1V05_S0GPU

80 OF 132 75 OF 103

83

6 7

73 80 81 82 83 85

91

6 7

51 75 77 80 82

91

6 7

51 75 77 80 82

91

6 7

51 75 77 80 82

83

6 7

51 75 77 80 82

VDD VDD

(9 OF 9)

FBVDDQ FBVDDQ

(7 OF 9)

GNDGND

(8 OF 9)

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

- =PP1V8_GPU_FBVDDQ

BOM options provided by this page:

- =PPVCORE_GPU

Signal aliases required by this page:

Page Notes

Power aliases required by this page:

???A @ ???MHz 1.8V GDDR3

(NONE)

???A @ ???/???MHz Core/Mem Clk for VDD

Nvidia PRD for GB-128 uses 4x4.7uF, 8x0.47uF, 16x0.1uF

2

1

C8101

402

0.22UF

6.3V CERM-X5R

10%

2

1

C8100

402

10V X5R

1UF

10%

2

1

C8102

402

CERM-X5R

6.3V

0.22UF

10%

2

1

C8107

402

16V CERM-X5R

0.022UF

10%

2

1

C8112

402

25V X7R

0.01UF

10%

2

1

C8117

402

25V X7R

0.01UF

10%

2

1

C8106

402

16V X7R

0.047UF

10%

2

1

C8105

402

16V X7R

0.047UF

10%

2

1

C8110

402

16V X7R

0.015UF

10%

2

1

C8111

402

16V X7R

0.015UF

10%

2

1

C8116

10%

0.01UF

X7R

25V 402

2

1

C8115

402

25V X7R

0.01UF

10%

2

1

C8104

10%

0.047UF

X7R

16V 402

2

1

C8109

402

16V CERM-X5R

0.022UF

10%

2

1

C8114

402

0.01UF

25V X7R

10%

2

1

C8113

402

0.01UF

25V X7R

10%

2

1

C8108

402

16V CERM-X5R

0.022UF

10%

2

1

C8103

402

16V X7R-CERM

0.1UF

10%

2

1

C8159

10V

20%

CERM

0.1UF

402

2

1

C8158

10V

20%

402

CERM

0.1UF

2

1

C8150

4.7UF

CERM

603

6.3V

20%

2

1

C8157

10V

20%

402

CERM

0.1UF

2

1

C8119

402

25V CERM

0.0047UF

10%

2

1

C8118

402

25V CERM

0.0068UF

10%

AC19

AC18

AC17

AC16

AC15

AC14

AC13

AC12

AC11

AB25

L19

AB23

AB21

AB19

AB17

AB15

AB13

AB11

Y24

Y22

Y20

L18

Y18

Y16

Y14

Y12

W25

W24

W23

W22

W21

AD24

L17

W19

W18

W17

W16

W15

W14

W13

W12

W11

V25

L16

V23

V21

V19

V17

V15

V13

V11

T24

T22

T20

L15

T18

T16

T14

T12

R25

R24

R23

R22

R21

R20

L14

R19

R18

R17

R16

R15

R14

R13

R12

R11

P25

L13

P23

P21

P19

P17

P15

P13

P11

M24

M22

M20

L12

M18

M16

M14

M12

L25

L24

L23

L22

W20

AD22

L21

AD18

AD16

AD14

AD12

AC25

AC24

AC23

AC22

AC21

AC20

L20

L11

U8000

OMIT

NV-GT216

BGA

AJ28

AE27

AD27

AC27

AB29

AB27

AA31

AA29

AA27

Y27

W27

V34

V29

V27

U29

U27

T27

R27

P27

N27

J29

J24

J23

J22

J21

J20

J17

J16

J15

J14

H29

G22

G18

G17

G9

G8

E21

B18

U8000

BGA

NV-GT216

OMIT

V22

V20

V18

V16

V14

V12

V9

V5

V2

U25

B30

U24

U23

U22

U21

U20

U19

U18

U17

U16

U15

B27

U14

U13

U12

U11

T25

T23

T21

T19

T17

T15

B24

T13

T11

R34

R31

R5

R2

P24

P22

P20

P18

B21

P16

P14

P12

N25

N24

N23

N22

N21

N20

N19

B15

N18

N17

N16

N15

N14

N13

N12

N11

M34

M31

B12

M25

M23

M21

M19

M17

M15

M13

M11

M5

M2

B9

L9

J34

J31

J5

J2

F34

F31

F5

F2

E30

B6

AK14

K9

AP30

AP27

E27

AP24

AP21

AP18

AP15

AP12

AP9

AP6

AP3

AN34

AN2

E24

AL30

AL27

AL24

AL21

AL18

AL15

AL12

AL9

AL6

AK34

E18

AK31

AP33

AK5

AK2

AG34

AG31

AG5

AG2

AE25

AE24

E15

AE23

AE22

AE21

AE20

AE19

AE18

AE17

AE16

AE15

AE14

E12

AE13

AE12

AE11

AD34

AD31

AD25

AD23

AD21

AD17

AD15

E9

AD13

AD11

AD5

AD2

AC9

AB24

AB22

AB20

AB18

AB16

E6

AB14

AB12

AA34

AA25

AA24

AA23

AA22

AA21

AA20

AA19

C34

AA18

AA17

AA16

AA15

AA14

AA13

AA12

AA11

AA5

AA2

C2

Y25

Y23

Y21

Y19

Y17

Y15

Y13

Y11

V31

V24

B33

B3

U8000

BGA

NV-GT216

OMIT

2

1

C8156

20%

6.3V CERM

4.7UF

603

2

1

C8160

16V X7R

10%

402

0.047UF

2

1

C8162

16V X7R

10%

402

0.047UF

2

1

C8163

16V X7R

0.047UF

10%

402

2

1

C8164

25V X7R

0.01UF

10%

402

2

1

C8165

25V X7R

0.01UF

10%

402

2

1

C8166

25V X7R

0.01UF

10%

402

SYNC_DATE=03/26/2009

SYNC_MASTER=GT216

NV GT216 CORE/FB POWER

PPVCORE_GPU

PP1V8_S0GPU_ISNS

81 OF 132 76 OF 103

6 7 50

83

6 7 8

51 77 78 79

BI

BI BI BI

BI BI

BI

BI BI BI

BI

BI BI

BI

BI BI

BI BI BI

BI

BI BI

BI

BI BI BI

BI

BI BI

BI

BI BI

BI

BI BI

OUT

OUT OUT

OUT

OUT OUT

OUT

OUT OUT

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

OUT

OUT OUT

OUT

OUT OUT OUT OUT OUT OUT OUT

OUT OUT OUT OUT OUT

OUT

OUT OUT OUT

OUT OUT OUT OUT OUT OUT OUT OUT

OUT

BI

BI BI

IN

OUT OUT OUT

OUT

OUT OUT

OUT

BI

BI BI

BI

IN

IN IN

OUT

OUT OUT

OUT

OUT OUT

D

SG

IN

OUT

NC

NC NC NC NC NC NC NC

NC

OUT

(3 OF 9)

FBA_DQM3 FBA_DQM4

FBA_CLK1*

FBA_DQM0

FBA_CMD1 FBA_CMD2 FBA_CMD3

FBA_CLK0

FBA_CLK0*

FBA_CLK1

FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8

FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30

FBA_D00 FBA_D01 FBA_D02 FBA_D03 FBA_D04 FBA_D05 FBA_D06 FBA_D07 FBA_D08 FBA_D09 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63

FBA_DEBUG

FBA_DQM1

FBA_DQM2

FBA_DQM5

FBA_DQM6

FBA_DQM7

FBA_DQS_RN0 FBA_DQS_RN1 FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7

FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7

FB_CAL_PD_VDDQ

FB_CAL_PU_GND

FB_CAL_TERM_GND

FB_DLLAVDD FB_PLLAVDD

NC

FBA_CMD0

FBC_DQM1

FBC_CLK0

FBC_CLK0*

FBC_CLK1

FBC_CLK1*

FBC_CMD0 FBC_CMD1 FBC_CMD2 FBC_CMD3 FBC_CMD4 FBC_CMD5 FBC_CMD6 FBC_CMD7 FBC_CMD8

FBC_CMD9 FBC_CMD10 FBC_CMD11 FBC_CMD12 FBC_CMD13 FBC_CMD14 FBC_CMD15 FBC_CMD16 FBC_CMD17 FBC_CMD18 FBC_CMD19 FBC_CMD20 FBC_CMD21 FBC_CMD22 FBC_CMD23 FBC_CMD24 FBC_CMD25 FBC_CMD26 FBC_CMD27 FBC_CMD28 FBC_CMD29 FBC_CMD30

FBC_D00 FBC_D01 FBC_D02 FBC_D03 FBC_D04 FBC_D05 FBC_D06 FBC_D07 FBC_D08 FBC_D09 FBC_D10 FBC_D11 FBC_D12 FBC_D13 FBC_D14 FBC_D15 FBC_D16 FBC_D17 FBC_D18 FBC_D19 FBC_D20 FBC_D21 FBC_D22 FBC_D23 FBC_D24 FBC_D25 FBC_D26 FBC_D27 FBC_D28 FBC_D29 FBC_D30 FBC_D31 FBC_D32 FBC_D33 FBC_D34 FBC_D35 FBC_D36 FBC_D37 FBC_D38 FBC_D39 FBC_D40 FBC_D41 FBC_D42 FBC_D43 FBC_D44 FBC_D45 FBC_D46 FBC_D47 FBC_D48 FBC_D49 FBC_D50 FBC_D51 FBC_D52 FBC_D53 FBC_D54 FBC_D55 FBC_D56 FBC_D57 FBC_D58 FBC_D59 FBC_D60 FBC_D61 FBC_D62 FBC_D63

FBC_DEBUG

FBC_DQM0

FBC_DQM2

FBC_DQM3

FBC_DQM4

FBC_DQM5

FBC_DQM6

FBC_DQM7

FBC_DQS_RN0 FBC_DQS_RN1 FBC_DQS_RN2 FBC_DQS_RN3 FBC_DQS_RN4 FBC_DQS_RN5 FBC_DQS_RN6 FBC_DQS_RN7

FBC_DQS_WP0 FBC_DQS_WP1 FBC_DQS_WP2 FBC_DQS_WP3 FBC_DQS_WP4 FBC_DQS_WP5 FBC_DQS_WP6 FBC_DQS_WP7

FB_VREF

NC

(4 OF 9)

OUT

D

SG

NC

NC NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Signal aliases required by this page:

Power aliases required by this page:

- =PP1V8_GPU_FBIO

(NONE)

Page Notes

- =PP1V2_GPU_FBPLLAVDD

(NONE)

BOM options provided by this page:

78 98

78

78 98

79 98

78

78 98

79 98

79

79 98

79

79 98

10K

MF-LF 402

5% 1/16W

2

1

R8200

79 98

10K

MF-LF 402

5% 1/16W

2

1

R8250

31.6

1%

MF-LF

1/16W

402

PLACE_NEAR=U8000.L27:3mm

2

1

R8291

NO STUFF

0.1uF

X5R 402

10% 16V

2

1

C8296

1.07K

MF-LF

402

1%

1/16W

2

1

R8295

0603

21

L8200

FERR-220-OHM-2.5A

56.2

402

MF-LF

1/16W

1%

PLACE_NEAR=U8000.K27:3mm

2

1

R8290

6.3V

10% 603

4.7UF

X5R-CERM

2

1

C8200

10K

MF-LF 402

5% 1/16W

2

1

R8201

10K

MF-LF 402

5% 1/16W

2

1

R8251

78 98

79 98

SOT563

NO STUFF

SSM6N15FEAPE

1

2

6

Q8295

2.49K

MF-LF

402

1%

1/16W

2

1

R8296

NO STUFF

1.02K

MF-LF

402

1%

1/16W

2

1

R8297

78 79 80 81

78 98

79 98

78 98

81

79 98

81

40.2

MF-LF

402

1%

1/16W

PLACE_NEAR=U8000.M27:3mm

2

1

R8292

78 98

OMIT

NV-GT216

BGA

AH29

AG29

AE29

AD29

R29

P29

M29

L29

AC33

AJ34

AJ32

AE31

N31

J32

H35

L34

AC34

AJ35

AJ31

AD32

N32

H31

L35

AF35

AL34

AL32

AF32

P30

J30

H34

P32

T30

AC35

AB32

AE33

AE34

AE35

AF34

AE32

AF33

AM35

AM34

AL35

AJ33

AH32

AH34

AH35

AH33

AH30

AJ30

AK32

AK30

AL33

AM33

AL31

AN33

AD30

AC32

AE30

AF30

AF31

AH31

AG32

AG30

R30

R32

P31

M30

N30

M32

L30

L31

K31

H30

K32

K30

G32

G30

F30

G31

E33

E34

G33

G34

H33

K34

K33

K35

P34

P33

P35

N35

N34

L33

N33

L32

T34

W30

W33

W35

AB34

AB35

W29

Y32

T33

AB33

AB30

U33

U30

U35

V30

W34

Y35

U34

U31

Y31

U32

Y33

AA32

AA30

W32

Y34

Y30

AB31

T35

W31

V32

AC30

AC31

T31

T32

AF27

AG27

M27

L27

K27

U8000

G35

OMIT

NV-GT216

BGA

G28

G27

G25

G24

G15

G14

G12

G11

B26

A32

D32

E26

D14

E10

A10

C14

A26

A31

D31

F26

E14

D9

B10

B14

D28

A34

D34

D27

D15

F11

D10

A16

G19

A25

B25

D25

C26

C28

A28

B28

A29

B34

B35

B32

C32

B31

C29

C31

B29

E29

D30

F29

C33

E31

D33

F32

E32

E25

D24

F25

D26

E28

F28

F27

D29

F17

F16

E16

F15

F14

F13

E13

D12

E11

D11

D8

F12

F9

F10

F8

E8

A8

B8

C8

C10

A11

C11

B11

C13

D16

A17

B16

C16

A14

A13

D13

B13

F20

G21

E20

B23

D21

A23

A20

F21

B20

C23

F22

C19

F18

D19

E19

D20

D22

A19

D18

B22

C20

E22

C25

F24

B17

C22

A22

F23

F19

B19

C17

E23

D23

D17

E17

J27

U8000

10K

MF-LF 402

5% 1/16W

2

1

R8203

10K

MF-LF 402

5% 1/16W

2

1

R8252

78

79

X5R-CERM

6.3V

10%

4.7UF

603

2

1

C8201

402

1UF

CERM

10%

6.3V

2

1

C8202

SOT563

NO STUFF

SSM6N15FEAPE

4

5

3

Q8295

SYNC_MASTER=K18_MLB

SYNC_DATE=06/29/2009

NV GT216 FRAME BUFFER I/F

PP1V05_S0GPU

FB_A_MA<7>

MIN_NECK_WIDTH=0.2 MM

PP1V05_GPU_FBPLLAVDD_F

MIN_LINE_WIDTH=0.2 MM VOLTAGE=1.05V

FB_A_MA<11>

FB_B_DQ<32>

FB_A_MA<1>

FB_A_DQ<48>

FBCAL_PU_GND

FB_A_DQ<63>

FB_B_DQ<37>

FB_B_DQ<0>

FB_B_DQ<2> FB_B_DQ<3>

FB_A_UCKE

FB_B_DQ<5>

FB_B_DQ<17>

FB_B_DQ<20>

FB_A_DQM_L<1>

NC_FB_A_LCS1_L

FB_A_LCS0_L

NC_FB_A_UCS1_L

FB_A_LMA<3>

FB_A_LCKE

FB_A_DRAM_RST

FB_A_UMA<5>

FB_A_WE_L

FB_A_UMA<4>

FB_A_UCS0_L

FB_A_LCAS_L

FB_A_LMA<4> FB_A_RAS_L FB_A_LMA<5>

FB_A_UMA<2>

FB_A_DQ<38>

FB_A_DQ<36>

FB_A_DQ<33>

FB_A_DQ<31>

FB_A_DQ<27>

FB_A_DQ<23>

FB_A_DQ<20>

FB_A_DQ<19>

FB_A_DQ<16>

FB_A_DQ<12>

FB_A_DQ<6>

FB_A_DQ<5>

FB_A_DQ<4>

FB_A_DQ<3>

FB_A_DQ<2>

FB_A_DQ<0> FB_A_DQ<1>

FB_A_DQ<32>

FB_A_DQM_L<5>

FB_B_RDQS<6>

FB_B_LMA<3>

FB_B_MA<12>

FB_B_BA<1>

FB_B_LMA<4>

FB_B_DQM_L<1>

FB_B_CLK_P<0> FB_B_CLK_N<0> FB_B_CLK_P<1> FB_B_CLK_N<1>

FB_B_RAS_L FB_B_LMA<5>

FB_B_UMA<4>

FB_B_UCS0_L FB_B_MA<11>

FB_B_UMA<5>

FB_B_MA<7> FB_B_MA<10>

FB_B_MA<0> FB_B_MA<9> FB_B_MA<6> FB_B_LMA<2> FB_B_MA<8>

NC_FBB_MA<13>

NC_FB_B_LCS1_L

FB_B_DQ<1>

FB_B_DQ<4>

FB_B_DQ<6> FB_B_DQ<7> FB_B_DQ<8> FB_B_DQ<9> FB_B_DQ<10> FB_B_DQ<11> FB_B_DQ<12> FB_B_DQ<13> FB_B_DQ<14>

FB_B_DQ<18> FB_B_DQ<19>

FB_B_DQ<22> FB_B_DQ<23> FB_B_DQ<24> FB_B_DQ<25> FB_B_DQ<26> FB_B_DQ<27> FB_B_DQ<28> FB_B_DQ<29> FB_B_DQ<30> FB_B_DQ<31>

FB_B_DQ<33> FB_B_DQ<34> FB_B_DQ<35> FB_B_DQ<36>

FB_B_DQ<38> FB_B_DQ<39> FB_B_DQ<40> FB_B_DQ<41> FB_B_DQ<42> FB_B_DQ<43>

FB_B_DQ<47> FB_B_DQ<48> FB_B_DQ<49> FB_B_DQ<50> FB_B_DQ<51>

FB_B_DQ<54>

FB_B_DQ<56>

FB_B_DQM_L<0>

FB_B_DQM_L<2> FB_B_DQM_L<3> FB_B_DQM_L<4> FB_B_DQM_L<5> FB_B_DQM_L<6> FB_B_DQM_L<7>

FB_B_RDQS<0>

FB_B_RDQS<2> FB_B_RDQS<3> FB_B_RDQS<4> FB_B_RDQS<5>

FB_B_WDQS<0> FB_B_WDQS<1> FB_B_WDQS<2> FB_B_WDQS<3> FB_B_WDQS<4> FB_B_WDQS<5>

FB_B_WDQS<7>

FB_A_DQM_L<3> FB_A_DQM_L<4>

FB_A_CLK_N<1>

FB_A_BA<1>

FB_A_CLK_P<1>

FB_A_UMA<3>

NC_FBA_MA<13> FB_A_BA<2>

FB_A_DQ<8> FB_A_DQ<9>

FB_A_DQ<14> FB_A_DQ<15>

FB_A_DQ<21> FB_A_DQ<22>

FB_A_DQ<26>

FB_A_DQ<28> FB_A_DQ<29> FB_A_DQ<30>

FB_A_DQ<34> FB_A_DQ<35>

FB_A_DQ<37>

FB_A_DQ<39> FB_A_DQ<40> FB_A_DQ<41> FB_A_DQ<42> FB_A_DQ<43> FB_A_DQ<44> FB_A_DQ<45> FB_A_DQ<46> FB_A_DQ<47>

FB_A_DQ<49> FB_A_DQ<50> FB_A_DQ<51> FB_A_DQ<52> FB_A_DQ<53> FB_A_DQ<54> FB_A_DQ<55> FB_A_DQ<56> FB_A_DQ<57> FB_A_DQ<58> FB_A_DQ<59> FB_A_DQ<60> FB_A_DQ<61> FB_A_DQ<62>

FB_A_DQM_L<7>

FB_A_WDQS<2> FB_A_WDQS<3> FB_A_WDQS<4> FB_A_WDQS<5>

FB_A_WDQS<7>

FB_VREF_UNTERM

FB_A_MA<12>

FB_A_BA<0>

FB_B_DQ<45>

FB_B_DQ<44>

FB_A_DQM_L<2>

FB_A_RDQS<7>

FB_A_DQM_L<6>

FB_A_RDQS<0>

FB_A_RDQS<3> FB_A_RDQS<4>

FB_B_DQ<46>

GPU_FB_VREF_UNTERM_L

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm

FB_A_WDQS<6>

FB_A_RDQS<6>

FB_B_DQ<21>

FB_B_BA<0>

FB_B_DRAM_RST

FB_B_UMA<2>

FB_B_UCKE

FB_B_UMA<3>

FB_A_CLK_N<0>

FB_A_MA<8>

FB_A_MA<6>

FB_B_DQ<15> FB_B_DQ<16>

FB_A_UCAS_L

FB_A_RDQS<1>

FB_A_CLK_P<0>

FB_A_LMA<2>

FB_A_MA<0> FB_A_MA<9>

PP1V8_S0GPU_ISNS

GPU_FB_VREF

FB_B_RDQS<7>

FB_B_RDQS<1>

FB_B_LCS0_L

NC_FB_B_UCS1_L

FB_B_BA<2>

FB_B_MA<1>

FB_B_LCKE

FB_B_WE_L

FB_B_LCAS_L

FB_B_UCAS_L

FB_B_WDQS<6>

FB_B_DQ<58>

FB_A_MA<10>

FB_A_DQ<13>

FB_A_DQM_L<0>

FB_A_WDQS<1>

FB_B_DQ<53>

FB_B_DQ<52>

FB_B_DQ<55>

FB_B_DQ<57>

FB_B_DQ<59> FB_B_DQ<60> FB_B_DQ<61> FB_B_DQ<62> FB_B_DQ<63>

FB_A_WDQS<0>

FB_A_RDQS<5>

FB_A_DQ<17>

FB_A_DQ<24>

FBCAL_TERM_GND

FB_A_DQ<10> FB_A_DQ<11>

FB_A_DQ<7>

PP1V8_S0GPU_ISNS

FB_A_DQ<18>

FB_A_DQ<25>

FB_A_RDQS<2>

FBCAL_PD_VDDQ

82 OF 132 77 OF 103

6 7

51 75 80 82

81

78 98

81

6 7 8

51

76 77 78 79

79 98

81

6 7 8

51 76 77 78 79

IN

BI

BI BI

BI

BI BI BI

BI

BI BI BI

BI

IN

IN IN IN

OUT OUT

IN

IN IN

IN

OUT

OUT OUT

OUT

IN

IN IN

IN

BI

BI BI BI BI BI

BI

BI BI BI BI

BI

IN IN

BI

IN IN

D

SG

D

SG

D

SG

D

SG

IN IN

CK*

DQ17

CKE

A8/AP

RFU

DQ9

A11

CK

CS0*

DM2

BA2

BA1

BA0

WDQS1

WDQS3

WDQS2

WDQS0

RDQS3

RDQS2

SEN

DQ24

DQ20

DQ1

DQ0

DQ2 DQ3

DQ5 DQ6

DQ4

DQ7

DQ10 DQ11 DQ12 DQ13

DQ15 DQ16

DQ18 DQ19

DQ21

DQ23

DQ22

DQ25 DQ26 DQ27

DQ29

DQ28

DQ30 DQ31

A3 A4

DM3

DM1

DM0

CAS*

WE*

MF

ZQ

RAS*

A5 A6

A9

DQ8

RDQS1

RDQS0

RESET

A10

A7

A2

A1

A0

A12/CS1*

DQ14

MFHIGH

(1 OF 2)

MFHIGH

CK*

DQ17

CKE

A8/AP

RFU

DQ9

A11

CK

CS0*

DM2

BA2

BA1

BA0

WDQS1

WDQS3

WDQS2

WDQS0

RDQS3

RDQS2

SEN

DQ24

DQ20

DQ1

DQ0

DQ2 DQ3

DQ5 DQ6

DQ4

DQ7

DQ10 DQ11 DQ12 DQ13

DQ15 DQ16

DQ18 DQ19

DQ21

DQ23

DQ22

DQ25 DQ26 DQ27

DQ29

DQ28

DQ30 DQ31

A3 A4

DM3

DM1

DM0

CAS*

WE*

MF

ZQ

RAS*

A5 A6

A9

DQ8

RDQS1

RDQS0

RESET

A10

A7

A2

A1

A0

A12/CS1*

DQ14

MFHIGH

(1 OF 2)

MFHIGH

VDD0 VDD1

VDD4

VDD3

VDD2

VSS6 VSS7

VSS3

VSS5

VSS2

VSS1

VSS0

VSS4

VSSA0 VSSA1

VDDA0 VDDA1

VDD7

VDD6

VDDQ0 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 VDDQ19 VDDQ20 VDDQ21

VSSQ0

VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8

VSSQ9 VSSQ10 VSSQ11 VSSQ12 VSSQ13 VSSQ14 VSSQ15 VSSQ16 VSSQ17 VSSQ18 VSSQ19

VREF0 VREF1

VSSQ2

VSSQ1

VDD5

(2 OF 2)

VDD0 VDD1

VDD4

VDD3

VDD2

VSS6 VSS7

VSS3

VSS5

VSS2

VSS1

VSS0

VSS4

VSSA0 VSSA1

VDDA0 VDDA1

VDD7

VDD6

VDDQ0 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 VDDQ19 VDDQ20 VDDQ21

VSSQ0

VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8

VSSQ9 VSSQ10 VSSQ11 VSSQ12 VSSQ13 VSSQ14 VSSQ15 VSSQ16 VSSQ17 VSSQ18 VSSQ19

VREF0 VREF1

VSSQ2

VSSQ1

VDD5

(2 OF 2)

BI

BI BI

BI

NC NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

- =PP1V8_S0_FB_VREFA

Page Notes

Power aliases required by this page:

- =PP1V8_S0_FB_VDD

Signal aliases required by this page:

VRAM4

U8400.J12

U8400.J1U8400.J1

(NONE)

BOM options provided by this page:

Connect to designated pin, then GNDConnect to designated pin, then GND

U8400.J12

1/16W

1%

402

MF-LF

549

R8430

1

2

1/16W

1%

402

MF-LF

R8431

1

2

1.33K

16V

10%

402

X5R

0.1uF

C8403

1

2

16V

10%

402

X5R

0.1uF

C8402

1

2

16V

10%

402

X5R

0.1uF

C8404

1

2

0.1uF

16V

10%

402

X5R

C8401

1

2

16V

10% 402

X5R

0.1uF

C8422

1

2

16V

10% 402

X5R

0.1uF

C8423

1

2

16V

10% 402

X5R

0.1uF

C8424

1

2

16V

10% 402

X5R

0.1uF

C8425

1

2

16V

10% 402

X5R

0.1uF

C8426

1

2

1/16W

5%

402

MF-LF

100

R8449

1

2

1/16W

1%

402

MF-LF

R8448

1

2

243

1/16W

1%

402

MF-LF

121

VRAM4

R8445

1

2

1/16W

1%

402

MF-LF

243

R8446

1

2

16V

10% 402

X5R

0.1uF

C8421

1

2

16V

10%

402

X5R

0.1uF

C8415

1

2

16V

10%

402

X5R

0.1uF

C8410

1

2

1/16W

5%

402

MF-LF

1K

R8440

1

1/16W

1%

402

MF-LF

243

R8447

1

2

1/16W

1%

402

MF-LF

121

VRAM4

R8444

1

2

1/16W

1%

402

MF-LF

121

VRAM4

R8443

1

2

1/16W

1%

402

MF-LF

121

VRAM4

R8442

1

2

77 98

77 78 98

77

77 78 98

77 98

77 78 98

77 98

77 78 98

77 98

77 78 98

77 98

77 78 98

77

77 78 98

77 98

77 78 98

77 98

77 78 98

1/16W

5%

402

MF-LF

1K

R8490

1

2

1/16W

1%

402

MF-LF

121

VRAM4

R8492

1

2

16V

10% 402

X5R

0.1uF

C8471

1

2

16V

10% 402

X5R

0.1uF

C8472

1

2

1/16W

1%

402

MF-LF

243

R8498

1

2

1/16W

5%

402

MF-LF

100

R8499

1

2

1/16W

1%

402

MF-LF

121

VRAM4

R8493

1

2

1/16W

1%

402

MF-LF

121

VRAM4

R8495

1

2

1/16W

1%

402

MF-LF

121

VRAM4

R8494

1

2

1/16W

1%

402

MF-LF

243

R8497

1

2

1/16W

1%

402

MF-LF

243

R8496

1

2

16V

10% 402

X5R

0.1uF

C8473

1

2

16V

10% 402

X5R

0.1uF

C8474

1

2

16V

10% 402

X5R

0.1uF

C8475

1

2

16V

10% 402

X5R

0.1uF

C8476

1

2

16V

10%

402

X5R

0.1uF

C8451

1

2

16V

10%

402

X5R

0.1uF

C8452

1

2

16V

10%

402

X5R

0.1uF

C8460

1

2

16V

10%

402

X5R

0.1uF

C8453

1

2

16V

10%

402

X5R

0.1uF

C8465

1

2

16V

10%

402

X5R

0.1uF

C8454

1

2

77 98

C8400

6.3V

20%

603

X5R

10UF

1

2

6.3V

20% 603

X5R

10UF

1

2

C8420

6.3V

20%

603

X5R

10UF

C8450

1

2

6.3V

20% 603

X5R

10UF

C8470

1

2

16V

10% 402

CERM

0.01UF

C8446

1

2

16V

10%

402

CERM

0.01UF

C8496

1

2

1/16W

1%

402

MF-LF

931

R8432

1

2

16V

10% 402

CERM

0.01uF

C8481

1

2

1/16W

1%

402

MF-LF

931

R8482

1

2

1/16W

1%

402

MF-LF

549

R8480

1

2

1/16W

1%

402

MF-LF

1.33K

R8481

1

2

77 78 79 80 81

SOT563

SSM6N15FEAPE

Q8400

6

2

1

SOT563

SSM6N15FEAPE

Q8450

6

2

1

1/16W

1%

402

MF-LF

931

R8435

1

2

1/16W

1%

402

MF-LF

549

R8433

1

2

1/16W

1%

402

MF-LF

1.33K

R8434

1

2

16V

10% 402

CERM

0.01UF

C8431

1

2

SOT563

SSM6N15FEAPE

Q8400

3

5

4

16V

10% 402

CERM

0.01uF

C8482

1

2

1/16W

1%

402

MF-LF

931

R8485

1

2

1/16W

1%

402

MF-LF

549

R8483

1

2

1/16W

1%

402

MF-LF

1.33K

R8484

1

2

SOT563

SSM6N15FEAPE

Q8450

3

5

4

77 78 98 77 78 98

BGA

K4J10324QD-HC11

32MX32-900MHZ-MFH

CRITICAL

OMIT

U8450

K9

H11

K11

L9

J3

K10

M9 K4 H2 K3 L4 K2 M4

G9 G4 H3

F9

J11 J10

H9

F4

E3 E10 N10 N3

B2 B3

C11 C10 E11 F10 F11 G10 M11 L10 N11 M10

C2

R11

R10 T11 T10 M2 L3 N2 M3 R2 R3

C3

T2 T3

E2

F3

F2

G3

B11

B10

A9

H10

D3 D10 P10

P3

V9

J2

V4

D2 D11 P11

P2

H4

A4

K4J10324QD-HC11

OMIT

CRITICAL

E3 E10

F2 G3 B11

F4 H4

F10

P11

D11

P3

D2

BGA

32MX32-900MHZ-MFH

U8400

K9

H11

K11

L9

J3

K10

M9 K4 H2 K3 L4 K2 M4

G9 G4 H3

F9

J11 J10

H9

N10 N3

B2 B3

C11 C10 E11

F11 G10 M11 L10 N11

C2

T11 T10 M2 L3 N2 M3 R2 R3

C3

T2 T3

E2 F3

B10

A9

D3 D10 P10

V9

J2

V4

P2

A4

M10 R11 R10

H10

BGA

K4J10324QD-HC11

32MX32-900MHZ-MFH

CRITICAL

OMIT

U8400

A2

A11

F1

F12

M1

M12

V2

V11

K1

K12

A1

A12

J4 J9 N1 N4 N9

N12

R1 R4 R9

R12

C1

V1

V12

C4 C9

C12

E1 E4 E9

E12

H1

H12

A3 A10 G1 G12 L1 L12 V3 V10

J1 J12

B1 B4

L2 L11 P1 P4 P9 P12 T1 T4 T9 T12

B9 B12 D1 D4 D9 D12 G2 G11

BGA

K4J10324QD-HC11

32MX32-900MHZ-MFH

CRITICAL

OMIT

U8450

A2

A11

F1

F12

M1

M12

V2

V11

K1

K12

A1

A12

J4 J9 N1 N4 N9

N12

R1 R4 R9

R12

C1

V1

V12

C4 C9

C12

E1 E4 E9

E12

H1

H12

A3 A10 G1 G12 L1 L12 V3 V10

J1 J12

B1 B4

L2 L11 P1 P4 P9 P12 T1 T4 T9 T12

B9 B12 D1 D4 D9 D12 G2 G11

77 98

16V

10% 402

CERM

0.01UF

C8432

1

2

GDDR3 Frame Buffer A (Top)

SYNC_DATE=03/26/2009

SYNC_MASTER=GT216

FB_A_DQ<3>

FB_A_DQ<2>

FB_A_DQ<31>

FB_A_DQ<29>

FB_A_DQ<24>

FB_A_DQ<18>

FB_A_DQ<26>

FB_A_DQ<28>

FB_A_DQ<8>

FB_A_DQ<27> FB_A_DQ<30>

FB_A_DQ<0> FB_A_DQ<4>

FB_A0_MF

FB_A_RAS_L

FB_A_LCAS_L

FB_A_WE_L

FB_A_LCS0_L

FB_A_CLK_N<0>

FB_A_CLK_P<0>

FB_A_MA<12>

FB_A_LCKE

FB_A0_ZQ

FB_A_DRAM_RST

FB_A_RDQS<3>

FB_A_WDQS<2> FB_A_WDQS<3>

FB_A_BA<0> FB_A_BA<1>

GPU_FB_A_VREF_DIV

FB_A_LMA<4>

FB_A_WDQS<1>

FB_A_BA<2>

FB_A_RDQS<1>

FB_A_DQ<16>

FB_A_DQ<11>

FB_A_DQ<15>

FB_A_DQ<9>

FB_A_DQ<13> FB_A_DQ<10>

FB_A_DQ<17>

FB_A_DQ<22>

PP1V8_S0GPU_ISNS

FB_A1_ZQ

FB_A_DQ<45> FB_A_DQ<42>

FB_A_DQ<41>

FB_A_DQ<44>

FB_A_DQ<40>

FB_A_DQ<43>

FB_A_DQ<47>

FB_A_DQ<58>

FB_A_DQ<60>

FB_A_DQ<63>

FB_A_MA<8>

FB_A_MA<6>

FB_A_MA<0>

FB_A_UMA<3>

FB_A_DQ<46>

FB_A_DQ<61>

FB_A_DQ<59>

FB_A_UMA<2>

FB_VREF_UNTERM

FB_A_RDQS<7>

FB_A_MA<7>

FB_A_DQ<37>

FB_A3_VREF_UNTERM_L FB_A1_VREF_UNTERM_L

VOLTAGE=0.9V

FB_A_CLK0_TERM

FB_A0_VREF

FB_A2_VREF_UNTERM_L

FB_A1_VREF

GPU_FB_A_VREF_DIV

VOLTAGE=0.9V

FB_A_CLK1_TERM

FB_A3_VREFFB_A2_VREF

FB_A0_VREF_UNTERM_L

PP1V8_S0GPU_ISNSPP1V8_S0GPU_ISNS

FB_A_DQ<14>

FB_A_WDQS<0>

FB_A_DQ<1> FB_A_DQ<5>

FB_A_DQ<7>

FB_A_DQ<6>

FB_A_DQ<21>

FB_A_DQ<19>

FB_A_LMA<3>

FB_A_MA<8>

PP1V8_S0GPU_ISNS

FB_A_DQ<36>

FB_A_DQ<39>

FB_A_DQ<32>

FB_A_DQ<34>

FB_A_DQ<35>

FB_A_DQ<33>

FB_A_DQ<38>

FB_A_DQ<62>

FB_A_DQ<56>

FB_A_DQ<49> FB_A_DQ<57>

FB_A_DQ<53>

FB_A_DQ<55>

FB_A_DQ<51>

FB_A_DQ<48>

FB_A_DQ<50>

FB_A_DQ<52>

FB_A_DQ<54>

FB_A_MA<9>

FB_A_UMA<5>

FB_A_MA<1>

FB_A1_SEN

FB_A_BA<2>

FB_A_BA<1>

FB_A_BA<0>

FB_A_WDQS<4>

FB_A_WDQS<5>

FB_A_WDQS<7>

FB_A_WDQS<6>

FB_A_RDQS<4>

FB_A_RDQS<5>

FB_A_UMA<4>

FB_A_MA<10>

FB_A_LMA<5>

FB_A_MA<7>

FB_A_MA<11>FB_A_MA<11>

FB_A_MA<10>

FB_A_MA<6>

FB_A_MA<0> FB_A_MA<1> FB_A_LMA<2>

FB_A_MA<9>

FB_A0_SEN

FB_A_DQ<25>

FB_A_DQ<23>

FB_A_DQ<20>

FB_A_DQ<12>

FB_A_RDQS<2>

FB_A_RDQS<0>

FB_A_RAS_L

FB_A_UCAS_L

FB_A_WE_L

FB_A_UCS0_L

FB_A_CLK_N<1>

FB_A_UCKE FB_A_MA<12>

FB_A_CLK_P<1>

FB_A1_MF

FB_A_RDQS<6>

FB_A_DRAM_RST

FB_VREF_UNTERM

FB_A_DQM_L<1> FB_A_DQM_L<2> FB_A_DQM_L<3> FB_A_DQM_L<0>

FB_A_DQM_L<6> FB_A_DQM_L<7> FB_A_DQM_L<5> FB_A_DQM_L<4>

84 OF 132 78 OF 103

8

32 78

6 7 8

51 76 77 78

79

8

32 78

6 7 8

51 76 77 78 79

6 7 8

51 76 77 78

79

6 7 8

51 76 77 78 79

IN

IN IN

IN

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI BI BI

IN

OUT OUT OUT OUT

IN

IN IN

IN

OUT

OUT OUT

OUT

IN

IN IN

IN

BI BI BI BI

BI BI

BI BI BI BI BI

BI

BI BI BI BI

BI

IN IN

BI

IN IN

D

SG

D

SG

D

SG

D

SG

ININ

CK*

DQ17

CKE

A8/AP

RFU

DQ9

A11

CK

CS0*

DM2

BA2

BA1

BA0

WDQS1

WDQS3

WDQS2

WDQS0

RDQS3

RDQS2

SEN

DQ24

DQ20

DQ1

DQ0

DQ2 DQ3

DQ5 DQ6

DQ4

DQ7

DQ10 DQ11 DQ12 DQ13

DQ15 DQ16

DQ18 DQ19

DQ21

DQ23

DQ22

DQ25 DQ26 DQ27

DQ29

DQ28

DQ30 DQ31

A3 A4

DM3

DM1

DM0

CAS*

WE*

MF

ZQ

RAS*

A5 A6

A9

DQ8

RDQS1

RDQS0

RESET

A10

A7

A2

A1

A0

A12/CS1*

DQ14

MFHIGH

(1 OF 2)

MFHIGH

CK*

DQ17

CKE

A8/AP

RFU

DQ9

A11

CK

CS0*

DM2

BA2

BA1

BA0

WDQS1

WDQS3

WDQS2

WDQS0

RDQS3

RDQS2

SEN

DQ24

DQ20

DQ1

DQ0

DQ2 DQ3

DQ5 DQ6

DQ4

DQ7

DQ10 DQ11 DQ12 DQ13

DQ15 DQ16

DQ18 DQ19

DQ21

DQ23

DQ22

DQ25 DQ26 DQ27

DQ29

DQ28

DQ30 DQ31

A3 A4

DM3

DM1

DM0

CAS*

WE*

MF

ZQ

RAS*

A5 A6

A9

DQ8

RDQS1

RDQS0

RESET

A10

A7

A2

A1

A0

A12/CS1*

DQ14

MFHIGH

(1 OF 2)

MFHIGH

VDD0 VDD1

VDD4

VDD3

VDD2

VSS6 VSS7

VSS3

VSS5

VSS2

VSS1

VSS0

VSS4

VSSA0 VSSA1

VDDA0 VDDA1

VDD7

VDD6

VDDQ0 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 VDDQ19 VDDQ20 VDDQ21

VSSQ0

VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8

VSSQ9 VSSQ10 VSSQ11 VSSQ12 VSSQ13 VSSQ14 VSSQ15 VSSQ16 VSSQ17 VSSQ18 VSSQ19

VREF0 VREF1

VSSQ2

VSSQ1

VDD5

(2 OF 2)

VDD0 VDD1

VDD4

VDD3

VDD2

VSS6 VSS7

VSS3

VSS5

VSS2

VSS1

VSS0

VSS4

VSSA0 VSSA1

VDDA0 VDDA1

VDD7

VDD6

VDDQ0 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 VDDQ19 VDDQ20 VDDQ21

VSSQ0

VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8

VSSQ9 VSSQ10 VSSQ11 VSSQ12 VSSQ13 VSSQ14 VSSQ15 VSSQ16 VSSQ17 VSSQ18 VSSQ19

VREF0 VREF1

VSSQ2

VSSQ1

VDD5

(2 OF 2)

BI

NC NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

- =PP1V8_S0_FB_VREF_B

Page Notes

Power aliases required by this page:

- =PP1V8_S0_FB_VDD

Signal aliases required by this page:

BOM options provided by this page:

U8500.J1

(NONE)

U8500.J12

U8500.J1

U8500.J12

Connect to designated pin, then GND

VRAM4

Connect to designated pin, then GND

0.1uF

X5R 402

10% 16V

C8503

1

2

16V

0.1uF

X5R 402

10%

C8502

1

2

0.1uF

X5R 402

10% 16V

C8504

1

2

0.1uF

X5R 402

10% 16V

C8501

1

2

0.1uF

X5R 402

10% 16V

C8522

1

2

0.1uF

X5R 402

10% 16V

1

2

C8523

0.1uF

X5R 402

10% 16V

C8524

1

2

0.1uF

X5R 402

10% 16V

C8525

1

2

0.1uF

X5R 402

10% 16V

C8526

1

2

100

MF-LF 402

5% 1/16W

R8549

1

2

243

MF-LF

402

1%

1/16W

R8548

1

2

0.1uF

X5R 402

10% 16V

C8521

1

2

0.1uF

X5R 402

10% 16V

1

2

C8515

0.1uF

X5R 402

10% 16V

C8510

1

2

77 98

77 79 98

77

77 79 98

77 98

77 79 98

77 98

77 79 98

77 98

77 79 98

77 98

77 79 98

77

77 79 98

77 98

77 79 98

77 98

77 79 98

0.1uF

X5R 402

10% 16V

C8571

1

2

0.1uF

X5R 402

10% 16V

C8572

1

2

243

MF-LF

402

1%

1/16W

R8598

1

2

100

MF-LF 402

5% 1/16W

R8599

1

2

0.1uF

X5R 402

10% 16V

C8573

1

2

0.1uF

X5R 402

10% 16V

C8574

1

2

0.1uF

X5R 402

10% 16V

C8575

1

2

0.1uF

X5R 402

10% 16V

C8576

1

2

0.1uF

X5R 402

10% 16V

C8551

1

2

0.1uF

X5R 402

10% 16V

C8552

1

2

0.1uF

X5R 402

10% 16V

C8560

1

2

0.1uF

X5R 402

10% 16V

C8553

1

2

0.1uF

X5R 402

10% 16V

C8565

1

2

0.1uF

X5R 402

10% 16V

C8554

1

2

77 98

10UF

X5R 603

20%

6.3V

C8500

1

2

10UF

X5R 603

20%

6.3V

C8520

1

2

10UF

X5R 603

20%

6.3V

C8550

1

2

10UF

X5R 603

20%

6.3V

C8570

1

2

243

MF-LF

402

1%

1/16W

R8546

1

2

402

2

243

MF-LF

1% 1/16W

R8547

1

VRAM4

121

MF-LF

402

1%

1/16W

R8544

1

2

1/16W

VRAM4

121

MF-LF 402

1%

R8545

1

2

VRAM4

121

MF-LF

402

1%

1/16W

R8542

1

2

1K

MF-LF

402

5%

1/16W

R8540

1

2

1%

VRAM4

121

MF-LF 402

1/16W

R8543

1

2

243

MF-LF

402

1%

1/16W

R8596

1

2

243

MF-LF 402

1% 1/16W

R8597

1

2

VRAM4

121

MF-LF 402

1% 1/16W

R8595

1

2

VRAM4

121

MF-LF

402

1%

1/16W

R8594

1

2

VRAM4

121

MF-LF

402

1%

1/16W

R8592

1

2

VRAM4

121

MF-LF 402

1% 1/16W

R8593

1

2

1K

MF-LF

402

5%

1/16W

R8590

1

2

0.01UF

CERM

402

10% 16V

C8596

1

2

CERM

402

10% 16V

C8546

1

2

0.01UF

1.33K

MF-LF

402

1%

1/16W

R8531

1

2

931

MF-LF

402

1%

1/16W

R8532

1

2

0.01uF

CERM 402

10% 16V

C8531

1

2

549

MF-LF

402

1%

1/16W

R8530

1

2

1.33K

MF-LF

402

1%

1/16W

R8581

1

2

1%

R8582

1

2

1/16W MF-LF

402

931

549

MF-LF

402

1%

1/16W

R8580

1

2

0.01uF

CERM 402

10% 16V

C8581

1

2

77 78 79 80 81

2

SSM6N15FEAPE

Q8500

SOT563

6

1

SSM6N15FEAPE

SOT563

Q8550

6

2

1

CERM 402

10% 16V

C8532

1

2

0.01uF

931

MF-LF

402

1%

1/16W

R8535

1

2

549

MF-LF

402

1%

1/16W

R8533

1

2

1.33K

MF-LF

402

1%

1/16W

R8534

1

2

SSM6N15FEAPE

SOT563

Q8500

3

5

4

0.01uF

CERM 402

10% 16V

C8582

1

2

931

MF-LF

402

1%

1/16W

R8585

1

2

549

MF-LF

402

1%

1/16W

R8583

1

2

1.33K

MF-LF

402

1%

1/16W

R8584

1

2

SSM6N15FEAPE

SOT563

Q8550

3

5

4

77 79 98 77 79 98

N10

OMIT

CRITICAL

32MX32-900MHZ-MFH

K4J10324QD-HC11

BGA

U8550

K9

H11

K11

L9

J3

K10

M9 K4 H2 K3 L4 K2 M4

G9 G4 H3

F9

J11 J10

H9

F4

E3 E10

N3

B2 B3

C11 C10

G10 M11 L10 N11 M10

C2

R11

R10 T11 T10 M2 L3 N2 M3 R2 R3

C3

T2 T3

E2

F3

F2

G3

B11

B10

A9

H10

D3 D10 P10

P3

V9

J2

V4

D2 D11 P11

P2

H4

A4

E11 F10 F11

E3

B2

BGA

CRITICAL

U8500

K9

H11

K11

L9

J3

M9 K4 H2 K3 L4 K2 M4

G9 G4 H3

F9

J11 J10

H9

F4

E10 N10 N3

B3

C11 C10 E11 F10 F11 G10 M11 L10 N11 M10

C2

R11 R10 T11 T10 M2 L3 N2 M3 R2 R3 T2 T3

E2 F3 F2 G3 B11 B10

A9

H10

D3 D10 P10

P3

V9

J2

V4

D2 D11 P11

P2

A4

K10

32MX32-900MHZ-MFH

K4J10324QD-HC11

C3

OMIT

H4

OMIT

CRITICAL

32MX32-900MHZ-MFH

K4J10324QD-HC11

BGA

U8500

A2

A11

F1

F12

M1

M12

V2

V11

K1

K12

A1

A12

J4 J9 N1 N4 N9

N12

R1 R4 R9

R12

C1

V1

V12

C4 C9

C12

E1 E4 E9

E12

H1

H12

A3 A10 G1 G12 L1 L12 V3 V10

J1 J12

B1 B4

L2 L11 P1 P4 P9 P12 T1 T4 T9 T12

B9 B12 D1 D4 D9 D12 G2 G11

OMIT

CRITICAL

32MX32-900MHZ-MFH

K4J10324QD-HC11

BGA

U8550

A2

A11

F1

F12

M1

M12

V2

V11

K1

K12

A1

A12

J4 J9 N1 N4 N9

N12

R1 R4 R9

R12

C1

V1

V12

C4 C9

C12

E1 E4 E9

E12

H1

H12

A3 A10 G1 G12 L1 L12 V3 V10

J1 J12

B1 B4

L2 L11 P1 P4 P9 P12 T1 T4 T9 T12

B9 B12 D1 D4 D9 D12 G2 G11

77 98

SYNC_MASTER=GT216

SYNC_DATE=03/26/2009

GDDR3 Frame Buffer B (Top)

FB_B_DQ<63>

FB_B_DQ<57>

FB_B_DQ<62>

FB_B_DQ<36> FB_B_DQ<38> FB_B_DQ<37> FB_B_DQ<39> FB_B_DQ<35> FB_B_DQ<34>

FB_B_DQ<33>

PP1V8_S0GPU_ISNS

FB_B1_VREF_UNTERM_L

FB_B_DQ<2>

FB_B_DQ<0>

FB_B_DQ<4>

FB_B_DQ<26>

FB_B_DQ<28>

FB_B_DQ<24>

FB_B_DQ<27>

FB_B_DQ<23>

FB_B_DQ<12>

FB_B_DQ<13>

FB_B_DQ<17> FB_B_DQ<22> FB_B_DQ<18>

FB_B_RDQS<0>

FB_B_RDQS<3>

FB_B_RDQS<2>

FB_B_RDQS<1>

FB_B_DRAM_RST

FB_B0_MF

FB_B_LCAS_L

PP1V8_S0GPU_ISNS

FB_B0_VREF

FB_VREF_UNTERM

FB_B_DQ<45>

FB_B_DQ<61>

FB_B_DQ<16>

FB_B_DQ<10>

FB_B_DQ<15>

FB_B_DQ<7>

FB_B0_VREF_UNTERM_L

FB_B_CLK_P<0> FB_B_CLK_N<0>

FB_B_RAS_L

FB_B_WE_L

FB_B_LCS0_L

FB_B_MA<9>

FB_B_WE_L

FB_B_UCKE

FB_B1_MF

FB_B_DQ<9>

FB_B_DRAM_RST

FB_B_DQ<51> FB_B_DQ<55> FB_B_DQ<52> FB_B_DQ<53>

FB_B_DQ<48>

FB_B_DQ<32>

FB_B_MA<8>

FB_B_CLK_N<1>

FB_B_UMA<4>

FB_B_MA<7>

FB_B_DQ<60>

FB_B_DQ<41>

FB_B_DQ<40>

FB_B_DQ<42>

FB_B_DQ<44> FB_B_DQ<59> FB_B_DQ<56>

FB_B_DQ<58>

FB_B_WDQS<2>

FB_B0_SEN

FB_B_WDQS<1>

FB_B_WDQS<3> FB_B_WDQS<0>

FB_B_BA<0>

FB_B_BA<2>

FB_B_DQ<3>

FB_B_DQ<6>

FB_B_DQ<5>

FB_B_DQ<1>

FB_B_DQ<30>

FB_B_DQ<31>

FB_B_DQ<25>

FB_B_DQ<14>

FB_B_DQ<21>

FB_B_DQ<19>

FB_B_DQ<8>

FB_B_DQ<29>

FB_B_DQ<20>

FB_B_LMA<5>

FB_B_MA<7>

FB_B_LMA<2>

FB_B_MA<8>

GPU_FB_B_VREF_DIV

PP1V8_S0GPU_ISNS

GPU_FB_B_VREF_DIV

FB_B_DQ<47>

FB_B_CLK0_TERM

VOLTAGE=0.9V

FB_B_CLK1_TERM

VOLTAGE=0.9V

FB_VREF_UNTERM

FB_B3_VREF_UNTERM_L

FB_B2_VREF FB_B3_VREF

FB_B1_VREF

FB_B_UMA<5>

FB_B_MA<10>

FB_B_BA<0>

FB_B_DQ<46>

FB_B_DQ<43>

FB_B_BA<1>

FB_B_WDQS<5>

FB_B_RDQS<6>

FB_B_RDQS<4>

FB_B_RDQS<7>

FB_B_RDQS<5>

FB_B1_SEN

FB_B1_ZQ

FB_B_BA<2>

FB_B_WDQS<6>

FB_B_WDQS<7>

FB_B_MA<1>

FB_B_MA<0>

FB_B_BA<1>

PP1V8_S0GPU_ISNS

FB_B_MA<11>

FB_B_DQ<50>

FB_B_DQ<49>

FB_B_DQ<54>

FB_B_MA<10> FB_B_MA<11>

FB_B_MA<12>

FB_B_LCKE

FB_B_MA<12>

FB_B_WDQS<4>

FB_B2_VREF_UNTERM_L

FB_B_MA<6>

FB_B_LMA<3> FB_B_LMA<4>

FB_B_MA<6>

FB_B_UCAS_L FB_B_RAS_L

FB_B_UCS0_L

FB_B_CLK_P<1>

FB_B_MA<9>

FB_B_UMA<3>

FB_B_MA<1>

FB_B_MA<0>

FB_B_UMA<2>

FB_B0_ZQ

FB_B_DQ<11>

FB_B_DQM_L<1> FB_B_DQM_L<2> FB_B_DQM_L<3> FB_B_DQM_L<0>

FB_B_DQM_L<5> FB_B_DQM_L<7> FB_B_DQM_L<4> FB_B_DQM_L<6>

85 OF 132 79 OF 103

6 7 8

51 76 77 78

79

6 7 8

51 76 77 78

79

8

32 79

6 7 8

51 76 77 78 79

8

32 79

6 7 8

51 76 77 78 79

BI BI

BI

BI BI

OUT

IN IN

IN

OUT

IN

OUT

IN

(6 OF 9)

XTAL_SSIN

XTAL_OUTBUFF

XTAL_OUT

XTAL_IN

VID_PLLVDD

VDD33

THERMDP THERMDN

TESTMODE

STRAP2

STRAP1

STRAP0

SP_PLLVDD

ROM_SO

ROM_SI

ROM_SCLK

ROM_CS*

PLLVDD

MULTI_STRAP_REF1_GND

MULTI_STRAP_REF0_GND

MIOB_VSYNC

MIOB_VREF

MIOB_VDDQ_4

MIOB_VDDQ_3

MIOB_VDDQ_2

MIOB_VDDQ_1

MIOB_HSYNC

MIOB_DE

MIOB_D14

MIOB_D13

MIOB_D12

MIOB_D11

MIOB_D10

MIOB_D9

MIOB_D8

MIOB_D7

MIOB_D6

MIOB_D5

MIOB_D4

MIOB_D3

MIOB_D2

MIOB_D1

MIOB_D0

MIOB_CTL3

MIOB_CLKOUT*

MIOB_CLKOUT

MIOB_CLKIN

MIOB_CAL_PU_GND

MIOB_CAL_PD_VDDQ

MIOA_VSYNC

MIOA_VREF

MIOA_VDDQ_4

MIOA_VDDQ_3

MIOA_VDDQ_2

MIOA_VDDQ_1

MIOA_HSYNC

MIOA_DE

MIOA_D14

MIOA_D13

MIOA_D12

MIOA_D11

MIOA_D10

MIOA_D9

MIOA_D8

MIOA_D7

MIOA_D6

MIOA_D5

MIOA_D4

MIOA_D3

MIOA_D2

MIOA_D1

MIOA_D0

MIOA_CTL3

MIOA_CLKOUT*

MIOA_CLKOUT

MIOA_CLKIN

MIOA_CAL_PU_GND

MIOA_CAL_PD_VDDQ

JTAG_TRST*

JTAG_TMS

JTAG_TDO

JTAG_TDI

JTAG_TCK

GPIO23

GPIO21

GPIO19

GPIO18

GPIO17

GPIO15

GPIO14

GPIO13

GPIO12

GPIO11

GPIO10

GPIO9

GPIO8

GPIO7

GPIO6

GPIO5

GPIO4

GPIO3

GPIO2

GPIO1

GPIO0

GPIO16

GPIO22

GPIO20

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

- =PP1V2_GPU_PLLVDD

(NONE)

Power aliases required by this page:

65mA

25mA

- =PP1V2_GPU_H_PLLVDD

Signal aliases required by this page:

- =PP1V2_GPU_VID_PLLVDD

- =PP3V3_GPU_VDD33

(NONE)

- =PP3V3_GPI_MIO

110mA

Page Notes

50mA

BOM options provided by this page:

1/16W

1%

402

MF-LF

40.2K

2

1

R8697

1UF

X5R 402

10%

6.3V

2

1

C8636

6.3V

20%

603

CERM

4.7UF

2

1

C8635

100NH-700MA-0.14OHM

0603

21

L8635

0603

100NH-700MA-0.14OHM

21

L8640

402

0.1uF

X5R

10% 16V

2

1

C8617

10K

MF-LF

402

5%

1/16W

2

1

R8616

10K

MF-LF

402

5%

1/16W

2

1

R8617

49.9

1%

402

1/16W MF-LF

2

1

R8620

1/16W

1%

402

MF-LF

49.9

2

1

R8622

1/16W

1%

402

MF-LF

49.9

2

1

R8621

402

X5R

16V

10%

0.1uF

2

1

C8619

10K

MF-LF 402

1/16W

5%

2

1

R8618

1/16W

5%

402

MF-LF

10K

2

1

R8619

6.3V

10% 402

CERM

1UF

2

1

C8611

6.3V

10% 402

CERM

1UF

2

1

C8610

1/16W

1%

402

49.9

MF-LF

2

1

R8623

0.1uF

X5R 402

10% 16V

2

1

C8631

4.7UF

20%

6.3V CERM

603

2

1

C8640

6.3V

20%

603

CERM

4.7UF

2

1

C8643

6.3V

20%

603

CERM

4.7UF

2

1

C8637

1/16W

1%

402

MF-LF

40.2K

2

1

R8696

402

10K

5% 1/16W MF-LF

2

1

R8660

402

10V

20% CERM

0.1UF

2

1

C8694

6.3V

10%

402

X5R

1UF

2

1

C8696

402

6.3V X5R-CERM1

4.7UF

20%

2

1

C8698

81 83

81 85

81

81 87

81

77 78 79 81

6

81

81 83

81 88

81 83

81

6

81

6

81

6

81

6

81

6

81

6

81

6

81

6

81

6

81

6

81

6

81

52 81 99

81

8

27 81 98

81 98

BGA

NV-GT216

OMIT

D2

D1

B2

B1

AD9

J13

J12

J11

J10

J9

B5 B4

AP35

V7

W7

W5

AF9

C4

D3

D4

C3

AE9

M9

N9

W2

AF1

Y9

W9

AB9

AA9

W1

Y5

AC3

AC2

AC1

AC4

AB1

AB2

AB3

Y3

Y6

W6

U6

AE2

AE3

Y2

Y1

W3

W4

V4

AE1

AA6

AA7

L3

N5

U9

T9

R9

P9

N3

N2

U1

U4

T1

T2

T3

P3

P2

P1

N6

T6

R6

U3

U2

P4

N1

P5

T4

R4

N4

T5

U5

AP16

AR14

AN16

AN14

AP14

J7

H6

H5

H4

H1

H2

H3

M6

L6

K6

L5

K3

L7

M4

L4

L2

L1

J6

J4

H7

K5

K4

K2

K1

U8000

402

6.3V

10% X5R

1UF

2

1

C8641

NV GT216 GPIO/MIO/MISC

SYNC_MASTER=K18_MLB

SYNC_DATE=06/29/2009

PP1V05_S0GPU

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

PP1V05_GPU_VID_PLLVDD_F

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm VOLTAGE=1.05V

PP1V05_GPU_H_PLLVDD_F

NC_GPU_MIOB_D<6>

PP3V3_S0GPU

NC_GPU_MIOB_D<12>

PP3V3_S0GPU

GPU_MIOA_PU_GND

GPU_MIOA_PD_VDDQ

NC_GPU_MIOA_CLKOUTN

NC_GPU_MIOA_CLKIN

TP_GPU_JTAG_TDI

GPU_CLK27M_SS

GPU_XTALOUTBUFF

NC_GPU_XTALOUT

GPU_CLK27M

GPU_TDIODE_P GPU_TDIODE_N

GPU_STRAP<2>

GPU_STRAP<1>

GPU_STRAP<0>

GPU_ROM_SO

GPU_ROM_SI

GPU_ROM_SCLK

NC_GPU_ROM_CS_L

GPU_STRAP_REF_MIOB_PD

NC_GPU_MIOB_VSYNC

NC_GPU_MIOB_HSYNC

NC_GPU_MIOB_DE

NC_GPU_MIOB_D<14>

NC_GPU_MIOB_D<13>

NC_GPU_MIOB_D<11>

NC_GPU_MIOB_D<10>

NC_GPU_MIOB_D<9>

NC_GPU_MIOB_D<8>

NC_GPU_MIOB_D<7>

NC_GPU_MIOB_D<5>

NC_GPU_MIOB_D<4>

NC_GPU_MIOB_D<3>

NC_GPU_MIOB_D<2>

NC_GPU_MIOB_D<1>

NC_GPU_MIOB_D<0>

NC_GPU_MIOB_CTL3

NC_GPU_MIOB_CLKOUTN

NC_GPU_MIOB_CLKOUTP

NC_GPU_MIOB_CLKIN

GPU_MIOB_PU_GND

GPU_MIOB_PD_VDDQ

NC_GPU_MIOA_VSYNC

NC_GPU_MIOA_HSYNC

TP_GPU_MIOA_DE

GPU_MIOA_D<13>

GPU_MIOA_D<12>

GPU_MIOA_D<11>

TP_GPU_MIOA_D<9>

TP_GPU_MIOA_D<8>

TP_GPU_MIOA_D<7>

TP_GPU_MIOA_D<6>

TP_GPU_MIOA_D<5>

TP_GPU_MIOA_D<4>

TP_GPU_MIOA_D<3>

TP_GPU_MIOA_D<2>

TP_GPU_MIOA_D<1>

TP_GPU_MIOA_D<0>

NC_GPU_MIOA_CTL3

NC_GPU_MIOA_CLKOUTP

TP_GPU_JTAG_TRST_L

TP_GPU_JTAG_TMS

TP_GPU_JTAG_TDO

TP_GPU_JTAG_TCK

NC_GPU_GPIO_23

NC_GPU_GPIO_21

NC_GPU_GPIO_19

NC_GPU_GPIO_18

NC_GPU_GPIO_17

NC_GPU_GPIO_15

NC_GPU_GPIO_14

FBVDD_ALTVO

SMC_GFX_THROTTLE_R_L

GPU_GPIO_11

FB_VREF_UNTERM

TP_GPU_GSTATE<0>

SMC_GFX_OVERTEMP_R_L

GPU_VCORE_VID2

GPU_VCORE_VID1

GPU_VCORE_VID0

EG_BKLT_EN

EG_LCD_PWR_EN

GPU_VCORE_VID4

DP_EG_HPD

GPU_VCORE_VID3

GPU_GPIO_16

NC_GPU_GPIO_22

NC_GPU_GPIO_20

PP3V3_S0GPU

GPU_STRAP_REF_3V3_PD

GPU_MIOB_PD_VDDQ

GPU_MIOA_D<10>

GPU_MIOA_D<14>

GPU_MIOB_PU_GND

GPU_MIOA_PU_GND

GPU_MIOA_PD_VDDQ

GPU_MIOB_VREF

GPU_MIOA_VREF

GPU_TESTMODE_PD

86 OF 132 80 OF 103

6 7

51 75 77 80 82

6 7

51 75 77 80 82

6 7

73 75 80 81 82 83 85

6 7

73 75 80 81 82 83 85

80

81

80

6 7

73 75 80 81 82 83 85

80

OUT

D

GS

IN

BI

OUT

IN

OUT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

G96 MIOA_DE and MIOA_D<9..0> are used as Debug Port.

E 1110 PU 35k F 1111 PU 45k

2 0010 PD 15k

8 1000 PU 5k

Strap S1/S2 Bit[3:0] PU/PD Rval

3GIO_PADCFG[1]

RAMCFG[2]

SUB_VENDOR

SLOT_CLK_CFG

SMB_ALT_ADDR

RAMCFG[0]

PCI_DEVID[1]

0 0000 PD 5k

Strap S1/S2 Bit[3:0] PU/PD Rval

MEM_VREF

ROM_SO

ROM_SCLK

STRAP 2

THERM

STRAP 1

PCI_DEVID[3]

Unused signals

USER[0]

FAN_PWM

SLI_SYNC

STRAP 0

XCLK_417

VGA_DEVICE

PEX_PLL_EN_TERM

USER[2]USER[3]

Strapping Bit 3

HPDDVID0

GPIOs

C 1100 PU 25k

VID1

Renamed signals

Strapping Bit 1

3GIO_PADCFG[0]

HDMI_DETECT1

Isolation FETs for DP MUX inputs

HPDF

DVI_MODE0

Unused Clocks

GP

HPDE

GP

9 1001 PU 10k

B 1011 PU 20k

6 0110 PD 35k

ROM_SI

Native Func

7 0111 PD 45k

5 0101 PD 30k

3 0011 PD 20k 4 0100 PD 25k

Unused I2C Buses

(I2CS requires pullups even if not used)

I2CS ties into SMBus connection page

PCI_DEVID[0]

SWAPRDY_A

DVI_MODE1

HDMI_DETECT0

GPIOs

D 1101 PU 30k

USER[1]

AC_DET

PCI_DEVID[2]

LCD0_BL_PWM

HPDC

PCI_DEVID[4:0]=0x14

VID2/MEM_VID

Native Func

A 1010 PU 15k

1 0001 PD 10k

PWR_CTL1

PWR_CTL0

3GIO_PADCFG[3]

RAMCFG[3]

PCI_DEVID[4]

Strapping Pin

Physical

Strapping Bit 0

FB_0_BAR_SIZE

RAMCFG[1]

Strapping Bit 2

3GIO_PADCFG[2]

LCD0_VDD

LCD0_BL_EN

Config Straps

GPU_SS_INT

10K

MF-LF

402

5%

1/16W

R8781

1

2

10K

MF-LF

402

5%

1/16W

R8780

1

2

80 81

80 81 87

1/16W MF-LF

402

2

1

R8708

1%

OMIT

45.3K

402

MF-LF

1/16W

1%

15.0K

R8712

1

2

402

MF-LF

1/16W

5%

NO STUFF

2.0K

R8702

1

2

OMIT

402

MF-LF

1/16W

2.0K

5%

R8707

2

1

4.99K

1% 1/16W MF-LF

402

NO STUFF

R8709

1

2

NO STUFF

1/16W

402

MF-LF

1%

10K

R8704

1

2

MF-LF

1/16W

1%

24.9K

R8706

NO STUFF

402

2

1

45.3K

MF-LF

402

1%

1/16W

1

2

R8701

MF-LF

1/16W

1%

R8703

1

2

402

34.8K

1

2

402

1%

MF-LF

1/16W

R8705

10K

DP_CA_DET_EG_FET

SSM3K15FV

SOD-VESM-HF

Q8742

3

1

2

DP_CA_DET_EG_FET

100K

MF-LF

1/16W

402

1%

R8742

1

2

85 86 88

80 81 85

4.7K

MF-LF

5%

1/16W

402

R8752

1

2

4.7K

402

5% 1/16W MF-LF

R8753

1

2

81 82 85

8

18 85

81 82 85

8

18 85

80

DP_CA_DET_EG_PLD

0

MF-LF

402

5%

1/16W

R8743

1 2

88

0

5%

1/16W

NO STUFF

402

MF-LF

R8798

1 2

0

MF-LF

5%

1/16W

402

R8799

1 2

46

6

2.2K

MF-LF

402

5%

1/16W

R8797

1

2

1/16W

5%

402

MF-LF

2.2K

R8796

1

2

80 81 88

80 81 87

77 78 79 80 81

402

10K

MF-LF

5%

1/16W

R8792

1

2

10K

MF-LF

402

5%

1/16W

R8793

1

2

402

10K

5% 1/16W MF-LF

R8794

1

2

402

5%

MF-LF

NO STUFF

1/16W

10K

R8795

1

2

10K

402

1/16W

1%

MF-LF

R8710

1

2

402

2.2K

MF-LF

5%

1/16W

R8750

1

2

MF-LF

1/16W

402

2.2K

5%

R8751

1

2

1

402

15.0K

1% 1/16W MF-LF

R8711

2

NO STUFF

80 81 83

1

VRAM_512_HYNIX

R8708

114S0368

RES,MTL FILM,1/16W,35.7K,1,0402,SMD,LF

1

VRAM_512_SAMSUNG

R8708

114S0353

RES,MTL FILM,1/16W,24.9K,1,0402,SMD,LF

SYNC_MASTER=K18_MLB

SYNC_DATE=07/01/2009

GT216 GPIOS & STRAPS

GPU_VCORE_VID3

EG_BKLT_EN

GPU_VCORE_VID1 GPU_VCORE_VID2

FB_VREF_UNTERM

FBVDD_ALTVO

GPU_VCORE_VID4

MAKE_BASE=TRUE

GPU_VCORE_VID2

MAKE_BASE=TRUE

GPU_VCORE_VID1

MAKE_BASE=TRUE

GPU_VCORE_VID0

GPU_VCORE_VID4

MAKE_BASE=TRUE

GPU_VCORE_VID3

MAKE_BASE=TRUE

DP_EG_HPD

GPU_STRAP<2>

PP3V3_S0GPU

GPU_STRAP<1>

SMC_GFX_OVERTEMP_L

SMC_GFX_THROTTLE_L EG_LCD_PWR_EN EG_BKLT_EN FBVDD_ALTVO FB_VREF_UNTERM

MAKE_BASE=TRUE

FB_VREF_UNTERM

MAKE_BASE=TRUE

TP_GPU_GSTATE<1>

MAKE_BASE=TRUE

TP_GPU_GSTATE<0>

GPU_GPIO_16

MAKE_BASE=TRUE

FBVDD_ALTVO

NO_TEST=TRUE

NC_GPU_GPIO_14

MAKE_BASE=TRUE

EG_LCD_PWR_EN

PP3V3_S0GPU

SMC_GFX_OVERTEMP_R_L

PP3V3_S0GPU

MAKE_BASE=TRUE

SMC_GFX_THROTTLE_R_L

GPU_STRAP<0>

GPU_ROM_SCLK

PP3V3_S0GPU

DP_EG_DDC_DATA

DP_EG_DDC_CLK

TP_GPU_JTAG_TCK TP_GPU_JTAG_TDI

MAKE_BASE=TRUE

TP_GPU_JTAG_TCK

MAKE_BASE=TRUE

TP_GPU_JTAG_TDI

MAKE_BASE=TRUE

TP_GPU_JTAG_TDO TP_GPU_JTAG_TDO

MAKE_BASE=TRUE

TP_GPU_JTAG_TMS TP_GPU_JTAG_TMS

MAKE_BASE=TRUE

TP_GPU_JTAG_TRST_L TP_GPU_JTAG_TRST_L

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_MIOB_CTL3

TP_LVDS_EG_B_CLK_PTP_LVDS_EG_B_CLK_P

MAKE_BASE=TRUE

GPU_ROM_SO

GPU_ROM_SI

DP_IG_DDC_DATA

NC_GPU_GPIO_14

DP_EG_HPD

MAKE_BASE=TRUE

NC_GPU_GPIO_23

PP3V3_S0

MAKE_BASE=TRUE

DP_EG_DDC_CLK

MAKE_BASE=TRUE

LVDS_EG_DDC_DATA

MAKE_BASE=TRUE

LVDS_EG_DDC_CLK

NO_TEST=TRUE

NC_GPU_GPIO_18

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_GPIO_17

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_I2CH_SDA

NC_GPU_GPIO_15

NC_GPU_GPIO_17 NC_GPU_GPIO_18

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_MIOA_CLKOUTN

NC_GPU_MIOA_CTL3

NC_LVDS_EG_B_DATA_N<3>

MAKE_BASE=TRUE

NO_TEST=TRUE

DP_EG_DDC_DATA

DP_EG_DDC_CLK

LVDS_EG_DDC_DATA

LVDS_EG_DDC_CLK

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_I2CH_SCL

NC_GPU_GPIO_21

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_I2CC_SCL

MAKE_BASE=TRUE

DP_EG_DDC_DATA

NO_TEST=TRUE

NC_GPU_GPIO_15

MAKE_BASE=TRUE

EG_DP_CA_DET

NC_GPU_I2CH_SDA

NC_GPU_I2CH_SCL

NC_GPU_I2CC_SDA

NO_TEST=TRUE

NC_FBA_MA<13>

MAKE_BASE=TRUE

NC_GPU_GPIO_19

DP_IG_DDC_CLK

NC_FB_B_UCS1_L

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_FB_B_LCS1_L

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_ROM_CS_L

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_FBB_MA<13>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_FB_A_UCS1_L

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_FB_A_UCS1_L

NC_GPU_ROM_CS_L

NC_FB_B_LCS1_L

NC_FB_A_LCS1_LNC_FB_A_LCS1_L

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_FB_B_UCS1_L

NC_LVDS_EG_B_DATA_P<3>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_EG_A_DATA_N<3>

MAKE_BASE=TRUE

NO_TEST=TRUE

TP_LVDS_EG_B_CLK_N

MAKE_BASE=TRUE

NC_FBB_MA<13>

NC_GPU_I2CC_SCL

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_I2CC_SDA

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_MIOB_CLKIN

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_MIOB_VSYNC

GPU_XTALOUTBUFF

GPU_TDIODE_N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_MIOB_CLKOUTP

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_MIOB_D<14..0>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_MIOB_CLKOUTN

GPU_CLK27M_SS

GPU_MIOB_D<14..0> NC_GPU_MIOB_VSYNC NC_GPU_MIOB_HSYNC

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_MIOB_HSYNC

NC_GPU_MIOB_CLKOUTP NC_GPU_MIOB_CLKOUTN

NC_GPU_MIOB_DE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_MIOB_DE

NC_GPU_MIOB_CTL3

NC_GPU_MIOB_CLKIN

MAKE_BASE=TRUE

GPU_TDIODE_N

MAKE_BASE=TRUE

GPU_TDIODE_P

MAKE_BASE=TRUE

GPU_CLK27M

MAKE_BASE=TRUE

GPU_CLK27M_SS

GPU_MIOA_D<9..0> NC_GPU_MIOA_CLKIN

NC_GPU_MIOA_CLKOUTP

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_MIOA_CLKOUTP

NC_GPU_MIOA_CLKOUTN

TP_GPU_MIOA_DE

NC_GPU_MIOA_HSYNC NC_GPU_MIOA_VSYNC

GPU_CLK27M_SS

NC_LVDS_EG_A_DATA_N<3>

NC_LVDS_EG_A_DATA_P<3>

NC_FBA_MA<13>

TP_LVDS_EG_B_CLK_N

NC_LVDS_EG_B_DATA_P<3> NC_LVDS_EG_B_DATA_N<3>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_MIOA_D<14..10>

NO_TEST=TRUE

NC_GPU_GPIO_21

MAKE_BASE=TRUE

DP_CA_DET

DP_CA_DET_EG

NC_LVDS_EG_A_DATA_P<3>

MAKE_BASE=TRUE

NO_TEST=TRUE

GPU_CLK27M

GPU_TDIODE_P

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_MIOA_HSYNC

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_MIOA_VSYNC

MAKE_BASE=TRUE

SMC_GFX_OVERTEMP_R_L

EG_DP_CA_DET

PP3V3_S0GPU

EG_BKLT_EN

MAKE_BASE=TRUE

SMC_GFX_THROTTLE_R_L

EG_LCD_PWR_EN

MAKE_BASE=TRUE

NC_GPU_GPIO_22

NC_GPU_GPIO_20

SMC_GFX_OVERTEMP_R_L TP_GPU_GSTATE<0>

SMC_GFX_THROTTLE_R_L

GPU_GPIO_11

GPU_VCORE_VID0

GPU_MIOA_D<14..10>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_MIOA_CLKIN

MAKE_BASE=TRUE

TP_GPU_MIOA_D<9..0>

MAKE_BASE=TRUE

TP_GPU_MIOA_DE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_MIOA_CTL3

NO_TEST=TRUE

NC_GPU_GPIO_19

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_GPIO_20

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_GPIO_22

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_GPIO_23

87 OF 132 81 OF 103

80 81

83

80 81

88

80 81

83

80 81

83

77 78

79

80

81

80 81

87

80 81

83

80 81

85

6 7

73 75 80 81 82 83 85

77 78 79 80 81

6

80 81

80

80 81

88

6 7

73 75 80 81 82 83 85

80 81

6 7

73 75 80 81 82 83 85

6 7

73 75 80 81 82 83 85

80 81

80 81 80 81

80 81

6

81 82

6

81 82

80 81

6 7 8

25 26 27 28 30 34 37 40 42 47 48

49 52 53 55 59 63 64 69 70 71 72 73 74

84 85 86 88 99

101

81 82 85

80 81

81 82

80 81

81 82 98

81 82 85

81 82

80 81

81 82

81 82 85

80 81

81

81 82

80 81

77 81

80 81

77 81

80 81

77 81

81 82 98

6

81 82

77 81

81 82

80 81

80

52 80 81 99

80 81

80

80 81

80 81 98

80 81

80 81 80 81

80 81

80 81 80 81

80 81

52 80 81 99

27 80 81 98

80 81 98

80 81

80 81 80 81

80 81

6

80 81

80 81 98

81 82 98

77 81

6

81 82

81 82 98

80 81

81 82 98

27 80 81 98

52 80 81 99

80 81

81

6 7

73 75 80 81 82 83 85

80 81 88

80 81

80 81 88

80 81

6

80 81

80

80 81

83

80

80 81

6

80

6

80 81

OUT OUT

OUT

OUT OUT OUT

OUT OUT OUT OUT OUT OUT OUT OUT

OUT OUT

NC NC

NC NC NC NC NC NC NC NC

NC NC NC

NC NC

NC NC NC

NC

NC NC

NC

BI BI

OUT OUT

(5 OF 9)

IFPD_L2*

IFPA_TXC*

IFPF_IOVDD

IFPAB_PLLVDD IFPAB_RSET

IFPC_PLLVDD IFPC_RSET

IFPEF_PLLVDD IFPEF_RSET

CEC

DACA_BLUE

DACA_GREEN

DACA_HSYNC

DACA_RED

DACA_RSET

DACA_VDD

DACA_VREF

DACA_VSYNC

DACB_GREEN

DACB_HSYNC

DACB_RED

DACB_RSET

DACB_VDD

DACB_VREF

DACB_VSYNC

DACB_BLUE

I2CA_SCL I2CA_SDA

I2CB_SCL I2CB_SDA

I2CC_SCL I2CC_SDA

I2CH_SCL I2CH_SDA

I2CS_SCL I2CS_SDA

IFPA_IOVDD

IFPA_TXC

IFPA_TXD0

IFPA_TXD0*

IFPA_TXD1

IFPA_TXD1*

IFPA_TXD2

IFPA_TXD2*

IFPA_TXD3

IFPA_TXD3*

IFPB_IOVDD

IFPB_TXC

IFPB_TXC*

IFPB_TXD4

IFPB_TXD4*

IFPB_TXD5

IFPB_TXD5*

IFPB_TXD6

IFPB_TXD6*

IFPB_TXD7

IFPB_TXD7*

IFPC_AUX_I2CW_SCL

IFPC_AUX_I2CW_SDA*

IFPC_IOVDD

IFPC_L0

IFPC_L0*

IFPC_L1

IFPC_L1*

IFPC_L2

IFPC_L2*

IFPC_L3

IFPC_L3*

IFPD_AUX_I2CX_SCL

IFPD_AUX_I2CX_SDA*

IFPD_IOVDD

IFPD_L0

IFPD_L0*

IFPD_L1

IFPD_L1*

IFPD_L2

IFPD_L3

IFPD_L3*

IFPD_PLLVDD

IFPD_RSET

IFPE_AUX_I2CY_SCL

IFPE_AUX_I2CY_SDA*

IFPE_IOVDD

IFPE_L0

IFPE_L0*

IFPE_L1

IFPE_L1*

IFPE_L2

IFPE_L2*

IFPE_L3

IFPE_L3*

IFPF_AUX_I2CZ_SCL

IFPF_AUX_I2CZ_SDA*

IFPF_L0

IFPF_L0*

IFPF_L1

IFPF_L1*

IFPF_L2

IFPF_L2*

IFPF_L3

IFPF_L3*

NC NC

NC NC NC NC NC NC NC NC

NC NC

NC NC NC NC NC NC NC NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Page Notes

I2CS addr fixed at 0x9E,0x9F

I2CS must be pulled up if not used

?mA peak for all pairs

?mA peak per diff pair

Power inputs must be pulled down if not used

(NONE)

Place at AJ8

Place at AG9

?mA peak per diff pair

?mA peak for all pairs

160mA peak

Place at AK8

I2CS addr fixed at 0x9E,0x9F

80mA peak

I2CS must be pulled up if not used.

BOM options provided by this page:

Signal aliases required by this page:

- =PP3V3_GPU_IFPCD_IOVDD

- =PP1V8_GPU_IFPX

Sum of peak currents: 240mA

Place at AG10

Power aliases required by this page:

402

1/16W

R8850

1

2

1K

MF-LF

1%

L8805

1 2

180-OHM-1.5A

0603

L8815

1 2

FERR-220-OHM-2.5A

0603

6

81

6

81

88 98

C8805

1

2

4.7UF

CERM

603

20%

6.3V

R8852

1

2

10K

MF-LF 402

5% 1/16W

R8853

1

2

10K

MF-LF 402

5% 1/16W

R8854

1

2

10K

MF-LF 402

5% 1/16W

C8815

1

2

4.7UF

CERM

603

20%

6.3V

C8801

1

0.1UF

CERM

402

20% 10V

2

C8800

1

2

CERM

603

6.3V

4.7UF

20%

L8800

1 2

FERR-220-OHM-2.5A

0603

C8803

1

0.1UF

402

20% 10V

CERM

2

1

2

10V

0.1UF

402

CERM

20%

C8813

1

2

CERM

20% 10V

402

C8811

0.1UF

C8810

1

2

CERM

4.7UF

603

6.3V

20%

L8810

1 2

180-OHM-1.5A

0603

1/16W

R8855

1

2

1K

MF-LF 402

1%

85 98

81 85

81

81 85

46 49 52

81 98

R8860

1

2

1/16W

5%

402

MF-LF

1K

NO STUFF

R8861

1

2

NO STUFF

MF-LF

402

1/16W

5%

1K

U8000

AB5

AL14

AM14

AM13

AM15

AK13

AJ12

AK12

AL13

AJ4

AL4

AM1

AK4

AH7

AG7

AK6

AM2

G1 G4

G3 G2

E3 E4

F6 G6

E2 E1

AG9

AM11 AM12

AM8 AL8 AM10

AK10 AL10 AK11 AL11

AK9

AJ11

AG10

AP13 AN13

AN8 AP8 AP10 AN10 AR11 AR10 AN11 AP11

AP2 AN3

AJ8

AM7 AM6 AL5 AM5 AM3 AM4 AP1 AR2

AJ9 AK7

AP4 AN4

AK8

AR8 AR7 AP7 AN7 AN5 AP5 AR5 AR4

AC6

AB6

AE4 AD4

AE7

AH6 AH5 AH4 AG4 AF4 AF5 AE6 AE5

AJ6 AL1

AF3 AF2

AD7

AL2 AL3 AJ3 AJ2 AJ1 AH1 AH2 AH3

OMIT

BGA

NV-GT216

AM9

R8858

1

2

1%

402

1K

1/16W MF-LF

C8816

1

2

1UF

CERM

10%

6.3V 402

C8806

1

2

CERM

10%

6.3V 402

1UF

1/16W

5%

402

MF-LF

10K

R8856

2

1

10K

MF-LF 402

5% 1/16W

R8857

1

2

R8851

1

2

1/16W

1%

402

MF-LF

1K

SYNC_MASTER=K18_MLB

SYNC_DATE=06/29/2009

NV GT216 VIDEO INTERFACES

PP1V8_GPUIFPX

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP3V3_GPU_IFPC_PLLVDD_F

PP3V3_S0GPU

PP1V8_GPU_IFPAB_IOVDD_F

VOLTAGE=1.8V

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm

PP1V05_GPU_IFPCD_IOVDD_F

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.1 mm VOLTAGE=1.05V

NC_GPU_I2CC_SDA

NC_GPU_I2CH_SDA

DP_EG_ML_N<2> DP_EG_ML_P<3> DP_EG_ML_N<3>

DP_EG_ML_N<1> DP_EG_ML_P<2>

GPU_IFPAB_RSET

GPU_IFPC_RSET PP1V8_GPU_IFPEF_PLLVDD_F

DP_EG_AUX_CH_P

DP_EG_ML_P<1>

DP_EG_ML_P<0> DP_EG_ML_N<0>

NC_LVDS_EG_B_DATA_N<3>

NC_LVDS_EG_B_DATA_P<3>

LVDS_EG_B_DATA_N<2>

LVDS_EG_B_DATA_P<2>

LVDS_EG_B_DATA_N<1>

LVDS_EG_B_DATA_P<1>

LVDS_EG_B_DATA_N<0>

LVDS_EG_B_DATA_P<0>

TP_LVDS_EG_B_CLK_N

TP_LVDS_EG_B_CLK_P

NC_LVDS_EG_A_DATA_N<3>

NC_LVDS_EG_A_DATA_P<3>

LVDS_EG_A_DATA_N<2>

LVDS_EG_A_DATA_P<2>

LVDS_EG_A_DATA_N<1>

LVDS_EG_A_DATA_N<0>

LVDS_EG_A_CLK_P LVDS_EG_A_CLK_N

LVDS_EG_DDC_DATA

GPU_IFPEF_RSET

PP3V3_GPU_IFPC_PLLVDD_F

GPU_IFPC_RSET

GPU_IFPD_RSET

GPU_DACA_VDD

PP1V8_GPU_IFPD_PLLVDD

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.1 mm VOLTAGE=1.8V

GPU_DACB_VDD

NC_GPU_I2CC_SCL

GPU_IFPD_RSET

PP1V05_GPU_IFPEF_IOVDD_F

NC_GPU_I2CH_SCL

PP1V05_GPU_IFPCD_IOVDD_F

LVDS_EG_DDC_CLK

DP_EG_DDC_DATA

DP_EG_DDC_CLK

DP_EG_AUX_CH_N

SMBUS_SMC_0_S5_SCL SMBUS_SMC_0_S5_SDA

PP1V05_S0GPU

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm VOLTAGE=1.05V

PP1V05_GPU_IFPAB_PLLVDD_F

PP1V05_S0GPU

PP1V8_GPU_IFPEF_PLLVDD_F

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.1 mm VOLTAGE=1.8V

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.1 mm

PP1V05_GPU_IFPEF_IOVDD_F

VOLTAGE=1.05V

LVDS_EG_A_DATA_P<0>

LVDS_EG_A_DATA_P<1>

GPU_IFPAB_RSET

GPU_IFPEF_RSET

88 OF 132 82 OF 103

6 7

73

82

6 7

73 75 80 81 83 85

82

6 7

51 75 77 80

82

6 7

51 75 77 80 82

82

PVCC

THRM_PAD

FDE

PGOOD

AF_EN

VR_ON

IMON

VID4

VID3

VID2

VID1

VID0

LGATE

PGND

PHASE

UGATE

BOOT

VSS

VIN

ISP

VO

ISN

ICOMP

RTN

VSEN

VDIFF

FB

COMP

VW

OCSET

SOFT

VDD

RBIAS

OUT

IN

S

G

D

G

S

OUT

IN

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Other VID states may not be valid..

(GFXIMVP6_AGND)

K17 Default Vcore Setpoints

353S2289

30A max output

Vout = 0.80V - 0.98V

(L8920 limit)

GPU VCore Setpoints

(PPVCORE_GPU_REG)

0

0 1

1

VID4 VID3

1 0

VID2

1

00 11

01 1

VID1 VID0

0.74675V

0.90125V

0.82400V

Voltage

Max Batt

-

- -

-

Balanced Max perf

-

K17

GPU VCore Regulator

150

2

1

R8951

1/16W MF-LF

1%

402

150K

2

1

R8950

MF-LF

1%

402

1/16W

PLACE_NEAR=U8900.9:7mm

1

5%

MF-LF

1/16W

20

402

R8908

2

MF-LF

1/16W

PLACE_NEAR=U8900.8:7mm

20

402

5%

R8920

1 2

R8907

MF-LF

402

5%

10K

1

2

1/16W

5%

10K

1/16W MF-LF

R8910

1

2

402

0.0068UF

25V

C8951

21

CERM

10%

402

1

R8953

3.01K

2

402

1/16W

1% MF-LF

C8952

2

1

402

10% 50V

330PF

CERM

10%

330PF

2 1

C8950

50V 402

CERM

SIGNAL_MODEL=EMPTY

C8920

0.001UF

10% 402

CERM

50V

1

2

CRITICAL

QFN

U8900

30

17

5

6

32

10

28

11

13

21

3

20

31

19

22

1

9

2

33

18

16

7

23 24

25

26 27

14

12

29

8

15

4

ISL6263C

SM

PLACE_NEAR=U8900.33:2mm PLACE_NEAR=U8900.15:2mm

XW8900

1 2

680pF

C8953

10% CERM

50V 402

1

2

7.15K

402

1/16W MF-LF

1%

R8909

1

2

0.001UF

X7R 402

10% 50V

C8922

1

2

CERM

10% 50V

0.001UF

402

C8923

1

2

8

74 87 88

CERM

402

10% 50V

0.001UF

C8921

1

2

1/16W MF-LF

402

1%

10

R8904

1 2

150K

MF-LF

402

1/16W

R8905

2 1

1%

X5R 402

10% 16V

C8904

12

0.033UF

1uF

402

10% 10V X5R

C8901

1

2

402

5%

1

MF-LF

1/16W

R8911

1 2

4.7UF

X5R-CERM

20%

6.3V

C8902

1

2

402

CERM 402

10% 16V

0.01uF

C8903

1

2

10% 50V

CERM

0.001UF

402

C8972

1

2

CERM

402-1

50V

68PF

5%

C8971

1 2

R8902

9.76K

1

2

MF-LF

402

1%

1/16W

9.09K

R8901

2

1

1/16W MF-LF

1%

402

C8956

10% X7R

603

16V

0.22UF

1

2

MPL104-SM

1

CRITICAL

L8920

0.6UH-30A-1.5MOHM

2

10UF

X5R 603

20%

6.3V

C8965

1

2

X5R 603

20%

6.3V

1

2

10UF

C8966

CRITICAL

330UF

POLY-TANT D2T-SM2

20%

2.0V

C8943

1

23

1K

MF-LF

5%

1/16W

402

R8930

1

2

C8930

CRITICAL

20% 16V

POLY-TANT

68UF

CASE-D2E-SM

2

1

1UF

603-1

C8932

1

10% X5R

25V

2 2

1

C8933

25V

10%

603-1

X5R

1UF

MF-LF

402

1/16W

1K

1

2

1%

R8903

50V

330PF

COG 402

5%

C8906

1

2

D2T-SM2

CRITICAL

330UF

POLY-TANT

20%

2.0V

C8942

1

2 3

10UF

20% X5R

603

6.3V

1

2

C8968

603

6.3V X5R-CERM

4.7UF

10%

C8967

1

2

C8931

CRITICAL

20% 16V

POLY-TANT

68UF

CASE-D2E-SM

2

1

74 88

0.001UF

402

X7R

10% 50V

C8934

1

2

402

10% 50V

0.001UF

X7R

C8969

1

2

1%

100

1

2

402

MF-LF

1/16W

R8924

1

402

1/16W

1%

100

MF-LF

R8925

2

IRF6710

CRITICAL

S1

Q8950

2 5 64

3

1

IRF6795

DIRECTFET-MX

6 7

5

3 4

1 2

CRITICAL

Q8951

51

0612

CRITICAL

MF-1

1W

0.001

1%

R8940

12 34

7.32K

1 2

402

MF-LF

1/16W

1%

R8900

80 81

21

R8998

0

402

MF-LF

1/16W

5%

1 2

R8993

402

0

1/16W MF-LF

5%

21

R8994

0

1/16W MF-LF

402

5%

80 81

21

R8990

MF-LF

1/16W

5%

402

0

2 1

R8986

0

402

5% 1/16W MF-LF

GPUVID0_0

R8988

2

1

2.2K

402

5%

MF-LF

1/16W

2

1

R8985

GPUVID1_0

402

MF-LF

2.2K

5%

1/16W

GPUVID0_1

2

1

R8987

402

MF-LF

5%

2.2K

1/16W

2

1

R8984

GPUVID1_1

2.2K

402

5% 1/16W MF-LF

2

1

R8983

1/16W

5%

402

MF-LF

2.2K

GPUVID2_0

2

1

R8996

GPUVID3_0

402

1/16W MF-LF

5%

2.2K

2

1

R8992

GPUVID4_0

5%

2.2K

402

1/16W MF-LF

2

1

R8982

1/16W

GPUVID2_1

5%

2.2K

402

MF-LF

2

1

R8995

MF-LF

402

GPUVID3_1

1/16W

5%

2.2K

2

1

R8991

2.2K

GPUVID4_1

1/16W MF-LF

5%

402

SYNC_MASTER=K17_WFERRY

GPU (GT216) CORE SUPPLY

SYNC_DATE=06/09/2009

GPUVID_0P90V

GPUVID4_0,GPUVID3_1,GPUVID2_1,GPUVID1_1,GPUVID0_1

GPUVID4_1,GPUVID3_0,GPUVID2_1,GPUVID1_0,GPUVID0_1

GPUVID_0P75V

GPUVID_0P82V

GPUVID4_1,GPUVID3_0,GPUVID2_0,GPUVID1_1,GPUVID0_0

GFXIMVP6_VID2

GFXIMVP6_FB

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_VIN

MIN_NECK_WIDTH=0.2MM

DIDT=TRUE

MIN_LINE_WIDTH=0.6MM

GFXIMVP6_UGATE

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_VO

VOLTAGE=0V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

GND_GFXIMVP6_AGND

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_VSUM

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_DFB

MIN_NECK_WIDTH=0.2MM

GFXIMVP6_AF_EN

PP3V3_S0GPU

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_SOFT

MIN_NECK_WIDTH=0.2MM

PPVCORE_GPU

MIN_NECK_WIDTH=0.2MM

PPVCORE_GPU_REG_R

VOLTAGE=1.2V

MIN_LINE_WIDTH=0.6MM

PPBUS_G3H

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_OCSET

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

SWITCH_NODE=TRUE

DIDT=TRUE

GFXIMVP6_PHASE

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_BOOT

DIDT=TRUE

MIN_NECK_WIDTH=0.2MM

GPU_VDD_SENSE

VOLTAGE=1.25V

MIN_NECK_WIDTH=0.20 mm MIN_LINE_WIDTH=0.25 mm

MIN_NECK_WIDTH=0.3MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_PHASE_VSUM

GFXIMVP6_RBIAS

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

GFXIMVP6_VID0 GFXIMVP6_VID1 GFXIMVP6_VID2

EG_RAIL3_EN

PP5V_S3

MIN_NECK_WIDTH=0.2MM

GFXIMVP6_LGATE

MIN_LINE_WIDTH=0.6MM

GATE_NODE=TRUE

DIDT=TRUE

PPVCORE_GPU

GFXIMVP6_VID3

MIN_NECK_WIDTH=0.2MM

GFXIMVP6_COMP

MIN_LINE_WIDTH=0.3MM

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

GFXIMVP6_VW

MIN_NECK_WIDTH=0.2MM

GFXIMVP6_DROOP

MIN_LINE_WIDTH=0.3MM

PM_ALL_GPU_PGOOD

GFXIMVP6_VID4

GPU_GND_SENSE

VOLTAGE=0V

MIN_NECK_WIDTH=0.20 mm MIN_LINE_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_VDIFF

MIN_NECK_WIDTH=0.2MM

GFXIMVP6_VDIFF_RC

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.3MM

MIN_NECK_WIDTH=0.2MM VOLTAGE=5V

MIN_LINE_WIDTH=0.3MM

PP5V_S5_GFXIMVP6_PVCC

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

GFXIMVP6_VSEN_N

GFXIMVP6_IMON

VOLTAGE=5V

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

PP5V_S5_GFXIMVP6_VDD

GFXIMVP6_COMP_RC

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.3MM

GFXIMVP6_FDE

GPU_VCORE_VID2

GPU_VCORE_VID3

GPU_VCORE_VID4

GPU_VCORE_VID1

GPU_VCORE_VID0

GFXIMVP6_VID1

GFXIMVP6_VID0

GFXIMVP6_VID3 GFXIMVP6_VID4

PP3V3_S0GPU

MIN_NECK_WIDTH=0.2MM

GFXIMVP6_VSEN_P

MIN_LINE_WIDTH=0.3MM

89 OF 132 83 OF 103

83

6 7

73 75 80

81 82

83 85

6 7

50 76 83

6 7 8

40 50 66 67 68 70 71 87

75

83

6 7

31

33 43 44

45 47 51

55 68 73

103

6 7

50 76 83

83

75

99

83

6 7

73 75 80 81 82 83 85

99

SYM_VER-1

NC

IN

GND

THRM

ON

VIN_1

VIN_2

VOUT_1

VOUT_2

PAD

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

LCD (LVDS) INTERFACE

Place close to the connector

518S0651

Place close to the connector

Panel has 2K pull-ups

no-panel case (development).

100K pull-ups are for

2

1

C9010

50V

0.001UF

X7R

10%

402

2

1

C9001

10%

0.1UF

X5R

16V

402

21

L9000

CRITICAL

FERR-250-OHM

SM

2

1

R9011

MF-LF

1/16W

100K

402

5%

2

1

R9010

100K

1/16W

402

MF-LF

5%

4 3

21

L9010

CRITICAL

DLP11S

90-OHM-100MA

4 3

21

L9011

CRITICAL

DLP11S

90-OHM-100MA

9

8

7

6

5

44

43

42

41

40

4

39

38

37

36

35

34

33

32

31

30

3

29

28

27

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

J9000

CRITICAL

F-RT-SM

20474-040E-11

2

1

C9002

50V

0.001UF

10% X7R

402

2

1

603

1000PF

10% 100V X7R

C9008

88

2

1

C9009

10%

402

16V X5R

0.1UF

2

1

R9094

402

10K

5% 1/16W MF-LF

CRITICAL

FPF1009

U9000

MFET-2X2

5

4

3

2

1

76

0.1UF

10% X5R

16V 402

C9011

1

2

10UF

20%

6.3V X5R 603

C9012

1

2

SYNC_MASTER=K20A_MLB SYNC_DATE=03/26/2009

LVDS Display Connector

MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V

MIN_LINE_WIDTH=0.5 mm

PP3V3_SW_LCD_UF

LCD_PWR_EN

PP3V3_S5

LVDS_CONN_A_CLK_F_P

LED_RETURN_4 LED_RETURN_5

LVDS_CONN_B_CLK_F_P

LVDS_CONN_A_CLK_F_N

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.5 mm

PP3V3_SW_LCD

MIN_NECK_WIDTH=0.25 mm

LVDS_CONN_B_CLK_N

LVDS_CONN_B_CLK_P

LED_RETURN_6

LED_RETURN_3

LED_RETURN_2

LED_RETURN_1

LVDS_CONN_B_DATA_N<1>

LVDS_CONN_BKL_SYNC

LVDS_CONN_A_DATA_P<0>

LVDS_CONN_A_DATA_N<0>

LVDS_CONN_B_DATA_N<0>

LVDS_CONN_A_DATA_P<2>

LVDS_CONN_A_DATA_N<2>

LVDS_CONN_A_DATA_P<1>

LVDS_CONN_A_DATA_N<1>

LVDS_CONN_B_DATA_P<1>

LVDS_CONN_B_DATA_P<0>

LVDS_DDC_DATA

LVDS_DDC_CLK

PP3V3_S0

LVDS_CONN_A_CLK_N

LVDS_CONN_A_CLK_P

LVDS_CONN_B_DATA_P<2>

LVDS_CONN_B_DATA_N<2>

LVDS_CONN_B_CLK_F_N

PPVOUT_S0_LCDBKLT

90 OF 132 84 OF 103

6 7

31 35 49 50 51 58 72 73 74 86 99

101

6

98

6

89

6

89

6

98

6

98

6

85 98

6

89

6

89

6

89

6

89

6

85 98

6 8

6

85 98

6

85 98

6

85 98

6

85 98

6

85 98

6

85 98

6

85 98

6

85 98

6

85 98

6

85

6

85

6 7 8

25 26 27 28 30 34 37 40 42 47 48

49 52 53 55 59 63 64 69 70 71 72 73 74

81 85 86 88 99

101

85 98

6

85 98

6

85 98

6

98

6

57 89

IN IN

IN

BI

IN

OUT

OUT OUT

OUT

BI

IN

BI

IN

IN IN

BI BI

IN

OUT

BI

IN

XSD*

HPD_1

DIN1_0-

DIN1_1+

DIN1_2-

DAUX1+

DIN1_3+

DDC_DAT2

DAUX2-

DDC_CLK2

HPD_2

GPU_SEL

TST0

DIN1_2+

DIN1_1-

DOUT_0-

DOUT_1+ DDC_CLK1 DDC_DAT1

DOUT_2+

DOUT_2-

DOUT_3+

DOUT_3-

DIN2_1+

DDC_AUX_SEL

DIN2_1-

AUX+ AUX-

HPDIN

DIN2_2+ DIN2_2-

DIN2_3+ DIN2_3-

DAUX2+

DIN2_0-

DIN2_0+

DIN1_0+

DAUX1-

DOUT_1-

DOUT_0+ DIN1_3-

VDD

GND

OUT

VCC

C1

C2

C3

C4

A1 B1

A2 B2

A3 B3

A4 B4

GND

THRM

IN

OUT

IN

BI

BI BI

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

LO=AUX_CH HI=DDC

DisplayPort Mux

HI=PORT2

LO=PORT1

LVDS DDC MUX

All emulated LVDS outputs require this termination

LVDS Transmitter Termination

8

93

8

93

8

93

8

93

8

93

8

93

8

93

8

93

8

18 81

8

18 81

8

18

86 98

81 86 88

16V10% 402X5R

0.1uF

C9330

1 2

16V10% 402X5R

0.1uF

C9331

1 2

8

18 93

8

18 93

20%

0.1UF

CERM 402

10V

C9320

1

2

82 98

16V10% 402X5R

0.1uF

C9335

1 2

16V

0.1uF

40210% X5R

C9336

1 2

82 98

81 82

80 81

81 82

85 86 88

88

0.1UF

CERM 402

20% 10V

C9321

1

2

CBTL06141EE

BGA

CRITICAL

U9320

H1

H2

J9

H9

J6

H6

C2

H8

H5

J8

J5

A4

B4

A5

B5

A6

B6

A9

A8

B9

B8

D9

D8

E9

E8

F9

F8

B1

B2

D1

D2

E1

E2

F1

F2

B3C8G8H4H7

A1

J2

H3

J1

G2

A2

J4

B7

85 86 88

SN74LV4066A

QFN1

U9370

1

4

8

11

2

3

9

10

13

5

6

12

7

15

14

88

6

84

81 82

18

81 82

18

6

84

10V

CERM

402

0.1UF

20%

C9370

1

2

5% 1/16W MF-LF 402

20K

R9373

1

2

20K

MF-LF

402

1/16W

5%

R9372

1

2

88

DPMUX_EN_S0&DPMUX_EN_PLD

1/16W

402

MF-LF

10K

1%

R9302

1

2

DPMUX_EN_PLD

1/16W

402

MF-LF

0

5%

R9303

1 2

MF-LF

402

1/16W

10K

1%

DPMUX_EN_HPD

R9301

1

2

88 98

357

1/16W

402

MF-LF

1%

PLACE_NEAR=U9600.A5:7mm

R9357

1 2

357

1/16W MF-LF

402

1%

PLACE_NEAR=U9600.B3:7mm

R9352

1 2

357

1/16W MF-LF

402

1%

PLACE_NEAR=U9600.C5:7mm

R9355

1 2

357

1/16W MF-LF

402

1%

PLACE_NEAR=U9600.A1:7mm

R9350

1 2

357

1/16W MF-LF

402

1%

PLACE_NEAR=U9600.A3:7mm

R9347

1 2

357

1/16W MF-LF

402

1%

PLACE_NEAR=U9600.C9:7mm

R9342

1 2

357

1/16W MF-LF

402

1%

PLACE_NEAR=U9600.A2:7mm

R9345

1 2

1%

402

MF-LF

1/16W

357

PLACE_NEAR=U9600.C8:7mm

R9340

1 2

1%

402

MF-LF

1/16W

357

PLACE_NEAR=U9600.A10:7mm

R9337

1 2

357

1% 1/16W MF-LF

402

PLACE_NEAR=U9600.C10:7mm

R9332

1 2

1%

1/16W

402

357

MF-LF

PLACE_NEAR=U9600.B10:7mm

R9335

1 2

1% 1/16W MF-LF

402

357

PLACE_NEAR=U9600.A9:7mm

R9330

1 2

1% 1/16W MF-LF

402

357

PLACE_NEAR=U9600.B9:7mm

R9327

1 2

88 98

MF-LF

402

1/16W

1%

357

PLACE_NEAR=U9600.A7:7mm

R9322

1 2

1/16W

402

MF-LF

1%

357

PLACE_NEAR=U9600.A8:7mm

R9325

1 2

402

1/16W

1%

357

MF-LF

PLACE_NEAR=U9600.A6:7mm

R9320

1 2

1UF

10%

6.3V CERM-X5R 402

DPMUX_EN_HPD

C9301

1

2

84 98

6

84 98

6

84 98

6

84 98

6

84 98

6

84 98

6

84 98

6

84 98

6

84 98

6

84 98

6

84 98

6

84 98

6

84 98

MF-LF

402

1/16W

100K

5%

R9305

1

2

MF-LF

402

1/16W

100K

5%

R9304

1

2

PLACE_NEAR=U9320.J1:3mm

1/16W

402

MF-LF

5%

1K

R9307

1 2

20K

402

1/16W MF-LF

5%

R9371

1

2

1/16W

402

MF-LF

20K

5%

R9370

1

2

SYNC_MASTER=K17_REF

SYNC_DATE=06/17/2009

Muxed Graphics Support

LVDS_CONN_A_CLK_P

LVDS_CONN_A_DATA_P<0>

LVDS_CONN_A_DATA_N<0>

LVDS_CONN_A_DATA_P<2>

DP_IG_AUX_CH_N

LVDS_A_DATA_N<2>

LVDS_A_CLK_P

DP_EG_HPD

DP_IG_AUX_CH_P

DP_IG_DDC_DATA

DP_IG_HPD

DP_EG_ML_P<2>

DP_EG_ML_N<3>

DP_EG_AUX_CH_C_N DP_EG_DDC_CLK DP_EG_DDC_DATA

DP_ML_P<2>

DP_IG_ML_N<0>

DP_IG_ML_N<1>

DP_IG_ML_N<2>

DP_EG_ML_P<3>

DP_AUX_CH_C_N

DP_AUX_CH_C_P

DP_ML_N<3>

DP_ML_N<2>

DP_ML_P<3>

LVDS_A_DATA_P<0>

LVDS_A_DATA_N<0>

LVDS_B_DATA_P<0>

LVDS_B_DATA_N<0>

LVDS_B_DATA_P<1>

DP_IG_AUX_CH_C_N DP_IG_DDC_CLK

DP_EG_ML_N<1>

DP_EG_ML_N<2>

DP_HOTPLUG_DET

PP3V3_S0

DP_IG_ML_P<2>

DP_IG_ML_P<1>

DP_IG_ML_P<0>

DP_HPD_R

DP_ML_P<0>

PP3V3_S0GPU

LVDS_DDC_CLK

LVDS_IG_DDC_DATA

LVDS_DDC_SEL_EG

LVDS_IG_DDC_CLK

LVDS_EG_DDC_CLK

PP3V3_S0

DP_EG_ML_N<0>

DP_EG_ML_P<0>

DP_ML_N<1>

DP_ML_P<1>

DP_ML_N<0>

DP_IG_AUX_CH_C_P

DP_EG_AUX_CH_C_P

LVDS_A_CLK_N

LVDS_B_DATA_N<1>

LVDS_A_DATA_N<1>

LVDS_DDC_SEL_IG

LVDS_DDC_DATA

LVDS_EG_DDC_DATA

MAKE_BASE=TRUE

DP_HOTPLUG_DET

DP_EG_ML_P<1>

DP_IG_ML_P<3> DP_IG_ML_N<3>

DP_MUX_XSD_L

DP_MUX_EN

PP3V3_S0

DP_MUX_SEL_EG

DP_EG_AUX_CH_N

DP_EG_AUX_CH_P

LVDS_B_DATA_P<2>

LVDS_A_DATA_P<1>

LVDS_B_DATA_N<2>

LVDS_B_CLK_P

LVDS_B_CLK_N

LVDS_CONN_A_CLK_N

LVDS_CONN_A_DATA_P<1>

LVDS_CONN_A_DATA_N<1>

LVDS_CONN_A_DATA_N<2>

LVDS_CONN_B_CLK_P

LVDS_CONN_B_CLK_N

LVDS_CONN_B_DATA_P<0>

LVDS_CONN_B_DATA_N<0>

LVDS_CONN_B_DATA_P<1>

LVDS_CONN_B_DATA_N<1>

LVDS_CONN_B_DATA_P<2>

LVDS_CONN_B_DATA_N<2>

LVDS_A_DATA_P<2>

DP_CA_DET

93 OF 132 85 OF 103

98

99

6 7 8

25 26 27 28 30 34 37 40 42 47 48

49 52 53 55 59 63 64 69 70 71 72 73 74

81 84 85 86 88 99

101

6 7

73 75 80 81 82 83

6 7 8

25 26 27 28 30 34 37 40 42 47 48

49 52 53 55 59 63 64 69 70 71 72 73 74

81 84 85 86 88 99

101

99

98

6 7 8

25 26 27 28 30 34 37

40 42 47 48 49 52 53 55 59 63

64 69 70 71 72 73 74 81 84

85 86 88 99

101

BI

IN

IO NC NC

IO

GND

OUT

IO NC NC

IO

GND

IO NC NC

IO

GND

IO NC NC

IO

GND

IN

G

D

S

G

D

S

SYM_VER-2

OUT

G

D

S

G

D

S

BI

IN

OC*

OUT

EN

GND

IN

GND

ML_LANE0N

ML_LANE0P

ML_LANE1P

GND

ML_LANE1N

GND

DP_PWR

ML_LANE2P

AUX_CHP

RETURN

HOT_PLUG_DETECT

AUX_CHN

ML_LANE3P ML_LANE3N

ML_LANE2N

CONFIG1 CONFIG2

BOT ROW TOP ROW

TH PINS SM PINS

SHIELD PINS

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

514-0637

DP to DVI/HDMI

Port Power Switch

Q9440 must have Drain to Gate leakage of <500nA and Gate to Source resistance of >5MOhm

pull-up to DP_PWR.

(CA) has 100k

Cable Adapter

to 100K (DPv1.1a).

greater than or equal

down HPD input with

DP Source must pull

85 98

100K

R9421

2

1

MF-LF

1/16W

5%

402

10

9

12

3

D9411

RCLAMP0524P

CRITICAL

SLP2510P8

DP_ESD

21

C9415

40216V

0.1uF

X5R10%

C9414

21

40216V

0.1uF

X5R10%

81 85 88

21

C9411

0.1uF

X5R 40216V10%

21

C9410

0.1uF

X5R 40210% 16V

MF-LF

5%

1/16W

402

100K

R9420

1

2

D9410

RCLAMP0524P

CRITICAL

DP_ESD

SLP2510P8

3

9

2

10

1

SC70-6-1

D9400

CRITICAL

DP_ESD

52

6

4

3

1

RCLAMP0504F

76

45

3

D9411

RCLAMP0524P

SLP2510P8

DP_ESD

CRITICAL

1/16W

R9425

1M

402

2

1

5% MF-LF

D9410

DP_ESD

CRITICAL

RCLAMP0524P

SLP2510P8

3

6

5

7

4

21

C9417

X5R 40210% 16V

0.1uF

21

C9416

0.1uF

X5R 40210% 16V

21

C9413

0.1uF

X5R 40210% 16V

21

C9412

X5R 40210% 16V

0.1uF

85 98

2

1

C9400

0.01UF

CERM 603

50V

20%

21

L9400

0603

FERR-120-OHM-3A

85 98

4

5

3

Q9440

SOT-363

2N7002DW-X-G

1

2

6

Q9440

SOT-363

2N7002DW-X-G

2

1

R9443

100K

MF-LF

402

1/16W

5%

2

1

R9442

MF-LF

100K

402

1/16W

5%

4

3 2

1

FL9403

12-OHM-100MA

TCM1210-4SM

CRITICAL

4

32

1

FL9402

TCM1210-4SM

12-OHM-100MA

CRITICAL

4

32

1

FL9401

12-OHM-100MA

TCM1210-4SM

CRITICAL

4

32

1

FL9400

TCM1210-4SM

12-OHM-100MA

CRITICAL

21

R9403

0

1/16W

5% 402

MF-LF

NO STUFF

21

R9413

NO STUFF

1/16W

5% 402

MF-LF

0

21

R9402

0

1/16W

5% 402

MF-LF

NO STUFF

21

R9432

0

1/16W

5% 402

MF-LF

NO STUFF

21

R9401

MF-LF

5%

0

402

1/16W

NO STUFF

21

R9431

NO STUFF

5%

0

MF-LF

402

1/16W

21

R9400

0

1/16W

5% 402

MF-LF

NO STUFF

21

R9430

NO STUFF

MF-LF

4025%

1/16W

0

85 88

1

2

6

Q9441

2N7002DW-X-G

SOT-363

4

5

3

Q9441

2N7002DW-X-G

SOT-363

2

1

R9422

5%

MF-LF

402

1/16W

1M

2

1

R9445

10K

MF-LF

402

1/16W

5%

2

1

R9444

10K

MF-LF

5%

402

1/16W

2

1

R9423

5%

MF-LF

1/16W

402

100K

2

1

C9480

6.3V

20% X5R

10UF

603

2

1

C9481

0.1UF

402

CERM

10V

20%

85 98

20% X5R-CERM

603

1

2

22UF

C9486

CRITICAL

6.3V

CERM

20% 10V

402

1

2

C9485

0.1UF

1 3

5

2

U9480

TPS2051B

SOT23

CRITICAL

4

6

18 31 46 74

DSPLYPRT-M97-1

19

10 12

15 17

9 11

3 5

22 21

2

14 13

8 7

1

20

6

4

16 18

J9400

CRITICAL

F-RT-THSM

6.3V POLY-TANT

100UF

CRITICAL

20%

C9487

CASE-B2-SM

2

1

SYNC_DATE=03/26/2009SYNC_MASTER=K20A_MLB

DisplayPort Connector

DP_ML_CONN_P<1>

DP_ML_CONN_N<1>

DP_ML_CONN_P<2>

DP_ML_CONN_N<3>

DP_ML_CONN_N<2>

DP_CA_DET_Q

TP_DPPWR_OC_L

DP_HOTPLUG_DET

DP_HPD_L_Q

DP_ML_C_P<1>

DP_ML_C_P<0>

DP_ML_C_N<0>

DP_ML_C_N<1>

DP_ML_C_P<2>

DP_ML_C_N<2>

DP_ML_N<2>

DP_ML_P<2>

DP_ML_N<1>

DP_ML_P<1>

DP_ML_N<0>

DP_ML_P<0>

DP_CA_DET_L_Q

DP_CA_DET

DP_ML_N<3>

DP_ML_C_P<3>

PP3V3_S0

DP_ML_C_N<3>

PP3V3_S0_DPPWR

MIN_LINE_WIDTH=0.38 MM VOLTAGE=3.3V

MIN_NECK_WIDTH=0.20 MM

PM_SLP_S3_L

PP3V3_S5

PP3V3_S0_DPILIM

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V

DP_ML_CONN_P<0> DP_ML_CONN_N<0>

PP3V3_S0

DP_AUX_CH_C_P

DP_HPD_Q

DP_ML_CONN_P<3>

DP_AUX_CH_C_N

ESD_HOT=TRUE

HDMI_CEC

DP_ML_P<3>

94 OF 132 86 OF 103

98

6 7 8

25 26 27 28 30

34 37 40 42 47 48 49

52 53 55 59 63 64 69

70 71 72 73 74 81 84

85 86 88 99

101

98

6 7

31 35 49 50 51 58 72 73 74 84 99

101

98

6 7 8

25 26 27 28 30 34

37 40 42 47 48 49 52 53

55 59 63 64 69 70 71 72

73 74 81 84 85 86 88 99

101

98

IN OUT

IN

OUT

D

GS

NC

IN

G

D

S

G

D

S

THRM_PAD

POK1

REF

TON

EN_LDO

VREF3

VIN

LDO

LDOREFIN

BYP FB1 ILIM1

EN1

PVCC

SECFB

GND

PGND

LGATE2

BOOT2

PHASE2

UGATE2

EN2

POK2

SKIP*

OUT2

ILIM2

REFIN2

VCC

OUT1

LGATE1

PHASE1

UGATE1

BOOT1

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

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Apple Inc.

PAGE

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8 7 5 4 2 1

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

(Rb should be between 10K and 100K)

<Rb>

GPIO7

8A MAX OUTPUT

Vout = 1.8V

<Ra>

<Rb>

(Q9560 limit?) F = 500 KHZ

0

(SGND)

353S2312

1.553V

1

1.8V

Vout = 0.7V * (1 + Ra / Rb)

Vout = 1.05V

3.5A MAX OUTPUT (Q9510 limit?)

f = 400 kHz

(Internal 10-ohm path

Vout = 2(Req/(Ra+Req))

from PVCC to VCC)

FBVDDQ

<Ra>

(=PP1V8FB_S0_REG)

603

20%

10UF

X5R

6.3V

C9565

1

2

25V

10%

1UF

X5R 603-1

C9595

1

2

C9530

0.1UF

X7R

50V

10%

603-1

1

2

10% 25V

603-1

1UF

X5R

C9545

1

2

10.5K

1/16W

1%

402

MF-LF

R9520

1

2

R9521

20.0K

402

1/16W MF-LF

2

1

1%

10UF

20%

6.3V 603

X5R

C9515

1

2

MF-LF

1/16W 402

1%

R9535

2

1

75K

1

R9585

130K

1%

1/16W

402

MF-LF

2

2.2UH-8.0A

CRITICAL

PCMB065T-SM

L9510

1 2

POLY-TANT B2-SM

20%

330UF

1

2

CRITICAL

2.0V

C9510

C9560

220UF

2.5V

20%

CASE-B2-SM2

POLY-TANT

CRITICAL

1

2

74 88

8

74 83 87 88

73 74 88

8

74 83 87 88

CRITICAL

1.0UH-13A-5.6MOHM

PCMB065T-SM

L9560

1 2

X7R 603-1

10% 50V

0.1UF

C9580

1

2

1

2

CASE-B2

62UF

ELEC

11V

C9540

20%

CRITICAL

1

2

CASE-B2

62UF

ELEC

11V

C9590

CRITICAL

20%

PLACE_NEAR=L9560.2:3mm

XW9565

SM

12

NO STUFF

2

5%

100PF

C9520

1

402

CERM

50V

SM

XW9515

1 2

PLACE_NEAR=L9510.1:3mm

805

25V

10% X5R

10UF

C9500

1

2

SM

XW9500

1 2

10V

20%

402

CERM

0.1UF

C9585

1

2

127K

MF-LF

1%

1/16W

402

R9564

2

1

402-1

10V

1UF

10% X5R

C9503

1

2

C9501

10% X5R

402-1

1UF

10V

1

2

FB1V55

1/16W

1%

402

MF-LF

R9562

1

2

60.4K

SSM3K15FV

SOD-VESM-HF

Q9565

3

1

2

10%

0.001UF

C9561

1

2

402

CERM

50V

402

5%

4.7

1/16W MF-LF

R9500

12

10V X5R

1UF

10%

C9504

1

2

402-1

80 81

SIZ700DT

Q9510

CRITICAL

7

POWERPAIR-6X3.7

1

6

45

23

8

PWRPK-12128

CRITICAL

SIS426DN

Q9560

5

4

1 2 3

PWRPK-12128

CRITICAL

SIS426DN

Q9561

5

4

1 2 3

20

19

CRITICAL

ISL6236

QFN2

U9500

17 24

9

14 27

4

11

21

12 31

7 8

18 23 10 30

22

16 25

13 28

1

32

29

33

2

15 26

365

R9563

11.8K

1/16W MF-LF

1%

1

2

402

RES,1/16W,30.9K,1%,0402,LF

114S0362

R9562

1

FB1V35

1.05V GPU / 1V8 FB Power Supply

SYNC_MASTER=K17_REF

SYNC_DATE=06/17/2009

GND_P1V05P1V8_SGND

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM VOLTAGE=0V

GPU_P1V8_REFIN P1V8FB_TRIP

PM_ALL_GPU_PGOOD

P1V05GPU_TRIP

P1V05GPU_VFB

PP5V_S0

DIDT=TRUE

MIN_LINE_WIDTH=0.6MM

P1V8FB_LL

MIN_NECK_WIDTH=0.2MM SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

DIDT=TRUE

GATE_NODE=TRUE

P1V8FB_DRVL

FBVDD_ALTVO

GPUFB_VID_L

PP1V8_S0GPU_ISNS_R

P1V8_GPU_VSNS

PP2V_S0GPU_P1V8_REF

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=2V

PPBUS_G3H

PVIN_S0GPU_P1V05

P1V05GPU_DRVH

DIDT=TRUE

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

DIDT=TRUE

P1V8FB_DRVH

MIN_NECK_WIDTH=0.2MM GATE_NODE=TRUE

MIN_LINE_WIDTH=0.6MM

MIN_NECK_WIDTH=0.2MM

P1V05GPU_VBST

MIN_LINE_WIDTH=0.6MM

DIDT=TRUE

PP5V_S0GPU_P1V05P1V8_VCC

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V

P1V8FB_VBST

DIDT=TRUE

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V

PP5V_S0GPU_VREF

PM_ALL_GPU_PGOOD

PP1V05_S0GPU_ISNS_R

EG_RAIL4_EN

P1V05GPU_DRVL

DIDT=TRUE

MIN_NECK_WIDTH=0.2MM GATE_NODE=TRUE

MIN_LINE_WIDTH=0.6MM

EG_RAIL1_EN

P1V05S0_VSNS

SWITCH_NODE=TRUE

P1V05GPU_LL

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

DIDT=TRUE

95 OF 132 87 OF 103

6 7 8

23 42 48 53 55 69 70 71 73

102

6 7

51

6 7 8

40 50 66 67 68 70 71 83

7

51

IN

OUT

IN

OUT

IN IN

IN

IN OUT

D

SG

D

SG

IN

OUT

IN IN

IN

IN IN

IN

PB14B PB15A PB15B PB16A

PB17A

PT19A

PT16A

PB18B

PT7A

PR11B

PR24A PR24B

PR14A PR14B

PR12B

PR12A

PR11A

PR10B

PR10A

PR6A PR6B PR7A PR7B PR8A

PR9A PR9B

PR8B

PT28A

PT8B

PT8A

PT7B

PT9A PT9B

PL25A PL25B

PL15A

PL14B

PL14A

PL12B

PL11B PL12A

PL9A

PL8A PL8B

PL6B

PL7B

PL7A

PL6A

PB28B

PB27A

PB28A

PB27B

PB26A

PB7B

PB7A

VCCIO2

PT17B

PT17A

PT16B

PT15A

PT14B

PT20B

PT19B

CFG0

GND

GNDIO0

GNDIO1

GNDIO2

GNDIO3

GNDIO4

GNDIO5

GNDIO6

GNDIO7

LRC_GNDPLL

LRC_VCCPLL

PB18A

PB19A PB19B PB20A PB20B

PL2A PL2B

PR2A PR2B

PT14A

PT15B

PT18B

PT20A

TCK TDI TDO TMS TOE

ULC_GNDPLL

ULC_VCCPLL

VCCAUX

VCCIO0

VCCIO1

VCCIO3

VCCIO4

VCCIO5

VCCIO6

VCCIO7

VCCJ

PT18A

VCC

PT28B

PB26B

PL11A

PL10B

PL10A

PL9B

PB16B

PL15B

PB14A

PB17B

BANK6

BANK2 BANK0

BANK5 BANK7BANK4

BANK3 BANK1

(OD)

IN

IN OUT

IN

BI BI

BI

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

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GMUX CPLD

(Use open-drain PGOOD output to hold off the start of the GPU PWRSEQ until the first GPU rail’s source is valid)

Required Pulldowns

(Tie/strap low if EGPU doesn’t provide CLKREQ_L output, provide pullup to GPU rail if using CLKREQ_L output from EGPU)

Required Pullups

LVDS Receiver Termination

82 88 98

85 86

81 85 86

85 98

2

1

20%

402

X5R

4V

4.7UF

C9600

85 98

88

85 98

21

R9693

5%

1/16W

402

MF-LF

100K

21

R9691

100K

1/16W MF-LF

4025%

NO STUFF

21

R9683

402

10K

MF-LF1/16W

5%

21

R9682

1/16W

10K

5% 402

MF-LF

8

74 83 87

21

R9681

1/16W MF-LF

4025%

10K

1 2

1/16W MF-LF

4025%

R9680

1K

2

1

C9630

CERM 402

20% 10V

0.1UF

CERM

2

1

C9631

20%

402

10V

21

R9666

1/16W MF-LF1%402

100

SIGNAL_MODEL=EMPTY

PLACE_NEAR=U9600.H12:5mm

21

R9665

SIGNAL_MODEL=EMPTY

1%

1/16W MF-LF

402

100

PLACE_NEAR=U9600.G13:5mm

21

R9664

SIGNAL_MODEL=EMPTY

1%

1/16W MF-LF

100

402

PLACE_NEAR=U9600.G14:5mm

R9663

21

SIGNAL_MODEL=EMPTY

1%

402

100

MF-LF1/16W

PLACE_NEAR=U9600.F12:5mm

8

75

21

R9656

SIGNAL_MODEL=EMPTY

1%

1/16W MF-LF

402

100

PLACE_NEAR=U9600.B2:5mm

21

R9662

SIGNAL_MODEL=EMPTY

1%

1/16W MF-LF

402

100

PLACE_NEAR=U9600.E14:5mm

21

R9661

SIGNAL_MODEL=EMPTY

1%

1/16W MF-LF

402

100

PLACE_NEAR=U9600.D13:5mm

21

R9660

SIGNAL_MODEL=EMPTY

100

402

MF-LF1/16W

1%

PLACE_NEAR=U9600.J12:5mm

21

R9655

SIGNAL_MODEL=EMPTY

1%

1/16W MF-LF

402

100

PLACE_NEAR=U9600.G3:5mm

1

100

2

SIGNAL_MODEL=EMPTY

1%

1/16W MF-LF

402

PLACE_NEAR=U9600.E1:5mm

R9651 R9652

21

SIGNAL_MODEL=EMPTY

1%

MF-LF

402

100

1/16W

PLACE_NEAR=U9600.E3:5mm

R9653

21

SIGNAL_MODEL=EMPTY

1%

1/16W MF-LF

402

100

PLACE_NEAR=U9600.G1:5mm

21

R9654

SIGNAL_MODEL=EMPTY

1/16W MF-LF

402

100

1%

PLACE_NEAR=U9600.G2:5mm

PLACE_NEAR=U9600.H3:5mm

21

R9650

SIGNAL_MODEL=EMPTY

1%

1/16W MF-LF

402

100

2

1

R9679

402

MF-LF

1%

10K

1/16W

SILK_PART=GMUX_RST

NO STUFF

27

18 88 93

2

1

R9674

4.7K

1/16W

5% MF-LF

402

2

1

R9673

402

1/16W MF-LF

5%

4.7K

2

1

R9672

MF-LF

4.7K

5% 1/16W

402

2

1

R9671

MF-LF

4.7K

5% 1/16W

402

FERR-220-OHM

21

L9621

0402

L9620

FERR-220-OHM

21

0402

8

1

2

6

Q9607

SSM6N15FEAPE

SOT563

4

5

3

Q9607

SOT563

SSM6N15FEAPE

1/16W

2

1

R9676

100K

402

5% MF-LF

2

1

R9675

NO STUFF

MF-LF

1/16W 402

0

5%

18 88 93

2

1

R9678

1/16W

402

5%

MF-LF

4.7K

25 27 46 74

6

5

4

3

2

1

8

7

J9600

CRITICAL

1909782

M-RT-SM

GMUX_JTAG_CONN

1K

5%

MF-LF1/16W

R9684

402

21

8

18 88 93

1 2

402

5%

0

1/16W MF-LF

R9600

R9610

MF-LF

1/16W

0

5%

402

21

GMUXPLL_3V3

1 2

402

R9612

MF-LF

1/16W

0

5%

GMUXPLL_1V8

1 2

402

R9611

5%

0

1/16W MF-LF

18 88 93

K12

F2

C3M1N5M3M9

M12

F13

C14

A12

B7

B5

M8

J14

J2

C11

P8

N11

J13

J3C4B11

A4

B4

K2

L12

K13

L13

K14

A5

C5

B3

A1

A3

A2

B13

B12

A11

A10

B10

C10

A9

B9

A8

C9

C8

A7

A6

C7

B6

G14

F14

F12

E12

E14

D14

D13

D12

B14

A14

N13

N14

M13

L14

J12

H14

H12

H13

G13

G12

G1

F1

E3

D2

E1

D1

D3

C2

B2

B1

P1

N1

L2

K3

L3

L1

H3

H1

G3

H2

G2

F3

N2

P2

P14

N12

P13

P12

M10

P10

N9

P9

N8

N7

M7

P7

M6

P6

M5

P5

M4

N3

N4

P4

P11

M11

E2C1M2

P3

N6

N10

M14

E13

C13

C12

C6

B8

J1

K1

U9600

CSBGA

XP25-5

CRITICAL

OMIT

A13

18 88 93

27

20

6

17 46 48 94

6

17 46 48 94

6

17 46 48 94

6

17 46 48 94

NO STUFF

2

1

402

10K

1%

R9647

1/16W MF-LF

6

17 46 48 94

84 88

81

8

17

73 74 87 88

74 83 88

73 74 88

74 87 88

8

75 88

85 88

85

2

1

C9604

0.1UF

20% 10V CERM 402

C9605

10V

2

1

CERM

20%

0.1UF

402

85 88

6

88 89

8

90

2

1

R9641

1/16W MF-LF

10K

NO STUFF

402

1%

2

1

C9606

20%

402

0.1UF

10V CERM

0.1UF

C9607

2

1

20% CERM

10V 402

C9608

2

1

0.1UF

10V

20%

402

CERM

C9609

10V

0.1UF

2

1

402

20% CERM

2

1

0.1UF

10V

20% CERM

402

C9610

2

1

C9611

0.1UF

CERM 402

20% 10V

2

1

C9621

CERM 402

20% 10V

0.1UF

C9622

2

1

0.1UF

402

10V

20% CERM

C9612

0.1UF

20%

2

1

CERM

10V 402

10V

C9613

2

20% CERM

402

0.1UF

1

2

1

R9646

10K

NO STUFF

402

1% 1/16W MF-LF

1

C9623

0.1UF

10V 402

2

CERM

20%

C9624

0.1UF

CERM

2

1

402

20% 10V

2

C9614

402

1

10V

20%

0.1UF

CERM

2

1

C9625

402

CERM

10V

0.1UF

20%

402

10V

2

1

C9615

CERM

20%

0.1UF

CERM

2

1

C9616

402

10V

20%

0.1UF

2

1

C9626

10V

20%

0.1UF

CERM 402

10V

C9627

0.1UF

2

1

402

CERM

20%

0.1UF

CERM

20%

C9617

2

1

10V 402

2

1

R9640

1/16W

1%

402

MF-LF

10K

2

1

C9628

10V

20%

0.1UF

402

CERM

C9629

2

1

CERM

0.1UF

20% 10V

402

80 81

8

18

80 81

8

18

82 88 98

2

1

R9645

MF-LF 402

10K

1/16W

1%

82 88 98

SYNC_MASTER=K17_REF

Graphics MUX (GMUX)

SYNC_DATE=06/24/2009

PP3V3_S0

PP1V8_S0

LPC_AD<3>

LPC_AD<0>

LVDS_IG_A_DATA_P<0>

LVDS_IG_B_DATA_P<2>

GND GND

LCD_BKLT_EN

JTAG_GMUX_TMS

PP1V8_S0

PP3V3_S0

GMUX_VSYNC

EG_PWRSEQ_EN

PP3V3_S0

GMUX_DEBUG_RESET_L

LVDS_IG_A_DATA_N<1> LVDS_IG_A_DATA_P<2>

EG_RAIL3_EN

EG_RAIL4_EN

LVDS_EG_B_DATA_N<0>

DP_HOTPLUG_DET

LVDS_EG_B_DATA_N<2>

LVDS_EG_A_DATA_N<2>

ALL_SYS_PWRGD

PEX_CLKREQ_L

LVDS_IG_B_DATA_P<1>

PP3V3_S0

GMUX_RESET_L

LVDS_DDC_SEL_IG

EG_RAIL2_EN

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

PP3V3R1V8_S0_GMUX_ULC_VCCPLL

VOLTAGE=3.3V

DP_MUX_SEL_EG

LVDS_EG_A_DATA_N<2>

LVDS_B_DATA_N<1>

LVDS_B_DATA_P<1>

LVDS_B_DATA_N<0>

PP3V3_S0

GMUX_TOE GMUX_CFG0

LVDS_EG_B_DATA_N<0>

LVDS_EG_A_DATA_P<2>

GMUX_S3_PD_GND

LVDS_DDC_SEL_EG

LVDS_EG_B_DATA_N<1>

LVDS_EG_B_DATA_P<0>

LVDS_DDC_SEL_EG

EG_RAIL3_EN

EG_RAIL1_EN

EG_RAIL4_EN

JTAG_GMUX_TCK JTAG_GMUX_TDI

JTAG_GMUX_TDO

LCD_BKLT_PWM

EG_RESET_L

LVDS_IG_B_DATA_P<1>

LVDS_IG_A_DATA_P<1> LVDS_IG_A_DATA_P<2> LVDS_IG_A_DATA_N<2>

LVDS_IG_B_DATA_P<0> LVDS_IG_B_DATA_N<0>

LVDS_EG_A_CLK_P LVDS_EG_A_CLK_N

LVDS_EG_B_DATA_P<1> LVDS_EG_B_DATA_N<1>

LVDS_EG_B_DATA_P<0>

LVDS_IG_B_DATA_N<2>

LVDS_IG_A_DATA_N<1>

LVDS_IG_A_CLK_N

LVDS_IG_B_DATA_N<1>

LVDS_IG_A_DATA_N<0>

LVDS_EG_B_DATA_P<2>

LVDS_EG_A_DATA_P<1>

LVDS_EG_A_DATA_P<0>

PP3V3_S3

GMUX_S3_PD_EN

LCD_PWR_EN

LVDS_EG_A_DATA_N<1>

LVDS_EG_A_DATA_N<0>

LVDS_IG_A_CLK_P

LVDS_DDC_SEL_IG

LVDS_A_DATA_P<2>

LVDS_B_DATA_P<0>

LVDS_EG_B_DATA_N<2>

LVDS_IG_BKL_ON EG_BKLT_EN

LVDS_IG_PANEL_PWR

LVDS_EG_A_CLK_N

LVDS_EG_A_CLK_P

LVDS_EG_B_DATA_P<2>

LVDS_EG_B_DATA_P<1>

LVDS_EG_A_DATA_P<0> LVDS_EG_A_DATA_N<0> LVDS_EG_A_DATA_P<1> LVDS_EG_A_DATA_N<1> LVDS_EG_A_DATA_P<2>

LVDS_B_DATA_P<2> LVDS_B_DATA_N<2>

PM_ALL_GPU_PGOOD

TP_LVDS_MUX_SEL_EG

LVDS_IG_A_CLK_N

LVDS_IG_B_DATA_N<1> LVDS_IG_A_CLK_P

LVDS_IG_A_DATA_P<1>

TP_GMUX_PL6B

LVDS_IG_A_DATA_N<0>

LVDS_IG_A_DATA_P<0>

GMUX_INT

LPC_CLK33M_GMUX

LPCPLUS_RESET_L

LCD_BKLT_PWM

LVDS_A_DATA_N<0>

LVDS_B_CLK_N

GND

LVDS_A_DATA_N<2>

LVDS_IG_B_DATA_P<2> LVDS_IG_B_DATA_N<2>

DP_CA_DET

EG_PWRSEQ_EN

GND

LVDS_A_DATA_P<1>

LVDS_IG_B_DATA_N<0>

LVDS_IG_B_DATA_P<0>

LVDS_IG_A_DATA_N<2>

EG_RAIL1_EN

EG_RAIL2_EN

EG_RESET_L

DP_MUX_SEL_EG

DP_MUX_EN

JTAG_GMUX_TMS

JTAG_GMUX_TDI

DP_CA_DET_EG

PEG_CLKREQ_L

GMUX_DEBUG_RESET_L LVDS_A_CLK_P

LVDS_A_DATA_P<0>

LVDS_A_DATA_N<1>

LVDS_A_CLK_N LVDS_B_CLK_P

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

PP3V3R1V8_S0_GMUX_LRC_VCCPLL

TP_GMUX_PL14B

LPC_FRAME_L

LPC_AD<2>

LPC_AD<1>

LCD_PWR_EN

JTAG_GMUX_TCK

GMUX_PL6A

JTAG_GMUX_TDO

PP3V3_S0_GMUX_R

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.09 mm VOLTAGE=3.3V

EG_LCD_PWR_EN

PP1V8_S0_GMUX_R

MIN_NECK_WIDTH=0.09 mm VOLTAGE=1.8V

MIN_LINE_WIDTH=0.4 mm

PP1V2_S0

PP3V3R1V8_S0_GMUX

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

96 OF 132 88 OF 103

6 7 8 25 26 27 28 30 34 37 40 42 47 48 49 52

53 55 59 63 64 69 70 71 72 73 74 81 84

85 86 88 99

101

6 7

12 16 72 73 88

101

18 88 93

19 88

6 7

12 16 72

73 88

101

6 7 8

25 26 27 28 30

34 37 40 42 47

48 49 52 53 55

59 63 64 69 70

71 72 73 74 81

84 85 86 88 99

101

88

74 83 88

73 74 87 88

82 88 98

6 7 8

25 26 27 28 30 34 37 40 42 47 48

49 52 53 55 59 63 64 69 70 71 72 73 74

81 84 85 86 88 99

101

85 88

6 7 8

25 26 27 28

30 34 37 40 42 47

48 49 52 53 55 59

63 64 69 70 71 72

73 74 81 84 85 86

88 99

101

82 88 98

85 88

20 25 88

19 88

20 88

6

88 89

8

75 88

18 88 93

18 88 93 18 88 93

82 88 98 82 88 98

82 88 98

18 88 93

82 88 98

6 7

17 20

31 32 33 34 35 36 49 50 51 54 55 56 72

74

102 103

84 88

82 88 98

18 88 93

74 87 88

73 74 88

19 88

20 25 88

20 88

6 7

73

OUT

IN

VIN

VDC2

VDC1

EN

WAKE

PWM

COMP

OVP

VOUT

SWB

SWA

FAIL

THRM

PGNDB

PGNDA

GND

ISET

CH1

CH2

CH3

CH4

CH5

CH6

PAD

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

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PAGE TITLE

C

A

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

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8 7 5 4 2 1

KV: C9718 AND C9719 FOR 17" PANEL

OVP = Vovp * (1 + Ra/Rb)

<Ra>

<Riset>

353S2758

ACTUAL: ISET = 24.7mA, OVP = 49.5V

Target: ISET = 25mA, OVP = 50V

(SGND)

<Rb>

ISET = 153mA / <Riset>

VOVP = 6.9V +/- 0.35V

f = 300(TBD)kHz

KV: WAKE AND EN WIRING CHANGED FROM REF SCHEMATIC AS QFET IS PRESENT ON P.98

17 Inch Panel (14 LEDs per string)

PLACE_NEAR=U9700.8:3mm

NOSTUFF

100PF

50V

CERM

2

1

5%

402

C9722

2

1

C9724

CERM

402

100PF

50V

5%

NOSTUFF

PLACE_NEAR=U9700.10:3mm

NOSTUFF

C9723

100PF

CERM

2

1

5% 50V

402

PLACE_NEAR=U9700.9:3mm

PLACE_NEAR=U9700.12:3mm

C9726

2

1

402

5%

CERM

50V

100PF

NOSTUFF

100PF

C9725

NOSTUFF

50V

2

1

5% CERM

402

PLACE_NEAR=U9700.11:3mm

XW9700

1

OMIT

SM

PLACEMENT_NOTE=PLACE XW9700 FAR FROM THE NOISY PINS 3 AND 4

2

10.2

R9717

1/16W

21

402

1%

MF-LF

21

R9718

402

10.2

1%

MF-LF

1/16W

21

R9720

MF-LF

1/16W

1%

10.2

402

21

R9721

MF-LF

1/16W

402

1%

10.2

21

R9722

1%

MF-LF

10.2

402

1/16W

402

21

1%

MF-LF

10.2

1/16W

R9719

NOSTUFF

MF-LF

1/16W

2

1

402

5%

0

R9702

5%

10

1/16W

1

2

402

MF-LF

R9730

1

0.020

43

2

MF-LF

805

0.25W

1%

CRITICAL

R9700

57 99

22K

R9726

5%

MF-LF

1

2

402

1/16W

NOSTUFF

PLACE_NEAR=C9717.2:3mm

2

XW9701

SM

OMIT

1

2

C9705

10% 16V

56NF

402

CER

402

2

1

1% 1/16W MF

1.8K

R9705

1000PF

50V 603

C0G-CERM

C9727

5%

1

2

PLACE_NEAR=U9700.1:3mm

C9713

0.1UF

402

25V X5R

10%

PLACE_NEAR=L9710.1:8mm

1210

10%

2.2UF

X7R-CERM

100V

C9718

1

2

CRITICAL CRITICAL

C9719

10%

2.2UF

X7R-CERM

100V 1210

1

2

MM3Z2V4ST1G

D9702

2 1

SOD323

NOSTUFF

C9728

NOSTUFF

100PF

5%

50V

CERM

402

1

2

1%

162K

1

2

402

R9716

1/16W MF-LF

50V 402

1

2

5%

CERM

47PF

C9735

PLACE_NEAR=R9725.1:3mm

CRITICAL

D9710

PLACE_NEAR=L9710.2:3mm

DFLS260

POWERDI-123

21

R9725

1/16W MF-LF

1%

402

2 1

200

L9710

33UH-1.8A-110MOHM

CRITICAL

1217AS-2SM

21

10% X7R-CERM

100V 1210

1

2

2.2UF

C9715

CRITICAL

10%

2.2UF

C9716

1210

1

CRITICAL

100V X7R-CERM

2

6

84

6

84

6

84

6

84

6

84

6

84

2

X5R

CRITICAL

805

10UF

10% 25V

1

C9710

PLACE_NEAR=L9710.1:8mm

20%

X5R-CERM

2

1

2.2UF

10V 402

C9700

402

2

2.2UF

1

20%

C9701

X5R-CERM

10V

1M

2

1

1%

402

R9715

1/16W MF-LF

C9711

1UF

10% X5R

603-1

2

1

25V

PLACE_NEAR=U9700.1:8mm

R9710

402

1% 1/16W MF-LF

2

1

6.19K

25V

5%

CERM

402

1

2

220PF

C9706

6

88

PLACE_NEAR=D9710.2:5mm

1

1000PF

2

C9717

100V

10% X7R

603

420

MC34845BEP

6

1

12

U9700

LLP

11

10

9

8

7

15

19

13

25

14

3

24

22

17

16 18

23

21

CRITICAL

2

5

MIN_LINE_WIDTH=0.5 mm

PLACE_NEAR=U9700.7:3mm

C9721

100PF

5%

2

50V CERM

1

402

NOSTUFF

LCD Backlight Driver (MC34845)

SYNC_DATE=12/16/2009

SYNC_MASTER=K17_VEMURI

GND_LCDBKLT_SGND

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.24 MM VOLTAGE=0V

LCDBKLT_COMP_RC

MIN_LINE_WIDTH=0.5 MM

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.38 MM

PPVOUT_S0_LCDBKLT_SW

VOLTAGE=50V

DIDT=TRUE

MIN_NECK_WIDTH=0.24 MM

PPVOUT_S0_LCDBKLT

VOLTAGE=50V

MIN_LINE_WIDTH=0.5 MM

MIN_LINE_WIDTH=0.2 MM

LCDBKLT_ISET

BKL_MC_CH6

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

GND_LCDBKLT_PGND

VOLTAGE=0V

MIN_NECK_WIDTH=0.4 MM

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.3 MM

LCDBKLT_VIN

MIN_LINE_WIDTH=0.2 MM

LCDBKLT_COMP

ISNS_LCDBKLT_N

ISNS_LCDBKLT_P

LED_RETURN_3

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

LED_RETURN_2

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.20 mm

LED_RETURN_4

MIN_LINE_WIDTH=0.5 mm

LED_RETURN_6

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

LED_RETURN_1

MIN_NECK_WIDTH=0.20 mm

LED_RETURN_5

MIN_LINE_WIDTH=0.5 mm

GND_LCDBKLT_PGND

PPBUS_S0_LCDBKLT_PWR

PP5V5_S0_LCDBKLT

VOLTAGE=5.5V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.3 MM

PP2V5_S0_LCDBKLT

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=2.5V

BKL_MC_CH5

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

LCDBKLT_FAIL

MIN_NECK_WIDTH=0.20 mm

BKL_MC_CH1

BKL_MC_CH4

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

BKL_MC_CH3

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

BKL_MC_CH2

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

LCDBKLT_OVP

LVDS_BKL_PWM_RC

LCD_BKLT_PWM

VOLTAGE=6V

MIN_NECK_WIDTH=0.38 MM

MIN_LINE_WIDTH=0.5 MM

PPVIN_BKL

97 OF 132 89 OF 103

6

57 84

89

90

D

SG

D

SG

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

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PAGE TITLE

C

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

CHANNEL

LOADING

RDS(ON)

MOSFET

PPBUS S0 LCDBkLT FET

P-TYPE

0.4 A (EDP)

43 mOhm @4.5V

FDC638APZ

.

21

F9800

3AMP-32V-467

603-HF

2

1

R9808

1/16W MF-LF

1%

301K

402

2

1

R9809

MF-LF

1/16W

402

147K

1%

2

1

C9802

X5R 402

10% 16V

0.1UF

4

3

6521

Q9806

SSOT6-HF

CRITICAL

FDC638APZ_SBMS001

1

2

6

Q9807

SOT563

SSM6N15FEAPE

4

5

3

Q9807

SOT563

SSM6N15FEAPE

8

88

27

2

1

R9840

402

1/16W

5%

4.7K

MF-LF

LCD Backlight Support

SYNC_MASTER=K20A_MLB SYNC_DATE=03/26/2009

PBUS_S0_LCDBKLT_EN_L

BKLT_EN_L

MIN_NECK_WIDTH=0.375 MM

MIN_LINE_WIDTH=0.5 MM

PPBUS_S0_LCDBKLT_PWR

VOLTAGE=10V

PBUS_S0_LCDBKLT_EN_DIV

PPBUS_S0_LCDBKLT_FUSED

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.375 MM VOLTAGE=10V

BKLT_PLT_RST_L

PPVIN_S0_LCDBKLT

LCD_BKLT_EN

98 OF 132 90 OF 103

89

8

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

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PAGE TITLE

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A

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Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

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345678

D

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8 7 5 4 2 1

(FSB_CPURST_L)

NET_TYPE

PHYSICAL

SPACING

ELECTRICAL_CONSTRAINT_SET

CPU Net Properties

NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.

Most CPU signals with impedance requirements are 50-ohm single-ended. Some signals require 27.4-ohm single-ended impedance.

PCI-Express

SOURCE: Calpella SFF DG (DG-407364_v1.5), Section 2.8

CPU Signal Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.4

CPU Constraints

SYNC_DATE=06/09/2009

SYNC_MASTER=K17_WFERRY

?

PCIE

*

=3X_DIELECTRIC

?

CLK_PCIE

*

20 MIL

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

=85_OHM_DIFF =85_OHM_DIFF* =85_OHM_DIFF

PCIE_85D

=90_OHM_DIFF

=90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF

=90_OHM_DIFF =90_OHM_DIFF*

CLK_PCIE_90D

PCIE

?

TOP,BOTTOM

=4X_DIELECTRIC

CPU_VCCSENSE

*

?

25 MIL

=2:1_SPACING

CPU_ITP

*

?

=27P4_OHM_SE

CPU_27P4S

*

=27P4_OHM_SE

7 MIL

=27P4_OHM_SE =27P4_OHM_SE

7 MIL

*

?

CPU_COMP

20 MIL

*

?

8 MIL

CPU_8MIL

*

?

CPU_AGTL

=STANDARD

=50_OHM_SE=50_OHM_SE

=STANDARD

CPU_50S

=STANDARD*

=50_OHM_SE =50_OHM_SE

TOP,BOTTOM

=2x_DIELECTRIC

?

CPU_AGTL

=55_OHM_SE

*

CPU_55S

=55_OHM_SE =55_OHM_SE =55_OHM_SE

=STANDARD=STANDARD

CPU_VCCSENSE

CPU_27P4S

CPU_VTTSENSE_N

CPU_VCCSENSE

PEG_D2R_C_N<15..0>

PCIEPCIE_85D

PEG_D2R_C_P<15..0>

PCIEPCIE_85D

PEG_D2R_N<15..0>

PCIE_85D PCIE

PEG_D2R_P<15..0>

PCIE

PEG_D2R

PCIE_85D

PEG_R2D_C_N<15..0>

PCIEPCIE_85D

PEG_R2D_C_P<15..0>

PEG_R2D

PCIEPCIE_85D

PEG_R2D_N<15..0>

PCIE_85D PCIE

PEG_R2D_P<15..0>

PCIEPCIE_85D

CPU_27P4S

CPU_VCCSENSE

CPU_VCCSENSE_P

CPU_VCCSENSE

CPU_27P4S

CPU_VCCSENSE CPU_VCCSENSE

CPU_VCCSENSE_N

FDI_LSYNC<1..0>

CPU_50S

CPU_AGTL

PCIE_85DFDI_DATA

FDI_DATA_P<7:0>

PCIE

DMI_S2N

PCIE_85D

DMI_S2N_P<3:0>

PCIE

PCIE_85DFDI_DATA

FDI_DATA_N<7:0>

PCIE

CPU_50S

CPU_AGTL

FDI_INT

PCIE_85D

DMI_N2S

PCIE

DMI_N2S_N<3:0>

DMI_S2N

PCIEPCIE_85D

DMI_S2N_N<3:0>

PCIE_85D

DMI_N2S

DMI_N2S_P<3:0>

PCIE

CPU_50S

FDI_FSYNC<1..0>

CPU_AGTL

CPU_50S

CPU_PWRGD

CPU_50S

TP_CPU_VTT_SELECT

CPU_AGTL

CPU_50S

CPU_PROCHOT_L

CPU_AGTL

CPU_CATERR_L

CPU_50S

CPU_AGTLCPU_CATERR_L

CPU_CFG<17..0>

CPU_ITPCPU_50SCPU_CFG

CPU_SM_RCOMP2

CPU_COMP

CPU_27P4S

CPU_SM_RCOMP

CPU_SM_RCOMP0

CPU_COMP

CPU_27P4S

CPU_SM_RCOMP

CPU_SM_RCOMP1

CPU_COMP

CPU_27P4S

CPU_AGTL

CPU_50S

PM_EXT_TS_L<1>

CPU_AGTL

CPU_50S

PM_EXT_TS_L<0>

CPU_ITP

XDP_PREQ_L

CPU_50S

XDP_PREQ_l

XDP_PRDY_L

CPU_ITPCPU_50S

XDP_BDRESET_L

CPU_ITP

XDP_DBRESET_L

CPU_50S

XDP_XPU_PWRGOOD

CPU_ITPCPU_50S

XDP_CPUPWRGD

CPU_VTT_S0_PGOOD

CPU_AGTL

CPUVTTS0_PGOOD

CPU_50S

CPU_AGTL

PM_SYNC CPU_50S

PM_SYNC

CPU_50S

CPU_AGTL

PM_MEM_PWRGD

CPU_PECI PCIE

CPU_50S

CPU_PECI

CPU_50S

CPU_AGTLFSB_CPURST_L

FSB_CPURST_L

CPU_8MIL

PM_THRMTRIP_L

CPU_50S

PM_THRMTRIP_L

GFXIMVP_IMON

CPU_50S

CPU_AGTL

GFX_VR_EN

CPU_AGTL

CPU_50S

GFX_DPRSLPVR

PM_DPRSLPVR

CPU_50S

CPU_AGTL

GFX_VID<6..0>

CPU_8MIL

CPU_55S

CPU_27P4S

CPU_VCCSENSE

GFX_VSENSE_N

CPU_VCCSENSE

CPU_27P4S

GFX_VSENSE_P

CPU_VCCSENSE

CPU_27P4S

CPU_VTTSENSE_P

CPU_VCCSENSE

CPU_AGTL

CPU_50S

CPUIMVP_IMON

CPU_55S

CPU_VID<6..0>

CPU_8MIL

CPU_50S

XDP_CPURST_L

CPU_ITP

CPU_50S

XDP_BPM_L

XDP_BPM_L<7>

CPU_ITP

CPU_50S

XDP_BPM_L

XDP_BPM_L<6..0>

CPU_ITP

XDP_TRST_L

CPU_50S

XDP_TRST_L

CPU_ITP

CPU_50SXDP_TMS CPU_ITP

XDP_TMS

CPU_50S CPU_ITPXDP_TCK

XDP_TCK

CPU_50S CPU_ITPXDP_TDI

XDP_TDI

CPU_50S CPU_ITP

XDP_TDO

CPU_27P4S

CPU_COMP CPU_COMP

CPU_COMP0

CPU_27P4S

CPU_COMP CPU_COMP

CPU_COMP1

CPU_27P4S

CPU_COMP

CPU_COMP2

CPU_COMP

CPU_27P4S

CPU_PEG_RBIAS

CPU_27P4S

CPU_COMP

CPU_COMP3

CPU_COMP

CPU_27P4S

CPU_PEG_COMP

PM_DPRSLPVR

CPU_50S

CPU_AGTL

PM_DPRSLPVR

PCIE_CLK100M_CPU

PCIE_CLK100M_CPU_N

CLK_PCIE_90D CLK_PCIE

CPU_55S

CPU_PSI_L

CPU_8MIL

FSB_CLK_ITP

CLK_PCIE

FSB_CLK133M_ITP_N

CLK_PCIE_90D

PCIE_CLK100M_CPU

PCIE_CLK100M_CPU_P

CLK_PCIE_90D CLK_PCIE

FSB_CLK_ITP

CLK_PCIE

FSB_CLK133M_ITP_P

CLK_PCIE_90D

FSB_CLK133M_CPU_N

CLK_PCIECLK_PCIE_90D

FSB_CLK_CPU

CLK_PCIE_90D

FSB_CLK133M_CPU_P

CLK_PCIE

FSB_CLK_CPU

100 OF 132

91 OF 103

12 71

75

8 9

75

8 9

75

8

75

8

75

12 69

9

18

9

18

9

18

9

18

9

18

9

18

9

18

9

18

9

18

10 20 25

8

12

10 47 69

10

8 9

25

10

10 47

10 25

10 25 27

10 25

10 71

10 18

10 18 31

10 20

10 25

10 20 47

13 70

8

13

13 70

12 71

12 50 69

8

12 15

25

10 25

25

10

9

10

9

12 15 69

10 17

12 15 69

10 25

10 17

10 25

10 20

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_PHYSICAL_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

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PAGE TITLE

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

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8 7 5 4 2 1

NET_TYPE

SPACING

PHYSICAL

Memory Bus Constraints

Maximum length of any signal from die pad to SODIMM pad is 139.7mm, from procesor ball to SODIMM pad is 114.3mm.

Need to support MEM_*-style wildcards!

SOURCE: Calpella SFF Platform DG, Rev 1.5 (#407364), Section 2.2

A/BA/CMD signals should be matched within [CLK-12.7mm] to [CLK+12.7mm] of CLK pairs. DQ/DQS/A/BA/cmd signal spacing is 4x dielectric, CLK is 5x dielectric.

DQS to clock matching should be within [CLK-12.7mm] and [CLK+25.4mm].

CONTROL signals should be matched within [CLK-12.7mm] to [CLK+0.0mm] of CLK pairs.

DQS intra-pair matching should be within 0.127mm, no inter-pair matching requirement.

Memory Bus Spacing Group Assignments

CLK intra-pair matching should be within 0.127mm, inter-pair matching should be within 0.508mm.

DQ/DM signals should be matched within 0.508mm of associated DQS pair.

DDR3:

ELECTRICAL_CONSTRAINT_SET

Memory Net Properties

Memory Constraints

SYNC_MASTER=K17_WFERRY

SYNC_DATE=06/09/2009

MEM_DATA

MEM_DATA2DATA

*

MEM_DATA

MEM_DATA2MEM

MEM_DATA

*

MEM_DQS

=85_OHM_DIFF

MEM_85D

=85_OHM_DIFF

* =85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF =85_OHM_DIFF

=40_OHM_SE=40_OHM_SE =40_OHM_SE=40_OHM_SE

=STANDARD* =STANDARD

MEM_40S

=37_OHM_SE =37_OHM_SE =37_OHM_SE=37_OHM_SE

MEM_37S

=STANDARD=STANDARD*

* =72_OHM_DIFF

=72_OHM_DIFF =72_OHM_DIFF =72_OHM_DIFF

=72_OHM_DIFF =72_OHM_DIFF

MEM_72D

*

?

=3:1_SPACING

MEM_CMD2MEM

MEM_DATA2DATA

?

*

=1.5:1_SPACING

MEM_DATA2MEM

*

?

=3:1_SPACING

?

MEM_2OTHER

*

25 MILS

MEM_DQS2MEM

MEM_DATA

*

MEM_DQS

MEM_DQS2MEM

MEM_DQS

*

MEM_DQS

MEM_DQS MEM_CMD

MEM_DQS2MEM

*

MEM_DQS2MEM

MEM_DQS

MEM_CTRL

*

MEM_CLK

MEM_DQS2MEM

MEM_DQS

*

MEM_CTRL

*

MEM_DQS

MEM_CTRL2MEM

*

MEM_CTRL MEM_DATA

MEM_CTRL2MEM

*

MEM_CTRL

MEM_CMD

MEM_CTRL2CTRL

*

MEM_CTRL MEM_CTRL

MEM_CTRL

*

MEM_CLK

MEM_CTRL2MEM

MEM_CLK2MEM

MEM_CLK

*

MEM_CMD

*

MEM_CLK

MEM_DATA

MEM_CLK2MEM MEM_CLK2MEM

MEM_CLK

*

MEM_DQS

MEM_CLK2MEM

MEM_CLK

*

MEM_CTRL

MEM_CLK2MEM

MEM_CLK

*

MEM_CLK

?

*

MEM_DQS2MEM

=3:1_SPACING

MEM_CMD2CMD

*

=1.5:1_SPACING

?

MEM_2OTHER

MEM_CMD

**

MEM_2OTHER

* *

MEM_DATA

MEM_2OTHER

MEM_DQS

**

MEM_2OTHER

* *

MEM_CTRL

MEM_2OTHER

MEM_CLK

**

MEM_DATA

*

MEM_CMD

MEM_DATA2MEM

MEM_DATA

*

MEM_CTRL

MEM_DATA2MEM

MEM_DATA

MEM_CLK

*

MEM_CMD2MEM

MEM_CMD

*

MEM_DQS

*

MEM_CMD2MEM

MEM_DATA

MEM_CMD

*

MEM_CMD

MEM_CMD2CMD

MEM_CMD

*

MEM_CMD2MEM

MEM_CTRL

MEM_CMD

*

MEM_CLK

MEM_CMD2MEM

?

*

=3:1_SPACING

MEM_CTRL2CTRL

*

?

MEM_CTRL2MEM

=2.5:1_SPACING

=4:1_SPACING

MEM_CLK2MEM

?

*

=50_OHM_SE

=STANDARD* =STANDARD

=50_OHM_SE =50_OHM_SE =50_OHM_SE

MEM_50S

MEM_37S

MEM_A_CS_L<3..0>

MEM_CTRL

MEM_A_CNTL

MEM_37S

MEM_A_ODT<3..0>

MEM_CTRL

MEM_A_CNTL

MEM_40S MEM_CMD

MEM_A_A<15..0>

MEM_A_CMD

MEM_40S MEM_CMD

MEM_A_CMD

MEM_A_BA<2..0>

MEM_40S MEM_CMD

MEM_A_CMD

MEM_A_RAS_L

MEM_40S

MEM_A_CAS_L

MEM_A_CMD

MEM_CMD MEM_CMDMEM_40S

MEM_A_WE_L

MEM_A_CMD

MEM_A_DQ<7..0>

MEM_A_DQ_BYTE0

MEM_DATA

MEM_50S

MEM_A_DQ<15..8>

MEM_A_DQ_BYTE1

MEM_DATA

MEM_50S

MEM_B_CLK

MEM_72D

MEM_B_CLK_N<5..0>

MEM_CLK

MEM_B_CNTL

MEM_37S

MEM_CTRL

MEM_B_CKE<3..0>

MEM_37S

MEM_CTRL

MEM_B_CNTL

MEM_B_ODT<3..0>

MEM_CMDMEM_40S

MEM_B_BA<2..0>

MEM_B_CMD

MEM_40S MEM_CMD

MEM_B_CAS_L

MEM_B_CMD

MEM_B_DQ<47..40>

MEM_DATA

MEM_B_DQ_BYTE5 MEM_50S

MEM_37S

MEM_CTRL

MEM_B_CNTL

MEM_B_CS_L<3..0>

MEM_40S

MEM_B_A<15..0>

MEM_CMD

MEM_B_CMD

MEM_DQS

MEM_B_DQS_P<4>

MEM_B_DQS4

MEM_85D

MEM_DQS

MEM_B_DQS7

MEM_B_DQS_N<7>

MEM_85D

MEM_40S MEM_CMD

MEM_B_RAS_L

MEM_B_CMD

MEM_72D MEM_CLK

MEM_A_CLK

MEM_A_CLK_P<5..0>

MEM_72D MEM_CLK

MEM_A_CLK

MEM_A_CLK_N<5..0>

MEM_DQS

MEM_A_DQS_N<1>

MEM_A_DQS1

MEM_85D

MEM_A_DQ_BYTE0

MEM_A_DM<0>

MEM_DATA

MEM_50S

MEM_DATA

MEM_A_DQ<63..56>

MEM_A_DQ_BYTE7 MEM_50S

MEM_DATA

MEM_A_DQ<23..16>

MEM_A_DQ_BYTE2 MEM_50S

MEM_A_DQ_BYTE4

MEM_DATA

MEM_A_DQ<39..32>

MEM_50S

MEM_DATA

MEM_B_DQ<63..56>

MEM_B_DQ_BYTE7 MEM_50S

MEM_B_DQS6

MEM_DQS

MEM_B_DQS_N<6>

MEM_85D

MEM_DQS

MEM_B_DQS_P<7>

MEM_B_DQS7

MEM_85D

MEM_DQS

MEM_B_DQS_P<6>

MEM_B_DQS6

MEM_85D

MEM_B_DQS5

MEM_DQS

MEM_B_DQS_P<5>

MEM_85D

MEM_DQS

MEM_B_DQS_N<4>

MEM_B_DQS4

MEM_85D

MEM_B_DQS5

MEM_DQS

MEM_B_DQS_N<5>

MEM_85D

MEM_DATA

MEM_A_DQ_BYTE3

MEM_A_DQ<31..24>

MEM_50S

MEM_A_DQ<47..40>

MEM_A_DQ_BYTE5

MEM_DATA

MEM_50S

MEM_A_DQ<55..48>

MEM_A_DQ_BYTE6

MEM_DATA

MEM_50S

MEM_A_DQ_BYTE1

MEM_A_DM<1>

MEM_DATA

MEM_50S

MEM_A_DQ_BYTE2

MEM_DATA

MEM_A_DM<2>

MEM_50S

MEM_A_DQ_BYTE4

MEM_DATA

MEM_A_DM<4>

MEM_50S

MEM_A_DQ_BYTE5

MEM_DATA

MEM_A_DM<5>

MEM_50S

MEM_A_DQ_BYTE6

MEM_A_DM<6>

MEM_DATA

MEM_50S

MEM_A_DQ_BYTE7

MEM_A_DM<7>

MEM_DATA

MEM_50S

MEM_A_DQS_P<0>

MEM_DQS

MEM_A_DQS0

MEM_85D

MEM_DQS

MEM_A_DQS_N<0>

MEM_A_DQS0

MEM_85D

MEM_DQS

MEM_A_DQS1

MEM_A_DQS_P<1>

MEM_85D

MEM_DQS

MEM_A_DQS_P<4>

MEM_A_DQS4

MEM_85D

MEM_DQS

MEM_A_DQS_N<4>

MEM_A_DQS4

MEM_85D

MEM_A_DQS2

MEM_DQS

MEM_A_DQS_P<2>

MEM_85D

MEM_DQS

MEM_A_DQS_N<2>

MEM_A_DQS2

MEM_85D

MEM_DQS

MEM_A_DQS_P<3>

MEM_A_DQS3

MEM_85D

MEM_DQS

MEM_A_DQS_N<3>

MEM_A_DQS3

MEM_85D

MEM_A_DQS5

MEM_DQS

MEM_A_DQS_P<5>

MEM_85D

MEM_DQS

MEM_A_DQS_P<7>

MEM_A_DQS7

MEM_85D

MEM_40S MEM_CMD

MEM_B_WE_L

MEM_B_CMD

MEM_DATA

MEM_B_DQ<7..0>

MEM_B_DQ_BYTE0 MEM_50S

MEM_DATA

MEM_B_DQ<15..8>

MEM_B_DQ_BYTE1 MEM_50S

MEM_DATA

MEM_B_DQ<23..16>

MEM_B_DQ_BYTE2 MEM_50S

MEM_B_DQ<31..24>

MEM_DATA

MEM_B_DQ_BYTE3 MEM_50S

MEM_DATA

MEM_B_DQ<39..32>

MEM_B_DQ_BYTE4 MEM_50S

MEM_DATA

MEM_B_DQ<55..48>

MEM_B_DQ_BYTE6 MEM_50S

MEM_DATA

MEM_B_DM<0>

MEM_B_DQ_BYTE0 MEM_50S

MEM_DATA

MEM_B_DM<1>

MEM_B_DQ_BYTE1 MEM_50S

MEM_DATA

MEM_B_DM<2>

MEM_B_DQ_BYTE2 MEM_50S

MEM_DATA

MEM_B_DM<3>

MEM_B_DQ_BYTE3 MEM_50S

MEM_DQS

MEM_B_DQS_P<0>

MEM_B_DQS0

MEM_85D

MEM_DQS

MEM_B_DQS_N<0>

MEM_B_DQS0

MEM_85D

MEM_DQS

MEM_B_DQS_N<1>

MEM_B_DQS1

MEM_85D MEM_85D MEM_DQS

MEM_B_DQS_P<2>

MEM_B_DQS2

MEM_DQS

MEM_B_DQS_N<2>

MEM_B_DQS2

MEM_85D

MEM_85D MEM_DQS

MEM_B_DQS_N<3>

MEM_B_DQS3

MEM_DQS

MEM_B_DQS_P<3>

MEM_B_DQS3

MEM_85D

MEM_DQS

MEM_B_DQS_P<1>

MEM_B_DQS1

MEM_85D

MEM_B_DQ_BYTE6

MEM_DATA

MEM_B_DM<6>

MEM_50S

MEM_A_DQ_BYTE3

MEM_A_DM<3>

MEM_DATA

MEM_50S

MEM_37S

MEM_CTRL

MEM_A_CKE<3..0>

MEM_A_CNTL

MEM_B_CLK

MEM_72D MEM_CLK

MEM_B_CLK_P<5..0>

MEM_DQS

MEM_A_DQS_N<7>

MEM_A_DQS7

MEM_85D

MEM_DQS

MEM_A_DQS_N<6>

MEM_A_DQS6

MEM_85D

MEM_DQS

MEM_A_DQS_N<5>

MEM_A_DQS5

MEM_85D

MEM_A_DQS6

MEM_DQS

MEM_A_DQS_P<6>

MEM_85D

MEM_DATA

MEM_B_DM<7>

MEM_B_DQ_BYTE7 MEM_50S

MEM_B_DQ_BYTE4

MEM_DATA

MEM_B_DM<4>

MEM_50S

MEM_B_DQ_BYTE5

MEM_DATA

MEM_B_DM<5>

MEM_50S

101 OF 132

92 OF 103

11 28

11 29

11 30

11 29

11 30

11 29

11 30

11 28

11 29

11 28 29

11 29

11 28 29

11 29

11 28 29

11 29

11 30

11 29

11 29 30

11 29

11 29 30

11 29

11 29 30

11 29

11 28

11 30

11 29

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

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A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1.

SATA Interface Constraints

USB 2.0 Interface Constraints

Max length of LVDS/DisplayPort/TMDS traces: 12 inches.

PHYSICAL

SPACING

NET_TYPE

ELECTRICAL_CONSTRAINT_SET

LVDS intra-pair matching should be 5 mils. Pairs should be within 100 mils of clock length. DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps.

PCH Net Properties

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4.

SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.8

DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.

Digital Video Signal Constraints

=85_OHM_DIFF

DP_85D

* =85_OHM_DIFF

=85_OHM_DIFF=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF =85_OHM_DIFF

=85_OHM_DIFF

*

LVDS_85D

=85_OHM_DIFF

=85_OHM_DIFF=85_OHM_DIFF

DISPLAYPORT

?

=4x_DIELECTRIC

TOP,BOTTOM

=4x_DIELECTRIC

LVDS

?

TOP,BOTTOM

=85_OHM_DIFF =85_OHM_DIFF

=85_OHM_DIFF

*

USB_85D

=85_OHM_DIFF =85_OHM_DIFF

=85_OHM_DIFF

?

*

=3x_DIELECTRIC

DISPLAYPORT

LVDS

*

?

=3x_DIELECTRIC

?

SATA

TOP,BOTTOM

USB

?

TOP,BOTTOM

=4x_DIELECTRIC

?

*

8 MILSATA_ICOMP

*

?

=2x_DIELECTRIC

USB

PCH Constraints 1

SYNC_MASTER=K17_WFERRY

SYNC_DATE=06/09/2009

*

=90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF

=90_OHM_DIFF=90_OHM_DIFF

SATA_90D

=90_OHM_DIFF

*

SATA

?

=4x_DIELECTRIC

=STANDARD

PCH_USB_RBIAS

=STANDARD

8 MIL

*

8 MIL

=STANDARD

USB_EXTC_P

USB

USB_85D

USB_EXTC

USB_85D

USB

USB_HUB1_UP_P

USB_HUB1_UP

USB

USB_85D

USB_HUB1_UP_N USB_CAMERA_P

USB

USB_85D

USB_CAMERA

USB_CAMERA_N

USB

USB_85D

CLK_PCIE_90D CLK_PCIE

PCH_CLK96M_DOT_P

USB_BT_P

USB_85D

USB_BT

USB

USB_TPAD_P

USB

USB_TPAD

USB_85D

LVDS_IG_A_CLK

LVDS

LVDS_IG_A_CLK_P

LVDS_85D

LVDS_IG_A_DATA

LVDS_IG_A_DATA_P<2..0>

LVDSLVDS_85D

USB_EXTB_N

USB

USB_85D

NC_USB_MINIP

USB

USB_85D

USB_MINI

USB

USB_85D

USB_BT_N

USB

USB_IR_P

USB_IR

USB_85D

USB_IR_N

USB

USB_85D

USB

USB_EXCARD_P

USB_85D

USB_EXCARD

USB

USB_EXCARD_N

USB_85D

USB_TPAD_N

USB

USB_85D

CLK_PCIE_90D CLK_PCIE

PCIE_CLK100M_PCH_P

CLK_PCIE_90D CLK_PCIE

PCIE_CLK100M_PCH_N

PCH_CLK100M_PCH

CLK_PCIE_90D

FSB_CLK133M_PCH_P

CLK_PCIE

USB

USB_BRCRYPT_P

USB_BRCRYPT

USB_85D USB_85D

USB

USB_BRCRYPT_N

PCH_USB_RBIASPCH_USB_RBIAS

PCH_USB_RBIAS

CLK_PCIE_90D CLK_PCIE

PCH_CLK96M_DOT_N

GFX_CLK_DPLLSS

CLK_PCIE_90D CLK_PCIE

GFX_CLK120M_DPLLSS_N

GFX_CLK_DPLLSS

CLK_PCIE_90D CLK_PCIE

GFX_CLK120M_DPLLSS_P

PCH_CLK33M_PCIIN

CPU_50S

CLK_PCIE

CPU_50S

PCH_CLK14P3M_REFCLK

CLK_PCIE

PCH_CLK100M_SATA

CLK_PCIE

PCH_CLK100M_SATA_N

CLK_PCIE_90D

PCH_CLK100M_SATA_P

CLK_PCIE_90D CLK_PCIE

PCH_CLK100M_SATA

CLK_PCIE_90D CLK_PCIE

FSB_CLK133M_PCH_N

USB

NC_USB_MININ

USB_85D

USB

USB_85D

USB_HUB2_UP_N

USB

USB_85D

USB_HUB2_UP_P

USB_HUB2_UP

USB_EXTC_N

USB

USB_85D

USB_EXTB_P

USB

USB_EXTB

USB_85D

USB

USB_EXTA_N

USB_85D

USB_EXTA_P

USB

USB_EXTA

USB_85D

LVDS_IG_B_DATA

LVDSLVDS_85D

LVDS_IG_B_DATA_P<2..0>

LVDS_IG_B_CLK

LVDSLVDS_85D

TP_LVDS_IG_B_CLKN

LVDS_IG_B_CLK

LVDSLVDS_85D

TP_LVDS_IG_B_CLKP

LVDS_IG_A_DATA3

LVDSLVDS_85D

NC_LVDS_IG_A_DATAN<3>

LVDS_IG_A_DATA3

LVDSLVDS_85D

NC_LVDS_IG_A_DATAP<3>

LVDS

LVDS_IG_A_DATA

LVDS_85D

LVDS_IG_A_DATA_N<2..0>

LVDS_IG_A_CLK

LVDS

LVDS_IG_A_CLK_N

LVDS_85D

DP_85D

DISPLAYPORT

DP_AUX_CH

DP_IG_AUX_CH_N

DP_85D

DISPLAYPORT

DP_ML

DP_IG_ML_N<3..0>

DP_85D

DISPLAYPORT

DP_ML

DP_IG_ML_P<3..0>

DP_85D

DP_AUX_CH

DISPLAYPORT

DP_IG_AUX_CH_P

SATA_90D SATA

SATA_ODD_R2D_P

SATA_ODD_R2D_C_N

SATASATA_90D

SATA_EXTA_D2R

TP_SATA_EXTA_D2R_P

SATASATA_90D

SATA_ODD_D2R_C_P

SATASATA_90D

SATA_ODD_R2D_N

SATA_90D SATA

SATA_ODD_D2R_N

SATA

SATA_ODD_D2R_C_N

SATA_90D

SATA_90D SATA

TP_SATA_EXTA_D2R_N

SATASATA_90D

TP_SATA_EXTA_R2D_C_N

SATA_ODD_D2R SATA

SATA_ODD_D2R_P

SATA_90D

TP_SATA_EXTA_R2D_C_P

SATA_90D

SATA_EXTA_R2D

SATA

SATA_HDD_D2R_C_N

SATA_90D SATA

SATA_ODD_R2D_C_P

SATA_ODD_R2D SATASATA_90D

SATA_HDD_R2D_C_P

SATA_HDD_R2D SATA_90D SATA

SATA_HDD_R2D_P

SATA_90D SATA

SATA_HDD_R2D_N

SATA_90D SATA

SATA_HDD_R2D_C_N

SATA_90D SATA

SATA_HDD_D2R_C_P

SATA_90D SATA

SATA_90D

SATA_HDD_D2R_N

SATA

SATA_HDD_D2R

SATA_HDD_D2R_P

SATA_90D SATA

NC_LVDS_IG_B_DATAN<3>

LVDS_85D

LVDS_IG_B_DATA3

LVDS

NC_LVDS_IG_B_DATAP<3>

LVDS_85D

LVDS_IG_B_DATA3

LVDS

LVDS_IG_B_DATA_N<2..0>

LVDS_85D LVDS

LVDS_IG_B_DATA

PCH_SATA_ICOMP

SATA_ICOMP

PCH_SATA_ICOMP

102 OF 132

93 OF 103

35 44

19 35

33 35

17 26

33 36

36 54

18 88

35 43

6

33 36

35 45

8

34 36

8

34 36

36 54

17 26

19

103

19

103

19

17 26

10 17

17 27

17 26

6

19 36

35 44

35 43

36 43

18 88

6 8

18

6 8

18

8

18

8

18

18 88

8

18 85

8

85

8

85

8

18 85

6

42

17 42

8

17

42

6

42

17 42

42

8

17

8

17

17 42

8

17

42

17 42

6

42

6

42

17 42

42

17 42

8

18

8

18

18 88

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

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8 7 5 4 2 1

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

NET_TYPE

PCH Net Properties

HD Audio Interface Constraints

SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.15

ELECTRICAL_CONSTRAINT_SET

SPACING

LPC Bus Constraints

PHYSICAL

SMBus Interface Constraints

SPI Interface Constraints

SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.15

SIO Signal Constraints

I235

I236

I237 I238

I239 I240

I241

I242 I243

I244

I245 I246

I247

I248 I249

I250

I251

I252

I253

I254

*

=50_OHM_SE =50_OHM_SE =50_OHM_SE

HDA_50S

=STANDARD

=50_OHM_SE

=STANDARD

=55_OHM_SE=55_OHM_SE =55_OHM_SE

=STANDARD*

=55_OHM_SE

CLK_SLOW_55S

=STANDARD

SYNC_MASTER=K17_REF

SYNC_DATE=06/17/2009

PCH Constraints 2

8 MIL

?

SPI

*

* =STANDARD =STANDARD

=55_OHM_SE

SPI_55S

=55_OHM_SE=55_OHM_SE=55_OHM_SE

8 MIL

*

CLK_SLOW

?

SMB_50S

=50_OHM_SE=50_OHM_SE

=STANDARD* =STANDARD

=50_OHM_SE =50_OHM_SE

=50_OHM_SE=50_OHM_SE=50_OHM_SE

LPC_50S

* =STANDARD=STANDARD

=50_OHM_SE

=50_OHM_SE=50_OHM_SE=50_OHM_SE

CLK_LPC_50S

* =STANDARD=STANDARD

=50_OHM_SE

*

LPC

6 MIL

?

CLK_LPC

8 MIL

*

?

=2x_DIELECTRIC

HDA

*

?

SMB

=2x_DIELECTRIC

CONN_PCIE_AP_D2R_N

PCIEPCIE_85D

CONN_PCIE_AP_R2D_N

PCIE_85D PCIE

PCIE_AP_D2R

CONN_PCIE_AP_D2R_P

PCIEPCIE_85D

PCIE_AP_R2D

CONN_PCIE_AP_R2D_P

PCIE_85D PCIE

CPU_COMP

CPU_27P4S

PCH_VSS_NCTF<11>

CPU_COMP

CPU_27P4S

PCH_VSS_NCTF<12>

CPU_COMP

CPU_27P4S

PCH_VSS_NCTF<17>

CPU_27P4S

CPU_COMP

PCH_VSS_NCTF<29>

PCIE_85D PCIE

PCIE_FW_R2D_N

PCIE_85D PCIE

PCIE_FW_R2D_P

PCIE_85D PCIE

PCIE_AP_D2R_N

PCIEPCIE_85D

PCIE_FW_R2D_C_N

PCIE_85D PCIE

PCIE_FW_D2R_C_N

PCIE_85D PCIE

PCIE_EXCARD_R2D_P

PCIE

PCIE_EXCARD_R2D_N

PCIE_85D

PCIE

PCIE_EXCARD_R2D_C_P

PCIE_EXCARD_R2D

PCIE_85D

PCIE_EXCARD_R2D_C_N

PCIEPCIE_85D

PCIE_EXCARD_D2R_N

PCIEPCIE_85D

PCIE_EXCARD_D2R_P

PCIE_EXCARD_D2R

PCIEPCIE_85D

PCIE_85D PCIE

PCIE_AP_R2D_C_N

PCIEPCIE_85D

PCIE_AP_D2R_P

PCIE_AP_D2R

MCP_PE2_REFCLK

CLK_PCIE_90D

PCIE_CLK100M_FW_P

CLK_PCIE

MCP_PE3_REFCLK

CLK_PCIE_90D

PCIE_CLK100M_EXCARD_P

CLK_PCIE

CPU_COMP

CPU_27P4S

PCH_VSS_NCTF<2>

CPU_27P4S

CPU_COMP

PCH_VSS_NCTF<5>

CPU_COMP

CPU_27P4S

PCH_VSS_NCTF<25>

CPU_27P4S

CPU_COMP

PCH_VSS_NCTF<27>

CPU_COMP

CPU_27P4S

PCH_VSS_NCTF<22>

CPU_COMP

PCH_VSS_NCTF<21>

CPU_27P4S

PEG_CLK100M_N

CLK_PCIECLK_PCIE_90D

CLK_PCIE_90D

PCIE_CLK100M_FW_N

CLK_PCIE

PCIE_CLK100M_EXCARD_N

CLK_PCIE_90D CLK_PCIE

CPU_27P4S

CPU_COMP

TP_PCH_VSS_NCTF<7>

CPU_COMP

CPU_27P4S

PCH_VSS_NCTF<9>

CPU_COMP

CPU_27P4S

PCH_VSS_NCTF<19>

CPU_COMP

CPU_27P4S

PCH_VSS_NCTF<15>

CPU_COMP

CPU_27P4S

PCH_VSS_NCTF<9>

CPU_27P4S

CPU_COMP

PCH_VSS_NCTF<1>

PCIE_CLK100M_ENET

PCIE_CLK100M_ENET_P

CLK_PCIECLK_PCIE_90D CLK_PCIE

PCIE_CLK100M_ENET_N

CLK_PCIE_90D

MCP_PE1_REFCLK

CLK_PCIE_90D

PCIE_CLK100M_AP_P

CLK_PCIE

PEG_CLK100M_P

MCP_PE0_REFCLK

CLK_PCIE_90D

LPC_FRAME_L

LPC_50S

LPC

LPC_FRAME_L

CLK_LPC_50S

LPC_CLK33M_SMC

CLK_LPC

CLK_LPC_50S

LPC_CLK33M_LPCPLUS

CLK_LPC

SMB_50S

SMBUS_PCH_0_CLK

SMB

SML_PCH_0_CLK

SMBUS_PCH_1_CLK

SML_PCH_1_CLK

SMB_50S

SMB

SMBUS_PCH_1_DATA

SML_PCH_1_DATA

SMB_50S

SMB

HDA_BIT_CLK

HDA_50S

HDA

HDA_BIT_CLK

HDA_50S

HDA

HDA_SYNC_R

HDA_RST_L

HDA_50S

HDA_RST_R_L

HDA

HDA_50S

HDA_RST_L

HDA

HDA_SDIN0

HDA_50S

HDA_SDIN0

HDA

HDA_50S

HDA_SDIN_CODEC

HDA

SPI_CS0_R_L

SPI_CS0

SPI

SPI_55S

PCIEPCIE_85D

PCIE_ENET_R2D_N

PCIEPCIE_85D

PCIE_ENET_R2D_C_N

PCIEPCIE_85D

PCIE_ENET_D2R

PCIE_ENET_D2R_P

PCIEPCIE_85D

PCIE_ENET_D2R_N

PCIEPCIE_85D

PCIE_ENET_D2R_C_N

PCIEPCIE_85D

PCIE_AP_R2D_P

PCIEPCIE_85D

PCIE_AP_R2D_N

PCIE_85D PCIE

PCIE_AP_R2D

PCIE_AP_R2D_C_P

PCIE

PCIE_FW_R2D

PCIE_85D

PCIE_FW_R2D_C_P

PCIEPCIE_85D

PCIE_FW_D2R_P

PCIE_FW_D2R

PCIEPCIE_85D

PCIE_FW_D2R_N

PCIEPCIE_85D

PCIE_FW_D2R_C_P

CLK_PCIE_90D

PCIE_CLK100M_AP_N

CLK_PCIE

MCP_LPC_CLK0

CLK_LPC_50S

LPC_CLK33M_SMC_R

CLK_LPC

LPC_50S

LPC_AD

LPC

LPC_AD<3..0>

SMBUS_PCH_0_DATA

SMB

SMB_50S

SML_PCH_0_DATA

LPC_50S

LPC

LPCPLUS_RESET_L

LPC_RESET_L

HDA_50S

HDA_BIT_CLK_R

HDA

HDA_SYNC

HDA_50S

HDA_SYNC

HDA

HDA_SDOUT

HDA_50S

HDA_SDOUT

HDA

HDA_50S

HDA_SDOUT_R

HDA

PM_CLK32K_SUSCLK

PM_SUS_CLK

CLK_SLOWCLK_SLOW_55S

SPI_55SSPI_CLK

SPI_CLK_R

SPI

SPI_CLK

SPI_55S

SPI

SPI_MOSI

SPI_55S

SPI_MOSI_R

SPI

SPI_MISO

SPI_55S

SPI

SPI_MISO

PCIEPCIE_85D

PCIE_ENET_R2D_P

SMBUS_PCH_DATA

SMB_50S

SMB

SMBUS_PCH_CLK

SMB_50S

SMB

SPI_55S

SPI_MOSI

SPI

SPI_CS0_L

SPI

SPI_55S

PCIEPCIE_85D

PCIE_ENET_R2D

PCIE_ENET_R2D_C_P

PCIEPCIE_85D

PCIE_ENET_D2R_C_P

103 OF 132

94 OF 103

6

20

6

20

6

20

6

20

39

6

17 33

17 39

39

6

34

6

34

17 34

6

17 34

6

17 34

17 33

6

17 33

17 39

17 34

6

20

6

20

6

20

6

20

6

20

17 75

17 39

17 34

20

6

20 94

6

20

6

20

6

20 94

6

20

17 37

17 33

17 75

6

17 46 48 88

27 46

6

27 48

17 49

17 59

17

17 59

17 48

37

17 37

37

6

33

6

33

17 33

17 39

39

17 33

19 27

6

17 46 48 88

17 49

6

27 48 88

17

17 59

17

18 47

17 48

48

17 48

37

6

17 25 26 28 30 32 34 42 48 49

64

6

17 25 26 28 30 32 34 42 48 49

64

48

17 37

37

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8 7 5 4 2 1

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

PHYSICAL

SPACING

Ethernet Net Properties

CAESAR II (Ethernet) Constraints

CAESAR II (Ethernet PHY) Constraints

SOURCE: Broadcom 5764-DS04-RDS Page 38

?

*

0.6 MM

ENET_MDI

=100_OHM_DIFF

*

=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF

ENET_100D

=3:1_SPACING

*

?

ENET_3X

ENET_50S

=50_OHM_SE

=50_OHM_SE =50_OHM_SE =50_OHM_SE

=STANDARD =STANDARD*

SYNC_DATE=06/09/2009

SYNC_MASTER=K17_WFERRY

Ethernet Constraints

ENET_50S

ENET_RESET_L

ENET_3X

BCM5764_CLK25M_XTALI

ENET_50S ENET_50S

ENET_3X

BCM5764_CLK25M_XTALO

ENET_MDI

ENET_MDI_P<3..0>

ENET_MDI

ENET_100D

ENET_MDI

ENET_MDI_N<3..0>

ENET_100D

104 OF 132

95 OF 103

27 37

37 38

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

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8 7 5 4 2 1

ELECTRICAL_CONSTRAINT_SET

FireWire Net Properties

SPACING

NET_TYPE

FireWire Interface Constraints

PHYSICAL

Port 2 Not Used

FireWire Constraints

SYNC_MASTER=K17_WFERRY

SYNC_DATE=06/09/2009

*

=3:1_SPACING

?

FW_TP

=110_OHM_DIFF=110_OHM_DIFF

FW_110D

=110_OHM_DIFF=110_OHM_DIFF

=110_OHM_DIFF

*

=110_OHM_DIFF

FW_P1_TPA

FW_TP

FW_110D

FW_PORT1_TPA_P

FW_P1_TPA

FW_TP

FW_110D

FW_PORT1_TPA_N

FW_P1_TPB

FW_TP

FW_110D

FW_PORT1_TPB_P

FW_P1_TPB

FW_TP

FW_110D

FW_PORT1_TPB_N

FW_P0_TPB

NC_FW0_TPBN

FW_TP

FW_110D

FW_P0_TPB

NC_FW0_TPBP

FW_TP

FW_110D

FW_P0_TPA

NC_FW0_TPAN

FW_TP

FW_110D

FW_P0_TPA

NC_FW0_TPAP

FW_110D

FW_TP

105 OF 132

96 OF 103

39 40 41

6

39 41

6

39 41

6

39 41

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B

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345678

D

B

8 7 5 4 2 1

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

PHYSICAL

SPACING

SMC SMBus Net Properties

SPACING

PHYSICAL

NET_TYPE

ELECTRICAL_CONSTRAINT_SET

SMBus Charger Net Properties

=STANDARD =STANDARD

0.1 MM 0.1 MM*

=STANDARD=STANDARD

1TO1_DIFFPAIR

SMC Constraints

SYNC_MASTER=K17_WFERRY

SYNC_DATE=06/09/2009

SMBUS_SMC_A_S3_SCL

SMB

SMBUS_SMC_A_S3_SCL

SMB_50S

SMBUS_SMC_A_S3_SDA

SMB

SMB_50S

SMB

SMBUS_SMC_B_S0_SCL

SMB_50S

CHGR_CSO_N

1TO1_DIFFPAIR

CHGR_CSO_P

1TO1_DIFFPAIR

CHGR_CSO

CHGR_CSI_P

1TO1_DIFFPAIR

CHGR_CSI

CHGR_CSI_N

1TO1_DIFFPAIR

SMBUS_SMC_BSA_SDA

SMB

SMB_50S

SMB

SMBUS_SMC_MGMT_SDA

SMB_50S

SMB

SMBUS_SMC_MGMT_SCL

SMB_50S

SMB

SMBUS_SMC_BSA_SCL

SMB_50S

SMBUS_SMC_0_S0_SDA

SMB

SMB_50S

SMBUS_SMC_0_S0_SCL

SMB

SMB_50S

SMB

SMBUS_SMC_B_S0_SDA

SMB_50S

106 OF 132

97 OF 103

6

33 46 49 55

6

33 46 49 55

46 49 52

66

6

46 49 65 66

46 49 57

102

46 49 57

102

6

46 49 65 66

46 49 52

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

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TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MUXGFX Net Properties

SPACING

GDDR3 FB A/B Net Properties

ELECTRICAL_CONSTRAINT_SET ELECTRICAL_CONSTRAINT_SET

(CK505_DOT96)

PHYSICAL

NET_TYPE

SPACING

PHYSICAL

NET_TYPE

SPACING

NET_TYPE

SPACING

PHYSICAL

G96 Net Properties

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

GDDR3 FB C/D Net Properties

NET_TYPE

GDDR3 Frame Buffer Signal Constraints

Digital Video Signal Constraints

LVDS intra-pair matching should be 0.127 mm. Pairs should be within 0.508mm of entire channel. DisplayPort/TMDS intra-pair matching should be 0.127mm. Inter-pair matching should be within 2.54cm. Max Length 241.3mm.

Max length of LVDS/DisplayPort/TMDS traces: 13 inches.

DIsplayPort AUX CH intra-pair matching should be 0.127mm. Max length 330.2mm.

SOURCE: Calpella SFF DG Rev 1.5 (407364) and Family GPU DG-04202-001-v04.

I138

I139

I142

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I208 I209

?

=4x_DIELECTRIC

TOP,BOTTOM

LVDS

?

=4x_DIELECTRIC

TOP,BOTTOM

DISPLAYPORT

?

=3x_DIELECTRIC

*

LVDS

?

=3x_DIELECTRIC

*

DISPLAYPORT

=85_OHM_DIFF

*

=85_OHM_DIFF

LVDS_85D

=85_OHM_DIFF=85_OHM_DIFF

=85_OHM_DIFF =85_OHM_DIFF

=85_OHM_DIFF

*

=85_OHM_DIFF

DP_85D

=85_OHM_DIFF=85_OHM_DIFF

=85_OHM_DIFF =85_OHM_DIFF

?

=2.5:1_SPACING

*

GDDR3_DATA

?

=2.5:1_SPACING

*

GDDR3_DQS

GPU (GT216) CONSTRAINTS

SYNC_MASTER=K17_WFERRY

SYNC_DATE=06/09/2009

=40_OHM_SE

GDDR3_40SE

*

=40_OHM_SE =40_OHM_SE

0.095 MM

=STANDARD =STANDARD

=85_OHM_DIFF

*

=85_OHM_DIFF

GDDR3_80D

=85_OHM_DIFF

0.095 MM

=85_OHM_DIFF =85_OHM_DIFF

=2.5:1_SPACING

?

*

GDDR3_CMD

?

=2.5:1_SPACING

*

GDDR3_CLK

=55_OHM_SE

*

=40_OHM_SE

GDDR3_40R55SE

12.7 MM

0.095 MM

=STANDARD =STANDARD

FB_A_WDQS2

FB_A_WDQS<2>

GDDR3_DQS

GDDR3_40SE

FB_A_WDQS<1>

GDDR3_40SE

GDDR3_DQS

FB_A_WDQS1

FB_A_UMA<5..2>

GDDR3_40SE

FB_B_CMD

GDDR3_CMD

GDDR3_40SEFB_B_RDQS2

FB_A_RDQS<6>

GDDR3_DQS

GDDR3_40SE

GDDR3_DQS

FB_B_RDQS0

FB_A_RDQS<4>

GDDR3_40SEFB_B_WDQS2

FB_A_WDQS<6>

GDDR3_DQS

GDDR3_40SEFB_B_WDQS0

FB_A_WDQS<4>

GDDR3_DQS

GDDR3_40SE

FB_A_DQM3

FB_A_DQM_L<3>

GDDR3_DATA

FB_B_DQ_BYTE1

GDDR3_40SE GDDR3_DATA

FB_A_DQ<47..40>

LVDS_EG_A_CLK

LVDS

LVDS_EG_A_CLK_P

LVDS_85D

LVDS_EG_B_DATA_N<2..0>

LVDS

LVDS_EG_B_DATA

LVDS_85D

LVDS_EG_B_DATA3

NC_LVDS_EG_B_DATA_P<3>

LVDSLVDS_85D

LVDS_EG_B_DATA_P<2..0>

LVDS

LVDS_EG_B_DATA

LVDS_85D

GPU_CLK27M

CLK_SLOW_55S CLK_SLOW

GPU_CLK27M_SS

CK505_CLK27MSS

CLK_SLOW_55S CLK_SLOW

LVDS_EG_A_CLK_N

LVDS_EG_A_CLK

LVDSLVDS_85D

LVDS_EG_A_DATA_N<2..0>

LVDS_EG_A_DATA

LVDSLVDS_85D

LVDS_EG_A_DATA3

NC_LVDS_EG_A_DATA_N<3>

LVDSLVDS_85D

DP_EG_ML_P<3..0>

DP_ML

DISPLAYPORT

DP_85D

DP_EG_ML_N<3..0>

DP_ML

DISPLAYPORT

DP_85D

LVDS_85D

LVDS_CONN_B_CLK_F_P

LVDS

LVDS_CONN_A_DATA_P<2..0>

LVDS_85D

LVDS_CONN_B_CLK_N

LVDSLVDS_85D

LVDS_CONN_A_CLK_F_P

LVDSLVDS_85D

LVDS_85D

LVDS_CONN_A_CLK_F_N

LVDS

DP_AUX_CH_C_N

DP_AUX_CH

DISPLAYPORT

DP_85D

FB_C_CLK

GDDR3_80D

FB_B_CLK_P<0>

GDDR3_CLK

FB_AB_CMD

FB_A_BA<2..0>

GDDR3_40R55SE

GDDR3_CMD

FB_AB_CMD

FB_A_MA<12..6>

GDDR3_40R55SE

GDDR3_CMD

GDDR3_80D

FB_A_CLK_P<0>

FB_A_CLK

GDDR3_CLK

GDDR3_80D

FB_B_CLK_N<0>

GDDR3_CLK

FB_D_CLK

GDDR3_80D

FB_B_CLK_P<1>

GDDR3_CLK

GDDR3_80D

FB_B_CLK_N<1>

GDDR3_CLK

FB_B_MA<1..0>

FB_CD_CMD GDDR3_CMD

GDDR3_40R55SE

FB_B_RAS_L

FB_CD_CMD GDDR3_CMD

GDDR3_40R55SE

FB_CD_CMD

FB_B_WE_L

GDDR3_CMD

GDDR3_40R55SE

FB_CD_CMD_PD

FB_B_UCKE

GDDR3_CMD

GDDR3_40R55SE

LVDS_A_CLK_N

LVDS_A_CLK

LVDSLVDS_85D

LVDS_B_DATA_P<2..0>

LVDS_B_DATA

LVDSLVDS_85D

LVDS_B_DATA_N<2..0>

LVDS_B_DATA

LVDSLVDS_85D

LVDS_A_CLK_P

LVDS_A_CLK

LVDSLVDS_85D

DP_EG_AUX_CH_P

DP_AUX_CH

DISPLAYPORT

DP_85D

DP_EG_AUX_CH_C_N

DISPLAYPORT

DP_85D

DP_EG_AUX_CH_C_P

DISPLAYPORT

DP_85D

DP_EG_AUX_CH_N

DP_AUX_CH

DISPLAYPORT

DP_85D

GDDR3_80D

FB_A_CLK_N<1>

GDDR3_CLK

GDDR3_80D

FB_A_CLK_P<1>

FB_B_CLK

GDDR3_CLK

FB_A_MA<1..0>

FB_AB_CMD

GDDR3_40R55SE

GDDR3_CMD

FB_A_RAS_L

FB_AB_CMD

GDDR3_40R55SE

GDDR3_CMD

FB_CD_CMD_PD

FB_B_DRAM_RST

GDDR3_40R55SE

GDDR3_40SE

FB_C_CMD

GDDR3_CMD

FB_B_LMA<5..2>

GDDR3_40SE

FB_D_CMD

GDDR3_CMD

FB_B_UMA<5..2>

GDDR3_40SEFB_C_WDQS0

GDDR3_DQS

FB_B_WDQS<0>

FB_C_WDQS3 GDDR3_40SE

GDDR3_DQS

FB_B_WDQS<3>

FB_C_WDQS2 GDDR3_40SE

GDDR3_DQS

FB_B_WDQS<2>

FB_C_RDQS1 GDDR3_40SE

GDDR3_DQS

FB_B_RDQS<1>

FB_C_RDQS0 GDDR3_40SE

GDDR3_DQS

FB_B_RDQS<0>

GDDR3_40SE

FB_C_DQ_BYTE2

GDDR3_DATA

FB_B_DQ<23..16>

GDDR3_40SE

FB_C_DQM0

GDDR3_DATA

FB_B_DQM_L<0>

GDDR3_40SE

FB_C_DQ_BYTE3

GDDR3_DATA

FB_B_DQ<31..24>

GDDR3_40SE

FB_C_DQM2

GDDR3_DATA

FB_B_DQM_L<2>

GDDR3_40SEFB_D_WDQS3

GDDR3_DQS

FB_B_WDQS<7>

GDDR3_40SEFB_D_RDQS1

GDDR3_DQS

FB_B_RDQS<5>

GDDR3_40SE

FB_D_DQM2

GDDR3_DATA

FB_B_DQM_L<6>

GDDR3_40SE

FB_D_DQM1

GDDR3_DATA

FB_B_DQM_L<5>

FB_D_DQM3

GDDR3_40SE GDDR3_DATA

FB_B_DQM_L<7>

GDDR3_40SEFB_D_RDQS3

GDDR3_DQS

FB_B_RDQS<7>

GDDR3_40SEFB_D_RDQS2

GDDR3_DQS

FB_B_RDQS<6>

FB_D_DQ_BYTE1

GDDR3_40SE GDDR3_DATA

FB_B_DQ<47..40>

GDDR3_40SE

FB_D_DQ_BYTE0

GDDR3_DATA

FB_B_DQ<39..32>

GDDR3_40SE

FB_D_DQ_BYTE2

GDDR3_DATA

FB_B_DQ<55..48>

GDDR3_40SE

FB_D_DQ_BYTE3

GDDR3_DATA

FB_B_DQ<63..56>

GDDR3_40SE

FB_D_DQM0

GDDR3_DATA

FB_B_DQM_L<4>

GDDR3_40SE

FB_C_DQ_BYTE1

GDDR3_DATA

FB_B_DQ<15..8>

GDDR3_40SE

FB_C_DQM3

GDDR3_DATA

FB_B_DQM_L<3>

GDDR3_40SEFB_D_WDQS1

GDDR3_DQS

FB_B_WDQS<5>

FB_CD_CS0 GDDR3_CMD

FB_B_LCS0_L

GDDR3_40R55SE

FB_CD_CMD_PD

GDDR3_CMD

FB_B_LCKE

GDDR3_40R55SE

FB_B_CAS_L

FB_CD_CMD GDDR3_CMD

GDDR3_40R55SE

FB_B_BA<2..0>

FB_CD_CMD GDDR3_CMD

GDDR3_40R55SE

FB_B_MA<12..6>

FB_CD_CMD GDDR3_CMD

GDDR3_40R55SE

GDDR3_40SEFB_A_RDQS1

FB_A_RDQS<1>

GDDR3_DQS

GDDR3_40SEFB_A_RDQS2

FB_A_RDQS<2>

GDDR3_DQS

GDDR3_40SE

FB_A_DQ_BYTE0

FB_A_DQ<7..0>

GDDR3_DATA

GDDR3_DATAGDDR3_40SE

FB_A_DQM2

FB_A_DQM_L<2>

GDDR3_40SEFB_B_RDQS1

FB_A_RDQS<5>

GDDR3_DQS

GDDR3_80D

FB_A_CLK_N<0>

GDDR3_CLK

FB_A_CAS_L

FB_AB_CMD

GDDR3_40R55SE

GDDR3_CMD

FB_AB_CMD

GDDR3_40R55SE

FB_A_WE_L

GDDR3_CMD

FB_A_LMA<5..2>

GDDR3_40SE

FB_A_CMD

GDDR3_CMD

GDDR3_40SEFB_B_WDQS1

FB_A_WDQS<5>

GDDR3_DQS

GDDR3_40SEFB_B_WDQS3

FB_A_WDQS<7>

GDDR3_DQS

FB_B_DQ_BYTE0

GDDR3_40SE GDDR3_DATA

FB_A_DQ<39..32>

GDDR3_40SE

FB_A_DQM0

FB_A_DQM_L<0>

GDDR3_DATA

GDDR3_40SE GDDR3_DATA

FB_A_DQ_BYTE3

FB_A_DQ<31..24>

GDDR3_40SE

FB_A_DQ_BYTE2

FB_A_DQ<23..16>

GDDR3_DATA

GDDR3_40SE

FB_A_DQ<15..8>

FB_A_DQ_BYTE1

GDDR3_DATA

GDDR3_40SEFB_A_RDQS0

FB_A_RDQS<0>

GDDR3_DQS

FB_A_WDQS3

FB_A_WDQS<3>

GDDR3_DQS

GDDR3_40SE

FB_AB_CMD_PD

GDDR3_40R55SE

FB_A_LCKE

GDDR3_CMD

FB_AB_CMD_PD

GDDR3_40R55SE

FB_A_UCKE

GDDR3_CMD

FB_AB_CS0

GDDR3_40R55SE

FB_A_LCS0_L

GDDR3_CMD

GDDR3_40SEFB_A_RDQS3

FB_A_RDQS<3>

GDDR3_DQS

LVDS_EG_A_DATA_P<2..0>

LVDS_EG_A_DATA

LVDSLVDS_85D

FB_B_RDQS3 GDDR3_40SE

FB_A_RDQS<7>

GDDR3_DQS

GDDR3_DATAGDDR3_40SE

FB_A_DQM1

FB_A_DQM_L<1>

LVDS_EG_A_DATA3

NC_LVDS_EG_A_DATA_P<3>

LVDSLVDS_85D

LVDS_EG_B_DATA3

NC_LVDS_EG_B_DATA_N<3>

LVDSLVDS_85D

GDDR3_40SE

FB_A_WDQS<0>

FB_A_WDQS0

GDDR3_DQS

FB_AB_CMD_PD

GDDR3_40R55SE

FB_A_DRAM_RST

GDDR3_CMD

LVDS_A_DATA_P<2..0>

LVDS_A_DATA

LVDSLVDS_85D

LVDS_A_DATA_N<2..0>

LVDS_A_DATA

LVDSLVDS_85D

LVDS_B_CLK_P

LVDS_B_CLK

LVDSLVDS_85D

LVDS_B_CLK_N

LVDS_B_CLK

LVDSLVDS_85D

LVDS_85D

LVDS_CONN_B_CLK_F_N

LVDS

DP_AUX_CH_C_P

DP_AUX_CH

DISPLAYPORT

DP_85D

GDDR3_40SEFB_D_RDQS0

GDDR3_DQS

FB_B_RDQS<4>

GDDR3_40SEFB_D_WDQS2

GDDR3_DQS

FB_B_WDQS<6>

GDDR3_40SEFB_D_WDQS0

GDDR3_DQS

FB_B_WDQS<4>

GDDR3_40SE

FB_C_DQM1

GDDR3_DATA

FB_B_DQM_L<1>

GDDR3_40SE

FB_C_DQ_BYTE0

GDDR3_DATA

FB_B_DQ<7..0>

GDDR3_40SEFB_C_RDQS3

GDDR3_DQS

FB_B_RDQS<3>

GDDR3_40SEFB_C_RDQS2

GDDR3_DQS

FB_B_RDQS<2>

GDDR3_40SEFB_C_WDQS1

GDDR3_DQS

FB_B_WDQS<1>

GDDR3_40SE

FB_B_DQM3

FB_A_DQM_L<7>

GDDR3_DATA

GDDR3_40SE

FB_B_DQM2

FB_A_DQM_L<6>

GDDR3_DATA

GDDR3_40SE

FB_B_DQM1

FB_A_DQM_L<5>

GDDR3_DATA

GDDR3_40SE

FB_B_DQM0

FB_A_DQM_L<4>

GDDR3_DATA

GDDR3_40SE

FB_B_DQ_BYTE3

FB_A_DQ<63..56>

GDDR3_DATA

GDDR3_40SE

FB_B_DQ_BYTE2

FB_A_DQ<55..48>

GDDR3_DATA

DP_ML_CONN_N<3..0>

DISPLAYPORT

DP_85D

DP_ML_CONN_P<3..0>

DP_ML

DISPLAYPORT

DP_85D

DP_ML_N<3..0>

DISPLAYPORT

DP_85D

DP_ML_P<3..0>

DP_ML

DISPLAYPORT

DP_85D

DP_ML_C_N<3..0>

DISPLAYPORT

DP_85D

DP_ML_C_P<3..0>

DP_ML

DISPLAYPORT

DP_85D

LVDS_CONN_B_DATA_N<2..0>

LVDSLVDS_85D

LVDS_CONN_B_DATA_P<2..0>

LVDSLVDS_85D

LVDS_CONN_B_CLK_P

LVDSLVDS_85D

LVDS_CONN_A_DATA_N<2..0>

LVDSLVDS_85D

LVDS_CONN_A_CLK_N

LVDSLVDS_85D

LVDS_85D

LVDS_CONN_A_CLK_P

LVDS

107 OF 132

98 OF 103

77 78

82 88

81 82

82 88

27 80 81

80 81

82 88

81 82

82 85

6

84

6

84 85

6

84

6

84

85 86

77 79

77 78

77 79

85 88

82 85

85

82 85

77 78

77 79

77 78

82 88

77 78

81 82

77 78

85 88

6

84

85 86

77 79

77 78

86

85 86

86

6

84 85

6

84 85

6

84 85

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(USB_EXTD) (USB_EXTD) (USB_CAMERA)

K17 Specific Net Properties

ELECTRICAL_CONSTRAINT_SET

K17 Specific Net Properties

(USB_EXTA) (USB_EXTA) (USB_EXTA)

(USB_CAMERA)

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

NET_TYPE

SPACING SPACING

NET_TYPE

PHYSICAL

(USB_EXTA)

Allow 0.127 mm necks for >0.127 mm lines for ARD fanout.

Memory Constraint Relaxations

Graphics ,SATA Constraint Relaxations

Alternate diffpair width/gap through BGA fanout areas (95-ohm diff)

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SYNC_DATE=06/17/2009

SYNC_MASTER=K17_REF

Project Specific Constraints

GND_P2MM

GND

*

CPU_VCCSENSE

ENET_MDI

*

GND_P2MM

GND

*

PCIE

GND_P2MM

GND

0.1 MMTOP

500 MILUSB_85D

LVDS_85DLVDS_85D

BGA

100_DIFF_BGA

DP_85D

BGA

SATA_90D

100_DIFF_BGA

CLK_PCIE_90D 100_DIFF_BGA

BGA

MEM_CLK

GND

*

GND_P2MM

MEM_CTRL

*

GND

GND_P2MM

CPU_27P4S

0.23 MM 100 MIL

BOTTOM

1000

*

GND_P2MM

0.20 MM

1000

*

PWR_P2MM

0.20 MM

GND =STANDARD

?*

*

?

AUDIO

=2:1_SPACING

SB_POWER

*

PWR_P2MM

USB

*

GND

GND_P2MMCPU_COMP

?*

SENSE

=2:1_SPACING

SB_POWER

*

PWR_P2MM

SATA

GND_P2MM

*

GND

CLK_PCIE

MEM_72D 6.35 MM

0.127 MM

BOTTOM

0.1 MMTOP

MEM_85D 6.35 MM

LVDS

GND

GND_P2MM

*

CLK_PCIE PWR_P2MMSB_POWER

MEM_DATA

GND

*

GND_P2MM

PCIE_85D

*

100 MIL0.09 MM

100 MIL

*

MEM_40S 0.09 MM

GND_P2MM

MEM_DQS

*

GND

*

GND_P2MM

MEM_CMD

USB GND

GND_P2MM

*

GND

GND_P2MM

*

SATA

DIFFPAIR

=1:1_DIFFPAIR

*

=1:1_DIFFPAIR

=1:1_DIFFPAIR =1:1_DIFFPAIR

=55_OHM_SE

=1:1_DIFFPAIR

*

=1:1_DIFFPAIR=1:1_DIFFPAIR

=55_OHM_SE =55_OHM_SE

SENSE_1TO1_55S

100 MILMEM_72D

*

0.09 MM

?

25 MILS

ENETCONN

*

* ?

THERM

=2:1_SPACING

=55_OHM_SE =55_OHM_SE =55_OHM_SE

=1:1_DIFFPAIR

*

=1:1_DIFFPAIR

THERM_1TO1_55S

=1:1_DIFFPAIR

PCIE_CLK100M_EXCARD_CONN_N

CLK_PCIECLK_PCIE_90D

CLK_PCIE_90D CLK_PCIE

PCIE_CLK100M_EXCARD_CONN_P

SPK_OUT

AUDIO

SPKRAMP_FL_OUT_P

DIFFPAIR

AUDIO

DIFFPAIR

SPKRAMP_FL_OUT_N

SB_POWER

PP3V3_S0

USB_TPAD_R_P

USB_85D

USB

DIFFPAIR

AUDIO

SSM2315LFE_IN_N

DIFFPAIR

AUDIO

SSM2315LFE_IN_P

DIFFPAIR

AUDIO

SSM2315BL_IN_P

DIFFPAIR

AUDIO

SSM2315BL_IN_N

INT_MIC_N

AUDIO

DIFFPAIR

INT_MIC_P

AUDIO

DIFFPAIR

INT_MIC_F_N

AUDIO

DIFFPAIR

INT_MIC_F_P

AUDIO

DIFFPAIR

SSM2315BR_IN_N

AUDIO

DIFFPAIR

SSM2315BR_IN_P

AUDIO

DIFFPAIR

SPKRAMP_LFE_IN_L_N

AUDIO

SPKRAMP_LFE_IN_L_P

AUDIO

DIFFPAIR

SENSE_1TO1_55S

SENSE

ISNS_P1V8GPU_R_N

SENSE_1TO1_55SSENSE_DIFFPAIR

SENSE

ISNS_CPU_P

SENSE

SENSE_1TO1_55S

DDRISNS_N

SENSE_1TO1_55S

SENSE

GPUISENS_N

PP1V5_S0

SB_POWER

SSM2315FR_IN_P

AUDIO

DIFFPAIR

SSM2315FL_IN_N

AUDIO

DIFFPAIR

SSM2315FL_IN_P

AUDIO

DIFFPAIR

SSM2315FR_IN_N

AUDIO

DIFFPAIR

SPKRAMP_FL_IN_L_P

DIFFPAIR

AUDIO

SPKRAMP_FL_IN_L_N

AUDIO

DIFFPAIR

SPKRAMP_BL_IN_L_P

DIFFPAIR

AUDIO

SPKRAMP_BL_IN_L_N

DIFFPAIR

AUDIO

SPKRAMP_FR_IN_L_P

DIFFPAIR

AUDIO

SPKRAMP_FR_IN_L_N

DIFFPAIR

AUDIO

SPKRAMP_BR_IN_L_N

AUDIO

DIFFPAIR

SPKRAMP_BR_IN_L_P

AUDIO

DIFFPAIR

PP3V3_S5

SB_POWER

USB

USB_LT3_P

USB_85D

USB_LT3_N

USB

USB_85D

USB_TPAD_R_N

USB_85D

USB

SPKRAMP_LFE_IN_C_N

AUDIO

DIFFPAIR

SPKRAMP_LFE_IN_C_P

AUDIO

DIFFPAIR

SPKRAMP_BR_IN_C_N

AUDIO

DIFFPAIR

SPKRAMP_BR_IN_C_P

AUDIO

DIFFPAIR

SPKRAMP_FR_IN_C_N

DIFFPAIR

AUDIO

SPKRAMP_FR_IN_C_P

DIFFPAIR

AUDIO

SPKRAMP_BL_IN_C_N

DIFFPAIR

AUDIO

SPKRAMP_BL_IN_C_P

DIFFPAIR

AUDIO

SPKRAMP_FL_IN_C_P

DIFFPAIR

AUDIO

SPKRAMP_FL_IN_C_N

AUDIO

DIFFPAIR

AUDIO

DIFFPAIR

SPKRAMP_LFE_OUT_N

AUDIO

DIFFPAIR

SPKRAMP_BR_OUT_N

SPK_OUT

AUDIO

DIFFPAIR

SPKRAMP_LFE_OUT_P

DIFFPAIR

AUDIO

SPKRAMP_FR_OUT_N

AUDIO

DIFFPAIR

SPK_OUT

SPKRAMP_BR_OUT_P

DIFFPAIR

SPK_OUT

SPKRAMP_FR_OUT_P

AUDIO

DIFFPAIR

AUDIO

SPKRAMP_BL_OUT_N

DIFFPAIR

AUDIO

SPK_OUT

SPKRAMP_BL_OUT_P

ISNS_PP3V3_S3_P

SENSE_1TO1_55SSENSE_DIFFPAIR

SENSE

ISNS_PP1V05_P

SENSE_1TO1_55SSENSE_DIFFPAIR

SENSE

ISNS_PVTTS0PCH_R_P

SENSE_1TO1_55SSENSE_DIFFPAIR

SENSE

NC_ISNS_PVTTS0PCH_N

SENSE_1TO1_55S

SENSE

NC_ISNS_PVTTS0PCH_P

SENSE_1TO1_55SSENSE_DIFFPAIR

SENSE

ISNS_PP5V_S0_R_P

SENSE_1TO1_55SSENSE_DIFFPAIR

THERM

SENSE_1TO1_55SSENSE_DIFFPAIR

ISNS_3V3_S3_R_P

GPU_TDIODE_P

THERM_1TO1_55S

THERM

SENSE_DIFFPAIR

THERM_1TO1_55S

THERM

GPUTHMSNS_D_N

THERM

THERM_1TO1_55S

CPU_THERMD_N

SATA_HDD_R2D_RDRV_IN_P

SATASATA_90D

SENSE_DIFFPAIR THERM_1TO1_55S

THERM

GPUTHMSNS_D_P

SATA_ODD_R2D_UF_N

SATASATA_90D

SATA_ODD_D2R_UF_N

SATA_90D SATA

PCIE_CLK100M_AP_CONN_N

CLK_PCIECLK_PCIE_90D

PCIE_CLK100M_AP

PCIE_CLK100M_AP_CONN_P

CLK_PCIECLK_PCIE_90D

CHGR_CSI_R_N

1TO1_DIFFPAIR

CHGR_CSI_R_P

1TO1_DIFFPAIR

USB

USB2_EXTA_MUXED_N

USB_85D

USB_BRCRYPT_CONN_N

USB

USB_85D

USB_BRCRYPT_CONN_P

USB

USB_85D

USB

USB_CAMERA_CONN_P

USB_85D

USB2_LT1_P

USB

USB_85D

USB

USB2_EXTA_MUXED_P

USB_85D

CHGR_CSO_R_N

1TO1_DIFFPAIR

CHGR_CSO_R_P

1TO1_DIFFPAIR

ENETCONN_P<3..0>

ENET_100D

ENETCONN

USB_CAMERA_CONN_N

USB

USB_85D

DP_IG_AUX_CH_C_N

DP_85D

DISPLAYPORT

SENSE_1TO1_55S

SENSE

DDRISNS_R_N

SENSE_1TO1_55SSENSE_DIFFPAIR

SENSE

GPUISENS_P

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_55S

ISNS_AIRPORT_P

SENSE_1TO1_55S

SENSE

ISNS_AIRPORT_N

SENSE

SENSE_DIFFPAIR SENSE_1TO1_55S

DDRISNS_P

SENSE_1TO1_55S

SENSE

ISNS_CPU_N

ISNS_HDD_N

SENSE_1TO1_55S

SENSE

ISNS_LCDBKLT_P

SENSE

SENSE_DIFFPAIR SENSE_1TO1_55S

SENSE_1TO1_55S

SENSE

SENSE_DIFFPAIR

NC_ISNS_P1V05S0PCH_P

CPUVTTS0_CS_P

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_55S

NC_ISNS_P1V05S0PCH_N

SENSE

SENSE_1TO1_55S

CPUVTTS0_CS_N

SENSE_1TO1_55S

SENSE

CPUVTTS0_CS_R_N

SENSE_1TO1_55S

SENSE

NC_ISNS_P3V3S0MPCH_N

SENSE

SENSE_1TO1_55S

NC_ISNS_P3V3S0MPCH_P

SENSE

SENSE_1TO1_55SSENSE_DIFFPAIR

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_55S

ISNS_P3V3S0MPCH_R_P

GFXIMVP_CS_P

SENSE_DIFFPAIR SENSE_1TO1_55S

SENSE

ISNS_P3V3S0MPCH_R_N

SENSE

SENSE_1TO1_55S

GFXIMVP_CS_R_P

SENSE_1TO1_55S

SENSE

SENSE_DIFFPAIR

GFXIMVP_CS_N

SENSE

SENSE_1TO1_55S

GFXIMVP_CS_R_N

SENSE_1TO1_55S

SENSE

ISNS_PP5V_S0_R_N

SENSE_1TO1_55S

ISNS_PVTTS0PCH_R_N

SENSE_1TO1_55S

SENSE

ISNS_PP1V05_N

SENSE_1TO1_55S

SENSE

SENSE_1TO1_55S

ISNS_PP3V3_S3_N

SENSE

SENSE_1TO1_55S

ISNS_PP3V3_S5_P

SENSE

SENSE_DIFFPAIR

SENSE_1TO1_55S

SENSE

ISNS_PP3V3_S5_N

SENSE_1TO1_55S

ISNS_PP5V_S3_P

SENSE

SENSE_DIFFPAIR

ISNS_PP5V_S0_N

SENSE

SENSE_1TO1_55S

ISNS_PP5V_S3_N

SENSE_1TO1_55S

SENSE

SENSE_DIFFPAIR

ISNS_1V5_S3_P

SENSE_1TO1_55S

SENSE

ISNS_1V5_S3_N

SENSE_1TO1_55S

THERM

SENSE_DIFFPAIR

ISNS_1V5_S3_R_P

SENSE_1TO1_55S

THERM

ISNS_1V5_S3_R_N

SENSE_1TO1_55S

SENSE_DIFFPAIR

SENSE

ISNS_AIRPORT_R_P

SENSE_1TO1_55S

SENSE

ISNS_AIRPORT_R_N

GFXIMVP6_VSEN_P

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_55S

GFX_ISNS_R_P

SENSE_1TO1_55S

SENSE

SENSE_DIFFPAIR

GFX_ISNS_R_N

SENSE_1TO1_55S

SENSE

GFXIMVP6_VSEN_N

SENSE

SENSE_1TO1_55S

SATA_HDD_D2R_UF_P

SATA_90D SATA

SATA_HDD_D2R_RDRV_IN_P

SATA_90D SATA

SATA_HDD_D2R_RDRV_IN_N

SATASATA_90D

SATA_HDD_D2R_UF_N

SATA_90D SATA

SATA_ODD_D2R_UF_P

SATASATA_90D

ENETCONN_N<3..0>

ENET_100D

ENETCONN

SATA_90D

SATA_HDD_R2D_UF_P

SATA

SATA_90D

SATA_HDD_R2D_UF_N

SATA

SATA_HDD_D2R_RDRV_OUT_P

SATASATA_90D

CPUVTTS0_CS_R_P

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_55S

SENSE

SENSE_1TO1_55S

ISNS_AIRPORT_N

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_55S

ISNS_AIRPORT_P

THERM

THERM_1TO1_55S

CPUTHMSNS_D2_N

SENSE_DIFFPAIR

CPUTHMSNS_D2_P

THERM_1TO1_55S

THERM

SATA_HDD_R2D_RDRV_OUT_P

SATASATA_90D

SATA_HDD_R2D_RDRV_IN_N

SATASATA_90D

SATA_HDD_R2D_RDRV_OUT_N

SATA_90D SATA

SENSE

SENSE_1TO1_55S

DDRISNS_R_P

SENSE_DIFFPAIR

SENSE_1TO1_55SSENSE_DIFFPAIR

SENSE

ISNS_P1V8GPU_R_P

ISNS_HDD_P

SENSE_DIFFPAIR SENSE_1TO1_55S

SENSE

ISNS_HDD_R_N

SENSE_1TO1_55S

SENSE

ISNS_ODD_R_N

SENSE_1TO1_55S

SENSE

ISNS_ODD_N

SENSE_1TO1_55S

ISNS_LCDBKLT_N

SENSE

ISNS_ODD_P

SENSE_1TO1_55SSENSE_DIFFPAIR

ISNS_ODD_R_P

SENSE_1TO1_55SSENSE_DIFFPAIR

SENSE

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_55S

ISNS_P1V8GPU_P

SENSE_1TO1_55S

SENSE

ISNS_P1V8GPU_N

ISNS_HDD_R_P

SENSE_DIFFPAIR SENSE_1TO1_55S

SENSE

THERM_1TO1_55SSENSE_DIFFPAIR

THERM

CPU_THERMD_P

THERM

ISNS_3V3_S3_R_N

SENSE_1TO1_55S

GPU_TDIODE_N

THERM

THERM_1TO1_55S

SATA_HDD_D2R_RDRV_OUT_N

SATASATA_90D

DISPLAYPORT

DP_85D

DP_IG_AUX_CH_C_P

USB2_EXCARD_CONN_N

USB

USB_85D

USB2_EXCARD_CONN_P

USB

USB_85D

CONN_USB2_BT_N

USB

USB_85D

CONN_USB2_BT_P

USB

USB_85D

USB

USB2_LT1_N

USB_85D

SATA_ODD_R2D_UF_P

SATASATA_90D

USB_LT2_P

USB

USB_85D

USB_LT2_N

USB

USB_85D

USB

USB_BRCRYPT_R_N

USB_85D

USB

USB_BRCRYPT_R_P

ISNS_PP5V_S0_P

SENSE_1TO1_55S

SENSE

SENSE_DIFFPAIR

GND

108 OF 132

99 OF 103

6

34

6

34

6

62 63

6

62 63

6 7 8

25 26 27 28 30 34 37 40

42 47 48 49 52 53 55 59 63 64

69 70 71 72 73 74 81 84 85 86

88

101

54

62

6

63

6

63

63 64

62

51

50

57

51

7 34 42 59 72 74

62

6 7

31 35 49 50 51 58 72 73 74

84 86

101

6

44

6

44

54

62

6

62 63

6

62 63

6

62 63

6

62 63

6

62 63

6

62 63

6

62 63

6

62 63

102

51

102

8

102

8

102

52 80 81

52

9

52

42

52

42

6

42

6

33

6

33

66

43

6

33

6

43

50 66

38

6

33

85

57

51

33 57 99

57

50

42 57

57 89

8

50

71

8

50

71

8

102

8

102

70

102

50 70

70

50 70

102

51

102

51

102

51

51 68

51

57

83

50

83

6

42

6

42

6

42

38

42

71

33 57 99

52

42

57

51

42 57

57

42 57

57 89

42 57

57

51

57

9

52

102

52 80 81

42

85

6

34

6

34

6

33

6

33

6

43

42

6

43

6

43

102

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_BOARD_INFO

VERSION

ALLEGRO

(MIL or MM)

BOARD UNITS

BOARD LAYERS

BOARD AREAS

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

NOTE: From T18 MLB, changed to reflect K17 mlb stackup.

NOTE: 100_DIFF_BGA is 100-ohms differential impedance on outer layers and 95-ohms on inner layers.

NOTE: 110_DIFF is 110-ohms differential impedance on outer layers and 105-ohms on inner layers.

K17 Board-Specific Spacing & Physical Constraints

0.090 MM0.155 MM

37_OHM_SE

Y*

=STANDARD

37_OHM_SE

Y

0.095 MM0.185 MM

TOP,BOTTOM

=STANDARD=STANDARD

* Y

=STANDARD

0.090 MM0.090 MM

50_OHM_SE

Y

0.095 MM

TOP,BOTTOM

0.110 MM

Y

55_OHM_SE

=STANDARD

*

=STANDARD

0.076 MM0.076 MM

Y

TOP,BOTTOM

55_OHM_SE

0.090 MM 0.090 MM

=DEFAULT

10 MM

Y

=DEFAULT

*

=DEFAULTSTANDARD =DEFAULT

DEFAULT

0 MM

10 MM

=50_OHM_SE

0 MM

* Y

=50_OHM_SE

BGA

CLK_PCIE

*

BGA_P2MM

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

NO_TYPE,BGA

MM

15.5.1

BGA

MEM_CLK

BGA_P2MM

*

**

BGA_P1MM

BGA0.1 MM

DEFAULT

* ?

STANDARD

?*

=DEFAULT

*

BGA_P1MM

?

=DEFAULT

0.4 MM

4:1_SPACING

* ?

?

0.3 MM

3:1_SPACING

*

?*

0.2 MM

2:1_SPACING

PCB Rule Definitions

SYNC_DATE=06/09/2009

SYNC_MASTER=K17_WFERRY

0.25 MM

* ?

2.5:1_SPACING

BGA_P2MM

* ?

=DEFAULT CLK_SLOW

*

BGA_P2MM

BGA

?

1.5:1_SPACING

*

0.15 MM

Y

TOP,BOTTOM

27P4_OHM_SE

0.310 MM 0.095 MM

=STANDARD

Y*

=STANDARD

27P4_OHM_SE

0.250 MM 0.250 MM

TOP,BOTTOM

Y

40_OHM_SE

0.165 MM 0.095 MM

0.135 MM

=STANDARD

* Y

=STANDARD

40_OHM_SE

0.090 MM

=STANDARD

*

=STANDARD

N

72_OHM_DIFF

Y

ISL3,ISL4

72_OHM_DIFF

0.154 MM

0.200 MM 0.200 MM

0.154 MM

Y

ISL9,ISL10

72_OHM_DIFF

0.154 MM

0.200 MM

0.154 MM

0.200 MM

Y

ISL2,ISL11

72_OHM_DIFF

0.175 MM 0.175 MM

0.200 MM 0.200 MM

TOP,BOTTOM

Y

72_OHM_DIFF

0.175 MM 0.175 MM

0.200 MM 0.200 MM

100_DIFF_BGA

0.075 MM

Y

ISL3,ISL4 0.125 MM0.125 MM

0.075 MM

100_DIFF_BGA

=100_OHM_DIFF

*

=100_OHM_DIFF=100_OHM_DIFF

100_DIFF_BGA

0.075 MM

ISL9,ISL10

Y

0.125 MM0.125 MM

0.075 MM

0.180 MM0.180 MM

Y

ISL3,ISL4

0.110 MM

85_OHM_DIFF

0.110 MM

=STANDARD

N

=STANDARD

*

=STANDARD

85_OHM_DIFF

N

90_OHM_DIFF

*

=STANDARD

=STANDARD =STANDARD

=STANDARD

Y

ISL3,ISL4

90_OHM_DIFF

0.220 MM0.220 MM

0.102 MM0.102 MM

ISL9,ISL10

90_OHM_DIFF

Y

0.220 MM 0.220 MM

0.102 MM0.102 MM

0.115 MM

Y

0.230 MM0.230 MM

ISL2,ISL11

90_OHM_DIFF

0.115 MM

ISL3,ISL4

100_OHM_DIFF

Y

0.080 MM

0.200 MM 0.200 MM

0.080 MM

=STANDARD

100_OHM_DIFF

=STANDARD

N

=STANDARD =STANDARD

*

=STANDARD

TOP,BOTTOM

100_OHM_DIFF

0.089 MM

Y

0.220 MM

0.089 MM

0.220 MM

TOP,BOTTOM

0.115 MM

90_OHM_DIFF

Y

0.230 MM 0.230 MM

0.115 MM

ISL9,ISL10

0.080 MM

100_OHM_DIFF

Y

0.200 MM0.200 MM

0.080 MM

ISL2,ISL11

100_OHM_DIFF

0.089 MM

Y

0.089 MM

0.220 MM0.220 MM

0.075 MM

ISL9,ISL10

110_OHM_DIFF

0.330 MM

Y

0.330 MM

0.075 MM

TOP,BOTTOM

110_OHM_DIFF

0.075 MM 0.075 MM

Y

0.330 MM 0.330 MM

ISL2,ISL11

0.075 MM

110_OHM_DIFF

0.330 MM

Y

0.075 MM

0.330 MM

0.075 MM

ISL3,ISL4

110_OHM_DIFF

Y

0.330 MM0.330 MM

0.075 MM

=STANDARD

* N

110_OHM_DIFF

=STANDARD =STANDARD

=STANDARD

0.180 MM 0.180 MM

Y

ISL9,ISL10

85_OHM_DIFF

0.110 MM 0.110 MM

0.125 MM0.125 MM

0.190 MM0.190 MM

ISL2,ISL11

Y

85_OHM_DIFF

0.190 MM0.190 MM

TOP,BOTTOM

Y

85_OHM_DIFF

0.125 MM 0.125 MM

=STANDARD =STANDARD

0.1 MM 0.1 MM

Y*

1:1_DIFFPAIR

=STANDARD

0.126 MM

2X_DIELECTRIC

*

?

0.189 MM

3X_DIELECTRIC

?

*

0.252 MM

4X_DIELECTRIC

*

?

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Apple A1297 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual