Apple A1286 Schematics

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

www.qdzbwx.com

7

6 5 4 3

2 1

REV ECN

DESCRIPTION OF REVISION

CK
APPD

DATE

2012-02-15

SCHEM,MLB_KEPLER_2PHASE,J31

FRB & RISK RAMP 02/15/12

(.csa)

46
47
48
49
50
51
52
53
54
55
56 SPI ROM
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90

50

SMC Support

51

LPC+SPI Debug Connector

52

SMBus Connections

53

Power Sensors: Load Side

54

Power Sensors: High Side, CPU, AXG

55

Thermal Sensors

56

Fan Connectors

57

WELLSPRING 1

58

WELLSPRING 2

59

Digital Accelerometer

61

62

AUDIO: CODEC/REGULATOR

63

AUDIO: LINE INPUT FILTER

64

AUDIO: DETECT/MIC BIAS

65

AUDIO: HEADPHONE FILTER

66

AUDIO: SPEAKER AMP

67

AUDIO: JACKS

68

AUDIO: JACK TRANSLATORS

69

DC-In & Battery Connectors

70

PBus Supply & Battery Charger

71

System Agent Supply

72

5V / 3.3V Power Supply

73

1.5V DDR3 Supply

74

CPU IMVP7 & AXG VCore Regulator

75

CPU IMVP7 & AXG VCore Output

76

CPU VCCIO (1V0R1V05 S0) POWER SUPPLY

77

Misc Power Supplies

78

Power FETs

79

Power Control 1/ENABLE

80

KEPLER PCI-E

81

KEPLER CORE/FB POWER

82

KEPLER FRAME BUFFER I/F

83

1V05 GPU / 1V35 FB POWER SUPPLY

84

GDDR5 Frame Buffer A

85

GDDR5 Frame Buffer B

86

KEPLER LVDS/DP/GPIO

87

KEPLER GPIOS,CLK & STRAPS

88

KEPLER PEX PWR/GNDS

89

GFX IMVP VCore Regulator

90

LVDS Display Connector

92

Muxed Graphics Support

93

Thunderbolt MUXing A

94

Thunderbolt Connector A

96

Graphics MUX (GMUX)

97

LCD Backlight Driver

Contents

J31_YONAS

J5_MLB

K18_MLB

J31_YONAS

J31_YONAS

J31_YONAS

K18_MLB

J30_MLB

J31_LINDA

J31_YONAS

K91_BEN

J31_AUDIO

J31_AUDIO

J31_AUDIO

J31_AUDIO

J31_AUDIO

J31_AUDIO

J31_AUDIO

J31_JACK

J31_JACK

J31_JACK

J31_JACK

J31_JACK

J31_JACK

J31_JACK

J31_JACK

J31_JACK

J31_MARY

J31_MARY

J31_SREE

D2_MLB_2P

J31_SREE

J31_JACK

J31_SREE

J31_SREE

J31_SREE

J31_SREE

J31_SREE

D2_MLB_2P

K18_MLB

K92_MLB

J31_WILL

T29_REF

K91_MARY

J31_KIRAN

Sync

Date

MASTER

04/19/2011

06/30/2009

MASTER

05/28/2009

04/27/2010

08/29/2011

04/27/2010

03/11/2011

08/03/2010

06/15/2010

08/03/2010

06/15/2010

08/19/2010

08/19/2010

06/02/2011

05/26/2011

06/02/2011

06/02/2011

03/21/2011

03/21/2011

05/26/2011

06/09/2011

07/06/2010

09/16/2011

04/27/2010

06/23/2010

05/10/2010

06/23/2010

10/25/2011

06/09/2011

11/11/2011

06/14/2011

06/14/2011

06/22/2011

10/11/2010

05/26/2010

04/27/2010

06/17/2011

06/10/2010

11/17/2011

09/21/2011

08/04/2011

04/27/2010

12/19/2011

Page

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10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

(.csa)

1

1
2
3
4
5
6
7
8
9

Table of Contents

2

Revision History

3

Power Block Diagram

4

Revision History

5

BOM Configuration

7

Functional / ICT Test

8

Power Aliases

9

Signal Aliases

10

CPU DMI/PEG/FDI/RSVD

11

CPU CLOCK/MISC/JTAG

12

CPU DDR3 INTERFACES

13

CPU POWER

14

CPU POWER AND GND

16

CPU DECOUPLING-I

17

CPU DECOUPLING-II

18

PCH SATA/PCIe/CLK/LPC/SPI

19

PCH DMI/FDI/PM/Graphics

20

PCH PCI/USB/TP/RSVD

21

PCH GPIO/MISC/NCTF

22

PCH POWER

23

PCH GROUNDS

24

PCH DECOUPLING

25

CPU & PCH XDP

26

Chipset Support

27

USB HUB & MUX

28

CPU Memory S3 Support

29

DDR3 SO-DIMM Connector A

30

DDR3 Byte/Bit Swaps

31

DDR3 SO-DIMM Connector B

33

SD Card Connector

34

DDR3/FRAMEBUF VREF MARGINING

35

X19/ALS/CAMERA CONNECTOR

36

Thunderbolt Host (1 of 2)

37

Thunderbolt Host (2 of 2)

38

Thunderbolt Power Support

39

ETHERNET PHY (CAESAR IV)

40

Ethernet Connector

41

FireWire LLC/PHY (FW643)

42

FireWire Port & PHY Power

43

FireWire Connector

45

SATA Redriver/Conn, IR, SIL

46

External A USB3 Connector

47

External B USB3 Connector

48

Front Flex Support

49

SMC45

Contents

MASTER

J31_MLB

K17_REF

MASTER

K17_REF

K18_MLB

J31_MLB

K18_MLB

J5_MLB

K92_MLB

K92_SUMA

K92_MLB

K92_SUMA

K92_MLB

K92_MLB

J31_ANNE

J5_MLB

J31_ANNE

J31_ANNE

J5_MLB

J5_MLB

J5_MLB

J31_ANNE

K92_MLB

J31_LINDA

K18_MLB

K92_SUMA

K92_SUMA

K92_SUMA

J31_YONAS

J31_ANNE

J30_MLB

T29_REF

T29_REF

T29_REF

K91_ERIC

K91_TRINHNI

K18_MLB

K91_MLB

T27_REF

J31_YONAS

J31_LINDA

J30_MLB

K18_MLB

J31_YONAS

D

C

B

Page

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

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Sync

Date

01/19/2012

05/26/2011

04/27/2010

01/19/2012

10/25/2011

09/08/2011

04/27/2010

06/10/2011

07/01/2011

08/11/2011

06/08/2010

10/26/2011

10/26/2011

10/26/2011

10/26/2011

10/26/2011

10/26/2011

10/26/2011

09/02/2011

11/14/2011

09/14/2011

11/09/2011

07/07/2011

11/11/2011

11/11/2011

09/19/2011

06/10/2011

05/05/2011

06/06/2011

10/25/2011

01/18/2012

10/25/2011

11/16/2011

10/25/2011

10/25/2011

10/25/2011

11/16/2011

10/31/2011

01/18/2012

04/27/2010

11/21/2010

06/20/2011

06/14/2011

08/03/2010

03/21/2011

Page

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

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TABLE_TABLEOFCONTENTS_ITEM

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TABLE_TABLEOFCONTENTS_ITEM

91
92
93
94
95
96
97
98

99
100
101
102
103
104
105

(.csa)

98

PCH VCCIO (1.05V) POWER SUPPLY

99

Power Sequencing EG/PCH S0

100

CPU Constraints

101

Memory Constraints

102

PCH Constraints 1

103

PCH Constraints 2

104

Ethernet/FW Constraints

105

Thunderbolt Constraints

106

SMC Constraints

107

GPU (Kepler) CONSTRAINTS

108

Project Specific Constraints

109

PCB Rule Definitions

130

Power Sensors: SMC Extended

131

Power Sensors: Debug ADC

132

Power Sensors: CPU Ripple

Contents

Sync

J31_JACK

J31_SREE

K92_MLB

K91_MLB

K92_MLB

J31_YONAS

K91_ERIC

T29_REF

J31_YONAS

K92_MLB

K18_MLB

K18_MLB

J31_YONAS

J31_YONAS

J31_YONAS

Date

09/16/2011

09/19/2011

08/09/2010

06/25/2011

08/09/2010

05/05/2011

08/03/2010

06/14/2011

08/11/2011

08/09/2010

04/27/2010

04/27/2010

09/12/2011

09/12/2011

08/24/2011

D

C

B

A

Schematic / PCB #’s

PART NUMBER

051-9585

820-3330

DRAWING

ABBREV=DRAWING

TITLE=MLB

LAST_MODIFIED=Wed Feb 15 20:30:03 2012

QTY

1 SCH

1 PCB

DESCRIPTION

SCHEM,MLB_KEPLER_2PHASE,J31

PCBF,MLB_KEPLER_2PHASE,J31

REFERENCE DES

CRITICAL

CRITICAL

CRITICAL

BOM OPTION

www.vinafix.vn

SIZE

A

D

DRAWING TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

3

SCHEM,MLB_KEPLER,J31

Apple Inc.

R

DRAWING NUMBER

051-9585

REVISION

3.0.0

BRANCH

PAGE

1 OF 132

SHEET

1 OF 105

1245678

8 7 6 5 4 3

12

2 DIMMS

RTC

PG 16

PG 19

J2500,J2550

XDP CONN

J2900

J3100

DIMM

PG 27,29

J5100

LPC + SPI CONN
Port80,serial

PG 23

U6100

SPI

Boot ROM

PG 55

J6950

DC/BATT

PG 63

ALS SENSOR

U5920

SMS SENSOR

THERMAL SENSOR

POWER SENSE 

J5650,5660

FAN CONN AND CONTROL

Ser

B,0 BSB

Prt

PG 46

U4900

SMC

I2C I2C

FanADC

PG 44

PG 32

PG 50

PG 50

PG 48

PG 51

POWER SUPPLY

D

C

U8000

GRAPHICS

NVIDIA KEPLER

PG 73

INTEL CPU

2.X GHZ

IVY BRIDGE

PG 9

DDR3-1067/1333MHZ

D

GPIO

PG 19 PG 17

U3600

4

20 31 5

CLK

BUFFER

PG 16

SATA

PG 16

T29

PG 33/34

J4500

SATA

ODD

CONN

HDD

CONN

PG 41

SATA

PG 41

DP/T29

MUX

PG 85

J4501

C

FDI

INTEL

PANTHER-POINT

MOBILE

U1800

DMI

PG 17

Misc

SPI

PG 16

LPC

PG 16

PWR

CTRL

U9220

DP DDC MUX

PG 84

J9400

MINI DP PORT

PG 84

B

U9270

LVDS DDC MUX

PG 84

J9000

LVDS

PG 17

PCI

PG 18

JTAG

PG 16

PEG

PG 16

PCI-E

(UP TO 16 LINES)

PG 16

LVDS CONN

PG 83

PG 17

PG 18

USB

(UP TO 14 DEVICES)

SMB

PG 16 

HDA

PG 16 

U2700

12
11 13

10

8 9

7

65

431 20

USB HUB

J4600

J4610

PG 25

EXTERNAL A

EXTERNAL B

J3501

BLUETOOTH

J4501/U4800

J5713/U5701

TRACKPAD/KEYBOARD

J4600

SMC DEBUG PORT

PG 42

PG 42

PG 32

PG 41/43

IR

PG 52

PG 42

B

SMBUS

CONNECTION

PG 47

DIMM

PG 27,29

U9600

GMUX

PG 86

www.qdzbwx.com

A

J3501

AirPort

PG 32

U4100 

J4310

FIREWIRE

FW643

PG 38

CONN

PG 40 PG 37

U3900 

ETHERNET

BCM57765B0

J4000 

ETHERNET

PG 36

J3300 

SDCARD READER

CONNCONN

PG 30

6 3

LINE INPUT

FILTER

U6201

AUDIO
CODEC

PG 56

U6610,6620,6630

HEADPHONE

PG 57 PG 58 PG 59

J6700,J6750

FILTER

AUDIO

SPEATKER

CONN

AMP

J6781,J6782

SPEATKER

SIZE

A

D

SYNC_MASTER=J31_MLB

PAGE TITLE

Revision History

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:

PG 60PG 60

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=04/19/2011

DRAWING NUMBER

051-9585

REVISION

3.0.0

BRANCH

PAGE

2 OF 132

SHEET

2 OF 105

124578

www.vinafix.vn

D

C

B

A

J6900

AC

ADAPTER

IN

3S2P

SMC

U4900

(PAGE 45)

COUGAR-POINT

(PAGE 16~21)

GMUX
U9600

(PAGE 88)

PORT A MCU

U9330

(PAGE 86)

SMC_BATLOW_L

PM_SLP_SUS_L

GMUX

U9600

XP25-5

(PAGE 88)

ISOLATE_CPU_MEM_L

PM_SLP_S3_L

PLT_RST_L

CPU_MEM_RESET_L

8 7 6 5 4 3

PPBUS_G3H

Q7840

P5VSUS_EN

POWER SWITCH

VIN

4.5V AUDIO
MAX8840

VIN

(PAGE 57)

PP3V3_S4_FET

P3V3S4_EN

PP1V5_S0_REG

PP1V8_GPU_FET

D6990

PPBUS_G3H

PP5V_SUS_FET

USB PORT

5V

VOUT1

U4600

VOUT2

(PAGE 42)

EN2

EN1

CTRL

(PAGE 54)

VOUT

U6200

T29_A_HV_EN

PP1V05_SUS_LDO

VOUT

SMC_GPU_1V8_ISENSE

Q5300

SMC_PBUS_VSENSE

V

PP5V_S3_RTUSB_A_ILIM

PP5V_S3_RTUSB_B_ILIM

VIN

LED

KB_BL
LT3491
U5850

PP4V5_AUDIO_ANALOG

T29 15V BOOST

VIN

(PAGE 35)

POWER SWITCH

VIN

FWPORT_PWR_EN

PPBUS_SW_LCDBKLT_PWR

UD180

(RD186)

PP1V8_S0GPU_ISNS

A

PPBUS_G3H

A

U5400

SMC_CPU_HI_ISENSE

PPBUS_G3H

A

U5410

SMC_GPU_HI_ISENSE

EN

FIREWIRE PORT

U4260

(PAGE 39)

EN

F9700

LCD_BKLT_EN

BKLT_PLT_RST_L

PP15V_T29_REG

VOUT

PPBUS_FW_FET

VOUT

&&

LP8550
U9701

EN

(PAGE 89)

LT3957
U3890

3A 32V FUSE

www.qdzbwx.com

Q9706

ENABLE

PP5V_S0_CPUVCCIOS0

DDRVTT_EN

PVDDCI_EN

UD120

PPBUS_SW_BKL

A

SMC_LCDBKLT_ISENSE

VIN

PPVOUT_SW_LCDBKLT

VOUT

SMC_LCDBKLT_VSENSE

PP5V_S3_GPUVCORE

GPUVCORE_EN

3.425V G3HOT
PM6640
U6990

(PAGE 63)

CPUVCCIOS0_EN

CPUIMVP_VR_ON

DDRREG_EN

V

CPU/AXG VCORE

VIN

EN

PP5V_S3_DDRREG

S5

S3

GPU VDDCI

VIN

0V9~1V15
ISL95870A

U9800

EN

(PAGE 90)

VDD/PVCC

GPU VCORE

ISL6263C

VR_ON

(PAGE 83)

R5388/U5388

PP3V42_G3H

CPU VCCIO

VIN

1V0 /

1.05V
ISL95870

EN

(PAGE 70)

MAX15119GTM

U7400

(PAGE 68)

VIN

1.5V

0.75V

TPS51916

U7300

(PAGE 67)

PVCCSA_EN

P1V0GPU_EN

P1V5FB_EN

VIN

U8900

U7600

CPU VOUT

PGOKA

PGOKB

VLDOIN

VOUT1

VOUT2

VOUT

PGOOD

VOUT

PGOOD

SMC_TPAD_RST_L

VOUT

PGOOD

PPVTT_S0_DDR_LDO

DDRREG_PGOOD

PGOOD

PPVDDCI_S0_REG

PVDDCI_PGOOD

SMC_GPU_ISENSE

SMC_ONOFF_L

SMC_CPUVCCIO_ISENSE

CPUVCCIOS0_PGOOD

U5450

A

SMC_CPU_ISENSE

U5460

A

SMC_AXG_ISENSE

CPUIMVP_PGOOD

CPUIMVP_AXG_PGOOD

PPDDR_S3_REG

SYSTEM AGENT

VIN

ISL95870A

U7100

EN

(PAGE 65)

VIN

EN1

1V0GPU/1V5 FB

1.003V(L/H)

EN2

1.503V(R/H)

ISL6236

U8300

(PAGE 77)

U5310

A

GPUVCORE_PGOOD

U5310

(R7640)

A

U5360
(R7350)

VOUT

PGOOD

VOUT1

SMC_GPU_1V0_ISENSE

VOUT2

POK1

POK2

V

VIN

SMC AVREF SUPPLY

MR1

MR2

A

P1V0GPU_PGOOD

P1V5FB_PGOOD

J31 POWER SYSTEM ARCHITECTURE

F6905
6A FUSE

DCIN(18.5V)

SMC_DCIN_ISENSE

J6950

(9 TO 12.6V)

MOBILE

U1800

(N8)

(18)

PB7A
PB16B

PB17A

PB17B

PB18A

PL25A

$CDS_IMAGE|O.jpg|416|272

$CDS_IMAGE|O_0.jpg|416|272

$CDS_IMAGE|O_1.jpg|416|272

PPVBAT_G3H_CONN

P5VS3_EN

P3V3S5_EN

SMC_BATLOW_L

H10

M2

SMC_PM_G2_EN

SLP_S4#(H4)

SLP_SUS

SLP_S5*(D10)

SLP_S3#(F4)

LCD_PWR_EN

T29_A_HV_EN_R

EN1

EN2

PGOOD1

PM_SLP_S5_L

$CDS_IMAGE|R.jpg|272|166

XDP_DB2_WOL_EN

(D14)

FW_PWR_EN_PCH

(V13)

AUD_IPHS_SWITCH_EN_PCH

(U2)

PM_SLP_S3_L

$CDS_IMAGE|R.jpg|272|166

3.3V/5.0V

(A)

U7940

(C)

(PAGE 73)

LCD_BKLT_EN

EG_RAIL1_EN

EG_RAIL2_EN

EG_RAIL3_EN

EG_RAIL4_EN

ALL_EG_PGOOD

(Y)

SUS ENABLE

Q7055

CHGR_BGATE

VIN

VREG5

VOUT1

5V

(L/H)

VOUT2

3.3V
(R/H)

TPS51980

U7201

(PAGE 66)

PGOOD2

P3V3S5_PGOOD

P5VS3_PGOOD

P3V3S5_EN

RC
DELAY

RC

P3V3S3_EN

DELAY

DDRREG_EN

RC

DELAY

P5VS3_EN

PM_SLP_S4_L

PM_SLP_SUS_L

R7916

R2526

$CDS_IMAGE|R.jpg|272|166

(A2)

R9334

T29_A_HV_EN

P5VSUS_EN

P3V3SUS_EN

P3V3GPU_EN

GPUVCORE_EN

P1V0GPU_EN

P1V5FB_EN

P1V8GPU_EN

PM_ALL_GPU_PGOOD

PM_SLP_S4_L

PM_SLP_S3_L

PP18V5_DCIN_CONN

R7020

A

SMC_RESET_L

PP5V_S3_REG

PP3V3_S5_REG

P3V3S4_EN

WOL_EN

U2150

(Y2)

(PAGE 24)

U2152

(A2)

(PAGE 24)

P1V5CPU_EN

MEMVTT_EN

MEM_RESET_L

FW_PWR_EN

(Y1)

RC

DELAY

RC

DELAY

RC

DELAY

RC

DELAY

RC

DELAY

RC

DELAY

ISL6259HRTZ

VIN

PBUS SUPPLY/

BATTERY CHARGER

SMB_RST_N

(PAGE 64)

PP3V3_S5

Q7870

Q7810

Q7830

TBT_PWR_EN

R7978

PM_SLP_S3_R_L

P1V8S0_EN

P1V2S0_EN

CPUVCCIOS0_EN

P1V5S0_EN

PVCCSA_EN

PCHVCCIOS0_EN

P5VS0_EN

P3V3S0_EN

PBUSVSENS_EN

U7000

PP5V_S5_LDO

P1V5CPU_EN

PP5V_S5_LDO

PP3V3_S0GPU_FET

P3V3GPU_EN

PP3V3_S3_FET

P3V3S3_EN

PP3V3_S0_FET

P3V3S0_EN

P1V8S0_EN

SMC_DCIN_VSENSE

VOUT

SMC_BMON_ISENSE

PPVBAT_G3H_CHGR_R

VIN

ON

SLG5AP020

U7801

(PAGE 72)

VIN

TPS61045

U5805

(PAGE 54)

Q7922

PM_SLP_S3_L & WOL_EN & SMC_ADAPTER_EN

TBT_PWR_EN

VIN

FW_PWR_EN

P1V5S0_EN

P1V2S0_EN

Q7820

EN

P1V8GPU_EN

V

Q5310

PPVBUS_G3H

R7050

PP5V_S5_P5VSUSFET

PPDDR_S3_REG

G

VOUT

PP3V3_ENET_FET

T29 SWITCH

3.3V

TPS22924

VIN

U3810

(PAGE 35)

TPS22924

U4201

VOUT

(PAGE 39)

EN

LCD_PWR_EN

VIN

EN

PP3V3_SUS_FET

PP3V3_SUS_P1V05SUSLDO

P3V3SUS_EN

VIN

ISL8014A

U7720

(PAGE 71)

A

P1V5S3RS0FET_GATE

PP18V5_S4

Q7860

P5VS0_EN

PP3V3_S0_AUDIO

PP3V3_T29_FET

VOUT

EN

PP3V3_FW_FET

FPF1009

U9000

VIN

(PAGE 84)

TPS62201

EN

U7710

(PAGE 71)

1V2_S0(GMUX)

TPS62201
U7760

(PAGE 71)

VOUT

P1V8S0_PGOOD

PGOOD

VIN

EN

1V8GPU FET

NCP4543IMN5RG-A

U7880

(PAGE 72)

R6990

Q7801

PP1V5_S3RS0_FET

SMC_SYS_KBDLED

PP5V_S0_FET

VOUT

EN

VIN

PP1V2_S0_REG

VOUT

VIN

EN

PP1V8_S0_REG

F7040

8A FUSE

USB_PWR_EN

SHND

Q7800

PP3V3_SW_LCD_UF

VOUT

TPS720105

U7740

(PAGE 71)

VOUT

6 3

SMC RESET

SN0903048

U5010

(PAGE 46)

PPCPUVCCIO_S0_REG

(PAGE 39)

V

SMC_CPU_VSENSE

PPVCORE_S0_CPU

SMC_AXG_VSENSE

V

PPVCORE_S0_AXG_REG

PP1V5_S3

SMC_DDR3_ISENSE

U5360

(R7140)

PPVCCSA_S0_REG

A

SMC_CPUVCCSA_ISENSE

PVCCSA_PGOOD

PP5V_S0_VMON

PP1V5_S3RS0_VMON

PP1V05_S0_VMON

UD141

(RD145)

PP1V0_S0GPU_REG

A

PP1V5_GPU_REG

GPUVCORE_PGOOD

P1V5FB_PGOOD

P1V0GPU_PGOOD

SMC_GPU_VSENSE

PPVCORE_GPU_REG

RESET

REFOUT

TPS22924

U4202

VOUT

VIN

EN

FW_PWR_EN

PP3V3_S0_PWRCTL

SMC_RESET_L

PP3V3_S5_AVREF_SMC

U3815 & U3816

1V05 T29

SWITCH

(PAGE 35)

EN

TBT_PWR_EN

PP3V3_S0_VMON

V2MON

V3MON

V4MON

R9990

PM_ALL_GPU_PGOOD

ALL_EG_PGOOD

VOUT

ISL88042IRTEZ

TRST = 200mS

VIN

PP1V0_FW_FET_R

PP1V05_T29_FET

U9950

PM_PCH_PWROK

CPUIMVP_VR_ON

P1V5S0_PGOOD

P1V8S0_PGOOD

P5VS3_PGOOD

CPUVCCIOS0_PGOOD

PCHVCCIOS0_PGOOD

PVCCSA_PGOOD

ALL_SYS_PWRGD_R

VCC

U7960

RST*

(PAGE 73)

WHISTLER PCI-E

PWRGOOD
(AH16)

(PAGE 74)

GRAPHICS MUX

PL25A
(N1)

(PAGE 88)

PM_S0_PGOOD

PM_PCH_SYS_PWROK

U9950

COUGAR_POINT

SYS_RERST#

ACPRESENT/GPIQ31

PLTRST#

SYS_PWROK

PROCPWRGD

DRAMPWROK

RSMRST#

U1800

(PAGE 16~21)

3V3 SUS DETECT

U7930

(PAGE 73)

CPU

SM_DRAMPWROK

UNCOREPWRGOOD

U1000

(PAGE 9~13)

ALL_SYS_PWRGD
S5_PWRGD

PM_SLP_S5_L

PM_SLP_S4_L

PM_SLP_S3_L

U8000

U9600

SMC_ONOFF_L

SYNC_MASTER=K17_REF

PAGE TITLE

WT2CCP0/PH0(K3)

SSIOFSS/PA3

S5_PWRGD(L9)

PQ7/IRQ131(L6)

WT3CCP1/PH5

WT3CCP0/PH4

PQ6/IRQ130(M6)

PQ5/IRQ129(K5)

PQ4/IRQ128(N6)

LM4FSXAH5BB

(PAGE 44)

Power Block Diagram

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

PWRBTN#

DPWROK

(AY25)

(C60)

SMC

T1CCP1/PJ1

U4900

(E20)

(K3)

(E22)

(H20)
(C6)

(AY11)

(C21)

RESET

RESET*
(K51)

(B9)

(M3)

(H4)

(J3)

VREFA+

(D2)

RST*

(G10)

PM_PWRBTN_L

PM_SYSRST_L

PM_DSW_PWRGD

SMC_ADAPTER_EN

PLT RESET L

CPU_PWRGD

PM_MEM_PWRGD

PM_RSMRST_L

PM_MEM_PWRGD

CPU_PWRGD

CPU_RESET_L

SMC_ADAPTER_EN

PM_DSW_PWRGD

PM_SYSRST_L

PM_PWRBTN_L

PP3V3_S5_AVREF_SMC

SMC_RESET_L

12

SYNC_DATE=06/30/2009

DRAWING NUMBER

051-9585

REVISION

3.0.0

BRANCH

PAGE

3 OF 132

SHEET

3 OF 105

124578

SIZE

D

C

B

A

D

www.vinafix.vn

8 7 6 5 4 3

12

D

C

D

C

SIZE

B

A

D

B

A

6 3

SYNC_MASTER=MASTER

PAGE TITLE

Revision History

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=MASTER

DRAWING NUMBER

051-9585

REVISION

3.0.0

BRANCH

PAGE

4 OF 132

SHEET

4 OF 105

124578

www.vinafix.vn

BOM VARIANTS - FSB

BOM NUMBER

639-3860

639-3861

639-3862

639-3863

639-3864

639-3865

D

607-9557

085-4620

SUB BOMS

PART NUMBER

8 7 6 5 4 3

TABLE_BOMGROUP_HEAD

BOM NAME

PCBA,MLB_2P,FSB,2.3,FOX,512_HYN,REN,J31,F327

PCBA,MLB_2P,FSB,2.3,MOL,512_SAM,FAIR,J31,F32C

PCBA,MLB_2P,FSB,2.6,MOL,1G_HY,FAIR,J31,F325

PCBA,MLB_2P,FSB,2.6,FOX,1G_SAM,REN,J31,F324

PCBA,MLB_2P,FSB,2.7,FOX,1G_HY,REN,J31,F328

PCBA,MLB_2P,FSB,2.7,MOL,1G_SAM,FAIR,J31,F329

CMN PTS,PCBA,MLB_KEPLER,J31

J31 MLB_KEP_2P DEVELOPMENT BOM

QTY

085-4620

607-9557 CRITICAL

1

1

DESCRIPTION

J31 MLB_KEP_2P DEVELOPMENT BOM

CMN PTS,PCBA,MLB_KEP_2P,J31

REFERENCE DES

DEVEL

CMNPTS

J31_CMNPTS,SODIMM:FOXCONN,CPU:2_3GHZ,FB_512_HYNIX,FET:REN,DEVEL_BOM,GPUDEC:EXP,EEEE:F327

J31_CMNPTS,SODIMM:MOLEX,CPU:2_3GHZ,FB_512_SAMSUNG,FET:FAIR,DEVEL_BOM,GPUDEC:EXP,EEEE:F32C

J31_CMNPTS,SODIMM:MOLEX,CPU:2_6GHZ,FB_1G_HYNIX_A_DIE,FET:FAIR,DEVEL_BOM,GPUDEC:EXP,EEEE:F325

J31_CMNPTS,SODIMM:FOXCONN,CPU:2_6GHZ,FB_1G_SAMSUNG,FET:REN,DEVEL_BOM,GPUDEC:EXP,EEEE:F324

J31_CMNPTS,SODIMM:FOXCONN,CPU:2_7GHZ,FB_1G_HYNIX_A_DIE,FET:REN,DEVEL_BOM,GPUDEC:EXP,EEEE:F328

J31_CMNPTS,SODIMM:MOLEX,CPU:2_7GHZ,FB_1G_SAMSUNG,FET:FAIR,DEVEL_BOM,GPUDEC:EXP,EEEE:F329

CRITICAL

CRITICAL

BOM OPTIONS

J31_COMMON

J31_DEVEL:PVT

BOM OPTION

DEVEL_BOM

J31_CMNPTS

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

­|

PART NUMBER

826-4393

826-4393

826-4393

826-4393

QTY

1

1

1

1

1

826-4393

1

DESCRIPTION

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

/ EEEE #’sBar Code Labels

REFERENCE DES

[EEEE_F327]

[EEEE_F32C]

[EEEE_F325]

[EEEE_F324]

[EEEE_F328]

[EEEE_F329]

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL826-4393

CRITICAL

BOM OPTION

EEEE:F327

EEEE:F32C

EEEE:F325

EEEE:F324

EEEE:F328

EEEE:F329

12

D

BOM GROUPS

C

Module Parts

PART NUMBER

B

A

BOM GROUP

J31_COMMON

J31_COMMON1

J31_COMMON2

J31_PROGPARTS

J31_PROGPARTS1

J31_PVT

J31_DEVEL:ENG

J31_DEVEL:FSB

J31_DEVEL:PVT

IVB_PPT_XDP

DDRVREF_DAC,VREF:ENG_M3,IVB_PPT_XDP,GMUX_JTAG_CONN,LPCPLUS_CONN:YES,BKLT:ENG,S0PGOOD_ISL,CPURIPPLE_ENG,LOADISNS:YES,XWLOADISNS:YES,DEBUG_ADC

DDRVREF_DAC,VREF:ENG_M3,IVB_PPT_XDP,LPCPLUS_CONN:YES,BKLT:PROD,S0PGOOD_ISL,LOADISNS:YES,XWLOADISNS:NO

ALTERNATE,COMMON,J31_COMMON1,J31_COMMON2,J31_PROGPARTS,J31_PROGPARTS1,UVGLUE_J31,J31_PVT

CPUMEM_S0,RAMCFG_SLOT,USBHUB2513B,HUB_3NONREM,SMC_PACKAGE:PROD,MOJO:YES,TBTHV:P15V,SKIP_5V3V3:AUDIBLE

BTPWR:S4,TPAD:Z2,T29:YES,TBTBST:Y,SDRV_PD,SDRVI2C:MCU,T29_DP_HPD:ALL_OR,LPCPLUS_R:YES,MEM_VDD_SEL:GPIO15,GPU:2P

GMUX_PROG,IR_PROG,TPAD_PROG:FSB,ENETROM_PROG:FSB,T29ROM:PROG,T29MCU:PROG

VREF:PROD,XDP,XDP_CPU:BPM,BKLT:PROD,LOADISNS:NO,XWLOADISNS:NO

XDP,XDP_CONN_PCH,XDP_CONN_CPU,XDP_CPU:BPM,XDP_PCH

BOM GROUP
VREF:PROD

VREF:ENG_M3

VREF:ENG_LDO

QTY

337S4266

337S4267

337S4268

337S4269 CRITICAL

337S4239

338S1072

338S0753

333S0619

333S0620

333S0631

333S0609

725-1479

516S0806 CRITICAL

516-0246

516-0245

516S0805 CRITICAL

516-0246

376S0964

376S0965 CRITICAL

376S0979

376S0874 CRITICAL

376S0826

376S0617

376S0917

1

1

1

1

1

1

1

1

4

4

4

4

4

1

1

1

1

1

1

1

2

2

2

2

1

1

1

1

DESCRIPTION

IC,CPU,IVB,S,R0MP,PRQ,E1,2.3,45W,4+2,1.2,6M,BGA

IC,CPU,IVB,S,R0MM,PRQ,E1,2.6,45W,4+2,1.25,6M,BGA

IC,CPU,IVB,S,R0MK,PRQ,E1,2.7,45W,4+2,1.25,8M,BGA

IC,PCH,PPT,C1,SLJ8C,PRQ,BD82HM77

IC,GPU,NV GK107-GTX-QS-A2

IC,ASSP,LIGHTRIDGE,PRQ,S LJJY,FCBGA,15X15MM,C1

IC,FW643-E,1394B PHY/OHCI LINK/PCI-E,12

IC,PI3VEDP212,X2 DISPLAYPORT 2:1 MUX,QFN

IC,SGRAM,GDDR5,32MX32.1.25GHz,G-DIE,HF

IC,SDRAM,GDDR5,32MX32,1.5GHz,VEGA 44NM,B-DIE

IC,SGRAM,GDDR5,64MX32,5GBPS,D-DIE,HF

IC,SGRAM,GDDR5,64MX32,5GBPS,A-DIE,HF

IC,SGRAM,GDDR5,64MX32,4.2GBPS,M-DIE,HF

MLB LOCTITE UV EB CPU,PCH,T29,GPU,K91

CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA,FOXCONN

CONN,204P,SODIMM,SOCKET,DDR3,p=0.6M,FOXCONN

CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA,MOLEX

CONN,204P,SODIMM,SOCKET,DDR3,p=0.6M,MOLEX

CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA,MOLEX

CONN,204P,SODIMM,SOCKET,DDR3,p=0.6M,FOXCONN

RJK0225

RJK0225

FDMC0225

FDMC0202S

FET,N-CH,30V,3.6MOHM,LF,HF,RJK0332DPB

FET,N-CH,30V,30A,6.7MOHM,RJK0305DPB

FET,N-CH,30V,3.6MOHM,LF,HF,FDMS0355S

FET,N-CH,30V,14A,13MOHM,FDMS0349

REFERENCE DES

U8400,U8450,U8500,U8550

U8400,U8450,U8500,U8550

U8400,U8450,U8500,U8550

U8400,U8450,U8500,U8550

U8400,U8450,U8500,U8550

BOM OPTIONS

SMC_PROG:RR,BOOTROM_PROG:FSB

LPCPLUS_CONN:YES,XDP_CONN_CPU

BOM OPTIONS

VREFDQ:M1_M3,VREFCA:LDO

VREFDQ:M1_M3,VREFCA:LDO_DAC

VREFDQ:M1_DAC,VREFCA:LDO_DAC

CRITICAL

U1000

U1000

U1000

U1800

U8000

U3600

U4100

U9390

UV_GLUE_J31

J3100

J2900

J3100

J2900

J3100

J2900

Q7330,Q8360

Q7335,Q8361

Q7330,Q8360

Q7335,Q8361

Q7030

Q7035

Q7030

Q7035

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL353S3055

CRITICAL

CRITICAL

CRITICAL

CRITICAL333S0630

CRITICAL

CRITICAL

CRITICAL

CRITICAL516S0805

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL376S1018

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

BOM OPTION

CPU:2_3GHZ

CPU:2_6GHZ

CPU:2_7GHZ

T29:YES

FB_512_SAMSUNG

FB_512_HYNIX

FB_1G_SAMSUNG

FB_1G_HYNIX_A_DIE

FB_1G_HYNIX_M_DIE

UVGLUE_J31

SODIMM:FOXCONN

SODIMM:FOXCONN

SODIMM:MOLEX

SODIMM:MOLEX

SODIMM:HYBRID

SODIMM:HYBRID

FET:REN

FET:REN

FET:FAIR

FET:FAIR

FET:REN

FET:REN

FET:FAIR

FET:FAIR

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

PD Parts

PART NUMBER

452-1708

452-1708

725-1607

Alternate Parts

(Alternate)

PART NUMBER

157S0058

152S0896

353S2805

128S0303

353S3085

376S0972 376S0612

376S0855

138S0676 138S0691

138S0652 138S0648

138S0681

376S0977

353S2592

335S0550

371S0709

138S0671

514-0788

155S0578

138S0681

138S0671

155S0625

376S0777

157S0084

376S0958

376S1053

371S0713

127S0134

197S0431

QTY

2

2

1

(Primary)

ALTERNATE FOR
PART NUMBER

157S0055

152S0518

155S0329155S0457

353S2603

128S0257128S0264

128S0282

353S1658

376S0613

138S0638

152S0796152S0685

376S0859

353S3199

335S0777

371S0652

138S0673

514-0671

155S0367

138S0638

138S0673

155S0559

376S0761

157S0055

353S3055353S3312

376S0953

376S0604

371S0558

128S0329128S0311

127S0111

127S0090127S0127

197S0432

197S0343197S0434

197S0343197S0435

DESCRIPTION

SCR,M1.6X0.35X6.0,D4,HO.3,BLK,M97

SCR,M1.6X0.35X6.0,D4,HO.3,BLK,M97

INSULATOR,GPU,J31

BOM OPTION

REF DES

COMMENTS:

ALL

Delta alt to TDK Magnetics

ALL MAG LAYERS ALT TO CYNTEC

MAG LAYERS ALT TO MURATAALL

Fairchild wafer option

ALL

ALL

Sanyo alt to Kemet

ALL

Panasonic alt to Sanyo

ALL

ST Micro alt to LT

ALL

ROHM alt to Toshiba N-FET

ALL

Diodes alt to Toshiba dual N-FET

Murata alt to Samsung cap

ALL

Samsung / Murata alt for Taiyo Yuden

ALL

ALL

Taiyo Yuden alt for Samsung

ALL

Dale/Vishay/TDK alt for Cyntec

ALL

Diodes alt for Rohm

U6201 AUDIO CODEC OLD REV IS ALTERNATE FOR NEW REV

ALL

ALL

add 4K byte as alternative to 2K

ALL

NXP alternate for pin diodes

ALL

Taiyo Yuden alt for Murata 10 uF caps

Acon (with liteon) alt to Acon

ALL

ALL

Tayo Yuden alt to Murata inductors

ALL

Tayo Yuden alt to Samsung caps

ALL

Tayo Yuden alt to Murata caps

ALL

Murata alt to TDK cm mode filter

AON alternate to Siliconix

ALL

ALL

TDK alternate for ethernet transformer

NXP alternate to Pericom DP mux

ALL

For Q7260, Fairchild alt to Ren.

ALL

ALL

Radar 10562726

ALL

Radar 10562508

ALL

Radar 10257464

ALL

Radar 10360888

ALL

Radar 10382328

RADAR 10670230

ALL

ALL

RADAR 10739227

ALL

RADAR 10739227

REFERENCE DES

SODIMM_SCREW1,SODIMM_SCREW2

SODIMM_SCREW3,SODIMM_SCREW4

GPU_INSULATOR

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

CRITICAL

CRITICAL

CRITICAL

CRITICAL

Programmables - All Builds

PSOC

ETHERNET ROM

SMC

EFI ROM

BOM OPTION

6 3

341S3099

341S3351

341S3227 CRITICAL

341S3522

336S0042

341S2384

341S3430

335S0777 CRITICAL

341S3365

335S0852 CRITICAL

335S0663

341S3096

338S0895

341S3258

341S3294

341S3401

341S3481

341S3296

341S3297 CRITICAL

335S0740

341S3257

341S3344

341S3419

341S3454

341S3510

341S3476

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

IC,TP PSOC,K9x,DVT,PVT,J31

IC,TP PSOC,PROTO1,J31

IC,TP PSOC,PROTO2,PROTO3-Z2,J31

IC,TP PSOC,PIB,J31

IC,TP PSOC,FSB,J31

IC,CPLD,LATTICE,GMUX,K91/K91F,J31

IC,PLD,LATTICE,LFXP2-5E-5,132 BALL CSBGA

IR,ENCORE II,CY7C63833-LFXC

IC,T29 EEPROM,LR,J30/J31

IC,EEPROM,SERIAL,8KB,SOIC

IC,PROGRMD,LPC1112A,T29 PORT MCU,PVT,HVQFN25,J31

IC,MCU,32B,LPC1112A,16KB/2KB,HVQFN25

IC,GPUROM,J31,BLANK

IC,FLASH,SERIAL,SPI,1MBIT,2V7,8P,SOIC

IC,ENET ROM,1MBIT,DVT,PVT,K90i/K91x,J31

IC,PRGRMD,ENET,SPI ROM,FSB,J30/J31

IC,SMC,HS8/2117,9MMX9MM,TLP

IC,SMC,DEVELOPMENT-PROTO0,J31

IC,SMC,DEVELOPMENT-PROTO1,J31

IC,EXTERNAL,PROTO2,PROTO3,J31

IC,SMC,EXTERNAL,PIB,V2.1A83,A3,J31

IC,SMC,EXTERNAL,FSB,V2.1A143,J31

IC,SMC,EXTERNAL,RISKRAMP,J31

64 MBIT SPI SERIAL DUAL I/O FLASH

IC,EFI,ROM,PROTO0, J31

IC,EFI,ROM,PROTO1, J31

IC,EFI,ROM,PROTO2,J31

IC,EFI,ROM,PROTO3,J31

IC,EFI,ROM,POST-PIB,J31

IC,EFI,ROM,FSB,J31

SYNC_MASTER=K17_REF

PAGE TITLE

U5701

U5701

U5701

U5701

U5701

U9600

U9600

U4800

U3690

U3690

U9330

U9330

U8701

U3990

U3990

U3990

U4900

U4900

U4900

U4900

U4900

U4900

U4900

U6100

U6100

U6100

U6100

U6100

U6100

U6100

CRITICAL

CRITICAL

CRITICAL341S3489

CRITICAL

CRITICAL341S2830

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL337S3997

CRITICAL

CRITICAL

CRITICAL341S3492

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

BOM Configuration

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

TPAD_PROG:PROTO0

TPAD_PROG:PROTO1

TPAD_PROG:PROTO3

TPAD_PROG:PIB

TPAD_PROG:FSB

GMUX_PROG

GMUX_BLANK

IR_PROG

T29ROM:PROG

T29ROM:BLANK

T29MCU:PROG

T29MCU:BLANK

GPUROM:BLANK

ENETROM_BLANK

ENETROM_PROG:PROTO3

ENETROM_PROG:FSB

SMC_BLANK

SMC_PROG:PROTO0

SMC_PROG:PROTO1

SMC_PROG:PROTO3

SMC_PROG:A3_PIB

SMC_PROG:FSB

SMC_PROG:RR

BOOTROM_BLANK

BOOTROM_PROG:PROTO0

BOOTROM_PROG:PROTO1

BOOTROM_PROG:PROTO2

BOOTROM_PROG:PROTO3

BOOTROM_PROG:PIB2

BOOTROM_PROG:FSB

SYNC_DATE=05/28/2009

DRAWING NUMBER

051-9585

REVISION

3.0.0

BRANCH

PAGE

5 OF 132

SHEET

5 OF 105

124578

SIZE

C

B

A

D

www.vinafix.vn

8 7 6 5 4 3

J5713 (KEY BOARD CONN)

PP3V3_S4

TRUE

6 TPs

32

32 95

32 95

6 64

54

6 7

54

53 54

53 54

53 54

53 54

53 54

54

53 54

53 54

53 54

53 54

53 54

53 54

53 54

53 54

53 54

6 45 48 99

6 45 48 99

64

64

64
65

6 45 48 99

6 45 48 99

6 64

6
7

6 45 48 99

6 45 48 99

45 46 64

6 64

10 TPs

2 TPs

2 TPs

3 TPs

7 TPs

3 TPs

7 TPs

I1103

PP3V42_G3H

TRUE

I1102

WS_KBD1

TRUE

I1104

WS_KBD2

TRUE

I1105

WS_KBD3

TRUE

I1107

WS_KBD4

TRUE

I1106

WS_KBD5

TRUE

I1108

WS_KBD6

TRUE

I1109

WS_KBD7

TRUE

I1110

WS_KBD8

TRUE

I1111

WS_KBD9

TRUE

I1112

WS_KBD10

TRUE

I1113

WS_KBD11

TRUE

I1114

WS_KBD12

TRUE

I1115

WS_KBD13

TRUE

I1117

WS_KBD14

TRUE

I1116

WS_KBD15_CAP

TRUE

I1118

WS_KBD16_NUM

TRUE

I1119

WS_KBD17

TRUE

I1120

WS_KBD18

TRUE

I1122

WS_KBD19

TRUE

I1121

WS_KBD20

TRUE

I1123

WS_KBD21

TRUE

I1124

WS_KBD22

TRUE

I1125

WS_KBD23

TRUE

I1127

WS_KBD_ONOFF_L

TRUE

I1126

WS_LEFT_SHIFT_KBD

TRUE

I1128

WS_LEFT_OPTION_KBD

TRUE

I1129

WS_CONTROL_KBD

TRUE

I1130

TRUE

J6950 (BIL CABLE CONN)

TRUE

I1150

TRUE

I1149

TRUE

I1151

TRUE

I1152

TRUE

FUNC_TEST

I640

I602

I604

I605

I606

I610

I612

I611

I623

I620

I621

I618

I615

I616

I614

I627

I626

I639

I637

I636

I709

I714

I1160

I1161

I1613

I1612

I1614

I1615

I1592

I1591

I1593

I1594

I1595

I1596

I1617

I1616

I1618

I1619

I1620

I1622

I1621

I1834

I1835

GND

PP5V_S3_IR_R
SMC_LID_R
IR_RX_OUT
SYS_LED_ANODE

GND

POWER RAILS

TRUE

PM_SLP_S3_L

PP0V75_S0_DDRVTT

TRUE

PP1V05_S0

TRUE

PP1V05_S0GPU

TRUE

PP1V0_FW_FWPHY

TRUE

PP1V2_ENET

TRUE

PP1V2_S0

TRUE

PP1V5_S3

TRUE

PP1V8_S0

TRUE

PP3V3_ENET

TRUE

PP3V3_FW_FWPHY

TRUE

PP3V3_S0

TRUE

PP3V3_S3

TRUE

PP3V3_S5

TRUE

PP3V3_S5_AVREF_SMC

TRUE

PP3V42_G3H

TRUE

PP5V_S0

TRUE

PP5V_S3

TRUE

PPBUS_G3H

TRUE

PPDCIN_G3H

TRUE

PPVCORE_GPU

TRUE

PPVCORE_S0_CPU

TRUE

PPVP_FW

TRUE

PPVTTDDR_S3

TRUE

TP_FW643_SCIFCLK

TRUE

TP_FW643_SCIFDAIN

TRUE

TP_FW643_SCIFDOUT

TRUE

TP_FW643_SCIFMC

TRUE

TP_FW643_SDA

TRUE

TP_FW643_SE

TRUE

TP_FW643_SM

TRUE

TP_FW643_CE

TRUE

TP_FW643_FW620_L

TRUE

TP_FW643_JASI_EN

TRUE

DMI_S2N_N<1>

TRUE

DMI_S2N_P<1>

TRUE

FDI_DATA_N<1>

TRUE

FDI_DATA_P<1>

TRUE

FDI_FSYNC<1..0>

TRUE

FDI_LSYNC<1..0>
FDI_INT

TRUE

FDI_DATA_N<7..4>

TRUE

FDI_DATA_P<7..4>

TRUE

NC NO_TESTs

NO_TEST

Functional Test Points

J5650 (LEFT FAN CONN)

FUNC_TEST

TRUE

TRUE
TRUE

D

TRUE

I1493

TRUE
TRUE
TRUE

TRUE

I557

TRUE

I558

TRUE

I559

TRUE

J5100

TRUE

I1672

I1671

J6781 & J6782 (SPEAKERS CONN)

TRUE

I989

TRUE

I990

TRUE

I992

TRUE

I991

TRUE

I994

TRUE

I993

C

TRUE

I995

TRUE

I996

TRUE

I997

TRUE

I998

TRUE

I1000

TRUE

I1001

TRUE

I1002

TRUE

I1004

TRUE

I1003

TRUE

I1005

TRUE

I1007

TRUE

I1006

TRUE

I1009

TRUE

I1008

TRUE

I1010

TRUE

I1011

TRUE

I1012

TRUE

I1014

TRUE

I1013

TRUE

I1015

TRUE

I1016

TRUE

I1017

TRUE

I1018

TRUE

B

A

I1019

TRUE

I1020

TRUE

I1022

TRUE

I1021

TRUE

J4500 (SATA ODD CONN)

PP5V_SW_ODD

TRUE

I1024

SMC_ODD_DETECT

TRUE

I1026

SATA_ODD_D2R_C_P

TRUE

I1025

SATA_ODD_D2R_C_N

TRUE

I1028

SATA_ODD_R2D_P

TRUE

I1027

SATA_ODD_R2D_N

TRUE

I1029

TRUE

J4501 (SATA HDD CONN)

TRUE

I1032

TRUE

I1031

TRUE

I1033

TRUE

I1035

TRUE

I1034

TRUE

TRUE

I1689

TRUE

I1690

TRUE

I1691

TRUE

I1692

J5815 (KBD BACKLIGHT CONN)

TRUE

I1145

TRUE

I1146

PP5V_S0

FAN_LT_PWM
FAN_LT_TACH

TRUE

GND

J5660 (RIGHT FAN CONN)

PP5V_S0
FAN_RT_PWM
FAN_RT_TACH
GND

J6780 (MIC CONN)

BI_MIC_N
BI_MIC_SHIELD
BI_MIC_P

GND

GND

TRUE
TRUE

TRUE

J9000 (LVDS CONN)

PP5V_S0
PP3V42_G3H

SPKRCONN_L_OUT_P
SPKRCONN_L_OUT_N
SPKRCONN_R_OUT_P
SPKRCONN_R_OUT_N
SPKRCONN_S_OUT_P
SPKRCONN_S_OUT_N

GND

PP3V3_SW_LCD
PP3V3_S0
PPVOUT_S0_LCDBKLT
LVDS_DDC_CLK
LVDS_DDC_DATA
LVDS_CONN_A_DATA_P<0>
LVDS_CONN_A_DATA_N<0>
LVDS_CONN_A_DATA_P<1>
LVDS_CONN_A_DATA_N<1>
LVDS_CONN_A_DATA_P<2>
LVDS_CONN_A_DATA_N<2>
LVDS_CONN_A_CLK_F_P
LVDS_CONN_A_CLK_F_N
LVDS_CONN_B_DATA_P<0>
LVDS_CONN_B_DATA_N<0>
LVDS_CONN_B_DATA_P<1>
LVDS_CONN_B_DATA_N<1>
LVDS_CONN_B_DATA_P<2>
LVDS_CONN_B_DATA_N<2>
LVDS_CONN_B_CLK_F_P
LVDS_CONN_B_CLK_F_N
LED_RETURN_1
LED_RETURN_2
LED_RETURN_3
LED_RETURN_4
LED_RETURN_5
LED_RETURN_6

GND

GND

PP5V_S0_HDD_FLT
SATA_HDD_R2D_P
SATA_HDD_R2D_N
SATA_HDD_D2R_C_N
SATA_HDD_D2R_C_P

GND

IR_RX_OUT
PP5V_S3_IR_R
SSD_OOBD2R_L
SSD_OOBR2D_L

KBDLED_ANODE
SMC_KDBLED_PRESENT_L

GND

TRUE

41 45

41 95

41 95

41 95

41 95

85

6 7 101

8 85 104

85 86

85 86

85 86 100

85 86 100

85 86 100

85 86 100

85 86 100

85 86 100

85 100

85 100

85 86 100

85 86 100

85 86 100

85 86 100

85 86 100

85 86 100

85 100

85 100

85 90

85 90

85 90

85 90

85 90

85 90

41

41 95

41 95

41 95

41 95

6 41 44

6 41

41

41

6 7

52

52

6 7

52

52

62 63 101

62 63

62 63 101

2 TPs

6 TPs

6 7

6 7

61 62 101

61 62 101

61 62 101

61 62 101

61 62 101

61 62 101

2 TP needed

4 TPs

8 TPs

54

54

4 TPs

3 TP needed

8 TPs

41

4 TPs

7 TPs

2 TPs

J3501 & J3502 (AIRPORT/BT/CAMERA CONN)

PCIE_AP_R2D_P

TRUE

I1053

PCIE_AP_R2D_N

TRUE

I1052

PCIE_CLK100M_AP_CONN_P

TRUE

I1054

PCIE_CLK100M_AP_CONN_N

TRUE

I1056

AP_CLKREQ_Q_L

TRUE

I1055

PCIE_WAKE_L

TRUE

I1058

WIFI_EVENT_L

TRUE

I1496

AP_RESET_CONN_L

TRUE

I1057

PP3V3_WLAN

TRUE

I1059

PP5V_S3_ALSCAMERA_F

TRUE

I1061

SMBUS_SMC_2_S3_SDA

TRUE

I1060

SMBUS_SMC_2_S3_SCL

TRUE

I1063

USB_CAMERA_CONN_P

TRUE

I1062

USB_CAMERA_CONN_N

TRUE

I1064

TRUE

TRUE

I1663

TRUE

I1664

TRUE

I1665

GND

PP3V3_S3RS4_BT_F
USB_BT_CONN_P
USB_BT_CONN_N

J6950 (BAT CONN)

SYS_DETECT_L

TRUE

I1510

J5800 (IPD FLEX CONN)

PP18V5_Z2

TRUE

I1659

PP3V3_S4

TRUE

I1660

PP5V_S5_CUMULUS

TRUE

I1509

Z2_HOST_INTN

TRUE

I1086

Z2_MOSI

TRUE

I1508

Z2_CS_L

TRUE

I1273

Z2_DEBUG3

TRUE

I1089

Z2_MISO

TRUE

I1088

Z2_BOOST_EN

TRUE

I1090

Z2_SCLK

TRUE

I1464

Z2_CLKIN

TRUE

I1098

Z2_KEY_ACT_L

TRUE

I1097

Z2_RESET

TRUE

I1095

PSOC_F_CS_L

TRUE

I1096

PICKB_L

TRUE

I1092

PSOC_MISO

TRUE

I1093

PSOC_MOSI

TRUE

I1094

PSOC_SCLK

TRUE

I1099

SMBUS_SMC_2_S3_SCL

TRUE

I1100

SMBUS_SMC_2_S3_SDA

TRUE

I1101

J6900 (DC POWER CONN)

TRUE

I1131

TRUE

I1132

TRUE

J6950 (MAIN BATT CONN)

TRUE

I1134

TRUE

I1136

TRUE

I1135

TRUE

I1669

TRUE

I1140

I1142

I1141

I1143

I1673

GND

TRUE

ADAPTER_SENSE
PP18V5_DCIN_FUSE

GND

PPVBAT_G3H_CONN
SMBUS_SMC_5_G3_SCL
SMBUS_SMC_5_G3_SDA
SYS_DETECT_L

GND

J6955 (BAT LED CONN)

PP3V42_G3H

TRUE

SMBUS_SMC_5_G3_SDA

TRUE

SMBUS_SMC_5_G3_SCL

TRUE

SMC_BIL_BUTTON_L

TRUE

SMC_LID_R

TRUE

TRUE

GND

32 96

32 96

32 101

32 101

32

17 24 32

32 45 46

32

32 46

32

6 45 48 99

6 45 48 99

32 95

32 95

2 TPs needed

FUNC_TEST

BKLT_EN

38

38

38

38

38

38

38

38

38

38

93
6 9
17

9
17
93

93
17
9

93
17
9 17 93

9 17 93

9 17 93

I720

I722

I724

I723

I725

I726

I727

I729

I728

I730

I732

I731

I734

I1668

I737

I739

I738

I740

I741

I742

I743

I744

I751

I752

I760

I756

I1292

I1288

I1481

I1483

I1486

I1485

I1488

I1487

I1489

I1491

I1490

I1492

I1563

I1562

I1564

I1566

I1565

I1567

I1569

I1568

I1570

I1571

I1572

I1573

I1574

I1575

I1576

I1577

I1578

I1579

I1580

I1581

I1583

I1582

I1584

I1585

I1587

I1588

I1589

I1586

I1590

I1833

I1598

I1600

I1601

I1602

I1599

I1603

I1605

I1604

I1606

I1607

I1631

I1630

I1624

I1623

I1625

I1626

I1627

I1629

TRUE

ISSP_SCLK_P1_1

TRUE

ISSP_SDATA_P1_0

TRUE

LCD_BKLT_PWM

TRUE

LPCPLUS_GPIO

TRUE

LPCPLUS_RESET_L

TRUE

LPC_AD<0..3>

TRUE

LPC_CLK33M_LPCPLUS

TRUE

LPC_FRAME_L

TRUE

LPC_PWRDWN_L

TRUE

LPC_SERIRQ

TRUE

PM_CLKRUN_L

TRUE

PM_SYSRST_L

TRUE

SMC_ONOFF_L

TRUE

SMC_RESET_L

TRUE

SMC_RX_L

TRUE

SMC_TCK

TRUE

SMC_TDI

TRUE

SMC_TDO

TRUE

SMC_TMS

TRUE

SMC_ROMBOOT

TRUE

SMC_TX_L

TRUE

SPIROM_USE_MLB

TRUE

SPI_ALT_CLK

TRUE

SPI_ALT_CS_L

TRUE

SPI_ALT_MISO

TRUE

SPI_ALT_MOSI

TRUE

SYS_LED_ANODE_R

TRUE

NO_TEST=TRUE

TBT_R2D_C_P<1..0>

TRUE

TBT_R2D_C_N<1..0>

TRUE

TBTDPA_ML_P<3..0>

TRUE

TBTDPA_ML_N<3..0>

TRUE

DP_TBTSNK0_AUXCH_C_P

TRUE

DP_TBTSNK0_AUXCH_C_N

TRUE

DP_TBTSNK0_AUXCH_P

TRUE

DP_TBTSNK0_AUXCH_N

TRUE

DP_TBTSNK0_ML_C_P<3..0>

TRUE

DP_TBTSNK0_ML_C_N<3..0>

TRUE

DP_TBTSNK0_ML_P<3..0>

TRUE

DP_TBTSNK0_ML_N<3..0>

TRUE

DP_TBTSNK1_AUXCH_C_P

TRUE

DP_TBTSNK1_AUXCH_C_N

TRUE

DP_TBTSNK1_AUXCH_P

TRUE

DP_TBTSNK1_AUXCH_N

TRUE

DP_TBTSNK1_ML_C_P<3..0>

TRUE

DP_TBTSNK1_ML_C_N<3..0>

TRUE

DP_TBTSNK1_ML_P<3..0>

TRUE

DP_TBTSNK1_ML_N<3..0>

TRUE

TP_DP_TBTSRC_AUXCH_CN

TRUE

TP_DP_TBTSRC_AUXCH_CP

TRUE

TP_DP_TBTSRC_ML_CP<3..0>

TRUE

TP_DP_TBTSRC_ML_CN<3..0>

TRUE

DP_SDRVA_ML_C_P<0>

TRUE

DP_SDRVA_ML_C_N<0>

TRUE

DP_SDRVA_ML_C_P<2>

TRUE

DP_SDRVA_ML_C_N<2>

TRUE

DP_SDRVA_ML_P<0>

TRUE

DP_SDRVA_ML_N<0>

TRUE

DP_SDRVA_ML_P<2>

TRUE

DP_SDRVA_ML_N<2>

TRUE

TP_TBT_PCIE_RESET0_L

TRUE

TP_TBT_PCIE_RESET1_L

TRUE

TP_TBT_PCIE_RESET2_L

TRUE

TP_TBT_PCIE_RESET3_L

TRUE

PEG_D2R_C_P<7..0>

TRUE

PEG_D2R_C_N<7..0>

TRUE

PEG_R2D_P<7..0>

TRUE

PEG_R2D_N<7..0>

TRUE

TP_FW643_VAUX_ENABLE

TRUE

TP_FW643_VBUF

TRUE

TP_FW643_TCK

TRUE

TP_FW643_TDO

TRUE

TP_FW643_TMS

TRUE

TP_SMC_P10

TRUE

TP_P7_7

TRUE

TP_PSOC_SCL

TRUE

TP_PSOC_SDA

TRUE

TP_SMC_P24

TRUE

DC_TEST_BH1_BG2

TRUE

DC_TEST_BH3_BJ2

TRUE

TP_USB_HUB1_OCS1

TRUE

TP_USB_HUB1_PRTPWR1

TRUE

TP_USB_HUB2_OCS1

TRUE

TP_USB_HUB2_PRTPWR1

TRUE

TP_DC_TEST_A62

TRUE

TP_DC_TEST_D65

TRUETRUE

8

8

89 90

19 47

24 47

16 45 47 89 96

24 47 96

16 45 47 89 96

17 45 47

16 45 47

17 45 47

17 24 45

45 46 53

45 46 47 65

45 46 47

45 46 47

45 46 47

45 46 47

45 46 47

46 47

45 46 47

19 47 56

47

47

47

47

41

6 33

6 33

6 33

6 33

6 33

33 81 98

33 81 98

33 98 7

33 98

33 81 98

33 81 98 7

33 98

33 98

33 81 98

33 81 98

33 98

33 98

33 81 98

33 81 98

33 98

33 98

6 33

6 33

6 33

6 33

87 98

87 98

87 98

87 98

87 98

87 98

87 98

87 98

6 33

6 33

6 33

6 33

75 93

75 93

75 92 93

75 92 93

38

38

38

38

38

53

53

53

12

12

12

12 9

6 33

TP_DP_TBTSRC_AUXCH_CN
TP_TBT_PCIE_RESET0_L
TP_TBT_PCIE_RESET1_L
TP_TBT_PCIE_RESET2_L

6 7

6 7

53

53

53

53

53

53

53

53

53

53

53

53

53

53

53

53

53

53

53

53

53

53

53

53

53

53

53

6 41

6 64

6 41 44

41 46

17 26 45
74

7

7

7

7

7

7

7

7

6 7 101

7

7 101

45 46

6 7

6 7

7

7

7

7

7

7

7

ICT Test Points

CPU NO_TESTs

NO_TEST

TP_CPU_RSVD<65..62>

TP_CPU_RSVD<58..45>

TP_CPU_RSVD<43..32>

TP_CPU_RSVD<27..26>

TP_CPU_RSVD<24..15>

TP_CPU_RSVD<2..1>

TP_CPU_RSVD_NCTF<8..5>

NC NO_TESTs

NO_TEST

TP_CRT_IG_BLUE

17

TP_CRT_IG_GREEN

17

TP_CRT_IG_RED

17

TP_CRT_IG_DDC_CLK

17

TP_CRT_IG_DDC_DATA

17

TP_CRT_IG_HSYNC

17

TP_CRT_IG_VSYNC

17

TP_LVDS_IG_CTRL_CLK

17

TP_LVDS_IG_CTRL_DATA

17

TP_PCH_LVDS_VBG

17

TP_HDA_SDIN1 NC_HDA_SDIN1

16

TP_HDA_SDIN2

16

TP_HDA_SDIN3

16

TP_TBT_PCIE_RESET3_L

TP_TBT_MONDC0

33

TP_TBT_MONDC1

33

TP_TBT_MONOBSP

33

TP_TBT_MONOBSN

33

TP_DP_TBTSRC_ML_CP<0..3>

6 33

TP_DP_TBTSRC_ML_CN<0..3>

6 33

TP_PCI_PME_L

18

TP_PCI_CLK33M_OUT3

18

TP_PCIE_CLK100M_PE4N

16

TP_PCIE_CLK100M_PE4P NC_PCIE_CLK100M_PE4P

16

TP_PCIE_CLK100M_PE5N

16

TP_PCIE_CLK100M_PE5P

16

TP_PCIE_CLK100M_PE6N NC_PCIE_CLK100M_PE6N
TP_PCIE_CLK100M_PE6P
TP_PCIE_CLK100M_PE7N
TP_PCIE_CLK100M_PE7P

TP_PSOC_P1_3

53

TP_SATA_B_D2RN
TP_SATA_B_D2RP
TP_SATA_B_R2D_CN
TP_SATA_B_R2D_CP
TP_SATA_D_D2RN

16

TP_SATA_D_D2RP

16

TP_SATA_D_R2D_CN

16

TP_SATA_D_R2D_CP

16

TP_SATA_E_D2RN

16

TP_SATA_E_D2RP

16

TP_SATA_E_R2D_CN

16

TP_SATA_E_R2D_CP

16

TP_SATA_F_D2RN

16

TP_SATA_F_D2RP

16

TP_SATA_F_R2D_CN

16

TP_SATA_F_R2D_CP

16

NC_LPC_DREQ0_L

MAKE_BASE=TRUE

16

16

16

TP_PCIE_CLK100M_PEBN

16

TP_PCIE_CLK100M_PEBP

16

TRUE

I1632

TRUE

I1634

TRUE

I1633

TRUE

I1636

TRUE

I1635

TRUE

I1637

TRUE

I1638

TRUE

I1639

TRUE

I1641

TRUE

I1642

TRUE

I1644

I1643

I1645

TP_SMC_P41

TP_CLINK_CLK
TP_CLINK_DATA
TP_CLINK_RESET_L

NO_TEST

TP_AUD_GPIO_2
TP_AUD_GPIO_1
TP_AUD_LO1_L_N
TP_AUD_LO1_L_P
TP_BKL_FAULT

TP_SPI_DESCRIPTOR_OVERRIDE_L

TP_XDPPCH_HOOK2
TP_XDPPCH_HOOK3
TP_GMUX_PL6B

CPUIMVP_BOOT1
CPUIMVP_BOOT2

CPUIMVP_UGATE2

TRUE

TP_1V05_S0_PCH_VCCAPLLEXP

TRUE

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE

TRUE

MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

PCH ALIASES

TRUE
MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE
TRUE

MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

NC_TP_CPU_RSVD<65..62>

TRUE

MAKE_BASE=TRUE

NC_TP_CPU_RSVD<58..45>

TRUE

MAKE_BASE=TRUE

NC_TP_CPU_RSVD<43..32>

TRUE

MAKE_BASE=TRUE

NC_TP_CPU_RSVD<27..26>

TRUE

MAKE_BASE=TRUE

NC_TP_CPU_RSVD<24..15>

TRUE

MAKE_BASE=TRUE

NC_TP_CPU_RSVD<2..1>

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_CRT_IG_BLUE
NC_CRT_IG_GREEN
NC_CRT_IG_RED

NC_CRT_IG_DDC_CLK
NC_CRT_IG_DDC_DATA

NC_CRT_IG_HSYNC
NC_CRT_IG_VSYNC

NC_LVDS_IG_CTRL_CLK

NC_LVDS_IG_CTRL_DATA

NC_PCH_LVDS_VBG

NC_HDA_SDIN2
NC_HDA_SDIN3

TP_DP_TBTSRC_AUXCH_CPTP_DP_TBTSRC_AUXCH_CP
TP_DP_TBTSRC_AUXCH_CN

NC_TBT_PCIE_RESET0_L
NC_TBT_PCIE_RESET1_L
NC_TBT_PCIE_RESET2_L
NC_TBT_PCIE_RESET3_L

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

NC_DP_TBTSRC_ML_CP<0..3>

TRUE
MAKE_BASE=TRUE

NC_DP_TBTSRC_ML_CN<0..3>

TRUE
MAKE_BASE=TRUE

90

23

23

89

6 69 70

6 69 70

6 69 70

20

NC_PCI_PME_L
NC_PCI_CLK33M_OUT3

NC_PCIE_CLK100M_PE4N

NC_PCIE_CLK100M_PE5N
NC_PCIE_CLK100M_PE5P

NC_PCIE_CLK100M_PE6P
NC_PCIE_CLK100M_PE7N
NC_PCIE_CLK100M_PE7P
NC_PSOC_P1_3
NC_SATA_B_D2RN
NC_SATA_B_D2RP
NC_SATA_B_R2D_CN
NC_SATA_B_R2D_CP
NC_SATA_D_D2RN
NC_SATA_D_D2RP
NC_SATA_D_R2D_CN
NC_SATA_D_R2D_CP
NC_SATA_E_D2RN
NC_SATA_E_D2RP
NC_SATA_E_R2D_CN
NC_SATA_E_R2D_CP
NC_SATA_F_D2RN
NC_SATA_F_D2RP
NC_SATA_F_R2D_CN
NC_SATA_F_R2D_CP

NC_SMC_P41

TP_LPC_DREQ0_L

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PEBN
NC_PCIE_CLK100M_PEBP

NC_TP_CPU_RSVD_NCTF<8..5>

NC_TBT_MONDC0

NC_TBT_MONDC1

NC_TBT_MONOBSP

NC_CLINK_CLK
NC_CLINK_DATA
NC_CLINK_RESET_L

NO_TEST

TRUE

I1297

TRUE

I761

TRUE

I762

TRUE

I763

TRUE

I764

TRUE

I765

TRUE

I767

TRUE

I766

TRUE

I769

TRUE

I768

TRUE

I770

TRUE

I772

TRUE

I771

TRUE

I774

TP_FW643_AVREG

38

TP_FW643_TDI

38

TP_DP_IG_C_HPD
TP_DP_IG_C_CTRL_CLK
TP_DP_IG_C_CTRL_DATA
TP_DP_IG_C_MLP<3..0>

17

TP_DP_IG_C_MLN<3..0>

17

TP_DP_IG_C_AUXP
TP_DP_IG_C_AUXN

TP_DP_IG_D_HPD

17

TP_DP_IG_D_CTRL_CLK

17

TP_DP_IG_D_CTRL_DATA

17

TP_DP_IG_D_MLP<3..0>

17

TP_DP_IG_D_MLN<3..0>

17

TP_DP_IG_D_AUXP

17

TP_DP_IG_D_AUXN

17

TP_SDVO_TVCLKINN

17

TP_SDVO_TVCLKINP

17

TP_SDVO_STALLN

17

6 33

TP_SDVO_STALLP

17

6 33

TP_SDVO_INTN

17

TP_SDVO_INTP

17

TP_GPU_BUFRST_L
TP_GPU_GSTATE<0>
TP_GPU_GSTATE<1>
TP_GPU_MIOA_D<9..0>
TP_GPU_MIOA_DENC_TBT_MONOBSN

TP_LVDS_EG_BKL_PWM
TP_LVDS_IG_B_CLKN

8

TP_LVDS_IG_B_CLKP

8

TP_LVDS_IG_BKL_PWM

8

MEM_A_BA<2..0>

TRUE

I1513

I1514

I1515

I1516

I1517

I1518

I1519

I1520

I1529

I1530

I1536

I1535

I1534

I1533

I1537

I1539

I1558 I1559

I1540

I1541

I1542

I1543

I1544

I1545

I1560 I1561

I1436

I1437

I1438

I1439

I1440

I1441

I1442

I1443

16

MEM_A_CKE<1..0>

TRUE

MEM_A_CLK_N<1..0>

TRUE

MEM_A_CLK_P<1..0>

TRUE

MEM_A_CS_L<1..0>

TRUE

MEM_A_ODT<1..0>

TRUE

MEM_A_SA<1..0>

TRUE

MEM_A_DQ<63..0>

TRUE

MEM_A_DQS_N<7..0>

TRUE

MEM_A_DQS_P<7..0>

TRUE

FB_A0_DQ<31..0>

TRUE

FB_A0_A<8..0>

TRUE

FB_A0_ABI_L

TRUE

FB_A0_EDC<3..0>

TRUE

FB_A0_WCLK_N<1..0>

TRUE

FB_A0_WCLK_P<1..0>

TRUE

FB_A0_DBI_L<3..0>

TRUE

FB_A1_DQ<31..0>

TRUE

FB_A1_A<8..0>

TRUE

FB_A1_ABI_L

TRUE

FB_A1_EDC<3..0>

TRUE

FB_A1_WCLK_N<1..0>

TRUE

FB_A1_WCLK_P<1..0>

TRUE

FB_A1_DBI_L<3..0>

TRUE

MEM_A_A<15..0>

TRUE

MEM_A_CAS_L

TRUE

MEM_A_RAS_L

TRUE

MEM_A_WE_L

TRUE

MEM_B_A<15..0>

TRUE

MEM_B_CAS_L

TRUE

MEM_B_RAS_L

TRUE

MEM_B_WE_L

TRUE

SYNC_MASTER=K18_MLB

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

NC NO_TESTs

NC_SMC_FAN_3_TACH
NC_SMC_FAN_3_CTL
NC_SMC_FAN_2_TACH
NC_SMC_FAN_2_CTL
NC_FW2_TPBP
NC_FW2_TPBN
NC_FW2_TPBIAS
NC_FW2_TPAP
NC_FW2_TPAN
NC_FW0_TPBP
NC_FW0_TPBN
NC_FW0_TPAP
NC_ESTARLDO_EN
NC_ALS_GAIN

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_DP_IG_C_HPD

TRUE
MAKE_BASE=TRUE

NC_DP_IG_C_CTRL_CLK

TRUE
MAKE_BASE=TRUE

NC_DP_IG_C_CTRL_DATA

TRUE
MAKE_BASE=TRUE

NC_DP_IG_C_MLP<3..0>

TRUE
MAKE_BASE=TRUE

NC_DP_IG_C_MLN<3..0>

TRUE
MAKE_BASE=TRUE

NC_DP_IG_C_AUXP

TRUE
MAKE_BASE=TRUE

NC_DP_IG_C_AUXN

TRUE
MAKE_BASE=TRUE

NC_DP_IG_D_HPD

TRUE
MAKE_BASE=TRUE

NC_DP_IG_D_CTRL_CLK

TRUE
MAKE_BASE=TRUE

NC_DP_IG_D_CTRL_DATA

TRUE
MAKE_BASE=TRUE

NC_DP_IG_D_MLP<3..0>

TRUE
MAKE_BASE=TRUE

NC_DP_IG_D_MLN<3..0>

TRUE
MAKE_BASE=TRUE

NC_DP_IG_D_AUXP

TRUE
MAKE_BASE=TRUE

NC_DP_IG_D_AUXN

TRUE
MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

11 27 94

I1524

TRUE

11 27 94

I1523

TRUE

11 27 94

I1522

TRUE

11 27 94

I1521

TRUE

11 27 94

I1525

TRUE

11 27 94

I1526

TRUE

27

I1527

TRUE

11 28 94

I1528

TRUE

11 28 94

I1531

TRUE

11 28 94

I1532

77 79 100

77 79 100

77 79 100

77 79 100

77 79 100

77 79 100

77 79 100

77 79 100

77 79 100

77 79 100

77 79 100

77 79 100

77 79 100

11 27 94

11 27 94

11 27 94

11 27 94

11 29 94

11 29 94

11 29 94

11 29 94

TRUE

I1546

TRUE

I1547

TRUE

I1548

TRUE

I1549

TRUE

I1550

TRUE

I1551

TRUE

TRUE

I1552

TRUE

I1554

TRUE

I1553

TRUE

I1555

TRUE

I1557

TRUE

I1556

TRUE

Functional / ICT Test

Apple Inc.

R

6 3

12

40

40

40

40

40

40

40

40

NC_FW643_AVREG
NC_FW643_TDI

NC_SDVO_TVCLKINN
NC_SDVO_TVCLKINP

NC_SDVO_STALLN
NC_SDVO_STALLP

NC_SDVO_INTN
NC_SDVO_INTP

NC_GPU_BUFRST_L
NC_GPU_GSTATE<0>
NC_GPU_GSTATE<1>
NC_GPU_MIOA_D<9..0>
NC_GPU_MIOA_DE

NC_LVDS_EG_BKL_PWM
NC_LVDS_IG_B_CLKN
NC_LVDS_IG_B_CLKP
NC_LVDS_IG_BKL_PWM

MEM_B_BA<2..0>
MEM_B_CKE<1..0>
MEM_B_CLK_N<1..0>
MEM_B_CLK_P<1..0>
MEM_B_CS_L<1..0>
MEM_B_ODT<1..0>
MEM_B_SA<1..0>
MEM_B_DQ<63..0>
MEM_B_DQS_N<7..0>
MEM_B_DQS_P<7..0>

FB_B0_DQ<31..0>
FB_B0_A<8..0>
FB_B0_ABI_L
FB_B0_EDC<3..0>
FB_B0_WCLK_N<1..0>
FB_B0_WCLK_P<1..0>
FB_B0_DBI_L<3..0>
FB_B1_DQ<31..0>
FB_B1_A<8..0>
FB_B1_ABI_L
FB_B1_EDC<3..0>
FB_B1_WCLK_N<1..0>
FB_B1_WCLK_P<1..0>
FB_B1_DBI_L<3..0>

SYNC_DATE=04/27/2010

DRAWING NUMBER

051-9585

REVISION

BRANCH

PAGE

7 OF 132

SHEET

6 OF 105

124578

3.0.0

11 29 94

11 29 94

11 29 94

11 29 94

11 29 94

11 29 94

29

11 28 94

11 28 94

11 28 94

77 80 100

77 80 100

77 80 100

77 80 100

77 80 100

77 80 100

77 80 100

77 80 100

77 80 100

77 80 100

77 80 100 77 79 100

77 80 100

77 80 100

77 80 100

SIZE

NO_TEST=TRUE

I1693

I1694

I1695

I1696

I1697

I1699

I1698

I1700

I1702

I1701

I1703

I1704

D

I1705

I1707

I1706

I1708

I1710

I1709

I1711

I1713

I1712

I1714

I1716

I1715

I1717

I1718

I1719

I1720

I1721

I1722

I1723

I1724

I1725

I1726

I1727

I1728

I1730

I1729

C

I1731

I1732

I1734

I1735

I1736

I1733

I1737

I1779

I1785

I1787

I1786

I1789

I1788

I1784

I1782

I1783

I1781

I1780

I1790

I1793

I1792

I1794

I1795

I1796

I1797

I1798

B

I1800

I1799

I1801

I1803

I1802

I1804

I1813

I1814

I1815

I1816

I1818

I1817

I1819

I1820

I1821

I1822

TRUE
TRUE

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

TRUE
TRUE

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

TRUE
TRUE

USB3_EXTA_RX_F_N

TRUE

USB3_EXTA_RX_F_P

TRUE
TRUE
TRUE

USB3_EXTA_TX_F_N

TRUE
TRUE
TRUE

USB3_EXTA_TX_F_P

TRUE

CHGR_ICOMP_RC
CHGR_LGATE
CHGR_PHASE
CHGR_UGATE
CHGR_VCOMP
CPU_VCCSASENSE_DIV
CPUIMVP_AXG1_SNUB
CPUIMVP_AXG2_SNUB
CPUIMVP_BOOT1
CPUIMVP_BOOT1_RC
CPUIMVP_BOOT1G

CPUIMVP_BOOT1G_R
CPUIMVP_LGATE1
CPUIMVP_LGATE1G
CPUIMVP_LGATE2
CPUIMVP_LGATE2G
CPUIMVP_LGATE3
CPUIMVP_PH1_SNUB
CPUIMVP_PH2_SNUB
CPUIMVP_PH3_SNUB
CPUIMVP_PHASE1
CPUIMVP_PHASE1G
CPUIMVP_PHASE2
CPUIMVP_PHASE2G

CPUIMVP_PHASE3

CPUIMVP_SKIP

CPUIMVP_SLEW

CPUIMVP_TONA

CPUIMVP_TONB

CPUIMVP_VSWG1
CPUIMVP_VSWG2
CPUVCCIOS0_BOOT_RC
CPUVCCIOS0_DRVH
CPUVCCIOS0_DRVL
CPUVCCIOS0_FB

CPUVCCIOS0_LL

CPUVCCIOS0_OCSET

CPUVCCIOS0_RTN

CPUVCCIOS0_VBST
DC_TEST_B3_C2
DDRREG_DRVH
DDRREG_DRVL
DDRREG_FB
DDRREG_LL
P3V3S5_VBST
P3V3S5_VFB2
P3V42G3H_SW
P5VS3_CSP1_R
P5VS3_DRVH
P5VS3_DRVL
P5VS3_LL
P5VS3_SNUBR
P5VS3_TG
P5VS3_VBST
P5VS3_VFB1

PCHVCCIOS0_BOOT_RC

PCHVCCIOS0_DRVH

PCHVCCIOS0_DRVL

PCHVCCIOS0_FB

PCHVCCIOS0_LL

PCHVCCIOS0_OCSET

PCHVCCIOS0_VBST
PPVCORE_S0_CPU_PH1_L
PPVCORE_S0_CPU_PH2_L
PPVCORE_S0_CPU_PH3_L
VCCSAS0_B00T_RC
VCCSAS0_DRVL
VCCSAS0_LL
VCCSAS0_VBST

USB3_EXTA_RX_N
USB3_EXTA_RX_P

USB3_EXTA_TX_N
USB3_EXTA_TX_C_N

USB3_EXTA_TX_P
USB3_EXTA_TX_C_P

I1746

I1749

I1748

I1750

I1751

I1752

I1753

I1754

I1755

I1756

I1757

I1759

I1758

I1760

I1762

I1761

I1764

I1763

I1765

I1767

I1766

I1768

I1770

I1769

I1772

I1771

I1773

I1775

I1774

I1776

I1777

I1778

I1805

I1806

I1807

I1809

I1808

I1810

I1812

I1811

I1823

I1825

I1824

I1826

I1827

I1828

I1830

I1829

I1831

I1832

I1743

I1742

I1744

I1745

I1739

I1738

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

CPUIMVP_UGATE1

TRUE

CPUIMVP_UGATE1G

TRUE

CPUIMVP_UGATE2

TRUE

CPUIMVP_UGATE2G

TRUE

CPUIMVP_UGATE3

TRUE

DDRREG_TRIP

TRUE

GFXIMVP_LGATE

TRUE

GFXIMVP_LL_RC

TRUE

GFXIMVP_PHASE

TRUE

GFXIMVP_PHASE_L

TRUE

GFXIMVP_UGATE

TRUE

GFXIMVP_UGATE_R

TRUE

GFXIMVP_VBST

TRUE

GFXIMVP_VBST_R

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

P1V05_GPU_DRVL

TRUE

P1V05_GPU_DRVH

TRUE

P1V05_GPU_LL

TRUE

P1V05_GPU_VBST

TRUE

P1V05_GPU_BOOT_RC

TRUE

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

TRUE
TRUE
TRUE
TRUE
TRUE

TRUE

TRUE
TRUE

USB3_EXTB_RX_F_N

TRUE

USB3_EXTB_RX_F_P

TRUE

USB3_EXTB_TX_N

TRUE

USB3_EXTB_TX_C_N

TRUE

USB3_EXTB_TX_F_N

TRUE

USB3_EXTB_TX_P

TRUE

USB3_EXTB_TX_C_P

TRUE

USB3_EXTB_TX_F_P

TRUE

CPUIMVP_BOOT2
CPUIMVP_BOOT2_RC
CPUIMVP_BOOT2G
CPUIMVP_BOOT2G_RC
CPUIMVP_BOOT3
CPUIMVP_BOOT3_RC

GPUFB_BOOT_RC
GPUFB_DRVH
GPUFB_DRVL
GPUFB_LL
GPUFB_VBST

P1V8S0_FB

P1V8S0_SW
P3V3S5_CSP2_R
P3V3S5_DRVH
P3V3S5_DRVL
P3V3S5_LL
P3V3S5_SNUBR
P3V3S5_TG

P5V5G3H_BOOST
P5V5G3H_SW

DMI_S2N_N<3>

DMI_S2N_P<3>

DMI_S2N_N<1..0>

DMI_S2N_P<1..0>

DMI_N2S_N<3..1>

DMI_N2S_P<3..1>

USB3_EXTB_RX_N
USB3_EXTB_RX_P

CHGR_BOOT

TRUE

A

D

www.vinafix.vn

D

C

B

A

=PPBUS_G3H

64 65

G3H Rails

=PPVIN_S5_HS_COMPUTING_ISNS

50

=PPVIN_S5_HS_GPU_ISNS

50

=PPVIN_S5_HS_OTHER_ISNS

50

=PP18V5_DCIN_CONN

64

=PP3V42_G3H_REG

64

For PCH RTC Power

=PPVRTC_G3_OUT

24

5V Rails

=PP5V_S5_LDO

67

=PP5V_SUS_FET

73

=PP5V_S3_REG

67

=PP5V_S0_FET

73

=PP5V_S0_ISNS

103

3.3V Rails

=PP3V3_S4_FET

73

=PP3V3_S4_SD_HPD

30

=PP3V3_S4_BT

32

=PP3V3_SUS_FET

73

8 7 6 5 4 3

8

49

72

56

20 22

35

6

103 104

53 54

73

49

VOLTAGE=3.3V

=PP3V3_S5_REG

67

=PP3V3_S3_FET

=PP3V3_S3_ISNS

7

=PP3V3_S0_FET

73

T29 Rails

=PP3V3_TBT_FET

35

=PP1V05_TBT_FET

35

=PP15V_TBT_REG

8

35

PP3V3_S5

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

=PP3V3_GPU_P3V3GPUFET
=PP3V3_S0_P3V3S0FET
=PP3V3_S3_P3V3S3FET

=PP3V3_S4_P3V3S4FET

=PP3V3_S5_SYSCLK
=PP3V3_S5_LCD
=PP3V3_FW_P3V3FWFET
=PP3V3_S5_P1V2P1V8
=PP3V3_S5_PCH
=PP3V3_S5_PCHPWRGD
=PP3V3_S5_PCH_GPIO
=PP3V3_S5_CPU_VCCDDR
=PP3V3_S5_MEMVDDSEL

=PP3V3_S5_PCH_VCCDSW
=PP3V3_S5_VMON
=PP3V3_S5_XDP
=PP3V3_S5_P3V3SUSFET

=PP3V3_S5_PWRCTL
=PP3V3_S5_P1V5S0
=PP3V3_S5_SMCBATLOW

=PP3V3_S4_TBTAPWRSW

PP3V3_S3_FET

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM

=PP3V3_S3_ISNS_R

PP3V3_S3

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM

=PP3V3_S3_BT
=PP3V3_S3_GMUX
=PP3V3_S3_MEMRESET
=PP3V3_S3_P3V3ENETFET
=PP3V3_S3_SMBUS_SMC_2_S3
=PP3V3_S3_SMBUS_SMC_3
=PP3V3_S3_SMS

=PP3V3_S3_USB_HUB

=PP3V3_S3_USB_RESET
=PP3V3_S3_VREFMRGN
=PP3V3_S3_WLAN
=PP3V3_S3_ISNS
=PP3V3_S3_PCH_GPIO
=PP3V3_S3_USBMUX
=PP3V3_S3_SDBUF

PP3V3_S0

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.075 mm

=PP3V3_S0_XDP
=PP3V3_S0_ENETPHY
=PP3V3_S0_AUDIO
=PP3V3_S0_BKL_VDDIO
=PP3V3_S0_DPSDRVA
=PP3V3_S0_HS_ISNS
=PP3V3_S0_CPUTHMSNS
=PP3V3_S0_DDC_LCD
=PP3V3_S0_ISNS
=PP3V3_S0_TBTPWRCTL
=PP3V3_S0_DPMUX
=PP3V3_S0_FAN_LT
=PP3V3_S0_FAN_RT
=PP3V3_S0_FWPWRCTL
=PP3V3_S0_FWLATEVG
=PP3V3_S0_CPU_VCCIO_SEL
=PP3V3_S0_GMUX

=PP3V3_S0_P3V3TBTFET
=PP3V3_S0_GPUTHMSNS
=PP3V3_S0_LVDSDDCMUX
=PP3V3_S0_ODD
=PP3V3_S0_PCH
=PP3V3_S0_PCH_GPIO
=PP3V3_S0_PCH_VCC3_3_CLK
=PP3V3_S0_PCH_VCC3_3_GPIO
=PP3V3_S0_PCH_VCC3_3_HVCMOS
=PP3V3_S0_PCH_VCC3_3_PCI
=PP3V3_S0_PCH_VCC3_3_SATA
=PP3V3_S0_PCH_VCCADAC
=PP3V3_S0_PCH_VCCA_LVDS
=PP3V3_S0_PWRCTL
=PP3V3_S0_RSTBUF
=PP3V3_S0_SB_PM
=PP3V3_S0_SDCARD
=PP3V3_S0_SMBUS_PCH
=PP3V3_S0_SMBUS_SMC_0_S0
=PP3V3_S0_SMBUS_SMC_1_S0
=PP3V3_S0_SMC

=PP3V3_S0_TPAD
=PP3V3_S0_VMON

=PPSPD_S0_MEM_A
=PPSPD_S0_MEM_B

=PP3V3_S0_HDD

=PP3V3_S0_P1V8GPUFET
=PP3V3_S0_IMVPISNS
=PP3V3_S0_T29I2C
=PP3V3_S0_TBT_HPD_GPU

PP3V3_TBT

MIN_LINE_WIDTH=0.4 MM

=PP3V3_T29_PCH_GPIO

=PPVDDIO_T29_CLK
=PP3V3_TBT_RTR
=PP3V3_T29_JTAG

PP1V05_TBT

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM

=PP1V05_TBT_RTR_R

PP15V_TBT

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM

=PPHV_SW_TBTAPWRSW

VOLTAGE=3.3V

VOLTAGE=3.3V
MAKE_BASE=TRUE

VOLTAGE=3.3V
MAKE_BASE=TRUE

VOLTAGE=3.3V
MAKE_BASE=TRUE

VOLTAGE=3.3V
MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM
MAKE_BASE=TRUE

VOLTAGE=1.05V
MAKE_BASE=TRUE

VOLTAGE=15V
MAKE_BASE=TRUE

16 19

24

33 34 35

89

6

101

73

73

73

73

24

85

39

72

17

92

19

26

20 22

74

23

73

74

72

46

88

104

6

89

26

74

48

48

55

25

25

31

32

7

49

103 104

18 24

25

24

6

101

23

36

57 62 63

90

87

51

85

49 50

103 104

35

86

52

52

39

39 40

12

86 89

35

51

86

41

16 22

16 17 18 19 30

22

20 22

20 22

20 22

20 22

22

20

74 92

24

24 92

30

48

48

48

41

54

74

27

29

41

73

50

48

35

104

88

=PP1V8_S0_REG

72

2A max supply

=PP1V8_S0_CPU_VCCPLL_R

12 14

=PPDDR_S3_REG

68

=PP1V5_S3_ISNS

103

=PP1V5_S3RS0_FET

73

=PP1V5_S3_DDR_ISNS

49

=PP1V5_S0_REG

72

=PPVTT_S3_DDR_BUF

31 68

=PPVTT_S0_DDR_LDO

68

=PP1V2_S0_REG

72

=PP1V05_SUS_LDO

72

=PPCPUVCCIO_S0_REG

71

Backlight Rails

=PPBUS_SW_BKL

90

104

=PP3V3_ENET_FET

74

ENET Rails

=PP1V2_S3_ENET_PHY

72

TBT Rails

=PP1V05_TBT_RTR

34

104

I1658

PPVIN_SW_TBTBST

VOLTAGE=12.8V

1.8V/1.5V/1.2V/1.05V Rails

PP1V8_S0

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

=PP1V8_S0_GMUX
=PP1V8_S0_GPUFET
=PP1V8_S0_PCH_VCCTX_LVDS
=PP1V8_S0_PCH_VCC_DFTERM
=PP1V8_S0_CPU_VCCPLL

=PP1V8R1V5_S0_PCH_VCCVRM

=PPVDDIO_S0_SBCLK

PP1V8_S0_CPU_VCCPLL_R

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

PP1V5_S3_REG

MIN_LINE_WIDTH=0.8 MM
MIN_NECK_WIDTH=0.1 MM

=PP1V5_S3_ISNS_R
PP1V5_S3

MIN_LINE_WIDTH=0.8 MM
MIN_NECK_WIDTH=0.1 MM

=PP1V5_S3_DDR_ISNS_R
=PPVIN_S3_P1V5S3RS0_FET

PP1V5_S3RS0

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

=PP1V5_S3_CPU_VCCDDR

PP1V5_S3_DDR

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

=PP1V5_S3_MEMRESET
=PP1V5_S3_MEM_A
=PP1V5_S3_MEM_B
=PPVIN_S0_DDRREG_LDO
=PPDDR_S3_MEMVREF

PP1V5_S0

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.5V
MAKE_BASE=TRUE

=PP1V5_S0_RDRVR
=PP1V5_S0_AUDIO

=PP3V3R1V5_S0_PCH_VCCSUSHDA

=PP1V5_S0_VMON

PPVTTDDR_S3

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0.75V
MAKE_BASE=TRUE

PP0V75_S0_DDRVTT

MIN_LINE_WIDTH=2 mm
MIN_NECK_WIDTH=0.17 mm
VOLTAGE=0.75V
MAKE_BASE=TRUE

=PP0V75_S0_MEM_VTT_A
=PP0V75_S0_MEM_VTT_B
=PPVTT_S0_VTTCLAMP

PP1V2_S0

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.2V
MAKE_BASE=TRUE

=PP1V2_S0_GMUX

PP1V05_SUS

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE

=PP1V05_SUS_PCH_JTAG

PP1V05_S0

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

=PP1V05_S0_CPU_VCCIO

=PPVCCIO_S0_XDP
=PPVCCIO_S0_CPUIMVP
=PPVCCIO_S0_SMC
=PP1V05_S0_RMC
=PP1V05_S0_FWPWRCTL
=PP1V05_FW_P1V0FWFET
=PP1V05_S0_VMON
=PP1V05_S0_P1V05TBTFET
=PP1V05_S0_PCH_VCCIO_PLLPCIE
=PP1V05_S0_PCH_VCCADPLL
=PP1V05_S0_PCH_VCCIO
=PP1V05_S0_PCH_VCCIO_PCIE
=PP1V05_S0_PCH_VCCIO_SATA
=PP1V05_S0_PCH_VCCIO_CLK
=PP1V05_S0_PCH_VCCIO_USB
=PP1V05_S0_PCH_VCC_CORE
=PP1V05_S0_PCH_VCCASW
=PP1V05_S0_PCH_VCCIO_CLK
=PP1V05_S0_PCH_VCCDIFFCLK
=PP1V05_S0_PCH
=PP1V05_S0_PCH_VCCSSC
=PP1V05_S0_PCH_V_PROC_IO
=PP1V05_S0_PCH_VCCIO_PLLUSB
=PP1V05_S0_PCH_VCC_DMI
=PP1V05_S0_PCH_VCCIO_PLLFDI
=PP1V05_S0_PCH_VCCDMI_FDI

=PPPCHVCCIO_S0_REG

PPBUS_SW_BKL

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

PP3V3_ENET

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

=PP3V3_ENET_PHY
=PPVDDIO_ENET_CLK
=PP3V3_ENET_SYSCLK

PP1V2_ENET

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

=PP1V2_ENET_PHY

PP1V05_TBT_RTR

MIN_LINE_WIDTH=0.6 MM

35

MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE
VOLTAGE=12.8V

PPBUS_G3H

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

=PPBUS_S0_LCDBKLT
=PPBUS_S5_FWPWRSW
=PPVIN_S5_HS_OTHER_ISNS_R

=PPVIN_S5_HS_COMPUTING_ISNS_R

=PPVIN_S5_HS_GPU_ISNS_R
=PPVIN_SW_TBTBST
=PPBUS_S0_VSENSE

PPVIN_S5_HS_COMPUTING_ISNS

MIN_LINE_WIDTH=0.6 mm

=PPVIN_S0_CPUIMVP
=PPVIN_S3_DDRREG
=PPVIN_S0_CPUVCCIOS0
=PPVIN_S0_CPUAXG
=PPVIN_S0_VCCSAS0

=PPVIN_S0_PCHVCCIOS0

PPVIN_S5_HS_GPU_ISNS

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

=PPVIN_S0GPU_P1V5
=PPVIN_S0_GFXIMVP
=PPVIN_S0GPU_P1V05

PPVIN_S5_HS_OTHER_ISNS

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

=PPVIN_S5_P5VP3V3
PPDCIN_G3H

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM

=PPDCIN_S5_CHGR
=PPDCIN_S5_VSENSE
PP3V42_G3H

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM

=PP3V3_S5_LPCPLUS
=PP3V3_S5_SMC
=PP3V42_G3H_BIL
=PP3V42_G3H_CHGR
=PP3V42_G3H_ONEWIREPROT
=PP3V42_G3H_PWRCTL
=PP3V42_G3H_SMBUS_SMC_5
=PP3V42_G3H_SMCUSBMUX
=PP3V42_G3H_TPAD
=PPVIN_S5_SMCVREF
=PPVBAT_G3_SYSCLK
=PP3V42_G3H_AUDIO

PPVRTC_G3H

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM

=PPVRTC_G3_PCH

PP5V_S5

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

=PP5V_S5_P1V5S3RS0FET
=PP5V_S5_P5VSUSFET
=PP5V_S5_TPAD
=PP5V_S5_ISNS

PP5V_SUS

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

=PP5V_SUS_PCH

PP5V_S3

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm

=PP5V_S3_ALSCAMERA
=PP5V_S3_DDRREG

=PP5V_S5_DEBUG_ADC_AVDD
=PP5V_S5_DEBUG_ADC_DVDD

=PP5V_S3_AUDIO
=PP5V_S3_IR
=PP5V_S3_MEMRESET

=PP5V_S3_ODD

=PP5V_S3_P5VS0FET
=PP5V_S3_USB
=PP5V_S3_SYSLED

=PP5V_S3_P5VS0SW
=PP5V_S3_P3V3S0SW

=PP5V_S3_GFXIMVP

PP5V_S0

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM

=PP5V_S0_BKL
=PP5V_S0_CPUIMVP
=PP5V_S0_CPUVCCIOS0
=PP5V_S0_FAN_LT
=PP5V_S0_FAN_RT
=PP5V_S0_VCCSAS0
=PP5V_S0_VMON

=PP5V_S0_HDD
=PP5V_S0_KBDLED
=PP5V_S0_LPCPLUS

=PP5V_S0_PCH

=PP5V_S0GPU_P1V05
=PP5V_S0_AUDIO_XW
=PP5V_S0_RMC

=PP5V_S0GPU_P1V5

PP3V3_S4

MIN_LINE_WIDTH=0.6 MM

=PP3V3_S4_TPAD

=PP3V3_S4_SMC
PP3V3_SUS

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

=PP3V3_SUS_P1V05SUSLDO

=PP3V3_SUS_PCH_VCCSUS
=PP3V3_SUS_PCH_VCCSUS_GPIO
=PP3V3_SUS_PCH_GPIO
=PP3V3_SUS_PCH_VCCSUS_USB

=PP3V3_SUS_CNTRL
=PP3V3_SUS_SMC
=PP3V3_SUS_ROM

=PP3V3_SUS_PCH_VCC_SPI

MIN_NECK_WIDTH=0.25 mm

VOLTAGE=18.5V
MAKE_BASE=TRUE

VOLTAGE=3.42V
MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE
VOLTAGE=3.3V

VOLTAGE=12.8V
MAKE_BASE=TRUE

VOLTAGE=3.42V
MAKE_BASE=TRUE

VOLTAGE=5V
MAKE_BASE=TRUE

VOLTAGE=5V
MAKE_BASE=TRUE

VOLTAGE=5V
MAKE_BASE=TRUE

VOLTAGE=5V
MAKE_BASE=TRUE

VOLTAGE=12.8V

VOLTAGE=12.8V
MAKE_BASE=TRUE

VOLTAGE=12.8V
MAKE_BASE=TRUE

6

MAKE_BASE=TRUE

67

6

65

49

6

47

45 46 82

64

65 74

64

16 17 20

73

73

54

22

6

32

68

104

104

41 44

26

41

73

42

46

84

6

90

69 70

71

52

52

66

74

41

54

47

22 24

78

8

105

78

MAKE_BASE=TRUE

90

39

50

50

50

69 70

68

71

70

66

78

84

78

74

48

42

53

46

24

59

46

20 22

20 22

16 17 18 19

20 22

74

46

6 3

VOLTAGE=1.5V
MAKE_BASE=TRUE

VOLTAGE=1.8V
MAKE_BASE=TRUE

VOLTAGE=1.5V
MAKE_BASE=TRUE

VOLTAGE=1.5V
MAKE_BASE=TRUE

VOLTAGE=1.5V
MAKE_BASE=TRUE

VOLTAGE=1.5V
MAKE_BASE=TRUE

VOLTAGE=1.05V
MAKE_BASE=TRUE

VOLTAGE=3.3V
MAKE_BASE=TRUE

VOLTAGE=1.2V

MAKE_BASE=TRUE

VOLTAGE=1.05V
MAKE_BASE=TRUE

89

73

22

19 20 22

14

20

24

103

6

49

73

101

10 13 15 26

26

27

29

68

31

41

57

20 22 24

74

6

6

27

29

26

6

89

23

6

9

10 12 13 14

23

69

46

105

39

39

74

35

20

22

20 22

17

16 20 22

7

20 22

20 22

20 22

20 22

7

20 22

16 20 22

16 22

20 22

20 22

20

20 22

20

20

91

6

24 36 72

24

24

6

36

12

6

=PP3V3_S0GPU_FET

73

=PP3V3_S0GPU_ISNS

104

=PP1V8_GPU_FET

73

=PP1V5R1V35_GPU_REG

78

103

=PP1V05_S0GPU_REG

78

=PPVCORE_S0_GFX_REG

84

=PPVCORE_S0_CPU_REG

70

=PPVCORE_S0_AXG_REG

49 70

=PP1V5_S3_CPU_VCCDQ

12 15

=PP1V05_S0_CPU_VCCPQE

8

12 14

=PPVCCSA_S0_REG

49 66

=PPBUS_FW_FET

39

=PP3V3_FW_FET

39

=PP1V0_FW_FET_R

39

SYNC_MASTER=J31_MLB

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

"GPU" Rails

PP3V3_S0GPU_FET

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.10MM
VOLTAGE=3.3V
MAKE_BASE=TRUE

=PP3V3_S0GPU_ISNS_R
PP3V3_S0GPU

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.10MM
VOLTAGE=3.3V
MAKE_BASE=TRUE

=PP3V3_GPU_IFPX_PLLVDD
=PP3V3_GPU_LVDS_DDC
=PP3V3_S0_GFX3V3BIAS
=PP3V3_GPU_VDD33
=PP3V3_GPU_OSC

PP1V8_S0GPU

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.15 MM
VOLTAGE=1.8V
MAKE_BASE=TRUE

=PP1V8_GPU_IFPAB_IOVDD

PPGPUFB_S0

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

=PP1V35_GPU_FBVDDQ
=PP1V35_GPU_S0_FB

PP1V05_S0GPU

MIN_LINE_WIDTH=0.9 MM
MIN_NECK_WIDTH=0.2 MM

=PP1V05_GPU_IFPAB_PLLVDD

=PP1V05_GPU_IFPCD_IOVDD
=PP1V05_GPU_IFPEF_IOVDD
=PP1V05_GPU_PEX_IOVDD
=PP1V05_GPU_PEX_PLLVDD

PPVCORE_GPU

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

=PPVCORE_GPU
=PPVCORE_GPU_REG

Chipset "VCore" Rails

PPVCORE_S0_CPU

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM

=PPVCORE_S0_CPU

PPVCORE_S0_AXG

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

=PPVCORE_S0_CPU_VCCAXG

PP1V5_S3_CPU_VCCDQ

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_CPU_VCCPQE

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

PPVCCSA_S0_REG

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

=PPVCCSA_S0_CPU

FireWire Rails

PPVP_FW

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM

=PPVP_FW_PORT1
=PPVP_FW_PHY_CPS_FET

PP3V3_FW_FWPHY

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM

=PP3V3_FW_FWPHY

PP1V0_FW_FWPHY

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM

=PP1V0_FW_FWPHY

Power Aliases

Apple Inc.

R

VOLTAGE=1.5V
MAKE_BASE=TRUE

VOLTAGE=1.05V
MAKE_BASE=TRUE

VOLTAGE=1.0V
MAKE_BASE=TRUE

MAKE_BASE=TRUE
VOLTAGE=1.25V

MAKE_BASE=TRUE
VOLTAGE=1.05V

MAKE_BASE=TRUE
VOLTAGE=1.5V

VOLTAGE=1.05V
MAKE_BASE=TRUE

VOLTAGE=0.9V
MAKE_BASE=TRUE

VOLTAGE=12.8V
MAKE_BASE=TRUE

VOLTAGE=3.3V
MAKE_BASE=TRUE

VOLTAGE=1.0V
MAKE_BASE=TRUE

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

051-9585

104

81

86

84

75 81 82 83

81

76 79 80

77

6

81

81

81

77 83

81 83

6

76 83

49

6

12 14 49
105

12 13 15

12 15

6

40

40

6

38 39 40

6

38 39

SYNC_DATE=08/29/2011

3.0.0

8 OF 132
7 OF 105

SIZE

D

C

B

A

D

124578

www.vinafix.vn

D

SL-3.1X2.7-6CIR-NSP

C

B

A

8 7 6 5 4 3

Thermal Module Holes

1

1

1

Frame Holes

GND_BATT_CHGND

GND_CHASSIS_LVDS

GND_CHASSIS_FAN

GND_CHASSIS_SATA

GND_CHASSIS_BATTCONN

SH0930

SM

1

SH0931

SM

1

SH0902

SM

1

SH0903

SM

1

SH0904

SM

1

SH0936

SM

1

SH0910

SM

1

SH0912

SM

1

SH0901

SM

1

SH0914

SM

1

ZT0915

3R2P5

ZT0940

3R2P5

ZT0950

TH

ZT0960

3R2P5

ZT0990

3R2P5

ZT0984

ZT0987

ZT0980

1

1

1

1

1

STDOFF-4.5OD.98H-1.1-3.48-TH

STDOFF-4.5OD.98H-1.1-3.48-TH

STDOFF-4.5OD.98H-1.1-3.48-TH

Tall EMI pogo pins

POGO-2.0OD-3.5H-K86-K87

POGO-2.0OD-3.5H-K86-K87

NOSTUFF

POGO-2.0OD-3.5H-K86-K87

POGO-2.0OD-3.5H-K86-K87

POGO-2.0OD-3.5H-K86-K87

POGO-2.0OD-3.5H-K86-K87

Short (IO Row) EMI pogo pins

1.4DIA-SHORT-SILVER-K99

1.4DIA-SHORT-SILVER-K99

1.4DIA-SHORT-SILVER-K99

1.4DIA-SHORT-SILVER-K99

T29_A_BIAS

MAKE_BASE=TRUE

=TBT_A_BIAS

87

NOSTUFF

GND_CHASSIS_AUDIO_JACK

1

2

C9490

0.1UF

10%

6.3V
X5R
201

STDOFF-4.5OD.98H-1.1-3.48-TH

STDOFF-4.5OD.98H-1.1-3.48-TH

STDOFF-4.5OD.98H-1.1-3.48-TH

NOSTUFF

SH0932

POGO-2.0OD-3.5H-K86-K87

POGO-2.0OD-3.5H-K86-K87

POGO-2.0OD-3.5H-K86-K87

POGO-2.0OD-3.5H-K86-K87

POGO-2.0OD-3.5H-K86-K87

POGO-2.0OD-3.5H-K86-K87

1.4DIA-SHORT-SILVER-K99

1.4DIA-SHORT-SILVER-K99

1.4DIA-SHORT-SILVER-K99

1.4DIA-SHORT-SILVER-K99

R9490

51

1 2

5%

1/20W

MF

201

SM

1

SH0933

SM

1

SH0900

SM

1

SH0916

SM

1

SH0937

SM

1

SH0938

SM

1

SH0911

SM

1

SH0913

SM

1

SH0917

SM

1

SH0918

SM

1

62

DPLL_REF_CLKP

93

MAKE_BASE=TRUE

T29_A_BIAS_R

VOLTAGE=3.3V

PLACE_NEAR=C9490.1:2 mm

ZT0981

1

ZT0985

1

ZT0986

1

NOSTUFF

NOSTUFF

NOSTUFF

10

Fan Holes

STDOFF-4.5OD.98H-1.1-3.48-TH

STDOFF-4.5OD.98H-1.1-3.48-TH

STDOFF-4.5OD.98H-1.1-3.48-TH

STDOFF-4.5OD.98H-1.1-3.48-TH

Left Speaker Holes

ZT0934

STDOFF-4.0OD3.0H-TH

STDOFF-4.0OD3.0H-TH

1

ZT0935

1

NOSTUFF

SH0934

POGO-2.0OD-3.5H-K86-K87

1

SH0935

POGO-2.0OD-3.5H-K86-K87

1

Keyboard / IPD Conn Protect

ZT0952

4.0OD1.85H-M1.6X0.35

ZT0953

4.0OD1.85H-M1.6X0.35

R0921

51

T29_A_BIAS_R

8

T29_A_BIAS_R TBT_A_BIAS0N

8

T29_A_BIAS_R

8

T29_A_BIAS_R

8

DPLL_REF_CLK_P

8

1 2

R0922

1 2

1/20W

R0923

51

1 2

5%

1/20W

MF

201

R0924

51

1 2

5%

1/20W

MF

201

1

R0941

1K

5%
1/16W
MF-LF
402

2

DPLL_REF_CLK_N

10

Unused eDP CLK

=PPVIN_SW_TBTBST

7

35

5%

1/20W

MF

201

51

5%

MF

201

TBT_A_BIAS0P

1

2

TBT_A_BIAS2P

1

2

TBT_A_BIAS2N

1

C0904

0.01UF

10%
10V

2

X5R
201

6 3

ZT0930

1

ZT0988

1

ZT0989

1

ZT0991

1

SM

SM

1

1

1

C0901

0.01UF

10%
10V

2

X5R
201

C0902

0.01UF

10%
10V
X5R
201

C0903

0.01UF

10%
10V
X5R

201

=PP1V05_S0_CPU_VCCPQE

1

R0940

1K

5%
1/16W
MF-LF
402

2

NOSTUFF

DPLL_REF_CLKN

MAKE_BASE=TRUE

TBTBST:N

R0950

0

1 2

5%

1/8W

MF-LF

805

19 23

19 89

33

33

GMUX ALIASES

17

17

85

104

87

87

16

87

16

16

16

16

16

87

14
7
12

7

=PP15V_TBT_REG

JTAG_ISP_TCK

MAKE_BASE=TRUE

JTAG_ISP_TDI

MAKE_BASE=TRUE

JTAG_ISP_TDO

19 89

MAKE_BASE=TRUE

TBT_LSOE<3>

TBT_LSOE<2>

GMUX_INT

89

MAKE_BASE=TRUE

PM_ALL_GPU_PGOOD

92

MAKE_BASE=TRUE

TP_LVDS_MUX_SEL_EG

MAKE_BASE=TRUE

6

39

EG_RESET_L

MAKE_BASE=TRUE

LVDS_IG_BKL_ON

MAKE_BASE=TRUE

LVDS_IG_PANEL_PWR

MAKE_BASE=TRUE

PPVOUT_S0_LCDBKLT

MAKE_BASE=TRUE

PEX_CLKREQ_L

MAKE_BASE=TRUE

PEG_CLKREQ_L

16

MAKE_BASE=TRUE

PM_ENET_EN

MAKE_BASE=TRUE

DP_INT_IG_ML_P<3..0>

9

93

DP_INT_IG_ML_N<3..0>

9

93

DP_INT_IG_AUX_P

9

93

DP_INT_IG_AUX_N

9

93

DP_INT_IG_HPD

9

FW_PLUG_DET_L

MAKE_BASE=TRUE

FW643_WAKE_L

MAKE_BASE=TRUE

TP_SMC_EXCARD_PWR_EN

MAKE_BASE=TRUE

PCIE_EXCARD_D2R_N

16

PCIE_EXCARD_D2R_P

16

PCIE_EXCARD_R2D_C_N

16

PCIE_EXCARD_R2D_C_P

16

PCIE_CLK100M_EXCARD_N

16 96

PCIE_CLK100M_EXCARD_P

16 96

TP_PEG_B_CLKRQ_L_GPIO56

TP_PCIECLKRQ4_L_GPIO26

TP_ISSP_SCLK_P1_1

53

MAKE_BASE=TRUE

TP_ISSP_SDATA_P1_0

53

MAKE_BASE=TRUE

89

89

89

89

=PP1V05_S0M_PCH_VCC_LAN

TP_PCH_GPIO64_CLKOUTFLEX0
TP_PCH_GPIO65_CLKOUTFLEX1

TP_PCH_GPIO66_CLKOUTFLEX2
TP_PCH_GPIO67_CLKOUTFLEX3

NC_FSB_CLK133M_PCHP

MAKE_BASE=TRUE

NC_FSB_CLK133M_PCHN

MAKE_BASE=TRUE

NC_LT_GAIN_TP

MAKE_BASE=TRUE

NC_RT_GAIN_TP

MAKE_BASE=TRUE

NC_SW_GAIN_TP

MAKE_BASE=TRUE

=PP5V_S0_AUDIO_XW

T29 / GMUX JTAG Signals

NO_TEST=TRUE

TP_GMUX_PT20A
TP_GMUX_PT20B
TP_GMUX_PT32A
TP_GMUX_PT32B

TP_PCH_CLKOUT_DPP

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

93

7

35

JTAG_GMUX_TCK

JTAG_TBT_TCK

JTAG_TBT_TDI

JTAG_TBT_TDO

T29_LSEO_LSOE3

MAKE_BASE=TRUE

T29_LSEO_LSOE2

MAKE_BASE=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

DPMUX_UC_IRQ

ALL_EG_PGOOD

LVDS_MUX_SEL_EG

GPU_RESET_L

IG_BKLT_EN

IG_LCD_PWR_EN

PPVOUT_SW_LCDBKLT

EG_CLKREQ_IN_L

EG_CLKREQ_OUT_L

=P1V2ENET_EN

Unused eDP signals

TRUE

MAKE_BASE=TRUE

XW0901

SM

1 2

XW0902

SM

1 2

XW0903

SM

1 2

NC_DP_INT_IG_MLP<3..0>

MAKE_BASE=TRUE

NC_DP_INT_IG_MLN<3..0>

MAKE_BASE=TRUE

NC_DP_INT_IG_AUXP

MAKE_BASE=TRUE

NC_DP_INT_IG_AUXN

MAKE_BASE=TRUE

NC_DP_INT_IG_HPD

MAKE_BASE=TRUE

FW_PME_L

=FW_PME_L

SMC_EXCARD_PWR_EN

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

ISSP_SCLK_P1_1

ISSP_SDATA_P1_0

TRUE

MAKE_BASE=TRUE

NC_PCH_CLKOUT_DPP

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_PCH_GPIO64_CLKOUTFLEX0
NC_PCH_GPIO65_CLKOUTFLEX1

NC_PCH_GPIO66_CLKOUTFLEX2
NC_PCH_GPIO67_CLKOUTFLEX3

FSB_CLK133M_PCH_P

FSB_CLK133M_PCH_N

LT_GAIN_TP

RT_GAIN_TP

SW_GAIN_TP

PP5V_S0_AUDIO

MAKE_BASE=TRUE

=PP5V_S0_AUDIO

PP5V_S0_AUDIO_AMP_L

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.30MM
VOLTAGE=5V

PP5V_S0_AUDIO_AMP_R

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.30MM
VOLTAGE=5V

89

33

19 33

33

TBT_LSEO<3>

TBT_LSEO<2>

19

89

89

75 82 89

89

89

90

82 89

89

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NC_PCIE_EXCARD_D2RN
NC_PCIE_EXCARD_D2RP
NC_PCIE_EXCARD_R2D_CN
NC_PCIE_EXCARD_R2D_CP

NC_PCIE_CLK100M_EXCARDN

NC_PCIE_CLK100M_EXCARDP

NC_PEG_B_CLKRQ_L_GPIO56

NC_PCIECLKRQ4_L_GPIO26

NC_PCH_CLKOUT_DPNTP_PCH_CLKOUT_DPN

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

33

33

NC_PEG_D2RP<15..12>

MAKE_BASE=TRUE

NC_PEG_D2RN<15..12>

MAKE_BASE=TRUE

NC_PEG_R2D_CP<15..12>

MAKE_BASE=TRUE

NC_PEG_R2D_CN<15..12>

MAKE_BASE=TRUE

PCIE_TBT_D2R_P<3..0>

33 96

MAKE_BASE=TRUE

PCIE_TBT_D2R_N<3..0>

33 96

MAKE_BASE=TRUE

PCIE_TBT_R2D_C_P<3..0>

33 96

MAKE_BASE=TRUE

PCIE_TBT_R2D_C_N<3..0>

33 96

MAKE_BASE=TRUE

PEG_D2R_P<7..0>

75 93

MAKE_BASE=TRUE

PEG_D2R_N<7..0>

75 93

MAKE_BASE=TRUE

PEG_R2D_C_P<7..0>

75 93

MAKE_BASE=TRUE

PEG_R2D_C_N<7..0>

75 93

MAKE_BASE=TRUE

TBT_D2R_P<3..2>

33 98

TBT_D2R_N<3..2>

33 98

TBT_R2D_C_P<3..2>

33 98

TBT_R2D_C_N<3..2>

33 98

19 39

26

38 39

6

6

LCD_BKLT_EN

89 90

57

61

61

NC_USB_EXTD_EHCIN

NC_USB_EXTD_EHCIP

NC_USB3_EXTC_RXN

NC_USB3_EXTC_RXP

NC_USB3_EXTC_TXN

NC_USB3_EXTC_TXP

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

MEMVTT_EN

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_DPB_IG_AUX_CHP

MAKE_BASE=TRUE

NC_DPB_IG_AUX_CHN

MAKE_BASE=TRUE

NC_DPB_IG_DDC_CLK

MAKE_BASE=TRUE

NC_DPB_IG_DDC_DATA

MAKE_BASE=TRUE

NC_DPB_IG_HPD

MAKE_BASE=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

Unused PEG signals

=PEG_D2R_P<15..12>

=PEG_D2R_N<15..12>

T29 Signals Through PEG

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

=PEG_D2R_P<11..8>

=PEG_D2R_N<11..8>

GPU signals

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

Unused T29 Ports

=PEG_D2R_P<7..0>

=PEG_D2R_N<7..0>

=PEG_R2D_C_P<7..0>

=PEG_R2D_C_N<7..0>

NC_T29_D2RP<3..2>

MAKE_BASE=TRUE

NC_T29_D2RN<3..2>

MAKE_BASE=TRUE

NC_T29_R2D_CP<3..2>

MAKE_BASE=TRUE

NC_T29_R2D_CN<3..2>

MAKE_BASE=TRUE

CPU signals

=DDRVTT_EN

DP_EG_AUXCH_N

DP_EG_AUXCH_P

NC_DPB_EG_AUX_CHN

MAKE_BASE=TRUE

NC_DPB_EG_AUX_CHP

MAKE_BASE=TRUE

NC_DPB_EG_DDC_CLK

MAKE_BASE=TRUE

NC_DPB_EG_DDC_DATA

MAKE_BASE=TRUE

NC_DPB_EG_MLN<3..0>

MAKE_BASE=TRUE

NC_DPB_EG_MLP<3..0>

MAKE_BASE=TRUE

T29_A_BIAS_R

8

1

R0901

4.7K

5%
1/16W
MF-LF
402

2

TRUE

TRUE

TRUE

TRUE

TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NC_DP_IG_MLP<3..0>

MAKE_BASE=TRUE

NC_DP_IG_MLN<3..0>

MAKE_BASE=TRUE

DP_IG_AUX_CH_P

86 95

MAKE_BASE=TRUE

DP_IG_AUX_CH_N

86 95

MAKE_BASE=TRUE

DP_IG_DDC_CLK

86

MAKE_BASE=TRUE

DP_IG_DDC_DATA

86

MAKE_BASE=TRUE

DP_IG_HPD

86

MAKE_BASE=TRUE

USB_EXTD_EHCI_N

USB_EXTD_EHCI_P

USB3_EXTC_RX_N

USB3_EXTC_RX_P

USB3_EXTC_TX_N

USB3_EXTC_TX_P

=PEG_R2D_C_P<15..12>

=PEG_R2D_C_N<15..12>

=PEG_R2D_C_P<11..8>

=PEG_R2D_C_N<11..8>

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

DP_EG_AUX_CH_N

DP_EG_AUX_CH_P

R0926

51

1 2

5%

1/20W

MF

201

DP_A_BIAS

MAKE_BASE=TRUE

=DP_A_BIAS

87

PLACE_NEAR=C9361.1:2 mm

NO_TEST=TRUE

NO_TEST=TRUE

DPB_IG_AUX_CH_P

DPB_IG_AUX_CH_N

DPB_IG_DDC_CLK

DPB_IG_DDC_DATA

DPB_IG_HPD

USB Signals

9

9

9

9

9

9

9

9

9

9

26 68

USB_BT_N

32 95

MAKE_BASE=TRUE

18

USB_BT_P

32 95

MAKE_BASE=TRUE

18

USB_TPAD_N

53 95

MAKE_BASE=TRUE

18

USB_TPAD_P

53 95

MAKE_BASE=TRUE

18

MAKE_BASE=TRUE

18

USB_IR_P USBHUB_DN2_P

44 95 25

MAKE_BASE=TRUE

18

9

9

USB_SMC_N

95

MAKE_BASE=TRUE

USB_SMC_P

95

MAKE_BASE=TRUE

NC_ADC_CH6

MAKE_BASE=TRUE

NC_ADC_CH7

MAKE_BASE=TRUE

TP_LVDS_IG_B_CLKP

6

MAKE_BASE=TRUE

TP_LVDS_IG_B_CLKN

6

MAKE_BASE=TRUE

TP_LVDS_IG_BKL_PWM

6

MAKE_BASE=TRUE

NC_GPU_XTALOUT

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATAP<3>

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATAN<3>

MAKE_BASE=TRUE

NC_LVDS_IG_B_DATAP<3>

MAKE_BASE=TRUE

NC_LVDS_IG_B_DATAN<3>

MAKE_BASE=TRUE

NC_USB_EXTCN

MAKE_BASE=TRUE

NC_USB_EXTCP

MAKE_BASE=TRUE

NC_USB3_EXTD_RXN

MAKE_BASE=TRUE

NC_USB3_EXTD_RXP

MAKE_BASE=TRUE

NC_USB3_EXTD_TXN

MAKE_BASE=TRUE

NC_USB3_EXTD_TXP

MAKE_BASE=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

USBHUB_DN1_N

USBHUB_DN1_P

USBHUB_DN3_N

USBHUB_DN3_P

USBHUB_DN2_NUSB_IR_N

USBHUB_DN4_N

USBHUB_DN4_P

ADC_CH6

ADC_CH7

LVDS_IG_B_CLK_P

LVDS_IG_B_CLK_N

LVDS_IG_BKL_PWM

GPU_XTALOUT

LVDS_IG_A_DATA_P<3>

LVDS_IG_A_DATA_N<3>

LVDS_IG_B_DATA_P<3>

LVDS_IG_B_DATA_N<3>

USB_EXTC_N

USB_EXTC_P

USB3_EXTD_RX_N

USB3_EXTD_RX_P

USB3_EXTD_TX_N

USB3_EXTD_TX_P

TALL POGO PINS for BT NF

81 86

DPB_EG_AUX_CH_N

DPB_EG_AUX_CH_P

DPB_EG_DDC_CLK

DPB_EG_DDC_DATA

81 86

100

100

SH0939

POGO-2.0OD-3.5H-K86-K87

POGO-2.0OD-3.5H-K86-K87

SM

SH0940

SM

1

1

POGO-2.0OD-3.5H-K86-K87

POGO-2.0OD-3.5H-K86-K87

DPB_EG_ML_N<3..0>

DPB_EG_ML_P<3..0>

R0927

51

TBT_A_BIAS1P TBT_A_BIAS1N

1

C0906

0.01UF

10%
10V

2

X5R
201

R9362

51

12

5%

1/20W

MF

201

TP_DP_IG_B_MLP<3..0>

T29_A_BIAS_R

8

88 88

PLACE_NEAR=C9361.1:2 mm

R9363

51

12

5%

1/20W

MF

201

DP_A_BIAS0

87

TP_DP_IG_B_MLN<3..0>

DPA_IG_AUX_CH_P

DPA_IG_AUX_CH_N

DPA_IG_DDC_CLK

DPA_IG_DDC_DATA

DPA_IG_HPD

17

17

17

17

17

SYNC_MASTER=K18_MLB

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

17

17

17

17

17

R

1 2

5%

1/20W

MF

201

DP_A_BIAS2

87

1

2

C0905

0.01UF

10%
10V
X5R
201

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.095 mm
VOLTAGE=0V

17

17

Digital Ground

Signal Aliases

Apple Inc.

GND

1

C0907

2

0.01UF

10%
10V
X5R
201

12

SH0941

SM

1

SH0942

SM

1

1

C0908

0.01UF

10%
10V

2

X5R
201

SYNC_DATE=04/27/2010

DRAWING NUMBER

051-9585

REVISION

3.0.0

BRANCH

PAGE

9 OF 132

SHEET

8 OF 105

124578

18 95

18 95

25

25

25

25

25 44 95

25

25

104

104

17

17

17

17 95

17 95

17

17

D

C

18

18

18

18

B

A

SIZE

D

www.vinafix.vn

8 7 6 5 4 3

=PP1V05_S0_CPU_VCCIO

1

R1010

2

24.9

1%
1/16W
MF-LF
402

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

U1000

IVY-BRIDGE

BGA

OMIT_TABLE

(1 OF 11)

PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO

DMI

PEG_RX10*
PEG_RX11*
PEG_RX12*
PEG_RX13*
PEG_RX14*
PEG_RX15*

INTEL FLEXIBLE DISPLAY INTERFACE SIGNALS

PCI EXPRESS BASED INTERFACE SIGNALS

PEG_TX10*
PEG_TX11*
PEG_TX12*
PEG_TX13*
PEG_TX14*
PEG_TX15*

EMBEDDED DISPLAY PORT

PEG_RX0*
PEG_RX1*
PEG_RX2*
PEG_RX3*
PEG_RX4*
PEG_RX5*
PEG_RX6*
PEG_RX7*
PEG_RX8*
PEG_RX9*

PEG_RX0
PEG_RX1
PEG_RX2
PEG_RX3
PEG_RX4
PEG_RX5
PEG_RX6
PEG_RX7
PEG_RX8

PEG_RX9
PEG_RX10
PEG_RX11
PEG_RX12
PEG_RX13
PEG_RX14
PEG_RX15

PEG_TX0*
PEG_TX1*
PEG_TX2*
PEG_TX3*
PEG_TX4*
PEG_TX5*
PEG_TX6*
PEG_TX7*
PEG_TX8*
PEG_TX9*

PEG_TX0

PEG_TX1

PEG_TX2

PEG_TX3

PEG_TX4

PEG_TX5

PEG_TX6

PEG_TX7

PEG_TX8

PEG_TX9
PEG_TX10
PEG_TX11
PEG_TX12
PEG_TX13
PEG_TX14
PEG_TX15

G2

H1

F3

F23

H23
H21

H19

J20
G18

K17
F15

H15

H13
H11

J12

E8
G10

J8

F7

G22
K23

K21

F19
K19

H17

K15
G14

J16

K13
F11

K11
F9

H9

H7
G6

A22
B23

C18

D21
B19

E20
A14

D17

B15
E16

D13

A10
B11

D9

B7
E12

C22

D23

A18
B21

D19

F21
C14

B17

D15
F17

B13
C10

D11

B9
D7

F13

93

=PEG_D2R_N<0>

=PEG_D2R_N<1>
=PEG_D2R_N<2>

=PEG_D2R_N<3>
=PEG_D2R_N<4>

=PEG_D2R_N<5>

=PEG_D2R_N<6>
=PEG_D2R_N<7>

=PEG_D2R_N<8>

=PEG_D2R_N<9>
=PEG_D2R_N<10>

=PEG_D2R_N<11>

=PEG_D2R_N<12>
=PEG_D2R_N<13>

=PEG_D2R_N<14>
=PEG_D2R_N<15>

=PEG_D2R_P<0>
=PEG_D2R_P<1>

=PEG_D2R_P<2>

=PEG_D2R_P<3>
=PEG_D2R_P<4>

=PEG_D2R_P<5>

=PEG_D2R_P<6>
=PEG_D2R_P<7>

=PEG_D2R_P<8>
=PEG_D2R_P<9>

=PEG_D2R_P<10>

=PEG_D2R_P<11>
=PEG_D2R_P<12>

=PEG_D2R_P<13>

=PEG_D2R_P<14>
=PEG_D2R_P<15>

=PEG_R2D_C_N<0>
=PEG_R2D_C_N<1>

=PEG_R2D_C_N<2>
=PEG_R2D_C_N<3>

=PEG_R2D_C_N<4>

=PEG_R2D_C_N<5>
=PEG_R2D_C_N<6>

=PEG_R2D_C_N<7>

=PEG_R2D_C_N<8>
=PEG_R2D_C_N<9>

=PEG_R2D_C_N<10>

=PEG_R2D_C_N<11>
=PEG_R2D_C_N<12>

=PEG_R2D_C_N<13>
=PEG_R2D_C_N<14>

=PEG_R2D_C_N<15>

=PEG_R2D_C_P<0>

=PEG_R2D_C_P<1>

=PEG_R2D_C_P<2>
=PEG_R2D_C_P<3>

=PEG_R2D_C_P<4>

=PEG_R2D_C_P<5>
=PEG_R2D_C_P<6>

=PEG_R2D_C_P<7>
=PEG_R2D_C_P<8>

=PEG_R2D_C_P<9>

=PEG_R2D_C_P<10>
=PEG_R2D_C_P<11>

=PEG_R2D_C_P<12>

=PEG_R2D_C_P<13>
=PEG_R2D_C_P<14>

=PEG_R2D_C_P<15>

AC10

AA10

N10

R10

R8

U10

N8
T9

R6

U8

N4
R4

P1

U6

N2

R2
P3

T5

V7

W8

AA8

U4

W2

V1
Y5

W6

W10

Y9

U2
W4

V3

AA6

AC8

AA2

AD9

AB3

AB7

AG2

AF1
AE6

AG6

AG4

AF3
AF7

AG8

AE4

AE2

AB1

AC2

AE8

DMI_RX0*
DMI_RX1*
DMI_RX2*
DMI_RX3*

DMI_RX0
DMI_RX1
DMI_RX2
DMI_RX3

DMI_TX0*
DMI_TX1*
DMI_TX2*
DMI_TX3*

DMI_TX0
DMI_TX1
DMI_TX2
DMI_TX3

FDI0_TX0*
FDI0_TX1*
FDI0_TX2*
FDI0_TX3*

FDI1_TX0*
FDI1_TX1*
FDI1_TX2*
FDI1_TX3*

FDI0_TX0
FDI0_TX1
FDI0_TX2
FDI0_TX3

FDI1_TX0
FDI1_TX1
FDI1_TX2
FDI1_TX3

FDI0_FSYNC
FDI1_FSYNC

FDI_INT

FDI1_LSYNC
FDI0_LSYNC

EDP_TX0*
EDP_TX1*
EDP_TX2*
EDP_TX3*

EDP_TX0
EDP_TX1
EDP_TX2
EDP_TX3

EDP_AUX
EDP_AUX*

EDP_ICOMPO
EDP_COMPIO

EDP_HPD*

DMI_S2N_N<0> CPU_PEG_COMP

6

17 93

IN

DMI_S2N_N<1>

6

17 93

IN

DMI_S2N_N<2>

17 93

IN

DMI_S2N_N<3>

6

17 93

IN

DMI_S2N_P<0>

6

17 93

IN

DMI_S2N_P<1>

6

17 93

IN

DMI_S2N_P<2>

17 93

D

C

=PP1V05_S0_CPU_VCCIO

7 9

10 12 13 14

1

OMIT_TABLE

B

8

IN

R1031

1K

5%
1/16W
MF-LF

402

DP_INT_IG_HPD

1

2

R1030

24.9

1%
1/16W
MF-LF
402

2

PLACE_NEAR=U1000.AB1:12.7mm

IN

DMI_S2N_P<3>

6

17 93

IN

DMI_N2S_N<0>

17 93

OUT

DMI_N2S_N<1>

6

17 93

OUT

DMI_N2S_N<2>

6

17 93

OUT

DMI_N2S_N<3>

6

17 93

OUT

DMI_N2S_P<0>

17 93

OUT

DMI_N2S_P<1>

6

17 93

OUT

DMI_N2S_P<2>

6

17 93

OUT

DMI_N2S_P<3>

6

17 93

OUT

FDI_DATA_N<0>

17 93

OUT

FDI_DATA_N<1>

6

17 93

OUT

FDI_DATA_N<2>

17 93

OUT

FDI_DATA_N<3>

17 93

OUT

FDI_DATA_N<4>

6

17 93

OUT

FDI_DATA_N<5>

6

17 93

OUT

FDI_DATA_N<6>

6

17 93

OUT

FDI_DATA_N<7>

6

17 93

OUT

FDI_DATA_P<0>

17 93

OUT

FDI_DATA_P<1>

6

17 93

OUT

FDI_DATA_P<2>

17 93

OUT

FDI_DATA_P<3>

17 93

OUT

FDI_DATA_P<4>

6

17 93

OUT

FDI_DATA_P<5>

6

17 93

OUT

FDI_DATA_P<6>

6

17 93

OUT

FDI_DATA_P<7>

6

17 93

OUT

FDI_FSYNC<0>

6

17 93

IN

FDI_FSYNC<1>

6

17 93

IN

FDI_INT

6

17 93

IN

FDI_LSYNC<1>

6

17 93

IN

FDI_LSYNC<0>

6

17 93

IN

DP_INT_IG_ML_N<0>

8

93

OUT

DP_INT_IG_ML_N<1>

8

93

OUT

DP_INT_IG_ML_N<2>

8

93

OUT

DP_INT_IG_ML_N<3>

8

93

OUT

DP_INT_IG_ML_P<0>

8

93

OUT

DP_INT_IG_ML_P<1>

8

93

OUT

DP_INT_IG_ML_P<2>

8

93

OUT

DP_INT_IG_ML_P<3>

8

93

OUT

DP_INT_IG_AUX_P

8

93

BI

DP_INT_IG_AUX_N

8

93

BI

CPU_EDP_COMP

93

DP_INT_IG_HPD_L

D

3

Q1031

1

2N7002TXG

G

SOT-523-3

EDP:YES

S

2

7 9

10 12 13 14

NOTE:

Intel is investigating processor driven VREF_DQ generation.
This connection is to support the same.

9

23 93

9

23 93

9

23 93

9

23 93

9

23 93

9

23 93

9

23 93

9

23 93

23 93

23 93

23 93

23 93

23 93

23 93

23 93

23 93

9

23 93

23 93

PPCPU_MEM_VREFDQ_B

31 93

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V

PPCPU_MEM_VREFDQ_A

31 93

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V

CPU_CFG<0>

CPU_CFG<1>
CPU_CFG<2>

CPU_CFG<3>
CPU_CFG<4>

CPU_CFG<5>

CPU_CFG<6>
CPU_CFG<7>

CPU_CFG<8>

CPU_CFG<9>
CPU_CFG<10>

CPU_CFG<11>

CPU_CFG<12>
CPU_CFG<13>

CPU_CFG<14>
CPU_CFG<15>

CPU_CFG<16>

CPU_CFG<17>

B57

(IPU)

D57

(IPU)

B55

(IPU)

A54

(IPU)

A58

(IPU)

D55

(IPU)

C56

(IPU)

E54

(IPU)

J54

(IPU)

G56

(IPU)

CFG

F55

(IPU)

K55

(IPU)

F57

(IPU)

E58

(IPU)

H57

(IPU)

H55

(IPU)

D53

(IPU)

K57

(IPU)

G64

NC

BJ42

NC

BJ34

NC

BJ22

NC

BH43

NC

BH35

NC

BH25

NC

BH23

NC

BH21

NC

BH19

NC

BG62

NC

BG34

NC

BG26

NC

BG22

NC

BG4

(DDR_VREF1)

BF63

NC

BF43

NC

BF41

BF35
BF25

BF23

BF21
BF19

BE32

BE16

BD33

BD29

BD19
BD15

BD13

BC42
BC30

BC14

RSVD

BF3

(DDR_VREF0)

BE6

NC
NC
NC
NC
NC
NC

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

U1000

IVY-BRIDGE

BGA

(5 OF 11)

RESERVED

OMIT_TABLE

(THERMDA)

(THERMDC)

RSVD

BB57

BB43
BB25

BB17

BB15
BB13

BA48

BA16
AY45

AY41
AY17

AY15

AY13
AW50

AW46

AW42
AW14

AJ10

AJ6
AH5

AD5
AC6

AC4

AA4
P7

N6

M9
M5

L10

L6
L4

L2
K49

K47

K9
K7

K5

J50
J4

J2

H49
H47

H5
G52

G48

G4
F5

D49

D25
D3

C52

C24
C4

B53
B25

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

12

D

C

B

CPU_CFG<7>

9

23 93

CPU_CFG<6>

9

23 93

CPU_CFG<5>

9

23 93

CPU_CFG<4>

9

23 93

9

23 93

A

CPU_CFG<4> should be pulled down to enable EDP

CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS
CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4
CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED
CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED
CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

NOSTUFF

R1042

EDP:YES

1

R1044

1K

1K

5%

1/16W

1/16W

MF-LF

MF-LF

402

2

1

1

R1045

1K

5%

5%

1/16W
MF-LF

402402

2

2

NOSTUFF

R1046

NOSTUFF

1

1

R1047

1K

1K

5%

5%

1/16W

1/16W

MF-LF

MF-LF

402

402

2

2

CPU_CFG<16>

9

23 93

CPU_CFG<3>

9

23 93

CPU_CFG<1>

9

23 93

CPU_CFG<0>CPU_CFG<2>

9

23 93

NOSTUFF

R1040

These can be Placed close to J2500 and Only for debug access

NOSTUFF

1

1K

5%
1/16W
MF-LF

402

2

R1041

NOSTUFF

1

R1043

1K

5%
1/16W
MF-LF

402

2

PART NUMBER

116S0066

116S0090

NOSTUFF

1

1K

5%
1/16W
MF-LF

402

2

R1049

1

1K

5%
1/16W
MF-LF

402

2

QTY

1

1

DESCRIPTION

RES,MTL FILM,1/16W,1K,0402,SMD,LF

RES,MTL FILM,1/16W,10K,0402,SMD,LF

REFERENCE DES

R1031

R1031

CRITICAL

BOM OPTION

EDP:YES

EDP:NO

6 3

PAGE TITLE

CPU DMI/PEG/FDI/RSVD

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-9585

REVISION

3.0.0

BRANCH

PAGE

10 OF 132

SHEET

9 OF 105

124578

SIZE

A

D

www.vinafix.vn

8 7 6 5 4 3

12

D

=PP1V05_S0_CPU_VCCIO

7 9

10 12 13 14

=PP1V05_S0_CPU_VCCIO

7 9

10 12 13 14

1

R1101

68

5%

1/16W

MF-LF

402

2

CPU_PROC_SEL_L

19 93

R1103

C

7 9

10 12 13 14

CPU_PROCHOT_L

45 46 69 93

BI

=PP1V05_S0_CPU_VCCIO

CPU_RESET_L

23 24

IN

=PP1V5_S3_CPU_VCCDDR

7

10 13 15 26

PLACE_NEAR=R1121.2:1mm

R1126

1/16W
MF-LF

1

75

1%

402

2

R1120

PM_MEM_PWRGD

17 26 93

B

R1120 and R1121 are Intel recommended values

PLACE_NEAR=U1000.BJ44:2.54mm

IN

=PP1V5_S3_CPU_VCCDDR

7

10 13 15 26

R1130

1

1K

5%
1/16W
MF-LF

402

2

56

12

5%
1/16W
MF-LF

402

1

200

1%
1/16W
MF-LF

402

PLACE_NEAR=U1000.AY25:51.562mm

R1121

2

130

1%
1/16W
MF-LF

402

R1125

43.2

12

1%
1/16W
MF-LF

402

12

PLACE_NEAR=U1000.BJ46:12.7mm

45 93

19 46 93

19 46 93

PLT_RESET_LS1V1_L

17 93

19 23 93

26

OUT

1

R1112

140

1%
1/16W
MF-LF
402

2

PLACE_NEAR=U1000.BG46:12.7mm

OUT

OUT

BI

OUT

IN

IN

PM_MEM_PWRGD_R

=MEM_RESET_L

CPU_DDR_VREF

1

R1113

25.5

1%
1/16W
MF-LF
402

2

CPU_CATERR_L

CPU_PECI

CPU_PROCHOT_R_L

PM_THRMTRIP_L

PM_SYNC

CPU_PWRGD

1

R1114

200

2

1%
1/16W
MF-LF
402

NOSTUFF

1

R1100

1K

5%

1/20W

MF

201

2

CPU_SM_RCOMP<0>

93

CPU_SM_RCOMP<1>

93

CPU_SM_RCOMP<2>

93

PLACE_NEAR=U1000.BF45:12.7mm

1

R1104

51

5%
1/16W
MF-LF
402

2

NOSTUFF

NOSTUFF

1

R1102

1K

5%
1/20W
MF
201

2

NC

1

R1111

10K

5%

PLACE_NEAR=U1800.AY11:157mm

1/16W
MF-LF
402

2

B59

PROC_DETECT*

AH9

PROC_SELECT*

H53

CATERR*

F53

PECI

H51

PROCHOT*

F51

THERMTRIP*

K51

RESET*

K53

PM_SYNC

C60

UNCOREPWRGOOD

AY25

SM_DRAMPWROK

BE24

SM_DRAMRST*

BJ44

SM_VREF

BJ46

SM_RCOMP0

BG46

SM_RCOMP1

BF45

SM_RCOMP2

U1000

IVY-BRIDGE

BGA

OMIT_TABLE

(2 OF 11)

CLOCKS

THERMAL

PWR MGMT

JTAG & BPM

DDR3 MISC

DPLL_REF_CLK

DPLL_REF_CLK*

BCLK_ITP

BCLK_ITP*

BCLK

BCLK*

PRDY*

(IPU)

PREQ*

(IPU)

(IPD)

(IPU)

TRST*

(IPU)

(IPU)

DBR*

BPM0*

(IPU)

BPM1*

(IPU)

BPM2*

(IPU)

BPM3*

(IPU)

BPM4*

(IPU)

BPM5*

(IPU)

BPM6*

(IPU)

BPM7*

(IPU)

TCK
TMS

TDI
TDO

AJ4
AJ2

K63
K65

D5

C6

J62

H65

J58

H59

H63

K61
K59

H61

C62

D61
E62

F63

D59
F61

F59
G60

DPLL_REF_CLK_P

DPLL_REF_CLK_N

ITPCPU_CLK100M_P

ITPCPU_CLK100M_N

DMI_CLK100M_CPU_P

DMI_CLK100M_CPU_N

XDP_CPU_PRDY_L

XDP_CPU_PREQ_L

XDP_CPU_TCK

XDP_CPU_TMS
XDP_CPU_TRST_L

XDP_CPU_TDI
XDP_CPU_TDO

XDP_DBRESET_L

XDP_BPM_L<0>
XDP_BPM_L<1>

XDP_BPM_L<2>

XDP_BPM_L<3>
XDP_BPM_L<4>

XDP_BPM_L<5>

XDP_BPM_L<6>
XDP_BPM_L<7>

8

IN

8

IN

16 93

IN

16 93

IN

16 93

IN

16 93

IN

23 93

OUT

23 93

IN

23 93

IN

23 93

IN

23 93

IN

23 93

IN

23 93

OUT

23 24 93

OUT

23 93

BI

23 93

BI

23 93

BI

23 93

BI

23 93

BI

23 93

BI

23 93

BI

23 93

BI

D

C

B

1

R1131

PLACE_NEAR=U1000.BJ44:2.54mm

1K

5%
1/16W
MF-LF

402

PLACE_NEAR=U1000.BJ44:2.54mm

A

1

C1130

0.1UF

10%
16V

2

X5R

2

402

SIZE

A

D

6 3

PAGE TITLE

CPU CLOCK/MISC/JTAG

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-9585

REVISION

3.0.0

BRANCH

PAGE

11 OF 132

SHEET

10 OF 105

124578

www.vinafix.vn

8 7 6 5 4 3

12

SA_CLK0

SA_CKE0

SA_CLK1

SA_CKE1

SA_CS0*
SA_CS1*

SA_ODT0
SA_ODT1

SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8

SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15

BB31

BA32

BC18

AW34

AY33

BD17

BD41

BD45

BB41

BC46

AN8

AU6

BC6
BD9

BC50
BB55

BD59

AU60

AN6

AU8
BD5

BC10

BB51
BD55

BD61
AV61

BD27
BA28

BB27

AW26
BB23

BA24

AY21
BD21

BC22
BB21

AW38

AW22
BA20

BB45

BE20
AW18

MEM_A_CLK_P<0>

MEM_A_CLK_N<0>

MEM_A_CKE<0>

MEM_A_CLK_P<1>

MEM_A_CLK_N<1>

MEM_A_CKE<1>

MEM_A_CS_L<0>

MEM_A_CS_L<1>

MEM_A_ODT<0>

MEM_A_ODT<1>

MEM_A_DQS_N<0>

MEM_A_DQS_N<1>
MEM_A_DQS_N<2>

MEM_A_DQS_N<3>

MEM_A_DQS_N<4>
MEM_A_DQS_N<5>

MEM_A_DQS_N<6>

MEM_A_DQS_N<7>

MEM_A_DQS_P<0>
MEM_A_DQS_P<1>

MEM_A_DQS_P<2>

MEM_A_DQS_P<3>
MEM_A_DQS_P<4>

MEM_A_DQS_P<5>

MEM_A_DQS_P<6>
MEM_A_DQS_P<7>

MEM_A_A<0>
MEM_A_A<1>

MEM_A_A<2>
MEM_A_A<3>

MEM_A_A<4>

MEM_A_A<5>
MEM_A_A<6>

MEM_A_A<7>

MEM_A_A<8>
MEM_A_A<9>

MEM_A_A<10>

MEM_A_A<11>
MEM_A_A<12>

MEM_A_A<13>
MEM_A_A<14>

MEM_A_A<15>

SB_CLK0

SB_CLK0*

SB_CKE0

SB_CLK1

SB_CLK1*

SB_CKE1

SB_CS0*
SB_CS1*

SB_ODT0
SB_ODT1

SB_DQS0*
SB_DQS1*
SB_DQS2*
SB_DQS3*
SB_DQS4*
SB_DQS5*
SB_DQS6*
SB_DQS7*

SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8

SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15

BF33

BH33

BD25

BF37

BH37

BJ26

BE40

BH41

BG42

BH45

AN4

AW2

BH9
BF15

BF51
BH57

AY63

AN62

AN2

AW4
BF9

BH15

BH51
BF57

AY65
AN64

BF31
BH31

BB37

BC34
BF27

BB33

BH27
BG30

BH29
BF29

AY37

BJ30
AW30

BA40

BB29
BE28

MEM_B_CLK_P<0>

MEM_B_CLK_N<0>

MEM_B_CKE<0>

MEM_B_CLK_P<1>

MEM_B_CLK_N<1>

MEM_B_CKE<1>

MEM_B_CS_L<0>

MEM_B_CS_L<1>

MEM_B_ODT<0>

MEM_B_ODT<1>

MEM_B_DQS_N<0>

MEM_B_DQS_N<1>
MEM_B_DQS_N<2>

MEM_B_DQS_N<3>

MEM_B_DQS_N<4>
MEM_B_DQS_N<5>

MEM_B_DQS_N<6>

MEM_B_DQS_N<7>

MEM_B_DQS_P<0>
MEM_B_DQS_P<1>

MEM_B_DQS_P<2>

MEM_B_DQS_P<3>
MEM_B_DQS_P<4>

MEM_B_DQS_P<5>

MEM_B_DQS_P<6>
MEM_B_DQS_P<7>

MEM_B_A<0>
MEM_B_A<1>

MEM_B_A<2>
MEM_B_A<3>

MEM_B_A<4>

MEM_B_A<5>
MEM_B_A<6>

MEM_B_A<7>

MEM_B_A<8>
MEM_B_A<9>

MEM_B_A<10>

MEM_B_A<11>
MEM_B_A<12>

MEM_B_A<13>
MEM_B_A<14>

MEM_B_A<15>

6

29 94

OUT

6

29 94

OUT

6

29 94

OUT

6

29 94

OUT

6

29 94

OUT

6

29 94

OUT

6

29 94

OUT

6

29 94

OUT

6

29 94

OUT

6

29 94

OUT

6

28 94

BI

6

28 94

BI

6

28 94

BI

6

28 94

BI

6

28 94

BI

6

28 94

BI

6

28 94

BI

6

28 94

BI

6

28 94

BI

6

28 94

BI

6

28 94

BI

6

28 94

BI

6

28 94

BI

6

28 94

BI

6

28 94

BI

6

28 94

BI

6

29 94

OUT

6

29 94

OUT

6

29 94

OUT

6

29 94

OUT

6

29 94

OUT

6

29 94

OUT

6

29 94

OUT

6

29 94

OUT

6

29 94

OUT

6

29 94

OUT

6

29 94

OUT

6

29 94

OUT

6

29 94

OUT

6

29 94

OUT

6

29 94

OUT

6

29 94

OUT

D

C

B

BF11
BJ10

BH11

BG10
BJ14

BG14

BF17
BJ18

BF13

BH13
BH17

BG18
BH49

BF47

BH53
BG50

BF49

BH47
BF53

BJ50

BF55
BH55

BJ58
BH59

BJ54

BG54
BG58

BF59

BA64
BC62

AU62

AW64
BA62

BC64
AU64

AW62

AR64
AT65

AL64

AM65
AR62

AT63

AL62
AM63

BJ38

BD37

AY29

BH39

BG38
BF39

AL4

AK3
AP3

AR2

AL2
AK1

AP1

AR4
AV3

AU4
BA4

BB1

AV1
AU2

BA2

BB3
BC2

BF7

BC4
BH7

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

SB_BS0
SB_BS1
SB_BS2

SB_CAS*
SB_RAS*
SB_WE*

U1000

BGA

(4 OF 11)

MEMORY CHANNEL B

OMIT_TABLE

MEM_B_DQ<0>

6

6

27 94

OUT

6

27 94

OUT

6

27 94

OUT

6

27 94

OUT

6

27 94

OUT

6

27 94

OUT

6

27 94

OUT

6

27 94

OUT

6

27 94

OUT

6

27 94

OUT

6

28 94

BI

6

28 94

BI

6

28 94

BI

6

28 94

BI

6

28 94

BI

6

28 94

BI

6

28 94

BI

6

28 94

BI

6

28 94

BI

6

28 94

BI

6

28 94

BI

6

28 94

BI

6

28 94

BI

6

28 94

BI

6

28 94

BI

6

28 94

BI

6

27 94

OUT

6

27 94

OUT

6

27 94

OUT

6

27 94

OUT

6

27 94

OUT

6

27 94

OUT

6

27 94

OUT

6

27 94

OUT

6

27 94

OUT

6

27 94

OUT

6

27 94

OUT

6

27 94

OUT

6

27 94

OUT

6

27 94

OUT

6

27 94

OUT

6

27 94

OUT

28 94

BI

MEM_B_DQ<1>

6

28 94

BI

MEM_B_DQ<2>

6

28 94

BI

MEM_B_DQ<3>

6

28 94

BI

MEM_B_DQ<4>

6

28 94

BI

MEM_B_DQ<5>

6

28 94

BI

MEM_B_DQ<6>

6

28 94

BI

MEM_B_DQ<7>

6

28 94

BI

MEM_B_DQ<8>

6

28 94

BI

MEM_B_DQ<9>

6

28 94

BI

MEM_B_DQ<10>

6

28 94

BI

MEM_B_DQ<11>

6

28 94

BI

MEM_B_DQ<12>

6

28 94

BI

MEM_B_DQ<13>

6

28 94

BI

MEM_B_DQ<14>

6

28 94

BI

MEM_B_DQ<15>

6

28 94

BI

MEM_B_DQ<16>

6

28 94

BI

MEM_B_DQ<17>

6

28 94

BI

MEM_B_DQ<18>

6

28 94

BI

MEM_B_DQ<19>

6

28 94

BI

MEM_B_DQ<20>

6

28 94

BI

MEM_B_DQ<21>

6

28 94

BI

MEM_B_DQ<22>

6

28 94

BI

MEM_B_DQ<23>

6

28 94

BI

MEM_B_DQ<24>

6

28 94

BI

MEM_B_DQ<25>

6

28 94

BI

MEM_B_DQ<26>

6

28 94

BI

MEM_B_DQ<27>

6

28 94

BI

MEM_B_DQ<28>

6

28 94

BI

MEM_B_DQ<29>

6

28 94

BI

MEM_B_DQ<30>

6

28 94

BI

MEM_B_DQ<31>

6

28 94

BI

MEM_B_DQ<32>

6

28 94

BI

MEM_B_DQ<33>

6

28 94

BI

MEM_B_DQ<34>

6

28 94

BI

MEM_B_DQ<35>

6

28 94

BI

MEM_B_DQ<36>

6

28 94

BI

MEM_B_DQ<37>

6

28 94

BI

MEM_B_DQ<38>

6

28 94

BI

MEM_B_DQ<39>

6

28 94

BI

MEM_B_DQ<40>

6

28 94

BI

MEM_B_DQ<41>

6

28 94

BI

MEM_B_DQ<42>

6

28 94

BI

MEM_B_DQ<43>

6

28 94

BI

MEM_B_DQ<44>

6

28 94

BI

MEM_B_DQ<45>

6

28 94

BI

MEM_B_DQ<46>

6

28 94

BI

MEM_B_DQ<47>

6

28 94

BI

MEM_B_DQ<48>

6

28 94

BI

MEM_B_DQ<49>

6

28 94

BI

MEM_B_DQ<50>

6

28 94

BI

MEM_B_DQ<51>

6

28 94

BI

MEM_B_DQ<52>

6

28 94

BI

MEM_B_DQ<53>

6

28 94

BI

MEM_B_DQ<54>

6

28 94

BI

MEM_B_DQ<55>

6

28 94

BI

MEM_B_DQ<56>

6

28 94

BI

MEM_B_DQ<57>

6

28 94

BI

MEM_B_DQ<58>

6

28 94

BI

MEM_B_DQ<59>

6

28 94

BI

MEM_B_DQ<60>

6

28 94

BI

MEM_B_DQ<61>

6

28 94

BI

MEM_B_DQ<62>

6

28 94

BI

MEM_B_DQ<63>

6

28 94

BI

MEM_B_BA<0>

6

29 94

OUT

MEM_B_BA<1>

6

29 94

OUT

MEM_B_BA<2>

6

29 94

OUT

MEM_B_CAS_L

6

29 94

OUT

MEM_B_RAS_L

6

29 94

OUT

MEM_B_WE_L

6

29 94

OUT

AL10

AN10

AR10

AW12

AV11

BB11
BA12

BA10
BD11

BE12
BB49

AY49

BE52
BD51

BD49

BE48
BA52

AY51

BC54
AY53

AW54
AY55

BD53

BB53
BE56

BA56

BD57
BF61

BA60

BB61
BE60

BD63
BB59

BC58

AW58
AY59

AL60

AP61
AW60

AY57

AN60
AR60

BA36

BC38

BB19

BE44

BE36
BA44

AL6

AL8
AP7

AM5

AK7

AM9

AR8
AV7

AY5

AT5
AR6

AW6

AT9
BA6

BA8

BG6
AY9

AW8
BB7

BC8

BE4

BE8

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

SA_BS0
SA_BS1
SA_BS2

SA_CAS*
SA_RAS*
SA_WE*

U1000

IVY-BRIDGE IVY-BRIDGE

(3 OF 11)

SA_CLK0*

BGA

OMIT_TABLE

SA_CLK1*

SA_DQS0*
SA_DQS1*
SA_DQS2*
SA_DQS3*
SA_DQS4*
SA_DQS5*
SA_DQS6*
SA_DQS7*

MEMORY CHANNEL A

MEM_A_DQ<0>

6

28 94

BI

MEM_A_DQ<1>

6

28 94

BI

MEM_A_DQ<2>

6

28 94

BI

MEM_A_DQ<3>

6

28 94

BI

MEM_A_DQ<4>

6

28 94

D

C

B

BI

MEM_A_DQ<5>

6

28 94

BI

MEM_A_DQ<6>

6

28 94

BI

MEM_A_DQ<7>

6

28 94

BI

MEM_A_DQ<8>

6

28 94

BI

MEM_A_DQ<9>

6

28 94

BI

MEM_A_DQ<10>

6

28 94

BI

MEM_A_DQ<11>

6

28 94

BI

MEM_A_DQ<12>

6

28 94

BI

MEM_A_DQ<13>

6

28 94

BI

MEM_A_DQ<14>

6

28 94

BI

MEM_A_DQ<15>

6

28 94

BI

MEM_A_DQ<16>

6

28 94

BI

MEM_A_DQ<17>

6

28 94

BI

MEM_A_DQ<18>

6

28 94

BI

MEM_A_DQ<19>

6

28 94

BI

MEM_A_DQ<20>

6

28 94

BI

MEM_A_DQ<21>

6

28 94

BI

MEM_A_DQ<22>

6

28 94

BI

MEM_A_DQ<23>

6

28 94

BI

MEM_A_DQ<24>

6

28 94

BI

MEM_A_DQ<25>

6

28 94

BI

MEM_A_DQ<26>

6

28 94

BI

MEM_A_DQ<27>

6

28 94

BI

MEM_A_DQ<28>

6

28 94

BI

MEM_A_DQ<29>

6

28 94

BI

MEM_A_DQ<30>

6

28 94

BI

MEM_A_DQ<31>

6

28 94

BI

MEM_A_DQ<32>

6

28 94

BI

MEM_A_DQ<33>

6

28 94

BI

MEM_A_DQ<34>

6

28 94

BI

MEM_A_DQ<35>

6

28 94

BI

MEM_A_DQ<36>

6

28 94

BI

MEM_A_DQ<37>

6

28 94

BI

MEM_A_DQ<38>

6

28 94

BI

MEM_A_DQ<39>

6

28 94

BI

MEM_A_DQ<40>

6

28 94

BI

MEM_A_DQ<41>

6

28 94

BI

MEM_A_DQ<42>

6

28 94

BI

MEM_A_DQ<43>

6

28 94

BI

MEM_A_DQ<44>

6

28 94

BI

MEM_A_DQ<45>

6

28 94

BI

MEM_A_DQ<46>

6

28 94

BI

MEM_A_DQ<47>

6

28 94

BI

MEM_A_DQ<48>

6

28 94

BI

MEM_A_DQ<49>

6

28 94

BI

MEM_A_DQ<50>

6

28 94

BI

MEM_A_DQ<51>

6

28 94

BI

MEM_A_DQ<52>

6

28 94

BI

MEM_A_DQ<53>

6

28 94

BI

MEM_A_DQ<54>

6

28 94

BI

MEM_A_DQ<55>

6

28 94

BI

MEM_A_DQ<56>

6

28 94

BI

MEM_A_DQ<57>

6

28 94

BI

MEM_A_DQ<58>

6

28 94

BI

MEM_A_DQ<59>

6

28 94

BI

MEM_A_DQ<60>

6

28 94

BI

MEM_A_DQ<61>

6

28 94

BI

MEM_A_DQ<62>

6

28 94

BI

MEM_A_DQ<63>

6

28 94

BI

MEM_A_BA<0>

6

27 94

OUT

MEM_A_BA<1>

6

27 94

OUT

MEM_A_BA<2>

6

27 94

OUT

MEM_A_CAS_L

6

27 94

OUT

MEM_A_RAS_L

6

27 94

OUT

MEM_A_WE_L

6

27 94

OUT

A

PAGE TITLE

CPU DDR3 INTERFACES

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=06/15/2010

DRAWING NUMBER

051-9585

REVISION

3.0.0

BRANCH

PAGE

12 OF 132

SHEET

11 OF 105

124578

SIZE

A

D

www.vinafix.vn

8 7 6 5 4 3

12

D

C

PLACE_NEAR=U1000.B47:50.8mm

B

PLACE_SIDE=BOTTOM

PLACE_NEAR=U1000.A46:50.8mm

PLACE_SIDE=BOTTOM

NOSTUFF

69 93

69 93

69 93

69 93

71 93

71 93

NOSTUFF

OUT
OUT

OUT
OUT

OUT
OUT

R1360

R1361

1

100

1%
1/16W
MF-LF

402

2

1

100

1%
1/16W
MF-LF

402

2

CPU_VIDSOUT

69 93

BI

CPU_VIDSCLK

69 93

OUT

CPU_VIDALERT_L

69 93

IN

=PPVCORE_S0_CPU

=PP1V05_S0_CPU_VCCIO

PLACE_SIDE=BOTTOM

PLACE_NEAR=U1000.AW10:50.8mm

NOSTUFF

1

2

1

2

1

R1362

100

R1363

100

R1366

100

1%
1/16W
MF-LF
402

PLACE_SIDE=BOTTOM

PLACE_NEAR=U1000.AU10:50.8mm

1%
1/16W
MF-LF
402

NOSTUFF

1%
1/16W
MF-LF
402

2

PLACE_NEAR=U1000.F49:50.8mm

PLACE_NEAR=U1000.E50:50.8mm

PLACE_SIDE=BOTTOM

1

R1367

100

1%
1/16W
MF-LF
402

2

NOSTUFF

NOSTUFF

7

12 14 49

7 9

PLACE_SIDE=BOTTOM

PLACE_SIDE=BOTTOM

PLACE_SIDE=BOTTOM

=PP1V05_S0_CPU_VCCIO

PLACE_NEAR=R1310.1:2.54mm

1

R1300

75

1%
1/16W
MF-LF
402

2

402 1/16W

0

0

1/16W402

105

10 12 13 14

7

12 13

15

R1364

49.9

NOSTUFF

1/20W

201

R1365

49.9

NOSTUFF

1/20W

201

R1312

1 2

R1311

1 2

R1310

1 2

43

1

1%

MF

2

1

1%

MF

2

7 9

10 12 13 14

=PP1V05_S0_CPU_VCCIO

5% MF-LF

MF-LF1/16W402 5%

MF-LF5%

PLACE_NEAR=U1000.B51:38mm

=PPVCORE_S0_CPU

=PPVCORE_S0_CPU_VCCAXG=PPVCORE_S0_CPU_VCCAXG

PLACE_SIDE=BOTTOM

NOSTUFF

1

R1370

49.9

1%
1/20W
MF
201

2

66 93

OUT

1

R1371

PLACE_SIDE=BOTTOM

49.9
NOSTUFF

1%
1/20W
MF
201

2

1

R1302

130

PLACE_NEAR=U1000.A50:2.54mm

1%
1/16W
MF-LF
402

2

CPU_VIDSOUT_R

CPU_VIDSCLK_R

CPU_VIDALERT_L_R

=PPVCCSA_S0_CPU

1

R1368

100

1%
1/16W
MF-LF
402

2

7

12 14 49

105
7

12 13 15

D

=PP3V3_S0_CPU_VCCIO_SEL

CPU:SNB

1

R1320

10K

1/16W

=PPVCCSA_S0_CPU

7

12 15

7 9

10 12 13 14

7

12

15

CPU_VCCSA_VID<0>

66 93

OUT

CPU_VCCSA_VID<1>

66 93

OUT

CPU_VCCSENSE_P

CPU_VCCSENSE_N

CPU_AXG_SENSE_P

CPU_AXG_SENSE_N

CPU_VCCIOSENSE_P

CPU_VCCIOSENSE_N

TP_CPU_VDDQSENSEP

TP_CPU_VDDQSENSEN

CPU_VCCSASENSE

TP_CPU_DIE_SENSE

CPU_VCC_VALSENSE_P

CPU_VCC_VALSENSE_N

CPU_AXG_VALSENSE_P

CPU_AXG_VALSENSE_N

1

R1314

10K

5%
1/16W
MF-LF

402

2

W17

W15
W12

U17
U15

U12

T16
T14

T11

N18

VCCSA

N16

N14

M17
M15

M12
M11

L18

L14

A50

VIDSOUT

D51

VIDSCLK

B51

VIDALERT*

AE10

VCCSA_VID0

AG10

VCCSA_VID1

B47

VCC_SENSE

A46

VSS_SENSE

F49

VAXG_SENSE

E50

VSSAXG_SENSE

AW10

VCCIO_SENSE

AU10

VSS_SENSE_VCCIO

AY19

VDDQ_SENSE

AW20

VSS_SENSE_VDDQ

K3

VCCSA_SENSE

F47

VCC_DIE_SENSE

D47

VCC_VAL_SENSE

C48

VSS_VAL_SENSE

B49

VAXG_VAL_SENSE

A48

VSSAXG_VAL_SENSE

1

R1313

10K

5%
1/16W
MF-LF
402

2

U1000

IVY-BRIDGE

BGA

(9 OF 11)

(IPU)

VCCIO_SEL

OMIT_TABLE

VSS_NCTF

DC_TEST_A4
DC_TEST_A62
DC_TEST_A64

DC_TEST_B3
DC_TEST_B63
DC_TEST_B65
DC_TEST_BF1

DC_TEST_BF65

DC_TEST_BG2

DC_TEST_BG64

DC_TEST_BH1
DC_TEST_BH3

DC_TEST_BH63
DC_TEST_BH65

DC_TEST_BJ2
DC_TEST_BJ4

DC_TEST_BJ62
DC_TEST_BJ64

DC_TEST_C2
DC_TEST_C64

DC_TEST_D1
DC_TEST_D65

VCCDQ

VCCPLL

VCCPQE

AJ8

AV23

AT23
AP23

AL23

AK65

AK63

AK61

AV21

AT21
AP21

AL21

BJ60

BJ6
BH61

BH5

BE64
BE2

BD65

BD1
F65

F1
E64

E2

B61
B5

A60

A6

A4

A62
A64

B3
B63

B65

BF1
BF65

BG2

BG64
BH1

BH3

BH63
BH65

BJ2
BJ4

BJ62

BJ64
C2

C64

D1
D65

CPU_VCCIO_SEL

TP_DC_TEST_A4

TP_DC_TEST_A62
DC_TEST_B63_A64

DC_TEST_B3_C2

6

DC_TEST_B65_C64

TP_DC_TEST_BF1

TP_DC_TEST_BF65
DC_TEST_BH1_BG2

6

DC_TEST_BG64_BH65

DC_TEST_BH3_BJ2

6

DC_TEST_BJ64_BH63

TP_DC_TEST_BJ4
TP_DC_TEST_BJ62

TP_DC_TEST_D1

TP_DC_TEST_D65

MF-LF

=PP1V5_S3_CPU_VCCDQ

=PP1V8_S0_CPU_VCCPLL_R

=PP1V05_S0_CPU_VCCPQE

6

Pullup for SNB

5%

402

2

7

15

7

14

7 8

14

6

105

7

=PPVCORE_S0_CPU

7

12 14 49

R46
R42

R40

R36
R34

R29

R27 G38
R23

R21
N45

N43

N39
N37

N33

N30
N26

N24

N20
M46

M42
M40

M36

M34
M29

M27

M23
M21

L44

VCC VCC

L40
L38

L34
L32

L28

L26
L22

K45

K43
K41

K37

K35
K31

K29
K25

J44

J40
J38

J34

J32
J28

J26

H45
H43

H41
H37

U1000

IVY-BRIDGE

BGA

(6 OF 11)

CORE POWER

OMIT_TABLE

=PPVCORE_S0_CPU

H35
H31

H29

H25
G44

G40

G34

G32
G28

G26

F45
F43

F41

F37
F35

F31

F29
F25

E44
E40

E38

E34
E32

E28

E26
D45

D43

D41
D37

D35
D31

D29

C44
C40

C38

C34
C32

C28

C26
B45

B43
B41

B37

B35
B31

B29

A44
A40

A38

A34
A32

A28
A26

7

12 14 49

105

C

B

NOTE: Intel validation sense lines per doc 439028 rev1.0

HR_PPDG sections 6.2.1 and 6.3.1.

A

6 3

SYNC_MASTER=K92_MLB

PAGE TITLE

CPU POWER

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=08/03/2010

DRAWING NUMBER

051-9585

REVISION

3.0.0

BRANCH

PAGE

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SHEET

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A

D

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8 7 6 5 4 3

12

BJ56

BJ52
BJ48

BJ40

BJ32
BJ24

BJ20

BJ16

D

C

B

BJ12

BG60
BG56

BG52
BG48

BG44

BG36
BG28

BG24

BG20
BG16

BG12

BE62
BE58

BE54

BE50
BE46

BE42

BE38
BE34

BE30

BE26
BE22

BE18
BE14

BE10

BD35

BC60
BC56

BC52

BC48
BC44

BC40
BC36

BC32

BC28
BC26

BC24

BC20
BC16

BC12

BB65
BB63

BB47
BB39

BA58

BA54

BA50
BA46

BA42

BA38
BA34

BA30
BA26

BA22

BA18
BA14

AY61

AY11

AW56

AW52
AW48

AW44

AW40
AW36

AW32

AW28
AW24

BJ8

BG8
BF5

BD7

BD3

BB9

BB5

AY7

AY3

AY1

U1000

IVY-BRIDGE

BGA

(10 OF 11)

OMIT_TABLE

A

AW16

AV65
AV63

AV59

AV57
AV50

AV44

AV38
AV31

AV25

AV19
AV9

AV5
AU54

AU47

AU41
AU35

AU28

AU22
AU16

AU14

AT61
AT57

AT50
AT44

AT38

AT31
AT25

AT19

AT11
AT7

AT3

AT1
AR54

AR47
AR41

AR35

AR28
AR22

AP65

AP63
AP57

AP50

AP44

VSSVSS

AP38

AP31
AP25

AP19

AP17
AP15

AP12

AP11
AP9

AP5

AN54
AN47

AN41
AN35

AN28

AN22
AM61

AM7

AM3
AM1

AL57

AL50
AL44

AL38
AL31

AL25

AL19
AK16

AK14

AK11
AK9

AK5

AJ64
AJ62

AJ60
AJ57

AH7

AH3
AH1

AG57

AG17
AG15

AG12

AF65
AF63

AF61

AF11

AE57
AD16

AD14

AC64

AC62

AC60
AC57

AB11

AA57

AA17
AA15

AA12

U1000

IVY-BRIDGE

BGA

OMIT_TABLE

(11 OF 11)

AF9

AF5

AD7
AD3

AD1

AB9
AB5

Y65

Y63

Y61

Y7

Y3

Y1
W57

V16

V14
V11

V9

V5

U64

U62
U60

U57

T7

T3

T1

R57
R50

R44
R38

R31

R25
R19

R17

R15
R12

P65

P63
P61

P11

P9

P5

N54
N47

N41

N35
N28

N22

M57
M50

M44
M38

M31

M25
M19

M7

M3

M1

L64

L62
L60

L58
L54

L50

L46
L42

L36

L30
L24

6 3

L20

L16
L12

L8

K39
K33

K27

K1
J64

J60

J56
J52

J48
J46

J42

J36
J30

J24

J22
J18

J14

J10
J6

H39
H33

H27

H3
G62

G58

G54
G50

G46

G42
G36

G30
G24

G20

G16
G12

G8

VSSVSS

F39
F33

F27

E60
E56

E52
E48

E46

E42
E36

E30

E24
E22

E18

E14
E10

E6
E4

D63

D39
D33

D27

C58
C54

C50

C46
C42

C36
C30

C20

C16
C12

C8

B39
B33

B27

A56
A52

A42
A36

A30

A24
A20

A16

A12
A8

=PPVCORE_S0_CPU_VCCAXG

7

12 15

AH65

AH63
AH61

AH58

AH56
AG64

AG62

AG60
AF58

AF56

AE64
AE62

AE60
AD65

AD63

AD61
AD58

AD56

AB65
AB63

AB61

AB58
AB56

AA64
AA62

AA60

VDDQ

BJ36

BJ28
BG40

BG32

BD47
BD43

BD39

BD31
BD23

BB35

AY47
AY43

AY39
AY35

AY31

AY27
AY23

AV46

AV42
AV40

AV36

AV34
AV29

AV27
AU45

AU43

AU39
AU37

AU33

AU30
AU26

AU24

AT46
AT42

AT40
AT36

AT34

AT29
AT27

AR45

AR43
AR39

AR37

AR33
AR30

AR26
AR24

AP46

AP42
AP40

AP36

AP34
AP29

AP27

AN45
AN43

AN39
AN37

AN33

AN30
AN26

AN24

AL46
AL42

AL40

AL36
AL34

AL29
AL27

U1000

IVY-BRIDGE

BGA

OMIT_TABLE

(8 OF 11)

Y58
Y56

W64

W62
W60

V65

V63

VAXG

V61

V58
V56

T65

T63
T61

T58

T56
R64

R62

R60
R55

R53
R48

N64

N62
N60

N58

N56
N52

N49

M65
M63

M61
M59

M55

M53
M48

L56

L52
L48

GRAPHIC CORE POWER

IO POWER DDR3

=PP1V5_S3_CPU_VCCDDR

7

10 15 26

7 9

10 12 13 14

AV55
AV53

AV48

AV17
AV15

AV12
AU58

AU56

AU52
AU49

AU20

AU18
AT55

AT53

AT48
AT17

AT15
AT12

AR58

AR56
AR52

AR49

AR20
AR18

AR16

AR14
AP55

AP53
AP48

AN58

AN56
AN52

AN49

U1000

IVY-BRIDGE

BGA

(7 OF11)
IO POWER

OMIT_TABLE

AN20
AN18

AN16

AN14
AM11

AL55
AL53

AL48

AL17
AL15

AL12

AK58
AK56

AJ17

AJ15
AJ12

AH16

VCCIOVCCIO

AH14

AH11

AF16
AF14

AE17

AE15
AE12

AD11

AC17
AC15

AC12
AB16

AB14

Y16
Y14

Y11

=PP1V05_S0_CPU_VCCIO=PP1V05_S0_CPU_VCCIO

7 9

10 12 13 14

PAGE TITLE

CPU POWER AND GND

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-9585

REVISION

3.0.0

BRANCH

PAGE

14 OF 132

SHEET

13 OF 105

SIZE

D

C

B

A

D

124578

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8 7 6 5 4 3

12

CPU VCORE DECOUPLING

Intel recommendation: 4x 470uF 4mOhm, 16x 22uF 0805, 4x 10uF 0603, 20x 1uF 0402, 8x 1uF 0402 (NOSTUFF)
Apple Implementation: 4x 470uF 4mOhm, 1x 470uF 4mOhm (NOSTUFF), 16x 22uF 0603, 4x 10uF 0402, 20x 1uF 0402, 28x 1uF 0201 (NOSTUFF), 4x 22uF 0603 (NOSTUFF)

=PPVCORE_S0_CPU

7

12 49

105

D

PLACEMENT_NOTE (C1600-C16C7):

Place on bottom side of U1000

Place on bottom side of U1000

Place on bottom side of U100.

Place on bottom side of U1000

1

C1600

2

1UF

10%
10V
X5R
402

1

C1601

1UF

10%
10V

2

X5R
402

1

2

C1602

1UF

10%
10V
X5R
402

1

C1603

1UF

10%
10V

2

X5R
402

1

C1604

1UF

10%
10V

2

X5R
402 402

1

C1605

2

10%
10V
X5R
402

1

2

C1606

1UF

10%
10V
X5R
402

1

C1607

2

1UF

10%
10V
X5R
402

1

C1608

2

1UF

10%
10V
X5R
402

1

2

C1609

1UF

10%
10V
X5R
402

1

2

C1610

1UF

10%
10V
X5R
402

1

C1611

2

1UF

10%
10V
X5R
402

1

C1612

1UF

2

1

C1613

10%
10V
X5R
402

1UF

10%
10V

2

X5R
402

1

C1614

2

1UF

10%
10V
X5R
402

1

C1615

1UF

2

10%
10V
X5R
402

1

C1616

2

1UF

10%
10V
X5R
402

1

C1617

1UF

2

1

C1618

1UF

10%
10V
X5R

10%
10V

2

X5R
402

1

C1619

2

1UF1UF

10%
10V
X5R
402

D

NOSTUFF

1

C16A0

2

1

2

1UF

20%

6.3V
X5R
0201

NOSTUFF

C16C0

1UF

20%

6.3V
X5R
0201

NOSTUFF

1

C16A1

2

1UF

20%

6.3V
X5R
0201

1

C16C1

2

1UF

20%

6.3V
X5R
0201

NOSTUFF

1

C16A2

1UF

20%

6.3V

2

X5R
0201

1

2

NOSTUFF

C16C2

1UF

20%

6.3V
X5R
0201

NOSTUFF

1

C16A3

1UF

2

1

2

20%

6.3V
X5R
0201

NOSTUFFNOSTUFF

C16C3

1UF

20%

6.3V
X5R
0201

NOSTUFF

1

C16A4

1UF

20%

6.3V

2

X5R
0201

1

2

NOSTUFF

C16C4

20%

6.3V
X5R
0201

1

2

NOSTUFF

C16A5

1UF

20%

6.3V
X5R
0201

NOSTUFF

1

C16C5

1UF1UF

20%

6.3V

2

X5R
0201

1

2

1

2

NOSTUFF

C16A6

1UF

20%

6.3V
X5R
0201

NOSTUFF

C16C6

1UF

20%

6.3V
X5R
0201

NOSTUFF NOSTUFF

1

C16A7

1UF

20%

6.3V

2

X5R
0201

NOSTUFF

1

C16C7

1UF

20%

6.3V

2

X5R
0201

1

C16A8

2

1UF

20%

6.3V
X5R
0201

NOSTUFF

1

C16A9

1UF

2

20%

6.3V
X5R
0201

NOSTUFF

1

C16B0

1UF

20%

6.3V

2

X5R
0201

NOSTUFF

1

C16B1

1UF

20%

6.3V

2

X5R
0201

1

2

NOSTUFF

C16B2

1UF

20%

6.3V
X5R
0201

NOSTUFF

1

C16B3

2

1UF

20%

6.3V
X5R
0201

NOSTUFF

1

C16B4

1UF

20%

6.3V

2

X5R
0201

1

2

NOSTUFF

C16B5

1UF

20%

6.3V
X5R
0201

NOSTUFF

1

C16B6

1UF

2

20%

6.3V
X5R
0201

NOSTUFF

1

C16B7

1UF

2

20%

6.3V
X5R
0201

NOSTUFF

1

C16B8

2

1UF

20%

6.3V
X5R
0201

NOSTUFF

1

C16B9

2

1UF

20%

6.3V
X5R
0201

PLACEMENT_NOTE (C1620-C1623):

Place near U1000 on bottom sidePlace near U1000 on bottom side

Place near U1000 on bottom side

Place near U1000 on bottom side

CRITICAL

1

C1620

10UF

20%

6.3V

2

CERM-X5R
0402-1

C

PLACEMENT_NOTE (C1624-C16D5):

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

CRITICAL

1

C1624

22UF 22UF

20%

6.3V

2

X5R-CERM1
0603

CRITICAL

1

C1621

10UF

20%

6.3V

2

CERM-X5R
0402-1

Place near inductors on bottom side.

CRITICAL

1

C1625

22UF

20%

6.3V

2

X5R-CERM1
0603

CRITICAL

1

C1622

10UF

20%

6.3V

2

CERM-X5R
0402-1

CRITICAL

1

2

Place near inductors on bottom side.

CRITICAL

1

C1626

22UF

20%

6.3V

2

X5R-CERM1
0603

1

2

C1623

10UF

20%

6.3V
CERM-X5R
0402-1

CRITICAL

C1627

22UF

20%

6.3V
X5R-CERM1
0603

CRITICAL

1

C1628

20%

6.3V

2

X5R-CERM1
0603

CRITICAL

1

C1629

22UF

20%

6.3V

2

X5R-CERM1
0603

CRITICAL

1

C1630

22UF

20%

6.3V

2

X5R-CERM1
0603

CRITICAL

1

C1631

22UF

20%

6.3V

2

X5R-CERM1
0603

CRITICAL

1

C1632

22UF

20%

6.3V

2

X5R-CERM1
0603

CRITICAL

1

C1633

22UF

20%

6.3V

2

X5R-CERM1
0603

CRITICAL

1

C1634

22UF

20%

6.3V

2

X5R-CERM1
0603

CRITICAL

1

C1635

22UF

20%

6.3V

2

X5R-CERM1
0603

CRITICAL

1

C1636

22UF

20%

6.3V

2

X5R-CERM1
0603

CRITICAL

1

C1637

22UF

20%

6.3V

2

X5R-CERM1
0603

CRITICAL

1

C1638

22UF

20%

6.3V

2

X5R-CERM1
0603

CRITICAL

1

C1639

22UF

20%

6.3V

2

X5R-CERM1
0603

1

2

NOSTUFF

C16D0

22UF

20%

6.3V
X5R-CERM1
0603

NOSTUFF

1

C16D1

22UF

20%

6.3V

2

X5R-CERM1
0603

NOSTUFF

1

C16D2

2

22UF

20%

6.3V
X5R-CERM1
0603

NOSTUFF

1

C16D3

22UF

20%

6.3V

2

X5R-CERM1
0603

NOSTUFF

1

C16D4

2

22UF

20%

6.3V
X5R-CERM1
0603

NOSTUFF

1

C16D5

2

22UF

20%

6.3V
X5R-CERM1
0603

C

PLACEMENT_NOTE (C1640-C1645):

Place near inductors on bottom side.

NOSTUFF

1

C1640

470UF-4MOHM

20%

2.0V

23

POLY-TANT
D2T-SM

CPU VCCIO/VCCPQ DECOUPLING

Intel recommendation: 2x 330uF, 10x 10uF 0603, 26x 1uF 0402
Apple Implementation: 2x 330uF, 10x 10uF 0603, 26x 1uF 0402

PLACEMENT_NOTE (C1646-C1671):

Place on bottom side of U1000

Place on bottom side of U1000

Place on bottom side of U100.

=PP1V05_S0_CPU_VCCIO

7 9

10 12 13

B

Place on bottom side of U1000

1

C1646

2

1

C1659

2

10%
10V
X5R
402

1UF

10%
10V
X5R
402

1

C1647

2

1

C1660

2

CRITICAL CRITICAL

1

C1641

470UF-4MOHM

20%

2.0V

23

POLY-TANT
D2T-SM1

1

C1648

1UF1UF

10%
10V
X5R
402

1UF

10%
10V
X5R
402

1UF

10%
10V

2

X5R
402

1

C1661

1UF

10%
10V

2

X5R
402

1

C1642

470UF-4MOHM

20%

2.0V

23

POLY-TANT
D2T-SM1

1

C1649

1UF

10%
10V

2

X5R
402

1

C1662

1UF

10%
10V

2

X5R
402

1

2

1

2

C1650

1UF

10%
10V
X5R
402

C1663

1UF

10%
10V
X5R
402

CRITICAL

1

C1643

470UF-4MOHM

20%

2.0V

23

POLY-TANT
D2T-SM1

1

2

1

2

C1651

1UF

10%
10V
X5R
402

C1664

1UF

10%
10V
X5R
402

CRITICAL

1

C1644

470UF-4MOHM

20%

2.0V

23

POLY-TANT
D2T-SM1

1

C1652

1UF

10%
10V

2

X5R

1

C1665

1UF

10%
10V

2

X5R
402

1

2

1

C1666

1UF

2

C1653

1UF

10%
10V
X5R
402402

10%
10V
X5R
402

1

C1654

2

1

C1667

2

1UF

10%
10V
X5R
402

1UF

10%
10V

402

1

C1655

1UF

2

1

C1668

1UF

2

CPU VCCPLL DECOUPLING

1

C1656

1UF

10%
10V
X5R
402

10%
10V
X5RX5R
402

2

1

C1669

1UF

2

10%
10V
X5R
402

10%
10V
X5R
402

1

2

1

C1670

2

C1657

1UF

10%
10V
X5R
402

1UF

10%
10V
X5R
402

1

2

1

C1671

2

C1658

1UF

10%
10V
X5R
402

1UF

10%
10V
X5R
402

=PP1V8_S0_CPU_VCCPLL

7

PLACE_NEAR=U1000.AK63:2.54 mm:NO_VIA

R1600

0

1 2

5%
1/16W
MF-LF

402

1

C1685

1UF

10%
10V

2

X5R
402

PLACE_NEAR=U1000.AK65:2.54 mm:NO_VIA

1

2

C1686

1UF

10%
10V
X5R
402

CPU VCCPLL Low pass filter

=PP1V8_S0_CPU_VCCPLL_R

CRITICAL

C1687

1

330UF-0.006OHM

20%
2V
POLY

2

CASE-D2-SM

PLACE_NEAR=U1000.AK61:5 mm

7

12

B

PLACEMENT_NOTE (C1672-C1681):

Place near U1000 on bottom side

Place near U1000 on bottom side

Place near U1000 on bottom side

Place near U1000 on bottom side

Place near U1000 on bottom side

Place near U1000 on bottom side

Place near U1000 on bottom side

Place near U1000 on bottom side

Place near U1000 on bottom side

Place near U1000 on bottom side

CRITICAL

1

C1672

10UF

20%

6.3V

2

X5R
603

Place near inductors on bottom side

Place near inductors on bottom side

C1682

1

330UF-0.006OHM

20%
2V
POLY

2

A

CASE-D2-SM

CRITICAL

CRITICAL

1

C1673

10UF

20%

6.3V

2

X5R
603

CRITICAL

C1683

1

330UF-0.006OHM

20%
2V
POLY

2

CASE-D2-SM

CRITICAL

1

C1674

10UF

20%

6.3V

2

X5R
603

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

R1601

0.010

1 2

1/4W

0603

1%

MF

=PP1V05_S0_CPU_VCCPQE

1

C1684

1UF

10%
10V

2

X5R
402

CRITICAL

1

C1675

10UF

20%

6.3V

2

X5R
603

7 8

12

CRITICAL

1

C1676

10UF

20%

6.3V

2

X5R
603

CRITICAL

1

C1677

10UF

20%

6.3V

2

X5R
603

CRITICAL

1

C1678

10UF

20%

6.3V

2

X5R
603

6 3

CRITICAL

1

C1679

10UF

20%

6.3V

2

X5R
603

CRITICAL

1

C1680

10UF

20%

6.3V

2

X5R
603

CRITICAL

1

C1681

10UF

20%

6.3V

2

X5R
603

SYNC_MASTER=K92_MLB

PAGE TITLE

CPU DECOUPLING-I

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=08/19/2010

DRAWING NUMBER

051-9585

REVISION

3.0.0

BRANCH

PAGE

16 OF 132

SHEET

14 OF 105

124578

SIZE

A

D

www.vinafix.vn

8 7 6 5 4 3

12

VAXG DECOUPLING

Intel recommendation: 2x 470uF 4mOhm, 2x 470uF 4mOhm (NOSTUFF), 6x 22uF 0805, 2x 22uF 0805 (NOSTUFF), 8x 10uF 0603, 2x 10uF 0603 (NOSTUFF), 9x 1uF 0402, 9x 1uF 0402 (NOSTUFF)
Apple Implementation: 2x 470uF 4mOhm, 1x 470uF 4mOhm (NOSTUFF), 6x 22uF 0603, 2x 22uF 0603 (NOSTUFF), 6x 10uF 0402, 2x 10uF 0402 (NOSTUFF), 9x 1uF 0402, 9x 1uF 0402 (NOSTUFF)

=PPVCORE_S0_CPU_VCCAXG

7

12 13

D

C

PLACEMENT_NOTE (C1700-C1708):

Place on bottom side of U1000

Place on bottom side of U1000

Place on bottom side of U100.

Place on bottom side of U1000

1

2

C1700

1UF

10%
10V
X5R
402

1

C1701

2

1UF

10%
10V
X5R
402

PLACEMENT_NOTE (C1718-C1723):

Place close to U1000 on bottom side

Place close to U1000 on bottom side

Place close to U1000 on bottom side

Place close to U1000 on bottom side

Place close to U1000 on bottom side

Place close to U1000 on bottom side

Place close to U1000 on bottom side

Place close to U1000 on bottom side

1

2

C1718

10UF

20%

6.3V
CERM-X5R
0402-1

1

C1719

2

10UF

20%

6.3V
CERM-X5R
0402-1

PLACEMENT_NOTE (C1726-C1731):

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

1

2

C1726

22UF

20%

6.3V
X5R-CERM1
0603

1

C1727

2

22UF

20%

6.3V
X5R-CERM1
0603

PLACEMENT_NOTE (C1734-C1735):

CRITICAL

1

C1734

470UF-4MOHM

20%

2.0V

23

POLY-TANT
D2T-SM1

CRITICAL

1

C1735

470UF-4MOHM

20%

2.0V

23

POLY-TANT
D2T-SM1

1

2

1

2

1

2

C1702

1UF

10%
10V
X5R
402

C1720

10UF

20%

6.3V
CERM-X5R
0402-1

C1728

22UF

20%

6.3V
X5R-CERM1
0603

1

C1703

1UF

10%
10V

2

X5R
402

1

C1721

10UF

20%

6.3V

2

CERM-X5R
0402-1

1

C1729

22UF

20%

6.3V

2

X5R-CERM1
0603

NOSTUFF

CRITICAL

1

C1737

470UF-4MOHM

20%

2.0V

23

POLY-TANT
D2T-SM1

1

2

1

2

1

2

C1704

1UF

10%
10V
X5R
402

C1722

10UF

20%

6.3V
CERM-X5R
0402-1

C1730

22UF

20%

6.3V
X5R-CERM1
0603

1

C1705

2

1

C1723

2

1

2

1UF

10%
10V
X5R
402

10UF

20%

6.3V
CERM-X5R
0402-1

C1731

22UF

20%

6.3V
X5R-CERM1
0603

1

2

1

C1724

10UF

20%

6.3V

2

CERM-X5R
0402-1

C1706

1UF

10%
10V
X5R
402

NOSTUFF

NOSTUFF

1

C1732

22UF

20%

6.3V

2

X5R-CERM1
0603

1

2

1

C1725

2

C1707

1UF

10%
10V
X5R
402

NOSTUFF

10UF

20%

6.3V
CERM-X5R
0402-1

NOSTUFF

1

C1733

22UF

20%

6.3V

2

X5R-CERM1
0603

1

C1708

1UF

10%
10V

2

X5R
402

NOSTUFF

1

C1709

1UF

2

NOSTUFF

1

C1710

1UF

10%
10V
X5R
402

10%
10V

2

X5R
402

NOSTUFF

1

C1711

1UF

2

10%
10V
X5R
402

NOSTUFF

1

C1712

1UF

10%
10V

2

X5R
402

NOSTUFF

1

C1713

2

1UF

10%
10V
X5R
402

NOSTUFF

1

C1714

1UF

2

10%
10V
X5R
402

NOSTUFF

1

C1715

2

1UF

10%
10V
X5R
402

1

2

NOSTUFF

C1716

1UF

10%
10V
X5R
402

NOSTUFF

1

C1717

2

1UF

10%
10V
X5R
402

D

C

CPU VDDQ/VCCDQ DECOUPLING

Intel recommendation: 1x 330uF, 8x 10uF 0603, 10x 1uF 0402
Apple Implementation: 1x 330uF, 8x 10uF 0603, 10x 1uF 0402

=PP1V5_S3_CPU_VCCDDR

7

10 13 26

B

PLACEMENT_NOTE (C1738-C1747):

Place on bottom side of U1000

Place on bottom side of U1000

Place on bottom side of U100.

Place on bottom side of U1000

1

C1738

1UF

10%
10V

2

X5R
402

Place close to U1000 on bottom side

Place close to U1000 on bottom side

Place close to U1000 on bottom side

Place close to U1000 on bottom side

Place close to U1000 on bottom side

Place close to U1000 on bottom side

Place close to U1000 on bottom side

Place close to U1000 on bottom side

1

C1748

10UF

20%

6.3V

2

X5R
603

1

C1739

2

1

C1749

2

1UF

10%
10V
X5R
402

10UF

20%

6.3V
X5R
603

1

2

1

2

Place near inductors on bottom side

C1756

1

330UF-0.006OHM

20%
2V
POLY

2

CASE-D2-SM

C1740

1UF

10%
10V
X5R
402

C1750

10UF

20%

6.3V
X5R
603

1

2

1

C1751

2

C1741

1UF

10%
10V
X5R
402

10UF

20%

6.3V
X5R
603

1

C1742

2

1

C1752

2

1UF

10%
10V
X5R
402

10UF

20%

6.3V
X5R
603

1

C1743

1UF

10%
10V

2

X5R
402

1

C1753

10UF

20%

6.3V

2

X5R
603

1

2

1

C1754

2

C1744

1UF

10%
10V
X5R

10UF

20%

6.3V
X5R
603

1

2

1

C1755

10UF

2

C1745

1UF

10%
10V
X5R
402402

20%

6.3V
X5R
603

1

C1746

1UF

10%
10V

2

402

1

2

C1747

1UF

10%
10V
X5RX5R
402

=PPVCCSA_S0_CPU

7

12

CPU VCCSA DECOUPLING

Intel recommendation: 1x 330uF, 3x 10uF 0603, 3x 1uF 0402
Apple Implementation: 1x 330uF, 5x 10uF 0603, 5x 1uF 0402

PLACEMENT_NOTE (C1758-C1762):

Place on bottom side of U1000

Place on bottom side of U1000

Place on bottom side of U100.

Place on bottom side of U1000

1

C1758

1UF

10%
10V

2

X5R

402

1

C1763

10UF

20%

6.3V

2

X5R
603

1

C1768

330UF-0.006OHM

20%
2V

2

POLY
CASE-D2-SM

1

2

1

2

C1759

1UF

10%
10V
X5R
402

C1764

10UF

20%

6.3V
X5R
603

1

2

1

2

C1760

1UF

10%
10V
X5R
402

C1765

10UF

20%

6.3V
X5R
603

1

2

1

C1766

10UF

20%

6.3V

2

X5R
603

C1761

1UF

10%
10V
X5R
402

1

C1762

2

1

C1767

2

1UF

10%
10V
X5R
402

10UF

20%

6.3V
X5R
603

B

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

R1700

0.010

1 2

1/4W

0603

1%

MF

=PP1V5_S3_CPU_VCCDQ

1

2

C1757

1UF

10%
10V
X5R
402

7

12

A

SYNC_MASTER=K92_MLB

PAGE TITLE

CPU DECOUPLING-II

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=08/19/2010

DRAWING NUMBER

051-9585

REVISION

3.0.0

BRANCH

PAGE

17 OF 132

SHEET

15 OF 105

124578

SIZE

A

D

www.vinafix.vn

8 7 6 5 4 3

12

SYSCLK_CLK32K_RTC

24

IN

RTC_RESET_L

16

PCH_SRTCRST_L

16

PCH_INTRUDER_L

16

PCH_INTVRMEN_L

D

VSel strap not functional (VCCVRM = 1.8V)

C

16

HDA_BIT_CLK_R

16 96

HDA_SYNC_R

16 96

PCH_SPKR

16

HDA_RST_R_L

16 96

HDA_SDIN0

57 96

IN

TP_HDA_SDIN1

6

TP_HDA_SDIN2

6

TP_HDA_SDIN3

6

HDA_SDOUT_R

16 24 96

JTAG_TBT_TMS

16 33

OUT

ENET_MEDIA_SENSE_RDIV

16 24

IN

XDP_PCH_TCK

23

IN

XDP_PCH_TMS

23

IN

XDP_PCH_TDI

23

IN

XDP_PCH_TDO

23

OUT

SPI_CLK_R

47 96

OUT

SPI_CS0_R_L

47 96

OUT

TP_SPI_CS1_L

SPI_MOSI_R

47 96

OUT

SPI_MISO

47 96

IN

=PPVRTC_G3_PCH

1

330K

1/20W

1

R1801

1M

5%

5%
1/20W

MF

MF

201

201

2

2

R1800

B

=PP3V3_SUS_PCH_GPIO
=PP3V3_S0_PCH_GPIO
=PP3V3_T29_PCH_GPIO

R1876
R1877

R1878
R1834

R1833
R1842

R1869
R1844
R1845
R1847

A

R1814
R1815

R1843
R1846
R1848
R1853
R1854
R1855

R1879

A20

OMIT_TABLE

RTCX1

C20

D20

G22

K22

C17

N34

L34

T10

K34

E34
G34

C34

A34

A36

C36

N32

J3

H7

K5

H1

T3

Y14

T1

V4

U3

201

MF

201

MF

MF

201

201
201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF
MF

201

201

201

MF

201

MF

MF

201

RTCX2

RTCRST*

SRTCRST*

INTRUDER*

INTVRMEN

HDA_BCLK

HDA_SYNC

SPKR

(IPD-PLTRST#)

HDA_RST*

HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3

HDA_SDO

HDA_DOCK_EN*/GPIO33
HDA_DOCK_RST*/GPIO13

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

SPI_CLK

SPI_CS0*

SPI_CS1*

SPI_MOSI

SPI_MISO

16

16

16

16

JTAG_TBT_TMS

PCH_SPKR
PCH_SATALED_L

DP_AUXCH_ISOL
SATARDRVR_EN

FW_CLKREQ_L
AP_CLKREQ_L
EXCARD_CLKREQ_L
JTAG_DPMUXUC_TRST_L
ENET_CLKREQ_L
PEG_CLKREQ_L
TBT_CLKREQ_L

PCIECLKRQ0_L_GPIO73
PEGCLKRQA_L_GPIO47
PEGCLKRQB_L_GPIO56
PCH_GPIO11
USB_EXTB_SEL_XHCI
USB_EXTD_SEL_XHCI

ENET_MEDIA_SENSE_RDIV

NC

7

17 20

1

20K

5%

MF

201

2

1

2

7

17 18 19

7

17 18 19 30

7

19

5%

5%

5%

5% MF
5%

5%

5%

5%
5%

5%

5%
5%

5%

5%
5%

5% MF

5%
5%

5%

1

R1803

20K

5%
1/20W
MF
201

2

RTC_RESET_L
PCH_SRTCRST_L
PCH_INTRUDER_L
PCH_INTVRMEN_L

1

C1803

1UF

10%
10V10V

2

X5R
402

1/20W

1/20W

1/20W

1/20W
1/20W

1/20W

1/20W

1/20W
1/20W

1/20W

1/20W
1/20W

1/20W

1/20W

GPU:1P

1/20W

1/20W

1/20W
1/20W

1/20W

R1802

1/20W

C1802

1UF

10%
X5R

402

10K

1 2

4.7K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

2 1

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

Connect to ENET_MEDIA_SENSE via alias if HDA = 3.3V.
Connect to ENET_MEDIA_SENSE via 12K R if HDA = 1.5V.
If HDA = S0, must also ensure that signal cannot be high in S3.

PANTHERPOINT

(IPD-BOOT)

(IPD)
(IPD)
(IPD)
(IPD)

(IPD-BOOT)

(IPD)

(IPU)

(IPU)

(IPD-BOOT)

(IPU)

U1800

MOBILE

FCBGA

(1 OF 10)

RTC

IHDA

JTAG

SPI

FWH4/LFRAME*

(IPU)

LDRQ1*/GPIO23

(IPU)

LPC

SATA

SATA3RCOMPO

SATA0GP/GPIO21
SATA1GP/GPIO19

(IPU)

LPC_AD_R<0>

16

LPC_AD_R<1>

16

LPC_AD_R<2>

16

LPC_AD_R<3>

16

LPC_FRAME_R_L

16

HDA_BIT_CLK_R

16 96

HDA_SYNC_R

16 96

HDA_RST_R_L

16 96

HDA_SDOUT_R

16 24 96

16 33

16

16

23 87

23 41

16 39

16 32

16

16

16 36

8

16 35

16

16

16

16

16 25

16

16 24

LDRQ0*

SERIRQ

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

SATALED*

C38
A38

B37

C37

D36

E36

K36

V5

AM3
AM1

AP7

AP5

AM10
AM8

AP11
AP10

AD7

AD5

AH5
AH4

AB8

AB10

AF3
AF1

Y7

Y5
AD3

AD1

Y3

Y1
AB3

AB1

Y11

Y10

AB12

AB13
AH1

P3

V14
P1

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

(IPU)

SATAICOMPO
SATAICOMPI

SATA3COMPI
SATA3RBIAS

PLACE_NEAR=U1800.N34:1.27mm

PLACE_NEAR=U1800.L34:1.27mm

PLACE_NEAR=U1800.K34:1.27mm

PLACE_NEAR=U1800.A36:1.27mm

16

LPC_AD_R<0>
LPC_AD_R<1>
LPC_AD_R<2>
LPC_AD_R<3>

LPC_FRAME_R_L

TP_LPC_DREQ0_L
TBT_PWR_EN_PCH

LPC_SERIRQ

SATA_HDD_D2R_N
SATA_HDD_D2R_P
SATA_HDD_R2D_C_N
SATA_HDD_R2D_C_P

SATA_ODD_D2R_N
SATA_ODD_D2R_P
SATA_ODD_R2D_C_N
SATA_ODD_R2D_C_P

TP_SATA_C_D2RN
TP_SATA_C_D2RP
TP_SATA_C_R2D_CN
TP_SATA_C_R2D_CP

TP_SATA_D_D2RN
TP_SATA_D_D2RP
TP_SATA_D_R2D_CN
TP_SATA_D_R2D_CP

TP_SATA_E_D2RN
TP_SATA_E_D2RP
TP_SATA_E_R2D_CN
TP_SATA_E_R2D_CP

TP_SATA_F_D2RN
TP_SATA_F_D2RP
TP_SATA_F_R2D_CN
TP_SATA_F_R2D_CP

PCH_SATAICOMP

95

PCH_SATA3COMP

95

PCH_SATA3RBIAS

PCH_SATALED_L

XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL

XDP_DC3_PCH_GPIO19_SATARDRVR_EN

33

R1860
R1861
R1862
R1863
R1864

R1810
R1811
R1812
R1813

1 2

33

1 2

33

1 2

33

1 2

33

1 2

33

1 2

33

1 2

33

1 2

33

1 2

16

16

16

16

16

6

24

OUT

41 95

IN

41 95

IN

41 95

OUT

41 95

OUT

41 95

IN

41 95

IN

41 95

OUT

41 95

OUT

6

6

6

6

6

6

6

6

6

6

6

6

16

5%

1/20W

1/20W

5%

1/20W

5%

1/20W

5%

5%

1/20W

5%

1/20W

1/20W

5%

1/20W

5%

1/20W

5%

ITPCPU_CLK100M_N

10 93

ITPCPU_CLK100M_P

10 93

=PP3V3_S0_PCH

1

R1820

10K

5%
1/20W
MF
201

2

6

45 47

BI

=PP1V05_S0_PCH_VCCIO_SATA

PLACE_NEAR=U1800.Y11:2.54mm

1

R1830

37.4

1%
1/20W
MF
201

2

=PP1V05_S0_PCH

1

R1831

49.9

1%
1/20W
MF
201

2

PLACE_NEAR=U1800.AB12:2.54mm

PLACE_NEAR=U1800.AH1:2.54mm

1

R1832

750

5%

23

OUT
OUT

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

1/20W
MF

23

201

2

LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
LPC_FRAME_L

HDA_BIT_CLK

HDA_SYNC

HDA_RST_L

HDA_SDOUT

NO STUFF

R1841

0

1 2

5%

1/20W

MF

201

7

22

7

20 22

7

22

6

45 47 89 96

BI

6

45 47 89 96

BI

6

45 47 89 96

BI

6

45 47 89 96

BI

6

45 47 89 96

OUT

57 96

OUT

57 96

OUT

57 96

OUT

57 96

OUT

NO STUFF

R1840

0

1 2

5%

1/20W

MF

201

36 96

IN

36 96

IN

36 96

OUT

36 96

OUT

32 96

IN

32 96

IN

32 96

OUT

32 96

OUT

38 96

IN

38 96

IN

38 96

OUT

38 96

OUT

8

IN

8

IN

8

OUT

8

OUT

36 96

OUT

36 96

OUT

16

38 96

OUT

38 96

OUT

16 39

IN

32 96

OUT

32 96

OUT

16 32

IN

8

96

OUT

8

96

OUT

16

IN

6

6

16

OUT

6

6

16 36

IN

6

6

16

75 96

OUT

75 96

OUT

8

16

IN

33 96

OUT

33 96

OUT

16 35

IN

23 93

23 93

PCIE_ENET_D2R_N
PCIE_ENET_D2R_P
PCIE_ENET_R2D_C_N
PCIE_ENET_R2D_C_P

PCIE_AP_D2R_N
PCIE_AP_D2R_P
PCIE_AP_R2D_C_N
PCIE_AP_R2D_C_P

PCIE_FW_D2R_N
PCIE_FW_D2R_P
PCIE_FW_R2D_C_N
PCIE_FW_R2D_C_P

PCIE_EXCARD_D2R_N
PCIE_EXCARD_D2R_P
PCIE_EXCARD_R2D_C_N
PCIE_EXCARD_R2D_C_P

NC_PCIE_5_D2RN
NC_PCIE_5_D2RP
NC_PCIE_5_R2D_CN
NC_PCIE_5_R2D_CP

NC_PCIE_6_D2RN
NC_PCIE_6_D2RP
NC_PCIE_6_R2D_CN
NC_PCIE_6_R2D_CP

NC_PCIE_7_D2RN
NC_PCIE_7_D2RP
NC_PCIE_7_R2D_CN
NC_PCIE_7_R2D_CP

NC_PCIE_8_D2RN
NC_PCIE_8_D2RP
NC_PCIE_8_R2D_CN
NC_PCIE_8_R2D_CP

PCIE_CLK100M_ENET_N
PCIE_CLK100M_ENET_P

PCIECLKRQ0_L_GPIO73

PCIE_CLK100M_FW_N
PCIE_CLK100M_FW_P

FW_CLKREQ_L

PCIE_CLK100M_AP_N
PCIE_CLK100M_AP_P

AP_CLKREQ_L

PCIE_CLK100M_EXCARD_N
PCIE_CLK100M_EXCARD_P

EXCARD_CLKREQ_L

TP_PCIE_CLK100M_PE4N
TP_PCIE_CLK100M_PE4P

JTAG_DPMUXUC_TRST_L

TP_PCIE_CLK100M_PE5N
TP_PCIE_CLK100M_PE5P

ENET_CLKREQ_L

TP_PCIE_CLK100M_PEBN
TP_PCIE_CLK100M_PEBP

PEGCLKRQB_L_GPIO56

PEG_CLK100M_N
PEG_CLK100M_P

PEG_CLKREQ_L

PCIE_CLK100M_TBT_N
PCIE_CLK100M_TBT_P

TBT_CLKREQ_L

ITPXDP_CLK100M_N
ITPXDP_CLK100M_P

Unused clock terminations for FCIM Mode

10K
10K

10K
10K

10K
10K

10K

10K
10K

R1880

10K

GPU:2P

1 2

PCH_CLK96M_DOT_P

16 96

PCH_CLK96M_DOT_N

16 96

PCH_CLK100M_SATA_P

16 96

PCH_CLK100M_SATA_N

16 96

PCIE_CLK100M_PCH_P

16 96

PCIE_CLK100M_PCH_N

5%

1/20W

MF

PEGCLKRQB_L_GPIO56

201

16

16 96

PCH_CLK14P3M_REFCLK

16 96

PCH_CLKIN_GNDP1

16

PCH_CLKIN_GNDN1

16

R1891
R1892

R1893
R1894

R1895
R1896

R1897

R1870
R1871

6 3

24

1 2
1 2

1 2

1 2

1 2

1 2

1 2

1 2
1 2

IN

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

J2

PCIECLKRQ0*/GPIO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

M1

PCIECLKRQ1*/GPIO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2*/GPIO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

A8

PCIECLKRQ3*/GPIO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4*/GPIO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5*/GPIO44

(IPU-RSMRST#)

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

E6

PEG_B_CLKRQ*/GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6*/GPIO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7*/GPIO46

(IPU-RSMRST#)

AK14

CLKOUT_ITPXDP_N

AK13

CLKOUT_ITPXDP_P

SYSCLK_CLK25M_SB

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

OMIT_TABLE

U1800

PANTHERPOINT

MOBILE

FCBGA

(2 OF 10)

SMBUS

SML1ALERT*/PCHHOT*/GPIO74

PCI-E*

C-LINK

Controlled by PCIECLKRQ5#

CLOCKS

FLEX

CLOCKS

R1872

604

1 2

1%
1/16W
MF-LF

402

201

MF

201

MF

MF

201

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

SMBALERT*/GPIO11

SMBCLK

SMBDATA

SML0ALERT*/GPIO60

SML0CLK

SML0DATA

SML1CLK/GPIO58

SML1DATA/GPIO75

(IPU/IPD)

(IPU/IPD)

CL_CLK1

CL_DATA1

CL_RST1*

PEG_A_CLKRQ*/GPIO47

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

CLKOUT_DMI_N
CLKOUT_DMI_P

CLKOUT_DP_N
CLKOUT_DP_P

CLKIN_DMI_N
CLKIN_DMI_P

CLKIN_GND1_N
CLKIN_GND1_P

CLKIN_DOT_96N
CLKIN_DOT_96P

CLKIN_SATA_N
CLKIN_SATA_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0/GPIO64

(IPD-PWROK)

CLKOUTFLEX1/GPIO65

(IPD-PWROK)

CLKOUTFLEX2/GPIO66

(IPD-PWROK)

CLKOUTFLEX3/GPIO67

(IPD-PWROK)

SYSCLK_CLK25M_SB_R

1.8V -> 1.1V

1

R1873

1K

1%
1/20W
MF
201

2

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

E12

H14
C9

A12

C8

G12

C13

E14
M16

M7

T11

P10

M10

AB37
AB38

AV22

AU22

AM12
AM13

BF18

BE18

BJ30
BG30

G24

E24

AK7
AK5

K45

H45

V47

V49

Y47

K43

F47

H47

K49

PCH_GPIO11

SMBUS_PCH_CLK
SMBUS_PCH_DATA

USB_EXTB_SEL_XHCI

SML_PCH_0_CLK
SML_PCH_0_DATA

USB_EXTD_SEL_XHCI

SML_PCH_1_CLK
SML_PCH_1_DATA

TP_CLINK_CLK

TP_CLINK_DATA

TP_CLINK_RESET_L

PEGCLKRQA_L_GPIO47

TP_PCIE_CLK100M_PEGAN
TP_PCIE_CLK100M_PEGAP

DMI_CLK100M_CPU_N
DMI_CLK100M_CPU_P

TP_PCH_CLKOUT_DPN
TP_PCH_CLKOUT_DPP

PCIE_CLK100M_PCH_N
PCIE_CLK100M_PCH_P

PCH_CLKIN_GNDN1
PCH_CLKIN_GNDP1

PCH_CLK96M_DOT_N
PCH_CLK96M_DOT_P

PCH_CLK100M_SATA_N
PCH_CLK100M_SATA_P

PCH_CLK14P3M_REFCLK

PCH_CLK33M_PCIIN

DOES THIS NEED LENGTH MATCH???

SYSCLK_CLK25M_SB_R

NC

=PP1V05_S0_PCH_VCCDIFFCLK

7

20 22

PLACE_NEAR=U1800.Y47:2.54mm

PCH_XCLK_RCOMP

TP_PCH_GPIO64_CLKOUTFLEX0

TP_PCH_GPIO65_CLKOUTFLEX1

TP_PCH_GPIO66_CLKOUTFLEX2

TP_PCH_GPIO67_CLKOUTFLEX3

16

SYNC_DATE=06/02/2011SYNC_MASTER=J31_ANNE

PCH SATA/PCIe/CLK/LPC/SPI

Apple Inc.

R

DRAWING NUMBER

051-9585

REVISION

BRANCH

PAGE

18 OF 132

SHEET

16 OF 105

124578

16

OUT

BI

OUT

OUT

BI

OUT

OUT

BI

6

6

6

16

OUT
OUT

OUT
OUT

IN
IN

16

16

IN
IN

IN
IN

IN

IN

16

R1890

90.9

1/20W

48 96

48 96

16 25

48 96

48 96

16

48 96

48 96

10 93

10 93

8

8

16 96

16 96

16 96

16 96

16 96

16 96

16 96

24 96

1

1%
MF

201

2

3.0.0

D

C

B

8

8

8

8

A

SIZE

D

www.vinafix.vn

8 7 6 5 4 3

12

=PP3V3_SUS_PCH_GPIO
=PP1V05_S0_PCH_VCCIO_PCIE

PLACE_NEAR=U1800.BJ24:12.7mm

1

1

10K

R1900

49.9

1%

5%

1/20W
MF

MF

201

201

2

2

93

93

93

93

93

93

93

93

93

93

93

93

DMI_N2S_N<0>

9

93

IN

DMI_N2S_N<1>

6 9

IN

DMI_N2S_N<2>

6 9

IN

DMI_N2S_N<3>

6 9

IN

DMI_N2S_P<0>

9

93

IN

DMI_N2S_P<1>

6 9

IN

DMI_N2S_P<2>

6 9

IN

DMI_N2S_P<3>

6 9

IN

DMI_S2N_N<0>

6 9

OUT

DMI_S2N_N<1>

6 9

OUT

DMI_S2N_N<2>

9

93

OUT

DMI_S2N_N<3>

6 9

OUT

DMI_S2N_P<0>

6 9

OUT

DMI_S2N_P<1>

6 9

OUT

DMI_S2N_P<2>

9

93

OUT

DMI_S2N_P<3>

6 9

OUT

R1905

1/20W

D

PCH_DMI_COMP

6

24 45

23 45 92

24 92

92

10 26 93

74

17 23 45

45 46 74

46

PCH_DMI2RBIAS

PCH_SUSACK_L

17

PM_SYSRST_L

IN

PM_PCH_SYS_PWROK

IN

PM_PCH_PWROK

IN

PM_PCH_APWROK

IN

PM_MEM_PWRGD

OUT

PM_RSMRST_L

IN

PCH_SUSWARN_L

17

PM_PWRBTN_L

IN

SMC_ADAPTER_EN

IN

PM_BATLOW_L

IN

PLACE_NEAR=U1800.BH21:2.54mm

1

R1920

750

1%
1/20W
MF
201

2

C

PCH_RI_L

=PP3V3_SUS_PCH_GPIO

7

16 17 18 19

PCH_SUSWARN_L

17

B

7

16 17 18 19

7

R1983

10K

1/20W

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK*

K3 B9

SYS_RESET*

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST*

K16

SUSWARN*/SUSPWRDNACK/GPIO30

E20

PWRBTN*

H20

ACPRESENT/GPIO31

(IPD-DeepS4/S5)

E10

BATLOW*/GPIO72

A10

RI*

1

5%
MF

201

R1986

2

0

12

PCH_SUSACK_L

5%

1/20W

MF

201

U1800

PANTHERPOINT

MOBILE

FCBGA

(3 OF 10)

DMI

(IPU)

MANAGEMENT

SYSTEM POWER

(IPU)

(IPU)

17

FDI

FDI_FSYNC0
FDI_FSYNC1

FDI_LSYNC0
FDI_LSYNC1

CLKRUN*/GPIO32

SUS_STAT*/GPIO61

SUSCLK/GPIO62

SLP_S5*/GPIO63

SLP_LAN*/GPIO29

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

FDI_INT

DSWVRMEN

DPWROK

WAKE*

SLP_S4*

SLP_S3*

SLP_A*

SLP_SUS*

PMSYNCH

BJ14

AY14

BE14
BH13

BC12

BJ12
BG10

BG9

BG14

BB14
BF14

BG13
BE12

BG12

BJ10
BH9

AW16

AV12
BC10

AV14

BB10

A18

E22

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

FDI_DATA_N<0>
FDI_DATA_N<1>
FDI_DATA_N<2>
FDI_DATA_N<3>
FDI_DATA_N<4>
FDI_DATA_N<5>
FDI_DATA_N<6>
FDI_DATA_N<7>

FDI_DATA_P<0>
FDI_DATA_P<1>
FDI_DATA_P<2>
FDI_DATA_P<3>
FDI_DATA_P<4>
FDI_DATA_P<5>
FDI_DATA_P<6>
FDI_DATA_P<7>

FDI_INT

FDI_FSYNC<0>
FDI_FSYNC<1>

FDI_LSYNC<0>
FDI_LSYNC<1>

PCH_DSWVRMEN

PM_DSW_PWRGD

PCIE_WAKE_L

PM_CLKRUN_L

LPC_PWRDWN_L

PM_CLK32K_SUSCLK_R

PM_SLP_S5_L

PM_SLP_S4_L

PM_SLP_S3_L

TP_PM_SLP_A_L

PM_SLP_SUS_L

PM_SYNC

MEM_VDD_SEL_1V5_L

IN
IN
IN
IN
IN
IN
IN
IN

IN
IN
IN
IN
IN
IN
IN
IN

OUT

OUT
OUT

OUT
OUT

IN

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

9

93

6 9

93

9

93

9

93

6 9

93

6 9

93

6 9

93

6 9

93

9

93

6 9

93

9

93

9

93

6 9

93

6 9

93

6 9

93

6 9

93

6 9

93

6 9

93

6 9

93

6 9

93

6 9

93

6

17 24 32

6

17 45 47

6

45 47

46

17 45 74

17 26 32 45 74

6

17 26 45 74

17 74

10 93

17

PLACE_NEAR=U1800.AF37:2.54mm

=PPVRTC_G3_PCH

1

R1915

390K

5%
1/20W
MF
201

2

45

IN

1

R1909

100K

5%
1/20W
MF
201

2

7

R1950

2.37K

16 20

1/20W

AF37

AF36

AE48
AE47

AK39
AK40

AN48

AM47

AK47
AJ48

AN47

AM49
AK49

AJ47

AF40

AF39

AH45

AH47
AF49

AF45

AH43
AH49

AF47

AF43

J47

M45

P45

T40

K47

T45
P39

N48

P49
T49

T39

M40

M47

M49

T43

T42

L_BKLTEN
L_VDD_EN

L_BKLTCTL

L_DDC_CLK
L_DDC_DATA

(IPD-PLTRST#)
L_CTRL_CLK
L_CTRL_DATA

LVD_IBG
LVD_VBG

LVD_VREFH
LVD_VREFL

LVDSA_CLK*
LVDSA_CLK

LVDSA_DATA0*
LVDSA_DATA1*
LVDSA_DATA2*
LVDSA_DATA3*

LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3

LVDSB_CLK*
LVDSB_CLK

LVDSB_DATA0*
LVDSB_DATA1*
LVDSB_DATA2*
LVDSB_DATA3*

LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

CRT_BLUE
CRT_GREEN
CRT_RED

CRT_DDC_CLK
CRT_DDC_DATA

CRT_HSYNC
CRT_VSYNC

DAC_IREF
CRT_IRTN

LVDS_IG_BKL_ON

8

17

OUT

LVDS_IG_PANEL_PWR

8

17

OUT

LVDS_IG_BKL_PWM

8

OUT

LVDS_IG_DDC_CLK

86

OUT

LVDS_IG_DDC_DATA

86

OUT

TP_LVDS_IG_CTRL_CLK

6

TP_LVDS_IG_CTRL_DATA

6

PCH_LVDS_IBG
TP_PCH_LVDS_VBG

1

1%
MF

201

2

6

LVDS_IG_A_CLK_N

89 95

OUT

LVDS_IG_A_CLK_P

89 95

OUT

LVDS_IG_A_DATA_N<0>

89 95

OUT

LVDS_IG_A_DATA_N<1>

89 95

OUT

LVDS_IG_A_DATA_N<2>

89 95

OUT

LVDS_IG_A_DATA_N<3>

8

95

OUT

LVDS_IG_A_DATA_P<0>

89 95

OUT

LVDS_IG_A_DATA_P<1>

89 95

OUT

LVDS_IG_A_DATA_P<2>

89 95

OUT

LVDS_IG_A_DATA_P<3>

8

95

OUT

LVDS_IG_B_CLK_N

8

OUT

LVDS_IG_B_CLK_P

8

OUT

LVDS_IG_B_DATA_N<0>

89 95

OUT

LVDS_IG_B_DATA_N<1>

89 95

OUT

LVDS_IG_B_DATA_N<2>

89 95

OUT

LVDS_IG_B_DATA_N<3>

8

OUT

LVDS_IG_B_DATA_P<0>

89 95

OUT

LVDS_IG_B_DATA_P<1>

89 95

OUT

LVDS_IG_B_DATA_P<2>

89 95

OUT

LVDS_IG_B_DATA_P<3>

8

OUT

TP_CRT_IG_BLUE

6

TP_CRT_IG_GREEN

6

TP_CRT_IG_RED

6

TP_CRT_IG_DDC_CLK

6

TP_CRT_IG_DDC_DATA

6

TP_CRT_IG_HSYNC

6

TP_CRT_IG_VSYNC

6

PCH_DAC_IREF

PLACE_NEAR=U1800.T43:2.54mm

1

R1951

1K

5%
1/20W
MF
201

2

OMIT_TABLE

OMIT_TABLE

U1800

PANTHERPOINT

MOBILE

FCBGA

(4 OF 10)

LVDS

CRT

(IPD)
(IPD)

(IPD)
(IPD)

(IPD)
(IPD)

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

AP43

AP45

AM42

AM40

AP39
AP40

P38
M39

AT49

AT47
AT40

AV42

AV40

AV45
AV46

AU48

AU47
AV47

AV49

P46

P42

AP47
AP49

AT38

AY47

AY49
AY43

AY45
BA47

BA48

BB47
BB49

M43
M36

AT45

AT43

BH41

BB43

BB45

BF44
BE44

BF42

BE42
BJ42

BG42

SDVO_TVCLKINN
SDVO_TVCLKINP

SDVO_STALLN
SDVO_STALLP

SDVO_INTN
SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

(IPD-PLTRST#)

DDPB_AUXN
DDPB_AUXP

DDPB_HPD

DDPC_CTRLCLK

DDPC_CTRLDATA

(IPD-PLTRST#)

DDPC_AUXN
DDPC_AUXP

DDPC_HPD

DIGITAL DISPLAY INTERFACE

DDPD_CTRLCLK

DDPD_CTRLDATA

(IPD-PLTRST#)

DDPD_AUXN
DDPD_AUXP

DDPD_HPD

TP_SDVO_TVCLKINN
TP_SDVO_TVCLKINP

TP_SDVO_STALLN
TP_SDVO_STALLP

TP_SDVO_INTN
TP_SDVO_INTP

DPA_IG_DDC_CLK
DPA_IG_DDC_DATA

DPA_IG_AUX_CH_N
DPA_IG_AUX_CH_P
DPA_IG_HPD

TP_DP_IG_B_MLN<0>
TP_DP_IG_B_MLP<0>
TP_DP_IG_B_MLN<1>
TP_DP_IG_B_MLP<1>
TP_DP_IG_B_MLN<2>
TP_DP_IG_B_MLP<2>
TP_DP_IG_B_MLN<3>
TP_DP_IG_B_MLP<3>

DPB_IG_DDC_CLK
DPB_IG_DDC_DATA

DPB_IG_AUX_CH_N
DPB_IG_AUX_CH_P
DPB_IG_HPD

TP_DP_IG_C_MLN<0>
TP_DP_IG_C_MLP<0>
TP_DP_IG_C_MLN<1>
TP_DP_IG_C_MLP<1>
TP_DP_IG_C_MLN<2>
TP_DP_IG_C_MLP<2>
TP_DP_IG_C_MLN<3>
TP_DP_IG_C_MLP<3>

TP_DP_IG_D_CTRL_CLK
TP_DP_IG_D_CTRL_DATA

TP_DP_IG_D_AUXN
TP_DP_IG_D_AUXP
TP_DP_IG_D_HPD

TP_DP_IG_D_MLN<0>
TP_DP_IG_D_MLP<0>
TP_DP_IG_D_MLN<1>
TP_DP_IG_D_MLP<1>
TP_DP_IG_D_MLN<2>
TP_DP_IG_D_MLP<2>
TP_DP_IG_D_MLN<3>
TP_DP_IG_D_MLP<3>

6

6

6

6

6

6

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

D

C

B

=PP3V3_SUS_PCH_GPIO
=PP3V3_S0_PCH_GPIO
=PP3V3_S5_PCH

R1985
R1991

A

R1982
R1925

R1924
R1921
R1922
R1923

R1981
R1984

8.2K

10K

100K
100K
100K
100K

100K
100K

1K

1K

1 2

1 2

1 2

1 2

2 1
2 1
2 1
2 1

2 1
2 1

7

16 17 18 19

7

16 18 19 30

7

5%

5%

5%

5%

5%

5%

5%
5%

5%

5%

1/20W

1/20W

1/20W

1/20W

1/20W

1/20W

1/20W
1/20W

1/20W

1/20W

MF

MF

MF

MF

MF

MF

MF
MF

MF

MF

PM_PWRBTN_L

201

PM_CLKRUN_L

201

MEM_VDD_SEL_1V5_L

201

PCIE_WAKE_L

201

MAKE_BASE=TRUE

PM_SLP_S3_L

201

PM_SLP_S4_L

201

PM_SLP_S5_L

201

PM_SLP_SUS_L

201

LVDS_IG_BKL_ON

201

LVDS_IG_PANEL_PWR

201

17 23 45

6

17 45 47

17

6

17 24 32

=TBT_WAKE_L

6

17 26 45 74

17 26 32 45 74

17 45 74

17 74

8

17

8

17

87

IN

6 3

SYNC_MASTER=J5_MLB

PAGE TITLE

PCH DMI/FDI/PM/Graphics

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=05/26/2011

DRAWING NUMBER

051-9585

REVISION

3.0.0

BRANCH

PAGE

19 OF 132

SHEET

17 OF 105

124578

SIZE

A

D

www.vinafix.vn

8 7 6 5 4 3

12

OMIT_TABLE

BG26
BJ26

BH25

BJ16
BG16

AH38

AH37
AK43

AK45

AH12

AB46

AB45

AY16

BG46

BE28
BC30

BE32

BJ32

BC28
BE30

BF32
BG32

AV26
BB26

AU28

AY30

AU26
AY26

AV28

AW30

C18

N30

H3

AM4

AM5
Y13

K24

L24

B21
M20

K40

K38
H38

G38

C46

C44

E40

D47
E42

F46

G42

G40

C42
D44

K10

C6

H49

H43
J48

K42

H40

TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20

TP21
TP22
TP23
TP24

USB3RN1
USB3RN2
USB3RN3
USB3RN4

USB3RP1
USB3RP2
USB3RP3
USB3RP4

USB3TN1
USB3TN2
USB3TN3
USB3TN4

USB3TP1
USB3TP2
USB3TP3
USB3TP4

PIRQA*
PIRQB*
PIRQC*
PIRQD*

REQ1*/GPIO50
REQ2*/GPIO52
REQ3*/GPIO54

GNT1*/GPIO51
GNT2*/GPIO53
GNT3*/GPIO55

PIRQE*/GPIO2
PIRQF*/GPIO3
PIRQG*/GPIO4
PIRQH*/GPIO5

PME*

PLTRST*

CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4

(IPU-PCIERST#)

(IPU)

(IPD)

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

D

TP_PCH_TP23

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

NC
NC

NC

USB3_EXTA_RX_N

6

42 95

IN

USB3_EXTB_RX_N

6

43 95

IN

USB3_EXTC_RX_N

8

IN

USB3_EXTD_RX_N

8

C

=PP3V3_S0_PCH_GPIO

7

16 17 18 19 30

R2010
R2011
R2012
R2013

B

R2054

=PP3V3_SUS_PCH_GPIO
=PP3V3_S3_PCH_GPIO
=PP3V3_S0_PCH_GPIO

R2016
R2017
R2018

R2030

R2014
R2031

A

R2033

R2069
R2060

R2061
R2062
R2068

R2067

10K
10K
10K

10K

10K
10K

10K

10K

10K
10K
10K
10K

10K

1 2

1 2

1 2

1 2

NO STUFF

1 2

1 2

NO STUFF

1 2

1 2

1 2
1 2

1 2
1 2

2 1

7

16 17 19

24

7

16 17 18 19 30

JTAG_GMUX_TMS

MF

5%

1/20W
1/20W

5%

1/20W

1/20W

5%

1/20W

5%

1/20W

Redundant to pull-up on audio page

5%

1/20W

1/20W

5%

1/20W

5%

1/20W

5% MF

1/20W

5%

1/20W

5%

1/20W

5%

201

BLC_I2C_MUX_SEL

201

MF5%

USE_HDD_OOB_L

MF

201

BLC_GPIO

MF5%

201

Redundant to pull-up on audio page

XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

AUD_IP_PERIPHERAL_DET

MF

201

TBT_PWR_REQ_L

MF

201

AUD_I2C_INT_L

MF

201

201

MF

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L

MF

201

XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L

201

XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L

MF

201

XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L

201

MF

AP_PWR_EN

MF

201

10K
10K
10K
10K

10K

1 2

1 2

1 2
1 2

NO STUFF

2 1

18 89

18

18

18

18 63

18 87

18 63

23 32 74

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

1/20W

5%

18 23

18 23

18 23

18 23

18 23

IN

6

42 95

IN

6

43 95

IN

8

IN

8

IN

6

42 95

OUT

6

43 95

OUT

8

OUT

8

OUT

6

42 95

OUT

6

43 95

OUT

8

OUT

8

OUT

MF

201

MF

201

MF

201

MF

201

18 89

OUT

18

OUT

18

OUT

201

MF

18

IN

18 63

IN

18 87

IN

18 63

IN

6

24 26

OUT

24 96

OUT

24

OUT

24

6 7

24

OUT

USB3_EXTA_RX_P
USB3_EXTB_RX_P
USB3_EXTC_RX_P
USB3_EXTD_RX_P

USB3_EXTA_TX_N
USB3_EXTB_TX_N
USB3_EXTC_TX_N
USB3_EXTD_TX_N

USB3_EXTA_TX_P
USB3_EXTB_TX_P
USB3_EXTC_TX_P
USB3_EXTD_TX_P

PCI_INTA_L
PCI_INTB_L
PCI_INTC_L
PCI_INTD_L

JTAG_GMUX_TMS
BLC_I2C_MUX_SEL
USE_HDD_OOB_L

TP_PCH_STRP_BBS1
TP_PCH_STRP_ESI_L
PCH_STRP_TOPBLK_SWP_L

BLC_GPIO
AUD_IP_PERIPHERAL_DET
TBT_PWR_REQ_L
AUD_I2C_INT_L

TP_PCI_PME_L

PLT_RESET_L

LPC_CLK33M_SMC_R
LPC_CLK33M_LPCPLUS_R
TP_PCI_CLK33M_OUT2
TP_PCI_CLK33M_OUT3
PCH_CLK33M_PCIOUT

U1800

PANTHERPOINT

MOBILE

FCBGA

(5 OF 10)

USB

PCI

USBRBIAS*

OC0*/GPIO59
OC1*/GPIO40
OC2*/GPIO41
OC3*/GPIO42
OC4*/GPIO43

OC5*/GPIO9
OC6*/GPIO10
OC7*/GPIO14

6 3

RSVD1
RSVD2
RSVD3
RSVD4

RSVD5
RSVD6

RSVD7
RSVD8

RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22

RSVD23
RSVD24

RSVD25

RSVD26
RSVD27

RSVD28
RSVD29

USBP0N
USBP0P

USBP1N
USBP1P

USBP2N
USBP2P

USBP3N
USBP3P

USBP4N
USBP4P

USBP5N
USBP5P

USBP6N
USBP6P

USBP7N
USBP7P

USBP8N
USBP8P

USBP9N
USBP9P

USBP10N
USBP10P

USBP11N
USBP11P

USBP12N
USBP12P

USBP13N
USBP13P

(IPD)

USBRBIAS

AY7

NC

AV7

NC

AU3

NC

BG4

NC

AT10

NC

BC8

NC

AU2

NC

AT4

NC

AT3

NC

AT1

NC

AY3

NC

AT5

NC

AV3

NC

AV1

NC

BB1

NC

BA3

NC

BB5

NC

BB3

NC

BB7

NC

BE8

NC

BD4

NC

BF6

NC

AV5

NC

AV10

NC

AT8

NC

AY5

NC

BA2

NC

AT12

NC

BF3

NC

C24
A24

C25

B25

C26

A26

K28

H28

E28

D28

C28
A28

C29

B29

N28
M28

L30

K30

G30

E30

C30
A30

L32

K32

G32
E32

C32

A32

C33

B33

A14

K20
B17

C16

L16
A16

D14

C14

USB_EXTA_N
USB_EXTA_P

USB_EXTB_XHCI_N
USB_EXTB_XHCI_P

USB_EXTC_N
USB_EXTC_P

USB_EXTD_XHCI_N
USB_EXTD_XHCI_P

TP_USB_4N
TP_USB_4P

TP_USB_SDN
TP_USB_SDP

TP_USB_WLANN
TP_USB_WLANP

USB_HUB_UP_N
USB_HUB_UP_P

USB_CAMERA_N
USB_CAMERA_P

USB_EXTB_EHCI_N
USB_EXTB_EHCI_P

USB_EXTD_EHCI_N
USB_EXTD_EHCI_P

TP_USB_BT_HSN
TP_USB_BT_HSP

TP_USB_12N
TP_USB_12P

TP_USB_13N
TP_USB_13P

PCH_USB_RBIAS

95

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L
XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L
XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L
XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L
XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L
XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L
XDP_DB2_PCH_GPIO10_AP_PWR_EN
XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

D

42 95

BI

42 95

BI

25 95

BI

25 95

BI

8

95

BI

8

95

BI

25 95

BI

25 95

BI

Ext A (XHCI/EHCI)

Ext B (XHCI)

Ext C (XHCI/EHCI)

Ext D (XHCI) (Mobiles: Trackpad?)

C

Unused

RSVD: SD

RSVD: WiFi

25 95

BI

25 95

BI

32 95

BI

32 95

BI

25 95

BI

25 95

BI

8

BI

8

BI

USB Hub (All LS/FS Devices)

Camera

Ext B (EHCI)

Ext D (EHCI)

RSVD: BT (HS)

Unused

B

Unused

PLACE_NEAR=U1800.B33:2.54mm

1

R2070

2

22.6

1%
1/20W
MF
201

PAGE TITLE

PCH PCI/USB/TP/RSVD

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=06/02/2011SYNC_MASTER=J31_ANNE

DRAWING NUMBER

051-9585

REVISION

BRANCH

PAGE

20 OF 132

SHEET

18 OF 105

3.0.0

SIZE

A

D

18 23

IN

18 23

IN

18 23

IN

18 23

IN

23

IN

23

IN

23

OUT

18 23

IN

124578

www.vinafix.vn

8 7 6 5 4 3

BOM GROUP

RAMCFG_SLOT

BOM OPTIONS

RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H

12

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

Systems with no chip-down memory should pull all 4 RAMCFG GPIOs high.

Systems with chip-down memory should add pull-downs on another page and set straps per software.

=PP3V3_S0_PCH_GPIO

7

16 17 18 19 30

RAMCFG3:H

R2172

D

XDP_FC1_PCH_GPIO0

19 23

FW_PME_L

8

19 39

IN

DPMUX_UC_IRQ

8

19

IN

SMC_RUNTIME_SCI_L

19 45

IN

TP_PCH_GPIO8

WOL_EN

19 74

OUT

XDP_FC0_PCH_GPIO15

23 68

IN

XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH

23

OUT

LPCPLUS_GPIO

6

19 47

BI

ODD_PWR_EN_L

19 41

OUT

PCH_GPIO24

19

(PU necessary?)

SMC_SCI_L

19 46

XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L

23

0

35

TBT_SW_RESET_L

OUT

R2180

1 2

C

OUT

TBT_SW_RESET_R_L

19

5%

1/20W

MF

201

XDP_DC1_PCH_GPIO35_MXM_GOOD

23

OUT

XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL

19 23

OUT

XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK

23

OUT

JTAG_ISP_TDO

8

19 89

IN

JTAG_ISP_TDI

8

89

OUT

FW_PWR_EN_PCH

19 24

OUT

XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH

23

OUT

SPIROM_USE_MLB

6

19 47 56

BI

T7

BMBUSY*/GPIO0

A42

TACH1/GPIO1

H36

TACH2/GPIO6

E38

TACH3/GPIO7

C10

GPIO8

(IPU-RSMRST#)

C4

LAN_PHY_PWR_CTRL/GPIO12

G2

GPIO15

(IPU)

SATA4GP/GPIO16

TACH0/GPIO17

SCLOCK/GPIO22

GPIO24

GPIO27

(IPU-DeepS4/S5)

GPIO28

(IPU-RSMRST#)

STP_PCI*/GPIO34

GPIO35

SATA2GP/GPIO36

(IPD-PLTRST#)

SATA3GP/GPIO37

(IPD-PLTRST#)

SLOAD/GPIO38

SDATAOUT0/GPIO39

SDATAOUT1/GPIO48

SATA5GP/GPIO49/TEMP_ALERT*

GPIO57

VSS_NCTF_0
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13

BD49

BE49

BF49

U2

D40

T5

E8

E16

P8

K1

K4

V8

M5

N2

M3

V13

V3

D6

A4

A44

A45
A46

A5
A6

B3

B47
BD1

BE1

BF1

OMIT_TABLE

U1800

PANTHERPOINT

MOBILE

FCBGA

(6 OF 10)

NCTF

(IPD-PLTRST#?)

CPU/MISC

GPIO

TACH4/GPIO68

TACH5/GPIO69

TACH6/GPIO70

TACH7/GPIO71

A20GATE

PECI

(IPD)

RCIN*

PROCPWRGD

THRMTRIP*

INIT3_3V*

(IPU)

DF_TVS

TS_VSS1
TS_VSS2
TS_VSS3
TS_VSS4

NC_1

VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31

C40

B41

C41

A40

P4

AU16

P5

AY11

AY10

T14

AY1

AH8

AK11
AH10

AK10

P37

BG2
BG48

BH3

BH47
BJ4

BJ44

BJ45
BJ46

BJ5
BJ6

C2

C48
D1

D49

E1
E49

F1

F49

NC

MLB_RAMCFG3

MLB_RAMCFG2

MLB_RAMCFG1

MLB_RAMCFG0

PCH_A20GATE

PCH_PECI

PCH_RCIN_L

PCH_PROCPWRGD

PM_THRMTRIP_L_R

46

PCH_INIT3V3_L

PCH_DF_TVS

NO STUFF

R2130

1/20W

1/20W

19

19

1

1K

This has internal pull up and should not pulled low.

5%

THIS SIGNAL IS INTENDED FOR FIRMWARE HUB AND WE ARE NOT USING IT.

MF

201

2

10K

5%

MF

201

R2170

R2140

R2156

1

2

RAMCFG2:H

1

R2173

10K

5%
1/20W
MF
201

2

43

0

390

NO STUFF

1 2

1 2

1 2

RAMCFG1:H RAMCFG0:H

1

R2174

10K

5%

1/20W

MF

201

2

CPU_PECI

5%

1/20W

MF

201

CPU_PWRGD

5%

1/20W

MF

201

PM_THRMTRIP_L

5%

1/20W

MF

201

1

R2175

10K

5%
1/20W
MF
201

2

BI

OUT

ININ

10 46 93

10 23 93

10 46 93

=PP1V8_S0_PCH_VCC_DFTERM

1

R2179

2.2K

5%
1/20W
MF

R2178

1K

1/20W

201

201

2

12

CPU_PROC_SEL_L

5%

DF_TVS:DMI & FDI Term Voltage

MF

Set to Vss when Low
Set to Vcc when High

10 93

D

7

20 22

C

SIZE

B

A

D

B

=PP3V3_S5_PCH_GPIO
=PP3V3_SUS_PCH_GPIO
=PP3V3_S0_PCH_GPIO
=PP3V3_T29_PCH_GPIO

R2186
R2199

R2160
R2185
R2196
R2190

R2197
R2184

R2150
R2155

A

R2194
R2192
R2193

R2191
R2111

R2195
R2112
R2198
R2113
R2116

10K
10K

10K
10K
10K

100K

10K
10K

10K
10K

10K
10K

100K

10K

20K

100K

10K
10K
10K
10K

1 2
1 2

1 2

1 2

1 2
1 2

NO STUFF

1 2
1 2

1 2

1 2

1 2

1 2
1 2

1 2

2 1
2 1
2 1
2 1
2 1
2 1

7

7

16 17 18

7

16 17 18 19 30

7

16

JTAG_ISP_TDO

MF

1/20W

5%

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

1/20W

5%

Must stuff R2197 when R2180 NO STUFFed.

5%

1/20W

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

1/20W

5%

201

JTAG_TBT_TDI

MF

201

XDP_FC1_PCH_GPIO0

MF

201

FW_PME_L

MF

201

SMC_RUNTIME_SCI_L

MF

201

LPCPLUS_GPIO

MF

201

TBT_SW_RESET_R_L

MF

201

FW_PWR_EN_PCH

MF5%

201

PCH_A20GATE

MF

201

PCH_RCIN_L

MF

201

WOL_EN

MF

201

PCH_GPIO24

MF

201

SPIROM_USE_MLB

MF

201

SMC_SCI_L

MF

201

DPMUX_UC_IRQ

MF

201

AUD_IPHS_SWITCH_EN_PCH

MF

201

ODD_PWR_EN_L

MF

201

XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL

MF

201

JTAG_ISP_TCK

MF

201

ENET_LOW_PWR_PCH

201

MF

8

8

8

19 45

6

19

19 24

19

19

19 74

19

6

19 46

8

23 24

19 41

19 23

8

23 24

19 89

33

19 39

19 47

19 47 56

19

23

R2181

2 1

5%

1/20W

MF

SPIROM_USE_MLB

201

6

19 47 56 19 23

NO STUFF

10K

6 3

SYNC_MASTER=J31_ANNE SYNC_DATE=06/02/2011

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

PCH GPIO/MISC/NCTF

Apple Inc.

R

DRAWING NUMBER

051-9585

REVISION

BRANCH

PAGE

21 OF 132

SHEET

19 OF 105

3.0.0

124578

www.vinafix.vn

8 7 6 5 4 3

12

D

OMIT_TABLE

AD49

VCCACLK pin left as NC per DG

=PP3V3_S5_PCH_VCCDSW

7

22

NC

TP_PPVOUT_PCH_DCPSUSBYP

PP3V3_S0_PCH_VCC3_3_CLK_F

22

VCCAPLLDMI2 pin left as NC per DG

=PP1V05_S0_PCH_VCCIO_CLK

7

20 22

AL24 left as NC per DG

=PP1V05_S0_PCH_VCCASW

7

20 22

NC

NC

C

PLACE_NEAR=U1800.N16:2.54mm

B

PCH output, for decoupling only

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

1

C2210

0.1UF

20%
10V

2

CERM

402

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

1

C2222

0.1UF

PLACE_NEAR=U1800.V16:2.54mm

20%
10V

2

CERM

402

PPVOUT_G3_PCH_DCPRTC

=PP1V8R1V5_S0_PCH_VCCVRM

7

20

PP1V05_S0_PCH_VCCADPLLA_F

22

PP1V05_S0_PCH_VCCADPLLB_F

22

=PP1V05_S0_PCH_VCCIO_CLK

7

20 22

=PP1V05_S0_PCH_VCCDIFFCLK

7

16 22

55mA Max, 5mA Idle

=PP1V05_S0_PCH_VCCSSC

7

22

PPVOUT_S0_PCH_DCPSST

=PP1V05_S0_PCH_V_PROC_IO

7

22

=PPVRTC_G3_PCH

7

16 17

C2231

PLACE_NEAR=U1800.A22:2.54mm

NC-ed per DG

1

1UF

10%

6.3V
2

CERM

402

NC
NC

1

C2232

0.1UF

20%
10V

2

CERM
402

PLACE_NEAR=U1800.A22:2.54mm

VCCACLK

T16

VCCDSW3_3

V12

DCPSUSBYP

T38

VCC3_3_5_CLK

BH23

VCCAPLLDMI2

AL29

VCCIO_14_PLLCLK

AL24

DCPSUS_3_CLK

AA19

VCCASW_1_CLK

AA21

VCCASW_2_CLK

AA24

VCCASW_3_CLK

AA26

VCCASW_4_CLK

AA27

VCCASW_5_CLK

AA29

VCCASW_6_CLK

AA31

VCCASW_7_CLK

AC26

VCCASW_8_CLK

AC27

VCCASW_9_CLK

AC29

VCCASW_10_CLK

AC31

VCCASW_11_CLK

AD29

VCCASW_12_CLK

AD31

VCCASW_13_CLK

W21

VCCASW_14_CLK

W23

VCCASW_15_CLK

W24

VCCASW_16_CLK

W26

VCCASW_17_CLK

W29

VCCASW_18_CLK

W31

VCCASW_19_CLK

W33

VCCASW_20_CLK

N16

DCPRTC

Y49

VCCVRM_4_CLK

BD47

VCCADPLLA

BF47

VCCADPLLB

AF17

VCCIO_7_CLK

AF33

VCCDIFFCLKN

AF34

VCCDIFFCLKN

AG34

VCCDIFFCLKN

AG33

VCCSSC

V16

DCPSST

T17

DCPSUS_1_CLK

V19

DCPSUS_2_CLK

BJ8

V_PROC_IO

A22

VCCRTC

1

C2233

0.1UF

20%
10V

2

CERM
402

PLACE_NEAR=U1800.A22:2.54mm

U1800

PANTHERPOINT

MOBILE

FCBGA

(8 OF 10)

CLK/MISC

CPURTC

VCCIO_29_USB
VCCIO_30_USB
VCCIO_31_USB
VCCIO_32_USB
VCCIO_33_USB

VCCSUS3_3_7_USB
VCCSUS3_3_8_USB
VCCSUS3_3_9_USB

VCCSUS3_3_10_USB

VCCSUS3_3_6_USB

VCCIO_34_PLLUSB

V5REF_SUS

USB

DCPSUS_4_USB

VCCSUS3_3_1_USB

V5REF

VCCSUS3_3_2_GPIO
VCCSUS3_3_3_GPIO
VCCSUS3_3_4_GPIO
VCCSUS3_3_5_GPIO

VCC3_3_1_GPIO
VCC3_3_8_GPIO

LPC

VCC3_3_4_GPIO

PCI/GPIO/

VCC3_3_2_SATA

VCCIO_5_PLLSATA

VCCIO_12_SATA3
VCCIO_13_SATA3

VCCIO_6_PLLSATA3

VCCAPLLSATA

SATAMISC

VCCVRM_1_SATA

VCCIO_2_SATA
VCCIO_3_SATA
VCCIO_4_SATA

VCCASW_22_MISC
VCCASW_23_MISC
VCCASW_21_MISC

VCCSUSHDA

HDA

N26

=PP1V05_S0_PCH_VCCIO_USB

P26
P28

T27
T29

T23

=PP3V3_SUS_PCH_VCCSUS_USB

T24

V23
V24

P24

T26

=PP1V05_S0_PCH_VCCIO_PLLUSB

M26

=PP5V_SUS_PCH_V5REFSUS

AN23

AN24

P34

N20

N22

P20
P22

AA16

W16
T34

AJ2

AF13

AH13

AH14

AF14

AK1

AF11

AC16

AC17

AD17

T21

V21

T19

P32

NC-ed per DG

NC

=PP3V3_SUS_PCH_VCCSUS

=PP5V_S0_PCH_V5REF

=PP3V3_SUS_PCH_VCCSUS_GPIO

=PP3V3_S0_PCH_VCC3_3_GPIO

=PP3V3_S0_PCH_VCC3_3_SATA

=PP1V05_S0_PCH_VCCIO_SATA

VCCAPLLSATA pin left as NC per DG

NC

=PP1V8R1V5_S0_PCH_VCCVRM

=PP1V05_S0_PCH_VCCIO_SATA

=PP1V05_S0_PCH_VCCASW

=PP3V3R1V5_S0_PCH_VCCSUSHDA

10 mA Max, 1mA Idle

7

22

7

22

7

22

7

22

22

7

22

7

22

7

22

7

16 20 22

7

20

7

16 20 22

7

20 22

7

22 24

VCCAFDIPLL pin left as NC per DG

=PP1V05_S0_PCH_VCC_CORE

7

22

1.44 A Max, 474mA Idle

=PP1V05_S0_PCH_VCCIO_PLLPCIE

7

TP_1V05_S0_PCH_VCCAPLLEXP

6

=PP1V05_S0_PCH_VCCIO

7

22

=PP3V3_S0_PCH_VCC3_3_PCI

7

22

=PP1V8R1V5_S0_PCH_VCCVRM

7

20

=PP1V05_S0_PCH_VCCIO_PLLFDI

7

=PP1V05_S0_PCH_VCCDMI_FDI

7

AA23

VCCCORE

AC23

VCCCORE

AD21

VCCCORE

AD23

VCCCORE

AF21

VCCCORE

AF23

VCCCORE

AG21

VCCCORE

AG23

VCCCORE

AG24

VCCCORE

AG26

VCCCORE

AG27

VCCCORE

AG29

VCCCORE

AJ23

VCCCORE

AJ26

VCCCORE

AJ27

VCCCORE

AJ29

VCCCORE

AJ31

VCCCORE

AN19

VCCIO_28_PLLPCIE

BJ22

VCCAPLLEXP

AN16

VCCIO_15_FDI

AN17

VCCIO_16_FDI

AN21

VCCIO_17_PCIE

AN26

VCCIO_18_PCIE

AN27

VCCIO_19_PCIE

AP21

VCCIO_20_PCIE

AP23

VCCIO_21_PCIE

AP24

VCCIO_22_PCIE

AP26

VCCIO_23_PCIE

AT24

VCCIO_24_PCIE

AN33

VCCIO_25_DP

AN34

VCCIO_26_DP

BH29

VCC3_3_3_PCIE

AP16

VCCVRM_2_FDI

BG6

NC

VCCAFDIPLL

AP17

VCCIO_27_PLLFDI

AU20

VCCDMI_2_FDI

OMIT_TABLE

U1800

PANTHERPOINT

MOBILE

FCBGA

(7 OF 10)

VCC CORE

LVDS

HVCMOS

VCCIO

DMI CRT

FDI

DFT/SPI

VCCADAC

VSSADAC

VCCALVDS

VSSALVDS

VCCTX_LVDS
VCCTX_LVDS
VCCTX_LVDS
VCCTX_LVDS

VCC3_3_6_HVCMOS

VCC3_3_7_HVCMOS

VCCVRM_3_DMI

VCCDMI_1_DMI

VCCCLKDMI

VCCDFTERM
VCCDFTERM
VCCDFTERM
VCCDFTERM

VCCSPI

U48

PP3V3_S0_PCH_VCCA_DAC_F

U47

AK36

=PP3V3_S0_PCH_VCCA_LVDS

AK37

PP1V8_S0_PCH_VCCTX_LVDS_F

AM37
AM38

AP36

AP37

=PP3V3_S0_PCH_VCC3_3_HVCMOS

V33

V34

AT16

=PP1V8R1V5_S0_PCH_VCCVRM

AT20

=PP1V05_S0_PCH_VCC_DMI

AB36

PP1V05_S0_PCH_VCCCLKDMI_F

=PP1V8_S0_PCH_VCC_DFTERM

AG16

AG17

AJ16
AJ17

V1

=PP3V3_SUS_PCH_VCC_SPI

22

7

22

7

22

7

20

7

22

22

7

19 22

7

22

D

C

B

A

SYNC_MASTER=J5_MLB

PAGE TITLE

PCH POWER

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=03/21/2011

DRAWING NUMBER

051-9585

REVISION

3.0.0

BRANCH

PAGE

22 OF 132

SHEET

20 OF 105

124578

SIZE

A

D

www.vinafix.vn

8 7 6 5 4 3

H5

VSS

AA17

VSS

AA2

VSS

AA3

VSS

AA33

VSS

AA34

VSS

AB11

VSS

AB14

VSS

AB39

VSS

AB4

VSS

AB43

AC19

AC21

AC24

AC33
AC34

AC48
AD10

AD11

AD12
AD13

AD19

AD24
AD26

AD27

AD33
AD34

AD36
AD37

AD38

AD39

AD40

AD42
AD43

AD45

AD46

AF10

AF12
AD14

AD16

AF16
AF19

AF24

AF26
AF27

AF29
AF31

AF38

AF42

AF46

AG19

AG31
AG48

AH11

AH36

AH39

AH40
AH42

AH46

AJ19

AJ21
AJ24

AJ33

AJ34
AK12

VSS

AB5

VSS

AB7

VSS
VSS

AC2

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AD4

VSS
VSS
VSS
VSS
VSS
VSS

AD8

VSS

AE2

VSS

AE3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AF4

VSS
VSS
VSS

AF5

VSS

AF7

VSS

AF8

VSS
VSS

AG2

VSS
VSS
VSS
VSS

AH3

VSS
VSS
VSS
VSS
VSS
VSS

AH7

VSS
VSS
VSS
VSS
VSS
VSS
VSS

AK3

VSS

D

C

B

U1800

PANTHERPOINT

MOBILE

FCBGA

(9 OF 10)

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AK38
AK4

AK42

AK46
AK8

AL16

AL17
AL19

AL2
AL21

AL23

AL26
AL27

AL31

AL33
AL34

AL48

AM11
AM14

AM36
AM39

AM43

AM45
AM46

AM7

AN2
AN29

AN3

AN31
AP12

AP19
AP28

AP30

AP32
AP38

AP4

AP42
AP46

AP8

AR2
AR48

AT11
AT13

AT18

AT22
AT26

AT28

AT30
AT32

AT34

AT39
AT42

AT46
AT7

AU24

AU30
AV11

AV16

AV20
AV24

AV30

AV38
AV4

AV43
AV8

AW14

AW18
AW2

AW22

AW26
AW28

AW32

AW34
AW36

AW40
AW48

AY12

AY22
AY28

A

OMIT_TABLE

AY42

AY46

BB12

BB16

BB20
BB22

BB24
BB28

BB30

BB38

BB46

BC14
BC18

BC22
BC26

BC32
BC34

BC36

BC40
BC42

BC48

BD46

BE22

BE26
BE40

BF10
BF12

BF16

BF20
BF22

BF24

BF26
BF28

BF30
BF38

BF40

BG17

BG21
BG33

BG44

BH11

BH15

BH17
BH19

BH27

BH31

BH33
BH35

BH39

BH43

AY4

AY8

B11

B15
B19

B23
B27

B31

B35
B39

B7

F45

BB4

BC2

BD5

BD3

BF8

BG8

H10

BH7

D3

D12
D16

D18
D22

D24

D26
D30

D32

D34
D38

D42

D8
E18

E26
G18

G20

G26
G28

G36

G48
H12

H18

H22
H24

H26
H30

H32

H34

F3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

OMIT_TABLE

U1800

PANTHERPOINT

MOBILE

FCBGA

(10 OF 10)

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

H46

K18

K26
K39

K46

K7
L18

L2
L20

L26

L28
L36

L48

M12
P16

M18

M22
M24

M30
M32

M34

M38
M4

M42

M46
M8

N18

P30
N47

P11
P18

T33

P40
P43

P47

P7
R2

R48

T12
T31

T37
T4

W34

T46
T47

T8

V11
V17

V26

V27
V29

V31
V36

V39

V43
V7

W17

W19
W2

W27

W48
Y12

Y38
Y4

Y42

Y46
Y8

BG29

N24

AJ3
AD47

B43

BE10

BG41

G14

H16

T36

BG22

BG24
C22

AP13

M14
AP3

AP1

BE16
BC16

BG28

BJ28

SYNC_MASTER=J5_MLB

PAGE TITLE

PCH GROUNDS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

12

SYNC_DATE=03/21/2011

DRAWING NUMBER

051-9585

REVISION

3.0.0

BRANCH

PAGE

23 OF 132

SHEET

21 OF 105

124578

SIZE

D

C

B

A

D

www.vinafix.vn

8 7 6 5 4 3

12

7

20

7

D

PLACE_NEAR=U1800.M26:2.54mm

7

7

C

7

B

7

A

7

16

=PP3V3_SUS_PCH_VCCSUS
=PP5V_SUS_PCH

1 mA S0-S5

R2404

1/16W
MF-LF

C2438

0.1UF

CERM

2

10

NC NC

5%

402

1

1

20%
10V

2

402

=PP1V8_S0_PCH_VCCTX_LVDS

PLACE_NEAR=U1800.AM37:2.54mm

=PP3V3_S0_PCH_VCCADAC

PLACE_NEAR=U1800.U48:2.54mm

=PP3V3_S0_PCH_VCC3_3_CLK

=PP1V05_S0_PCH_VCCADPLL

=PP1V05_S0_PCH

(Z = 1.2MM, PLACE ON SHORT SIDE BEHIND PCH)

PCH V5REF_SUS Filter & Follower
(PCH Reference for 5V Tolerance on USB)

4

D2400

NC

BAT54DW-X-G

SOT-363

3

PP5V_SUS_PCH_V5REFSUS

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=5V
MAKE_BASE=TRUE

=PP5V_SUS_PCH_V5REFSUS

CRITICAL

L2407

0.1UH

1 2

0805

CRITICAL

C2400

22UF

X5R-CERM-1

PLACE_NEAR=U1800.AM37:2.54mm

PLACE_NEAR=U1800.U48:2.54mm

PLACE_NEAR=U1800.AM37:2.54mm

R2450

0

1 2

5%

1/20W

MF

201

CRITICAL

C2450

10UF

PLACE_NEAR=U1800.U48:2.54mm

R2451

1

1 2

5%
1/16W
MF-LF

402

R2490

0

1 2

1/16W
MF-LF

5%

402

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

<1 mA S0-S5

20

1

1

C2406

0.01UF

20%

6.3V

603

20%

6.3V
X5R
603

PP3V3_S0_PCH_VCC3_3_CLK_R

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.075 MM
VOLTAGE=3.3V

PP1V05_S0_PCH_VCCADPLLA_R

10%
16V

2

2

CERM
402

1

1

C2451

0.1UF

10%

2

2

X5R
402

(Z = 1.2MM, PLACE ON SHORT SIDE BEHIND PCH)

R2491

0

1 2

PP1V05_S0_PCH_VCCADPLLB_R

MIN_LINE_WIDTH=0.4 MM

5%

MIN_NECK_WIDTH=0.2 MM

1/16W

VOLTAGE=1.05V

MF-LF

402

(Z = 1.2MM, PLACE ON SHORT SIDE BEHIND PCH)

CRITICAL

L2406

10UH-0.58A-0.35OHM

1 2

1098AS-SM

PP1V05_S0_PCH_VCCCLKDMI_R

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.05V

PLACE_NEAR=U1800.P34:2.54mm

PP1V8_S0_PCH_VCCTX_LVDS_F

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.8V

1

C2408

0.01UF

10%
16V

2

CERM
402

PP3V3_S0_PCH_VCCA_DAC_F

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

1

C2455

0.01UF

10%
16V16V

2

CERM
402

CRITICAL

L2451

10UH-0.12A-0.36OHM

1 2

0603

CRITICAL

C2453

PLACE_NEAR=U1800.T38:2.54mm

PLACE_NEAR=U1800.T38:2.54mm

CRITICAL

L2490

10UH-0.12A-0.36OHM

1 2

0603

CRITICAL

C2491

PLACE_NEAR=U1800.BD47:2.54MM

PLACE_NEAR=U1800.BD47:2.54MM

CRITICAL

L2491

10UH-0.12A-0.36OHM

1 2

0603

CRITICAL

C2493

PLACE_NEAR=U1800.BF47:2.54MM

PLACE_NEAR=U1800.BF47:2.54MM

R2415

0

1 2

5%
1/16W
MF-LF

402

C2411

PLACE_NEAR=U1800.AB36:2.54mm

=PP3V3_S0_PCH

7

16

24

10UF

6.3V

220UF

220UF

10UF

6.3V

2.5V
TANT

2.5V
TANT

20%
X5R

603

20%

B16

20%

B16

20%
X5R

603

=PP5V_S0_PCH

7

1 mA

1

2

1

2

1

2

1

2

2

R2405

100

5%
1/16W
MF-LF

402

1

1

C2439

1UF

10%
10V

2

X5R
402

20

20

PP3V3_S0_PCH_VCC3_3_CLK_F

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.075 MM
VOLTAGE=3.3V

1

C2454

1UF

10%
10V

2

X5R
402

PCH VCCADPLLA Filter
(PCH DPLLA PWR)

PP1V05_S0_PCH_VCCADPLLA_F

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

NO STUFF

1

C2492

1UF

10%

6.3V

2

CERM
402

PCH VCCADPLLB Filter
(PCH DPLLB PWR)

PP1V05_S0_PCH_VCCADPLLB_F

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

NO STUFF

1

C2494

1UF

10%

6.3V

2

CERM
402

PP1V05_S0_PCH_VCCCLKDMI_F

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.05V

PCH V5REF Filter & Follower
(PCH Reference for 5V Tolerance on PCI)

1

52

D2400

NC

BAT54DW-X-G

SOT-363

6

PP5V_S0_PCH_V5REF

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V
MAKE_BASE=TRUE

=PP5V_S0_PCH_V5REF

20

<1 mA

20

=PP3V3_S5_PCH_VCCDSW

7

20

=PP3V3_SUS_PCH_VCC_SPI

7

20

=PP3V3_SUS_PCH_VCCSUS_GPIO

7

20

PCH VCCSUS3_3 BYPASS
(PCH SUSPEND USB 3.3V PWR)

=PP3V3_SUS_PCH_VCCSUS_USB

7

20

PLACE_NEAR=U1800.P24:2.54mm

20

68 mA

20

69 mA

20

C2499

0.1UF

PLACE_NEAR=U1800.T16:2.54mm

C2442

PLACE_NEAR=U1800.V1:2.54mm

C2476

PLACE_NEAR=U1800.P22:2.54mm

1

C2484

0.1UF

10%
16V

2

X5R
402

PLACE_NEAR=U1800.V24:2.54mm

PCH VCCSUSHDA BYPASS

=PP3V3R1V5_S0_PCH_VCCSUSHDA

7

20 24

PLACE_NEAR=U1800.P32:2.54mm

=PP1V8_S0_PCH_VCC_DFTERM

7

19 20

PLACE_NEAR=U1800.AJ16:2.54mm

=PP1V05_S0_PCH_V_PROC_IO

7

20

C2416

PLACE_NEAR=U1800.BJ8:2.54mm

PLACE_NEAR=U1800.BJ8:2.54mm

=PP1V05_S0_PCH_VCC_DMI

7

20

PLACE_NEAR=U1800.BJ8:2.54mm

PLACE_NEAR=U1800.AT20:2.54mm

20%
10V

CERM

402

1UF

10%

6.3V
CERM

402

1UF

10%

6.3V
CERM

402

4.7UF

6.3V

7

20

7

20

7

20

1

2

7

20

1

2

1

2

1

C2413

0.1UF

10%
16V

2

X5R
402

1

C2441

0.1UF

20%
10V

2

CERM

402

1

C2440

0.1UF

20%
10V

2

CERM

402

1

1

C2417

0.1UF

20%
X5R

402

10%
16V

2

2

X5R
402

C2419

1UF

6.3V
CERM

1

C2430

0.1UF

10%
16V

2

X5R
402

1

10%

2

402

6 3

=PP3V3_S0_PCH_VCC3_3_GPIO

PLACE_NEAR=U1800.T34:2.54mm

PLACE_NEAR=U1800.AA16:2.54mm

=PP3V3_S0_PCH_VCC3_3_HVCMOS

PLACE_NEAR=U1800.V33:2.54mm

=PP3V3_S0_PCH_VCC3_3_PCI

PLACE_NEAR=U1800.BH29:2.54mm

=PP3V3_S0_PCH_VCC3_3_SATA

PLACE_NEAR=U1800.AJ2:2.54mm

1

C2486

0.1UF

10%
25V

2

X5R
402

=PP1V05_S0_PCH_VCCIO

7

20

=PP1V05_S0_PCH_VCCASW

7

20

1

C2485

0.1UF

10%
25V

2

X5R
402

1

C2424

0.1UF

10%
16V

2

X5R
402

1

C2421

0.1UF

10%
16V

2

X5R
402

1

C2423

0.1UF

10%
16V

2

X5R
402

PLACE_NEAR=U1800.AN27:2.54mm

PLACE_NEAR=U1800.AN27:2.54mm

PLACE_NEAR=U1800.AC27:2.54mm

PCH VCCCORE BYPASS
(PCH 1.05V CORE PWR)

=PP1V05_S0_PCH_VCC_CORE

7

20

PCH VCCIO BYPASS

PCH VCC3_3 BYPASS
(PCH PCI 3.3V PWR)

=PP1V05_S0_PCH_VCCSSC

7

20

=PP1V05_S0_PCH_VCCDIFFCLK

7

16 20

=PP1V05_S0_PCH_VCCIO_CLK

7

20

=PP1V05_S0_PCH_VCCIO_SATA

7

16 20

PLACE_NEAR=U1800.AH13:2.54mm

PCH VCCIO BYPASS
(PCH USB 1.05V PWR)

=PP1V05_S0_PCH_VCCIO_USB

7

20

1

C2401

10UF

20%

6.3V
X5R
603

PLACE_NEAR=U1800.AN27:2.54mm

C2420

22UF

20%

6.3V 6.3V

X5R-CERM-1

603

PLACE_NEAR=U1800.AC27:2.54mm

PLACE_NEAR=U1800.AC27:2.54mm

PLACE_NEAR=U1800.AG26:2.54mm

PLACE_NEAR=U1800.AD21:2.54mm

SYNC_MASTER=J5_MLB

PAGE TITLE

1

C2429

1UF

10%

6.3V

2

2

CERM
402

PLACE_NEAR=U1800.AN27:2.54mm

1

2

C2428

22UF

X5R-CERM-1

6.3V

1

20%

2

603

PLACE_NEAR=U1800.AC27:2.54mm

1

C2460

10UF

20%

6.3V
2

X5R
603

PLACE_NEAR=U1800.AG24:2.54mm

PCH DECOUPLING

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

C2475

PLACE_NEAR=U1800.AG33:2.54mm

C2434

PLACE_NEAR=U1800.AF34:2.54mm

C2469

PLACE_NEAR=U1800.AF17:2.54mm

1

C2444

1UF

6.3V
CERM

C2452

10%

2

402

PLACE_NEAR=U1800.AC17:2.54mm

C2446

PLACE_NEAR=U1800.P28:2.54mm

1

2

C2414

1UF

10%

6.3V
CERM
402

1

C2407

2

1UF

10%

6.3V
CERM
402

PLACE_NEAR=U1800.AN27:2.54mm

1

2

C2426

1UF

10%

6.3V
CERM
402

1

C2456

2

1UF

10%

6.3V
CERM
402

PLACE_NEAR=U1800.AC27:2.54mm

1

2

C2481

1UF

10%

6.3V
CERM
402

1

C2482

2

1UF

10%

6.3V
CERM
402

PLACE_NEAR=U1800.AJ27:2.54mm

SYNC_DATE=05/26/2011

DRAWING NUMBER

051-9585

REVISION

BRANCH

PAGE

SHEET

124578

1

1UF

10%

6.3V
2

CERM

402

1

1UF

10%

6.3V
2

CERM

402

1

1UF

10%

6.3V
2

CERM

402

1

1UF

10%

6.3V
2

CERM

402

1

1UF

10%

6.3V
2

CERM

402

1

C2463

1UF

10%

6.3V

2

CERM
402

1

C2496

1UF

10%

2

CERM
402

1

C2483

1UF

10%

6.3V

2

CERM
402

3.0.0

24 OF 132
22 OF 105

SIZE

D

C

B

A

D

www.vinafix.vn

8 7 6 5 4 3

12

=PP3V3_S0_XDP

7

XDP_CPU_PREQ_L

10 93

BI

XDP_CPU_PRDY_L

10 93

D

(R2560-R2563)

XDP_CPU:BPM

XDP_CPU:BPM

XDP_CPU:BPM

XDP_CPU:BPM

0

10 93

10 93

10 93

10 93

9

93

9

93

9

93

9

93

10 19 93

17 23 45

9

23 93

17 45 92

XDP_BPM_L<4>

IN
IN

XDP_BPM_L<6>

IN

XDP_BPM_L<7>

IN

CPU_CFG<12>

IN

CPU_CFG<13>

IN

CPU_CFG<14>

IN

CPU_CFG<15>

IN

CPU_PWRGD

IN

PM_PWRBTN_L

OUT

CPU_CFG<0>

OUT

PM_PCH_SYS_PWROK

OUT

R2560
R2561
R2562
R2563

R2564
R2565
R2566
R2567

PLACE_NEAR=U1000.C60:2.54mm

PLACE_NEAR=U4900.P17:2.54mm

PLACE_NEAR=U1000.B57:2.54mm

R2500

R2502

R2501

R2504

1 2

0

1 2

0

1 2

0

1 2

(R2564-R2567)

XDP_CPU:CFG

XDP_CPU:CFG

XDP_CPU:CFG

XDP_CPU:CFG

0

1 2

0

1 2

0

1 2

0

1 2

XDP

1K

1 2

XDP

0

1 2

XDP

1K

1 2

XDP

330

1 2

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

C

XDP SIGNALS

XDP_DA0_USB_EXTA_OC_L

23

OUT

XDP_DA1_USB_EXTB_OC_L

23

OUT

XDP_DA2_USB_EXTC_OC_L

23

OUT

XDP_DA3_USB_EXTD_OC_L

23

OUT

XDP_DB0_USB_EXTB_OC_EHCI_L

23

OUT

XDP_DB1_USB_EXTD_OC_EHCI_L

23

OUT

XDP_DB2_AP_PWR_EN

23

IN

XDP_DB3_SDCONN_STATE_CHANGE

23

OUT

XDP_FC0

23

OUT

XDP_FC1

23

OUT

XDP_DC0_ISOLATE_CPU_MEM_L

23

IN

XDP_DC1_MXM_GOOD

23

IN

XDP_DC2_DP_AUXCH_ISOL

23

IN

XDP_DC3_SATARDRVR_EN

23

IN

XDP_DD0_DP_GPU_TBT_SEL

23

IN

XDP_DD1_JTAG_ISP_TCK

23

IN

XDP_DD2_AUD_IPHS_SWITCH_EN

23

IN

XDP_DD3_ENET_LOW_PWR

23

IN

B

PCH/XDP Signal Isolation Notes:

- Following Intel’s Debug Prot Design Guid for HR and CR v1.3
doc id 404081.
Initially, stuffing both 33 and 0 ohms and validate whether
it is functional in that state, else add BOM options.

- For isolated GPIOs:

- ’Output’ non-XDP signals require pulls.

- ’Output’ PCH/XDP signals require pulls.

R252x, R253x, R257x and R259x should be placed where signal path
needs to split between route from PCH to J2550
and path to non-XDP signal destination.

ALL_SYS_PWRGD

45 74 89 92

17 23 45

IN

OUT

PM_PWRBTN_L

PLACE_NEAR=J2550.39:2.54mm

PLACE_NEAR=U4900.P17:2.54mm

R2584

R2585

R2520
R2521
R2522
R2523

R2524
R2525
R2526
R2527
R2528

R2529
R2530

R2531
R2532
R2533
R2534
R2535

R2536
R2537

A

XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L

18 23

XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L

18 23 18 23

(R2520-R2537)

33
33
33
33

33
33
33
33
33

33

33
33
33
33
33
33

33
33

XDP

1K

1 2

XDP

0

1 2

R2580

R2581

XDP

XDP

XDP

XDP

XDP

XDP

XDP

XDP

XDP

XDP

XDP

XDP

XDP

XDP

XDP

XDP

XDP

XDP

1 2
1 2

1 2

1 2

1 2

1 2
1 2

1 2

1 2

1 2

1 2
1 2

1 2

1 2
1 2

1 2

1 2

1 2

5%

5%

1K

1K

5%

5%

5% MF
5%

5%
5%

5%
5%

5%

5%

5% MF

5%

5% MF
5%

5%

5% MF

5%
5%

1/20W

1/20W

1 2

1 2

PCH SIGNALS

1/20W

1/20W

1/20W
1/20W

1/20W
1/20W

1/20W
1/20W

1/20W

1/20W

1/20W

1/20W

1/20W
1/20W

1/20W

1/20W

XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH

1/20W
1/20W

MF

MF

5%

5%

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L

201

MF

XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L

201

MF

XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L

201

XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L

201

MF

XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L

MF

201

XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L

201

MF

201

MF

XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

201

MF

201

MF

201

MF

XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L

201

MF

201

XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL

201

XDP_DC3_PCH_GPIO19_SATARDRVR_EN

201

XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL

201

XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK

201

201

XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH

201

23 48

23 48

16 23

XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L

201

MF

XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L

MF

201

201

201

MF

MF

MF
MF

1/20W

1/20W

IN

XDP_BPM_L<0>

10 93

IN

XDP_BPM_L<1>

10 93

IN

XDP_BPM_L<2>XDP_BPM_L<5>

10 93

IN

XDP_BPM_L<3>

10 93

IN

CPU_CFG<10>

9

93

IN

CPU_CFG<11>

9

93

IN

XDP_OBSDATA_B<0>
XDP_OBSDATA_B<1>

XDP_OBSDATA_B<2>
XDP_OBSDATA_B<3>

XDP_CPU_PWRGD

93

XDP_CPU_PWRBTN_L

XDP_CPU_CFG<0>
XDP_VR_READY

=SMBUS_XDP_SDA

23 48

BI

=SMBUS_XDP_SCL

23 48

IN

XDP_CPU_TCK

10 23 93

OUT

XDP_DB2_PCH_GPIO10_AP_PWR_EN

XDP_FC0_PCH_GPIO15

XDP_FC1_PCH_GPIO0

XDP_DC1_PCH_GPIO35_MXM_GOOD

TP_XDP_PCH_OBSFN_A<0>
TP_XDP_PCH_OBSFN_A<1>

XDP_DA0_USB_EXTA_OC_L

23 23

XDP_DA1_USB_EXTB_OC_L

23

XDP_DA2_USB_EXTC_OC_L

23

XDP_DA3_USB_EXTD_OC_L

23

TP_XDP_PCH_OBSFN_B<0>
TP_XDP_PCH_OBSFN_B<1>

XDP_DB0_USB_EXTB_OC_EHCI_L

23

XDP_DB1_USB_EXTD_OC_EHCI_L

23

XDP_DB2_AP_PWR_EN

23

XDP_DB3_SDCONN_STATE_CHANGE

23

XDP_PCH_S5_PWRGD
XDP_PCH_PWRBTN_L

TP_XDPPCH_HOOK2

6

TP_XDPPCH_HOOK3

6

=SMBUS_XDP_SDA

BI

=SMBUS_XDP_SCL

IN

XDP_PCH_TCK

OUT

6 3

7

23

NO STUFF

R2540

1/16W
MF-LF

402

=PPVCCIO_S0_XDP

1

1K

5%

2

OBSFN_A0
OBSFN_A1

OBSDATA_A0
OBSDATA_A1

OBSDATA_A2
OBSDATA_A3

OBSFN_B0
OBSFN_B1

OBSDATA_B0
OBSDATA_B1

OBSDATA_B2
OBSDATA_B3

PWRGD/HOOK0

VCC_OBS_AB

18 23

IN

18 23

IN

18

IN

18 23

IN

18 23

IN

18 23

IN

18 23

OUT

18 23

IN

19 68

IN

19

IN

19 23

OUT

19

OUT

16 23

OUT

16 23

OUT

19

OUT

19 23

OUT

19 23

OUT

19 23

OUT

OBSFN_A0
OBSFN_A1

OBSDATA_A0
OBSDATA_A1

OBSDATA_A2
OBSDATA_A3

OBSFN_B0
OBSFN_B1

OBSDATA_B0
OBSDATA_B1

OBSDATA_B2
OBSDATA_B3

PWRGD/HOOK0

VCC_OBS_AB

18 23

CPU Micro2-XDP

CRITICAL

XDP_CONN_CPU

J2500

DF40RC-60DP-0.4V

M-ST-SM

62

61

1

2

3

4

5

6

78

10

9
1112

1314

1516
1718

19

20

2122
2324

2526

2728
29

30

3132
3334

3536

3738
39

40

HOOK1

HOOK2
HOOK3

SDA

SCL
TCK1
TCK0

XDP

C2500

0.1uF

10%
16V
X5R
402

NOTE: This is not the standard XDP pinout.
Use with 921-0133 Adapter Flex to
support chipset debug.

NC

1

2

998-2516

4142

4344
4546

4748

49

50

5152

5354
5556

5758

59

60

6364

PCH Micro2-XDP

CRITICAL

XDP_CONN_PCH

J2550

DF40RC-60DP-0.4V

M-ST-SM

62

61

1

2

3

4

5

6

78

10

9

1112
1314

1516

1718
19

20

2122

2324
2526

2728
29

30

3132

3334
3536

3738

39

40

HOOK1

HOOK2
HOOK3

SDA

SCL
TCK1
TCK0

C2580

0.1uF

XDP

NC

1

10%
16V

2

X5R
402

998-2516

4142

4344

4546
4748

49

50

5152

5354

5556
5758

59

60

6364

NOTE: This is not the standard XDP pinout.
Use with 921-0133 Adapter Flex to
support chipset debug.

OBSFN_C0
OBSFN_C1

OBSDATA_C0
OBSDATA_C1

OBSDATA_C2
OBSDATA_C3

OBSFN_D0
OBSFN_D1

OBSDATA_D0
OBSDATA_D1

OBSDATA_D2
OBSDATA_D3

ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page
TDO
TRSTn
TDI
TMS
XDP_PRESENT#

XDP

1

C2501

0.1uF

10%
16V

2

X5R
402

=PP3V3_S5_XDP

OBSFN_C0
OBSFN_C1

OBSDATA_C0
OBSDATA_C1

OBSDATA_C2
OBSDATA_C3

OBSFN_D0
OBSFN_D1

OBSDATA_D0
OBSDATA_D1

OBSDATA_D2
OBSDATA_D3

ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page
TDO
TRSTn
TDI
TMS
XDP_PRESENT#

XDP

1

C2581

0.1uF

10%
16V

2

X5R
402

CPU_CFG<16>
CPU_CFG<17>

CPU_CFG<0>
CPU_CFG<1>

CPU_CFG<2>
CPU_CFG<3>

CPU_CFG<8>
CPU_CFG<9>

CPU_CFG<4>
CPU_CFG<5>

CPU_CFG<6>
CPU_CFG<7>

XDP_CPU_CLK100M_P

93

XDP_CPU_CLK100M_N

93

XDP_CPURST_L
XDP_DBRESET_L

XDP_CPU_TDO
XDP_CPU_TRST_L
XDP_CPU_TDI
XDP_CPU_TMS

PCH SIGNALS

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L

18 23

OUT

XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L

18 23

OUT

XDP_DB2_PCH_GPIO10_AP_PWR_EN

18 23

IN

XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

18 23

OUT

XDP_DC3_PCH_GPIO19_SATARDRVR_EN

16 23

IN

XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L

19 23

OUT

XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL

16 23

IN

7

XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK

XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH

19 23

OUT

XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH

19 23

OUT

XDP_FC0
XDP_FC1

XDP_DC0_ISOLATE_CPU_MEM_L
XDP_DC1_MXM_GOOD

XDP_DC2_DP_AUXCH_ISOL
XDP_DC3_SATARDRVR_EN

TP_XDP_PCH_OBSFN_D<0>
TP_XDP_PCH_OBSFN_D<1>

XDP_DD0_DP_GPU_TBT_SEL
XDP_DD1_JTAG_ISP_TCK

XDP_DD2_AUD_IPHS_SWITCH_EN
XDP_DD3_ENET_LOW_PWR

TP_XDP_PCH_HOOK4
TP_XDP_PCH_HOOK5

XDPPCH_PLTRST_L
XDP_DBRESET_L

XDP_PCH_TDO
TP_XDP_PCH_TRST_L
XDP_PCH_TDI
XDP_PCH_TMS

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

OUT

IN
OUT
OUT
OUT

9

93

9

93

9

23 93

9

93

9

93

9

93

9

93

9

93

9

93

9

93

9

93

9

93

10 23 24 93

10 23 93

10 23 93

10 23 93

10 23 93

R2515

R2516

R2505

23

23

23

23

23

23

23

23

23

IN

OUT

IN

OUT
OUT

24

10 23 24 93

16 23

16 23

16 23

XDP_CPU_TDO

10 23 93

XDP_CPU_TDI

10 23 93

XDP_CPU_TMS

10 23 93

XDP_CPU_TCK

10 23 93

XDP_CPU_TRST_L

10 23 93

XDP

0

0

1K

PLACE_NEAR=R1841.1:2.54mm

1 2

5%

XDP

PLACE_NEAR=R1840.1:2.54mm

1 2

5%

XDP

PLACE_NEAR=U1000.G3:2.54mm

1 2

5%

R2575
R2576
R2577

16 23

16 23

16 23

16 23

0
0
0
0

0

0

0

XDP_PCH_TDO

XDP_PCH_TDI

XDP_PCH_TMS

XDP_PCH_TCK

R2590
R2591
R2596
R2597

R2573

R2570
R2572

ITPXDP_CLK100M_P

1/20W

MF

ITPXDP_CLK100M_N

1/20W

MF

CPU_RESET_L

1/20W

MF

1 2

5%

1 2

5%

1 2

5%

1 2

5%

1 2

5%

1 2

5%

1 2

5%

0

1 2

0

1 2

0

1 2

201

201

201

1K series R on PCH Support Page

SYNC_MASTER=J31_ANNE SYNC_DATE=06/09/2011

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

23

XDP

51

IN

IN

IN

51

51

51

51

2 1

2 1

2 1

2 1

2 1

16 93

16 93

10 24

XDP

XDP

XDP

XDP

R2510

R2511

R2512

R2513

R2514

Non-XDP Signals

1/20W
1/20W

1/20W

1/20W

1/20W

1/20W

1/20W

5%

5%
5%

R2550

R2551

R2552

R2556

201

MF

201

MF

201

MF

SDCONN_STATE_CHANGE

201

MF

201

MF

201

MF

201

MF

1/20W

MF

AUD_IPHS_SWITCH_EN_PCH

1/20W

MF

1/20W

MF

51

51

51

51

ISOLATE_CPU_MEM_L

201

201

ENET_LOW_PWR_PCH

201

XDP

2 1

XDP

2 1

XDP

2 1

XDP

2 1

CPU & PCH XDP

Apple Inc.

R

=PPVCCIO_S0_XDP

7

PLACE_NEAR=J2500.52:2.54mm

1/20W

5%

PLACE_NEAR=U1000.K61:2.54mm

5%

PLACE_NEAR=U1000.H59:2.54mm

5%

PLACE_NEAR=U1000.J58:2.54mm

5%

PLACE_NEAR=U1000.H63:2.54mm

5%

USB_EXTA_OC_L
USB_EXTB_OC_L

1/20W

1/20W

1/20W

1/20W

AP_PWR_EN

MF

MF

MF

MF

MF

SATARDRVR_EN

DP_AUXCH_ISOL

JTAG_ISP_TCK

=PP1V05_SUS_PCH_JTAG

7

PLACE_NEAR=J2550.52:2.54mm

1/20W

5%

PLACE_NEAR=U1800.K5:2.54mm

5%

PLACE_NEAR=U1800.H7:2.54mm

5%

PLACE_NEAR=U1800.J3:2.54mm

5%

1/20W

1/20W

1/20W

MF

MF

MF

MF

DRAWING NUMBER

051-9585

REVISION

BRANCH

PAGE

25 OF 132

SHEET

23 OF 105

124578

201

201

201

201

201

IN
IN

OUT

IN

OUT

OUT

OUT

OUTOUT
OUT
OUT

201

201

201

201

3.0.0

42

42

18 32 74

24

16 41

26

16 87

8

19 19 23

19 24

19 24

SIZE

D

C

B

A

D

www.vinafix.vn

8 7 6 5 4 3

GPIO Glitch Prevention

=PP3V3_S3_PCH_GPIO

7

18 24

D

ENET_LOW_PWR_PCH

19 23

IN

PM_PCH_PWROK

17 24 92

IN

FW_PWR_EN_PCH

19

IN

=PP3V3_S3_PCH_GPIO

7

18 24

TBT_PWR_EN_PCH

16

IN

PM_PCH_PWROK

17 24 92

IN

AUD_IPHS_SWITCH_EN_PCH

19 23

IN

C

LPC_CLK33M_SMC_R

18 96

IN

LPC_CLK33M_LPCPLUS_R

18

IN

TP_PCI_CLK33M_OUT2

18

IN

PCH_CLK33M_PCIOUT

18

IN

B

System RTC Power Source & 32kHz / 25MHz Clock Generator

VDDIO_25M_A: SB power rail for XTAL circuit.
VDDIO_25M_B: Ethernet power rail for XTAL circuit.
VDDIO_25M_C: T29 power rail for XTAL circuit.

NOTE: VDD_25M must be powered if any VDDIO_25M_x is powered.

GreenClk 25MHz Power

Ethernet XTAL Power
SB XTAL Power
T29 XTAL Power

A

C2605

12PF

5%

50V

CERM

402

C2606

12PF

1 2

5%

50V

CERM

402

7

7

7

7

12

CRITICAL

VCC

U2150

SOT833

08

1

A1

2

B1

5

A2

6

B2

GND

CRITICAL

VCC

U2152

SOT833

08

1

A1

2

B1

5

A2

6

B2

GND

LPC_CLK33M_GMUX_R

MAKE_BASE=TRUE

=PP3V3_ENET_SYSCLK

=PPVDDIO_ENET_CLK
=PPVDDIO_S0_SBCLK
=PPVDDIO_T29_CLK

C2624

0.1UF

20%

10V

CERM

402

SYSCLK_CLK25M_X2

CRITICAL

13

Y2605

NC

24

SM-3.2X2.5MM

NC

25.000MHZ-12PF-20PPM

NOTE: 30 PPM crystal required

8

7

Y1

3

Y2

74LVC2G08GT

4

8

7

Y1

3

Y2

74LVC2G08GT

4

1

C2622

2

R2605

1 2

1

C2150

0.1UF

20%
10V

2

CERM
402

ENET_LOW_PWR

FW_PWR_EN

1

C2152

0.1UF

20%
10V

2

CERM
402

TBT_PWR_EN

AUD_IPHS_SWITCH_EN

R2655

22

1 2

5%

1/20W

MF

201

R2657

22

1 2

5%

1/20W

MF

201

1

0.1UF

20%

10V

2

CERM

402

0

5%

1/16W

1

MF-LF

402

2

30 36

OUT

39

OUT

35

OUT

63

OUT

SDCONN_STATE_CHANGE

23

LPC_CLK33M_SMC

R2656

22

1 2

R2659

1 2

=PPVBAT_G3_SYSCLK

7

Coin-Cell: VBAT (300-ohm & 10uF RC)
No Coin-Cell: 3.42V G3Hot (no RC)

=PP3V3_S5_SYSCLK

7

Coin-Cell & G3Hot: 3.42V G3Hot
Coin-Cell & No G3Hot: 3.3V S5
No Coin-Cell: 3.3V S5

C2620

0.1UF

SYSCLK_CLK25M_X2_R

NO STUFF

R2606

1M

5%
1/16W
MF-LF
402

1/20W

1/20W

5%

MF
201

22

5%
MF

201

20%

10V

CERM

402

LPC_CLK33M_LPCPLUS

LPC_CLK33M_GMUX

PCH_CLK33M_PCIIN

1

1

C2602

1UF

10%

10V

2

2

X5R
402-1

No bypass necessary

SYSCLK_CLK25M_X1

6 3

Ethernet WAKE# Isolation

=PP3V3_ENET_PHY

CRITICAL

Q2630

SSM3K15FV

SOD-VESM-HF

PCIE_WAKE_L

6

17 32 36

OUT

92

XDP_DBRESET_L

10 23 93

IN

D

3

=PP3V3_S0_SB_PM

7

PCH Reset Button

R2696

1 2

XDP

1/16W
MF-LF

1

R2630

10K

1

5%
1/16W

GS

MF-LF
402

2

ENET_WAKE_L

MAKE_BASE=TRUE

2

1

R2695

4.7K

5%
1/16W
MF-LF
402

2

0

5%

402

SDCONN_STATE_CHANGE

=PP3V3_S3_SDBUF

7

1

C2630

0.1UF

10%

6.3V

2

X5R
201

CRITICAL

TC7SZ08FEAPE

5

U2630

3

A

B

20 22 24

1

2

2

1

SDCONN_STATE_CHANGE_SMC

ENET_MEDIA_SENSE ISOLATION CIRCUIT

5%

MF

7

1

2

1

2

1 2

402

CRITICAL

SSM6N37FEAPE

Q2610

SSM6N37FEAPE

Q2610

SOT563

2

16

OUT

OUT

33

OUT

ENET_MEDIA_SENSE

36

IN

=PP3V3_S3_PCH_GPIO

7

18 24

ENET_MEDIA_SENSE_EN_L

=PP3V3R1V5_S0_PCH_VCCSUSHDA

7

R2612

ENET_MEDIA_SENSE_EN

SYSCLK_CLK32K_RTC

SYSCLK_CLK25M_SB
SYSCLK_CLK25M_ENET_R
SYSCLK_CLK25M_TBT
=PPVRTC_G3_OUT

For SB RTC Power

C2610

1UF

10%

6.3V
CERM
402

R2611

1/16W

MF-LF

100K

1/20W

201

0

5%

402

11

VDDIO_25M_A

6

VDDIO_25M_B

14

VDDIO_25M_C

3

X2

4

X1

OUT

OUT

OUT

OUT

5

VDD_25M

SLG3NB148A

71016

45 96

6

47 96

89

16 96

2

+V3.3A

U2600

TQFN

CRITICAL

VDD_RTC_OUT

GND

32KHZ_A

25MHZ_A
25MHZ_B
25MHZ_C

THRM

PAD

17

13

+3.42V

SOT665

4

Y

VBAT and +V3.3A are
internally ORed to
create VDD_RTC_OUT.

+V3.3A should be first
available ~3.3V power
to reduce VBAT draw.

12

9

8
15

1

7

36 72

=ENET_WAKE_L

PM_SYSRST_L

OMIT

1

R2697

0

5%
1/16W
MF-LF
402

2

SILK_PART=SYS RESET

R2610

5%

12K

ENET_MEDIA_SENSE_RDIV

MF-LF

1/16W

3

D

SOT563

5

SG

4

6

D

SG

1

R2600

16

0

1 2

1/20W

201

5%
MF

SYSCLK_CLK25M_ENET

30 46

18 26

IN

6

17 45

BI

16

OUT

=PP3V3R1V5_S0_PCH_VCCSUSHDA

7

20 22 24

OUT

Platform Reset Connections

PLT_RESET_L

Unbuffered

IN

MAKE_BASE=TRUE

Buffered

=PP3V3_S0_RSTBUF

7

24

1

C2680

0.1UF

20%
10V

2

CERM

402

=PP3V3_S0_RSTBUF

7

24

1

C2690

0.1UF

20%
10V

2

CERM

402

PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.
If high, ME is disabled. This allows for full re-flashing of SPI ROM.
SMC controls strap enable to allow in-field control of strap setting.
Q2620 & 5V pull-up allows circuit to work regardless of HDA voltage.

Note: Based on K91/K92 layout, ENET,AP and BKLT are moved to Buffered reset.

CRITICAL

5

MC74VHC1G08

1

2

U2680

SC70-HF

4

PLT_RST_BUF_L

MAKE_BASE=TRUE

1

3

R2680

100K

5%
1/16W
MF-LF
402

2

Buffered CPU reset

CRITICAL

5

U2690

74LVC1G07

SC70

2

NC

4

PLT_RST_CPU_BUF_L

MAKE_BASE=TRUE

1

R2690

3

1

NC

2

100K

5%
1/16W
MF-LF
402

R2681

1 2

1/16W
MF-LF

R2687

1 2

=PP5V_S0_PCH

7

22

33

5%

402

1/16W
MF-LF

0

5%

402

PCH ME Disable Strap

Q2620

SPI_DESCRIPTOR_OVERRIDE_L

45

IN

36

SSM6N37FEAPE

SOT563

D

3

SSM6N37FEAPE

Q2620

SOT563

5

SPI_DESCRIPTOR_OVERRIDE_LS5V

S G

SPI_DESCRIPTOR_OVERRIDE

4

6

D

2

SG

1

SYNC_MASTER=K92_MLB

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

LPC_RESET_L

LPCPLUS_RESET_L

MAKE_BASE=TRUE

R2683

33

1 2

1/16W
MF-LF

R2671

1 2

1/16W
MF-LF

5%

402

0

5%

402

SMC_LRESET_L

PCA9557D_RESET_L

XDP

R2689

1K

1 2

1/16W
MF-LF

5%

402

XDPPCH_PLTRST_L

GMUX_RESET_L

MAKE_BASE=TRUE

=GMUX_PCIE_RESET_L

=FW_RESET_L

Series R is R4283

=ENET_RESET_L

=TBT_RESET_L

Series R on Pg38, R3803

R2688

0

1 2

5%
1/16W
MF-LF

402

R2693

0

1 2

5%
1/16W
MF-LF

402

AP_RESET_L

BKLT_PLT_RST_L

CPU_RESET_L

VTT voltage divider on CPU page

1

R2620

100K

5%
1/20W
MF
201

2

1

R2621

1K

5%
1/20W
MF
201

2

HDA_SDOUT_R

IPD = 9-50k

Chipset Support

Apple Inc.

R

16 96

OUT

12

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

SYNC_DATE=07/06/2010

DRAWING NUMBER

051-9585

REVISION

3.0.0

BRANCH

PAGE

26 OF 132

SHEET

24 OF 105

124578

89 96

6

45

31

23

89

39

10 23

47

D

C

30

OUT

35

OUT

32

OUT

90

OUT

B

A

SIZE

D

www.vinafix.vn

8 7 6 5 4 3

12

BOM GROUP

HUB_ALLREM

HUB_1NONREM

USB MUX FOR LS/FS INTERNAL DEVICES

HUB_2NONREM
HUB_3NONREM

NON_REM 1 : NON_REM 0 STRAP PIN CFG
0 : 0 ALL PORTS ARE REMOVABLE

0 : 1 PORT 1 IS NON REMOVABLE
1 : 0 PORT 1&2 ARE NON REMOVABLE
1 : 1 PORT 1&2&3 ARE NON REMOVABLE

PART#

338S0824

338S0923

338S0983

J5 ENGINEERING: USE USB2513B PRODUCTION: USE USB2512B
J3X ENGINEERING: USE USB2514B PRODUCTION: USE USB2513B

25

25

25

25

7

25

TO CONNECT TP/KB TO PCH XHCI
NOSTUFF R5701 & R5702, STUFF R2720 & R2721

USB_EXTD_XHCI_N

18 95

BI

TO PCH XHCI

USB_EXTD_XHCI_P

18 95

BI

1

2

C2706

R2701

100

1 2

5%
1/16W
MF-LF

402

1

R2706

10K

5%
1/16W
MF-LF
402

2

C2702

0.1UF

10%
16V
X7R-CERM
402

0.1UF

X7R-CERM

BYPASS=U2700.5::2MM

1

C2703

0.1UF

10%
16V

2

X7R-CERM
402

BYPASS=U2700.23::2MM

1

C2708

10%
16V

2

402

0.1UF

X7R-CERM

USB_HUB_TEST

USB_HUB_RESET_L

25

USB_HUB_XTAL1
USB_HUB_XTAL2

USB_HUB_NONREM0

USB_HUB_NONREM1

USB_HUB_CFG_SEL0

USB_HUB_CFG_SEL1

1

R2707

10K

5%
1/16W
MF-LF
402

2

CANNOT INDICATE ALL 4 PORTS ARE NON REMOVABLE ON USB2514B VIA STARPPING, PROGRAM NON_REMOVABLE DEVICE REGISTER 09H

1

10%
16V

2

402

5

1015232936

VDD33

SYM VER 1

U2700

USB2513B

11

TEST

26

RESET*

33

XTALIN/CLKIN

32

XTALOUT

28

SUSP_IND/LOCAL_PWR/NON_REM0

22

SDA/SMBDATA/NON_REM1

24

SCL/SMBCLK/CFG_SEL0

25

HS_IND/CFG_SEL1

QFN

OMIT

THRM_PAD

PPUSB_HUB2_VDD1V8

MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.8V

PPUSB_HUB2_VDD1V8PLL

MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.8V

14

34

CRFILT

PLLFILT

USBDM_DN1/PRT_DIS_M1
USBDP_DN1/PRT_DIS_P1

USBDM_DN2/PRT_DIS_M2
USBDP_DN2/PRT_DIS_P2

USBDM_DN3/PRT_DIS_M3
USBDP_DN3/PRT_DIS_P3

PRTPWR1/BC_EN1*
PRTPWR2/BC_EN2*
PRTPWR3/BC_EN3*

37

IPU
IPU
IPU
IPU

OCS1*
OCS2*
OSC3*

RBIAS

VBUS_DET

USBDM_UP
USBDP_UP

1

C2711

0.1UF

10%
16V

2

X7R-CERM
402

1

USBHUB_DN1_N

2

USBHUB_DN1_P

3

USBHUB_DN2_N

4

USBHUB_DN2_P

6

USBHUB_DN3_N

7

USBHUB_DN3_P

8

USBHUB_DN4_N

NC

9

USBHUB_DN4_P

NC

12

TP_USB_HUB_PRTPWR1

16

NC_USB_HUB_PRTPWR2

18

NC_USB_HUB_PRTPWR3

20

NC_USB_HUB_PRTPWR4

NC

13

TP_USB_HUB_OCS1

17

NC_USB_HUB_OCS2

19

NC_USB_HUB_OCS3

21

NC_USB_HUB_OCS4

NC

35

USB_HUB_RBIAS

27

USB_HUB_VBUS_DET

30

USB_HUB_UP_N

31

USB_HUB_UP_P

PCH PORT 7 (EHCI1)

1

C2712

2

1UF

1

C2713

0.1UF

10%
16V

2

X7R-CERM

10%
16V
X5R
402

402

8

BI

8

BI

8

BI

8

BI

8

25

BI

8

25

BI

8

25

BI

8

25

BI

1

C2714

1UF

10%
16V

2

X5R
402

BLUETOOTH FOR J5 & J3X

TP/KB FOR J5, IR FOR J3X

SMC DEBUG PORT FOR J5, TP/KB FOR J3X

NC FOR J5, SMC DEBUG PORT FOR J3X

=PP3V3_S3_USB_HUB

1

R2708

10K

5%
1/16W
MF-LF
402

2

CRITICAL

1

18 95

BI
BI

18 95

R2709

12K

1%
1/16W
MF
402

2

=PP3V3_S3_USB_HUB

7

D

C

25

USB_HUB_XTAL_C

CRITICAL

1/16W
MF-LF

1/16W
MF-LF

10K

10K

HUB_NONREM0_1

1

1

R2703

10K

5%

5%

1/16W
MF-LF
402

402

2

2

HUB_NONREM0_0

1

1

R2705

10K

5%

5%

1/16W
MF-LF
402

402

2

2

HUB_NONREM1_1

R2702

HUB_NONREM1_0

R2704

J5 USES 197S0181 FOR Y2700 DUE TO HEIGHT LIMITATION
J3X USE 197S0284 FOR Y2700 TO SAVE COST

B

BYPASS=U27000.5::5MM

BYPASS=U2700.23::5MM

24.000M-60PPM-16PF

1

C2709

18PF

CERM

=PP3V3_S3_USB_RESET

7

1

5%

50V

2

402

2

1

C2700

4.7UF

20%

6.3V
2

X5R
603

BYPASS=U2700.15::2MM

1

C2704

4.7UF

20%

6.3V
2

X5R
603

CRITICAL

Y2700

1 2

5X3.2X1.4-SM

R2710

0

5%
1/16W
MF-LF
402

R2700

1M

1 2

5%
1/16W
MF-LF

402

CRITICAL

1

2

C2701

0.1UF

10%
16V

X7R-CERM

402

C2705

0.1UF

X7R-CERM

BYPASS=U2700.36::2MM

CRITICAL

1

C2710

18PF

5%
50V

2

CERM
402

R2712

10K

5%
1/16W
MF-LF
402

USB_HUB_RESET_L

1

2

BYPASS=U2700.10::2MM

1

10%
16V

2

402

BYPASS=U2650.29::2MM

25

HUB_NONREM1_0,HUB_NONREM0_0
HUB_NONREM1_0,HUB_NONREM0_1
HUB_NONREM1_1,HUB_NONREM0_0
HUB_NONREM1_1,HUB_NONREM0_1

DESCRIPTION

QTY

1

USB HUB 2514B

USB HUB 2513B

1

USB HUB 2512B

1

USBHUB_DN3_N

8

USBHUB_DN3_P

8

USBHUB_DN4_N

8

USBHUB_DN4_P

8

BOM OPTIONS

BOM TABLE

NOSTUFF NOSTUFF

1

R2716

10K

5%
1/16W
MF-LF
402

2

NOSTUFF

R2721

27

1 2

5%
1/16W
MF-LF

402

1 2

REFERENCE DESIGNATOR(S)

1

R2717

10K

5%
1/16W
MF-LF
402

2

NOSTUFF

R2720

27

5%
1/16W
MF-LF

402

U2700

U2700

U2700

NOSTUFF

1

R2718

10K

5%
1/16W
MF-LF
402

2

CRITICAL BOM OPTION

CRITICAL

CRITICAL

CRITICAL

=PP3V3_S3_USB_HUB

NOSTUFF

1

R2719

10K

5%
1/16W
MF-LF
402

2

USB_TPAD_R_N

USB_TPAD_R_P

USBHUB2514B

USBHUB2513B

USBHUB2512B

53 95

BI

TO TP/KB

53 95

BI

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

D

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

7

25

C

101

101

B

1

C2715

0.1UF

10%
16V

2

X7R-CERM

BYPASS=U2700.26::2MM

A

402

USB XHCI/EHCI2 PORT MUX FOR EXT B

=PP3V3_S3_USBMUX

7

1

PCH PORT 9 (EHCI2)

PCH PORT 1 (XHCI)

C2760

0.1UF

20%
10V

2

CERM

18 95

BI

18 95

BI

18 95

BI

18 95

BI

USB_EXTB_EHCI_P
USB_EXTB_EHCI_N

USB_EXTB_XHCI_P
USB_EXTB_XHCI_N

402

5
4

7
6

8

6 3

M+
M-

U2760

PI3USB102ZLE
D+
D-

9

VCC

TQFN

CRITICAL

GND

3

1

Y+

2

Y-

PULL-UP TO 3.3V SUS ON PCH PAGE, SEL PIN IS LEAKAGE-SAFE

10

SELOE*

USB_EXTB_MUX_P
USB_EXTB_MUX_N

USB_EXTB_SEL_XHCI

SEL=0 CHOOSE USB EHCI2 PORT
SEL=1 CHOOSE USB XHCI PORT

43 95

BI

43 95

BI

16

IN

TO CONNECTOR

PCH GPIO60

SYNC_MASTER=J31_LINDA

PAGE TITLE

USB HUB & MUX

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=09/16/2011

DRAWING NUMBER

051-9585

REVISION

3.0.0

BRANCH

PAGE

27 OF 132

SHEET

25 OF 105

124578

SIZE

A

D

www.vinafix.vn

8 7 6 5 4 3

The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well
as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.

ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.

D

WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated.
WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.

P1V5CPU_EN = (ISOLATE_CPU_MEM_L + PM_SLP_S3_L) * PM_SLP_S4_L
MEMVTT_EN = (ISOLATE_CPU_MEM_L + PLT_RST_L) * PM_SLP_S3_L
MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L

PM_SLP_S4_L

17 32 45 74

IN

CPUMEM_S0

SSM6N37FEAPE

=PP3V3_S3_MEMRESET

7

C

ISOLATE_CPU_MEM_L

23

IN IN

=PP5V_S3_MEMRESET

7

26

CPUMEM_S0

1

R2815

100K

5%
1/16W
MF-LF

402

2

CRITICAL

CPUMEM_S0

Q2815

SSM6N37FEAPE

D

6

CPU_MEM_RESET_L

MAKE_BASE=TRUE

2

S G

1

SOT563

B

NOSTUFF

1

C2817

0.047UF

10%

6.3V

2

X5R
201

MEMRESET_ISOL_LS5V_L

31

OUT

=MEM_RESET_L

10

IN

CPUMEM_S0

R2801

CPUMEM_S0

CRITICAL

SSM6N37FEAPE

Q2800

SOT563

5

CPUMEM_S0

R2802

CPUMEM_S0

SSM6N37FEAPE

CRITICAL

SOT563

2

CRITICAL

CPUMEM_S0

Q2815

SSM6N37FEAPE

5

S G

4

100K

1/16W
MF-LF

100K

1/16W
MF-LF

Q2800

SOT563

1

5%

402

2

D

SG

1

5%

402

2

D

SG

3

P1V5CPU_EN_L

3

4

MEMVTT_EN_L

6

1

D

CRITICAL

CPUMEM_S0

SSM6N37FEAPE

CRITICAL

=PP1V5_S3_MEMRESET

CPUMEM_S0

1

R2816

1K

5%
1/16W
MF-LF
402

2

Q2805

SOT563

2

SSM6N37FEAPE

3

D

S G

4

Q2810

SOT563

2

SSM6N37FEAPE

3

D

S G

4

1

2

CPUMEM_S3

R2817

0

1 2

5%
1/16W
MF-LF

402

Step ISOLATE_CPU_MEM_L PLT_RESET_L PM_SLP_S3_L PM_SLP_S4_L CPU_MEM_RESET_L MEM_RESET_L MEMVTT_EN P1V5CPU_EN

0 1 1 1 1 1 CPU_MEM_RESET_L 1 1

S0

1 0 1 1 1 1 1 1 1

to

2 0 0 1 1 1 1 0 1

A

3 0 0 0 1 X 1 0 0

S3

4 0 0 1 1 X 1 0 1
5 0 1 1 1 0 (*) 1 1 1

to

6 0 1 1 1 1 1 1 1
7 1 1 1 1 1 CPU_MEM_RESET_L 1 1

S0

(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO.

NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0
transition. Rails will power-up as if from S3, but MEM_RESET_L will not properly assert. Software
must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.

6 3

D

SG

Q2805

SOT563

D

SG

Q2810

SOT563

CPUMEM_S0

C2816

0.1UF

10%
16V
X5R
402

CPUMEM_S0

1

R2805

10K

5%
1/16W
MF-LF
402

2

P1V5CPU_EN

6

1

CPUMEM_S0

5

PM_SLP_S3_L

CPUMEM_S0

1

R2810

10K

5%
1/16W
MF-LF
402

2

MEMVTT_EN

6

1

5

PLT_RESET_L

7

CRITICAL

CPUMEM_S0

CRITICAL

MEM_RESET_L

12

D

1V5 S0 "PGOOD" for CPU

=PP3V3_S5_CPU_VCCDDR

7

PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page

=PP1V5_S3_CPU_VCCDDR

7

10 13 15

73

OUT

R2820

27.4K

1/16W
MF-LF

1

1%

402

2

P1V5_S0_DIV

NO STUFF

1

R2821

33.2K

1%
1/16W
MF-LF

402

2

6

17 45 74

8

OUT

C2820

0.001UF

1

20%
50V

2

CERM

402

5

1

R2822

10K

5%
1/16W
MF-LF
402

2

PM_MEM_PWRGD_L

CRITICAL

3

Q2820

DMB53D0UV

SOT-563

4

CRITICAL

G

2

PM_MEM_PWRGD

6

D

Q2820

DMB53D0UV

SOT-563

S

1

10 17 93

OUT

C

MEMVTT Clamp

Ensures CKE signals are held low in S3

=PPVTT_S0_VTTCLAMP

7

CRITICAL

CPUMEM_S0

NO STUFF

C2851

0.001UF

SSM6N37FEAPE

20%
50V

CERM

402

2

1

2

SOT563

Q2850

=PP5V_S3_MEMRESET

7

26

18 24

IN

27 29

OUT

=DDRVTT_EN

8

68

IN

CPUMEM_S0

R2851

CPUMEM_S0

CRITICAL

SSM6N37FEAPE

Q2850

SOT563

5

100K

1/16W
MF-LF

5%

402

D

SG

1

2

VTTCLAMP_EN

3

4

6

D

SG

1

CPUMEM_S0

VTTCLAMP_L

1

R2850

10

75mA max load @ 0.75V

5%

60mW max power

1/10W
MF-LF

603

2

SYNC_MASTER=K18_MLB

PAGE TITLE

CPU Memory S3 Support

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=04/27/2010

DRAWING NUMBER

051-9585

REVISION

3.0.0

BRANCH

PAGE

28 OF 132

SHEET

26 OF 105

SIZE

B

A

D

124578

www.vinafix.vn

8 7 6 5 4 3

12

Power aliases required by this page:

- =PP1V5_S0_MEM_A

- =PP1V5_S3_MEM_A

- =PP0V75_S0_MEM_VTT_A

- =PPSPD_S0_MEM_A (2.5 - 3.3V)

Signal aliases required by this page:

- =I2C_SODIMMA_SCL

- =I2C_SODIMMA_SDA

BOM options provided by this page:

D

(NONE)

C

B

A

Page Notes

=PPSPD_S0_MEM_A

7

1

2

C2940

2.2UF

20%

6.3V
CERM
402-LF

11 94

11 94

11 94

11 94

11 94

11 94

11 94

11 94

11 94

11 94

11 94

11 94

11 94

11 94

11 94

11 94

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

1

R2940

10K

2

=PP1V5_S3_MEM_A

7

1

2

PLACE_NEAR=J2900.75:2.54mm

1

C2900

10UF 10UF

20%

6.3V

2

X5R
603

PLACE_NEAR=J2900.75:2.54mm

1

C2901

2

20%

6.3V
X5R
603

PLACE_NEAR=J2900.75:2.54mm
PLACE_NEAR=J2900.75:2.54mm

OMIT_TABLE

CKE0

VDD
NC

BA2

VDD
A12/BC*
A9

VDD
A8
A5

VDD
A3
A1

VDD
CK0
CK0*

VDD
A10/AP
BA0

VDD
WE*
CAS*

VDD
A13
S1*

VDD
TEST

VSS
DQ32
DQ33

VSS
DQS4*
DQS4

VSS
DQ34
DQ35

VSS
DQ40
DQ41

VSS
DM5

VSS
DQ42
DQ43

VSS
DQ48
DQ49

VSS
DQS6*
DQS6

VSS
DQ50
DQ51

VSS
DQ56
DQ57

VSS
DM7

VSS
DQ58
DQ59

VSS
SA0
VDDSPD
SA1

VTT

KEY

J2900

F-RT-THB

(SYMBOL 2 OF 2)

DDR3-SODIMM-DUAL-K6

VREFCA

EVENT*

516-0229

CKE1

VDD

VDD

VDD

VDD

CK1*

VDD

RAS*

VDD

ODT0

VDD

ODT1

VDD

VSS
DQ36
DQ37

VSS

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5*

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7*

DQS7

VSS
DQ62
DQ63

VSS

VTT

A15
A14

A11

CK1

BA1

S0*

DM4

DM6

SDA
SCL

VDD

MEM_A_CKE<1>

78

80

8483

86

A7

90

A6

9291

A4

9695

A2

9897

A0

100

102

104

108

110

114

116

120
122

NC

126

130

132

136

138
140

142
144

146

148
150

152

154

158

160

164
166

170
172

174

176
178

180

182
184

186
188

192
194

198
200

NC

MEM_A_A<15>
MEM_A_A<14>

MEM_A_A<11>
MEM_A_A<7>

MEM_A_A<6>
MEM_A_A<4>

MEM_A_A<2>

MEM_A_A<0>

MEM_A_CLK_P<1>

MEM_A_CLK_N<1>

MEM_A_BA<1>

MEM_A_RAS_L

MEM_A_CS_L<0>

MEM_A_ODT<0>

MEM_A_ODT<1>

=MEM_A_DQ<36>

=MEM_A_DQ<37>

=MEM_A_DQ<38>

=MEM_A_DQ<39>

=MEM_A_DQ<44>

=MEM_A_DQ<45>

=MEM_A_DQS_N<5>

=MEM_A_DQS_P<5>

=MEM_A_DQ<46>

=MEM_A_DQ<47>

=MEM_A_DQ<52>

=MEM_A_DQ<53>

=MEM_A_DQ<54>

=MEM_A_DQ<55>

=MEM_A_DQ<60>

=MEM_A_DQ<61>

=MEM_A_DQS_N<7>

=MEM_A_DQS_P<7>

=MEM_A_DQ<62>

=MEM_A_DQ<63>

MEM_EVENT_L

=I2C_SODIMMA_SDA
=I2C_SODIMMA_SCL

MEM_A_CKE<0>

6

IN

MEM_A_BA<2>

6

IN

MEM_A_A<12>

6

IN

MEM_A_A<9>

6

IN

MEM_A_A<8>

6

IN

MEM_A_A<5>

6

IN

MEM_A_A<3>

6

IN

MEM_A_A<1>

6

IN

MEM_A_CLK_P<0>

6

IN

MEM_A_CLK_N<0>

6

IN

MEM_A_A<10>

6

IN

MEM_A_BA<0>

6

IN

MEM_A_WE_L

6

IN

MEM_A_CAS_L

6

IN

MEM_A_A<13>

6

IN

MEM_A_CS_L<1>

6

IN

=MEM_A_DQ<32>

BI

=MEM_A_DQ<33>

BI

=MEM_A_DQS_N<4>

BI

=MEM_A_DQS_P<4>

BI

=MEM_A_DQ<34>

BI

=MEM_A_DQ<35>

BI

=MEM_A_DQ<40>

BI

=MEM_A_DQ<41>

BI

=MEM_A_DQ<42>

BI

=MEM_A_DQ<43>

BI

=MEM_A_DQ<48>

BI

=MEM_A_DQ<49>

BI

=MEM_A_DQS_N<6>

BI

=MEM_A_DQS_P<6>

BI

=MEM_A_DQ<50>

BI

=MEM_A_DQ<51>

BI

=MEM_A_DQ<56>

BI

=MEM_A_DQ<57>

BI

=MEM_A_DQ<58>

BI

=MEM_A_DQ<59>

BI

MEM_A_SA<0>

6

MEM_A_SA<1>

6

1

R2941

10K

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

2

73 74

75 76
77

NC

79

81 82

85

87 88
89

93 94

99

101

103
105 106

107

109
111 112

113

115
117 118

119
121

123 124

125

NC

127 128

129

131
133 134

135

137
139

141
143

145

147
149

151

153
155 156

157

159
161 162

163
165

167 168

169
171

173

175
177

179

181
183

185
187

189 190

191
193

195 196

197
199

201 202

203 204

SPD ADDR=0xA0(WR)/0xA1(RD)

6 3

DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)

C2910

0.1UF

20%
10V
CERM CERM
402

1

2

PP0V75_S3_MEM_VREFDQ_A

31 93

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

29 45 46

OUT

BI
IN

C2911

0.1UF

20%
10V

402

11 94

11 94

11 94

11 94

11 94

11 94

11 94

11 94

11 94

11 94

11 94

11 94

11 94

11 94

11 94

11 94

48

48

1

C2912

0.1UF 0.1UF

20%
10V

2

CERM
402

PLACE_NEAR=J2900.75:2.54mm
PLACE_NEAR=J2900.75:2.54mm

1

2

1

C2950

1UF

10%
10V

2

X5R
402

C2935

2.2UF

20%

6.3V
CERM
402-LF

1

2

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

1

2

C2913

20%
10V
CERM
402

1

C2930

2.2UF

20%

6.3V

2

CERM
402-LF

BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

C2951

1UF

10%
10V
X5R
402

=MEM_A_DQ<0>

=MEM_A_DQ<1>

=MEM_A_DQ<2>
=MEM_A_DQ<3>

=MEM_A_DQ<8>
=MEM_A_DQ<9>

=MEM_A_DQS_N<1>

=MEM_A_DQS_P<1>

=MEM_A_DQ<10>

=MEM_A_DQ<11>

=MEM_A_DQ<16>

=MEM_A_DQ<17>

=MEM_A_DQS_N<2>

=MEM_A_DQS_P<2>

=MEM_A_DQ<18>

=MEM_A_DQ<19>

=MEM_A_DQ<24>

=MEM_A_DQ<25>

=MEM_A_DQ<26>

=MEM_A_DQ<27>

1

2

1

C2914

0.1UF

20%
10V

2

CERM
402

PLACE_NEAR=J2900.75:2.54mm
PLACE_NEAR=J2900.75:2.54mm

1

2

PP0V75_S3_MEM_VREFCA_A

C2936

0.1UF

20%
10V
CERM
402

1

C2952

1UF

10%
10V

2

X5R
402

C2931

0.1UF

20%
10V
CERM
402

1

2

1

2

C2915

0.1UF

20%
10V
CERM
402

1

C2916

0.1UF

20%
10V

2

CERM
402

PLACE_NEAR=J2900.75:2.54mm
PLACE_NEAR=J2900.75:2.54mm

OMIT_TABLE

1 2

VREFDQ

3

VSS

5

DQ0

CRITICAL

7

DQ1

9

VSS

11

13 14
15

17

19 20
21

23

25 26
27

29
31 32

33

35
37 38

39

41
43 44

45

47
49

51
53

55

57
59

61

63
65 66

67

69
71 72

DM0

VSS
DQ2
DQ3

VSS
DQ8
DQ9

VSS
DQS1*
DQS1

VSS
DQ10
DQ11

VSS
DQ16
DQ17

VSS
DQS2*
DQS2

VSS
DQ18
DQ19

VSS
DQ24
DQ25

VSS
DM3

VSS
DQ26
DQ27

VSS

J2900

F-RT-THB

See CSA05 BOM table

31 93

=PP0V75_S0_MEM_VTT_A

C2953

1UF

10%
10V
X5R
402

1

C2917

0.1UF

20%
10V

2

CERM
402

VSS
DQ4
DQ5

VSS

DQS0*

DQS0

VSS

DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

(SYMBOL 1 OF 2)

RESET*

DDR3-SODIMM-DUAL-K6

VSS
DQ14
DQ15

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3*

DQS3

VSS
DQ30
DQ31

VSS

KEY

7

1

C2918

0.1UF

20%
10V

2

CERM
402

PLACE_NEAR=J2900.75:2.54mm
PLACE_NEAR=J2900.75:2.54mm

4
6

8
10

12

16

18

22

24

28

30

34

36

40

42

46

48
50

52
54

56

58
60

62

64

68

70

1

C2919

0.1UF

20%
10V

2

CERM
402

=MEM_A_DQ<4>
=MEM_A_DQ<5>

=MEM_A_DQS_N<0>
=MEM_A_DQS_P<0>

=MEM_A_DQ<6>
=MEM_A_DQ<7>

=MEM_A_DQ<12>
=MEM_A_DQ<13>

MEM_RESET_L

=MEM_A_DQ<14>

=MEM_A_DQ<15>

=MEM_A_DQ<20>

=MEM_A_DQ<21>

=MEM_A_DQ<22>

=MEM_A_DQ<23>

=MEM_A_DQ<28>

=MEM_A_DQ<29>

=MEM_A_DQS_N<3>

=MEM_A_DQS_P<3>

=MEM_A_DQ<30>

=MEM_A_DQ<31>

1

C2920

0.1UF

20%
10V

2

CERM
402

PLACE_NEAR=J2900.75:2.54mm
PLACE_NEAR=J2900.75:2.54mm

BI
BIBI

BI
BI

BI
BI

BI
BI

IN

BI

BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

28

28

28

28

28

28

28

28

26 29

28

28

28

28

28

28

28

28

28

28

28

28

1

C2921

2

0.1UF

20%
10V
CERM
402

1

C2922

2

0.1UF

20%
10V
CERM
402

1

C2923

0.1UF

20%
10V

2

CERM
402

PLACE_NEAR=J2900.75:2.54mm
PLACE_NEAR=J2900.75:2.54mm

"Factory" (top) slot

SYNC_MASTER=K92_SUMA SYNC_DATE=06/23/2010

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DDR3 SO-DIMM Connector A

Apple Inc.

R

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

124578

051-9585

3.0.0

29 OF 132
27 OF 105

SIZE

D

C

B

A

D

www.vinafix.vn

8 7 6 5 4 3

12

CPU CHANNEL A DQS 0 -> DIMM A DQS 0

MEM_A_DQS_N<0>

6

11 94

MEM_A_DQS_P<0>

6

11 94

MEM_A_DQ<7>

6

11 94

MEM_A_DQ<6>

6

11 94

MEM_A_DQ<5>

6

11 94

MEM_A_DQ<4>

6

11 94

MEM_A_DQ<3>

6

11 94

MEM_A_DQ<2>

6

11 94

MEM_A_DQ<1>

6

11 94

MEM_A_DQ<0>

6

D

C

B

A

11 94

CPU CHANNEL A DQS 1 -> DIMM A DQS 1

MEM_A_DQS_N<1>

6

11 94

MEM_A_DQS_P<1>

6

11 94

MEM_A_DQ<15>

6

11 94

MEM_A_DQ<14>

6

11 94

MEM_A_DQ<13>

6

11 94

MEM_A_DQ<12>

6

11 94

MEM_A_DQ<11>

6

11 94

MEM_A_DQ<10>

6

11 94

MEM_A_DQ<9>

6

11 94

MEM_A_DQ<8>

6

11 94

CPU CHANNEL A DQS 2 -> DIMM A DQS 2

MEM_A_DQS_N<2>

6

11 94

MEM_A_DQS_P<2>

6

11 94

MEM_A_DQ<23>

6

11 94

MEM_A_DQ<22>

6

11 94

MEM_A_DQ<21>

6

11 94

MEM_A_DQ<20>

6

11 94

MEM_A_DQ<19>

6

11 94

MEM_A_DQ<18>

6

11 94

MEM_A_DQ<17>

6

11 94

MEM_A_DQ<16>

6

11 94

CPU CHANNEL A DQS 3 -> DIMM A DQS 3

MEM_A_DQS_N<3>

6

11 94

MEM_A_DQS_P<3>

6

11 94

MEM_A_DQ<31>

6

11 94

MEM_A_DQ<30>

6

11 94

MEM_A_DQ<29>

6

11 94

MEM_A_DQ<28>

6

11 94

MEM_A_DQ<27>

6

11 94

MEM_A_DQ<26>

6

11 94

MEM_A_DQ<25>

6

11 94

MEM_A_DQ<24>

6

11 94

CPU CHANNEL A DQS 4 -> DIMM A DQS 4

MEM_A_DQS_N<4>

6

11 94

MEM_A_DQS_P<4>

6

11 94

MEM_A_DQ<39>

6

11 94

MEM_A_DQ<38>

6

11 94

MEM_A_DQ<37>

6

11 94

MEM_A_DQ<36>

6

11 94

MEM_A_DQ<35>

6

11 94

MEM_A_DQ<34>

6

11 94 27

MEM_A_DQ<33>

6

11 94

MEM_A_DQ<32>

6

11 94

CPU CHANNEL A DQS 5 -> DIMM A DQS 5

MEM_A_DQS_N<5>

6

11 94

MEM_A_DQS_P<5>

6

11 94

MEM_A_DQ<47>

6

11 94

MEM_A_DQ<46>

6

11 94

MEM_A_DQ<45>

6

11 94

MEM_A_DQ<44>

6

11 94

MEM_A_DQ<43>

6

11 94

MEM_A_DQ<42>

6

11 94

MEM_A_DQ<41>

6

11 94

MEM_A_DQ<40>

6

11 94

CPU CHANNEL A DQS 6 -> DIMM A DQS 6

MEM_A_DQS_N<6>

6

11 94

MEM_A_DQS_P<6>

6

11 94 27

MEM_A_DQ<55>

6

11 94

MEM_A_DQ<54>

6

11 94

MEM_A_DQ<53>

6

11 94

MEM_A_DQ<52>

6

11 94

MEM_A_DQ<51>

6

11 94

MEM_A_DQ<50>

6

11 94

MEM_A_DQ<49>

6

11 94

MEM_A_DQ<48>

6

11 94

CPU CHANNEL A DQS 7 -> DIMM A DQS 7

MEM_A_DQS_N<7>

6

11 94

MEM_A_DQS_P<7>

6

11 94

MEM_A_DQ<63>

6

11 94

MEM_A_DQ<62>

6

11 94

MEM_A_DQ<61>

6

11 94

MEM_A_DQ<60>

6

11 94

MEM_A_DQ<59>

6

11 94

MEM_A_DQ<58>

6

11 94 27

MEM_A_DQ<57>

6

11 94

MEM_A_DQ<56>

6

11 94

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

=MEM_A_DQS_N<0>

=MEM_A_DQS_P<0>

=MEM_A_DQ<3>

=MEM_A_DQ<6>
=MEM_A_DQ<5>

=MEM_A_DQ<4>

=MEM_A_DQ<7>
=MEM_A_DQ<0>

=MEM_A_DQ<1>
=MEM_A_DQ<2>

=MEM_A_DQS_N<1>

=MEM_A_DQS_P<1>

=MEM_A_DQ<15>

=MEM_A_DQ<14>
=MEM_A_DQ<12>

=MEM_A_DQ<13>

=MEM_A_DQ<10>
=MEM_A_DQ<11>

=MEM_A_DQ<9>
=MEM_A_DQ<8>

=MEM_A_DQS_N<2>

=MEM_A_DQS_P<2>

=MEM_A_DQ<23>

=MEM_A_DQ<22>
=MEM_A_DQ<17>

=MEM_A_DQ<20>
=MEM_A_DQ<19>

=MEM_A_DQ<18>

=MEM_A_DQ<16>
=MEM_A_DQ<21>

=MEM_A_DQS_N<3>

=MEM_A_DQS_P<3>

=MEM_A_DQ<31>

=MEM_A_DQ<30>
=MEM_A_DQ<29>

=MEM_A_DQ<28>
=MEM_A_DQ<27>

=MEM_A_DQ<26>

=MEM_A_DQ<25>
=MEM_A_DQ<24>

=MEM_A_DQS_N<4>

=MEM_A_DQS_P<4>

=MEM_A_DQ<38>
=MEM_A_DQ<37>

=MEM_A_DQ<39>

=MEM_A_DQ<33>
=MEM_A_DQ<35>

=MEM_A_DQ<34>

=MEM_A_DQ<32>
=MEM_A_DQ<36>

=MEM_A_DQS_N<5>

=MEM_A_DQS_P<5>

=MEM_A_DQ<47>
=MEM_A_DQ<41>

=MEM_A_DQ<43>

=MEM_A_DQ<44>
=MEM_A_DQ<40>

=MEM_A_DQ<46>

=MEM_A_DQ<42>
=MEM_A_DQ<45>

=MEM_A_DQS_N<6>
=MEM_A_DQS_P<6>

=MEM_A_DQ<49>
=MEM_A_DQ<54>

=MEM_A_DQ<55>

=MEM_A_DQ<52>
=MEM_A_DQ<51>

=MEM_A_DQ<50>

=MEM_A_DQ<53>
=MEM_A_DQ<48>

=MEM_A_DQS_N<7>
=MEM_A_DQS_P<7>

=MEM_A_DQ<59>
=MEM_A_DQ<58>

=MEM_A_DQ<56>

=MEM_A_DQ<61>
=MEM_A_DQ<63>

=MEM_A_DQ<62>

=MEM_A_DQ<57>
=MEM_A_DQ<60>

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

CPU CHANNEL B DQS 0 -> DIMM B DQS 0

MEM_B_DQS_N<0>

6

11 94

MEM_B_DQS_P<0>

6

11 94

MEM_B_DQ<7>

6

11 94

MEM_B_DQ<6>

6

11 94

MEM_B_DQ<5>

6

11 94

MEM_B_DQ<4>

6

11 94

MEM_B_DQ<3>

6

11 94

MEM_B_DQ<2>

6

11 94

MEM_B_DQ<1>

6

11 94

MEM_B_DQ<0>

6

11 94

CPU CHANNEL B DQS 1 -> DIMM B DQS 1

MEM_B_DQS_N<1>

6

11 94

MEM_B_DQS_P<1>

6

11 94

MEM_B_DQ<15>

6

11 94

MEM_B_DQ<14>

6

11 94

MEM_B_DQ<13>

6

11 94

MEM_B_DQ<12>

6

11 94

MEM_B_DQ<11>

6

11 94

MEM_B_DQ<10>

6

11 94

MEM_B_DQ<9>

6

11 94

MEM_B_DQ<8>

6

11 94

CPU CHANNEL B DQS 2 -> DIMM B DQS 2

MEM_B_DQS_N<2>

6

11 94

MEM_B_DQS_P<2>

6

11 94

MEM_B_DQ<23>

6

11 94

MEM_B_DQ<22>

6

11 94

MEM_B_DQ<21>

6

11 94

MEM_B_DQ<20>

6

11 94

MEM_B_DQ<19>

6

11 94

MEM_B_DQ<18>

6

11 94

MEM_B_DQ<17>

6

11 94

MEM_B_DQ<16>

6

11 94

CPU CHANNEL B DQS 3 -> DIMM B DQS 3

MEM_B_DQS_N<3>

6

11 94

MEM_B_DQS_P<3>

6

11 94

MEM_B_DQ<31>

6

11 94

MEM_B_DQ<30>

6

11 94

MEM_B_DQ<29>

6

11 94

MEM_B_DQ<28>

6

11 94

MEM_B_DQ<27>

6

11 94

MEM_B_DQ<26>

6

11 94

MEM_B_DQ<25>

6

11 94

MEM_B_DQ<24>

6

11 94

CPU CHANNEL B DQS 4 -> DIMM B DQS 4

MEM_B_DQS_N<4>

6

11 94

MEM_B_DQS_P<4>

6

11 94

MEM_B_DQ<39>

6

11 94

MEM_B_DQ<38>

6

11 94

MEM_B_DQ<37>

6

11 94

MEM_B_DQ<36>

6

11 94

MEM_B_DQ<35>

6

11 94

MEM_B_DQ<34>

6

11 94

MEM_B_DQ<33>

6

11 94

MEM_B_DQ<32>

6

11 94

CPU CHANNEL B DQS 5 -> DIMM B DQS 5

MEM_B_DQS_N<5>

6

11 94

MEM_B_DQS_P<5>

6

11 94

MEM_B_DQ<47>

6

11 94

MEM_B_DQ<46>

6

11 94

MEM_B_DQ<45>

6

11 94

MEM_B_DQ<44>

6

11 94

MEM_B_DQ<43>

6

11 94

MEM_B_DQ<42>

6

11 94

MEM_B_DQ<41>

6

11 94

MEM_B_DQ<40>

6

11 94

CPU CHANNEL B DQS 6 -> DIMM B DQS 6

MEM_B_DQS_N<6>

6

11 94

MEM_B_DQS_P<6>

6

11 94

MEM_B_DQ<55>

6

11 94

MEM_B_DQ<54>

6

11 94

MEM_B_DQ<53>

6

11 94

MEM_B_DQ<52>

6

11 94

MEM_B_DQ<51>

6

11 94

MEM_B_DQ<50>

6

11 94

MEM_B_DQ<49>

6

11 94

MEM_B_DQ<48>

6

11 94

CPU CHANNEL B DQS 7 -> DIMM B DQS 7

MEM_B_DQS_N<7>

6

11 94

MEM_B_DQS_P<7>

6

11 94

MEM_B_DQ<63>

6

11 94

MEM_B_DQ<62>

6

11 94

MEM_B_DQ<61>

6

11 94

MEM_B_DQ<60>

6

11 94

MEM_B_DQ<59>

6

11 94

MEM_B_DQ<58>

6

11 94

MEM_B_DQ<57>

6

11 94

MEM_B_DQ<56>

6

11 94

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

=MEM_B_DQS_N<0>

=MEM_B_DQS_P<0>

=MEM_B_DQ<6>

=MEM_B_DQ<3>
=MEM_B_DQ<5>

=MEM_B_DQ<4>

=MEM_B_DQ<1>
=MEM_B_DQ<7>

=MEM_B_DQ<2>
=MEM_B_DQ<0>

=MEM_B_DQS_N<1>

=MEM_B_DQS_P<1>

=MEM_B_DQ<15>

=MEM_B_DQ<14>
=MEM_B_DQ<13>

=MEM_B_DQ<12>

=MEM_B_DQ<11>
=MEM_B_DQ<10>

=MEM_B_DQ<9>
=MEM_B_DQ<8>

=MEM_B_DQS_N<2>

=MEM_B_DQS_P<2>

=MEM_B_DQ<23>

=MEM_B_DQ<22>
=MEM_B_DQ<21>

=MEM_B_DQ<20>
=MEM_B_DQ<19>

=MEM_B_DQ<18>

=MEM_B_DQ<17>
=MEM_B_DQ<16>

=MEM_B_DQS_N<3>

=MEM_B_DQS_P<3>

=MEM_B_DQ<31>

=MEM_B_DQ<30>
=MEM_B_DQ<29>

=MEM_B_DQ<28>
=MEM_B_DQ<27>

=MEM_B_DQ<26>

=MEM_B_DQ<25>
=MEM_B_DQ<24>

=MEM_B_DQS_N<4>

=MEM_B_DQS_P<4>

=MEM_B_DQ<39>
=MEM_B_DQ<38>

=MEM_B_DQ<37>

=MEM_B_DQ<36>
=MEM_B_DQ<35>

=MEM_B_DQ<34>

=MEM_B_DQ<33>
=MEM_B_DQ<32>

=MEM_B_DQS_N<5>

=MEM_B_DQS_P<5>

=MEM_B_DQ<47>
=MEM_B_DQ<46>

=MEM_B_DQ<45>

=MEM_B_DQ<44>
=MEM_B_DQ<43>

=MEM_B_DQ<42>

=MEM_B_DQ<41>
=MEM_B_DQ<40>

=MEM_B_DQS_N<6>
=MEM_B_DQS_P<6>

=MEM_B_DQ<55>
=MEM_B_DQ<54>

=MEM_B_DQ<53>

=MEM_B_DQ<52>
=MEM_B_DQ<51>

=MEM_B_DQ<50>

=MEM_B_DQ<49>
=MEM_B_DQ<48>

=MEM_B_DQS_N<7>
=MEM_B_DQS_P<7>

=MEM_B_DQ<63>
=MEM_B_DQ<62>

=MEM_B_DQ<61>

=MEM_B_DQ<60>
=MEM_B_DQ<59>

=MEM_B_DQ<58>

=MEM_B_DQ<57>
=MEM_B_DQ<56>

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

6 3

SYNC_MASTER=K92_SUMA SYNC_DATE=05/10/2010

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DDR3 Byte/Bit Swaps

Apple Inc.

R

DRAWING NUMBER

051-9585

REVISION

3.0.0

BRANCH

PAGE

30 OF 132

SHEET

28 OF 105

124578

SIZE

D

C

B

A

D

www.vinafix.vn

8 7 6 5 4 3

12

D

C

B

A

Page Notes

Power aliases required by this page:

- =PP1V5_S0_MEM_B

- =PP1V5_S3_MEM_B

- =PP0V75_S0_MEM_VTT_B

- =PPSPD_S0_MEM_B (2.5 - 3.3V)

Signal aliases required by this page:

- =I2C_SODIMMB_SCL

- =I2C_SODIMMB_SDA

BOM options provided by this page:

(NONE)

=PPSPD_S0_MEM_B

7

1

2

C3140

2.2UF

20%

6.3V
CERM
402-LF

1

2

R3140

10K

5%
1/16W
MF-LF
402

=PP1V5_S3_MEM_B

7

PLACE_NEAR=J3100.75:2.54mm

1

C3100

10UF

20%

6.3V

2

X5R
603

PLACE_NEAR=J3100.75:2.54mm

1

C3101

10UF

20%

6.3V

2

X5R
603

OMIT_TABLE

MEM_B_CKE<0>

6

11 94

IN

MEM_B_BA<2>

6

11 94

IN

MEM_B_A<12>

6

11 94

IN

MEM_B_A<9>

6

11 94

IN

MEM_B_A<8>

6

11 94

IN

MEM_B_A<5>

6

11 94

IN

MEM_B_A<3>

6

11 94

IN

MEM_B_A<1>

6

11 94

IN

MEM_B_CLK_P<0>

6

11 94

IN

MEM_B_CLK_N<0>

6

11 94

IN

MEM_B_A<10>

6

11 94

IN

MEM_B_BA<0>

6

11 94

IN

MEM_B_WE_L

6

11 94

IN

MEM_B_CAS_L

6

11 94

IN

MEM_B_A<13>

6

11 94

IN

MEM_B_CS_L<1>

6

11 94

IN

=MEM_B_DQ<32>

28

BI

=MEM_B_DQ<33>

28

BI

=MEM_B_DQS_N<4>

28

BI

=MEM_B_DQS_P<4>

28

BI

=MEM_B_DQ<34>

28

BI

=MEM_B_DQ<35>

28

BI

=MEM_B_DQ<40>

28

BI

=MEM_B_DQ<41>

28

BI

=MEM_B_DQ<42>

28

BI

=MEM_B_DQ<43>

28

BI

=MEM_B_DQ<48>

28

BI

=MEM_B_DQ<49>

28

BI

=MEM_B_DQS_N<6>

28

BI

=MEM_B_DQS_P<6>

28

BI

=MEM_B_DQ<50>

28

BI

=MEM_B_DQ<51>

28

BI

=MEM_B_DQ<56>

28

BI

=MEM_B_DQ<57>

28

BI

=MEM_B_DQ<58>

28

BI

=MEM_B_DQ<59>

28

BI

MEM_B_SA<0>

6

MEM_B_SA<1>

6

1

R3141

10K

5%
1/16W
MF-LF
402

2

73 74

75 76
77

NC

79

81 82

85

87 88
89

93 94

99

101

103
105 106

107

109
111 112

113

115
117 118

119
121

123 124

125

NC

127 128

129

131
133 134

135

137
139

141
143

145

147
149

151

153
155 156

157

159
161 162

163
165

167 168

169
171

173

175
177

179

181
183

185
187

189 190

191
193

195 196

197
199

201 202

203 204

205 206
207 208

209 210
211 212

SPD ADDR=0xA4(WR)/0xA5(RD)

KEY

CKE0

VDD
NC

BA2

J3100

VDD

F-RT-BGA6

A12/BC*
A9

VDD
A8
A5

VDD
A3
A1

VDD
CK0
CK0*

VDD
A10/AP
BA0

VDD
WE*
CAS*

VDD
A13
S1*

VDD
TEST

VSS
DQ32
DQ33

VSS
DQS4*
DQS4

VSS
DQ34
DQ35

VSS
DQ40
DQ41

VSS
DM5

VSS
DQ42
DQ43

VSS
DQ48
DQ49

VSS
DQS6*
DQS6

VSS
DQ50
DQ51

VSS
DQ56
DQ57

VSS
DM7

VSS
DQ58
DQ59

VSS
SA0
VDDSPD
SA1

VTT

MTG PIN

MTG PIN

MTG PIN MTG PIN

MTG PIN

MTG PINS

516S0806

(2 OF 2)

DDR3-SODIMM

VREFCA

DQS5*

DQS7*

EVENT*

MTG PIN

MTG PIN

MTG PIN

CKE1

VDD

VDD

VDD

VDD

CK1*

VDD

RAS*

VDD

ODT0

VDD

ODT1

VDD

VSS
DQ36
DQ37

VSS

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7

VSS
DQ62
DQ63

VSS

VTT

A15
A14

A11

CK1

BA1

S0*

DM4

DM6

SDA
SCL

VDD

78

80

8483

86

A7

90

A6

9291

A4

9695

A2

9897

A0

100

102

104

108

110

114

116

120
122

NC

NC

126

130

132

136

138
140

142
144

146

148
150

152

154

158

160

164
166

170
172

174

176
178

180

182
184

186
188

192
194

198
200

6 3

DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)

1

C3110

0.1UF

20%
10V

2

CERM
402

PLACE_NEAR=J3100.75:2.54mm
PLACE_NEAR=J3100.75:2.54mm

MEM_B_CKE<1>

MEM_B_A<15>
MEM_B_A<14>

MEM_B_A<11>
MEM_B_A<7>

MEM_B_A<6>
MEM_B_A<4>

MEM_B_A<2>

MEM_B_A<0>

MEM_B_CLK_P<1>

MEM_B_CLK_N<1>

MEM_B_BA<1>

MEM_B_RAS_L

MEM_B_CS_L<0>

MEM_B_ODT<0>

MEM_B_ODT<1>

=MEM_B_DQ<36>

=MEM_B_DQ<37>

=MEM_B_DQ<38>

=MEM_B_DQ<39>

=MEM_B_DQ<44>

=MEM_B_DQ<45>

=MEM_B_DQS_N<5>

=MEM_B_DQS_P<5>

=MEM_B_DQ<46>

=MEM_B_DQ<47>

=MEM_B_DQ<52>

=MEM_B_DQ<53>

=MEM_B_DQ<54>

=MEM_B_DQ<55>

=MEM_B_DQ<60>

=MEM_B_DQ<61>

=MEM_B_DQS_N<7>

=MEM_B_DQS_P<7>

=MEM_B_DQ<62>

=MEM_B_DQ<63>

MEM_EVENT_L

=I2C_SODIMMB_SDA
=I2C_SODIMMB_SCL

PP0V75_S3_MEM_VREFDQ_B

31 93

IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

OUT

1

C3150

1UF

10%
10V

2

X5R
402

1

C3111

0.1UF

20%
10V

2

CERM
402

PLACE_NEAR=J3100.75:2.54mm
PLACE_NEAR=J3100.75:2.54mm

6

11 94

6

11 94

6

11 94

6

11 94

6

11 94

6

11 94

6

11 94

6

11 94

6

11 94

6

11 94

6

11 94

6

11 94

6

11 94

6

11 94

6

11 94

6

11 94

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

27 45 46

48

BI

48

IN

1

C3151

1UF

10%
10V

2

X5R
402

1

C3112

0.1UF

20%
10V

2

CERM
402

1

C3152

1UF

10%
10V

2

X5R
402

1

2

C3135

2.2UF

20%

6.3V
CERM
402-LF

1

2

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

C3113

0.1UF

20%
10V
CERM
402

1

C3130

2

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

1

C3114

0.1UF

20%
10V

2

CERM
402

PLACE_NEAR=J3100.75:2.54mm
PLACE_NEAR=J3100.75:2.54mm

1

C3131

=MEM_B_DQ<0>

=MEM_B_DQ<1>

=MEM_B_DQ<2>
=MEM_B_DQ<3>

=MEM_B_DQ<8>
=MEM_B_DQ<9>

=MEM_B_DQS_N<1>

=MEM_B_DQS_P<1>

=MEM_B_DQ<10>

=MEM_B_DQ<11>

=MEM_B_DQ<16>

=MEM_B_DQ<17>

=MEM_B_DQS_N<2>

=MEM_B_DQS_P<2>

=MEM_B_DQ<18>

=MEM_B_DQ<19>

=MEM_B_DQ<24>

=MEM_B_DQ<25>

=MEM_B_DQ<26>

=MEM_B_DQ<27>

1

C3136

0.1UF

20%
10V

2

CERM
402

0.1UF

20%
10V

2

CERM
402

PP0V75_S3_MEM_VREFCA_B

2.2UF

20%

6.3V
CERM
402-LF

=PP0V75_S0_MEM_VTT_B

1

C3153

1UF

10%
10V

2

X5R
402

1

2

C3115

0.1UF

20%
10V
CERM
402

1

C3116

0.1UF

20%
10V

2

CERM
402

PLACE_NEAR=J3100.75:2.54mm
PLACE_NEAR=J3100.75:2.54mm

OMIT_TABLE

1 2

VREFDQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13 14

VSS

15

DQ2

17

DQ3

19 20

VSS

21

DQ8

23

DQ9

25 26

VSS

27

DQS1*

29

DQS1

31 32

VSS

33

DQ10

35

DQ11

37 38

VSS

39

DQ16

41

DQ17

43 44

VSS

45

DQS2*

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65 66

VSS

67

DQ26

69

DQ27

71 72

VSS

7

CRITICAL

J3100

F-RT-BGA6

KEY

516S0806

31 93

1

C3117

0.1UF

20%
10V

2

CERM
402

VSS
DQ4
DQ5

VSS

DQS0*

DQS0

VSS

DQ6
DQ7

VSS

(1 OF 2)

DQ12

DDR3-SODIMM

DQ13

VSS

DM1

RESET*

VSS
DQ14
DQ15

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3*

DQS3

VSS
DQ30
DQ31

VSS

1

C3118

0.1UF

20%
10V

2

CERM
402

PLACE_NEAR=J3100.75:2.54mm
PLACE_NEAR=J3100.75:2.54mm

4
6

8
10

12

16

18

22

24

28

30

34

36

40

42

46

48
50

52
54

56

58
60

62

64

68

70

1

C3119

0.1UF

20%
10V

2

CERM
402

=MEM_B_DQ<4>
=MEM_B_DQ<5>

=MEM_B_DQS_N<0>
=MEM_B_DQS_P<0>

=MEM_B_DQ<6>
=MEM_B_DQ<7>

=MEM_B_DQ<12>
=MEM_B_DQ<13>

MEM_RESET_L

=MEM_B_DQ<14>

=MEM_B_DQ<15>

=MEM_B_DQ<20>

=MEM_B_DQ<21>

=MEM_B_DQ<22>

=MEM_B_DQ<23>

=MEM_B_DQ<28>

=MEM_B_DQ<29>

=MEM_B_DQS_N<3>

=MEM_B_DQS_P<3>

=MEM_B_DQ<30>

=MEM_B_DQ<31>

1

C3120

0.1UF

20%
10V

2

CERM
402

PLACE_NEAR=J3100.75:2.54mm
PLACE_NEAR=J3100.75:2.54mm

28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

26 27

IN

28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

1

C3121

0.1UF

20%
10V

2

CERM
402

1

C3122

0.1UF

2

1

C3123

20%
10V
CERM
402

2

0.1UF

20%
10V
CERM
402

"Expansion" (bottom) slot

PAGE TITLE

DDR3 SO-DIMM Connector B

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

PLACE_NEAR=J3100.75:2.54mm
PLACE_NEAR=J3100.75:2.54mm

SYNC_DATE=06/23/2010SYNC_MASTER=K92_SUMA

DRAWING NUMBER

051-9585

REVISION

BRANCH

PAGE

31 OF 132

SHEET

29 OF 105

124578

3.0.0

SIZE

D

C

B

A

D

www.vinafix.vn

8 7 6 5 4 3

12

SD Card Connector

516-0225

CRITICAL

J3300

SD-CARD-K19-K24

CRITICAL

L3300

SDCONN_CLK

36 97

IN

SDCONN_CMD

36 97

OUT

SDCONN_DATA<0>

36 97

D

BI

SDCONN_DATA<1>

36 97

BI

SDCONN_DATA<2>

36 97

BI

SDCONN_DATA<3>

36 97

BI

SDCONN_DATA<4>

36 97

BI

SDCONN_DATA<5>

36 97

BI

SDCONN_DATA<6>

36 97

BI

SDCONN_DATA<7>

36 97

BI

SDCONN_CARDDETECT_L

30

OUT

36

OUT

30

R3379
R3361
R3371
R3372
R3373
R3374
R3375
R3376
R3377
R3378

1 2

33

1 2

33

1 2

33

1 2

33

1 2

33

1 2

33

1 2

33

1 2

33

1 2

33

1 2

33

Place near attr for series resistors:

PLACE_NEAR=U3900.21:5MM
PLACE_NEAR=U3900.26:5MM
PLACE_NEAR=U3900.25:5MM
PLACE_NEAR=U3900.24:5MM
PLACE_NEAR=U3900.23:5MM
PLACE_NEAR=U3900.22:5MM
PLACE_NEAR=U3900.52:5MM
PLACE_NEAR=U3900.53:5MM
PLACE_NEAR=U3900.54:5MM
PLACE_NEAR=U3900.55:5MM

MF-LF

1/16W5%
1/16W

5%

1/16W

5%

1/16W5%
1/16W5%
1/16W5%
1/16W5%
1/16W5%
1/16W5%
1/16W5%

MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF

402
402
402
402
402
402
402
402
402
402

SDCONN_CLK_R

97

SDCONN_CMD_R
SDCONN_R_DATA<0>

97

SDCONN_R_DATA<1>

97

SDCONN_R_DATA<2>

97

SDCONN_R_DATA<3>

97

SDCONN_R_DATA<4>

97

SDCONN_R_DATA<5>

97

SDCONN_R_DATA<6>

97

SDCONN_R_DATA<7>

97

SDCONN_WP
=PP3V3_S0_SW_SD_PWR

1

C3372

10PF

5%
25V

2

CER
0201

1

C3373

10PF

5%
25V

2

CER
0201

NOSTUFF

NOSTUFF

1

C3374

10PF

5%
25V

2

CER
0201

1

C3375

10PF

5%
25V

2

CER
0201

NOSTUFF

NOSTUFF

NOSTUFF

1

C3377

10PF

5% 5%
25V

2

CER
0201

NOSTUFF

1

C3376

10PF

5%
25V

2

CER
0201

1

C3378

10PF

5%
25V

2

CER
0201

NOSTUFF

1

C3379

10PF

25V

2

CER
0201

NOSTUFF

1

C3380

10PF

5%
25V

2

CER
0201

NOSTUFF

1

C3381

10PF

5%
25V

2

CER
0201

NOSTUFF

47NH-1.3OHM

1 2

NOSTUFF

1

C3371

22PF

5%
50V

2

CERM
402

0402

SDCONN_CLK_R_L

97

NOSTUFF

1

C3370

15PF

5%
50V

2

CERM
402

F-RT-TH

3

VSS

6

VSS

5

CLK

2

CMD

7

DAT0

8

DAT1

9

DAT2

1

CD/DAT3

10

DAT4

11

DAT5

12

DAT6

13

DAT7

14

CARD_DETECT_SW

15

CARD_DETECT_GND

16

WRITE_PROTECT_SW

4

VDD

17

SHLD_PIN

18

SHLD_PIN

19

SHLD_PIN

20

SHLD_PIN

SD Not Inserted, CARD_DETECT is OPEN.
CAESAR-IV Card Detect is programmable,
but a Silicon bug makes the active
high case unusable.

D

C

C

SD Detect & Reset Logic

SDCONN_DETECT Debounce, Inversion, Detect-Changed PCH GPIO Latch Circuit
Converts SDCONN from active-low level signal to active-high pulses.

=PP3V3_S4_SD_HPD

7

1

C3310

R3311 and R3310 mutually exclusive
to control effect of =ENET_RESET_L
on DET_CHANGED# logic.

ENET_LOW_PWR

24 36

IN

=ENET_RESET_L

24

-> From PCH GPI0

-> From SD Conn
(Low active)

IN

SDCONN_CARDDETECT_L

30

IN

B

R3311

0

1 2

5%
1/16W
MF-LF

402

SLG_ENET_RESET_IN_L

1

R3310

10K

5%
1/16W
MF-LF
402

2

NOSTUFF

1UF

10%
10V

2

X5R

402-1

SD_DET_LVL_L

1

R3316

10K

5%
1/16W
MF-LF
402

2

2

3

7

1

LOW_PWR

RST_IN*

DET_IN

(IPU)

DET_LVL

VDD

U3311

SLG4AP026V

TDFN

RST

LOGIC

DLY

XOR

GND

5

10

XOR

CRITICAL

RST_OUT*

DET_CH_EN*

(OD)

DET_CHNGD*

(OD)

DET_OUT

THRM

PAD

11

4

SLG_ENET_RESET_OUT_L

6

SD_DET_CH_EN_L

9

SDCONN_STATE_CHANGE_SMC

8

SDCONN_DETECT_L

R3314

0

1 2

5%
1/16W
MF-LF

402

1

R3317

10K

5%
1/16W
MF-LF
402

2

1

R3315

10K

5%
1/16W
MF-LF
402

2

ENET_RESET_L

1

R3312

0

5%
1/16W
MF-LF
402

2

NOSTUFF

Must STUFF R3312 and NOSTUFF R3314
when R3311 is NOT STUFFED.
R3314 and R3312 mutually exclusive
to bypass reset logic

36 97

OUT

-> To SMC & to Isolation Circuit (then to PCH GPIO)

24 46

OUT

36

OUT

DLY block is 20ms nominal
When ENET_LOW_PWR deasserts, RST_OUT#
deasserts for >80ms, then asserts for
10ms regardless ofmove RST_IN# state.
Otherwise RST_OUT# follows RST_IN#

(Low active pulse signal)

-> To ENET Chip

B

SD Card 3.3V Overcurrent Protection

TPS2065-1 (1.0A limit) has active load discharge so R4810 is NOSTUFF.

CRITICAL

1

5%

402

2

=PP3V3_S0_SW_SD_PWR

PP3V3_S0_SW_SD_PWR

MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

=PP3V3_S0_PCH_GPIO

SDCONN_OC_L

U3300

TPS2065-1

2

=PP3V3_S0_SDCARD

7

ENET_CR_PWREN

A

36

CRITICAL

1

C3300

10UF

20%

6.3V

2

X5R
603

1

C3301

0.1UF

10%
16V

2

X7R-CERM
402

IN0

3

IN1

4

EN

GND

1

DGN

THRM

OUT0
OUT1
OUT2

OC*

PAD

353S3004

9

6
7
8

5

CRITICAL

1

C3302

10UF

20%

6.3V

2

X5R
603

1

C3303

0.1UF

10%
16V

2

X7R-CERM
402

SDCONN_OC_L_R

NOSTUFF

1

R3300

47K

5%
1/16W
MF-LF
402

2

R3302

0

1 2

5%
1/16W
MF-LF

402

R3301

10K

1/16W
MF-LF

6 3

30

7

16 17 18 19

SYNC_MASTER=J31_YONAS

PAGE TITLE

SD Card Connector

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=10/25/2011

DRAWING NUMBER

051-9585

REVISION

3.0.0

BRANCH

PAGE

33 OF 132

SHEET

30 OF 105

124578

SIZE

A

D

www.vinafix.vn