Rockwell Automation 1746-HSCE2 User Manual

Multi-Channel High Speed Counter

(Catalog Number 1746-HSCE2)

User Manual

Important User Information

Because of the variety of uses for the products described in this publication, those responsible for the application and use of these products must satisfy themselves that all necessary steps have been taken to assure that each application and use meets all performance and safety requirements, including any applicable laws, regulations, codes and standards. In no event will Rockwell Automation be responsible or liable for indirect or consequential damage resulting from the use or application of these products.

Any illustrations, charts, sample programs, and layout examples shown in this publication are intended solely for purposes of example. Since there are many variables and requirements associated with any particular installation, Rockwell Automation does not assume responsibility or liability (to include intellectual property liability) for actual use based upon the examples shown in this publication.

Allen-Bradley publication SGI-1.1, Safety Guidelines for the

Application, Installation and Maintenance of Solid-State Control

(available from your local Rockwell Automation office), describes some important differences between solid-state equipment and electromechanical devices that should be taken into consideration when applying products such as those described in this publication.

Reproduction of the contents of this copyrighted publication, in whole or part, without written permission of Rockwell Automation, is prohibited.

Throughout this publication, notes may be used to make you aware of safety considerations. The following annotations and their accompanying statements help you to identify a potential hazard, avoid a potential hazard, and recognize the consequences of a potential hazard:

WARNING

Identifies information about practices or circumstances that can cause an explosion in a hazardous environment, which may lead to personal injury or death, property damage, or economic loss.

ATTENTION

Identifies information about practices or circumstances that can lead to personal injury or death, property damage, or economic loss.

IMPORTANT

Identifies information that is critical for successful application and understanding of the product.

Allen-Bradley and SLC are trademarks of Rockwell Automation.

Module Overview

Preface

Who Should Use This Manual . . . . . . . . . . . . . . . . . . . . . . P-1

Purpose of This Manual. . . . . . . . . . . . . . . . . . . . . . . . . . . P-1

Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . P-2

Conventions Used In This Manual . . . . . . . . . . . . . . . . . . . P-3

Your Questions or Comments on the Manual . . . . . . . . . . . P-3

Chapter 1

Multi-Channel High-Speed Counter Module Overview . . . . 1-1

Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

Operating Class. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

Class 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

Class 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

Class 1 vs. Class 4 Comparison . . . . . . . . . . . . . . . . . . . 1-4

Hardware Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Jumpers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

Module Operation

Chapter 2

Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Input Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

Pulse/External Direction. . . . . . . . . . . . . . . . . . . . . . . . 2-2

Pulse/Internal Direction . . . . . . . . . . . . . . . . . . . . . . . . 2-3

Up and Down Pulses . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

X1 Quadrature Encoder . . . . . . . . . . . . . . . . . . . . . . . . 2-4

X2 Quadrature Encoder . . . . . . . . . . . . . . . . . . . . . . . . 2-4

X4 Quadrature Encoder . . . . . . . . . . . . . . . . . . . . . . . . 2-4

Input Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

Gate/Preset Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

No Preset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

Soft Preset Only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

Store/Continue. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

Store/Hold/Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

Store/Preset/Hold/Resume . . . . . . . . . . . . . . . . . . . . . . 2-7

Store/Preset/Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

Gate and Preset Limitations . . . . . . . . . . . . . . . . . . . . . 2-8

Gate and Preset Considerations . . . . . . . . . . . . . . . . . . 2-8

Summary of Available Counter Configurations . . . . . . . . . . 2-8

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Table of Contents ii

Installation and Wiring

Counter Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

Linear Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

Ring Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

Rate Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

Output Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

Range Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

Count Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

Rate Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

Counter Input Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

Class 1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

Class 4 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

Input Word Bit Values . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

Output State Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18

Counter Status Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18

Chapter 3

Compliance to European Union Directives . . . . . . . . . . . . . 3-1

EMC Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

Low Voltage Directive . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

Prevent Electrostatic Discharge . . . . . . . . . . . . . . . . . . . . . 3-2

Setting the Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

Installing the Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

Important Wiring Considerations . . . . . . . . . . . . . . . . . . . . 3-4

Considerations for Reducing Noise . . . . . . . . . . . . . . . . 3-5

Electronic Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

Auto Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

Input and Output Connections . . . . . . . . . . . . . . . . . . . . . 3-7

Removing the Terminal Block . . . . . . . . . . . . . . . . . . . 3-7

Encoder Wiring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

Differential Encoder Wiring . . . . . . . . . . . . . . . . . . . . . 3-8

Single-Ended Encoder Wiring (Open Collector). . . . . . . 3-9

Single-Ended Wiring (Discrete Devices) . . . . . . . . . . . . 3-10

Configuration and Programming

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Chapter 4

Selecting Operating Class . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

Power-up Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

Module Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

Programming Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

Table of Contents iii

Module Setup Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

Programming Block Identification Bit . . . . . . . . . . . . . . 4-6

TRMT: Transmit Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

DEBUG: Debug Mode Selection Bit . . . . . . . . . . . . . . . 4-6

INT: Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

RVF: Rate Value Format . . . . . . . . . . . . . . . . . . . . . . . . 4-7

PRA: Program Range Allocation . . . . . . . . . . . . . . . . . . 4-7

Op Mode: Operating Mode . . . . . . . . . . . . . . . . . . . . . 4-8

Range Allocation Values. . . . . . . . . . . . . . . . . . . . . . . . 4-8

Range Allocation Examples . . . . . . . . . . . . . . . . . . . . . 4-9

Counter Configuration Block . . . . . . . . . . . . . . . . . . . . . . . 4-10

Programming Block Identification Bit . . . . . . . . . . . . . . 4-11

TRMT: Transmit Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11

DEBUG: Debug Mode Selection Bit . . . . . . . . . . . . . . . 4-11

PGMn: Program Counter Number Bits . . . . . . . . . . . . . 4-12

CType: Counter Type Bit . . . . . . . . . . . . . . . . . . . . . . . 4-12

Input Config: Input Configuration Bits . . . . . . . . . . . . . 4-12

G/P Mode: Gate/Preset Mode Bits . . . . . . . . . . . . . . . . 4-13

Minimum/Maximum Count Value Block. . . . . . . . . . . . . . . 4-13

Programming Block Identification Bit . . . . . . . . . . . . . . 4-14

TRMT: Transmit Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14

DEBUG: Debug Mode Selection Bit . . . . . . . . . . . . . . . 4-14

AUTO PRESET: Automatic Preset Bit. . . . . . . . . . . . . . . 4-14

CNTR No.: Counter Number Bits . . . . . . . . . . . . . . . . . 4-15

Preset Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15

Minimum/Maximum Count Value Words . . . . . . . . . . . 4-15

Counter Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16

Minimum/Maximum Rate Value Block . . . . . . . . . . . . . . . . 4-16

Programming Block Identification Bit . . . . . . . . . . . . . . 4-17

TRMT: Transmit Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17

DEBUG: Debug Mode Selection Bit . . . . . . . . . . . . . . . 4-17

CNTR No.: Counter Number Bits . . . . . . . . . . . . . . . . . 4-18

Minimum/Maximum Rate Value Words . . . . . . . . . . . . . 4-18

Operating Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18

Program Ranges Block . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19

Programming Block Identification Bit . . . . . . . . . . . . . . 4-20

TRMT: Transmit Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20

DEBUG: Debug Mode Selection Bit . . . . . . . . . . . . . . . 4-20

CNTR No.: Counter Number Bits . . . . . . . . . . . . . . . . . 4-21

Rtype: Range Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21

Range No.: Range Number Bits. . . . . . . . . . . . . . . . . . . 4-21

Range Start Value, Range Stop Value . . . . . . . . . . . . . . 4-22

Output State: Output State Byte . . . . . . . . . . . . . . . . . . 4-22

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Table of Contents iv

Start Up, Operation, Troubleshooting, and Debug Mode

Counter Control Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23

Transmit Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24

Programming Block Identification Bit . . . . . . . . . . . . . . 4-24

Control Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24

ENn: Enable Counter (n) Bit. . . . . . . . . . . . . . . . . . . . . 4-24

SPn: Soft Preset Only (n) Bit . . . . . . . . . . . . . . . . . . . . 4-25

IDn: Internal Direction (n) Bit . . . . . . . . . . . . . . . . . . . 4-25

C/R(n): Count or Rate Value Bit . . . . . . . . . . . . . . . . . . 4-26

P(n): Program Counter (n) Bit . . . . . . . . . . . . . . . . . . . 4-26

Output ON (OR) Mask . . . . . . . . . . . . . . . . . . . . . . . . . 4-26

Output Enable Mask . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26

Enable Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27

Determining Actual Output State . . . . . . . . . . . . . . . . . 4-27

Programming Block Default Values . . . . . . . . . . . . . . . . . . 4-28

Class 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28

Class 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30

Chapter 5

Start Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

Module Diagnostic Errors . . . . . . . . . . . . . . . . . . . . . . . 5-2

Module Programming Errors. . . . . . . . . . . . . . . . . . . . . 5-3

Application Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

Debug Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

Activating Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . 5-7

Application Examples

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Chapter 6

Example 1 - Direct Addressing. . . . . . . . . . . . . . . . . . . . . . 6-2

Data Table for N10 File (hexidecimal). . . . . . . . . . . . . . 6-7

Data Table for N11 File (decimal). . . . . . . . . . . . . . . . . 6-7

Example 2 - Indirect Addressing . . . . . . . . . . . . . . . . . . . . 6-7

Data Table for N10 File (hexidecimal). . . . . . . . . . . . . . 6-10

Data Table for N11 File (decimal). . . . . . . . . . . . . . . . . 6-10

Example 3 - Block Transfers . . . . . . . . . . . . . . . . . . . . . . . 6-10

Data Table for N10 File (hexidecimal). . . . . . . . . . . . . . 6-14

Data Table for N11 File (decimal). . . . . . . . . . . . . . . . . 6-14

Example 4 - Using Soft Presets. . . . . . . . . . . . . . . . . . . . . . 6-14

Ladder File 9 - HSCE2 Initialization Routine . . . . . . . . . 6-17

Data Table for N10 File (hexidecimal). . . . . . . . . . . . . . 6-18

Data Table for N11 File (decimal). . . . . . . . . . . . . . . . . 6-18

Example 5 - Change Presets Dynamically . . . . . . . . . . . . . . 6-18

Data Table for N10 File (hexidecimal). . . . . . . . . . . . . . 6-22

Data Table for N11 File (decimal). . . . . . . . . . . . . . . . . 6-22

Specifications

Connecting a Differential Encoder

Module Programming Quick Reference

Table of Contents v

Example 6 - Retentive Counters . . . . . . . . . . . . . . . . . . . . . 6-23

Data Table for N10 File (hexidecimal). . . . . . . . . . . . . . 6-25

Data Table for N11 File (decimal). . . . . . . . . . . . . . . . . 6-25

Appendix A

General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1

Inputs A, B, and Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2

Outputs (sourcing) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2

On-State Current Derating . . . . . . . . . . . . . . . . . . . . . . A-3

Throughput and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . A-3

Appendix B

Appendix C

Frequently Asked Questions

Comparing 1746-HSCE2 to 1746-HSCE

Appendix D

Appendix E

Glossary

Index

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Table of Contents vi

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Summary of Changes

The information below summarizes the changes to this manual since the last printing.

To help you find new information and updated information in this release of the manual, we have included change bars as shown to the right of this paragraph.

New Information

The table below lists sections that include new information.

For this new information See page(s)

Note on limitations of rate value calculation at input frequencies below 60 Hz.

Clarified operation of Module Fault (MFLT) bit 2-17

Updated resistor information in single-ended wiring diagrams 3-9 and 3-10

Clarified programming cycle 4-2

Modifications to the COP instruction example for reading and writing floating point data

Corrected bit identification in Output State Byte 4-22

Example showing how to activate debug mode 5-10

Corrected bit identification table for Program Ranges Block C-2

2-11

4-4

1 Publication 1746-UM002B-EN-P - August 2004

2 Summary of Changes

Publication 1746-UM002B-EN-P - August 2004

Preface

Read this preface to familiarize yourself with the rest of the manual. This preface covers the following topics:

• who should use this manual

• how to use this manual

• related publications

• conventions used in this manual

• Rockwell Automation support

Who Should Use This Manual

Purpose of This Manual

Use this manual if you are responsible for designing, installing, programming, or troubleshooting control systems that use Allen-Bradley small logic controllers.

You should have a basic understanding of SLC 500™ products. You should understand programmable controllers and be able to interpret the ladder logic instructions required to control your application. If you do not, contact your local Rockwell Automation representative for information on available training courses before using this product.

As much as possible, we organized this manual to explain, in a task-by-task manner, how to install, configure, program, operate and troubleshoot an SLC 500-based system using the 1746-HSCE2 module.

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2 Preface

Conventions Used In This Manual

Your Questions or Comments on the Manual

The following conventions are used throughout this manual:

• Bulleted lists (like this one) provide information, not procedural

steps.

• Numbered lists provide sequential steps or hierarchical

information.

• Italic type is used for emphasis.

• Text in this font indicates words or phrases you should type.

If you find a problem with this manual, please notify us. If you have any suggestions for how this manual could be made more useful to you, please contact us at the address below:

Rockwell Automation Automation Control and Information Group Technical Communication, Dept. A602V P.O. Box 2086 Milwaukee, WI 53201-2086

Publication 1746-UM002B-EN-P - August 2004

4 Preface

Publication 1746-UM002B-EN-P - August 2004

Module Overview

This chapter contains the following:

• multi-channel high-speed counter module overview

• operating class

• hardware features

Chapter

Multi-Channel High-Speed Counter Module Overview

The 1746-HSCE2 is an intelligent counter module with its own microprocessor and I/O that is capable of reacting to high-speed input signals without the intervention of the SLC processor. The module is compatible with the SLC 500 family and can be used in a remote chassis with the SLC Remote I/O Adapter Module (1747-ASB).

Counters

The module is able to count in either direction. A maximum of four pulse counters are available (or 2 quadrature counters). Each counter can count to +/- 8,388,607 as a ring or linear counter. In addition to providing a count value, the module provides a rate value up to +/-1 MHz, dependent on the type of input. The rate value is the input frequency (in Hertz) to the counter. When the count value is increasing, the rate value is positive. When the count value is decreasing, the rate value is negative.

Counters can also be preset to any value between the minimum and maximum values. The conditions that preset the count value and generate capture values are configured by the gate/preset modes. The four counters can have different gate/preset modes.

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1-2 Module Overview

Inputs

The module features six high-speed differential inputs labeled ±A1, ±B1, ±Z1, ±A2, ±B2, and ±Z2. It supports quadrature encoders with ABZ inputs and/or up to six discrete switches. In addition, x1, x2, and x4 counting configurations are provided to fully use the capabilities of high resolution quadrature encoders. The inputs can be wired for single-ended or differential use. Inputs are opto-isolated from the backplane.

Outputs

Eight outputs are available, four real (dc sourcing) and four virtual bits. The virtual outputs are available to the processor only. The real outputs are protected from overloads by a self-resetting fuse. The outputs can be controlled by any or all of the counters and/or directly controlled by the user’s program.

Up to 16 dynamically configurable ranges are available, using rates or counts to control outputs. The ranges, programmed with range start and range stop values, can overlap. If the count or rate is within more than one range, the output patterns of those ranges are combined (logically ORed) to determine the actual status of the output. When an output is enabled by more than one counter and/or with the user program, its output state is determined by logically ORing the programmed setpoints of all those counters and the user program.

Operation

Module operation is controlled by user-programmed settings in the following six module programming blocks.

• Module Setup Block

• Counter Configuration Block

• Minimum/Maximum Count Value Block

• Minimum/Maximum Rate Value Block

• Program Ranges Block

• Counter Control Block

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Module Overview 1-3

Most programming parameters, except those in the Module Setup and Counter Configuration blocks, are dynamic and can be changed without halting counter operation. The table below lists the static and dynamic parameters by programming block.

Programming Block Parameter

Ty pe

(1)

Operating Mode

Module Setup

Range Allocation

Interrupt Enable

Static

Rate Value Format

Counter Type

Counter Configuration

Input Configuration

Static

(2)

Gate/Preset Mode

Minimum Count

Min./Max. Count Value

Maximum Count

Preset Value

Min./Max. Rate Value Minimum Rate

Maximum Rate

(2)

Static

(2)

Static

Dynamic

Counter Number

Range Type

Program Range

Range Number

Start Value

Dynamic

Stop Value

Output Image

Enabled

Soft Preset Only

Internal Direction

Counter Control

Output ON Mask

Dynamic

Output OFF Mask

Count or Rate Value

Range Enable Mask

(1) STATIC = the associated counter must be disabled to set this parameter.

DYNAMIC = this parameter may be changed while the associated counter is running.

(2) Only the selected counter must be disabled.

(3) Under specific conditions, this parameter is dynamic. See page 4-15 for more information.

(3)

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1-4 Module Overview

Operating Class

Module operation differs slightly based on the operating class. The operating class is selected via the module ID code.

Class 1

Class 1 operation is compatible with all SLC 500 processors. In Class 1 operation, the module uses 8 input and 8 output words and has an associated ID code of 3511. A maximum of four 16-bit counters are available in this operating class.

Class 4

Class 4 operation is compatible with SLC 5/03 and above systems. In Class 4 operation, the module uses 23 input and 8 output words and has an associated ID code of 15912. A maximum of four 24-bit counters are available in this class.

Class 1 vs. Class 4 Comparison

Class Class 1 Class 4

Counters 16-bit (±32,767) 24-bit (±8,388,607)

Input Words 8 with limited information. 23 with all information.

Backplane Interrupts Not permitted. Permitted.

Use in RIO Chassis Permitted. Not permitted.

Use in ControlNet Chassis Not permitted. Permitted.

Module ID Code 3511 15912

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Module Overview 1-5

Hardware Features

The module’s hardware features are illustrated below. Refer to Chapter 3 for detailed information on installation and wiring.

Figure 1.1 Hardware Features

Input Status LEDs

Input and Output Te rm in al s

COUNTER

OUTPUT STATUS

1023

A1 B1 Z1

A2 B2 Z2

INPUT STATUS

HSCE2

Output Status LEDs

RUN

Running Status LED

FLT

Fault Status LED

LEDs

The front panel has a total of twelve indicator LEDs, as shown in Figure 1.1 on page 1-5.

LED Color Indicates

0 OUT Green ON/OFF status of real output

1 OUT Green ON/OFF status of real output

2 OUT Green ON/OFF status of real output

3 OUT Green ON/OFF status of real output

RUN Green Running status of the module

FLT Red Steady on: Module fault

Flashing: Output overcurrent

A1 Yellow ON/OFF status of input A1

A2 Yellow ON/OFF status of input A2

B1 Yellow ON/OFF status of input B1

B2 Yellow ON/OFF status of input B2

Z1 Yellow ON/OFF status of input Z1

Z2 Yellow ON/OFF status of input Z2

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1-6 Module Overview

Jumpers

Six jumpers select the input voltages for the six inputs A1, B1, Z1, A2, B2, and Z2. The module accepts input voltages of 5V dc, 12V dc, or 24V dc. See Chapter 3 for jumper locations and settings.

Publication 1746-UM002B-EN-P - August 2004

Module Operation

The chapter contains information about:

• operating modes

• input configurations

• gate/preset modes

• counter types

• rate value

• outputs

• range types

Chapter

Operating Modes

The module’s operating mode determines the number of available counters and which inputs are attached to them. The three operating modes and their input assignments are summarized in Figure 2.1.

Figure 2.1 Operating Mode Input Assignments

Counter 1

Counter 2

Operating Mode 1

Counter 3

Counter 4

Counter 1

Counter 2

Operating Mode 3

Counter 3

Counter 4

Counter 1

Counter 2

Operating Mode 2

Counter 3

Counter 4

1 Publication 1746-UM002B-EN-P - August 2004

2-2 Module Operation

Input Configurations

Input configurations determine how the A and B inputs cause the counter to increment or decrement. The six available configurations are:

• Pulse/External Direction

• Pulse/Internal Direction

• Up and Down Pulses

• X1 Quadrature Encoder

• X2 Quadrature Encoder

• X4 Quadrature Encoder

See the Summary of Available Counter Configurations on page 2-8 for the input configurations available for the counters, based on operating mode.

Pulse/External Direction

With this configuration, the B input controls the direction of the counter, as shown below. If the B input is low (0), the counter increments on the rising edges of input A. If the input B is high (1), the counter decrements on the rising edges of input A.

Figure 2.2 Pulse/External Direction Configuration

Count Pulse

Encoder or Sensor

Sensor or Switch

Count Pulse

Direction Control High = Decrement Low = Increment

Count

12321012

Direction Control

Input A

Input B

Input Z

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Module Operation 2-3

Pulse/Internal Direction

When the Pulse/Internal Direction configuration is selected, a bit written from the backplane determines the direction of the counter. The counter increments on the rising edge of the input if the bit is low (0) and decrements on the rising edge of the input if the bit is high (1).

Up and Down Pulses

In this configuration, the counter increments on the rising edge of pulses applied to input A and decrements on the rising edge of pulses applied to input B.

TIP

When both inputs transition simultaneously or near simultaneously, the net result is no change to the count value. Therefore, simultaneous (or near simultaneous) pulses are ignored and no change in the count value is reported.

Figure 2.3 Up and Down Pulse Configuration

Increment Pulse

Incrementing Encoder

or Sensor

Decrement Pulse

Decrementing Encoder or

Sensor

Increment Pulse

(Input A)

(count down)

(count up)

Input A

Input B

Input Z

Module

Decrement Pulse

(Input B)

Count

12321012

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2-4 Module Operation

X1 Quadrature Encoder

When a quadrature encoder is attached to inputs A and B, the count direction is determined by the phase angle between inputs A and B. If A leads B, the counter increments. If B leads A, the counter decrements. The counter changes value only on one edge of input A as shown in Figure 2.4 on page 2-5.

TIP

If B is low, the count increments on the rising edge of input A and decrements on the falling edge of input A. If B is high, all transitions on input A are ignored.

X2 Quadrature Encoder

Like the X1 Quadrature Encoder, the count direction is determined by the phase angle between inputs A and B. If A leads B, the counter increments. If B leads A, the counter decrements. However, the counter changes value on the rising and falling edges of input A, as shown in Figure 2.4 on page 2-5.

X4 Quadrature Encoder

Operation is similar to the X2 Quadrature Encoder configuration, except the counter changes value on the rising and falling edges of inputs A and B as shown in Figure 2.4.

Publication 1746-UM002B-EN-P - August 2004

Figure 2.4 Quadrature Encoder Configurations

Quadrature

Encoder

Module Operation 2-5

Input A

Input B

Input Z

1 2 3 102

X1 Count

X2 Count

X4 Count

IMPORTANT

Forward Rotation

654321 102345

121110987654321 2345678910 1 0

Reverse Rotation

The input configuration is limited by the operating mode. In mode 1, Counters 1 and 2 can be assigned any input configuration. In mode 2, Counter 1 can be assigned any configuration, but Counters 2 and 3 are configured as pulse/internal direction. In mode 3, all counters have the pulse/internal direction configuration. See the Summary of Available Counter Configurations on page 2-8.

Input Frequency

Input frequency is determined by the input configuration as shown in the table below.

Input Configuration Input Frequency

X4 Quadrature Encoder 250 kHz

X2 Quadrature Encoder 500 kHz

All Other Configurations 1 MHz

IMPORTANT

The minimum high and low times for the pulse train are 475 ns. Therefore, the input pulse train must fall between a 47.5 to 52.5 percent duty cycle at 1 MHz.

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2-6 Module Operation

Gate/Preset Modes

A counter’s gate/preset mode determines what, if any, gating is applied to the counter and what, if any, conditions will preset the counter to the preset value. The Z inputs are the only inputs used for gating or presetting. The six gate/preset modes are described below.

No Preset

The counter is not preset under any conditions. The Z inputs are not used.

Soft Preset Only

The counter is preset when the matching preset bit in the SLC 500 output image table experiences a positive transition, but not in response to the Z input.

TIP

The soft preset bit operates in all the gate/preset modes except No Preset.

store, continue counting

Store/Continue

The count value is captured when the module detects an inactive-to-active transition on the Z input of the counter. This stored value is made available to the backplane. A stored status bit in the input image table is set to signal the processor that a new value is available. This bit is active until the capture value is read by the processor. Therefore, it is on for a maximum of 10 ms in Class 1, and a maximum of one scan or 10 ms, whichever is shorter, in Class 4. If a second capture event occurs before the first is read, the first value is lost. The count and rate values are not affected by a store event.

Publication 1746-UM002B-EN-P - August 2004

counter has stopped counting

stop count store count

resume counting

Module Operation 2-7

Store/Hold/Resume

The count value, captured when the module detects a positive transition on the Z input, is made available to the backplane. A stored status bit is set in the input image table to signal the processor that a new value is available. This bit is active until the capture value is read by the processor. Therefore, it is on for a maximum of 10 ms in Class 1, and a maximum of one scan or 10 ms, whichever is shorter, in Class

4. The count value is held as long as the Z input is active. Because the count value is not changing, the rate value is equal to zero while the counter is held.

Store/Preset/Hold/Resume

stop count,

store count,

store count, preset, start counting

counter has stopped counting

start counting from preset

The counter is set to its programmed preset value when the module detects a positive transition on the Z input of the counter. The capture value is made available to the backplane. A stored status bit is set in the input image table to signal the processor that a new value is available. This bit is active until the capture value is read by the processor. Therefore, it is on for a maximum of 10 ms in Class 1, and a maximum of one scan or 10 ms, whichever is shorter, in Class 4. The preset counter value is held as long as the Z input remains active. Because the count value is not changing, the rate value equals zero while the preset value is held.

Store/Preset/Start

The counter is set to its programmed preset value when the module detects a positive transition on the Z input of the counter. The capture value is made available to the backplane. A stored status bit is set in the input image table to signal the processor that a new value is available.This bit is active until the capture value is read by the processor. Therefore, it is on for a maximum of 10 ms in Class 1, and a maximum of one scan or 10 ms, whichever is shorter, in Class 4.

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2-8 Module Operation

Gate and Preset Limitations

Because only the Z inputs are used for external gating and presetting, the only gate/preset modes available for Counters 3 and 4 are No Preset and Soft Preset Only. All six modes are always available for Counters 1 and 2.

IMPORTANT

In Class 1, Operating Mode 2, Counter 2 does not have a capture value available. In Class 1, Operating Mode 3, no capture values are available.

Gate and Preset Considerations

Z-pulse Preset Operation

In applications where the Z pulse of the encoder is being used to preset the position, and where the Z pulse of the encoder is aligned with either the A or B pulses, the capture or count value may be affected by ± 1 count. If the Z pulse is edge aligned with the A pulse, preset operations may not be performed accurately in any of the quadrature modes. If the Z pulse is edge aligned with the B pulse, preset operation may not be performed accurately in the X4 quadrature mode only. A small capacitor (for example, 0.01 µF) across the Z inputs will dis-align these inputs and should correct this condition.

Summary of Available Counter Configurations

Publication 1746-UM002B-EN-P - August 2004

The table below summarizes the input configurations and gate/preset modes available for all counters, based on operating mode.

Operating Mode

11All All

21All All

3 1 Pulse/Internal Direction All

Counter Input Configuration Gate/Preset Mode

2All All

2 Pulse/Internal Direction All

3 Pulse/Internal Direction No Preset or Soft Preset Only

2 Pulse/Internal Direction All

3 Pulse/Internal Direction No Preset or Soft Preset Only

4 Pulse/Internal Direction No Preset or Soft Preset Only

Module Operation 2-9

Counter Types

Each counter can be programmed to operate as a linear or ring counter. Both types are described below.

Linear Counter

The figure below demonstrates linear counter operation. In linear operation, the count value must remain within the programmed minimum/maximum values. If the count value goes above or below these values, the counter stops counting, and an overflow/underflow bit is set. In the overflow or underflow condition, the rate value continues to be updated and valid.

The number of pulses accumulated in an overflow/underflow state are ignored. The counter begins counting again when pulses are applied in the proper direction. For example, if you exceed the maximum by 1,000 counts, you do not need to apply 1,000 counts in the opposite direction before the counter begins counting down. The first pulse in the opposite direction decrements the counter.

Figure 2.5 Linear Counter Diagram

Minimum Value

Underflow

Count Up

Counter Value

Maximum Value

Count Down

Overflow

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2-10 Module Operation

Ring Counter

Figure 2.6 demonstrates ring counter operation. In ring counter operation, the count value changes between programmable minimum and maximum values. If, when counting up, the counter reaches the maximum value, it rolls over to the minimum value. If, when counting down, the counter reaches the minimum value, it rolls over to the maximum value.

Figure 2.6 Ring Counter Diagram

Rate Value

Maximum Value

Rollover

Count Down

Minimum Value

Count Up

The rate value reported to the processor is calculated in counts per second (Hz), and is available with all input configurations. The input configuration determines how the rate value is calculated. When the count value is increasing, the rate value is positive. When the count value is decreasing, the rate value is negative.

The rate value is generally calculated as follows:

When the first input pulse is received, the value of an independent, free-running timer (Ta) is recorded. The module waits approximately 16 ms, while counting more input pulses. After 16 ms, the module waits for the next input pulse, and the value of the independent timer (Tb) is again recorded. The module then calculates the rate value using the formula:

number of counts



rate value

------------------------------------------



Tb Ta–

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Module Operation 2-11

Additional checks ensure that rates below 1 Hz, which are not supported by the module, and frequencies due to motor vibration, are not counted in the rate value calculation.

Table 2.1 Typical Rate Update Times

Rates (Hz) Time Between Pulses (ms) Time Between Updates (ms)

1 to 59 17 to 1000 17 to 1000

60 to 1000 0 to 16 0 to 33

Above 1000 0 to 1 16

IMPORTANT

Because of the way the 1746-HSCE2 performs rate value calculations, invalid rate measurements may occur if the input frequency is below 60 Hz. Therefore, we recommend that the 1746-HSCE2 module not be used for rate monitoring or rate range control for frequencies below 60 Hz.

The invalid measurements apply only to rate values and do not affect the count value reported to the controller, which are always correct.

Accuracy

The accuracy of the rate value can be ±0.005% (typical). For this resolution, the rate measurement value must be transferred in single-precision floating-point format. This format is only available when the module operates as Class 4. Fractional rates, those between 1 and 0 or -1 and 0, are not reported.

The rate measurement value can also be transferred as an integer value. The integer format is available in both Class 1 and Class 4.

Output Control

All eight outputs can be controlled by any or all of the counters, or they can be controlled by the user program. When controlled by a counter, an output can be programmed to turn on or off based on the count value and/or rate value of the counter.

The eight outputs are divided into four real outputs and four virtual outputs. The outputs can be activated from the user program or from the module in response to specified input events. The status of the real outputs is available to the user program. The virtual outputs are available only to the user program. They have no real output associated with them. The real outputs are protected from overloads by a self-resetting fuse.

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2-12 Module Operation

Range Control

-32,767 +32,767

The module can be programmed to use either counter or rate ranges to determine whether an output is active. Up to 16 dynamically configurable ranges are available. The ranges, programmed using range start and range stop values, can overlap. When the count is within more than one range, the output patterns of those ranges are combined (logically ORed) to determine the actual status of the output. A mixture of count ranges and rate ranges may be used.

Count Range

In a count range, the outputs are active if the count value is within the user-defined range. The valid count range is dependent upon the operating class. In Class 1, the valid range is -32,767 to +32,767. In Class 4, the valid range is -8,388,607 to +8,388,607. The examples in Figure 2.7 and Figure 2.8 use Class 1 operation.

Figure 2.7 Count Range with Linear Counter

Range 4 Stop

off

Value

Output 0

Output 1

Output 2

Output 3

Range 1

Range 3

Range Start

Value

1 -7000 -5000 0 0 0 0 0 0 0 1 0

2 -1000 +4500 0 0 0 0 0 0 1 0 1

3 -4000 +3000 0 0 0 0 0 1 0 0 2

4 +9000 -9000 0 0 0 0 1 0 0 1 0 and 3

(1) Bits 0 through 3 are real outputs. Bits 4 through 7 are virtual outputs.

Range 2

Stop

Value

Outputs

76543210

(1)

Range 4 Start

Value

Outputs

Affected

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Figure 2.8 Count Range with Ring Counter

Range 3

32,000

32,767

Module Operation 2-13

200

500

Range 2

Range

23,000

Range 4

Start

Value

20,000

Stop

Value

10,000

Outputs

Range 1

(1)

12,500

76543210

8,000

1 10,000 12,500 0 0 0 0 0 0 0 1 0

2 200 8,000 00000010 1

3 32,000 500 0 0 0 0 0 1 0 0 2

4 20,000 23,000 0 0 0 0 1 0 0 1 0 and 3

(1) Bits 0 through 3 are real outputs. Bits 4 through 7 are virtual outputs.

Outputs

Affected

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2-14 Module Operation

-32,767 0 +32,767

(min. rate value)

Rate Range

In a rate range, the outputs are active if the rate measurement is within the user-defined range. The valid input rate is dependent upon the operating class. In Class 1, the input rate can be up to 32,767 Hz in either direction. In Class 4, the input rate can be up to 1 MHz in either direction. The linear counter example in Figure 2.9 uses Class 1 operation.

Figure 2.9 Rate Range

(max. rate value)

Rate Value

off

Range 4

Output 0

Output 1

Output 2

Output 3

Range 1

Range 3

Range

1 -7000 -5000 00000001 0

2 -1000 +4500 00000010 1

3 -4000 +3000 00000100 2

4 +20000 -20000 00001001 0 and 3

(1) Bits 0 through 3 are real outputs. Bits 4 through 7 are virtual outputs.

Start

Value

Range 2

Stop

Value

Range 4

Outputs

76543210

(1)

Outputs

Affected

Counter Input Data

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The format of the counter input data table depends on the module’s mode and class of operation. The status data formats for Class 1 and Class 4 are shown below, followed by explanations of the programming bits and status bytes. Mode 1 is the default for both Class 1 and Class 4 operation.

Module Operation 2-15

Class 1 Operation

In this operating class, the input data consists of eight words. The counters are sixteen bits. The data stored in an input word change based on the module’s operating mode.

Figure 2.10 Mode 1 Input Data Format

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Word 0

0OP

MODE

ACK

MFLT

PERR

DEBUG

FB1

Word 1 Counter 2 Status Counter 1 Status Word 2 Counter 1: Count Value Word 3 Counter 1: Rate Value Word 4

Counter 1: Capture Value

Word 5 Counter 2: Count Value Word 6 Counter 2: Rate Value Word 7

(1) See page 2-6 for a description of capture values.

Counter 2: Capture Value

Output State

Virtual Real

(1)

Figure 2.11 Mode 2 Input Data Format

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Word 0

ACK

MFLT

PERR

DEBUG

0OP

FB1

MODE

Output State

Virtual Real

Word 1 Counter 2: Status Counter 1: Status Word 2 Counter 1: Count Value Word 3 Counter 1: Rate Value Word 4

Counter 1: Capture Value

(1)

Word 5 Counter 2: Count or Rate Value Word 6

0 0 0 0 0 0 0 0 Counter 3: Status

Word 7 Counter 3: Count or Rate Value

(1) See page 2-6 for a description of capture values.

Figure 2.12 Mode 3 Input Data Format

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Word 0

ACK

MFLT

PERR

DEBUG

0OP

FB1

MODE

Output State

Virtual Real

Word 1 Counter 2 Status Counter 1 Status Word 2 Counter 1: Count or Rate Value Word 3 Counter 2: Count or Rate Value Word 4 Counter 4: Status Counter 3: Status Word 5 Counter 3: Count or Rate Value Word 6 Counter 4: Count or Rate Value Word 7

Not Used. Set equal to 0000H

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2-16 Module Operation

Class 4 Operation

In Class 4 operation, the counter data consist of a maximum of 23 words.

Figure 2.13 Class 4 Data Format

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Word 0

ACK

MFLT

PERR

DEBUG

FB1

Word 1 Counter 2 Status Counter 1 Status Word 2 Upper 4 digits: Counter 1 Count Value Word 3 Lower 3 digits: Counter 1 Count Value Word 4 Word 5 Word 6 Upper 4 digits: Counter 1 Capture Value Word 7 Lower 3 digits: Counter 1 Capture Value Word 8 Upper 4 digits: Counter 2 Count Value Word 9 Lower 3 digits: Counter 2 Count Value Word 10 Word 11 Word 12 Upper 4 digits: Counter 2 Capture Value Word 13 Lower 3 digits: Counter 2 Capture Value Word 14 Counter 4 Status Counter 3 Status Word 15 Upper 4 digits: Counter 3 Count Value Word 16 Lower 3 digits: Counter 3 Count Value Word 17 Word 18

MODE

Virtual Real

Counter 1 Rate Value

Counter 2 Rate Value

Counter 3 Rate Value

Output State

(1)

(2)

Transferred in all Modes

(2)

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Transferred in Modes 2 and 3

Word 19 Upper 4 digits: Counter 4 Count Value

(2)

Word 20 Lower 3 digits: Counter 4 Count Value Word 21

Counter 4 Rate Value

(1)

Word 22

Transferred in Mode 3

(1) The format of the Rate Values is programmed with the Rate Value Format bit in the Module Setup programming

block. This bit specifies the rate value to be in integer or floating-point format. The default is integer format. Count values are always transferred in integer format. See Data Format on page 4-3.

(2) Data values transferred. Regardless of operating mode, the module will transfer up to 23 words. Words that do

not contain relevant data are set to 0000H.

Module Operation 2-17

Input Word Bit Values

ACK: Acknowledge Bit

This bit makes a 0 to 1 transition to signal the receipt of programming data.

MFLT: Module Fault Bit

This bit is set only if the module does not power up correctly. After a proper power up, the MFLT bit remains reset.

PERR: Programming Error Bit

The state of this bit is valid only when the acknowledge bit is set. This bit is reset when the last programming block is accepted without error. It is set when any one of the reserved bits are set or another programming error has occurred. For a list of other programming error conditions, see Module Programming Errors on page 5-3.

DEBUG: Debug Mode Bit

This bit is set when the debug mode is active.

IMPORTANT

For details, see Debug Mode Operation on page 5-7.

When the debug mode is active, the input data file shows the programming setup, not rate and count values.

FB1: Fuse Status Bit

The FB1 fuse status bit is set (1) when the fuse is open. In addition, the module fault LED blinks to indicate an open fuse.

When FB1 is set (1), the real outputs do not function. Virtual outputs are not affected. The input word reflects this condition.

The module tries resetting the outputs at intervals of 500 ms. During each retry, the fuse status bit is reset (0). After the overload condition is corrected, the fuse bit resets (0) automatically.

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2-18 Module Operation

OP MODE: Operating Mode Bits

The module uses these two bits to tell the processor what mode it is in. In class 1, the data value that an input word contains changes based on the operating mode.

Table 2.2 Mode Bit Settings

Bit 09 Bit 08 Mode

00Reserved

0 1 Mode 1

1 0 Mode 2

1 1 Mode 3

Output State Byte

These bits correspond to the real or virtual state of the outputs. Bits 00 through 03 represent real outputs. Bits 04 through 07 represent virtual outputs.

Counter Status Bytes

Each counter has an associated status byte. The format of the byte depends on the module’s class of operation as shown below.

Figure 2.14 Class 1 Counter Status Byte Format

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

C/R

Figure 2.15 Class 4 Counter Status Byte Format

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

0 0 ROvFRUdFCOvFCUdF CState

0 ROvF RUdF COvF CUdF CState

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Module Operation 2-19

C/R: Count/Rate Bit

The count/rate bit is used only in Class 1 operating mode. Because only one data word is available for Counters 2 and 3 in operating mode 2, and one data word for each of the four counters in operating mode 3, the module transfers either the counter’s count or rate value.

When this bit is reset (0), the data in the corresponding word is the count value. When this bit is set (1), the data in the corresponding word is the rate value.

ROvF: Rate Overflow Bit

This bit is set when the rate is greater than the maximum rate value.

RUdF: Rate Underflow Bit

This bit is set when the rate is less than the minimum rate value.

COvF: Counter Overflow Bit

When the counter is configured as a linear counter, this bit is set when the count would become one over the maximum count value.

TIP

Counter overflow or underflow bits are reset when a pulse in the opposite direction is received.

CUdF: Counter Underflow Bit

When the counter is configured as a linear counter, this bit is set when the count would become one under the minimum count value.

CState: Counter State Bits

These two bits show the operational state of the counter.

Table 2.3 Counter State Bit Settings

Bits 09 or 01 Bits 08 or 00 Operating State

0 0 Stopped

0 1 Running

10Hold

11Reserved

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2-20 Module Operation

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Installation and Wiring

This chapter provides the following information:

• compliance to European Union Directives

• module installation

• wiring considerations

• input/output connections

• encoder wiring

• switch wiring

Chapter

Compliance to European Union Directives

If this product has the CE mark, it is approved for installation within the European Union and EEA regions. It has been designed and tested to meet the following directives.

EMC Directive

This product is tested to meet Council Directive 89/336/EED Electromagnetic Compatibility (EMC) and the following standards, in whole or in part, documented in a technical construction file:

EN50081-2 EMC — Generic Emission Standard, Part 2 – Industrial Environment

EN50082-2 EMC — Generic Emission Standard, Part 2 – Industrial Environment

This product is intended for use in an industrial environment.

Low Voltage Directive

This product is tested to meet Council Directive 73/23/EEC Low Voltage, by applying the safety requirements of EN 61131-2 Programmable Controllers, Part 2 – Equipment Requirements and Tests.

1 Publication 1746-UM002B-EN-P - August 2004

3-2 Installation and Wiring

Prevent Electrostatic Discharge

For specific information required by EN61131-2, see the appropriate sections in this publication, as well as the following Allen-Bradley publications:

• Industrial Automation, Wiring and Grounding Guidelines for

Noise Immunity, publication 1770-4.1

• Automation Systems Catalog, publication B111

ATTENTION

Static discharges may cause permanent damage to the module. Follow these guidelines when you handle the module:

Setting the Jumpers

Six jumpers are located in a column on the side of the module. Use the jumpers to select the input voltage for each of the inputs A1, B1, Z1, A2, B2, and Z2. The settings are shown in the figure on the following page.

• Touch a grounded object to discharge static

potential.

• Wear an approved wrist-strap grounding device.

• Handle module by plastic case only. Avoid

contact between module circuits and any surface which can hold an electrostatic charge.

• If available, use a static-safe work station.

Publication 1746-UM002B-EN-P - August 2004

Figure 3.1 Jumper Settings

Installation and Wiring 3-3

JP1 (A1 )

JP2 (B1)

JP3 (Z1)

JP4 (A2)

JP5 (B2)

JP6 (Z2)

Jumper Settings

24V dc

10-30V dc

(default)

IMPORTANT

ATTENTION

5V dc

4.2-12V dc

For a 12V dc encoder signal, use the 24V dc jumper setting.

If jumpers are not set to match the encoder type, the module may be damaged.

The 5V dc settings respond to inputs with an active voltage between

4.2 and 12 volts. The 24V dc settings respond to inputs with active or high settings between 10 and 30 volts.

Installing the Module

ATTENTION

Disconnect power before attempting to install, remove, or wire the module.

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3-4 Installation and Wiring

1. Make sure your SLC power supply has adequate reserve current

capacity. The module requires 250 mA at +5V dc.

2. Align the full-sized circuit board with the chassis card guide as

shown in Figure 3.2. The first slot of the first chassis is reserved for the processor.

3. Slide the module into the chassis until the top and bottom

latches catch. To remove the module, press the release clips at the top and bottom of the module and slide it out.

4. Cover all unused card slots with the Card Slot Filler, catalog

number 1746-N2.

Figure 3.2 Installing the Module

Important Wiring Considerations

Publication 1746-UM002B-EN-P - August 2004

Use the following guidelines when planning the system wiring for the module:

• Install the SLC500 system in a NEMA-rated enclosure.

• Disconnect power to the SLC processor and the module before

wiring.

• Make sure the system is properly grounded.

• Group this module and low voltage DC modules away from AC

I/O or high voltage DC modules.

• Shielded cable is required for high-speed input signals A, B, and

Z. Use individually shielded, twisted-pair cable lengths up to 300 m (1000 ft.).

Installation and Wiring 3-5

• Shields should be grounded only at one end. Ground the shield

wire outside the module at the chassis mounting screw. Connect the shield at the encoder end only if the housing is electronically isolated from the motor and ground

Figure 3.3 Grounding the Shield Wire at the Chassis Mounting Screw

Spade Connector

Mounting Screw

Star Washer

Chassis Mounting Tab

• If you have a junction in the cable, treat the shields as

conductors at all junctions. Do not ground them to the junction box.

• If your application requires only low frequency inputs, you can

use a filter to minimize high frequency noise.

• If the Z pulse is edge aligned with A or B pulses, capture/preset

operation may be affected by ± 1 count. A small capacitor (0.01µF) across the Z inputs will dis-align these inputs and should correct this condition. See Z-pulse Preset Operation on page 2-8.

Considerations for Reducing Noise

In high noise environments, the 1746-HSCE2 inputs may accept “false” pulses, particularly when using low frequency input signals with slowly sloping pulse edges. To minimize the effects of high frequency noise on low frequency signals, the user can do the following:

• Identify and remove noise sources.

• Route 1746-HSCE2 input cabling away from noise sources.

• Install low pass filters on input signals. Filter values are

dependent on the application and can be determined empirically.

• Use devices which output differential signals, like differential

encoders, to minimize the possibility that a noise source will cause a false input.

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3-6 Installation and Wiring

Electronic Protection

The electronic protection of the 1746-HSCE2 has been designed to provide protection for the module from overload current conditions. The protection is based on a thermal cut-out principle. In the event of a short circuit or overload current condition on an output channel, all channels will turn off within milliseconds after the thermal cut-out temperature has been reached.

IMPORTANT

The module does not provide protection against reverse polarity wiring or wiring to AC power sources. Electronic protection is not intended to replace fuses, circuit breakers, or other code-required wiring protection devices.

Auto Reset Operation

IMPORTANT

1746-HSCE2 outputs perform auto-reset under overload conditions. When an output channel overload occurs as described above, all channels turn off within milliseconds after the thermal cut-out temperature has been reached. While the overcurrent condition is present, the module tries resetting the outputs at intervals of 500 ms. If the fuse cools below the thermal cut-out temperature, all outputs auto-reset and resume control of their external loads as directed by the module until the thermal cut-out temperature is again reached.

Publication 1746-UM002B-EN-P - August 2004

Removing power from an overloaded output channel would also allow the fuse to cool below the thermal cut-out temperature, allowing auto-reset to occur when power is restored. The output channels then operate as directed by the module until the thermal cut-out temperature is again reached.

To avoid auto-reset of output channels under overload conditions, monitor the fuse blown status bit (FB1) in the module’s status file and latch the outputs off when an overcurrent condition occurs. An external mechanical fuse can also be used to open output circuits when they are overloaded.

Installation and Wiring 3-7

Input and Output Connections

Input and output wiring terminals are shown in the figure below. Each terminal accepts #14 AWG wire. Tighten screws only tight enough to immobilize the wire. The torque applied to the screw should not exceed 0.9 Nm (8 in-lb.).

Figure 3.4 Terminal Wiring

Release Screw

OUTPUT COMMON

Release Screw

A1+

B1+

Z1+

A2+

B2+

Z2+

OUTPUT 1

OUTPUT 3

A1-

B1-

Z1-

A2-

B2-

Z2-

OUTPUT 0

OUTPUT 2

OUTPUT +Vdc

Removing the Terminal Block

Remove the terminal block by turning the slotted terminal block release screws counterclockwise. The screws are attached to the terminal block, so it will follow as the screws are turned out.

ATTENTION

To avoid cracking the removable terminal block, alternate turning the slotted terminal block release screws.

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3-8 Installation and Wiring

Encoder Wiring

Differential encoders provide the best immunity to electrical noise. We recommend, whenever possible, to use differential encoders.

The wiring diagrams on the following pages are provided to support the Allen-Bradley encoders you may already own.

Differential Encoder Wiring

Figure 3.5 Differential Encoder Wiring

(1)

Allen-Bradley

845H Series

differential

encoder

Cable

GND

Shield

+VDC

COM

A1(+)

A1(–)

B1(+)

B1(–)

Z1(+)

Z1(–)

Power Supply

shield/housing Connect only if housing is electronically isolated from the motor and ground.

(1) Refer to your encoder manual for proper cable type. The type of cable used should be twisted pair, individually

shielded cable with a maximum length of 300m (1000 ft.).

Earth

Module Inputs

Differential Encoder Output Waveforms

The Figure 3.6 shows the different encoder output waveforms. If your encoder matches these waveforms, the encoder signals can be directly connected to the associated screw terminals on the module. For example, the A lead from the encoder is connected to the module’s A+ screw. If your encoder does not match these waveforms, some wiring modifications may be necessary. See Appendix B for a description of these modifications.

Figure 3.6 Differential Encoder Output Waveforms

A A

B B

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Installation and Wiring 3-9

Single-Ended Encoder Wiring (Open Collector)

Figure 3.7 Single-Ended Encoder Wiring

(1)

GND

(2)

Cable

Allen-Bradley 845H Series

single-ended encoder

Shield

shield/housing Connect only if housing is electronically isolated from the motor and ground.

(1) Refer to your encoder manual for proper cable type. The type of cable used should be twisted-pair, individually

shielded cable with a maximum length of 300m (1000 ft.).

(2) Calculate the value of the pull-up resistor (R), as shown below:

Earth

+VDC

COM

A1(+)

A1(–)

B1(+)

B1(–)

Z1(+)

Z1(–)

Power Supply

Module Inputs

Vcc Vmin–()

For 5V dc jumper position:

For 24V dc jumper position:

--------------------------------------=

Imin

Vcc Vmin–()



--------------------------------------1KΩ–



Imin

where:R = pull-up resistor value

Vcc = power supply voltage

Vmin = 4.2 V dc

Imin = 6.3 mA

Power Supply Voltage (Vcc) Pull-up Resistor Value (R)

5V dc 127 Ω 12V dc 238 Ω 24V dc 2140 Ω

Single-Ended Encoder Output Waveforms

The figure below shows the single-ended encoder output waveforms. When the waveform is low, the encoder output transistor is on. When the waveform is high, the encoder output transistor is off.

Figure 3.8 Single-Ended Encoder Output Waveforms

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3-10 Installation and Wiring

Single-Ended Wiring (Discrete Devices)

Figure 3.9 Discrete Device Wiring

Proximity Sensor

OUT

COM

OUT

COM

Photo-electric Sensor with Open Collector Sinking Output

OUT

COM

Solid-State Switch

(1)

+VDC

COM

A1(+)

A1(–)

B1(+)

B1(–)

Z1(+)

Z1(–)

Power Supply

Module Inputs

(1) Calculate the value of the pull-up resistor (R), as shown below:

Vcc Vmin–()

For 5V dc jumper position:

For 24V dc jumper position:

--------------------------------------=

Imin

Vcc Vmin–()



--------------------------------------1KΩ–



Imin

where:R = pull-up resistor value

Vcc = power supply voltage Vmin = 4.2 V dc Imin = 6.3 mA

Power Supply Voltage (Vcc) Pull-up Resistor Value (R)

5V dc 127 Ω 12V dc 238 Ω 24V dc 2140 Ω

Publication 1746-UM002B-EN-P - August 2004

Configuration and Programming

This chapter provides information about:

• selecting operating class

• module programming

• programming blocks

• programming block default values

Chapter

Selecting Operating Class

Power-up Reset

Module Programming

The 1746-HSCE2 module has two operating classes which are determined by the ID code used by the module.

Class 1 operation uses 8 input and 8 output words and is compatible with SLC 5/01 and above processors and the 1747-ASB module. Enter ID Code 3511 to select Class 1 operation.

Class 4 operation uses 23 input and 8 output words and is compatible with SLC 5/03 and above processors and with 1747-ACN15 and

-ACNR15 modules. Enter ID Code 15912 to select Class 4 operation.

See Operating Class on page 1-4 for more information on Class 1 and Class 4 operation.

Whenever power is cycled or the processor mode is switched to RUN, all counters are reset to their defaults. The counters, ranges, presets, etc., need to be reprogrammed. See the default settings on page 4-28.

Module programming consists of the following six blocks:

• Module Setup

• Counter Configuration

• Minimum/Maximum Count Value

• Minimum/Maximum Rate Value

• Program Ranges

• Counter Control

1 Publication 1746-UM002B-EN-P - August 2004

4-2 Configuration and Programming

Each block is made up of eight words. The first word is the control word. The remaining seven words are data words. The control word determines which parameters are in the data words. This programming method applies to both classes of operation. The programming blocks are described on pages 4-6 through 4-23.

Programming Cycle

Except for the Counter Control Block, all programming blocks are written to the module with a programming cycle. Programming cycles are controlled by the transmit and acknowledge bits.

A programming cycle consists of six steps.

1. Write the new data into the correct output image table words.

The lower byte of each configuration block indicates which block is being transferred. See the programming block descriptions on pages 4-6 to 4-28.

2. Each block that can be altered has a Transmit bit (O:e.0/15). Set

the Transmit bit in the output image table. The 1746-HSCE2 will not act on the new programming block until the Transmit bit is set.

3. Once the Transmit bit is set, an Acknowledge bit (I:e.0/15) is

received.

4. When the ladder logic detects that the Acknowledge bit is set, it

should check for errors. Error bits are only valid when the Acknowledge bit is set. The error bits are the PERR bit (I:e.0/13) and the MFLT bit (I:e.0/14).

5. If either bit is set, the programming block is rejected. The block

pointer is not incremented and initialization fails.

If neither error bit is set, the block pointer is incremented and the Transmit bit is reset, allowing the module to transfer the next block.

6. Once the desired configurable blocks have been transferred to

the module and the Maximum Block Address is recognized, the Counter Control Block is transferred to the output image table to enable the counters.

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Configuration and Programming 4-3

Data Format

In Class 4, the counter accepts rate data in either integer or floating-point data formats, depending upon the setting of the rate value bit. Both formats are explained below.

TIP

Count values are always in integer format. The format of rate values is selected in the Module Setup Block as either integer or floating-point formats. All other data is in integer format.

Integer Format

In integer format, two words may be needed to hold each data value because the values can exceed ±32768 (decimal) when the module is in Class 4 operation. The combined decimal value of both words is calculated as follows:

actual value = (value of first word x 1000) + value of second word

Both word values must have the same sign or a programming error results. If the value is positive, both words must be positive. If the value is negative, both words must be negative.

TIP

A value of zero in either word may be paired with either sign in the other word.

The following example illustrates how numbers are represented in integer format.

Table 4.1 Integer Format Example

First Word Second Word Data

12 345 12,345

-12 -345 -12,345

12 0 12,000

-12 0 -12,000

Floating-Point Format

Floating-point notation (IEEE 754 single-precision used) is difficult to read and use, but may be simplified by using programming software to view and use the data in a floating-point file.

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4-4 Configuration and Programming

Reading the Data

In the following example, the 1746-HSCE2 module is located in slot 3. The rate value, in floating point rate value format, is located in input data file words 4 and 5 (I:3.4 and I:3.5). To view the rate value for counter 1, use the copy instruction as shown below.

COP Copy File Source #I:3.4 Dest #F8:1 Length 1

The source is the input data file, and the destination is the floating point file. The length is 1, the number of elements of the destination file in the COP instruction.

Writing the Data

In the following example the floating point value is copied into integer words 1 and 2 of the Minimum/Maximum Rate Value programming block (N10:0-7). The 1746-HSCE2 module is located in slot 3.

COP Copy File Source #F8:1 Dest N10:1 Length 2

The source is the floating-point file, and the destination is an integer data file. The length is 2, the number of elements being copied into the destination file using the copy instruction.

Converting from Two-Word Integer to Floating-Point Format

You can use RSLogix500™ programming software to convert the values from integer to floating-point notation using the compute instruction, as shown.

In this example, the 1746-HSCE2 module is located in slot 3, the upper 4 digits of the rate value are stored in the input data file word 4 (I:3.4), and the lower 3 digits of the rate value are stored in input data file word 5 (I:3.5). The compute instruction is as follows:

CPT

CPT Compute Dest F8:1

Expression ( I:3.4 * 1000 ) + I:3.5

The destination is in the floating-point file F8.

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Converting from Floating-Point to Two-word Integer Format

RSLogix500 programming software can also be used to convert from floating-point to two-word integer format as shown.

F8:4 holds the number to be converted. It is divided by 1000 and the result is placed in F8:3.

0001

Configuration and Programming 4-5

TWO-WORD 1 TEMP

DIV Divide Source A F8:4

0.0 < Source B 1000.0

1000.0 < Dest F8:3

0.0 <

The value in F8:3 is moved to N7:34, yielding the upper word (Most Significant Word - MSW).

0002

TWO-WORD 1 MSW

MOV Move Source F8:3

0.0 < Dest N7:34 0<

Rung 3 is used only when the original value in F8:4 is positive. If the value in N7:34 was rounded up, as determined by comparing it to the floating point version in F8:3, the value must be adjusted by subtracting one from it. The lower (Least Significant Word) - LSW) is then calculated by subtracting (MSW multiplied by 1000) from the original value.

0003

FLOAT TO TWO-WORD INT VALUE

Grtr Than or Eql (A>=B) Source A F8:4

0.0 < Source B 0.0

0.0 <

TWO-WORD INT 1 MSW

Greater Than (A>B) Source A N7:34 0< Source B F8:3

0.0 <

TWO-WORD INT 1 LSW

CPT Compute Dest N7:35 0< Expression F8:4 - ( N7:34 * 1000.0 )

TWO-WORD INT 1 MSW

SUBGRTGEQ Subtract Source A N7:34 0< Source B 1 1< Dest N7:34 0<

Rung 4 is used only when the original value in F8:4 is negative. If the value in N7:34 was rounded up, as determined by comparing it to the floating point version in F8:3, the value must be adjusted by adding one to it. The lower (LSW) is then calculated by adding (MSW multiplied by 1000) to the original value.

FLOAT TO TWO-WORD

0004

INT VALUE

LES Less Than (A<B) Source A F8:4

0.0 < Source B 0.0

0.0 <

TWO-WORD INT 1 MSW

LES Less Than (A<B) Source A N7:34 0< Source B F8:3

0.0 <

TWO-WORD INT 1 MSW

ADD Add Source A N7:34 0< Source B 1 1< Dest N7:34 0<

TWO-WORD INT 1 LSW

CPT Compute Dest N7:35 0< Expression F8:4 + ( ( - N7:34 ) * 1000.0 )

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4-6 Configuration and Programming

Module Setup Block

Figure 4.1 shows the format of the Module Setup block. This block sets the module’s basic configuration and range allocation to the counters. Counters cannot be running when this block is sent to the module or a programming error results. Sending this block to the module sets all other module parameters to their default values. See Programming Block Default Values on page 4-28.

Figure 4.1 Module Setup Block Format

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Word 0

Word 1

Word 2

Word 3

Word 4

Words 5-7

0 0

TRMT

0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 01

DEBUG

INT

RVF

RESERVED: Must equal 0

0 0 0 0 0 0

PRA

Mode

Counter 1

Range Allocation

Counter 2

Range Allocation

Counter 3

Range Allocation

Programming Block Identification Bit

(Word 0, Bit 0)

This bit identifies the type of block.

TRMT: Transmit Bit

(Word 0, Bit 15)

A 0 to 1 transition starts a programming cycle. This bit is not set until all words are in the output table.

DEBUG: Debug Mode Selection Bit

(Word 0, Bit 12)

When this bit is set, the debug mode is activated. Debug mode returns the input data file showing current settings in the module setup block.

Up to three sets of ranges can be allocated. The last set is always allocated automatically. If three sets of ranges are allocated, the fourth and last set is shown in word 5 in debug mode. For details, see Debug Mode Operation on page 5-7.

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INT: Interrupt Enable

(Word 1, Bit 10)

Configuration and Programming 4-7

IMPORTANT

In Class 4, when this bit is set (1), the module generates an I/O interrupt to the SLC processor whenever one of the eight outputs changes state. When this bit is reset (0), the module will not generate an interrupt.

IMPORTANT

Interrupt mode is not available in Class 1. Setting this bit while using Class 1 causes a programming error.

An I/O interrupt must be defined if the INT bit is set. The I/O interrupt subroutine number is defined in the advanced configuration window of the program’s I/O configuration. See the SLC 500 Instruction Set Reference Manual, publication number 1747-RM001, for more information on I/O interrupts.

RVF: Rate Value Format

(Word 1, Bit 09)

IMPORTANT

In Class 4, the module transmits the rate value in a two-word integer format when this bit is reset (0). The module transmits the rate value in single-precision floating-point format when this bit is set (1).

This bit is not used in Class 1. Setting this bit while using Class 1 causes a programming error.

PRA: Program Range Allocation

(Word 1, Bit 08)

When this bit is set (1), the module programs the range allocation to the values in words 2, 3, and 4.

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4-8 Configuration and Programming

Op Mode: Operating Mode

(Word 1, Bits 01 and 00)

These two bits program the module’s operating mode. The combinations are shown below:

Table 4.2 Operating Mode Programming Bit Settings

Bit 01 Bit 00 Operating Mode

0 1 Mode 1

1 0 Mode 2

1 1 Mode 3

(1) Using the reserved setting causes a programming error.

Reserved

(1)

Range Allocation Values

(Words 2, 3, and 4, Bits 00 to 04)

Sixteen ranges are available for programming output on/off positions and rates. These ranges are assigned to the counters using these range allocation parameters. Each value is the number of ranges assigned to each counter.

The operating mode parameter is read before the range allocation values. The module’s operating mode determines which counters’ allocation values are read.

• In Mode 1, two counters are used. Only the Counter 1 allocation

value is read. All other ranges are automatically assigned to Counter 2. Set words 3 and 4 to 0.

• In Mode 2, three counters are used. The Counter 1 and Counter

2 allocation values are read. All other ranges are automatically assigned to Counter 3. Set word 4 to 0.

• In Mode 3, all four counters are used. The Counter 1, Counter 2,

and Counter 3 allocation values are read. All other ranges are automatically assigned to Counter 4.

The sum of the range allocation values cannot exceed 16, or the module responds with a programming error. Unused range allocation words in Modes 1 and 2 must equal zero, or an error occurs.

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IMPORTANT

The number of ranges for the last configured counter used must equal zero, otherwise the module fills in the value and errors, even if the value is correct.

Configuration and Programming 4-9

Range Allocation Examples

Mode 1 Example

In the Module Setup block below, 4 ranges are assigned to Counter 1. The remaining 12 are assigned to Counter 2. The last counter is not specified.

Figure 4.2 Module Setup in Mode 1 (Showing Hex Format)

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Hex

0000000000000001 Word 0 0001

0000000100000001 Word 1 0101

0000000000000100 Word 2 0004

0000000000000000 Word 3 0000

0000000000000000 Word 4 0000

0000000000000000 Word 5 0000

0000000000000000 Word 6 0000

0000000000000000 Word 7 0000

Mode 2 Example

In the Module Setup block below, four ranges are assigned to Counter

1. Four ranges are assigned to Counter 2, with the remaining 8 assigned to Counter 3.

Figure 4.3 Module Setup in Mode 2 (Showing Hex Format)

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Hex

0000000000000001 Word 0 0001

0000000100000010 Word 1 0101

0000000000000100 Word 2 0004

0000000000000100 Word 3 0004

0000000000000000 Word 4 0000

0000000000000000 Word 5 0000

0000000000000000 Word 6 0000

0000000000000000 Word 7 0000

IMPORTANT

The number of ranges for the last configured counter used must equal zero, otherwise the module fills in the value and errors, even if the value is correct.

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4-10 Configuration and Programming

Mode 3 Example

In the Module Setup block below, four ranges are assigned to Counter

1. Eight ranges are assigned to Counter 2. Two ranges are assigned to Counter 3. The last two ranges are assigned to Counter 4, but the counter is not specified.

IMPORTANT

The number of ranges for the last configured counter used must equal zero, otherwise the module fills in the value and errors, even if the value is correct.

Figure 4.4 Module Setup in Mode 3 (Showing Hex Format)

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Hex

0000000000000001 Word 0 0001

0000000100000011 Word 1 0103

0000000000000100 Word 2 0004

0000000000001000 Word 3 0008

0000000000000010 Word 4 0002

0000000000000000 Word 5 0000

0000000000000000 Word 6 0000

0000000000000000 Word 7 0000

Counter Configuration

Figure 4.5 shows the format of the Counter Configuration Block. This block programs the following parameters of the selected counters:

Block

Publication 1746-UM002B-EN-P - August 2004

• Counter Type

• Input Configuration

• Gate/Preset Mode

All four counters can be programmed with one block. When this programming block is sent to the module, the selected counter(s) cannot be running or a programming error results. Sending this programming block to the module erases all programmed output ranges of the selected counter(s).

Word 0

Word 1

Word 2 Word 3

Word 4 Word 5

Word 6 Word 7

Configuration and Programming 4-11

Figure 4.5 Counter Configuration Block Format

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

0 0

TRMT

0 0 0 0 0 0 0 0 0 G/P Mode Input Config

0 0 0 0 0 0

PGM4

DEBUG

Counter 4 Counter 3

PGM3

RESERVED: Must equal 0

0 0 0 0 0 010

PGM2

PGM1

0 0 0 0 0 0

CType

G/Pmode

Counter 1

CType

Counter 2

CType

Counter 3 or 4

CType

as indicated

Programming Block Identification Bit

(Word 0, Bit 01)

This bit identifies the type of block.

TRMT: Transmit Bit

(Word 0, Bit 15)

A 0 to 1 transition starts a programming cycle.

DEBUG: Debug Mode Selection Bit

(Word 0, Bit 12)

When this bit is set, the debug mode is activated. Debug mode returns the input data file showing current settings in the counter configuration block. See Debug Mode Operation on page 5-7.

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4-12 Configuration and Programming

PGMn: Program Counter Number Bits

(Word 0, Bits 08 to 11)

These four bits select the counters to which the programming block is applied. If the bit is reset, the associated counter is not programmed and the counter can be running when this block is sent. In addition, the associated programming words must be zero or a programming error occurs. A counter must be stopped when programmed with this block.

CType: Counter Type Bit

(Words 1 and 3, Bit 00; Word 5, Bits 00 and 08)

For each counter, this bit defines whether the counter is a ring or linear counter.

Table 4.3 Counter Type Programming Bit Settings

Bit Counter Type

0 Ring Counter

1 Linear Counter

Input Config: Input Configuration Bits

(Words 1 and 3, Bits 01 to 03)

These bits define the input configuration for Counters 1 and 2. Counters 3 and 4 are always Pulse/Internal Direction counters and do not require programming bits. The table below shows the input configuration programming bit values.

Table 4.4 Input Configuration Programming Bit Settings

Bit 03 Bit 02 Bit 01 Input Configuration

0 0 0 RESERVED

0 0 1 Up/Down Pulses

0 1 0 Pulse/External Direction

0 1 1 Pulse/Internal Direction

1 0 0 Quadrature X1

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1 0 1 Quadrature X2

1 1 0 Quadrature X4

1 1 1 RESERVED

Configuration and Programming 4-13

G/P Mode: Gate/Preset Mode Bits

(Words 1 and 3, Bits 04 to 06; Word 5, Bits 09 and 01)

Counters 3 and 4 have only two gate/preset modes available. Therefore, they have only one G/P mode bit. When this single bit is equal to zero, the No Preset mode is selected. When the bit is set, the Soft Preset mode is selected. Three bits determine the Gate/Preset Mode for Counters 1 and 2. The table below shows the G/P Mode settings for counters 1 and 2.

Table 4.5 Gate/Preset Mode Programming Bit Settings for Counters 1 and 2

Bit 06 Bit 05 Bit 04 Gate/Preset Mode

0 0 0 No Preset

0 0 1 Soft Preset Only

0 1 0 RESERVED

0 1 1 RESERVED

1 0 0 Store/Continue/Soft Preset

1 0 1 Store/Hold/Resume/Soft Preset

Minimum/Maximum Count Value Block

1 1 0 Store/Preset/Hold/Resume/Soft Preset

1 1 1 Store/Preset/Start/Soft Preset

TIP

All configurations and modes are not available to all counters. See the Summary of Available Counter Configurations on page 2-8.

Figure 4.6 shows the format of the Minimum/Maximum Count Value block. This programming block programs the minimum and maximum counter value and preset value parameters of the selected counter. As long as the min/max counter values are not changed from their currently programmed values, the counter can be running when this block is sent to the module. If the minimum/maximum values are changed, the counter must be stopped when this block is sent or a programming error is generated. The preset values can be changed with the counter running.

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4-14 Configuration and Programming

Figure 4.6 Minimum/Maximum Count Value Block

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Word 0

0 0

TRMT

Word 1 Upper 4 digits: Minimum Count Value Word 2 Lower 3 digits: Minimum Count Value Word 3 Upper 4 digits: Maximum Count Value Word 4 Lower 3 digits: Maximum Count Value Word 5 Upper 4 digits: Preset Value Word 6 Lower 3 digits: Preset Value Word 7

DEBUG

CNTR

AUTO PRESET

RESERVED: Must equal zero

0 0 0 0 010 0

Programming Block Identification Bit

(Word 0, Bit 02)

This bit identifies the type of block.

TRMT: Transmit Bit

(Word 0, Bit 15)

A 0 to 1 transition starts a programming cycle.

DEBUG: Debug Mode Selection Bit

(Word 0, bit 12)

When this bit is set, the debug mode is activated. Debug mode returns the input data file showing current settings in the Min./Max. Count Value block. For details, see Debug Mode Operation on page 5-7.

AUTO PRESET: Automatic Preset Bit

(Word 0, bit 10)

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This bit is used to automatically preset the count value. If this bit is set (1) when the programming block is sent, the count value is set to its preset value. If the bit is reset (0), the count value is not changed.

Configuration and Programming 4-15

CNTR No.: Counter Number Bits

(Word 0, Bit 08 and 09)

These two bits select the counter to which this programming block is applied.

Table 4.6 Counter Number Bit Settings

Bit 09 Bit 08 Counter Number

0 0 Counter 1

0 1 Counter 2

1 0 Counter 3

1 1 Counter 4

Preset Value

(Words 5 and 6)

The preset value can be programmed to any number between the minimum count value and the maximum count value. If the preset value does not fall between the minimum and maximum count values, a programming error results. The preset value is specified in the two-word integer data format as described in Integer Format on page 4-3. This value may be changed with the counter running, if minimum and maximum values are equal to their previously programmed values.

Minimum/Maximum Count Value Words

(Words 1 to 4)

The valid range of the parameter is dependent upon the operating class.

Table 4.7 Minimum/Maximum Count Values by Class

Class 1 Count Value Class 4 Count Value

Minimum -32,767 to +32,766 Minimum -8,388,607 to +8,388,606

Maximum (Min. Value +1) to +32,767 Maximum (Min. Value +1) to +8,388,607

The minimum/maximum count value can be changed after the output ranges have been programmed. However, they cannot be changed while the counter is enabled. When the minimum/maximum values are changed, they are checked against the ranges. If any of the new values are outside the range boundaries, the new values are not accepted, and the programming error bit is set. The preset value is

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4-16 Configuration and Programming

always included with this block, and its value must fall between the minimum/maximum count values.

The data is in the two-word integer format as described in Integer Format on page 4-3.

Counter Type

The meanings of the minimum and maximum counter values are dependent on the counter type.

Ring Counter

As a ring counter, the counter counts between the minimum and maximum values. When counting up, if the maximum value is reached, the counter rolls over to the minimum value. When counting down, if the minimum value is reached, the counter rolls over to the maximum value.

Minimum/Maximum Rate Value Block

Linear Counter

As a linear counter, the counter counts between the minimum and the maximum value. If the maximum value would be exceeded when the counter is counting up, the counter stops counting and an overflow bit is set in the status field of the counter. If, while counting down, the counter reaches a value that would be less than the minimum value, an underflow bit is set in the status field of the counter.

If the linear counter is in an overflow/underflow state, the rate value continues to update.

Figure 4.7 shows the format of the Minimum/Maximum Rate Value programming block. This block programs the minimum and maximum rate values of the selected counter. All counters can be running when this block is sent to the module.

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Figure 4.7 Min./Max. Rate Value Block

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Word 0

Word 1 Word 2 Word 3 Word 4 Word 5-7

0 0

TRMT

Minimum Rate Value in integer or floating point notation

Maximum Rate Value in integer or floating point notation

DEBUG

CNTR

No.

RESERVED: Must equal zero

Programming Block Identification Bit

(Word 0, Bit 03)

This bit identifies the type of block.

Configuration and Programming 4-17

0 0 0 010 0 0

TRMT: Transmit Bit

(Word 0, Bit 15)

A 0 to 1 transition starts a programming cycle.

DEBUG: Debug Mode Selection Bit

(Word 0, bit 12)

When this bit is set, the debug mode is activated. Debug mode returns the input data file showing current settings in the Min./Max. Rate Value block. For details, see Debug Mode Operation on page 5-7.

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4-18 Configuration and Programming

CNTR No.: Counter Number Bits

(Word 1, Bits 08 and 09)

These two bits select the counter to which this programming block is applied.

Table 4.8 Counter Number Bit Settings

Bit 09 Bit 08 Counter Number

0 0 Counter 1

0 1 Counter 2

1 0 Counter 3

1 1 Counter 4

Minimum/Maximum Rate Value Words

(Words 1 to 4)

The valid range of this parameter is dependent on the operating class of the module.

Class 1 Rate Value (Hz) Class 4 Rate Value (Hz)

Minimum -32,767 to +32,766 Minimum -1,000,000 to +999,999

Maximum (Min. Value +1) to +32,767 Maximum (Min. Value +1) to +1,000,000

If the calculated rate value is less than the minimum value, a rate underflow bit is set in the input image table. If the calculated rate value is greater than the maximum value, a rate overflow bit is set in the input image table. Outputs assigned to the counter still function normally.

Operating Class

The format of the minimum/maximum rate values depends on the operating class of the module.

Class 1

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When the module is operating as Class 1, the minimum/maximum rate values are programmed in two-word integer format.

Configuration and Programming 4-19

Class 4

When the module is operating as Class 4, the data format of the minimum/maximum rate values is determined by the rate value format bit in the Module Setup programming block. When this bit specifies that the rate value be in floating-point format, the minimum/maximum rate values are also programmed in floating-point format. When the rate value format bit specifies integer format, the minimum/maximum rate value is also in two-word integer format.

When programmed in integer format, the data has the same format as described in Integer Format on page 4-3.

Program Ranges Block

TIP

Figure 4.8 shows the format of the Program Ranges programming block. This block programs the following parameters:

• Associated Counter

• Range Type

• Range Number

• Range Start Point

• Range End Point

• Output State

All counters can be running when this block is sent to the module.

The minimum/maximum rate values can be changed after output ranges have been programmed. The new values are checked against the ranges. If the new values are outside the range boundaries, the new values are not accepted, and the programming error bit is set.

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4-20 Configuration and Programming

Figure 4.8 Program Ranges Block

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Word 0

Word 1 Range Number

0 0

TRMT

DEBUG

RType

CNTR

0 0 010 0 0 0

Word 2 Word 3 Word 4 Word 5 Word 6

Word 7

0 0 0 0 0 0 0 0

Range Start Value

Range Stop Value

RESERVED: Must equal zero

Programming Block Identification Bit

(Word 0, Bit 04)

This bit identifies the type of block.

TRMT: Transmit Bit

(Word 0, Bit 15)

A 0 to 1 transition starts a programming cycle.

Output State

Virtual Real

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DEBUG: Debug Mode Selection Bit

(Word 0, bit 12)

When this bit is set, the debug mode is activated. Debug mode returns the input data file showing current settings in the Program Ranges block. For details, see Debug Mode Operation on page 5-7.

Configuration and Programming 4-21

CNTR No.: Counter Number Bits

(Word 0, Bits 08 and 09)

These two bits select the counter to which this programming block is applied. The counter number and range number must correspond to a valid combination as determined by the information in the Module Setup Block. See Range Allocation Values on page 4-8.

Table 4.9 Counter Number Programming Bit Settings

Bit 09 Bit 08 Counter Number

0 0 Counter 1

0 1 Counter 2

1 0 Counter 3

1 1 Counter 4

The valid range of this parameter is dependent on the programmed operating mode.

Rtype: Range Type

(Word 0, Bit 10)

When this bit equals zero, the range specified in this block is a count range. The output state is active when the count value of the associated counter is within the programmed range.

When this bit equals one, the range specified is a rate range. The output state is active when the rate value of the associated counter is within the programmed range.

Range No.: Range Number Bits

(Word 1, Bits 00 to 15)

These bits define which ranges (0-15) will be programmed or reset. If a bit is set (1), the corresponding range is programmed. The number of ranges available is programmed with the range allocation parameters in the Module Setup programming block.

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4-22 Configuration and Programming

The range number word is subject to the following special conditions:

• If the range start value equals the range stop value and word 6

equals zero, the range indicated is reset.

• If a range or ranges not belonging to the indicated counter are

set, the block is rejected and a programming error results.

• If the range number equals zero and words two through 7 are

equal to zero, all ranges associated with the counter are reset.

• Setting more than one range bit when the values for range start

and range stop are different causes a programming error.

TIP

Each of the 16 ranges has a unique bit. For example, the ranges allocated for Counter 2 begin sequentially after the ranges for Counter 1.

Range Start Value, Range Stop Value

(Words 2 to 5)

When specifying a count range, the range start and range stop values must be within the range of the minimum and maximum count values programmed in the Minimum/Maximum Count Value programming block.

The rate range must be programmed using the same data format as the rate value. If the rate value is specified in floating-point format, the rate range is also. If the rate value is specified in integer format, the rate range is programmed in integer format.

Count values are always in two-word integer format, as described in Integer Format on page 4-3.

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If the range start and range stop numbers are equal, the range specified by the range number is erased from memory.

Output State: Output State Byte

(Word 6, Bits 00 to 07)

This byte defines the state of the outputs while the programmed range is active. It is combined with other output state bytes and output masks to define the actual output states. See Determining Actual

Configuration and Programming 4-23

Output State on page 4-27 for a description of how the bytes are combined.

If the start value is less than the stop value, the output state is applied when the count or rate is within the range specified by the two values. (For example, see ranges 1 through 3 on page 2-13.) If the start value is greater than the stop value, the output state is applied when the count or rate is outside the range. (For example, see range 4 on page 2-13.) At least one of these bits must be set when programming a range or a programming error is generated.

Counter Control Block

Figure 4.9 shows the format of the Counter Control programming block. This block allows you to change the state of the following counter controls for all four counters in one cycle:

• Enable/Disable Counter

• Soft Preset (if enabled)

• Internal Direction (if enabled)

• Output ON Mask

• Output Enable Mask

• Count or Rate Value (Class 1 only)

• Enable/Disable Range

All counters can be running when this block is sent to the module.

Figure 4.9 Counter Control Block Format

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Word 0

Word 1

Word 2

Word 3

Word 4

Word 5 Output Enable Mask Output ON (OR) Mask Word 6 Enable Ranges Word 7

0 0 0 0 0 0 0 010 0 0 0 0 0 0

0 0 0 0 0 0

RESERVED: Must Equal Zero

0 0 0 0 0

C/R1

0 0 0 0 0

C/R2

0 0 0 0 0

C/R3

0 0 0 0 0

C/R4

ID1

ID2

ID3

ID4

SP1

SP2

SP3

SP4

EN1

EN2

EN3

EN4

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4-24 Configuration and Programming

Transmit Bit

The transmit bit is not used. A programming cycle is not needed to program these bits. The block is acted upon for every program scan that bit 07 of word 0 is set. Therefore, a transmit bit is not used.

TIP

If an invalid condition exists, the PERR and ACK bits are set and all data in the block is considered invalid.

Programming Block Identification Bit

(Word 0, Bit 07)

This bit identifies the type of block.

Control Words

(Words 1 to 4)

Each counter has its own control word.

Table 4.10 Control Word Assignments

Control Words Counter Number

Word 1 Counter 1

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Word 2 Counter 2

Word 3 Counter 3

Word 4 Counter 4

In the following programming bits, (n) equals the counter number.

ENn: Enable Counter (n) Bit

(Words 1 to 4, Bit 00)

On power-up or when the EN(n) bit is reset, the counter is in a frozen state. The counter is free to run when the EN(n) bit is set. All of the counters must be disabled before transmitting a Module Setup programming block. The affected counters must be disabled before transmitting a Counter Configuration programming block. The affected

Configuration and Programming 4-25

counter must also be disabled before sending new minimum/maximum count values.

TIP

Disabling a counter does not cause an output with the counter to turn off. As long as the count value is within the programming range the output remains active.

Enabling a counter that is not present causes a programming error.

SPn: Soft Preset Only (n) Bit

(Words 1 to 4, Bit 01)

When the counter has its gate/preset mode set to any mode except No Preset, the counter is set to its preset value when the corresponding bit makes a 0 to 1 transition. Setting this bit in No Preset mode causes a programming error.

TIP

Soft preset does not work when the counter’s P(n) bit is changed from 1 to 0 to 1 at the same time that the SP(n) bit is changed from 1 to 0 to 1. For example, when word 1 goes from 8003H to 0000H and back to 8003H, counter 1 is not preset.

IDn: Internal Direction (n) Bit

(Words 1 to 4, Bit 02)

When the counter has its input configuration set to Pulse/Internal Direction, the state of this bit determines the direction in which the counter counts. When this bit is reset, the counter increments. When this bit is set, the counter decrements. Setting this bit in other than the Pulse/Internal Direction mode causes a programming error.

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4-26 Configuration and Programming

C/R(n): Count or Rate Value Bit

(Words 1 to 4, Bit 08)

These bits are only used when the module is configured for Class 1 operation. Depending on the operating mode, the module only transmits the counter’s count or rate value. The count value is transmitted when the C/R(n) bit is reset. The rate value is transmitted when the C/R(n) bit is set. When configured for Class 4, setting these bits generates a programming error.

P(n): Program Counter (n) Bit

(Words 1 to 4, Bit 15)

If this bit is reset, bits 1 to 14 must be zero or a programming error results. This bit must be set before the counter control bits are updated for the counter. This allows the user to write 0000H into unused words in the block without inadvertently changing the state of a counter. When this bit is zero, all other bit values in the word are retained inside the module. This affects the soft preset, SP(n), as described in the note on page 4-25.

Output ON (OR) Mask

(Word 5, Bits 00 to 07)

This is a bit pattern which allows the user program to globally turn on outputs, regardless of the programmed ranges and Enable Ranges bytes. When a bit in this byte is zero, the output will turn on based on the programmed ranges, the state of the enable ranges byte, and Output Enable Mask. When this bit is one, the output is on if the corresponding bit in the Output Enable Mask equals one.

Output Enable Mask

(Word 5, Bits 08 to 15)

This is a bit pattern to globally turn off outputs, regardless of the programmed ranges and enable ranges bytes. When a bit in this mask is zero, the output is off regardless of the programmed ranges and the state of the Output ON Mask. When a bit in this mask is one, the

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Configuration and Programming 4-27

output turns on based on the programmed ranges, the state of the enabled ranges byte, and the Output ON Mask.

TIP

The outputs do not turn on if the corresponding bits are not set here.

Enable Range

(Word 6)

When a bit in this word is reset (0), the corresponding range (1-16) is disabled, and the output state for the range is ignored.

When a bit in this word is set (1), the corresponding output state for the range is used to determine the state of the eight outputs.

Bits in this word should be zero, unless you want to specifically enable the range.

Determining Actual Output State

The actual state of an output is determined in five steps, as follows:

1. The enable range bits determine if a range should be checked to

see if it is active.

2. The output state bytes of all active ranges that are enabled are

logically ORed.

3. The Output ON Mask is logically ORed with the results of step 2.

4. The Output Enable Mask is logically ANDed with the results of

step 3.

5. The result is applied to the outputs.

IMPORTANT

Outputs are always off when the SLC processor is in Program mode. The outputs are only enabled when the processor is in the Run mode.

Outputs not assigned to a counter can only be turned on with the Output ON Mask.

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4-28 Configuration and Programming

Figure 4.10 Determining Actual Outputs

Range Bit Setting 11001100

Output ON Mask 00010001

Output Enable Mask 00001111

Actual Outputs 00001101

Programming Block Default

The following tables list the default values for all of the programmed parameters in each class and operating mode. The default operating

Values

mode for each class is mode 1.

Class 1

Table 4.11 Class 1, Mode 1 Default Values

Parameter Counter 1 Counter 2

Debug Mode Selection Inactive

Range Allocation 8 8

Counter Type Ring Ring

Input Configuration X1 Quadrature X1 Quadrature

Gate/Preset Mode Store/Preset/Start Store/Preset/Start

Minimum Count -32,767 -32,767

Maximum Count +32,767 +32,767

Minimum Rate -32,767 -32,767

Maximum Rate +32,767 +32,767

Preset Value 0 0

All Output Ranges Not programmed.

Interrupt Enable Interrupt disabled

Rate Value Format Integer (not programmable)

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Configuration and Programming 4-29

Table 4.12 Class 1, Mode 2 Default Values

Parameter Counter 1 Counter 2 Counter 3

Debug Mode Selection Inactive

Range Allocation 8 4 4

Counter Type Ring Ring Ring

Input Configuration X1 Quadrature Pulse/Internal Pulse/Internal

Gate/Preset Mode Store/Preset/Start No Preset No Preset

Minimum Count -32,767 -32,767 -32,767

Maximum Count +32,767 +32,767 +32,767

Minimum Rate -32,767 -32,767 -32,767

Maximum Rate +32,767 +32,767 +32,767

Preset Value 0 0 0

All Output Ranges Not programmed.

Interrupt Enable Interrupt disabled

Rate Value Format Integer (not programmable)

Table 4.13 Class 1, Mode 3 Default Values

Parameter Counter 1 Counter 2 Counter 3 Counter 4

Debug Mode Selection Inactive

Range Allocation 4444

Counter Type Ring Ring Ring Ring

Input Configuration Pulse/Internal Pulse/Internal Pulse/Internal Pulse/Internal

Gate/Preset Mode No Preset No Preset No Preset No Preset

Minimum Count -32,767 -32,767 -32,767 -32,767

Maximum Count +32,767 +32,767 +32,767 +32,767

Minimum Rate -32,767 -32,767 -32,767 -32,767

Maximum Rate +32,767 +32,767 +32,767 +32,767

Preset Value0000

All Output Ranges Not programmed.

Interrupt Enable Interrupt disabled

Rate Value Format Integer (not programmable)

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4-30 Configuration and Programming

Class 4

Table 4.14 Class 4, Mode 1 Default Values

Parameter Counter 1 Counter 2

Debug Mode Selection Inactive

Range Allocation 8 8

Counter Type Ring Ring

Input Configuration X1 Quadrature X1 Quadrature

Gate/Preset Mode Store/Preset/Start Store/Preset/Start

Minimum Count -8,388,607 -8,388,607

Maximum Count +8,388,607 +8,388,607

Minimum Rate -1,000,000 -1,000,000

Maximum Rate +1,000,000 +1,000,000

Preset Value 0 0

All Output Ranges Not programmed.

Interrupt Enable Interrupt disabled.

Rate Value Format Integer

Table 4.15 Class 4, Mode 2 Default Values

Parameter Counter 1 Counter 2 Counter 3

Debug Mode Selection Inactive

Range Allocation 8 4 4

Counter Type Ring Ring Ring

Input Configuration X1 Quadrature Pulse/Internal Pulse/Internal

Gate/Preset Mode Store/Preset/Start No Preset No Preset

Minimum Count -8,388,607 -8,388,607 -8,388,607

Maximum Count +8,388,607 +8,388,607 +8,388,607

Minimum Rate -1,000,000 -1,000,000 -1,000,000

Maximum Rate +1,000,000 +1,000,000 +1,000,000

Preset Value 0 0 0

All Output Ranges Not programmed.

Interrupt Enable Interrupt disabled.

Rate Value Format Integer

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Configuration and Programming 4-31

Table 4.16 Class 4, Mode 3 Default Values

Parameter Counter 1 Counter 2 Counter 3 Counter 4

Debug Mode Selection Inactive

Range Allocation 4444

Counter Type Ring Ring Ring Ring

Input Configuration Pulse/Internal Pulse/Internal Pulse/Internal Pulse/Internal

Gate/Preset Mode No Preset No Preset No Preset No Preset

Minimum Count -8,388,607 -8,388,607 -8,388,607 -8,388,607

Maximum Count +8,388,607 +8,388,607 +8,388,607 +8,388,607

Minimum Rate -1,000,000 -1,000,000 -1,000,000 -1,000,000

Maximum Rate +1,000,000 +1,000,000 +1,000,000 +1,000,000

Preset Value 0000

All Output Ranges Not programmed.

Interrupt Enable Interrupt disabled.

Rate Value Format Integer

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4-32 Configuration and Programming

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Chapter

Start Up, Operation, Troubleshooting, and Debug Mode

This chapter provides start up, operation, and troubleshooting information, as well as detailing the operation of the debug mode.

Start Up

The following steps will assist you in the start up of your 1746-HSCE2 module.

1. Install the module in the chassis.

2. Wire the input and output devices.

3. Configure and program your SLC processor to operate with the

module.

4. Apply power to the SLC system and to the attached inputs and

outputs.

When power is applied to the SLC system, the processor and the module run through a power up diagnostic sequence. After the diagnostics are successfully completed, the SLC processor enters run mode and normal operation begins.

If the SLC processor was in the program mode when power was removed, it returns to the program mode when power is reapplied. Place the SLC processor into run mode using an SLC programming device or keyswitch.

Normal Operation

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During normal operation, the LEDs are illuminated as follows:

• The fault LED [FLT] is off.

• LEDs A1, A2, B1, B2, Z1, and Z2 illuminate, indicating the inputs

are energized.

• LEDs 1, 2, 3, and 4 illuminate, indicating the status of the

physical outputs.

• The run LED is on to indicate the module’s running status.

5-2 Start Up, Operation, Troubleshooting, and Debug Mode

Figure 5.1 LED Locations

Input Status

COUNTER

OUTPUT STATUS

1023

A1 B1 Z1

A2 B2 Z2

INPUT STATUS

HSCE2

RUN

FLT

Output Status

Running Status

Fault Status

Troubleshooting

Three types of module-generated errors can occur:

• module diagnostic errors

• module programming errors

• application errors.

The Fault LED indicates a module diagnostic error.

Fault LED Problem

Solid Red Module diagnostic error. Cycle power. If condition persists, replace

the module. Refer to “Module Diagnostic Errors” below.

Flashing Red Module output fuse has been tripped.

The counter status bytes indicate application errors encountered by the module.

Module Diagnostic Errors

A module diagnostic error is produced if the power up self-test or run-time-watchdog test fails. This is an indication of a potential hardware failure.

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When it detects a diagnostic error, the module halts all operations. Outputs are reset to zero, and a fault indication is sent to the SLC processor. The module fault LED turns solid red.

In response to a diagnostic error, cycle power. If the condition persists, replace the module.

Start Up, Operation, Troubleshooting, and Debug Mode 5-3

Module Programming Errors

A programming error is caused by improper set up of a module parameter. The module responds to a programming error by setting the programming error bit. When this bit is set, the entire programming block is rejected.

The programming error bit is set when a reserved bit is set. It is also set under the following conditions:

Table 5.1 Error Conditions by Programming Block

Programming Block

Module Setup • Operating mode bits are not set to a valid pattern.

Counter Configuration

Min./Max. Count Value

Error Conditions

• A counter’s range allocation value is greater than 16.

• The sum of all range allocation values is greater than 16.

• The range allocation value for Counter 2 and/or Counter 3 is

nonzero and the programmed operating mode has the counter disabled.

• A counter or counters were running when the block was sent.

• The INT bit was set in Class 1.

• The RVF bit was set in Class 1.

• Counter number bits are not set to a valid number.

(Operating mode may be incorrect.)

• Input configuration is invalid for the counter.

(Operating mode may be incorrect.)

• G/P mode is invalid for the counter.

(Operating mode may be incorrect).

• The selected counter was running when the block was sent.

• The program counter number bits are not set for a counter that

has one or more bits set in its corresponding counter setup word.

• Counter number bits are not set to a valid number. (Operating

Mode may be incorrect.)

• The minimum count is outside its valid range.

• The maximum count is outside its valid range.

• The maximum count is less than or equal to Minimum Count.

• Programmed output count ranges are outside the bounds of the

new minimum/maximum count values.

• The preset value is outside its valid range.

• Counter was running when the minimum/maximum count

value was changed.

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5-4 Start Up, Operation, Troubleshooting, and Debug Mode

Table 5.1 Error Conditions by Programming Block

Programming Block

Min./Max. Rate Value

Program Ranges

Counter Control

Error Conditions

• Counter number bits are not set to a valid number.

(Operating Mode may be incorrect.)

• The minimum rate is outside its valid range.

• The maximum rate is outside its valid range.

• The maximum rate is less than or equal to the Minimum Rate.

• Programmed output rate ranges are outside the boundaries of

the new minimum/maximum rate values.

• Rate values may be in the wrong format.

• The counter number bits are not set to a valid number.

(Operating mode may be incorrect.)

• The range number is greater than the programmed range

allocation value

• The range start value is outside its valid range.

• The range stop value is outside its valid range.

• Range values may be in the wrong format.

• The soft preset bit is set while in No Preset mode.

• The internal direction bit is set while not in the internal

direction mode.

• A counter that is not valid in the selected mode has its enable

counter bit set.

Application Errors

The module can encounter the following application errors.

Linear Counter Overflow/Underflow

When the maximum count would be exceeded, the counter overflow bit in the counter status byte is set.

When the count would become one lower than the minimum count, the count underflow bit in the counter status byte is set.

When the module is in overflow condition, the programmed maximum count value is reported and ranges that include the value will still be acted upon. Likewise, in underflow condition, the minimum count value is reported, and ranges including it are affected.

Rate Overflow/Underflow

The rate overflow bit is set when the rate is more than the maximum rate value.

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Start Up, Operation, Troubleshooting, and Debug Mode 5-5

The rate underflow bit is set when the rate value is less than the minimum rate value.

When the module is in overflow condition, the programmed maximum rate value is reported and ranges that include the value will still be acted upon. Likewise, in underflow condition, the minimum rate value is reported, and ranges including it are affected.

Counter Value Does Not Change

Check the LEDs associated with the Channel A and B inputs which have pulses coming in. The A and B LEDs should flash whenever pulses are being received by the 1746-HSCE2 module.

If the A and B LEDs do not flash, check the power to the input sensor and the wiring from the sensor to the module.

If the A and B LEDs flash, make sure that the configuration of the module is complete and counters are enabled.

Counter Value/Rate Value Goes in the Wrong Direction

If single-ended encoder inputs are used, swap channels A and B to change the direction. If differential encoder inputs are used, swap A(+) and A(-) wires.

If pulse and direction inputs are used, check the direction and input type.

If using up and down pulses mode, make sure inputs A and B have not been switched.

Output Does Not Turn On

Make sure the SLC processor is in run mode.

Check the output’s LED.

If the LED is illuminated, check the power supply and its connections to the module. Also check the connections to the output device.

If the LED is not illuminated, make sure the SLC processor is in the run mode, and that a module fault has not occurred. Check the output status field of the input image to see if the module is trying to energize the output. If not, make sure that the enable ranges byte and the output OFF mask are set.

Check the fuse status bit.

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5-6 Start Up, Operation, Troubleshooting, and Debug Mode

Output Does Not Turn Off

Check the associated module LED for the output.

If the LED is illuminated, check your program operation.

If the LED is not illuminated, check the wiring to your output device. Check the leakage current of your connected device.

Soft Preset Does Not Work

Soft preset does not work when the counter’s P(n) bit is changed from 1 to 0 to 1 at the same time that the SP(n) bit is changed from 1 to 0 to

1. For example, when word 1 goes from 8003H to 0000H and back to 8003H, counter 1 is not preset.

Application Programming Errors Affecting Initialization

Typically, ladder logic manipulates 1746-HSCE2 parameters twice. First, the ladder logic initializes the module at power-up using a handshaking procedure shown in Application Examples 1, 2, and 3 in Chapter 6. After initialization, ladder logic can be used to control the 1746-HSCE2 dynamically. For example, the program can manipulate the module’s counter preset values (see Example 5 on page 6-18), or the program can soft preset a module counter. The programmer must be very careful to ensure that ladder logic programs intended to manipulate module parameters after initialization do not affect the initialization process.

HSCE2_INIT_DONE

B3:0

0001

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A typical programming mistake is to use OTE instructions to set 1746-HSCE2 output image bits intended for post-initialization operations (for example, soft presets). OTE instructions set or reset the bit depending on whether the rung conditions are true or false. For example, the following ladder rung sets the bit if the condition is true, meaning bits B3/0 and B3/6 are set. However, it also clears the bit if the rung condition is false, when either B3/0 or B3/6 is reset. The result is that this logic, when scanned, manipulates the module’s output image even if it was only intended to run after initialization was complete.

Figure 5.2 OTE Instruction

SOFT_PRESET_TRGR

B3:0

HSCE2_CFG_BLK_1/1

O:1.1

Most programming errors are easy to locate, since the 1746-HSCE2 error bit (B3/1) is set and the configuration block pointer (N11:0) points at the configuration block during which the error occurred. However, errors that affect initialization are often very difficult to find

Start Up, Operation, Troubleshooting, and Debug Mode 5-7

due to their unpredictable nature. Even if the configuration block looks satisfactory in the N10 data file, the data block in the module’s output image may not be satisfactory.

The best way to check for this problem is to individually search the ladder logic program for all module output words (O:e.0, O:e.1, etc.). Carefully check all ladder logic which manipulates the 1746-HSCE2 output image to ensure that the output image is not corrupted during initialization.

Debug Mode Operation

The debug mode allows you to look at the existing module setup of the programming blocks. When invoked, debug mode echoes back the programming data instead of showing counts and rates in the input data file.

IMPORTANT

The Counter Control block does not support the debug mode. Setting the debug bit (word 0, bit 12) in the Counter Control block causes the block to ignore all commands. However, rates and counts continue to be counted. When the debug bit is reset, the module resumes accepting commands.

Activating Debug Mode

Setting the debug bit (word 0, bit 12) in the programming block activates the debug mode. You must also set the block type code, the low byte of word 0, to identify the programming block. The transmit (TRMT), acknowledge (ACK), and programming error (PERR) bit operation is unaffected by debug mode. Depending upon the programming block, other bits may also be required, as described below.

In the Module Setup Block

For the Module Setup Block, the required bits for the debug mode are the transmit bit, the debug bit, and the block type byte. All other bits in the module setup word 0 must be set to 0. Words 1 through 7 are ignored by the module while in debug mode.

Publication 1746-UM002B-EN-P - August 2004

5-8 Start Up, Operation, Troubleshooting, and Debug Mode

Figure 5.3 Required Bits for Module Setup and Counter Configuration Blocks

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Word 0

TRMT

0 0

0 0 0 0 BLOCK TYPE

DEBUG

The debug view of this block shows the range allocation of all four counters. The fourth counter is shown in word 5. The PRA bit (word 0, bit 08) is never set.

In the Counter Configuration Block

The required bits for debug mode in the Counter Configuration Block are the transmit bit, the debug bit, and the block type byte. Bits 13 and 14 must be zero. The values of words 1 through 7 are ignored by the module while in debug mode. The PGM(n) bits (word 0, bits 08 to

11) are never set in this block.

Figure 5.4 Required Bits for Counter Configuration Block

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Word 0

0 0

TRMT

0 0 0 0 BLOCK TYPE

DEBUG

In the Minimum/Maximum Count Value Block

For this block, the transmit bit, the debug bit, the block type byte, and the counter number are required for each configured counter. Word 0 must be used for each configured counter individually. Bit 10 is ignored and bits 11, 13, and 14 must be zero. The values of words 1 through 7 are ignored by the module while in debug mode.

Figure 5.5 Required Bits for Min./Max. Count Value Block

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Word 0

TIP

0 0

TRMT

0 X

DEBUG

If the counter number entered is not valid, the debug mode returns a programming error.

CNTR

No.

BLOCK TYPE

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Start Up, Operation, Troubleshooting, and Debug Mode 5-9

In the Minimum/Maximum Rate Value Block

For this block, the transmit bit, the debug bit, the block type byte, and the counter number are required for each configured counter. Word 0 must be used for each configured counter individually. Bits 10, 11, 13, and 14 must be zero. The values of words 1 through 7 are ignored by the module while in debug mode.

Figure 5.6 Required Bits for Min./Max. Rate Value Block

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Word 0

TIP

0 0

TRMT

0 0

DEBUG

If the counter number entered is not valid, the debug mode returns a programming error.

CNTR

No.

BLOCK TYPE

In the Program Ranges Block

To activate the debug mode in the Program Ranges block, the transmit bit, the debug bit, the block type byte, and the range number word (word 1, bits 0 - 15) are required for each range individually. The counter number (word 0, bits 08 and 09) must be zero or a programming error results. The values of any other bits or words 2 through 7 are ignored by the module while in debug mode.

Figure 5.7 Required Bits for Program Ranges Block

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Word 0

Word 1

0 0

TRMT

0 0 0 0 BLOCK TYPE

DEBUG

Range Number

TIP

If more than one bit in word 1 is set (1), the module returns a programming error.

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5-10 Start Up, Operation, Troubleshooting, and Debug Mode

EXAMPLE

Activating Debug Mode

1. Clear the output image table.

2. Set the required bits in the block that will be

echoed back.

3. Set the debug mode bit.

4. Set the transmit bit.

Once the steps above are complete, you can reference the input image words to reflect the block’s configuration.

NOTE: Only the first eight words in the input image have meaning in Class 4.

Publication 1746-UM002B-EN-P - August 2004

Chapter

Application Examples

This chapter contains the following application examples:

• Example 1 uses the 1746-HSCE2 in Class 1, mode 3 to count four

single-ended, high-speed pulse train inputs using direct addressing only (SLC 5/01™ or SLC 5/02™).

• Example 2 tracks counts and speeds from two quadrature

encoders with indirect addressing (SLC 5/03™ and above). The module is used in Class 4, mode 1.

• Example 3 uses the 1746-HSCE2 in Class 1, mode 3 to count two

single-ended, high-speed inputs with indexed addressing and the multi-channel high speed counter in a remote I/O chassis

(PLC-5

scanner).

• Example 4 illustrates the use of soft presets, expanding on

Example 2.

• Example 5 changes presets dynamically using the min/max

count block and working from the Example 2 program.

• Example 6 shows how you can use the Min/max Count block

preset value to simulate retentive counters, by modifying the Example 2 program.

In these examples, if a programming error occurs (PERR = 1), the error bit (B3:0/1) is set, and N11:0 points to the configuration block that was last sent to the module.

TIP

Any parameters which are defaults (see Programming Block Default Values on page 4-28) need not be programmed. For example, if you want all the default values of Class 4 operation, then you only need to configure the module as Class 4 and send a Counter Control block to enable the counters.

The data tables follow the ladder logic. The N10 data table is in hex format to improve readability.

1 Publication 1746-UM002B-EN-P - August 2004

6-2 Application Examples

Example 1 - Direct

This example sets up the module to count the number of pulses from a high-speed device and apply that information to your ladder

Addressing

Prior to use, the programmer sets N11:2 to the total number of data blocks which will be entered into file N10 (not including the Counter Control Block), adds one rung for each configuration block (including the Counter Control Block), and initializes the data blocks in file N10. Ten integer data blocks are used (instead of eight) to simplify the display in data windows. Note: The Counter Control Block rung differs from the other rungs because the Counter Control Block does not require hand-shaking. The first pass of the program initializes the following values:

1. The HSCE2 initialization done bit (B3/0) is unlatched.

2. The HSCE2 error bit (B3/1) is cleared.

3. The Counter Configuration Data Block is cleared. Note: The init HSCE2 routine (ladder file 9) is bypassed during the first pass to ensure the Configuration Data Block is reset prior to transfer of the first configuration block

4. The transfer data block offset (N11:0) is cleared; i.e. the first data block starts at offset 0 in N10 file.

5. Max data block address (N11:0) is calculated as: Total Data Blocks (N11:2) x 10 words/data block.

FIRST_PASS

S:1

0000

program. The module is in Class 1, mode 3, with 4 counters available.

Ladder File 8 - HSCE2

HSCE2_INIT_DONE

B3:0

HSCE2_ERROR

B3:0

U 1

FLL Fill File Source 0

Dest Length 8

#O:1.0

0001

0002

0003

If the HSCE2 initialization is not done, and the HSCE2 has not errored, call the HSCE2 initialization routine.

FIRST_PASS

S:1

HSCE2_INIT_DONE

B3:0

HSCE2_ERROR

B3:0

DATA_BLOCK_OFFSET

MOV

MOV Move Source 0 0< Dest N11:0 140<

MAX_BLOCK_ADDR

MUL

MUL Multiply Source A 10 10< Source B N11:2 14< Dest N11:1 140<

JSR

JSR Jump To Subroutine SBR File Number U:9

RET

Return

END

Publication 1746-UM002B-EN-P - August 2004

Ladder File 9 - HSCE2 Initialization Routine

Programming ladder file 9 shows the direct addressing required to set up the programming blocks in this example.

Copy Module Setup Block to the HSCE2 and set transmit bit.

Application Examples 6-3

0000

0001

0002

0003

DATA_BLOCK_PTR HSCE2_XMIT

EQU

EQU O:1 Equal Source A N11:0 140< Source B 0 0<

1746-HSCE2

HSCE2_ACK

I:1

1746-HSCE2

Copy File Source #N10:0 Dest #O:1.0 Length 8

When the previous block is completed (transmit and acknowledge bit are reset), copy Counter Configuration Block to the HSCE2 and set transmit bit (O:e.0/15).

DATA_BLOCK_PTR HSCE2_XMIT

EQU

EQU O:1 Equal Source A N11:0 140< Source B 10 10<

1746-HSCE2

HSCE2_ACK

I:1

1746-HSCE2

Copy File Source #N10:10 Dest #O:1.0 Length 8

When the previous block is completed (transmit and acknowledge bit are reset), copy Min/Max Count Value Block for counter 1 to the HSCE2 and set transmit bit (O:e.0/15).

DATA_BLOCK_PTR HSCE2_XMIT

EQU

EQU O:1 Equal Source A N11:0 140< Source B 20 20<

1746-HSCE2

HSCE2_ACK

I:1

1746-HSCE2

Copy File Source #N10:20 Dest #O:1.0 Length 8

When the previous block is completed (transmit and acknowledge bit are reset), copy Min/Max Count Value Block for counter 2 to the HSCE2 and set transmit bit (O:e.0/15).

DATA_BLOCK_PTR HSCE2_XMIT

EQU

EQU O:1 Equal Source A N11:0 140< Source B 30 30<

1746-HSCE2

HSCE2_ACK

I:1

1746-HSCE2

Copy File Source #N10:30 Dest #O:1.0 Length 8

COP

HSCE2_XMIT

O:1

1746-HSCE2

HSCE2_XMIT

O:1

1746-HSCE2

HSCE2_XMIT

O:1

1746-HSCE2

HSCE2_XMIT

O:1

1746-HSCE2

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6-4 Application Examples

When the previous block is completed (transmit and acknowledge bit are reset), copy Min/Max Count Value Block for counter 3 to the HSCE2 and set transmit bit (O:e.0/15).

Ladder File 9 Continued

0004

0005

0006

0007

DATA_BLOCK_PTR HSCE2_XMIT

EQU

EQU O:1 Equal Source A N11:0 140< Source B 40 40<

1746-HSCE2

HSCE2_ACK

I:1

1746-HSCE2

When the previous block is completed (transmit and acknowledge bit are reset), copy Programming Range Block 1 for counter 1 to the HSCE2 and set transmit bit (O:e.0/15).

DATA_BLOCK_PTR HSCE2_XMIT

EQU

EQU O:1 Equal Source A N11:0 140< Source B 50 50<

1746-HSCE2

HSCE2_ACK

I:1

1746-HSCE2

When the previous block is completed (transmit and acknowledge bit are reset), copy Programming Ranges Block 2 for counter 1 to the HSCE2 and set transmit bit (O:e.0/15).

DATA_BLOCK_PTR HSCE2_XMIT

EQU

EQU O:1 Equal Source A N11:0 140< Source B 60 60<

1746-HSCE2

HSCE2_ACK

I:1

1746-HSCE2

When the previous block is completed (transmit and acknowledge bit are reset), copy Programming Ranges Block 3 for counter 1 to the HSCE2 and set transmit bit (O:e.0/15).

DATA_BLOCK_PTR HSCE2_XMIT

EQU

EQU O:1 Equal Source A N11:0 140< Source B 70 70<

1746-HSCE2

HSCE2_ACK

I:1

1746-HSCE2

COP

COP Copy File Source #N10:40 Dest #O:1.0 Length 8

HSCE2_XMIT

O:1

1746-HSCE2

COP

COP Copy File Source #N10:50 Dest #O:1.0 Length 8

HSCE2_XMIT

O:1

1746-HSCE2

COP

COP Copy File Source #N10:60 Dest #O:1.0 Length 8

HSCE2_XMIT

O:1

1746-HSCE2

COP

COP Copy File Source #N10:70 Dest #O:1.0 Length 8

HSCE2_XMIT

O:1

1746-HSCE2

Publication 1746-UM002B-EN-P - August 2004

0008

0009

0010

0011

Ladder File 9 Continued

When the previous block is completed (transmit and acknowledge bit are reset), copy Programming Ranges Block 4 for counter 1 to the HSCE2 and set transmit bit (O:e.0/15).

DATA_BLOCK_PTR HSCE2_XMIT

EQU

EQU O:1 Equal Source A N11:0 140< Source B 80 80<

1746-HSCE2

When the previous block is completed (transmit and acknowledge bit are reset), copy Programming Ranges Block 5 for counter 1 to the HSCE2 and set transmit bit (O:e.0/15).

DATA_BLOCK_PTR HSCE2_XMIT

EQU

EQU O:1 Equal Source A N11:0 140< Source B 90 90<

1746-HSCE2

When the previous block is completed (transmit and acknowledge bit are reset), copy Programming Ranges Block 6 for counter 1 to the HSCE2 and set transmit bit (O:e.0/15).

DATA_BLOCK_PTR HSCE2_XMIT

EQU

EQU O:1 Equal Source A N11:0 140< Source B 100 100<

1746-HSCE2

When the previous block is completed (transmit and acknowledge bit are reset), copy Programming Ranges Block 7 for counter 1 to the HSCE2 and set transmit bit (O:e.0/15).

DATA_BLOCK_PTR HSCE2_XMIT

EQU

EQU O:1 Equal Source A N11:0 140< Source B 110 110<

1746-HSCE2

HSCE2_ACK

I:1

1746-HSCE2

HSCE2_ACK

I:1

1746-HSCE2

HSCE2_ACK

I:1

1746-HSCE2

HSCE2_ACK

I:1

1746-HSCE2

Application Examples 6-5

COP

COP Copy File Source #N10:80 Dest #O:1.0 Length 8

HSCE2_XMIT

O:1

1746-HSCE2

COP

COP Copy File Source #N10:90 Dest #O:1.0 Length 8

HSCE2_XMIT

O:1

1746-HSCE2

COP

COP Copy File Source #N10:100 Dest #O:1.0 Length 8

HSCE2_XMIT

O:1

1746-HSCE2

COP

COP Copy File Source #N10:110 Dest #O:1.0 Length 8

HSCE2_XMIT

O:1

1746-HSCE2

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6-6 Application Examples

When the previous block is completed (transmit and acknowledge bit are reset), copy Programming Ranges Block 8 for counter 1 to the HSCE2 and set transmit bit (O:e.0/15).

0012

When the previous block is completed (transmit and acknowledge bit are reset), copy Counter Configuration Block to the HSCE2 and set transmit bit (O:e.0/15).

0013

When HSCE2 sets its acknowledge bit (I:e.0/15), reset transmit bit (O:e.0/15), and check HSCE2 programming error bit (I:e.0/13). If the error bit is clear, increment the block counter to permit the next block move to start.

0014

Ladder File 9 Continued

DATA_BLOCK_PTR HSCE2_XMIT

EQU

EQU O:1 Equal Source A N11:0 140< Source B 120 120<

DATA_BLOCK_PTR

EQU

EQU O:1 Equal Source A N11:0 140< Source B 130 130<

HSCE2_XMIT

O:1

1746-HSCE2 1746-HSCE2

HSCE2_ACK

I:1

1746-HSCE2

HSCE2_XMIT

1746-HSCE2

HSCE2_ACK

I:1

1746-HSCE2

HSCE2_ACK

I:1

1746-HSCE2

MEQ

MEQ ADD Masked Equal Source I:1.0 776< Mask 6000h 8192< Compare 0 0<

COP

COP Copy File Source #N10:120 Dest #O:1.0 Length 8

HSCE2_XMIT

O:1

1746-HSCE2

COP

COP Copy File Source #N10:130 Dest #O:1.0 Length 8

HSCE2_XMIT

O:1

1746-HSCE2

HSCE2_XMIT

O:1

DATA_BLOCK_PTR

ADD Add Source A N11:0 140< Source B 10 10< Dest N11:0 140<

1746-HSCE2

Note: The Counter Control Block does not require a 0-1 positive transition of the transmit bit (O:3.0/15) to operate.

DATA_BLOCK_PTR HSCE2_XMIT

EQU

EQU O:1

0015

Equal Source A N11:0 140< Source B N11:1 140<

If the PERR bit or HSCE2 fault bit is set, set the HSCE2 error bit (B3/1).

HSCE2_ACK

0016

0017

I:1

1746-HSCE2

HSCE2_FAULT

I:1

1746-HSCE2

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HSCE2_PERR

I:1

1746-HSCE2

HSCE2_ACK

I:1

1746-HSCE2

COP

COP Copy File Source #N10:140 Dest #O:1.0 Length 8

HSCE2_INIT_DONE

B3:0

L 0

HSCE2_ERROR

B3:0

L 1

END

Application Examples 6-7

Data Table for N10 File (hexidecimal)

Programming Blocks Offset 0123456789

Module Setup N10:0 1 103 8 0 000000 Counter Configuration N10:10 F02 6 0 6 000000 Min/Max Count Value Counter 1 N10:20 400019000000 Min/Max Count Value Counter 2 N10:30 104 0 0 0 1F4 00000 Min/Max Count Value Counter 3 N10:40 204 0 0 0 258 00000 Min/Max Count Value Counter 4 N10:50 304 0 0 0 2BC 00000 Program Ranges N10:60 10 1 0 0 0 31 1 0 0 0 Program Ranges N10:70 10 2 0 32 0 63 2 0 0 0 Program Ranges N10:80 10 4 0 64 0 95 4 0 0 0 Program Ranges N10:90 10 8 0 96 0 C7 8 0 0 0 Program Ranges N10:100 10 10 0 C8 0 F9 1 0 0 0 Program Ranges N10:110 10 20 0 FA 0 12B 2 0 0 0 Program Ranges N10:120 10 40 0 12C 0 15D 4 0 0 0 Program Ranges N10:130 10 80 0 15E 0 190 8 0 0 0 Counter Control N10:140 80 8001 8001 8001 8001 FF00 FF 0 0 0

N10:15000000000

Example 2 - Indirect Addressing

Data Table for N11 File (decimal)

Offset 0123456789

N11:0 140 140 14

In this example, the module is set up in Class 4, mode 1 using only two counters. This example uses indirect addressing, which is compatible only with SLC 5/03 or higher processors.

TIP

This example may be used with any mode (1, 2, or

3) and with any SLC 5/03 or higher processor, as long as the module is in a local chassis. However, the N10 and N11 data files would need to be modified for a different configuration.

Publication 1746-UM002B-EN-P - August 2004

6-8 Application Examples

Ladder File 8 - HSCE2

The first pass of the program initializes the following values:

1. The HSCE2 initialization done bit (B3/0) is unlatched.

2. The HSCE2 error bit (B3/1) is cleared.

0000

FIRST_PASS

S:1

HSCE2_INIT_DONE

B3:0

U 0

HSCE2_ERROR

B3:0

#HSCE2_CFG_BLK

FLL Fill File Source 0

Dest Length 8

DATA_BLK_PTR

MOV

MOV Move Source 0 0< Dest N11:0

MUL

MUL Multiply Source A 10 10< Source B N11:2 17< Dest N11:1

#O:1.0

170<

If the HSCE2 initialization is not done, and the HSCE2 has not errored, call the HSCE2 initialization routine.

FIRST_PASS

S:1

0001

0002

HSCE2_INIT_DONE

Publication 1746-UM002B-EN-P - August 2004

B3:0

HSCE2_ERROR

B3:0

JSR

JSR Jump To Subroutine SBR File Number U:9

END

Rockwell Automation 1746-HSCE2 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Important User Information

Table of Contents

Summary of Changes

New Information

Preface

Who Should Use This Manual

Purpose of This Manual

Conventions Used In This Manual

Your Questions or Comments on the Manual

Multi-Channel High-Speed Counter Module Overview

Operating Class

Hardware Features

Operating Modes

Input Configurations

Input Frequency

Gate/Preset Modes

Summary of Available Counter Configurations

Counter Types

Rate Value

Output Control

Range Control

Counter Input Data

Compliance to European Union Directives

Prevent Electrostatic Discharge

Setting the Jumpers

Installing the Module

Important Wiring Considerations

Electronic Protection

Input and Output Connections

Encoder Wiring

Selecting Operating Class

Power-up Reset

Module Programming

Module Setup Block

Minimum/Maximum Count Value Block

Minimum/Maximum Rate Value Block

Program Ranges Block

Counter Control Block

Start Up

Normal Operation

Troubleshooting

Debug Mode Operation

Example 2 - Indirect Addressing