NEC 2SK3354-Z, 2SK3354-S, 2SK3354 Datasheet

DATA SHEET

MOS FIELD EFFECT TRANSISTOR

2SK3354

SWITCHING

N-CHANNEL POWER MOS FET

INDUSTRIAL USE

DESCRIPTION

The 2SK3354 is N-channel MOS Field Effect Transistor designed for high current switching applications.

FEATURES

∙Super low on-state resistance:

RDS(on)1 = 8.0 mΩ MAX. (VGS = 10 V, ID = 42 A)

RDS(on)2 = 12 mΩ MAX. (VGS = 4 V, ID = 42 A)

∙ Low Ciss: Ciss = 6300 pF TYP.

∙Built-in gate protection diode

ABSOLUTE MAXIMUM RATINGS (TA = 25°C)

ORDERING INFORMATION

PART NUMBER	PACKAGE
2SK3354	TO-220AB
2SK3354-S	TO-262
2SK3354-Z	TO-220SMD

	Drain to Source Voltage	VDSS	60	V
	Gate to Source Voltage	VGSS(AC)	±20	V
	Drain Current (DC)	ID(DC)	±83	A
	Drain Current (pulse) Note1	ID(pulse)	±332	A
	Total Power Dissipation (TC = 25°C)	P T	100	W
	Total Power Dissipation (TA = 25°C)	P T	1.5	W
	Channel Temperature	Tch	150	°C
	Storage Temperature	Tstg	–55 to +150	°C
	Single Avalanche Current Note2	IAS	55	A
	Single Avalanche Energy Note2	EAS	302	mJ

Notes 1. PW ≤ 10 μs, Duty cycle ≤ 1 %

2. Starting Tch = 25 °C, R G = 25 Ω, VGS = 20 V → 0 V

THERMAL RESISTANCE

Channel to Case	Rth(ch-C)	1.25	°C/W
Channel to Ambient	Rth(ch-A)	83.3	°C/W

The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.

Document No. D14131EJ1V0DS00 (1st edition) Date Published June 1999 NS CP(K)

Printed in Japan

The mark shows major revised points.	1999
©

2SK3354

ELECTRICAL CHARACTERISTICS (TA = 25 °C)

CHARACTERISTICS

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

Drain to Source On-state Resistance

RDS(on)1

VGS = 10 V, ID = 42 A

6.3

8.0

mΩ

RDS(on)2

VGS = 4 V, ID = 42 A

8.0

12

mΩ

Gate to Source Cut-off Voltage

VGS(off)

VDS = 10 V, ID = 1 mA

1.5

2.0

2.5

V

Forward Transfer Admittance

| yfs |

VDS = 10 V, ID = 42 A

35

59

S

Drain Leakage Current

IDSS

VDS = 60 V, VGS = 0 V

10

μA

Gate to Source Leakage Current

IGSS

VGS = ±20 V, VDS = 0V

±10

μA

Input Capacitance

Ciss

VDS = 10 V, VGS = 0 V, f = 1 MHz

6300

pF

Output Capacitance

Coss

1000

pF

Reverse Transfer Capacitance

Crss

490

pF

Turn-on Delay Time

td(on)

ID = 42 A, VGS(on) = 10 V, VDD = 30 V,

100

ns

RG = 10 Ω

Rise Time

tr

1500

ns

Turn-off Delay Time

td(off)

300

ns

Fall Time

tf

440

ns

Total Gate Charge

QG

ID = 83 A , VDD = 48 V, VGS = 10 V

106

nC

Gate to Source Charge

QGS

20

nC

Gate to Drain Charge

QGD

30

nC

Body Diode Forward Voltage

VF(S-D)

IF = 83 A, VGS = 0 V

1.0

V

Reverse Recovery Time

trr

IF = 83 A, VGS = 0 V,

55

ns

di/dt = 100 A/μs

Reverse Recovery Charge

Qrr

100

nC

TEST CIRCUIT 1 AVALANCHE CAPABILITY

TEST CIRCUIT 2 SWITCHING TIME

D.U.T.

D.U.T.

L

VGS

RG = 25 Ω

RL

VGS

90 %

10 %

VGS(on)

Wave Form

PG.

50 Ω

PG.

RG

0

VGS = 20 → 0 V

VDD

RG

= 10 Ω

VDD

VGS

ID

90 %

ID

90 %

BVDSS

0

ID

0 10 %

10 %

IAS

VDS

τ

Wave Form

VDD

ID

td(on)

tr td(off)

tf

τ = 1 μs

ton

toff

Starting Tch

Duty Cycle ≤ 1 %

TEST CIRCUIT 3 GATE CHARGE

D.U.T.

PG.

IG = 2 mA

RL

50

Ω

VDD

2	Data Sheet D14131EJ1V0DS00