Motorola MC100LVEL51DR2, MC100LVEL51, MC100LVEL51D Datasheet


SEMICONDUCTOR TECHNICAL DATA
4–1
REV 1
Motorola, Inc. 1996
8/96
 
The reset input is an asynchronous, level triggered signal. Data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the LVEL51 allow the device to be used as a negative edge triggered flip-flop.
input will be biased at VCC/2.
475ps Propagation Delay
2.8GHz Toggle Frequency
Operates from –3.3V (or 3.3V) Supply
75kInternal Input Pulldown Resistors
>2000V ESD Protection
1
2
3
4 5
6
78Q
V
EE
V
CC
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
D
QCLK
CLK
R
D
R
Flip-Flop

TRUTH TABLE
D
L
H
X
R
L
L
H
CLK
Z
Z
X
Q
L
H
L
Z = LOW to HIGH Transition
1
8
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05
MC100LVEL51
MOTOROLA ECLinPS and ECLinPS Lite
DL140 — Rev 3
4–2
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = GND)
–40°C 0°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit
I
EE
Power Supply Current 30 35 30 35 30 35 32 37 mA
V
EE
Power Supply Voltage –3.0 –3.3 –3.8 –3.0 –3.3 –3.8 –3.0 –3.3 –3.8 –3.0 –3.3 –3.8 V
I
IH
Input HIGH Current 150 150 150 150 µA
I
IL
Input LOW Current CLK
Other
–600
0.5
–600
0.5
–600
0.5
–600
0.5
µA
AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = GND)
–40°C 0°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit
f
MAX
Maximum Toggle Frequency
2.7 2.9 2.9 2.9 GHz
t
PLH
t
PHL
Propagation Delay to Output CLK
R
330 340
510 540
330 340
510 540
340 350
520 550
370 390
550 590
ps
t
S
Setup Time 150 0 150 0 150 0 150 0 ps
t
H
Hold Time 200 100 200 100 200 100 200 100 ps
t
RR
Reset Recovery 350 200 350 200 350 200 350 200 ps
t
PW
Minimum Pulse CLK Width Reset
400 500
400 500
400 500
400 500
ps
V
PP
Minimum Input Swing
1
150 150 150 150 mV
V
CMR
Common Mode Range
2
VPP < 500mV VPP 500mV
–2.0 –1.8
–0.4 –0.4
–2.1 –1.9
–0.4 –0.4
–2.1 –1.9
–0.4 –0.4
–2.1 –1.9
–0.4 –0.4
V
t
r
t
f
Output Rise/Fall Times Q (20% – 80%)
120 320 120 320 120 320 120 320 ps
1. Minimum input swing for which AC parameters are guaranteed.
2. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within
the specified range and the peak-to-peak voltage lies between VPPmin and 1V. The lower end of the CMR range varies 1:1 with VEE. The numbers in the spec table assume a nominal VEE = –3.3V. Note for PECL operation, the V
CMR
(min) will be fixed at 3.3V – |V
CMR
(min)|.
MC100LVEL51
4–3 MOTOROLAECLinPS and ECLinPS Lite
DL140 — Rev 3
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751–05
ISSUE P
SEATING PLANE
1
4
58
C
K
4X P
A0.25 (0.010)MT B
S S
0.25 (0.010)
M
B
M
8X D
R
M
J
X 45
_
_
F
–A–
–B–
–T–
DIM MIN MAX
MILLIMETERS
A 4.80 5.00 B 3.80 4.00 C 1.35 1.75 D 0.35 0.49
F 0.40 1.25 G 1.27 BSC J 0.18 0.25 K 0.10 0.25 M 0 7 P 5.80 6.20 R 0.25 0.50
__
G
NOTES:
1. DIMENSIONS A AND B ARE DATUMS AND T IS A DATUM SURFACE.
2. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
3. DIMENSIONS ARE IN MILLIMETER.
4. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION.
5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
6. DIMENSION D DOES NOT INCLUDE MOLD PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
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MC100LVEL51/D
*MC100LVEL51/D*
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