Motorola MC100LVEL51DR2, MC100LVEL51, MC100LVEL51D Datasheet
SEMICONDUCTOR TECHNICAL DATA
4–1
REV 1
Motorola, Inc. 1996
8/96
The MC100LVEL51 is a differential clock D flip-flop with reset. The
device is functionally equivalent to the EL51 device, but operates from a
low voltage supply. With propagation delays and output transition times
essentially equal to the EL51, the LVEL51 is ideally suited for those
applications which require the ultimate in AC performance at 3.3V VCC.
The reset input is an asynchronous, level triggered signal. Data enters
the master portion of the flip-flop when the clock is LOW and is
transferred to the slave, and thus the outputs, upon a positive transition of
the clock. The differential clock inputs of the LVEL51 allow the device to
be used as a negative edge triggered flip-flop.
The differential input employs clamp circuitry to maintain stability under
open input conditions. When left open, the CLK input will be pulled down
to VEE and the CLK
input will be biased at VCC/2.
• 475ps Propagation Delay
• 2.8GHz Toggle Frequency
• Operates from –3.3V (or 3.3V) Supply
• 75kΩ Internal Input Pulldown Resistors
• >2000V ESD Protection
1
2
3
4 5
6
78Q
V
EE
V
CC
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
D
QCLK
CLK
R
D
R
Flip-Flop
TRUTH TABLE
D
L
H
X
R
L
L
H
CLK
Z
Z
X
Q
L
H
L
Z = LOW to HIGH Transition
1
8
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05
MC100LVEL51
MOTOROLA ECLinPS and ECLinPS Lite
DL140 — Rev 3
4–2
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = GND)
–40°C 0°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit
I
EE
Power Supply Current 30 35 30 35 30 35 32 37 mA
V
EE
Power Supply Voltage –3.0 –3.3 –3.8 –3.0 –3.3 –3.8 –3.0 –3.3 –3.8 –3.0 –3.3 –3.8 V
I
IH
Input HIGH Current 150 150 150 150 µA
I
IL
Input LOW Current CLK
Other
–600
0.5
–600
0.5
–600
0.5
–600
0.5
µA
AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = GND)
–40°C 0°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit
f
MAX
Maximum Toggle
Frequency
2.7 2.9 2.9 2.9 GHz
t
PLH
t
PHL
Propagation Delay
to Output CLK
R
330
340
510
540
330
340
510
540
340
350
520
550
370
390
550
590
ps
t
S
Setup Time 150 0 150 0 150 0 150 0 ps
t
H
Hold Time 200 100 200 100 200 100 200 100 ps
t
RR
Reset Recovery 350 200 350 200 350 200 350 200 ps
t
PW
Minimum Pulse CLK
Width Reset
400
500
400
500
400
500
400
500
ps
V
PP
Minimum Input Swing
1
150 150 150 150 mV
V
CMR
Common Mode Range
2
VPP < 500mV
VPP ≥ 500mV
–2.0
–1.8
–0.4
–0.4
–2.1
–1.9
–0.4
–0.4
–2.1
–1.9
–0.4
–0.4
–2.1
–1.9
–0.4
–0.4
V
t
r
t
f
Output Rise/Fall Times Q
(20% – 80%)
120 320 120 320 120 320 120 320 ps
1. Minimum input swing for which AC parameters are guaranteed.
2. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within
the specified range and the peak-to-peak voltage lies between VPPmin and 1V. The lower end of the CMR range varies 1:1 with VEE. The
numbers in the spec table assume a nominal VEE = –3.3V. Note for PECL operation, the V
CMR
(min) will be fixed at 3.3V – |V
CMR
(min)|.
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