LG GM72V66841CT-8, GM72V66841CT-7K, GM72V66841CT-7J, GM72V66841CT-10K, GM72V66841CLT-8 Datasheet

LG Semicon Co.,Ltd.

REVISION HISTORY

/ Revision 1.0: July 1998

-Add PC100,7K(2-2-2) Specifications.

-Update Icc Specifications.

-Change Input Test Condition from 2.8/0.0V to 2.4/0.4V.

-Added post SPD Information separately(7K/7J/10K) for Modules.

-Add Minimum Capacitance Value for Component.

Rev. 1.0

LG Semicon Co.,Ltd.

GM72V66841CT/CLT

2,097,152 WORD x 8 BIT x 4 BANK SYNCHRONOUS DYNAMIC RAM

Description

Pin Configuration

The GM72V66841CT/CLT is a synchronous

VCC

VSS

dynamic random access memory comprised of

1

54

67,108,864

memory cells and logic including

DQ0

2

53

DQ7

input and output circuits operating synchronously

VCCQ

3

52

VSSQ

NC

NC

by referring to the positive edge of the externally

4

51

DQ1

DQ6

5

50

provided Clock.

VSSQ

VCCQ

6

49

NC

NC

The

GM72V66841CT/CLT provides four

7

48

DQ2

DQ5

banks of 2,097,152 word by 8 bit to realize high

8

47

VCCQ

VSSQ

9

46

bandwidth with the Clock frequency up to 125

NC

NC

10

45

Mhz.

DQ3

DQ4

11

44

VSSQ

VCCQ

12

JEDEC STANDARD

43

NC

NC

13

400 mil 54 PIN TSOP II

42

VCC

VSS

Features

14

41

NC

NC

15

(TOP VIEW)

40

* PC100,PC66 Compatible

/WE

16

39

DQM

/CAS

17

38

CLK

7K(2-2-2), 7J(3-2-2), 10K(PC66)

/RAS

18

37

CKE

/CS

NC

19

36

* 3.3V single Power supply

BA0/A13

20

35

A11

* LVTTL interface

BA1/A12

21

34

A9

A10,AP

22

33

A8

* Max Clock frequency

A0

23

32

A7

100/125 MHz

A1

24

31

A6

A2

25

30

A5

* 4,096 refresh cycle per 64 ms

A3

26

29

A4

* Two kinds of refresh operation

VCC

27

28

VSS

Auto refresh/ Self refresh

Pin Name

* Programmable burst access capability ;

CLK

Clock

- Sequence:Sequential / Interleave

CKE

Clock Enable

- Length

:1/2/4/8/FP

CS

Chip Select

* Programmable

latency : 2/3

CAS

RAS

Row Address Strobe

* 4 Banks can operate independently or

CAS

Column Address Strobe

simultaneously

WE

Write Enable

* Burst read/burst write or burst read/single

A0~A9,A11

Address input

A10 / AP

Address input or Auto Precharge

write operation capability

BA0/A13

Bank select

* Input and output masking by DQM input

~BA1/A12

* One Clock of back to back read or write

DQ0~DQ7

Data input / Data output

command interval

DQM

Data input / output Mask

* Synchronous Power down and Clock

VCCQ

VCC for DQ

VSSQ

VSS for DQ

suspend capability with one Clock latency

VCC

Power for internal circuit

for both entry and exit

VSS

Ground for internal circuit

*JEDEC Standard 54Pin 400mil TSOP II

NC

No Connection

Package

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LG Semicon

GM72V66841CT/CLT

Block Diagram

A0 to A13

A0 to A8

A0 to A13

Column address

Column address

Row address

Refresh

counter

buffer

counter

counter

Row decoder

Row decoder

Row decoder

Row decoder

bus

Memory array

bus

Memory array

bus

Memory array

bus

Memory array

Column decoder

Sense amplifier & I/O

Column decoder

Sense amplifier & I/O

Column decoder

Sense amplifier & I/O

Column decoder

Sense amplifier & I/O

Bank 0

Bank 1

Bank 2

Bank 3

4096 row

4096 row

4096 row

4096 row

x 512 column

x 512 column

x 512 column

x 512 column

x 8 bit

x 8 bit

x 8 bit

x 8 bit

Input

Output

Control logic &

buffer

buffer

timing generator

DQ0 to DQ7

CLK

CKE

CS

RAS

CAS

WE

DQM

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LG Semicon

GM72V66841CT/CLT

Pin Description

Pin Name

DESCRIPTION

CLK

CLK is the master Clock input to this pin. The other input signals are referred

(input pin)

at CLK rising edge.

CKE

This pin determines whether or not the next CLK is valid. If CKE is High, the

next CLK rising edge is valid. If CKE is Low, the next CLK rising edge is

(input pin)

invalid. This pin is used for Power-down and Clock suspend modes.

When

is Low, the command input cycle becomes valid. When

is high,

CS

CS

CS

all inputs are ignored. However, internal operations (bank active, burst

(input pin)

operations, etc.) are held.

Although these pin names are the same as those of conventional DRAMs,

RAS,

CAS,

and

WE

they function in a different way. These pins define operation commands (read,

(input pins)

write, etc.) depending on the combination of their voltage levels. For details,

refer to the command operation section.

Row address (AX0 to AX11) is determined by A0 to A11 level at the bank

active command cycle CLK rising edge. Column address(AY0 to AY8;

GM72V66841CT/CLT) is determined by A0 to A8 level at the read or write

A0 ~ A11

command cycle CLK rising edge. And this column address becomes burst

(input pins)

access start address. A10 defines the Precharge mode. When A10 = High at

the Precharge command cycle, all banks are Precharged. But when A10 =

Low at the Precharge command cycle, only the bank that is selected by

A12/A13 (BS) is Precharged.

A12/A13 are bank select signal (BS). The memory array of the

A12/A13

GM72V66841CT/CLT is divided into bank 0, bank 1, bank2 and bank 3.

GM72V66841CT/CLT contain 4096-row x 512-column x 8-bits. If A12 is

(input pin)

Low and if A13 is Low, bank 0 is selected. If A12 is High and A13 is Low,

bank 1 is selected. If A12 is Low and A13 is High, bank 2 is selected. If A12

is High and A13 is High, bank 3 is selected.

DQM, DQMU/DQML controls input/output buffers.

* Read operation: If DQM, DQMU/DQML is High, The output buffer

DQM,

becomes High-Z. If the DQM, DQMU/DQML is Low, the output buffer

becomes Low-Z.

DQMU/DQML

* Write operation: If DQM, DQMU/DQML is High, the previous data is held

(input pins)

(the new data is not written). If DQM, DQMU/DQML is Low, the data is

written.

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	Pin Description(Continued)
	Pin Name	DESCRIPTION
	DQ0 ~ DQ7	Data is input and output from these pins. These pins are the same as those of a
	(I/O pins)	conventional DRAM.
	VCC and VCCQ	3.3 V is applied. (VCC is for the internal circuit and VCCQ is for the output
	(Power supply pins)	buffer.)
	VSS and VSSQ	Ground is connected. (VSS is for the internal circuit and VSSQ is for the output
	(Power supply pins)	buffer.)
	NC	No Connection pins.

Command Operation Command Truth Table

The synchronous DRAM recognizes the following commands specified by the CS, RAS, CAS, WE and address pins.

CKE

A12~

A0~

Function

Symbol

CS

RAS

CAS

WE

A10

n-1

n

A13

A11

Ignore command

DESL

H

X

H

X

X

X

X

X

X

No Operation

NOP

H

X

L

H

H

H

X

X

X

Burst stop in full page

BST

H

X

L

H

H

L

X

X

X

Column address and

READ

H

X

L

H

L

H

V

L

V

read command

Read with auto-Precharge

READ A

H

X

L

H

L

H

V

H

V

Column address and

WRIT

H

X

L

H

L

L

V

L

V

write command

Write with auto-Precharge

WRIT A

H

X

L

H

L

L

V

H

V

Row address strobe and

ACTV

H

X

L

L

H

H

V

V

V

bank active

Precharge select bank

PRE

H

X

L

L

H

L

V

L

X

Precharge all banks

PALL

H

X

L

L

H

L

X

H

X

Refresh

REF/SELF

H

V

L

L

L

H

X

X

X

Mode register set

MRS

H

X

L

L

L

L

V

V

V

* Notes : H: VIH, L: VIL, X: VIH or VIL, V: Valid address input

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GM72V66841CT/CLT

Ignore command [DESL]: When this command is set (CS is High), the synchronous DRAM ignores command input at the Clock. However, the internal status is held.

No operation [NOP]: This command is not an execution command. However, the internal operations continue.

Burst stop in full page [BST] : This command stops a full-page burst operation (burst length = full-page(512;GM72V66841CT/CLT) and is illegal otherwise. Full page burst continues until this command is input. When data input/output is completed for full-page of data, it automatically returns to the start address, and input/output is performed repeatedly.

Column address strobe and read command [READ]: This command starts a read operation. In addition, the start address of burst read is determined by the column address

AY0 to AY8; GM72V66841CT/CLT) and the bank select address (A12/A13). After the read operation, the output buffer becomes High-Z.

Read with auto-Precharge [READ A]: This command automatically performs a Precharge operation after a burst read with a burst length of 1, 2, 4 or 8. When the burst length is full-page, this command is illegal.

Column address strobe and write command [WRIT]: This command starts a write operation. When the burst write mode is selected, the column address (AY0 to AY8; GM72V66841CT/CLT) and the bank select address (A12/A13) become the burst write start address. When the single write mode is selected, data is only written to the location specified by the column address (AY0 to AY8;GM72V66841CT/CLT) and the bank select address (A12/A13).

Write with auto-Precharge [WRIT A]: This command automatically performs a Precharge operation after a burst write with a length of 1, 2, 4 or 8, or after a single write operation. When the burst length is full-page, this command is illegal.

Row address strobe and bank activate [ACTV]: This command activates the bank that is selected by A12/A13(BS) and determines the row address (AX0 to AX11). If A12 is Low and if A13 is Low, bank 0 is activated. If A12 is High and A13 is Low, bank 1 is activated. If A12 is Low and A13 is High, bank 2 is activated. If A12 is High and A13 is High, bank 3 is activated.

Precharge selected bank [PRE]: This command starts Precharge operation for the bank selected by A12/A13. If A12 is Low and if A13 is Low, bank 0 is selected. If A12 is High and A13 is Low, bank 1 is selected. If A12 is Low and A13 is High, bank 2 is selected. If A12 is High and A13 is High, bank 3 is selected.

Precharge all banks [PALL]: This command starts a Precharge operation for all banks.

Refresh [REF/SELF]: This command starts the refresh operation. There are two types of refresh operation, the one is auto-refresh, and the other is self-refresh. For details, refer to the CKE truth table section.

Mode register set [MRS]: Synchronous DRAM has a mode register that defines how it operates. The mode register is specified by the address pins (A0 to A11) at the mode register set cycle. For details, refer to the mode register configuration. After Power on, the contents of the mode register are undefined, execute the mode register set command to set up the mode register.

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LG Semicon GM72V66841CT/CLT

DQM Truth Table

Function	Symbol		CKE		DQM
			n-1	n
Write enable/output enable	ENB		H	X	L
Write inhibit/output disable	MASK		H	X	H

* Notes : H: VIH, L: VIL, X: VIH or VIL. Write : lDID is needed.

Read : lDOD is needed.

The GM72V66841CT/CLT can mask input/output data by means of DQM.

During reading, the output buffer is set to Low-Z by setting DQM to Low, enabling data output. On the other hand, when DQM is set to High, the output buffer becomes High-Z, disabling data output.

During writing, data is written by setting DQM to Low. When DQM is set to High, the previous data is held (the new data is not written). Desired data can be masked during burst read or burst write by setting DQM. For details, refer to the DQM control section of the GM72V66841CT/CLT operating instructions.

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GM72V66841CT/CLT

CKE Truth Table

Current

CKE

Address

Function

CS

RAS

CAS

WE

State

n -1

n

Active

Clock suspend

H

L

H

X

X

X

X

mode entry

Any

Clock suspend

L

L

X

X

X

X

X

Clock Suspend

Clock suspend

L

H

X

X

X

X

X

mode exit

Idle

Auto-refresh

(REF)

H

H

L

L

L

H

X

command

Idle

Self-refresh

(SELF)

H

L

L

L

L

H

X

entry

Idle

Power down

H

L

L

H

H

H

X

entry

H

L

H

X

X

X

X

Self refresh

Self refresh

(SELFX)

L

H

L

H

H

H

X

exit

L

H

H

X

X

X

X

Power down

Power down

L

H

L

H

H

H

X

Exit

L

H

H

X

X

X

X

* Notes :

H: VIH, L: VIL, X: VIH or VIL.

Clock suspend mode entry: The synchronous DRAM enters Clock suspend mode from active mode by setting CKE to Low. The Clock suspend mode changes depending on the current status (1 Clock before) as shown below.

ACTIVE Clock suspend: This suspend mode ignores inputs after the next Clock by internally maintaining the bank active status.

READ suspend and READ A suspend: The data being output is held (and continues to be output).

WRITE suspend and WRIT A suspend: In this mode, external signals are not accepted. However, the internal state is held.

Clock suspend: During Clock suspend mode, keep the CKE to Low.

Clock suspend mode exit : The synchronous DRAM exits from Clock suspend mode by setting CKE to High during the Clock suspend state.

IDLE: In this state, all banks are not selected, and completed Precharge operation.

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GM72V66841CT/CLT

Auto-refresh command[REF]: When this command is input from the IDLE state, the synchronous DRAM starts auto-refresh operation. (The auto-refresh is the same as the CBR refresh of conventional DRAMs.) During the auto-refresh operation, refresh address and bank select address are generated inside the synchronous DRAM. For every auto-refresh cycle, the internal address counter is updated. Accordingly, 4,096 times are required to refresh the entire memory. Before executing the autorefresh command, all the banks must be in the IDLE state. In addition, since the Precharge for all banks is automatically performed after autorefresh, no Precharge command is required after auto-refresh.

Self-refresh entry[SELF]: When this command is input during the IDLE state, the synchronous DRAM starts self-refresh operation. After the execution of this command, self-refresh continues while CKE is Low. Since self-refresh is performed internally and automatically, external refresh operations are unnecessary.

Self-refresh exit[SELFX]: When this command is executed during self-refresh mode, the synchronous DRAM can exit from self-refresh mode. After exiting from self-refresh mode, the synchronous DRAM enters the IDLE state.

Power down mode entry: When this command is executed during the IDLE state, the synchronous DRAM enters Power down mode. In Power down mode, Power consumption is suppressed by cutting off the initial input circuit.

Power down exit: When this command is executed at the Power down mode, the synchronous DRAM can exit from Power down mode. After exiting from Power down mode, the synchronous DRAM enters the IDLE state.

Function Truth Table

The following table shows the operations that are performed when each command is issued in each mode of the synchronous DRAM.

Current

CS

RAS

CAS

WE

Address

Command

Operation

state

Precharge

H

X

X

X

X

DESL

Enter IDLE after tRP

L

H

H

H

X

NOP

Enter IDLE after tRP

L

H

H

L

X

BST

NOP

L

H

L

H

BA, CA, A10

READ/READ A

ILLEGAL

L

H

L

L

BA, CA, A10

WRIT/WRIT A

ILLEGAL

L

L

H

H

BA, RA

ACTV

ILLEGAL

L

L

H

L

BA, A10

PRE, PALL

NOP

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LG Semicon GM72V66841CT/CLT

Function Truth Table (Continued)

Current

CS

RAS

CAS

WE

Address

Command

Operation

state

Precharge

L

L

L

H

X

REF, SELF

ILLEGAL

L

L

L

L

MODE

MRS

ILLEGAL

Idle

H

X

X

X

X

DESL

NOP

L

H

H

H

X

NOP

NOP

L

H

H

L

X

BST

NOP

L

H

L

H

BA, CA, A10

READ/READ A

ILLEGAL

L

H

L

L

BA, CA, A10

WRIT/WRIT A

ILLEGAL

L

L

H

H

BA, RA

ACTV

Bank and row active

L

L

H

L

BA, A10

PRE, PALL

NOP

L

L

L

H

X

REF, SELF

Refresh

L

L

L

L

MODE

MRS

Mode register set

Row active

H

X

X

X

X

DESL

NOP

L

H

H

H

X

NOP

NOP

L

H

H

L

X

BST

NOP

L

H

L

H

BA, CA, A10

READ/READ A

Begin read

L

H

L

L

BA, CA, A10

WRIT/WRIT A

Begin write

L

L

H

H

BA, RA

ACTV

Other bank active

*3

ILLEGAL on same bank

L

L

H

L

BA, A10

PRE, PALL

Precharge

L

L

L

H

X

REF, SELF

ILLEGAL

L

L

L

L

MODE

MRS

ILLEGAL

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LG Semicon GM72V66841CT/CLT

Function Truth Table (Continued)

Current

CS

RAS

CAS

WE

Address

Command

Operation

state

Read

H

X

X

X

X

DESL

Continue burst to end

L

H

H

H

X

NOP

Continue burst to end

L

H

H

L

X

BST

Burst stop to full page

L

H

L

H

BA, CA, A10

READ/READ A

Continue burst read to

CAS

latency and New

read

L

H

L

L

BA, CA, A10

WRIT/WRIT A

Term burst read/start

write

L

L

H

H

BA, RA

ACTV

Other bank active

*3

ILLEGAL on same bank

L

L

H

L

BA, A10

PRE, PALL

Term burst read and

Precharge

L

L

L

H

X

REF, SELF

ILLEGAL

L

L

L

L

MODE

MRS

ILLEGAL

Read with

H

X

X

X

X

DESL

Continue burst to end

auto-

and Precharge

Precharge

L

H

H

H

X

NOP

Continue burst to end

and Precharge

L

H

H

L

X

BST

ILLEGAL

L

H

L

H

BA, CA, A10

READ/READ A

ILLEGAL

L

H

L

L

BA, CA, A10

WRIT/WRIT A

ILLEGAL

L

L

H

H

BA, RA

ACTV

Other bank active

*3

ILLEGAL on same bank

L

L

H

L

BA, A10

PRE, PALL

ILLEGAL

L

L

L

H

X

REF, SELF

ILLEGAL

L

L

L

L

MODE

MRS

ILLEGAL

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LG Semicon GM72V66841CT/CLT

Function Truth Table (Continued)

Current

CS

RAS

CAS

WE

Address

Command

Operation

state

Write

H

X

X

X

X

DESL

Continue burst to end

L

H

H

H

X

NOP

Continue burst to end

L

H

H

L

X

BST

Burst stop on full page

L

H

L

H

BA, CA, A10

READ/READ A

Term burst and New

read

L

H

L

L

BA, CA, A10

WRIT/WRIT A

Term burst and New

write

L

L

H

H

BA, RA

ACTV

Other bank active

*3

ILLEGAL on same bank

L

L

H

L

BA, A10

PRE, PALL

Term burst write and

*2

Precharge

L

L

L

H

X

REF, SELF

ILLEGAL

L

L

L

L

MODE

MRS

ILLEGAL

Write with

H

X

X

X

X

DESL

Continue burst to end

auto-

and Precharge

Precharge

L

H

H

H

X

NOP

Continue burst to end

and Precharge

L

H

H

L

X

BST

ILLEGAL

L

H

L

H

BA, CA, A10

READ/READ A

ILLEGAL

L

H

L

L

BA, CA, A10

WRIT/WRIT A

ILLEGAL

L

L

H

H

BA, RA

ACTV

Other bank active

*3

ILLEGAL on same bank

L

L

H

L

BA, A10

PRE, PALL

ILLEGAL

L

L

L

H

X

REF, SELF

ILLEGAL

L

L

L

L

MODE

MRS

ILLEGAL

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tRAS

LG Semicon

GM72V66841CT/CLT

Function Truth Table (Continued)

Current

CS

RAS

CAS

WE

Address

Command

Operation

state

Refresh

H

X

X

X

X

DESL

Enter IDLE after tRC

(auto-refresh)

L

H

H

H

X

NOP

Enter IDLE after tRC

L

H

H

L

X

BST

Enter IDLE after tRC

L

H

L

H

BA, CA, A10

READ/READ A

ILLEGAL

L

H

L

L

BA, CA, A10

WRIT/WRIT A

ILLEGAL

L

L

H

H

BA, RA

ACTV

ILLEGAL

L

L

H

L

BA, A10

PRE, PALL

ILLEGAL

L

L

L

H

X

REF, SELF

ILLEGAL

L

L

L

L

MODE

MRS

ILLEGAL

* Notes :

1. H: VIH, L: VIL, X: VIH or VIL.

The other combinations are inhibit.

2.An interval of tRWL is required between the final valid data input and the Precharge command.

3.If tRRD is not satisfied, this operation is illegal.

4.BA:Bank Address, RA:Row Address, CA:Column Address

From [Precharge]

To [DESL], [NOP] or [BST]: When these commands are executed, the synchronous DRAM enters the IDLE state after tRP has elapsed from the completion of Precharge

From [IDLE]

To [DESL], [NOP], [BST], [PRE] or [PALL]: These commands result in no operation.

To [ACTV]: The bank specified by the address pins and the ROW address is activated.

To [REF], [SELF]: The synchronous DRAM enters refresh mode (auto-refresh or self-refresh).

To [MRS]: The synchronous DRAM enters the mode register set cycle.

From [ROW ACTIVE]

To [DESL], [NOP] or [BST]: These commands result in no operation.

To [READ], [READ A]: A read operation starts. (However, an interval of tRCD is required.)

To [WRIT], [WRIT A]: A write operation starts. (However, an interval of tRCD is required.)

To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command.

To [PRE], [PALL]: These commands set the synchronous DRAM to Precharge mode. (However, an interval of is required.)

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GM72V66841CT/CLT

From [READ]

To [DESL], [NOP]: These commands continue read operations until the burst operation is completed.

To [BST]: This command stops a full-page burst.

To [READ], [READ A]: Data output by the previous read command continues to be

output. After CAS latency, the data output resulting from the next command will start.

To [WRIT], [WRIT A]: These commands stop a burst read, and start a write cycle.

To [ACTV]: This command makes other banks bank-active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command.

To [PRE], [PALL]: These commands stop a burst read, and the synchronous DRAM enters Precharge mode.

From [READ with AUTO-Precharge]

To [DESL], [NOP]: These commands continue read operations until the burst operation is completed, and the synchronous DRAM then enters Precharge mode.

To [ACTV]: This command makes other banks bank-active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command.

From [WRITE]

To [DESL], [NOP]: These commands continue write operations until the burst operation is completed.

To [BST]: This command stops a full-page burst.

To [READ], [READ A]: These commands stop a burst and start a read cycle.

To [WRIT], [WRIT A]: These commands stop a burst and start the next write cycle.

To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command.

To [PRE], [PALL]: These commands stop burst write and the synchronous DRAM then enters Precharge mode.

From [WRITE with AUTO-Precharge]

To [DESL], [NOP]: These commands continue write operations until the burst operation is completed, and the synchronous DRAM then enters Precharge mode.

To [ACTV]: This command makes the other bank active. (However, an interval of tRC is required.) Attempting to make the currently active bank active results in an illegal command.

From [REFRESH]

To [DESL], [NOP], [BST]: After an autorefresh cycle (after tRC), the synchronous DRAM automatically enters the Idle state.

13

LG Semicon

GM72V66841CT/CLT

64M SDRAM Function State Diagram

					SELF-
				REFRESH
		SR	ENTRY
			SR	EXIT
MODE	MRS				*1
				REFRESH
REGISTER		IDLE			AUTO-
					REFRESH
SET			CKE=L

ACTIVE

Clock

SUSPEND

CKE=H

BST

(on full page)

ACTIVE

CKE=L

ROW

ACTIVE

CKE=H

IDLE

Power

DOWN

BST

(on full page)

Write

CKE=L

WRITE

SUSPEND WRITE

CKE=H

WRITE

WITH AP

WRITE		WITH	AP
	WRITE
			READ
		READ
	WITH			AP

WRITEA	CKE=L			PRECHARGE
		WRITEA
SUSPEND
			PRECHARGE
	CKE=H

READ	READ
WITH	Read

AP

WRITE

WRITEAP

WITH

PRECHARGE

	CKE=L	READ
	READ
		SUSPEND
	CKE=H
	READ
	WITH AP

CKE=L

READA READA SUSPEND

CKE=H

	Power	Power	PRE-
			CHARGE
	APPLIED	ON
			Precharge

Automatic Transition after completion of command.

Transition resulting from command input.

Note: 1. After the auto-refresh operation, Precharge is performed automatically and enter the IDLE state.

14

LG Semicon

GM72V66841CT/CLT

Mode Register Configuration

The mode register is set by the input to the address pins (A0 to A13) during mode register set cycles. The mode register consists of five sections, each of which is assigned to address pins.

A13, A12, A11, A10, A9, A8: (OPCODE):

The synchronous DRAM has two types of write modes. One is the burst write mode, and the other is the single write mode. These bits specify write mode.

Burst read and BURST WRITE:

Burst write is performed for the specified burst length starting from the column address specified in the write cycle.

Burst read and SINGLE WRITE:

Data is only written to the column address specified during the write cycle, regardless of the burst length.

A7:

Keep this bit Low at the mode register set cycle.

A6, A5, A4: (LMODE):

These pins specify the CAS latency.

A3: (BT):

A burst type is specified . When full-page burst is performed, only "sequential" can be selected.

A2, A1, A0: (BL):

These pins specify the burst length.

A13	A12	A11		A10		A9			A8	A7	A6	A5	A4	A3	A2	A1	A0
		OPCODE								0		LMODE		BT		BL
					A6		A5		A4	CAS Latency			A3 Burst Type			A2 A1 A0			Burst Length
						0	0		0		R		0	Sequential					BT=0	BT=1
						0	0		1		R		1	Interleave		0	0	0	1	1
						0	1		0		2					0	0	1	2	2
						0	1		1		3					0	1	0	4	4
						1	X		X		R					0	1	1	8	8
																1	0	0	R	R
																1	0	1	R	R
A13 A12 A11 A10					A9	A8				Write mode						1	1	0	R	R
0	0	0	0		0		0	Burst read and BURST WRITE								1	1	1	F.P.	R
X	X	X	X		0		1				R				F.P. = Full Page
X	X	X	X		1		0	Burst read and SINGLE WRITE							(512:GM72V66841CT/CLT)
X X X X 1 1											R				R is Reserved (inhibit)
															X: 0 or 1
																				15

LG Semicon GM72V66841CT/CLT

Burst Sequence

	Burst		Starting Column			Addressing(decimal)
			Address
	Length
			A2	A1	A0	Sequential	Interleave
	2		V	V	0	0 - 1	0 - 1
			V	V	1	1 - 0	1 - 0
			V	0	0	0 - 1 - 2 - 3	0 - 1 - 2 - 3
	4		V	0	1	1 - 2 - 3 - 0	1 - 0 - 3 - 2
			V	1	0	2 - 3 - 0 - 1	2 - 3 - 0 - 1
			V	1	1	3 - 0 - 1 - 2	3 - 2 - 1 - 0
			0	0	0	0 - 1 - 2 - 3 - 4 - 5 - 6 - 7	0 - 1 - 2 - 3 - 4 - 5 - 6 - 7
			0	0	1	1 - 2 - 3 - 4 - 5 - 6 - 7 - 0	1 - 0 - 3 - 2 - 5 - 4 - 7 - 6
			0	1	0	2 - 3 - 4 - 5 - 6 - 7 - 0 - 1	2 - 3 - 0 - 1 - 6 - 7 - 4 - 5
	8		0	1	1	3 - 4 - 5 - 6 - 7 - 0 - 1 - 2	3 - 2 - 1 - 0 - 7 - 6 - 5 - 4
			1	0	0	4 - 5 - 6 - 7 - 0 - 1 - 2 - 3	4 - 5 - 6 - 7 - 0 - 1 - 2 - 3
			1	0	1	5 - 6 - 7 - 0 - 1 - 2 - 3 - 4	5 - 4 - 7 - 6 - 1 - 0 - 3 - 2
			1	1	0	6 - 7 - 0 - 1 - 2 - 3 - 4 - 5	6 - 7 - 4 - 5 - 2 - 3 - 0 - 1
			1	1	1	7 - 0 - 1 - 2 - 3 - 4 - 5 - 6	7 - 6 - 5 - 4 - 3 - 2 - 1 - 0

* Notes : V : Valid Address

16

LG Semicon	GM72V66841CT/CLT
Operation	of

GM72V661641CT/CLT, GM72V66841CT/CLT,

GM72V66441CT/CLT Series

Read / Write Operation

Bank active: Before executing a read or write operation, the corresponding bank and the row address must be activated by the bank active (ACTV) command. Bank 0, bank 1, bank 2 or bank 3 is activated according to the status of the A12/A13 pin, and the row address (AX0 to AX11) is activated by the A0 to A11 pins at the bank active command cycle. An interval of tRCD is required between the bank active command input and the following read/write command input.

Read operation: A read operation starts when a read command is input. Output buffer becomes Low-Z in the (CAS Latency - 1) cycle after read command set. GM72V66841CT/CLT can perform a burst read operation.

The burst length can be set to 1, 2, 4, 8 or full page(512;GM72V66841CT/CLT). The start address for a burst read is specified by the column address (AY0 to AY8; GM72V66841CT/CLT) and the bank select address (A12/A13) at the read command set cycle. In a read operation, data output starts after the number of cycles specified by the CAS Latency. The CAS Latency can be set to 2 or 3.

When the burst length is 1, 2, 4, or 8, the Dout buffer automatically becomes High-Z at the next cycle after the successive burst-length data has been output.

When the burst length is full-page (512;GM72V66841CT/CLT) data is repeatedly output until the burst stop command is input.

The CAS latency and burst length must be specified at the mode register.

CAS Latency
CLK
		tRCD
Command	ACTV	READ
Address	Row	Column
	CL = 2	out 0	out 1	out 2	out 3
Dout
	CL = 3		out 0	out 1	out 2	out 3
						CL : CAS Latency
						Burst	Length = 4
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