H
Quadrature Decoder/Counter
Interface ICs
Technical Data
HCTL-2000
HCTL-2016
HCTL-2020
•Interfaces Encoder to Microprocessor
•14 MHz Clock Operation
•Full 4X Decode
•High Noise Immunity:
Schmitt Trigger Inputs Digital Noise Filter
•12 or 16-Bit Binary Up/ Down Counter
•Latched Outputs
•8-Bit Tristate Interface
•8, 12, or 16-Bit Operating Modes
•Quadrature Decoder Output Signals, Up/Down and Count
•Cascade Output Signals, Up/ Down and Count
•Substantially Reduced System Software
•Interface Quadrature Incremental Encoders to Microprocessors
•Interface Digital Potentiometers to Digital Data Input Buses
The HCTL-2000, 2016, 2020 are CMOS ICs that perform the quadrature decoder, counter, and bus interface function. The HCTL-20XX family is designed to improve system performance
Part Number |
Description |
Package Drawing |
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HCTL-2000 |
12-bit counter. 14 MHz clock operation. |
A |
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HCTL-2016 |
All features of the HCTL-2000. |
16-bit counter. |
A |
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HCTL-2020 |
All features of the HCTL-2016. |
Quadrature decoder output |
B |
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signals. Cascade output signals. |
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ESD WARNING: Standard CMOS handling precautions should be observed with the HCTL-20XX family ICs.
2-178 |
5965-5894E |
in digital closed loop motion control systems and digital data input systems. It does this by shifting time intensive quadrature decoder functions to a cost effective hardware solution. The entire HCTL-20XX family consists of a 4x quadrature decoder, a binary up/down state counter,
and an 8-bit bus interface. The use of Schmitt-triggered CMOS inputs and input noise filters allows reliable operation in noisy environments. The HCTL-2000 contains a 12-bit counter. The HCTL-2016 and 2020 contain a 16-bit counter. The HCTL-2020 also contains quadrature decoder
output signals and cascade signals for use with many standard counter ICs. The HCTL20XX family provides LSTTL compatible tri-state output buffers. Operation is specified for a temperature range from -40 to +85°C at clock frequencies up to 14 MHz.
25.91 ± 0.25
19.05 ± 0.25 (1.02 ± 0.010)
(0.750 ± 0.010)
15°
1.52 |
± 0.13 |
15° |
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(0.060 |
± 0.005) |
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9.40 (0.370) |
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MOTION SENSING AND CONTROL
Table 1. Absolute Maximum Ratings
(All voltages below are referenced to VSS)
Parameter |
Symbol |
Limits |
Units |
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DC Supply Voltage |
VDD |
-0.3 to +5.5 |
V |
Input Voltage |
VIN |
-0.3 to VDD +0.3 |
V |
Storage Temperature |
TS |
-40 to +125 |
°C |
Operating Temperature |
TA[1] |
-40 to +85 |
°C |
Table 2. Recommended Operating Conditions |
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Parameter |
Symbol |
Limits |
Units |
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DC Supply Voltage |
VDD |
+4.5 to +5.5 |
V |
Ambient Temperature |
T [1] |
-40 to +85 |
°C |
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A |
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2-179
Table 3. DC Characteristics VDD = 5 V ± 5%; TA = -40 to 85°C
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Parameter |
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Condition |
Min. |
Typ. |
Max. |
Unit |
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V |
[2] |
Low-Level Input Voltage |
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1.5 |
V |
IL |
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V |
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High-Level Input Voltage |
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3.5 |
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V |
IH |
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VT+ |
Schmitt-Trigger Positive- |
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3.5 |
4.0 |
V |
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Going Threshold |
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VT- |
Schmitt-Trigger Negative- |
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1.0 |
1.5 |
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Going Threshold |
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VH |
Schmitt-Trigger Hysteresis |
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1.0 |
2.0 |
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IIN |
Input Current |
VIN = VSS or VDD |
-10 |
1 |
+10 |
μA |
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V |
[2] |
High-Level Output |
I |
OH |
-1.6 mA |
2.4 |
4.5 |
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V |
OH |
Voltage |
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V |
[2] |
Low-Level Output |
I |
OL |
= +4.8 mA |
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0.2 |
0.4 |
V |
OL |
Voltage |
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IOZ |
High-Z Output Leakage |
VO = VSS or VDD |
-10 |
1 |
+10 |
μA |
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Current |
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IDD |
Quiescent Supply Current |
VIN = VSS or VDD, VO = HiZ |
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5 |
μA |
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C |
IN |
Input Capacitance |
Any Input[3] |
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5 |
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pF |
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C |
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Output Capacitance |
Any Output[3] |
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pF |
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OUT |
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Notes:
1.Free air.
2.In general, for any VDD between the allowable limits (+4.5 V to +5.5 V), VIL = 0.3 VDD and VIH = 0.7 VDD; typical values are VOH = VDD - 0.5 V @ IOH = -40 μA and VOL = VSS + 0.2 V @ IOL = 1.6 mA.
3.Including package capacitance.
Figure 1. Reset Waveform.
Figure 2. Waveform for Positive Clock Related Delays.
2-180
Table 4. Functional Pin Descriptions
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Pin |
Pin |
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Symbol |
2000/2016 |
2020 |
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Description |
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VDD |
16 |
20 |
Power Supply |
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VSS |
8 |
10 |
Ground |
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CLK |
2 |
2 |
CLK is a Schmitt-trigger input for the external clock signal. |
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CHA |
7 |
9 |
CHA and CHB are Schmitt-trigger inputs which accept the outputs |
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CHB |
6 |
8 |
from a quadrature encoded source, such as incremental optical shaft |
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encoder. Two channels, A and B, nominally 90 degrees out of phase, |
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are required. |
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5 |
7 |
This active low Schmitt-trigger input clears the internal position |
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RST |
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counter and the position latch. It also resets the inhibit logic. |
RST |
is |
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asynchronous with respect to any other input signals. |
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4 |
4 |
This CMOS active low input enables the tri-state output buffers. The |
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OE |
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OE and SEL inputs are sampled by the internal inhibit logic on the |
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falling edge of the clock to control the loading of the internal position |
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data latch. |
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SEL |
3 |
3 |
This CMOS input directly controls which data byte from the position |
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latch is enabled into the 8-bit tri-state output buffer. As in OE above, |
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SEL also controls the internal inhibit logic. |
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SEL |
BYTE SELECTED |
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0 |
High |
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1 |
Low |
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CNTDCDR |
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16 |
A pulse is presented on this LSTTL-compatible output when the |
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quadrature decoder has detected a state transition. |
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5 |
This LSTTL-compatible output allows the user to determine whether |
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U/D |
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the IC is counting up or down and is intended to be used with the |
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CNTDCDR and CNTCAS outputs. The proper signal U (high level) or D |
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(low level) will be present before the rising edge of the CNTDCDR and |
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CNTCAS outputs. |
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CNTCAS |
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15 |
A pulse is presented on this LSTTL-compatible output when the |
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HCTL-2020 internal counter overflows or underflows. The rising edge |
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on this waveform may be used to trigger an external counter. |
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D0 |
1 |
1 |
These LSTTL-compatible tri-state outputs form an 8-bit output port |
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through which the contents of the 12/16-bit position latch may be read in |
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D1 |
15 |
19 |
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2 sequential bytes. The high byte, containing bits 8-15, is read first (on the |
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D2 |
14 |
18 |
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HCTL-2000, the most significant 4 bits of this byte are set to 0 internally). |
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D3 |
13 |
17 |
The lower byte, bits 0-7, is read second. |
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D4 |
12 |
14 |
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D5 |
11 |
13 |
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D6 |
10 |
12 |
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D7 |
9 |
11 |
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NC |
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6 |
Not connected - this pin should be left floating. |
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MOTION SENSING AND CONTROL
2-181
Table 5. Switching Characteristics Min/Max specifications at VDD = 5.0 ± 5%, TA = -40 to + 85°C.
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Symbol Description |
Min. |
Max. |
Units |
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1 |
tCLK |
Clock period |
70 |
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ns |
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2 |
tCHH |
Pulse width, clock high |
28 |
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3 |
t |
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[1] |
Delay time, rising edge of clock to valid, updated count |
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65 |
ns |
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CD |
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information on D0-7 |
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4 |
tODE |
Delay time, |
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fall to valid data |
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ns |
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OE |
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5 |
tODZ |
Delay time, |
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rise to Hi-Z state on D0-7 |
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ns |
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6 |
tSDV |
Delay time, SEL valid to stable, selected data byte |
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65 |
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(delay to High Byte = delay to Low Byte) |
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7 |
tCLH |
Pulse width, clock low |
28 |
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8 |
t |
[2] |
Setup time, SEL before clock fall |
20 |
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SS |
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9 |
t |
[2] |
Setup time, |
OE |
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before clock fall |
20 |
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OS |
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10 |
t |
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[2] |
Hold time, SEL after clock fall |
0 |
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SH |
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11 |
tOH[2] |
Hold time, |
OE |
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after clock fall |
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12 |
tRST |
Pulse width, |
RST |
low |
28 |
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13 |
tDCD |
Hold time, last position count stable on D0-7 after clock rise |
10 |
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14 |
tDSD |
Hold time, last data byte stable after next SEL state change |
5 |
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15 |
tDOD |
Hold time, data byte stable after |
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rise |
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16 |
tUDD |
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valid after clock rise |
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Delay time, U/D |
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17 |
tCHD |
Delay time, CNTDCDR or CNTCAS high after clock rise |
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45 |
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18 |
tCLD |
Delay time, CNTDCDR or CNTCAS low after clock fall |
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45 |
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19 |
tUDH |
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10 |
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Hold time, U/D |
stable after clock rise |
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20 |
tUDCS |
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tCLK-45 |
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Setup time, U/D |
valid before CNTDCDR or CNTCAS rise |
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21 |
tUDCH |
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tCLK-45 |
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Hold time, U/D |
stable after CNTDCDR or CNTCAS rise |
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Notes:
1.tCD specification and waveform assume latch not inhibited.
2.tSS, tOS, tSH, tOH only pertain to proper operation of the inhibit logic. In other cases, such as 8 bit read operations, these setup and hold times do not need to be observed.
Figure 3. Tri-State Output Timing.
2-182
AND CONTROL
MOTION SENSING
Figure 4. Bus Control Timing.
Figure 5. Decoder, Cascade Output Timing (HCTL-2020 only).
2-183