The MK2302S-01is a high performance Zero Delay
Buffer (ZDB) which integrates ICS’ proprietary
analog/digital Phase Locked Loop (PLL) techniques.
The chip is part of ICS’ ClockBlocksTM family and was
designed as a performance upgrade to meet today’s
higher speed and lo wer voltage requirements. The zero
delay feature means that the rising edge of the input
clock aligns with the rising edges of both output clocks,
giving the appearance of no delay through the device.
There are two outputs on the chip , one being a
low-skew divide by two of the other output.
The MK2302S-01 is ideal for synchronizing outputs in a
large variety of systems, from personal computers to
data communications to graphics/video. By allowing
off-chip feedback paths, the device can eliminate the
delay through other devices.
Features
• 8 pin SOIC package
• Low input to output skew of 250ps max
• Absolute jitter ± 500ps
• Propagation Delay ± 350ps
• Ability to choose between different multipliers from
0.5X to 16X
• Output clock frequency up to 133 MHz at 3.3V
• Can recover degraded input clock duty cycle
• Output clock duty cycle of 45/55
• Full CMOS clock swings with 25mA drive capability
at TTL levels
• Advanced, low power CMOS process
• Operating voltage of 3.3V or 5V
• Industrial temperature version available
Block Diagram
IC L K
S1:0
FBIN
Phase
Detector,
Charge
Pump,
and Loop
divide
by N
External feedback can come from CLK1 or CLK2 (see table on page 2)
Filter
VCO
/2
CLK1
CLK2
MDS 2302S-01 B
Integrated Circuit Systems, Inc.
● 525 Race Street, San Jose, CA 95126 ● tel (408 ) 295-9800 ● www.icst.com
Multiplier and Zero Delay Buffer
MK2302S-01
Pin Assignment
Clock Multiplier Decoding Table 1
(Multiplies Input clock by shown amount)
Pin Descriptions
FBIN
ICLK
GND
VDD
S0
CLK1
CLK21
2
3
4
8
7
6
5
GND
S1
1
2
3
4
8
7
6
5
8 pin (150 mil) SOIC
FBINS1S0CLK1CLK2
CLK1002 X ICLKICLK
CLK1014 X ICLK2 X ICLK
CLK110ICLKICLK/2
CLK1118 X ICLK4 X ICLK
CLK2004 X ICLK2 X ICLK
CLK2018 X ICLK4 X ICLK
CLK2102 X ICLKICLK
CLK21116 X ICLK8 XICLK
Pin
Number
Pin
Name
Pin
Type
Pin Description
1FBINInputFeedback clock input.
2ICLKInputReference clock input.
3GNDPowerConnect to ground.
4S0InputSelect 0 for output clock per decoding table above. Pull-up.
5S1InputSelect 1 for output clock per decoding table above. Pull up.
6CLK1OutputClock output per table above.
7VDDPowerConnect to +3.3V or +5.0V.
8CLK2OutputClock output per table above. Low skew divide by two of pin 6 clock.
131
AVR354 harman/kardon
MDS 2302S-01 B
Integrated Circuit Systems, Inc. ● 525 Race Str eet, San Jose, CA 95126 ● tel (408) 295 -9800 ● www.icst.com
Multiformat Video Encoder
Six, 11-Bit, 297 MHz DACs
ADV7342/ADV7343
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
74.25 MHz 20-/30-bit high definition input support
Compliant with SMPTE 274M (1080i), 296M (720p),
and 240M (1035i)
6, 11-bit, 297 MHz video DACs
16× (216 MHz) DAC oversampling for SD
8× (216 MHz) DAC oversampling for ED
4× (297 MHz) DAC oversampling for HD
37 mA maximum DAC output current
NTSC M, PAL B/D/G/H/I/M/N, PAL 60 support
NTSC and PAL square pixel operation (24.54 MHz/29.5 MHz)
Multiformat video input support
4:2:2 YCrCb (SD, ED, and HD)
4:4:4 YCrCb (ED and HD)
4:4:4 RGB (SD, ED, and HD)
Multiformat video output support
Composite (CVBS) and S-Video (Y/C)
Component YPrPb (SD, ED, and HD)
Component RGB (SD, ED, and HD)
Macrovision® Rev 7.1.L1 (SD) and Rev 1.2 (ED) compliant
Simultaneous SD and ED/HD operation
EIA/CEA-861B compliance support
Programmable features
Luma and chroma filter responses
Vertical blanking interval (VBI)
Subcarrier frequency (F
SC
) and phase
Luma delay
Copy generation management system (CGMS)
Closed captioning and wide screen signaling (WSS)
Integrated subcarrier locking to external video source
Complete on-chip video timing generator
On-chip test pattern generation
On-board voltage reference (optional external input)
Serial MPU interface with dual I
2
C® and SPI® compatibility
3.3 V analog operation
1.8 V digital operation
3.3 V I/O operation
Temperature range: −40°C to +85°C
APPLICATIONS
DVD recorders and players
High definition Blu-ray DVD players
HD-DVD players
FUNCTIONAL BLOCK DIAGRAM
R
GND_IO
VDD_IO
10-BIT
SD
VIDEO
DATA
20-BIT
ED/HD
VIDEO
DATA
S_HSYNCP_HSYNC P_VSYNC P_BLANKS_VSYNC
11-BIT
DAC 1
DAC 1
11-BIT
DAC 2
DAC 2
11-BIT
DAC 3
DAC 3
11-BIT
DAC 4
DAC 4
11-BIT
DAC 5
DAC 5
11-BIT
DAC 6
DAC 6
MULTIPLEXER
REFERENCE
AND CABLE
DETECT
16x/4x OVERSAM PLING
DAC PLL
VIDEO TI MING GENERATOR
POWER
MANAGEMENT
CONTRO L
CLKIN (2) PV
DD
PGND EXT_LF (2) V
REF
COMP (2)
R
SET
(2)
ED/HD INPUT
DEINTERLEAVE
PROGRAMMABLE
HDTV FILTERS
SHARPNESS AND
ADAPTIVE FILTER
CONTROL
YCbCr
HDTV
TEST
PATTERN
GENERATOR
YCbCr
TO
RGB MATRIX
G/B
RGB
ASYNC
BYPASS
RGB
DGND (2)VDD (2)
SCL/
MOSI
SDA/
SCLK
A
LSB/
SPI_SS
SFL/
MISO
MPU PORT
SUBCARRIER FREQUENCY
LOCK (SFL )
YUV
TO
YCrCb/
RGB
PROGRAMMABLE
CHROMINANCE
FILTER
ADD
BURST
RGB/YCrCb
TO
YUV
MATRIX
4:2:2 TO 4: 4:4
HD DDR
DEINTERLEAVE
SIN/COS DDS
BLOCK
16×
FILTER
16×
FILTER
4×
FILTER
AGND
V
AA
ADD
SYNC
VBI DATA SERVICE
INSERTION
PROGRAMMABLE
LUMINANCE
FILTER
06399-001
ADV7342/ADV7343
Figure 1.
Protected by U.S. Patent Numbers 5,343,196 and 5,442,355 and other intellectual property rights.
Protected by U.S. Patent Numbers 4,631,603, 4,577,216, 4,819,098 and other intellectual property rights.
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Rev. 0 | Page 18 of 88
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
64
GND_IO63CLKIN_B62S761S660S559S458S357DGND56V
DD
55S254S153S052
TEST551TEST450S_HSYNC49S_VSYNC
47
R
SET1
46
V
REF
45
COMP1
42
DAC 3
43
DAC 2
44
DAC 1
48
SFL/MISO
41
V
AA
40
AGND
39
DAC 4
37
DAC 6
36
R
SET2
35
COMP2
34
PV
DD
33
EXT_LF1
38
DAC 5
2
TEST0
3
TEST1
4
Y0
7
Y3
6
Y2
5
Y1
1
V
DD_IO
8
Y4
9
Y5
10
V
DD
12
Y6
13
Y7
14
TEST2
15
TEST3
16
C0
11
DGND
17C118C219
ALSB/SPI_SS
20
SDA/SCLK
21
SCL/MOSI
22 23
P_HSYNC
24
P_VSYNC
25
P_BLANK
26
C4
C327C528C629C7
30
CLKIN_A
31 32
PGND
PIN 1
ADV7342/ADV7343
TOP VIEW
(Not to Scale)
EXT_LF2
06399-021
Figure 21. Pin Configuration
Table 13. Pin Function Descriptions
Pin No. Mnemonic
Input/
Output
Description
13, 12,
9 to 4
Y7 to Y0 I 8-Bit Pixel Port. Y0 is the LSB. Refer to Table 31 for input modes.
29 to 25,
18 to 16
C7 to C0 I 8-Bit Pixel Port. C0 is the LSB. Refer to Table 31 for input modes.
62 to 58,
55 to 53
S7 to S0 I 8-Bit Pixel Port. S0 is the LSB. Refer to Table 31 for input modes.
52, 51, 15,
14, 3, 2
TEST5 to
TEST0
I Unused. These pins should be connected to DGND.
30 CLKIN_A I Pixel Clock Input for HD Only (74.25 MHz), ED1 Only (27 MHz or 54 MHz) or SD Only (27 MHz).
63 CLKIN_B I
Pixel Clock Input for Dual Modes Only. Requires a 27 MHz reference clock for ED operation or a
74.25 MHz reference clock for HD operation.
50
S_HSYNC
I/O
SD Horizontal Synchronization Signal. This pin can also be configured to output an SD, ED, or HD
horizontal synchronization signal. See the External Horizontal and Vertical Synchronization
Control section.
49
S_VSYNC
I/O
SD Vertical Synchronization Signal. This pin can also be configured to output an SD, ED, or HD
vertical synchronization signal. See the External Horizontal and Vertical Synchronization Control
section.
22
P_HSYNC
I
ED/HD Horizontal Synchronization Signal. See the External Horizontal and Vertical
Synchronization Control section.
23
P_VSYNC
I
ED/HD Vertical Synchronization Signal. See the External Horizontal and Vertical Synchronization
Control section.
24
P_BLANK
I ED/HD Blanking Signal. See the External Horizontal and Vertical Synchronization Control section.
48 SFL/MISO I/O
Multifunctional Pin: Subcarrier Frequency Lock (SFL) Input/SPI Data Output. The SFL input is
used to drive the color subcarrier DDS system, timing reset, or subcarrier reset.
47 R
SET1
I
This pin is used to control the amplitudes of the DAC 1, DAC 2, and DAC 3 outputs. For full-drive
operation (for example, into a 37.5 Ω load), a 510 Ω resistor must be connected from R
SET1
to
AGND. For low drive operation (for example, into a 300 Ω load), a 4.12 kΩ resistor must be
connected from R
SET1
to AGND.
133
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ADV7342/ADV7343
Rev. 0 | Page 19 of 88
Pin No. Mnemonic
Input/
Output Description
36 R
SET2
I
This pin is used to control the amplitudes of the DAC 4, DAC 5, and DAC 6 outputs. A 4.12 kΩ
resistor must be connected from R
SET2
to AGND.
45, 35
COMP1,
COMP2
O Compensation Pins. Connect a 2.2 nF capacitor from both COMP pins to V
AA
.
44, 43, 42
DAC 1, DAC 2,
DAC 3
O DAC Outputs. Full and low drive capable DACs.
39, 38, 37
DAC 4, DAC 5,
DAC 6
O DAC Outputs. Low drive only capable DACs.
21 SCL/MOSI I Multifunctional Pin: I2C Clock Input/SPI Data Input.
20 SDA/SCLK I/O Multifunctional Pin: I2C Data Input/Output. Also, SPI clock input.
19
ALSB/SPI_SS
I Multifunctional Pin: This signal sets up the LSB
2
of the MPU I2C address. Also, SPI slave select.
46 V
REF
Optional External Voltage Reference Input for DACs or Voltage Reference Output.
41 VAA P Analog Power Supply (3.3 V).
10, 56 VDD P
Digital Power Supply (1.8 V). For dual-supply configurations, V
DD
can be connected to other 1.8 V
supplies through a ferrite bead or suitable filtering.
1 V
DD_IO
P Input/Output Digital Power Supply (3.3 V).
34 PVDD P
PLL Power Supply (1.8 V). For dual-supply configurations, PV
DD
can be connected to other 1.8 V
supplies through a ferrite bead or suitable filtering.
33 EXT_LF1 I External Loop Filter for On-Chip PLL 1.
31 EXT_LF2 I External Loop Filter for On-Chip PLL 2.
32 PGND G PLL Ground Pin.
40 AGND G Analog Ground Pin.
11, 57 DGND G Digital Ground Pin.
64 GND_IO G Input/Output Supply Ground Pin.
1
ED = enhanced definition = 525p and 625p.
2
LSB = least significant bit. In the ADV7342, setting the LSB to 0 sets the I2C address to 0xD4. Setting it to 1 sets the I2C address to 0xD6. In the ADV7343, setting the
LSB to 0 sets the I2C address to 0x54. Setting it to 1 sets the I2C address to 0x56.
134
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IC51 XM IC
137
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5V POWERED MULTI-CHANNEL
RS-232 DRIVERS AND RECEIVERS
■ SUPPLYVOLTAGERANGE:4.5TO 5.5V
■
SUPPLYCURRENT NOLOAD(TYP):5mA
■ TRANSMITTEROUTPUTVOLTAGESWING
(TYP):±7.8V
■
CONTROLLEDOUTPUTSLEWRATE
■ RECEIVERINPUTVOLTAGERANGE:
■
DATARATE(TYP):220Kbps
■ OPERATINGTEMPERATURERAN GE:
-40TO85
■
COMPATIBLEWITH MAX232ANDMAX202
o
C,0 TO70oC
DESCRIPTION
The ST232 is a 2 driver, 2 receiver device
following EIA/TIA-232 and V.28 communication
standard. It is particularly suitable for applications
where ±12V is not available. The ST232 uses a
single 5V power supply and only four external
capacitors (0.1µF). Typical applications are in:
Portable Computers, Low PowerModems,
Interfaces Translation, Battery Powered RS-232
System,Multi-Drop RS-232 Networks.
±30V
ST232
N
(PlasticPackage)
(Micro Package)
W
(Micro PackageLarge)T(TSSOPPackage)
D
ORDERCODES
TypeTemperature
ST232CN0 to 70
ST232BN-40 to 85
ST232CD0 to 70
ST232BD-40 to 85
ST232CDR0 to 70
ST232BDR-40 to 85
ST232CW0 to 70
ST232BW-40 to 85
ST232CWR0 to 70
ST232BWR-40 to 85
ST232CT0 to 70
ST232BT-40 to 85
ST232CTR0 to 70
ST232BTR-40 to 85
February 2001
PackageCommen ts
Rang e
o
CDIP-1625 parts per tube / 40 tubeper box
o
CDIP-1625 parts per tube / 40 tubeper box
o
CSO-16 (Tube)50 parts per tube / 20 tubeper box
o
CSO-16 (Tube)50 parts per tube / 20 tube per box
o
CSO-16 (Tape& Reel)2500 parts per reel
o
CSO-16 (Tape & Reel)2500 parts per reel
o
CSO-16 Large (Tube)49 parts per tube / 25 tubeper box
o
CSO-16 Large (Tube)49 parts per tube / 25 tubeper box
o
CSO-16 Large (Tape & Reel)1000 parts per reel
o
CSO-16 Large (Tape & Reel)1000 parts per reel
o
CTSSOP16 (Tube)only for samples
o
CTSSOP16 (Tube)only for samples
o
CTSSOP16 (Tape & Reel)2500 parts per reel
o
CTSSOP16 (Tape & Reel)2500 parts per reel
1/11
150
AVR354 harman/kardon
ST232
PIN CONFIGURATION
PIN DESCRIPTION
PIN NoSYMBOLNAME AND F UNC T I O N
1C
+Positive Terminal forthe first Charge Pump Capacitor
1
2V+Doubled Voltage Terminal
3C
4C
5C
-Negative Terminal for the first Charge Pump Capacitor
1
+Positive Terminal forthe second Charge Pump Capacitor
2
-Negative Terminal for the second Charge Pump Capacitor
2
6V-Inverted Voltage Terminal
7T2
8R2
9R2
10T2
11T1
12R1
13R1
14T1
OUT
IN
OUT
IN
IN
OUT
IN
OUT
Second Transmitter Output Voltage
Second Receiver Input Voltage
Second Receiver Output Voltage
Second Transmitter Input Voltage
First Transmitter Input Voltage
First Receiver Output Voltage
First Receiver Input Voltage
First Transmitter Output Voltage
15GNDGround
16V
CC
Supply Voltage
ABSOLUTE MAXIMUM RATINGS(Note1)
Symb o lPara met erVal u eUnit
V
T
R
T
OUT
R
OUT
T
SCTOUT
T
AbsoluteMaximum Ratingsarethosevalues beyond whichdamage tothedevicemayoccur. Functionaloperationundertheseconditionisnot implied.
Note1:Noexternal supply can be appliedtoV+ terminalandV- terminal.
2/11
Supply Voltage-0.3 to 6V
CC
Transmitter Input Voltage Range-0.3 to (VCC+ 0.3)V
IN
Receiver Input Voltage Range±30V
IN
Transmitter Output Voltage Range(V+ + 0.3) to (V- - 0.3)V
Receiver Output Voltage Range-0.3 to (VCC+ 0.3)V
Short Circuit Duration on T
Storage Temperature Range-65 to +150
stg
OUT
infinite
o
C
151
AVR354 harman/kardon
M24C64
M24C32
64Kbit and 32Kbit Serial I²C Bus EEPROM
FEATURES SUMMARY
M24C64
M24C32
2
C Serial Interface
M24C64
M24C64-W
M24C64-R
M24C32
M24C32-W
M24C32-R
■Two-Wire I
Supports 400kHz Protocol
■Single Supply Voltage:
–4.5 to 5.5V for M24Cxx
–2.5 to 5.5V for M24Cxx-W
–1.8 to 5.5V for M24Cxx-R
■Write Control Input
■BYTE and PAGE WRITE (up to 32 Bytes)
■RANDOM and SEQUENTIAL READ Modes
■Self-Timed Programming Cycle
■Automatic Address Incrementing
■Enhanced ESD/Latch-Up Protection
■More than 1 Million Erase/Write Cycles
■More than 40-Year Data Retention
Table 1. Product List
ReferencePart Number
Figure 1. Packages
8
1
PDIP8 (BN)
8
1
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
UFDFPN8 (MB)
2x3mm² (MLP)
1/26January 2005
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AVR354 harman/kardon
M24C64, M24C32
SUMMARY DESCRIPTION
These I2C-compatible electrically erasable programmable memory (EEPROM) devices are organized as 8192 x 8 bits (M24C64) and 4096 x 8 bits
(M24C32).
Table 2. Signal Names
E0, E1, E2Chip Enable
SDASerial Data
Figure 2. Logic Diagram
V
CC
3
E0-E2SDA
SCL
WC
2
I
C uses a two-wire serial interf ace, comprisi ng a
M24C64
M24C32
V
SS
AI01844B
bi-directional data line and a clock line. The devices carry a built-in 4-bit Device Type Identifier code
(1010) in accordance with the I
The device behaves as a slave in the I
2
C bus definition.
2
C protocol,
with all memory operations synchronized by the
serial clock. Read and Write operations are initiated by a Start condition, generated by the bus master. The Start condition is followed by a Device
Select Code and Read/Write
bit (RW) (as described in Table 3.), terminated by an acknowledge bit.
When writing data to the memory, the dev ice inserts an acknowled ge bit during the 9
th
bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledge s the rec eipt o f the d ata by te
in the same way. Data transfers are terminated by
a Stop condition after an Ack for Write, and after a
NoAck for Read.
SCLSerial Clock
WC
V
CC
V
SS
Power On Reset: V
Write Control
Supply Voltage
Ground
Lock-Out Write Protect
CC
In order to prevent data corruption and inadvertent
Write operations during Power-up, a Power On
Reset (POR) circuit is included . At Power-up, the
internal reset i s he ld a cti ve unti l V
has reached
CC
the Power On Reset (POR) threshold voltage, and
all operations are disabled – the device will not respond to any command. In the sam e way, when
V
drops from the operat ing voltage, below the
CC
Power On Reset (PO R) threshold voltage, a ll operations are disa bled and the device will not respond to any command.
A stable and valid V
(as defined in Table 9. and
CC
Table 10.) must be applied before applying any
logic signal.
Figure 3. DIP, SO, TSSOP and UFDFPN
Connections
M24C64
M24C32
AI01845C
8
CC
7
WCE1
6
SCL
5
SDAV
1
E0V
2
3
E2
4
SS
Note: See PACKAGE ME CHANICAL section for package dimen-
sions, and how to identify pin-1.
4/26
153
AVR354 harman/kardon
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