Harman Kardon AVR-350 Schematic

harman/kardon

AVR 347/230, AVR 350/230 Semiconductor Pinouts

Page 1 of 51

harman/kardon Service Manual

AVR 347/230
AVR 350/230

7 x 55W 7.1 CHANNEL A/V RECEIVERS

THIS MANUAL CONTAINS SEMICONDUCTOR PINOUTS ONLY.
Main Service Manual in separate file

CONTENTS

Released EU2008 harman/kardon, Inc. Rev 0, 07/2008
250 Crossways Park Dr.
Woodbury, New York, 11797

54

∗hFE Rank O(5000to12000), P(6500to20000), Y(15000to30000)

Darlington 2SB1647

IC

–

V

CE Characteristics

(Typical)

hFE

–

I

C Characteristics

(Typical)

hFE

–

I

C

Temperature Characteristics (Typical)

IC

–

V

BE Temperature Characteristics

(Typical)

VCE(sat)–IB Characteristics

(Typical)

Pc–Ta Derating

–10mA

–50mA

–3mA

0

–3

–2

–1

–0.2

–1–0.5 –10–5 –200–100–50

Base Current IB(mA)

Collector-Emitter Saturation Voltage VCE(sat)(V)

I

C

=–10A

I

C

=–15A

IC =–5A

0

–15

–10

–5

0–3–2–1

Base-Emittor Voltage V

BE(V)

Collector Current IC(A)

(VCE=–4V)

125˚C (Case Temp)

25˚C (Case Temp)

–30˚C (Case Temp)

–0.2 –0.5 –1 –5 –10 –15

Collector Current I

C(A)

DC Current Gain hFE

(VCE=–4V)

1,000

10,000

50,000

5,000

Typ

(VCE=–4V)

–0.2 –1–0.5 –5 –10 –15

1000

5000

10000

50000

Collector Current IC(A)

DC Current Gain hFE

25˚C

–30˚C

125˚C

Time t(ms)

0.1

1

3

0.5

1 10 100 1000 2000

Transient Thermal Resistance θj-a(˚C/W)

0.02 0.10.05 0.5 1 5 10

0

40

20

60

Cut-off Frequency fT(MHZ)

(VCE=–12V)

Emitter Current I

E(A)

Safe Operating Area (Single Pulse)

θj-a

–

t

Characteristics

f

T

–

I

E Characteristics

(Typical)

0

0

–5

–10

–15

–2 –6–4

Collector-Emitter Voltage VCE(V)

Collector Current IC(A)

–1.5mA

–1.0mA

–0.8mA

I

B

=–0.3mA

–0.5mA

–2mA

130

100

50

3.5
0

Ambient Temperature Ta(˚C)

Maximum Power Dissipation PC(W)

With Infinite heatsink

Without Heatsink

0 25 50 75 100 125 150

Silicon PNP Epitaxial Planar Transistor (Complement to type 2SD2560)

Application : Audio, Series Regulator and General Purpose

Symbol
V

CBO

VCEO
VEBO
IC
IB
PC
Tj
T

stg

2SB1647

–150
–150

–5

–15

–1

130(Tc=25°C)

150

–55 to +150

Unit

V
V
V
A
A

W
°C
°C

■

Absolute maximum ratings

■

Electrical Characteristics

Symbol

I

CBO

IEBO
V(BR)CEO
hFE
VCE(sat)
VBE(sat)
fT
COB

2SB1647

–100

max

–100max
–150min
5000min∗

–2.5

max

–3.0max

45typ

320typ

Unit

µ

A

µ

A

V

V
V

MHz

pF

Conditions

V

CB=–150V

V

EB=–5V

I

C=–30mA

V

CE=–4V, IC=–10A

I

C=–10A, IB=–10mA

I

C=–10A, IB=–10mA

V

CE=–12V, IE=2A

V

CB=–10V, f=1MHz

(Ta=25°C) (Ta=25°C)

External Dimensions MT-100(TO3P)

15.6

±0.4

9.6

19.9

±0.3

4.0 2.0

5.0

±0.2

1.8

ø3.2

±0.1

2

3

1.05

+0.2

-0.1

20.0min

4.0max

BE

5.45

±0.1

5.45

±0.1

C

4.8

±0.2

0.65

+0.2

-0.1

1.4

2.0

±0.1

a
b

■Typical Switching Characteristics (Common Emitter)

V

CC

(V)

–40

RL

(Ω)

4

I

C

(A)

10

V

BB2

(V)

5

I

B2

(mA)

10

t

on

(µs)

0.7typ

t

stg

(µs)

1.6typ

t

f

(µs)

1.1typ

IB1

(mA)

–10

VBB1

(V)

–10

Weight : Approx 6.0g
a. Type No.
b. Lot No.

E

Equivalent circuit

harman/kardon

AVR 347/230, AVR 350/230 Semiconductor Pinouts

Page 2 of 51

(70Ω)

B

C

158

Silicon NPN Triple Diffused Planar Transistor (Complement to type 2SB1647)

Application : Audio, Series Regulator and General Purpose

Symbol
V

CBO

VCEO
VEBO
IC
IB
PC
Tj
T

stg

2SD2560

150
150

5

15

1

130(Tc=25°C)

150

–55to+150

Unit

V
V
V
A
A
W

°C
°C

■

Absolute maximum ratings

■

Electrical Characteristics

Symbol

I

CBO

IEBO
V(BR)CEO
hFE
VCE(sat)
VBE(sat)
fT
COB

2SD2560

100

max

100max
150min

5000min∗

2.5

max

3.0max
70typ

120typ

Unit

µ

A

µ

A

V

V
V

MHz

pF

Conditions

V

CB=150V

V

EB=5V

I

C=30mA

V

CE=4V, IC=10A

I

C=10A, IB=10mA

I

C=10A, IB=10mA

V

CE=12V, IE=–2A

V

CB=10V, f=1MHz

Darlington 2SD2560

(Ta=25°C) (Ta=25°C)

IC

–

V

CE Characteristics

(Typical)

Safe Operating Area (Single Pulse)

0

0

10

5

15

246

Collector-Emitter Voltage V

CE(V)

Collector Current IC(A)

50mA

I

B

=0.3mA

0.5mA

0.8mA

2mA

1.0mA

3mA

10mA

1.5mA

VCE(sat)–IB Characteristics

(Typical)

0

3

2

1

0.2

10.5 105 20010050
Base Current IB(mA)

Collector-Emitter Saturation Voltage VCE(sat)(V)

IC =.15A
IC =.10A

IC =.5A

IC

–

V

BE Temperature Characteristics

(Typical)

0

15

5

10

0 2 2.21

Base-Emittor Voltage V

BE(V)

Collector Current IC(A)

(VCE=4V)

125˚C (Case Temp)

25˚C (Case Temp)

–30˚C (Case Temp)

hFE

–

I

C Characteristics

(Typical)

Collector Current IC(A)

02 0.5 1 10 155

50000

1000

5000

10000

500

DC Current Gain hFE

(VCE=4V)

Typ

02 0.5 1 10 155

50000

1000

5000

10000

500

DC Current Gain hFE

(VCE=4V)

hFE

–

I

C

Temperature Characteristics (Typical)

Collector Current IC(A)

125˚C

–30˚C

25˚C

θj-a

–

t

Characteristics

0.1

1.0

3.0

0.5

1 10 100 1000 2000

Time t(ms)

Transient Thermal Resistance θj-a(˚C/W)

fT

–

I

E Characteristics

(Typical)

(VCE=12V)

Emitter Current I

E(A)

–0.05–0.02 –01 –0.5 –1 –5 –10

0

40

20

60

80

Cut-off Frequency fT(MHZ)

Pc–Ta Derating

130

100

50

3.5
0

Ambient Temperature Ta(˚C)

Maximum Power Dissipation PC(W)

With Infinite heatsink

Without Heatsink

0 25 50 75 100 125 150

External Dimensions MT-100(TO3P)

15.6

±0.4

9.6

19.9

±0.3

4.0 2.0

5.0

±0.2

1.8

ø3.2

±0.1

2

3

1.05

+0.2

-0.1

20.0min

4.0max

BE

5.45

±0.1

5.45

±0.1

C

4.8

±0.2

0.65

+0.2

-0.1

1.4

2.0

±0.1

a
b

Weight : Approx 6.0g
a. Type No.
b. Lot No.

■Typical Switching Characteristics (Common Emitter)

V

CC

(V)

40

RL

(Ω)

4

IC

(A)
10

V

BB2

(V)

–5

IB2

(mA)

–10

t

on

(µs)

0.8typ

t

stg

(µs)

4.0typ

t

f

(µs)

1.2typ

I

B1

(mA)

10

VBB1

(V)
10

Equivalent circuit

∗hFE Rank O(5000to12000), P(6500to20000), Y(15000to30000)

harman/kardon

AVR 347/230, AVR 350/230 Semiconductor Pinouts

Page 3 of 51

B

C

(70Ω)

E

74ACT04

harman/kardon

AVR 347/230, AVR 350/230 Semiconductor Pinouts

Page 4 of 51

HEX INVERTER

■ HIGH SPEED: t

■ LOW POWER DISSIPATION:

I

= 2µA(MAX.) at TA=25°C

CC

■ COMPATI B L E WITH TTL OUTPUT S

V

= 2V (MIN.), VIL = 0.8V (MAX.)

IH

■ 50Ω TRANSMI SS ION LINE DRIVING

= 5.0ns (TYP.) at VCC = 5V

PD

CAPABILITY

■ SYMMETRICAL OUTPUT IMPEDANCE:

|I

| = IOL = 24mA (MIN)

OH

■ BALANCED PROPAGATION DELAYS:

t

≅ t

PLH

■ OPERA TING VOLTAGE RANGE:

V

CC

■ PIN AND FUNCTION COMPATIBLE WITH

PHL

(OPR) = 4.5V to 5.5V

74 SERIES 04

■ IMPROVED LATCH-UP IMMUNITY

DESCRIPTION

The 74ACT04 is an advanced high-speed CMOS
HEX INVERTER fabricated with sub-micron
silicon gate and double-layer metal wiring C

2

MOS
technology.
The internal circuit is composed of 3 stages
including buffer output , which enables high noise
immunity and stable output.

TSSOPDIP SOP

ORDER CODES

PACKAGE TUBE T & R

DIP 74ACT04B

SOP 74ACT04M 74ACT04MTR

TSSOP 74ACT04TTR

The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with
protection circuits against stat ic discharge, giving
them 2KV ESD immunity and transient excess
voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

1/8July 2001

74LCX32

harman/kardon

AVR 347/230, AVR 350/230 Semiconductor Pinouts

Page 5 of 51

LOW VOLTAGE CMOS QUAD 2-INPUT OR GATE

WITH 5V TOLERANT INPUTS

■ 5V TOLERANT INPUTS

■ HIGH SPEED:

t

= 5.2ns (MAX.) at VCC = 3V

PD

■ POWER DOWN PROTECTION ON INPUTS

AND OUTPUTS

■ SYMMETRICAL OUTPUT IMPEDANCE:

|I

| = IOL = 24mA (MIN) at VCC = 3V

OH

■ PCI BUS LEVELS GUARANTEED AT 24 mA

■ BALANCED PROPAGATION DELAYS:

t

≅ t

PLH

■ OPERATI N G VOLTAGE RANGE:

V

CC

PHL

(OPR) = 2.0V to 3.6V (1.5V Data

Retention)

■ PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 32

■ LATCH-UP PERFORMANCE EXCEEDS

500mA (JESD 17)

■ ESD PERFORMANCE:

HBM > 2000V (MIL STD 883 method 3015);
MM > 200V

DESCRIPTION

The 74LCX32 is a low voltage CMOS QUAD
2-INPUT OR GATE fabricated with sub-micron
silicon gate and double-layer metal wiring C

2

MOS

TSSOPSOP

Table 1: Order Codes

PACKAGE T & R

SOP 74LCX32MTR

TSSOP 74LCX32TTR

technology. It is ideal for low power and high
speed 3.3V applications; it can be interfaced to 5V
signal environment for inputs.
It has same speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs and outputs are equipped with
protection circuits against static disc harge, giving
them 2KV ESD immunity and transient excess
voltage.

Figure 1: Pin Conne ction And IE C Logic Symbols

September 2004

Rev. 6

LOW VOLTAGE CMOS DUAL D-TYPE FLIP FLOP

harman/kardon

AVR 347/230, AVR 350/230 Semiconductor Pinouts

Page 6 of 51

■ 5V TOLERANT INPUTS

■ HIGH SPEED :

f

= 150 MHz (MAX.) at VCC=3V

MAX

■ POWER DOWNPROTECTION ON INPUTS

AND OUTPUTS

■ SYMMETRICAL OUTPUT IMPEDANCE:

|IOH|=IOL= 24mA (MIN) at VCC=3V

■ PCI BUS LEVELS GUARANTEED AT 24 mA

■ BALANCED PROPAGATION DELAYS:

t

≅ t

PLH

PHL

■ OPERATING VOLTAGE RANGE:

VCC(OPR) = 2.0V to 3.6V (1.5V Data
Retention)

■ PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 74

■ LATCH-UP PERFORMANCE EXCEEDS

500mA (JESD 17)

■ ESD PERFORMANCE:

HBM > 2000V (MIL STD 883 method 3015);
MM > 200V

DESCRIPTION

The 74LCX74 is a low voltage CMOS DUAL
D-TYPE FLIP FLOP WITH PRESET AND CLEAR
NON INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C2MOS
technology. It is ideal for low power and high
speed 3.3V applications; it can be interfaced to 5V
signal environment for inputs.

74LCX74

WITH 5V TOLERANT INPUTS

TSSOPSOP

ORDER CODES

PACKAGE TUBE T & R

SOP 74LCX74M 74LCX74MTR

TSSOP 74LCX74TTR

A signal on the D INPUT is transferred to the Q
OUTPUT duringthe positive going transition of the
clock pulse.
CLR and PR are independent of the clock and
accomplished by a low setting on the appropriate
input.
It has same speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

1/11September 2001

74VHC08

harman/kardon

AVR 347/230, AVR 350/230 Semiconductor Pinouts

Page 7 of 51

QUAD 2-INPUT AND GATE

■ HIGH SPEED: t

■ LOW POWER DISSIPATION:

I

= 2 µA (MAX.) at TA=25°C

CC

■ HIGH NOISE IMMUNITY:

V

= V

NIH

■ POWER DOWN PROTECTION ON INPUTS

■ SYMMETRICAL OUTPUT IMPEDANCE:

|I

| = IOL = 8mA (MIN)

OH

■ BALANCED PROPAGATION DELAYS:

t

≅ t

PLH

■ OPERATI N G VOLTAGE RANGE:

V

(OPR) = 2V to 5.5V

CC

■ PIN AND FUNCTION COMPATIBLE WITH

= 28% VCC (MIN.)

NIL

PHL

= 4.3 ns (TYP.) at VCC = 5V

PD

74 SERIES 08

■ IMPROVED LATCH-UP IMMUNITY

■ LOW NOISE: V

= 0.8V (MAX.)

OLP

DESCRIPTION

The 74VHC08 is a n advanced high-speed CM OS
QUAD 2-INPUT AND GATE fabricated with
sub-micron silicon gate and double-layer metal
wiring C

2

MOS technology.
The internal circuit is composed of 2 stages
including buffer ou tput, which provides high no ise
immunity and stable output.

TSSOPSOP

ORDER CODES

PACKAGE TUBE T & R

SOP 74VHC08M 74VHC08MTR

TSSOP 74VHC08TTR

Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against stat ic discharge, giving
them 2KV ESD immunity and transient excess
voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

June 2001

1

2

NC = NO CONNECT

V+

NC (OR V–)

V–

3

TOP

VIEW

QUANTITY

TEMPERATURE DRIFT – ppm/°C

0

–40

5

10

15

20

25

30

35

40

45

50

–30 –20 –10

0

10 20 30 40

QUANTITY

OUTPUT ERROR – mV

0

–10

50

100

150

200

250

300

–8 –6 –4 –2 0 2 4 10

68

1.2 V Micropower, Precision

harman/kardon

AVR 347/230, AVR 350/230 Semiconductor Pinouts

Page 8 of 51

a

FEATURES
Wide Operating Range: 50 mA–10 mA
Initial Accuracy: 60.1% max
Temperature Drift: 650 ppm/8C max
Output Impedance: 0.5 V max
Wideband Noise (10 Hz–10 kHz): 20 mV rms
Operating Temperature Range: –408C to +858C
High ESD Rating

4 kV Human Body Model
400 V Machine Model

Compact, Surface-Mount, SOT-23 Package

GENERAL DESCRIPTION

The AD1580 is a low cost, two-terminal (shunt), precision
bandgap reference. It provides an accurate 1.225 V output for
input currents between 50 µA and 10 mA.

The AD1580’s superior accuracy and stability is made possible
by the precise matching and thermal tracking of on-chip
components. Proprietary curvature correction design techniques
have been used to minimize the nonlinearities in the voltage
output temperature characteristics. The AD1580 is stable with
any value of capacitive load.

The low minimum operating current makes the AD1580 ideal
for use in battery powered 3 V or 5 V systems. However, the
wide operating current range means that the AD1580 is
extremely versatile and suitable for use in a wide variety of high
current applications.

The AD1580 is available in two grades, A and B, both of which
are provided in an SOT-23 package, the smallest surface mount
package available on the market. Both grades are specified over
the industrial temperature range of –40°C to +85°C.

Shunt Voltage Reference

AD1580

PIN CONFIGURATION

SOT-23 Package

Reverse Voltage Temperature Drift Distribution

TARGET APPLICATIONS

1. Portable, Battery-Powered Equipment:
Cellular Phones, Notebook Computers, PDAs, GPS and
DMM.

2. Computer Workstations
Suitable for use with a wide range of video RAMDACs.

3. Smart Industrial Transmitters

4. PCMCIA Cards.

5. Automotive.

6. 3 V/5 V 8–12-Bit Data Converters.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

Reverse Voltage Error Distribution

© Analog Devices, Inc., 1995

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] Fax: [phone]

ADV7322 Preliminary Technical Data

harman/kardon

AVR 347/230, AVR 350/230 Semiconductor Pinouts

Page 9 of 51

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

V

DD_IO

TEST0

TEST1

V

DGND

TEST2

TEST3

Y0

Y1

Y2

Y3

Y4

Y5

DD

Y6

Y7

C0

GND_IO63CLKIN_B62S761S660S559S458S357DGND56V

64

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

PIN 1

17C118C219

20

C

2

I

ALSB

DD

55S254S153S052

ADV7322

TOP VIEW

(Not to Scale)

21

22

23

24

25

26C327C428C529C630C731

SDA

SCLK

P_VSYNC

P_HSYNC

P_BLANK

Figure 19. Pin Configuration

TEST551TEST450S_HSYNC

S_VSYNC

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

CLKIN_A

RTC_SCR_TR

S_BLANK

R

SET1

V

REF

COMP1

DAC A

DAC B

DAC C

V

AA

AGND

DAC D

DAC E

DAC F

COMP2

R

SET2

EXT_LF

RESET

05067-019

Rev. PrA | Page 18 of 88

Preliminary Technical Data ADV7322

harman/kardon

AVR 347/230, AVR 350/230 Semiconductor Pinouts

Page 10 of 51

Table 6. Pin Function Descriptions

Mnemonic Input/Output Function

DGND G Digital Ground.
AGND G Analog Ground.
CLKIN_A I Pixel Clock Input for HD (74.25 MHz Only, PS Only (27 MHz), SD Only (27 MHz).
CLKIN_B I

COMP1,

O Compensation Pin for DACs. Connect 0.1 µF capacitor from COMP pin to V

COMP2
DAC A O CVBS/Green/Y/Y Analog Output.
DAC B O Chroma/Blue/U/Pb Analog Output.
DAC C O Luma/Red/V/Pr Analog Output.
DAC D O

DAC E O

DAC F O

P_HSYNC
P_VSYNC
P_BLANK
S_BLANK
S_HSYNC
S_VSYNC

I Video Horizontal Sync Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode.
I Video Vertical Sync Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode.
I Video Blanking Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode.
I/O Video Blanking Control Signal for SD Only.
I/O Video Horizontal Sync Control Signal for SD Only.
I/O Video Vertical Sync Control Signal for SD Only.

Y7 to Y0 I

C7 to C0 I

S7 to S0 I SD or Progressive Scan/HDTV Input Port for Cr [Red/V] data in 4:4:4 input mode. LSB is set up on Pin S0.
RESET

R

SET1

, R

SET2

I

I

SCLK I I2C Port Serial Interface Clock Input.
SDA I/O I2C Port Serial Data Input/Output.
ALSB I

V

P Power Supply for Digital Inputs and Outputs.

DD_IO

VDD P Digital Power Supply.
VAA P Analog Power Supply.
V

I/O Optional External Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).

REF

EXT_LF I External Loop Filter for the Internal PLL.
RTC_SCR_TR I Multifunctional Input. Real time control (RTC) input, timing reset input, subcarrier reset input.
I2C I This input pin must be tied high (V
GND_IO Digital Input/Output Ground.
TEST0 to

I Not used. Tie to DGND

TEST5

Pixel Clock Input. Requires a 27 MHz reference clock for progressive scan mode or a 74.25 MHz (74.1758
MHz) reference clock in HDTV mode. This clock is only used in dual modes.

.

AA

In SD Only Mode: CVBS/Green/Y Analog Output; in HD Only Mode and Simultaneous HD/SD Mode:
Y/Green [HD] Analog Output.

In SD Only Mode: Luma/Blue/U Analog Output; in HD Only Mode and Simultaneous HD/SD Mode: Pr/Red
Analog Output.

In SD Only Mode: Chroma/Red/V Analog Output; in HD Only Mode and Simultaneous HD/SD Mode:
Pb/Blue [HD] Analog Output.

SD or Progressive Scan/HDTV Input Port for Y Data. Input port for interleaved progressive scan data. The
LSB is set up on Pin Y0.

Progressive Scan/HDTV Input Port 4:4:4 Input Mode. This port is used for the Cb [Blue/U] data. The LSB is
set up on Pin C0.

This input resets the on-chip timing generator and sets the ADV7322 into default register setting.

RESET

an active low signal.
A 3040 Ω resistor must be connected from this pin to AGND and is used to control the amplitudes of the

DAC outputs.

2

TTL Address Input. This signal sets up the LSB of the I
activated, which reduces noise on the I

2

C interface.

) for the ADV7322 to interface over the I2C port.

DD_IO

C address. When this pin is tied low, the I2C filter is

is

Rev. PrA | Page 19 of 88

Features

harman/kardon

AVR 347/230, AVR 350/230 Semiconductor Pinouts

Page 11 of 51

• Low-voltage and Standard-voltage Operation

– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (V

• Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K),

1024 x 8 (8K) or 2048 x 8 (16K)

• Two-wire Serial Interface

• Schmitt Trigger, Filtered Inputs for Noise Suppression

• Bidirectional Data Transfer Protocol

• 100 kHz (1.8V) and 400 kHz (2.7V, 5V) Compatibility

• Write Protect Pin for Hardware Data Protection

• 8-byte Page (1K, 2K), 16-byte Page (4K, 8K, 16K) Write Modes

• Partial Page Writes Allowed

• Self-timed Write Cycle (5 ms max)

• High-reliability

– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years

• Automotive Grade and Lead-free/Halogen-free Devices Available

• 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead MAP, 5-lead SOT23,

8-lead TSSOP and 8-ball dBGA2 Packages

• Die Sales: Wafer Form, Waffle Pack and Bumped Wafers

= 1.8V to 5.5V)

CC

Two-wire
Serial EEPROM

1K (128 x 8)

2K (256 x 8)

4K (512 x 8)

8K (1024 x 8)

Description

The AT24C01A/02/04/08A/16A provides 1024/2048/4096/8192/16384 bits of serial
electrically erasable and programmable read-only memory (EEPROM) organized as
128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in many
industrial and commercial applications where low-power and low-voltage operation
are essential. The AT24C01A/02/04/08A/16A is available in space-saving 8-lead PDIP,
8-lead JEDEC SOIC, 8-lead MAP, 5-lead SOT23 (AT24C01A/AT24C02/AT24C04), 8­lead TSSOP, and 8-ball dBGA2 packages and is accessed via a Two-wire serial inter­face. In addition, the entire family is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to

5.5V) versions.

Table 1. Pin Configuration

Pin Name Function

A0 - A2 Address Inputs

SDA Serial Data

SCL Serial Clock Input

WP Write Protect

NC No Connect

GND Ground

VCC Power Supply

8-lead TSSOP

A0
A1
A2

GND

8-ball dBGA2

VCC

WP
SCL
SDA

Bottom View

8-lead PDIP

1
2
3
4

8

VCC

7

WP

6

SCL

5

SDA

GND

1

8
7
6
5

A0

2

A1

3

A2

4

GND

A0
A1
A2

8-lead MAP

VCC

8

WP

7

SCL

6

SDA

5

Bottom View

5-lead SOT23

8-lead SOIC

1
2
3
4

1
2
3
4

8
7
6
5

A0
A1
A2
GND

VCC
WP
SCL
SDA

16K (2048 x 8)

AT24C01A
AT24C02
AT24C04
AT24C08A
AT24C16A

A0
A1
A2

GND

1
2
3
4

8

VCC

7

WP

6

SCL

5

SDA

GND

SCL

SDA

1

2

3

WP

5

VCC

4

0180V–SEEPR–8/05

1

2. PIN DESCRIPTIONS

T

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AVR 347/230, AVR 350/230 Semiconductor Pinouts

Page 12 of 51

CS42528

CX_SDIN1

CX_SCLK

CX_LRCK

VD

DGND

VLC

SCL/CCLK

SDA/CDOUT

AD1/CDIN

AD0/CS

INT

RST

AINR-

AINR+

AINL+

AINL-

CX_SDIN2

CX_SDIN4

CX_SDIN3

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

1

2

3

4

5
6

7

8

9
10

11

12

13
14

15

16

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

VQ

FILT+

REFGND

OMCK

SAI_SCLK

SAI_LRCK

CS42528

VA

AOUTB4-

AOUTA4-

AOUTB4+

AOUTA4+

AGND

AOUTB3-

AOUTB3+

AOUTA3+

VLS

SAI_SDOU

RMCK

CX_SDOUT

ADCIN2

ADCIN1

DGND

AOUTA3-

VD

AOUTB2-

TXP

AOUTB2+

RXP0

AOUTA2+

48

47

46
45

44
43

42

41

40
39

38

37

36
35

34

33

RXP1/GPO1

RXP2/GPO2

RXP3/GPO3
RXP4/GPO4

RXP5/GPO5
RXP6/GPO6

RXP7/GPO7

VARX

AGND

LPFLT

MUTEC

AOUTA1-

AOUTA1+
AOUTB1+

AOUTB1-

AOUTA2-

Pin Name # Pin Description

CX_SDIN1
CX_SDIN2
CX_SDIN3
CX_SDIN4

CX_SCLK 2 CODEC Serial Clock (Input/Output) - Serial clock for the CODEC serial audio interface.
CX_LRCK 3 CODEC Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on

VD 451Digital Power (Input) - Positive power supply for the digital section.

DGND 552Digital Ground (Input) - Ground reference. Should be connected to digital ground.

VLC 6
SCL/CCLK 7 Serial Control Port Clock (Input) - Serial clock for the serial control port. Requires an external pull-up

SDA/CDOUT 8 Serial Control Data (Input/Output) - SDA is a data I/O line in I

AD1/CDIN 9 Address Bit 1 (I2C)/Serial Control Data (SPI) (Input) - AD1 is a chip address pin in I

1

Codec Serial Audio Data Input (Input) - Input for two’s complement serial audio data.

64
63
62

the CODEC serial audio data line.

Control Port Power (Input) - Determines the required signal level for the control port.

resistor to the logic interface voltage in I

2

C mode as shown in the Typical Connection Diagram.

2

C mode and requires an external pull-up
resistor to the logic interface voltage, as shown in the Typical Connection Diagram. CDOUT is the output
data line for the control port interface in SPI mode.

2

C mode; CDIN is

the input data line for the control port interface in SPI mode.

CS42528

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AVR 347/230, AVR 350/230 Semiconductor Pinouts

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10

Address Bit 0 (I2C)/Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I

2

C mode; CS

is the chip select signal in SPI mode.

INT 11 Interrupt (Output) - The CS42528 will generate an interrupt condition as per the Interrupt Mask register.

See “Interrupts” on page 40 for more details.

RST 12 Reset (Input) - The device enters a low power mode and all internal registers are reset to their default

settings when low.

AINR­AINR+

AINL+
AINL-

VQ 17 Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage.
FILT+ 18 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
REFGND 19 Reference Ground (Input) - Ground reference for the internal sampling circuits.
AOUT A1 +,-

AOUTB1 +,­AOUT A2 +,­AOUTB2 +,­AOUT A3 +,­AOUTB3 +,­AOUT A4 +,­AOUTB4 +,-

VA
VARX

AGND 2540Analog Ground (Input) - Ground reference. Should be connected to analog ground.

13

Differential Right Channel Analog Input (Input) - Signals are presented differentially to the delta-sigma

14

modulators via the AINR+/- pins.

15

Differential Left Channel Analog Input (Input) - Signals are presented differentially to the delta-sigma

16

modulators via the AINL+/- pins.

36,37

Differential Analog Output (Output) - The full-scale differential analog output level is specified in the

35,34

Analog Characteristics specification table.
32,33
31,30
28,29
27,26
22,23
21,20

24

Analog Power (Input) - Positive power supply for the analog section.

41

MUTEC 38 Mute Control (Out put) - The Mute Control pin outputs high impedance following an initial power-on con-

dition or whenever the PDN bit is set to a ‘1’, forcing the codec into power-down mode. The signal will

remain in a high impedance state as long as the part is in power-down mode. The Mute Control pin goes

to the selected “active” state during reset, muting, or if the master clock to left/right clock frequency ratio

is incorrect. This pin is intended to be used as a control for external mute circuits to prevent the clicks

and pops that can occur in any single supply system. The use of external mute circuits are not manda-

tory but may be desired for designs requiring the absolute minimum in extraneous clicks and pops.

LPFLT 39 PLL Loop Filter (Output) - An RC network should be connected between this pin and ground.
RXP7/GPO7

RXP6/GPO6
RXP5/GPO5
RXP4/GPO4
RXP3/GPO3
RXP2/GPO2
RXP1/GPO1

RXP0 49 S/PDIF Receiver Input (Input) - Dedicated receiver input for S/PDIF encoded data.
TXP 50 S/PDIF Transmitter Output (Output) - S/PDIF encoded data output, mapped directly from one of the

42

S/PDIF Receiver Input/ General Purpose Output (Input/Output) - Receiver inputs for S/PDIF encoded

43

data. The CS42528 has an internal 8:2 multiplexer to select the active receiver port, according to the

44

Receiver Mode Control 2 register. These pins can also be configured as general purpose output pins,

45

ADC Overflow indicators or Mute Control outputs according to the RXP/General Purpose Pin Control

46

registers.

47
48

receiver inputs as indicated by the Receiver Mode Control 2 register.

VLS 53 Serial Port Interface Power (Input) - Determines the required signal level for the serial port interfaces.

SAI_SDOUT

54 Serial Audio Interface Serial Data Output (Output) - Output for two’s complement serial audio PCM

data from the S/PDIF incoming stream. This pin can also be configured to transmit the output of the inter-

nal and external ADCs.

RMCK 55 Recovered Master Clock (Output) - Recovered master clock output from the External Clock Reference

(OMCK, pin 59) or the PLL which is locked to the incoming S/PDIF stream or CX_LRCK.

CS42528

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AVR 347/230, AVR 350/230 Semiconductor Pinouts

Page 14 of 51

CX_SDOUT 56 CODEC Serial Dat a Output (Output) - Output for two’s complement serial audio data from the internal

and external ADCs.

ADCIN1
ADCIN2

OMCK 59 External Reference Clock (Input) - External clock reference that must be within the ranges specified in

SAI_LRCK 60 Serial Audio Interface Left/Right Clock (Input/Output) - Determines which channel, Left or Right, is

SAI_SCLK 61 Serial Audio Interface Serial Clock (Input/Output) - Serial clock for the Serial Audio Interface.

58

External ADC Serial Input (Input) - The CS42528 provides for up to two external stereo analog to digital

57

converter inputs to provide a maximum of six channels on one serial data output line when the CS42528
is placed in One Line mode.

the register “OMCK Frequency (OMCK Freqx)” on page 54.

currently active on the serial audio data line.

3. TYPICAL CONNECTION DIAGRAM

harman/kardon

AVR 347/230, AVR 350/230 Semiconductor Pinouts

Page 15 of 51

CS42528

+3.3 V to +5 V

+2.5 V

to +5 V

+1.8 V

to +5 V

** Resistors are required for

2

I

+

10 µF

+

10 µF

Driver

S/PDIF

Interface

Up to 8

Sources

CS5361

A/D Converter

CS5361

A/D Converter

Digital Audio

Processor

Micro-

Controller

C control port operation

0.1 µF 0.01 µF

0.1 µF

OSC

** **

2 kΩ 2 kΩ

0.01 µF

0.1 µF

0.1 µF

VD
50
49
48
47
46
45
44
43
42

53

59

58

57

55

RMCK

54
60
61

3

2

56

1

64
63
62

11
12

7
8

9

10

6

4

TXP
RXP0
RXP1/GPO1
RXP2/GPO2
RXP3/GPO3
RXP4/GPO4
RXP5/GPO5
RXP6/GPO6
RXP7/GPO7

VLS

OMCK

ADCIN1

ADCIN2

51

CS42528

SAI_SDOUT
SAI_LRCK

SAI_SCLK

CX_LRCK

CX_SCLK

CX_SDOUT
CX_SDIN1

CX_SDIN2
CX_SDIN3
CX_SDIN4

INT
RST
SCL/CCLK
SDA/CDOUT

AD1/CDIN
AD0/CS

VLC

DGND

DGND

5

52 40

25

41

VAVD

24

VA

AOUTA1+

AOUTA1-

AOUTB1+

AOUTB1-

AOUTA2+

AOUTA2-

AOUTB2+

AOUTB2-

AOUTA3+

AOUTA3-

AOUTB3+

AOUTB3-

AOUTA4+

AOUTA4-

AOUTB4+

AOUTB4-

MUTEC

AINL+

AINL-

AINR+

AINR-

VQ

FILT+

REFGND

LPFLT

AGNDAGND

0.01 µF

0.01 µF

36
37

35
34

32
33

31
30

28
29

27
26

22
23

21
20

+VA

38

15

16

14

13

17

18

19

39

*

*

0.1 µF

RFILT

CFILT

0.1 µF

+

10 µF

0.1 µF

+

10 µF

Analog Output Buffer

and

Mute Circuit (optional)

Analog Output Buffer

and

Mute Circuit (optional)

Analog Output Buffer

and

Mute Circuit (optional)

Analog Output Buffer

and

Mute Circuit (optional)

Analog Output Buffer

and

Mute Circuit (optional)

Analog Output Buffer

and

Mute Circuit (optional)

Analog Output Buffer

and

Mute Circuit (optional)

Analog Output Buffer

and

Mute Circuit (optional)

Mute
Drive

(optional)

Analog

2700 pF*

Input

1

Buffer

Analog

Input

2700 pF*

1

Buffer

+

3

3

100 µF

CRIP

0.1 µF

3

+5 V

2

2

2

2

2

2

2

2

* Pull up or down as

required on startup if the

Mute Control is used.

Left Analog Input

Right Analog Inpu

+

4.7 µF

1. See the ADC Input Filter section in the Appendix.

2. See the DAC Output Filter section in the Appendix.

3. See the PLL Filter section in the Appendix.

20 DS586PP5

Connect DGND and AGND at single point near Codec

Figure 5. Typical Connection Diagram

harman/kardon

AVR 347/230, AVR 350/230 Semiconductor Pinouts

Page 16 of 51