Datasheet S6B0719 Datasheet (Samsung)

S6B0719

permission of LCD Driver IC Team.

160 SEG / 105 COM SEG DRIVER & CONTROLLER FOR STN LCD

Contents in this document are subject to change without notice. No part of this document may be reproduced or
transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written

Jan. 2000.

Ver. 0.4

Prepared by: Koo-Hyung, Jung

[e-mail]

160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.4 S6B0719

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S6B0719 Specification Revision History

Version Content Date

0.0 - Original Feb.1999

0.1

0.2

- Append pad center coordinate (refer to table 2)

- Append display data RAM map (refer to figure 8)

- Modify display data RAM map (refer to figure 8)

Mar.1999

May.1999

- Append reference circuit examples (refer to page 22)

- Change the low power consumption V0 = 13V -> 15V (refer to page 1)

Modify page address circuit description ; DB3, DB2 and DB1 are “H”, but

DB1 is “L” -> DB3, DB2 and DB0 are “H”, but DB1 is “L” (refer to page 20)

0.3

- Modify set partial display duty ratio (refer to page 27)

Jun.1999

Add partial duty changing “waiting for discharging the LCD power levels

(refer to figure 34)

Change the condition of power consumption : (VDD = 3V, x6 boosting, V0 =

15V) → (VDD = 3V, x5 boosting, V0 = 13V) (refer to page 1)

Change the absolute maximum ratings of V0 and VOUT : 20V → 17V (refer

to page 50)

0.4

Change the operating voltage of V0 and VOUT : 17V → 15V (refer to page 1

Jan.2000

and 51)

Change the operating voltage of VDD : (2.4 to 5.5V) → (2.4 to 3.6V) (refer to

page 1 and 51)

- Modify Figure20 (refer to page 24)

2

S6B0719 PRELIMINARY SPEC. VER. 0.4 160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD

CO

NTENTS

INTRODUCTION ..................................................................................................................................................1

BLOCK DIAGRAM...............................................................................................................................................2

PAD CONFIGURATION .......................................................................................................................................3

PAD CENTER COORDINATES ............................................................................................................................4

PIN DESCRIPTION ..............................................................................................................................................6

FUNCTIONAL DESCRIPTION............................................................................................................................ 11

MICROPROCESSOR INTERFACE.............................................................................................................11

DISPLAY DATA RAM (DDRAM)..................................................................................................................14

LCD DISPLAY CIRCUITS............................................................................................................................17

LCD DRIVER CIRCUIT ...............................................................................................................................19

POWER SUPPLY CIRCUITS ......................................................................................................................21

REFERENCE CIRCUIT EXAMPLES ...........................................................................................................26

RESET CIRCUIT.........................................................................................................................................28

INSTRUCTION DESCRIPTION...........................................................................................................................29

SPECIFICATIONS..............................................................................................................................................50

ABSOLUTE MAXIMUM RATINGS...............................................................................................................50

DC CHARACTERISTICS .............................................................................................................................51

AC CHARACTERISTICS............................................................................................................................. 55

REFERENCE APPLICATIONS........................................................................................................................... 59

MICROPROCESSOR INTERFACE.............................................................................................................59

CONNECTIONS BETWEEN S6B0719 AND LCD PANEL............................................................................ 60

3

S6B0719 PRELIMINARY SPEC. VER. 0.4 160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD

INTRODUCTION

The S6B0719 is a driver & controller LSI for graphic dot-matrix liquid crystal display systems. It contains 105
common and 160 segment driver circuits. This chip is connected directly to a microprocessor, accepts serial or 8­bit parallel display data and stores in an on-chip display data RAM of 105 x 160 bits. It provides a highly flexible
display section due to 1-to-1 correspondence between on-chip display data RAM bits and LCD panel pixels. And it
performs display data RAM read/write operation with no external-operating clock to minimize power consumption.
In addition, because it contains power supply circuits necessary to drive liquid crystal, it is possible to make a
display system with the fewest components.

FEATURES

Driver Output Circuits

− 105 common outputs / 160 segment outputs

Applicable Duty-ratios

Programmable duty ratio Applicable LCD bias Maximum display area

1/9 to 1/105 1/4 to 1/11

− Various partial display

− Partial window moving & data scrolling

On-chip Display Data RAM

105 × 160

− Capacity: 105 x 160 = 16,800 bits

− Bit data "1": a dot of display is illuminated

− Bit data "0": a dot of display is not illuminated

Microprocessor Interface

− 8-bit parallel bi-directional interface with 6800-series or 8080-series

− Serial interface (only write operation) available

On-chip Low Power Analog Circuit

− On-chip oscillator circuit

− Voltage converter (x3, x4, x5 or x6)

− Voltage regulator (temperature coefficient: -0.05%/°C or external input)

− On-chip electronic contrast control function (64 steps)

− Voltage follower (LCD bias: 1/4 to 1/11)

Operating Voltage Range

− Supply voltage (VDD): 2.4 to 3.6 V

− LCD driving voltage (VLCD = V0 - VSS): 4.0 to 15.0 V

Low Power Consumption

− TBD µΑ Typ. (VDD = 3V, x6 boosting, V0 = 13V, Internal power supply ON and display OFF)

− TBD µΑ Max. (during power save [standby] mode )

Package Type

− Gold bumped chip or TCP

1

160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.4 S6B0719

DB0

DB1

COMS

COM

3

:

:

:

7

:

:

BLOCK DIAGRAM

VDD

V0
V1
V2
V3
V4

VSS

HPMB

V0

VR

INTRS

VEXT

REF

VOUT

V/F

CIRCUIT

V/R

RCIRCUIT

PAGE

ADDRESS

CIRCUIT

SEG2

SEG1

SEG0

160 SEGMENT

DRIVER CIRCUITS

SEGMENT CONTROLLER

DISPLAY DATA RAM

105 X 160 = 16,800 Bits

COLUMN ADDRESS

CIRCUIT

SEG159SEG158SEG15

COMS

COM0

106 COMMON

DRIVER CIRCUITS

COMMON CONTROLLER

DISPLAY

LINE

ADDRESS

CIRCUIT

TIMING

GENERATOR

CIRCUIT

STATIC

DRIVER

OSCILLATOR

10

MS
CL
SYNC
M

FRS
FR

C1-

C1+

C2­C2+
C3+
C4+
C5+

VCI

V/C

CIRCUIT

INSTRUCTION DECODER & REGISTER

MPU INTERFACE (PARALLEL & SERIAL)

RW_WR

E_RD

RS

CS2

CS1B

PS

C68

RESETB

Figure 1. Block Diagram

STATUS REGISTERBUS HOLDER

DB5

DB6(SCLK)

DB7(SID)

DB4

DB3

DB2

2

S6B0719 PRELIMINARY SPEC. VER. 0.4 160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD

167

330

166

331

137

360

136

1

ðððð

- - - -

ðððð

ðððð

- - - -

ðððð

*2

*1

*3

PAD CONFIGURATION

рр ррррррррррррррррррр

- - - - - - - - - -

Y

S6B0719

(TOP VIEW)

(0,0) X

ррррррррррррррррррр

ðð

рррррррррррррррррррррр

- - - - - - - - - -

ррррррррррррррррррррррр

Figure 2. S6B0719 Chip Configuration

Table 1. S6B0719 Pad Dimensions

Size

Item Pad No.

X Y

Chip size - 9370 2220

29 to 108 70 (Min.)

Pad pitch

1 to 28, 109 to 136,

137 to 360

54 (Min.)

30 to 107 60 78

138 to 165, 332 to 359 78 44

Bumped

`pad size

3 to 27, 110 to 134

169 to 328

1, 2, 28, 29, 108, 109,

135, 136, 167, 168, 329

44 78

70 78

and 330

137, 166, 331 and 360 78 70

Bumped pad

height

30 um 30 um 30 um

1 to 360 14 (Typ.)

42 um 108 um

Unit

µm

42 um108 um

30 um 30 um 30 um

(-4033.05,-374.4)

*1 : COG Align Key *3 : ILB Align Key 2

(-3131.6,622.75)

*2 : ILB Align Key 1

42 um 108 um

42 um 108 um

(4135.6,-633.0)

3

160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.4 S6B0719

PAD CENTER COORDINATES

Table 2. Pad Center Coordinates

[Unit: µm]

NO NAME X Y NO NAME X Y NO NAME X Y NO NAME X Y

1 DUMMY -4453 -985 51 RW_WR -1225 -985 101 VR 2275 -985 151 COM13 4560 -27
2 DUMMY -4373 -985 52 E_RD -1155 -985 102 VSS 2345 -985 152 COM12 4560 27
3 COM80 -4293 -985 53 VDD -1085 -985 103 REF 2415 -985 153 COM11 4560 81
4 COM81 -4239 -985 54 DB0 -1015 -985 104 VEXT 2485 -985 154 COM10 4560 135
5 COM82 -4185 -985 55 DB1 -945 -985 105 VDD 2555 -985 155 COM9 4560 189
6 COM83 -4131 -985 56 DB2 -875 -985 106 INTRS 2625 -985 156 COM8 4560 243
7 COM84 -4077 -985 57 DB3 -805 -985 107 VSS 2695 -985 157 COM7 4560 297
8 COM85 -4023 -985 58 DB4 -735 -985 108 DUMMY 2775 -985 158 COM6 4560 351

9 COM86 -3969 -985 59 DB5 -665 -985 109 DUMMY 2917 -985 159 COM5 4560 405
10 COM87 -3915 -985 60 DB6 -595 -985 110 COM51 2997 -985 160 COM4 4560 459
11 COM88 -3861 -985 61 DB7 -525 -985 111 COM50 3051 -985 161 COM3 4560 513
12 COM89 -3807 -985 62 VDD -455 -985 112 COM49 3105 -985 162 COM2 4560 567
13 COM90 -3753 -985 63 VDD -385 -985 113 COM48 3159 -985 163 COM1 4560 621
14 COM91 -3699 -985 64 VDD -315 -985 114 COM47 3213 -985 164 COM0 4560 675
15 COM92 -3645 -985 65 VDD -245 -985 115 COM46 3267 -985 165 COMS 4560 729
16 COM93 -3591 -985 66 VCI -175 -985 116 COM45 3321 -985 166 DUMMY 4560 809
17 COM94 -3537 -985 67 VCI -105 -985 117 COM44 3375 -985 167 DUMMY 4453 985
18 COM95 -3483 -985 68 VSS -35 -985 118 COM43 3429 -985 168 DUMMY 4373 985
19 COM96 -3429 -985 69 VSS 35 -985 119 COM42 3483 -985 169 SEG0 4293 985
20 COM97 -3375 -985 70 VSS 105 -985 120 COM41 3537 -985 170 SEG1 4239 985
21 COM98 -3321 -985 71 VSS 175 -985 121 COM40 3591 -985 171 SEG2 4185 985
22 COM99 -3267 -985 72 VOUT 245 -985 122 COM39 3645 -985 172 SEG3 4131 985
23 COM100 -3213 -985 73 VOUT 315 -985 123 COM38 3699 -985 173 SEG4 4077 985
24 COM101 -3159 -985 74 C5+ 385 -985 124 COM37 3753 -985 174 SEG5 4023 985
25 COM102 -3105 -985 75 C5+ 455 -985 125 COM36 3807 -985 175 SEG6 3969 985
26 COM103 -3051 -985 76 C3+ 525 -985 126 COM35 3861 -985 176 SEG7 3915 985
27 COMS -2997 -985 77 C3+ 595 -985 127 COM34 3915 -985 177 SEG8 3861 985
28 DUMMY -2917 -985 78 C1- 665 -985 128 COM33 3969 -985 178 SEG9 3807 985
29 DUMMY -2775 -985 79 C1- 735 -985 129 COM32 4023 -985 179 SEG10 3753 985
30 FRS -2695 -985 80 C1+ 805 -985 130 COM31 4077 -985 180 SEG11 3699 985
31 FR -2625 -985 81 C1+ 875 -985 131 COM30 4131 -985 181 SEG12 3645 985
32 TEST1 -2555 -985 82 C2+ 945 -985 132 COM29 4185 -985 182 SEG13 3591 985
33 TEST2 -2485 -985 83 C2+ 1015 -985 133 COM28 4239 -985 183 SEG14 3537 985
34 TEST3 -2415 -985 84 C2- 1085 -985 134 COM27 4293 -985 184 SEG15 3483 985
35 CL -2345 -985 85 C2- 1155 -985 135 DUMMY 4373 -985 185 SEG16 3429 985
36 M -2275 -985 86 C4+ 1225 -985 136 DUMMY 4453 -985 186 SEG17 3375 985
37 SYNC -2205 -985 87 C4+ 1295 -985 137 DUMMY 4560 -809 187 SEG18 3321 985
38 VSS -2135 -985 88 VSS 1365 -985 138 COM26 4560 -729 188 SEG19 3267 985
39 HPMB -2065 -985 89 VSS 1435 -985 139 COM25 4560 -675 189 SEG20 3213 985
40 MS -1995 -985 90 V4 1505 -985 140 COM24 4560 -621 190 SEG21 3159 985
41 VDD -1925 -985 91 V4 1575 -985 141 COM23 4560 -567 191 SEG22 3105 985
42 PS -1855 -985 92 V3 1645 -985 142 COM22 4560 -513 192 SEG23 3051 985
43 C68 -1785 -985 93 V3 1715 -985 143 COM21 4560 -459 193 SEG24 2997 985
44 VSS -1715 -985 94 V2 1785 -985 144 COM20 4560 -405 194 SEG25 2943 985
45 CS1B -1645 -985 95 V2 1855 -985 145 COM19 4560 -351 195 SEG26 2889 985
46 CS2 -1575 -985 96 V1 1925 -985 146 COM18 4560 -297 196 SEG27 2835 985
47 VDD -1505 -985 97 V1 1995 -985 147 COM17 4560 -243 197 SEG28 2781 985
48 RESETB -1435 -985 98 V0 2065 -985 148 COM16 4560 -189 198 SEG29 2727 985
49

RS

50

VSS

-1365 -985 99 V0 2135 -985 149 COM15 4560 -135 199 SEG30 2673 985

-1295 -985 100 VR 2205 -985 150 COM14 4560 -81 200 SEG31 2619 985

4

S6B0719 PRELIMINARY SPEC. VER. 0.4 160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD

Table 2 (Continued)

[Unit: µm]

NO NAME X Y NO NAME X Y NO NAME X Y NO NAME X Y

201 SEG32 2565 985 251 SEG82 -135 985 301 SEG132 -2835 985 351 COM71 -4560 -297
202 SEG33 2511 985 252 SEG83 -189 985 302 SEG133 -2889 985 352 COM72 -4560 -351
203 SEG34 2457 985 253 SEG84 -243 985 303 SEG134 -2943 985 353 COM73 -4560 -405
204 SEG35 2403 985 254 SEG85 -297 985 304 SEG135 -2997 985 354 COM74 -4560 -459
205 SEG36 2349 985 255 SEG86 -351 985 305 SEG136 -3051 985 355 COM75 -4560 -513
206 SEG37 2295 985 256 SEG87 -405 985 306 SEG137 -3105 985 356 COM76 -4560 -567
207 SEG38 2241 985 257 SEG88 -459 985 307 SEG138 -3159 985 357 COM77 -4560 -621
208 SEG39 2187 985 258 SEG89 -513 985 308 SEG139 -3213 985 358 COM78 -4560 -675
209 SEG40 2133 985 259 SEG90 -567 985 309 SEG140 -3267 985 359 COM79 -4560 -729
210 SEG41 2079 985 260 SEG91 -621 985 310 SEG141 -3321 985 360 DUMMY -4560 -809
211 SEG42 2025 985 261 SEG92 -675 985 311 SEG142 -3375 985
212 SEG43 1971 985 262 SEG93 -729 985 312 SEG143 -3429 985
213 SEG44 1917 985 263 SEG94 -783 985 313 SEG144 -3483 985
214 SEG45 1863 985 264 SEG95 -837 985 314 SEG145 -3537 985
215 SEG46 1809 985 265 SEG96 -891 985 315 SEG146 -3591 985
216 SEG47 1755 985 266 SEG97 -945 985 316 SEG147 -3645 985
217 SEG48 1701 985 267 SEG98 -999 985 317 SEG148 -3699 985
218 SEG49 1647 985 268 SEG99 -1053 985 318 SEG149 -3753 985
219 SEG50 1593 985 269 SEG100 -1107 985 319 SEG150 -3807 985
220 SEG51 1539 985 270 SEG101 -1161 985 320 SEG151 -3861 985
221 SEG52 1485 985 271 SEG102 -1215 985 321 SEG152 -3915 985
222 SEG53 1431 985 272 SEG103 -1269 985 322 SEG153 -3969 985
223 SEG54 1377 985 273 SEG104 -1323 985 323 SEG154 -4023 985
224 SEG55 1323 985 274 SEG105 -1377 985 324 SEG155 -4077 985
225 SEG56 1269 985 275 SEG106 -1431 985 325 SEG156 -4131 985
226 SEG57 1215 985 276 SEG107 -1485 985 326 SEG157 -4185 985
227 SEG58 1161 985 277 SEG108 -1539 985 327 SEG158 -4239 985
228 SEG59 1107 985 278 SEG109 -1593 985 328 SEG159 -4293 985
229 SEG60 1053 985 279 SEG110 -1647 985 329 DUMMY -4373 985
230 SEG61 999 985 280 SEG111 -1701 985 330 DUMMY -4453 985
231 SEG62 945 985 281 SEG112 -1755 985 331 DUMMY -4560 809
232 SEG63 891 985 282 SEG113 -1809 985 332 COM52 -4560 729
233 SEG64 837 985 283 SEG114 -1863 985 333 COM53 -4560 675
234 SEG65 783 985 284 SEG115 -1917 985 334 COM54 -4560 621
235 SEG66 729 985 285 SEG116 -1971 985 335 COM55 -4560 567
236 SEG67 675 985 286 SEG117 -2025 985 336 COM56 -4560 513
237 SEG68 621 985 287 SEG118 -2079 985 337 COM57 -4560 459
238 SEG69 567 985 288 SEG119 -2133 985 338 COM58 -4560 405
239 SEG70 513 985 289 SEG120 -2187 985 339 COM59 -4560 351
240 SEG71 459 985 290 SEG121 -2241 985 340 COM60 -4560 297
241 SEG72 405 985 291 SEG122 -2295 985 341 COM61 -4560 243
242 SEG73 351 985 292 SEG123 -2349 985 342 COM62 -4560 189
243 SEG74 297 985 293 SEG124 -2403 985 343 COM63 -4560 135
244 SEG75 243 985 294 SEG125 -2457 985 344 COM64 -4560 81
245 SEG76 189 985 295 SEG126 -2511 985 345 COM65 -4560 27
246 SEG77 135 985 296 SEG127 -2565 985 346 COM66 -4560 -27
247 SEG78 81 985 297 SEG128 -2619 985 347 COM67 -4560 -81
248 SEG79 27 985 298 SEG129 -2673 985 348 COM68 -4560 -135
249 SEG80 -27 985 299 SEG130 -2727 985 349 COM69 -4560 -189
250 SEG81 -81 985 300 SEG131 -2781 985 350 COM70 -4560 -243

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160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.4 S6B0719

PIN DESCRIPTION

Table 3. Power Supply Pins

Name I/O Description

VDD Supply Power supply

Vss Supply Ground

LCD drivers supply voltages
The voltage determined by LCD pixel is impedance-converted by an operational amplifier

V0
V1
V2
V3
V4

I/O

for application.
Voltages should have the following relationship: V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ Vss
When the internal power circuit is active, these voltages are generated as following table
according to the state of LCD bias.

LCD bias V1 V2 V3 V4

1/N bias (N-1)/N x V0 (N-2)/N x V0 2/N x V0 1/N x V0

NOTE : *N = 4 to 11

Table 4. LCD Driver Supply Pins

Name I/O Description

C1-, C2- I/O Capacitor negative connection pins for voltage converter

C1+, C2+
C3+, C4+

C5+

VOUT I/O Voltage converter input/output pin

VCI I

VR I

REF I

VEXT I

I/O Capacitor positive connection pins for voltage converter

Voltage converter input voltage pin
Voltages should have the following relationship: VDD ≤ VCI ≤ V0

V0 voltage adjustment pin
It is valid only when on-chip resistors are not used. (INTRS = “L”)

Selects the external VREF voltage via VEXT pin

− REF = "L": using the external VREF

− REF = "H": using the internal VREF

Externally input reference voltage (VREF) for the internal voltage regulator.
It is valid only when REF is “L”.

6

S6B0719 PRELIMINARY SPEC. VER. 0.4 160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD

Table 5. System Control Pins

Name I/O Description

Master / Slave operations select pin

− MS = "H": master operation

− MS = "L": slave operation

The following table depends on the MS status.

MS I

CL I/O

SYNC I/O

M I/O

FR O

FRS O

INTRS I

HPMB I

TEST1

to

TEST3

MS

Internal analog circuits Display timing signals

Oscillator Power supply CL SYNC M

H Enabled Enabled Output Output Output

L Disabled Disabled Input Input Input

Display clock input / output pin
When the S6B0719 is used in master / slave mode (multi-chip), the CL pins must be
connected each other.

Display sync input / output pin
When the S6B0719 is used in master/slave mode (multi-chip), the SYNC pins must be
connected each other.

LCD AC input / output pin
When the S6B0719 is used in master/slave mode (multi-chip), the M pins must be
connected each other.

Static driver common output pin
This pin is used together with the FRS pin.

Static driver segment output pin
This pin is used together with the FR pin.

Internal resistors select pin
This pin selects the resistors for adjusting V0 voltage level.

− INTRS = "H”: use the internal resistors.

− INTRS = "L”: use the external resistors. VR pin and external resistive divider control V0

voltage.
Power control pin of the power supplies circuit for LCD driver

− HPMB = "L": high power mode

− HPMB = "H": normal mode

This pin is valid in master operation.
Test pins

I

Don’ t use these pins.

NOTE: DUMMY – These pins should be opened (floated).

7

160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.4 S6B0719

Table 6. Microprocessor Interface Pins

Name I/O Description

RESETB I

PS I

C68 I

CS1B

CS2

RS I

RW_WR I

Reset input pin
When RESETB is “L”, initialization is executed.

Parallel / Serial data input select input

PS Interface

mode

H Parallel RS DB0 to DB7

Data /

instruction

Data Read / Write Serial clock

E_RD

RW_WR

L Serial RS SID (DB7) Write only SCLK (DB6)

*NOTE: When PS is “L”, DB0 to DB5 are high impedance and E_RD and RW_WR
must be fixed to either “H” or “L”.

Microprocessor interface select input pin

− C68 = "H": 6800-series MPU interface

− C68 = "L": 8080-series MPU interface

Chip select input pins
Data / instruction I/O is enabled only when CS1B is “L” and CS2 is “H”.

I

When chip select is non-active, DB0 to DB7 may be high impedance.
Register select input pin

− RS = "H": DB0 to DB7 are display data

− RS = "L": DB0 to DB7 are control data

Read / Write execution control pin

C68 MPU Type RW_WR Description

Read/Write control input pin

H 6800-series RW

− RW = “H”: read

− RW = “L”: write

Write enable clock input pin

L 8080-series /WR

The data on DB0 to DB7 are latched at the rising
edge of the /WR signal.

-

8

S6B0719 PRELIMINARY SPEC. VER. 0.4 160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD

Table 6. (Continued)

Name I/O Description

Read / Write execution control pin

C68 MPU Type E_RD Description

Read / Write control input pin

− RW = “H”: When E is “H”, DB0 to DB7 are in an
output status.

− RW = “L”: The data on DB0 to DB7 are latched at

E_RD I

H 6800-series E

the falling edge of the E
signal.

L 8080-series /RD

Read enable clock input pin
When /RD is “L”, DB0 to DB7 are in an output status.

8-bit bi-directional data bus that is connected to the standard 8-bit microprocessor data

DB0

to

DB7

I/O

bus. When the serial interface selected (PS = "L");

− DB0 to DB5: high impedance

− DB6: serial input clock (SCLK)

− DB7: serial input data (SID).

When chip select is not active, DB0 to DB7 may be high impedance.

9

160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.4 S6B0719

Table 7. LCD driver output pins

Name I/O Description

LCD segment driver outputs
The display data and the M signal control the output voltage of segment driver.

SEG0

to

SEG159

COM0

to

COM103

COMS O

Display data M

Segment driver output voltage

Normal display Reverse display

H H V0 V2

O

H L Vss V3

L H V2 V0
L L V3 Vss

Power save mode Vss Vss

LCD common driver outputs
The internal scanning data and M signal control the output voltage of common driver.

Scan data M Common driver output voltage

H H Vss

O

H L V0

L H V1
L L V4

Power save mode Vss

Common output for the icons
The output signals of two pins are same. When not used, these pins should be left open.

10

S6B0719 PRELIMINARY SPEC. VER. 0.4 160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD

FUNCTIONAL DESCRIPTION

MICROPROCESSOR INTERFACE

Chip Select Input

There are CS1B and CS2 pins for chip selection. The S6B0719 can interface with an MPU only when CS1B is “L”
and CS2 is “H”. When these pins are set to any other combination, RS, E_RD, and RW_WR inputs are disabled
and DB0 to DB7 are to be high impedance. And, in case of serial interface, the internal shift register and the
counter are reset.

Parallel / Serial Interface

The S6B0719 has three types of interface with an MPU, which are one serial and two parallel interfaces. This
parallel or serial interface is determined by PS pin as shown in table 8.

Table 8. Parallel / Serial Interface Mode.

PS Type CS1B CS2 C68 Interface mode

H Parallel CS1B CS2

L Serial CS1B CS2

Parallel Interface (PS = "H")

The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by C68 as shown in
table 9. The type of data transfer is determined by signals at RS, E_RD and RW_WR as shown in table 10.

Table 9. Microprocessor Selection for Parallel Interface

C68 CS1B CS2 RS E_RD RW_WR DB0 to DB7 MPU bus

H CS1B CS2 RS E RW DB0 to DB7 6800-series

L CS1B CS2 RS /RD /WR DB0 to DB7 8080-series

Table 10. Parallel Data Transfer

Common 6800-series 8080-series Description

RS

E_RD

(E)

RW_WR

(RW)

E_RD

(/RD)

RW_WR

(/WR)

H 6800-series MPU mode
L 8080-series MPU mode

*×

Serial-mode

*×: Don't care

H H H L H Display data read out
H H L H L Display data write

L H H L H Register status read
L H L H L Writes to internal register (instruction)

11

160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.4 S6B0719

Serial Interface (PS = "L")

When the S6B0719 is active, serial data (DB7) and serial clock (DB6) inputs are enabled. And not active, the
internal 8-bit shift register and the 3-bit counter are reset. Serial data can be read on the rising edge of serial clock
going into DB6 and processed as 8-bit parallel data on the eighth serial clock. Serial data input is display data when
RS is high and control data when RS is low. Since the clock signal (DB6) is easy to be affected by the external
noise caused by the line length, the operation check on the actual machine is recommended.

CS1B

CS2

SID

SCLK

RS

DB6DB7DB0DB1DB2DB3DB4DB5DB6DB7

Figure 3. Serial Interface Timing

Busy Flag

The Busy Flag indicates whether the S6B0719 is operating or not. When DB7 is “H” in read status operation, this
device is in busy status and will accept only read status instruction. If the cycle time is correct, the microprocessor
needs not to check this flag before each instruction, which improves the MPU performance.

12

S6B0719 PRELIMINARY SPEC. VER. 0.4 160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD

RS

DB0 to DB7

BUS HOLDER

N

D(N)

D(N+1)

D(N+2)

N

N+1

N+2

N+3

Data Transfer

The S6B0719 uses bus holder and internal data bus for data transfer with the MPU. When writing data from the
MPU to on-chip RAM, data is automatically transferred from the bus holder to the RAM as shown in figure 4. And
when reading data from on-chip RAM to the MPU, the data for the initial read cycle is stored in the bus holder
(dummy read) and the MPU reads this stored data from bus holder for the next data read cycle as shown in figure 5.
This means that a dummy read cycle must be inserted between each pair of address sets when a sequence of
address sets is executed. Therefore, the data of the specified address cannot be output with the read display data
instruction right after the address sets, but can be output at the second read of data.

MPU signals

RS

/WR

DB0 to DB7

Internal signals

/WR

BUS HOLDER

COLUMN ADDRESS

MPU signals

/WR

/RD

Internal signals

/WR

N D(N) D(N+1) D(N+2) D(N+3)

N D(N) D(N+1) D(N+2) D(N+3)

N N+1 N+2 N+3

Figure 4. Write Timing

N

Dummy D(N) D(N+1)

/RD

COLUMN ADDRESS

Figure 5. Read Timing

13

160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.4 S6B0719

- -

- -

- -

- -

001

- -

0

011

- -

0

101

- -

0

000

- -

1

DISPLAY DATA RAM (DDRAM)

The Display Data RAM stores pixel data for the LCD. It is 105-row by 160-column addressable array. Each pixel
can be selected when the page and column addresses are specified. The 105 rows are divided into 13 pages of 8
lines and the 13th page with a single line (DB0 only). Data is read from or written to the 8 lines of each page directly
through DB0 to DB7. The display data of DB0 to DB7 from the microprocessor correspond to the LCD common
lines as shown in figure 6. The microprocessor can read from and write to RAM through the I/O buffer. Since the
LCD controller operates independently, data can be written into RAM at the same time as data is being displayed
without causing the LCD flicker.

DB0
DB1
DB2
DB3
DB4

1 0 0 - - 1

COM0

COM1
COM2
COM3
COM4

- -

Display Data RAM LCD Display

Figure 6. RAM-to-LCD Data Transfer

Page Address Circuit

This circuit is for providing a Page Address to Display Data RAM shown in figure 8. It incorporates 4-bit Page
Address register changed by only the “Set Page” instruction. Page Address 13 (DB3, DB2 and DB0 are “H”, but
DB1 is “L”) is a special RAM area for the icons and display data DB0 is only valid.

Line Address Circuit

This circuit assigns DDRAM a line address corresponding to the first line (COM0) of the display. Therefore, by
setting line address repeatedly, it is possible to realize the screen scrolling and page switching without changing
the contents of on-chip RAM as shown in figure 7. It incorporates 7-bit line address register changed by only the
initial display line instruction and 7-bit counter circuit. At the beginning of each LCD frame, the contents of register
are copied to the line counter which is increased by CL signal and generates the Line Address for transferring the
160-bit RAM data to the display data latch circuit. However, display data of icons are not scrolled because the MPU
can not access Line Address of icons.

14

S6B0719 PRELIMINARY SPEC. VER. 0.4 160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD

Column Address Circuit

Column Address circuit has an 8-bit preset counter that provides Column Address to the Display Data RAM as
shown in figure 8. When set Column Address MSB / LSB instruction is issued, 8-bit [Y7:Y0] is updated. And, since
this address is increased by 1 each a read or write data instruction, microprocessor can access the display data
continuously. However, the counter is not incremented and locked if a non-existing address above 9FH. It is
unlocked if a column address is set again by set Column Address MSB / LSB instruction. And the Column Address
counter is independent of page address register.

ADC select instruction makes it possible to invert the relationship between the Column Address and the segment
outputs. It is necessary to rewrite the display data on built-in RAM after issuing ADC select instruction. Refer to the
following figure 7.

SEG Output

SEG

0

SEG

1

SEG

2

SEG

3

... ...

SEG

156

SEG

157

SEG

158

SEG

159

Column address [Y7:Y0] 00H 01H 02H 03H ... ... 9CH 9DH 9EH 9FH

Display data 1 0 1 0 1 1 0 0

LCD panel display

... ...

( ADC = 0 )

LCD panel display

( ADC = 1 )

... ...

Figure 7. The Relationship between the Column Address and The Segment Outputs

Segment Control Circuit

This circuit controls the display data by the display ON / OFF, reverse display ON / OFF and entire display ON /
OFF instructions without changing the data in the display data RAM.

15

160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.4 S6B0719

Page Address

DB3 DB0DB1DB2

0 000

0 100

0 010

0 110

1 100

1 010

1 110

1 001

1 101 DB0 -

Column Address

LCD Segment Output

Data

DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7

DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7

ADC=0
ADC=1

00

SEG0

02

SEG1

SEG2

0301 04 05
9C9D 9A9B9E9F

SEG3

SEG4

SEG5

Page 0

Page 1

Page 2

Page 3

Page 9

Page 10

Page 11

Page 12

Page 13

- - - - - - - -

- - - - - - - -

- - - - - - - -

9C9D9A9B 9E 9F

SEG154

SEG155

0203 00010405

SEG156

SEG157

SEG158

SEG159

Line

Address

00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH

0BH
0CH
0DH
0EH
0FH

10H

11H

12H

13H

14H

15H

16H

17H

18H

19H
1AH
1BH
1CH
1DH
1EH
1FH

48H

49H
4AH
4BH
4CH
4DH
4EH
4FH

50H

51H

52H

53H

54H

55H

56H

57H

58H

59H
5AH
5BH
5CH
5DH
5EH
5FH

60H

61H

62H

63H

64H

65H

66H

67H

End = 07H

Start = 08H

1/97 Duty

1/105 Duty

Initial start line
address = 08H

COM

Output
COM0

COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8

COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31

COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COM80
COM81
COM82
COM83
COM84
COM85
COM86
COM87
COM88
COM89
COM90
COM91
COM92
COM93
COM94
COM95
COM96
COM97
COM98
COM99

COM100
COM101
COM102
COM103

COMS

16

Figure 8. Display Data RAM Map

S6B0719 PRELIMINARY SPEC. VER. 0.4 160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD

LCD DISPLAY CIRCUITS

Oscillator

This is completely on-chip Oscillator and its frequency is nearly independent of VDD. This oscillator signal is used in
the voltage converter and display timing generation circuit.

Display Timing Generator Circuit

This circuit generates some signals to be used for displaying LCD. The display clock, CL, generated by oscillation
clock, generates the clock for the line counter and the signal for the display data latch. The line address of on-chip
RAM is generated in synchronization with the display clock (CL) and the display data latch circuit in synchronization
latches the 160-bit display data with the display clock. The display data, which is read to the LCD driver, is
completely independent of the access to the display data RAM from the microprocessor. The display clock
generates an LCD AC signal (M) which enables the LCD driver to make a AC drive waveform, and also generates
an internal common timing signal and start signal to the common driver. The frame or the line changes the phase of
M by setting internal instruction. Driving waveform and internal timing signal are shown in figure 10.

In a multiple-chip configuration, the slave chip requires the CL, M and SYNC signals from the master. Table 11
shows the CL, SYNC, and M status.

Table 11. Master and Slave Timing Signal Status

Operation mode Oscillator CL SYNC M

Master ON (internal clock used) Output Output Output

Slave OFF (external clock used) Input Input Input

17

160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.4 S6B0719

8485123456789101112787980818283848512345

6

8485123456789101112787980818283848512345

6

CL

FR

M

V0
V1

COM0

COM1

SEGn

V2
V3
V4
VSS

V0
V1
V2
V3
V4
VSS

V0
V1
V2
V3
V4
VSS

Figure 9. 2-frame AC Driving Waveform (Duty Ratio = 1/85)

CL

FR

COM0

COM1

SEGn

M

V0
V1
V2
V3
V4
VSS

V0
V1
V2
V3
V4
VSS

V0
V1
V2
V3
V4
VSS

Figure 10. N-line Inversion Driving Waveform (N = 5, Duty Ratio = 1/85)

18

S6B0719 PRELIMINARY SPEC. VER. 0.4 160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD

SEG2

SEG0

COM2

COM0

VSS

VSS

VSS

VSS

VSS

VSS

LCD DRIVER CIRCUIT

106-channel common driver and 160-channel segment driver configure this driver circuit. This LCD panel driver
voltage depends on the combination of display data and M signal.

COM0
COM1

COM2
COM3

COM4
COM5

COM6
COM7

COM8

COM9
COM10
COM11
COM12

M

COM1

VDD

VSS

V0
V1
V2

V3
V4

V0
V1
V2

V3
V4

V0
V1
V2

V3
V4

V0
V1
V2

V3
V4

COM13
COM14
COM15

V0
V1
V2

SEG1

S

S

S

S

S

E

E

E

E

E

G

G

G

G

G

4

3

2

1

0

V3
V4

V0
V1
V2

V3
V4

Figure 11. Segment and Common Timing

19

160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.4 S6B0719

Partial Display on LCD

The S6B0719 realizes the partial display function on LCD with low-duty driving for saving power consumption and
showing the various display duties. To show the various display duties on LCD, LCD driving duty and bias are
programmable via the instruction. And, built-in power supply circuits are controlled by the instruction for adjusting
the LCD driving voltages

-- COMS

-- COM0

-- COM1

-- COM2

-- COM3

-- COM4

-- COM5

-- COM6

-- COM7

-- COM8

-- COM9

-- COM10

-- COM11

-- COM12

-- COM13

-- COM14

-- COM15

-- COM16

-- COM17

-- COM18

-- COM19

-- COM20

-- COM21

-- COM22

-- COM23

Figure 12. Reference Example for Partial Display (Display Duty = 25)

-- COMS

-- COM0

-- COM1

-- COM2

-- COM3

-- COM4

-- COM5

-- COM6

-- COM7

-- COM8

-- COM9

-- COM10

-- COM11

-- COM12

-- COM13

-- COM14

-- COM15

-- COM16

-- COM17

-- COM18

-- COM19

-- COM20

-- COM21

-- COM22

-- COM23

Figure 13. Partial Display (Partial Display Duty = 9, Initial COM0 = 0)

-- COMS

-- COM0

-- COM1

-- COM2

-- COM3

-- COM4

-- COM5

-- COM6

-- COM7

-- COM8

-- COM9

-- COM10

-- COM11

-- COM12

-- COM13

-- COM14

-- COM15

-- COM16

-- COM17

-- COM18

-- COM19

-- COM20

-- COM21

-- COM22

-- COM23

20

Figure 14. Moving Display (Partial Display Duty = 9, Initial COM0 = 8)

S6B0719 PRELIMINARY SPEC. VER. 0.4 160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD

POWER SUPPLY CIRCUITS

The Power Supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low­power consumption and the fewest components. There are voltage converter circuits, voltage regulator circuits,
and voltage follower circuits. They are valid only in master operation and controlled by power control instruction.
For details, refers to "Instruction Description". Table 12 shows the referenced combinations in using Power Supply
circuits.

Table 12. Recommended Power Supply Combinations

User setup

Only the internal power

supply circuits are used

Only the voltage

regulator circuits and

voltage follower circuits

are used

Only the voltage follower

circuits are used

Only the external power
supply circuits are used

Power

control

(VC VR VF)

1 1 1 ON ON ON Open Open Open

0 1 1 OFF ON ON

0 0 1 OFF OFF ON

0 0 0 OFF OFF OFF Open

V/C

circuits

V/R

circuits

V/F

circuits

VOUT V0 V1 to V4

External

input

External

input

Open Open

Open Open

External

input

External

input

21

160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.4 S6B0719

-

+

VOUT= 3 × VCI

-

+

-

+

-

+C1-

+

-

+

-

+

VOUT = 4 × VCI

-

+C1-

+C1-

+

-

+C1-

+C1-

+C1-

+C1-

+C1-

+C1-

+

VOUT = 5 × VCI

VOUT = 6 × VCI

-

+

Voltage Converter Circuits

These circuits boost up the electric potential between VCI and Vss to 3, 4, 5 or 6 times toward positive side and
boosted voltage is outputted from VOUT pin. It is possible to select the lower boosting level in any boosting circuit
by “Set DC-DC Step-up” instruction. When the higher level is selected by instruction, VOUT voltage is not valid.

[C1 = 1.0 to 4.7 µF]

Vss

C1

VOUT

C5+
C3+

Vss

C1

VOUT

C5+
C3+

C1

C1-

C1-

C1

C1+
C2+
C2 ­C4+

C1

VCI

Vss

C1+
C2+
C2 ­C4+

C1

VCI

Vss

Figure 15. Three Times Boosting Circuit Figure 16. Four Times Boosting Circuit

Vss

C1

VOUT

Vss

VOUT

C1

C5+

C5+

C1

C3+

C1­C1+
C2+

VCI

C2 -

Vss

C4+

C3+

C1­C1+
C2+

VCI

C2 -

Vss

C4+

Figure 17. Five Times Boosting Circuit Figure 18. Six Times Boosting Circuit

22

S6B0719 PRELIMINARY SPEC. VER. 0.4 160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD

GND

RaRbVSS

VRV0VOUT

Voltage Regulator Circuits

The function of the internal voltage regulator circuits is to determine liquid crystal operating voltage, V0, by
adjusting resistors, Ra and Rb, within the range of |V0| < |VOUT|. Because VOUT is the operating voltage of
operational-amplifier circuits shown in figure 19, it is necessary to be applied internally or externally.

For the Eq. 6-1, we determine V0 by Ra, Rb and VEV. The Ra and Rb are connected internally or externally by
INTRS pin. And VEV called the voltage of electronic volume is determined by Eq. 6-2, where the parameter α is the
value selected by instruction, "Set Reference Voltage Register", within the range 0 to 63. VREF voltage at Ta =
25°C is shown in Table 13.

V0 = { 1 + (Rb / Ra) } x VEV [V] ------ (Eq. 6-1)

VEV = { 1 - (63 - α) / 200 } x 2.0 = 1.69 [V] ------ (Eq. 6.2)

Table 13. VREF Voltage at Ta = 25°C

REF Temp. coefficient VREF [V]

1

-0.05% / °C

0 External input VEXT

+

V

EV

-

Figure 19. Internal Voltage Regulator Circuit

2.0

23

160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.4 S6B0719

0.00

2.00

4.00

6.00

8.00

10.00

12.00

14.00

16.00

08162432404856(1, 1, 1)

(1, 1, 0)

(1, 0, 1)

(1, 0, 0)

(0, 1, 1)

(0, 1, 0)

(0, 0, 1)

(0, 0, 0)

Electronic volume register (0 to 63)

63

In Case of Using Internal Resistors, Ra and Rb (INTRS = "H”)

When INTRS pin is “H”, resistor Ra is connected internally between VR pin and VSS, and Rb is connected between
V0 and VR. We determine V0 by two instructions, "Regulator Resistor Select" and "Set Reference Voltage".

3-bit data settings (R2 R1 R0)

0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

1 + (Rb / Ra) 2.6 3.4 4.2 5.0 5.8 6.6 7.4 8.3

Table 14. Internal Rb / Ra ratio Depending on 3-bit Data (R2 R1 R0)

Figure 20 shows V0 voltage measured by adjusting internal regulator register ratio (Rb / Ra) and 6-bit electronic
volume registers for each temperature coefficient at Ta = 25 °C.

V0 Voltage [V]

Figure 20. V0 Voltage by 1 + (Rb / Ra) and Electronic Volume Levels

24

S6B0719 PRELIMINARY SPEC. VER. 0.4 160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD

In Case of Using External Resistors, Ra and Rb (INTRS = "L")

When INTRS pin is “L”, it is necessary to connect external regulator resistor Ra between VR and VSS, and Rb
between V0 and VR.

Example: For the following requirements

1. LCD driver voltage, V0 = 10V

2. 6-bit reference voltage register = (1, 0, 0, 0, 0, 0)

3. Maximum current flowing Ra, Rb = 1 uA

From Eq. 6.1
10 = { 1 + (Rb / Ra) } x VEV [V] ------ (Eq. 6.3)

From Eq. 6.2
VEV = { 1 - (63 - 32) / 200 } x 2.0 = 1.69 [V] ------ (Eq. 6.4)

From requirement 3
10 / ( Ra + Rb) = 1 [uA] ------ (Eq. 6.5)

From equations Eq. 6.3, 6.4 and 6.5
Ra = 1.69 [MΩ]
Rb = 8.31 [MΩ]

Table 15 shows the range of V0 depending on the above requirements.

Table 15. The Range of V0

Electronic volume level

0 ....... 32 ....... 63

V0 8.10 ....... 10.00 ....... 11.83

Voltage Follower Circuits

VLCD voltage (V0) is resistively divided into four voltage levels (V1, V2, V3 and V4), and these output impedance
are converted by the Voltage Follower for increasing drive capability. Table 16 shows the relationship between V1
to V4 level and each duty ratio.

Table 16. V1 to V4 Level

LCD bias V1 V2 V3 V4 Remarks

1/N (N-1)/N x V0 (N-1)/N x V0 2/N x V0 1/N x V0 N = 4 to 11

25

160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.4 S6B0719

REFERENCE CIRCUIT EXAMPLES

[C1 = 1.0 to 4.7 [µF], C2 = 0.1 to 0.47 [µF]]

When using internal regulator resistors

V

DD

MS INTRS

VOUT

C5+
C3+
C1 ­C1+
C2+
C2 ­C4+

C1

C1

C1
C1

C1
C1

VR

C2

+
C2
C2
C2
C2

V

SS

V0

+

V1

+

V2

+

V3

+

V4

When not using internal regulator resistors

VDD

MS INTRS

VOUT

C5+
C3+
C1 ­C1+
C2+
C2 ­C4+

VR

Rb

+

V0

+

V1

+

V2

+

V3

+

V4

C1

C1

C1
C1

C1
C1

Ra

C2
C2
C2
C2
C2

VSS

VSS

Figure 21. When Using all LCD Power Circuits (6-Time V/C: ON, V/R: ON, V/F: ON)

When using internal regulator resistors

VDD

When not using internal regulator resistors

VDD

VSS

VSS

External

power

Supply

C2
C2
C2
C2
C2

+
+
+
+
+

MS INTRS

VOUT

C5+
C3+

C1 -

C1+
C2+

C2 -

C4+
VR
V0

V1
V2
V3
V4

VSS

External

power

Supply

Ra

C2
C2
C2
C2
C2

Rb

+
+
+
+
+

MS INTRS

VOUT
C5+
C3+
C1 ­C1+
C2+
C2 ­C4+

VR
V0

V1
V2
V3
V4

Figure 22. When Using some LCD Power Circuits (V/C: OFF, V/R: ON, V/F: ON)

26

S6B0719 PRELIMINARY SPEC. VER. 0.4 160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD

V

V

DD

MS INTRS

VOUT

C5+
C3+
C1 -

External

power

Supply

C1+
C2+
C2 ­C4+

VR

+
+
+
+
+

V0
V1
V2
V3
V4

SS

V

Figure 23. When Using only Voltage Follower Circuit (V/C: OFF, V/R: OFF, V/F: ON)

DD

MS INTRS

VOUT

C5+
C3+
C1 ­C1+
C2+
C2 ­C4+

VR
V0

External

power

Supply

V1
V2
V3
V4

SS

V

Figure 24. When Not Using all LCD Power Circuits (V/C: OFF, V/R: OFF, V/F: OFF)

27

160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.4 S6B0719

RESET CIRCUIT

Setting RESETB to “L” or Reset instruction can initialize internal function.
When RESETB becomes “L”, following procedure is occurred.

Page address: 0
Column address: 0
Modify-read: OFF
Display ON / OFF: OFF
Initial display line: 0 (first)
Initial COM0 register: 0 (COM0)
Partial display duty ratio: 1/105
Reverse display ON / OFF: OFF (normal)
n-line inversion register: 0 (disable)
Entire display ON / OFF: OFF (normal)
Power control register (VC, VR, VF) = (0, 0, 0)
DC-DC step up: 3 times converter circuit = (0, 0)
Regulator resistor select register: (R2, R1, R0) = (0, 0, 0)
Reference voltage control register: (EV5, EV4, EV3, EV2, EV1, EV0) = (1, 0, 0, 0, 0, 0)
LCD bias ratio: 1/11
SHL select: OFF (normal)
ADC select: OFF (normal)
Static indicator mode: OFF
Static indicator register: (S1, S0) = (0, 0)
Oscillator status: OFF
Power save mode: release

When RESET instruction is issued, following procedure is occurred.

Page address: 0
Column address: 0
Modify-read: OFF
Initial display line: 0 (First)
Regulator resistor select register: (R2, R1, R0) = (0, 0, 0)
Reference voltage control register (EV5, EV4, EV3, EV2, EV1, EV0) = (1, 0, 0, 0, 0, 0)
Static indicator mode: OFF
Static indicator register: (S1, S0) = (0, 0)

While RESETB is “L” or reset instruction is executed, no instruction except read status can be accepted. Reset
status appears at DB4. After DB4 becomes ”L”, any instruction can be accepted. RESETB must be connected to
the reset pin of the MPU, and initialize the MPU and this LSI at the same time. The initialization by RESETB is
essential before used.

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S6B0719 PRELIMINARY SPEC. VER. 0.4 160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD

INSTRUCTION DESCRIPTION

Table 17. Instruction Table

× : Don’ t care

Instruction

Read display data 1 1 Read data Read data from DDRAM

Write display data 1 0 Write data Write data into DDRAM

Read status 0 1

Set page address 0 0 1 0 1 1 P3 P2 P1 P0 Set page address

Set column address MSB 0 0 0 0 0 1 Y7 Y6 Y5 Y4 Set column address MSB

Set column address LSB 0 0 0 0 0 0 Y3 Y2 Y1 Y0 Set column address LSB

Set modify-read 0 0 1 1 1 0 0 0 0 0 Set modify-read mode

Reset modify-read 0 0 1 1 1 0 1 1 1 0 release modify-read mode

Display ON / OFF 0 0 1 0 1 0 1 1 1 D

Set initial display line

register

Set initial COM0 register

Set partial display

duty ratio

Set N-line inversion

Release N-line inversion 0 0 1 1 1 0 0 1 0 0 Release N-line Inversion mode

Reverse display ON / OFF 0 0 1 0 1 0 0 1 1 REV

Entire display ON / OFF 0 0 1 0 1 0 0 1 0 EON

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

BUSY

ADC

0 0 0 1 0 0 0 0
0 0
0 0 0 1 0 0 0 1
0 0
0 0 0 1 0 0 1 0

0 0
0 0 0 1 0 0 1 1
0 0

×

×

×

× × ×

ON RES

S6 S5 S4 S3 S2 S1 S0

C6 C5 C4 C3 C2 C1 C0

D6 D5 D4 D3 D2 D1 D0

N4 N3 N2 N1 N0

0 0 0 0 Read the internal status

× ×

× ×

× ×

× ×

Description

D = 0: display OFF
D = 1: display ON

2-byte instruction to specify the
initial display line to realize
vertical scrolling

2-byte instruction to specify the
initial COM0 to realize window
scrolling

2-byte instruction to set partial
display duty ratio

2-byte instruction to set n-line
inversion register

REV = 0: normal display
REV = 1: reverse display

EON = 0: normal display
EON = 1: entire display ON

29

160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.4 S6B0719

Table 17. Instruction Table (Continued)

Instruction

Power control 0 0 0 0 1 0 1 VC VR VF Control power circuit operation

Select DC-DC step-up 0 0 0 1 1 0 0 1 DC1 DC0

Select regulator resistor 0 0 0 0 1 0 0 R2 R1 R0

Set electronic volume

register

Select LCD bias 0 0 0 1 0 1 0 B2 B1 B0 Select LCD bias

SHL select 0 0 1 1 0 0 SHL

ADC select 0 0 1 0 1 0 0 0 0 ADC

Set static indicator mode 0 0 1 0 1 0 1 1 0 SM

Set static indicator register 0 0

Oscillator ON start 0 0 1 0 1 0 1 0 1 1 Start the built-in oscillator

Set power save mode 0 0 1 0 1 0 1 0 0 P

Release power save mode 0 0 1 1 1 0 0 0 0 1 Release power save mode

Reset 0 0 1 1 1 0 0 0 1 0 Initialize the internal functions

NOP 0 0 1 1 1 0 0 0 1 1 No operation

Test instruction 0 0 1 1 1 1

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 0 0 0 0 0 0 1
0 0

× ×

× × × × × ×

EV5 EV4 EV3 EV2 EV1 EV0

× × ×

S1 S0

× × × ×

Description

Select the step-up of the internal
voltage converter

Select internal resistance ratio of
the regulator resistor

2-byte instruction to specify the
electronic volume register

COM bi-directional selection
SHL = 0: normal direction
SHL = 1: reverse direction

SEG bi-directional selection
ADC = 0: normal direction
ADC = 1: reverse direction

2-byte instruction to specify the
static indicator mode

P = 0: standby mode
P = 1: sleep mode

Don't use this instruction.

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S6B0719 PRELIMINARY SPEC. VER. 0.4 160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD

Read Display Data

8-bit data from Display Data RAM specified by the column address and page address can be read by this
instruction. As the column address is incremented by 1 automatically after each this instruction, the
microprocessor can continuously read data from the addressed page. A dummy read is required after loading
an address into the column address register. Display data cannot be read through the serial interface.

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1 1 Read data

Write Display Data

8-bit data of display data from the microprocessor can be written to the RAM location specified by the column
address and page address. The column address is incremented by 1 automatically so that the microprocessor
can continuously write data to the addressed page.

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1 0 Write data

Set Page Address

Set Column Address

Data Write

Column = Column +1

Data Write Continue ?

No

Yes

Set Page Address

Set Column Address

Dummy Data Read

Column = Column +1

Data Read

Column = Column +1

Optional Status

Data Read Continue ?

Yes

No

Optional Status

Figure 25. Sequence for Writing Display Data Figure 26. Sequence for Reading Display Data

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160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.4 S6B0719

Read Status

Indicates the internal status of the S6B0719

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 1 BUSY ADC ON RES 0 0 0 0

Flag Description

The device is busy when internal operation or reset

BUSY

Any instruction is rejected until BUSY goes Low.
0: chip is active, 1: chip is being busy.

ADC

Indicates the relationship between RAM column address and segment driver.
0: reverse direction (SEG159 → SEG0), 1: normal direction (SEG0 → SEG159)

ON

RES

Indicates display ON / OFF status
0: display ON, 1: display OFF
Indicates the initialization is in progress by RESETB signal
0: chip is active, 1: chip is being reset.

Set Page Address

Sets the Page Address of display data RAM from the microprocessor into the Page Address register. Any
RAM data bit can be accessed when its Page Address and column address are specified. Along with the
column address, the Page Address defines the address of the display RAM to write or read display data.
Changing the Page Address doesn't effect to the display status.

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 0 1 1 P3 P2 P1 P0

P3 P2 P1 P0 Selected page Description

0 0 0 0 0
0 0 0 1 1
0 0 1 0 2

: : : : :

Accessible pages for displaying

dot-matrix display data

1 0 0 1 10
1 0 1 0 11
1 0 1 1 12
1 1 0 0 13 Accessible page for displaying icons
1 1 0 1 14
1 1 1 0 15

Not accessible page.

Do not use these pages.

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S6B0719 PRELIMINARY SPEC. VER. 0.4 160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD

Set Column Address

Sets the Column Address of display RAM from the microprocessor into the Column Address register. Along
with the Column Address, the Column Address defines the address of the display RAM to write or read display
data. When the microprocessor reads or writes display data to or from display RAM, Column Addresses are
automatically incremented.

Set Column Address MSB

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 1 Y7 Y6 Y5 Y4

Set Column Address LSB

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 0 Y3 Y2 Y1 Y0

Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

Selected column

address

0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1 1
0 0 0 0 0 0 1 0 2

:
:
:

:
:
:

:
:
:

:
:
:

:
:
:

:
:
:

:
:
:

:
:

:
1 0 0 1 1 1 0 1 157
1 0 0 1 1 1 1 0 158
1 0 0 1 1 1 1 1 159
1 0 1 0 0 0 0 0
1 0 1 0 0 0 0 1

Not accessible

column

1 0 1 0 0 0 1 0

:
:
:

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160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.4 S6B0719

Set Modify-Read

This instruction stops the automatic increment of the column address by the read display data instruction, but
the column address is still increased by the write display data instruction. And it reduces the load of
microprocessor when the data of a specific area is repeatedly changed during cursor blinking or others. This
mode is canceled by the reset Modify-read instruction.

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 1 1 0 0 0 0 0

Reset Modify-Read

This instruction cancels the Modify-read mode, and makes the column address return to its initial value just
before the set Modify-read instruction is started.

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 1 1 0 1 1 1 0

No

Set Page Address

Set Column Address (N)

Set Modify-Read

Dummy Read

Data Read

Data Process

Data Write

Change Complete ?

Yes

Reset Modify-Read

Return Column Address (N)

34

Figure 27. Sequence for Cursor Display

S6B0719 PRELIMINARY SPEC. VER. 0.4 160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD

Display ON / OFF

Turns the Display ON or OFF

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 0 1 0 1 1 1 D

D = 1: display ON
D = 0: display OFF

Set Initial Display Line Register

Sets the line address of display RAM to determine the initial display line using 2-byte instruction. The RAM
display data is displayed at the top row (COM0) of LCD panel.

The 1st Instruction

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 1 0 0 0 0

× ×

The 2nd Instruction

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0

×

S6 S5 S4 S3 S2 S1 S0

S6 S5 S4 S3 S2 S1 S0 Selected line address

0 0 0 0 0 0 0 0
0 0 0 0 0 0 1 1

: : : : : : : :
1 1 0 0 1 1 0 102
1 1 0 0 1 1 1 103
1 1 0 1 0 0 0

: : : : : : :

No operation

1 1 1 1 1 1 1

Setting Initial Display Line Start

1st Instruction (2-Byte Instruction for Mode Setting)

2nd Instruction (2-Byte Instruction for Register Setting)

Setting Initial Display Line End

Figure 28. The Sequence for Setting the Initial Display Line

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160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.4 S6B0719

Set Initial COM0 Register

Sets the initial row (COM) of the LCD panel using the 2-byte instruction. By using this instruction, it is possible
to realize the window moving without the change of display data.

The 1st Instruction

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 1 0 0 0 1

× ×

The 2nd Instruction

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0

×

C6 C5 C4 C3 C2 C1 C0

C6 C5 C4 C3 C2 C1 C0 Initial COM0

0 0 0 0 0 0 0 COM0
0 0 0 0 0 0 1 COM1
0 0 0 0 0 1 0 COM2

: : : : : : : :
1 1 0 0 1 0 1 COM101
1 1 0 0 1 1 0 COM102
1 1 0 0 1 1 1 COM103
1 1 0 1 0 0 0

: : : : : : :

No operation

1 1 1 1 1 1 1

36

Setting Initial COM0 Start

1st Instruction (Mode Setting)

2nd Instruction (Initial COM0 Setting)

Setting Initial COM0 End

Figure 29. Sequence for Setting the Initial COM0

S6B0719 PRELIMINARY SPEC. VER. 0.4 160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD

Set Partial Display Duty Ratio

Sets the duty ratio within range of 9, 17 and 32 to 105 to realize Partial Display by using the 2-byte instruction.

The 1st Instruction

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 1 0 0 1 0

× ×

The 2nd Instruction

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0

×

D6 D5 D4 D3 D2 D1 D0

D6 D5 D4 D3 D2 D1 D0 Selected partial duty ratio

0 0 0 1 0 0 1 1/9
0 0 1 0 0 0 1 1/17
0 1 0 0 0 0 0 1/32
0 1 0 0 0 0 1 1/33

: : : : : : : :
1 0 1 0 1 0 0 1/104
1 0 1 0 1 0 1 1/105

Other combinations No operation

Setting Partial Display Start

1st Instruction (Mode Setting)

2nd Instruction (Partial Display Duty Setting)

Setting Partial Display End

Figure 30. Sequence for Setting Partial Display

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160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.4 S6B0719

Set N-line Inversion Register

Sets the inverted line number within range of 2 to 32 to improve the display quality by controlling the phase of
the internal LCD AC signal (M) by using the 2-byte instruction.

The 1st Instruction

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 1 0 0 1 1

× ×

The 2nd Instruction

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0

× × ×

N4 N3 N2 N1 N0

N4 N3 N2 N1 N0 Selected n-line inversion

0 0 0 0 0 0-line inversion (frame inversion)
0 0 0 0 1 2-line inversion
0 0 0 1 0 3-line inversion
0 0 0 1 1 4-line inversion

: : : : : :
1 1 1 0 1 30-line inversion
1 1 1 1 0 31-line inversion
1 1 1 1 1 32-line inversion

Setting N-Line Inversion Start

1st Instruction (Mode Setting)

2nd Instruction (N-Line Inversion Setting)

Setting N-Line Inversion End

Figure 31. Sequence for Setting Partial Display

Release N-line Inversion

Returns to the frame inversion condition from the n-line inversion condition.

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 1 1 0 0 1 0 0

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S6B0719 PRELIMINARY SPEC. VER. 0.4 160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD

Reverse Display ON / OFF

Reverses the display status on LCD panel without rewriting the contents of the display data RAM.

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 0 1 0 0 1 1 REV

REV RAM bit data = “1” RAM bit data = “0”

0 (normal) LCD pixel is illuminated LCD pixel is not illuminated

1 (reverse) LCD pixel is not illuminated LCD pixel is illuminated

Entire Display ON / OFF

Forces the whole LCD points to be turned on regardless of the contents of the display data RAM. At this time,
the contents of the display data RAM are held. This instruction has priority over the reverse Display ON / OFF
instruction.

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 0 1 0 0 1 0 EON

EON RAM bit data = “1” RAM bit data = “0”

0 (Normal) LCD pixel is illuminated LCD pixel is not illuminated

1 (Entire) LCD pixel is illuminated LCD pixel is illuminated

Power Control

Selects one of eight power circuit functions by using 3-bit register. An external power supply and part of
internal power supply functions can be used simultaneously.

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 1 0 1 VC VR VF

VC VR VF Status of internal power supply circuits

0
1

0
1

0
1

Internal voltage converter circuit is OFF

Internal voltage converter circuit is ON

Internal voltage regulator circuit is OFF

Internal voltage regulator circuit is ON
Internal voltage follower circuit is OFF

Internal voltage follower circuit is ON

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160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.4 S6B0719

Select DC/DC Step-up

Selects one of 4 DC/DC step-up to reduce the power consumption by this instruction. It is very useful to realize
the partial display function.

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 1 1 0 0 1 DC1 DC0

DC1 DC0 Selected DC-DC converter circuit

0 0 3 times boosting circuit
0 1 4 times boosting circuit
1 0 5 times boosting circuit
1 1 6 times boosting circuit

Regulator Resistor Select

Selects resistance ratio of the internal resistor used in the internal voltage regulator. See voltage regulator
section in power supply circuit. Refer to the table 15.

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 1 0 0 R2 R1 R0

R2 R1 R0 [Rb / Ra] ratio

0 0 0 Small
0 0 1 :

: : : :
1 1 0 :
1 1 1 Large

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S6B0719 PRELIMINARY SPEC. VER. 0.4 160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD

Set Electronic Volume Register

Consists of 2-byte instruction. The 1st instruction sets Electronic Volume mode, the 2nd one updates the
contents of Electronic Volume register. After second instruction, Electronic Volume mode is released.

The 1st Instruction

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 0 0 0 0 0 0 1

The 2nd Instruction

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0

× ×

EV5 EV4 EV3 EV2 EV1 EV0

EV5 EV4 EV3 EV2 EV1 EV0

Reference voltage (α)

0 0 0 0 0 0 0
0 0 0 0 0 1 1

:
:

:
:

:
:

:
:

:
:

:

:
1 1 1 1 1 0 62
1 1 1 1 1 1 63

Setting Electronic Volume Start

1st Instruction for Mode Setting

2nd Instruction for Register Setting

Setting Electronic Volume End

Figure 32. Sequence for Setting the Electronic Volume

:
:

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160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.4 S6B0719

Select LCD Bias

Selects LCD Bias ratio of the voltage required for driving the LCD.

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 1 0 1 0 B2 B1 B0

B2 B1 B0 Selected LCD bias

0 0 0 1/4
0 0 1 1/5
0 1 0 1/6
0 1 1 1/7
1 0 0 1/8
1 0 1 1/9
1 1 0 1/10
1 1 1 1/11

SHL Select

COM output scanning direction is selected by this instruction which determines the LCD driver output status.

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 1 0 0 SHL

× × ×

SHL = 0: normal direction (COM0 → COM103)
SHL = 1: reverse direction (COM103 → COM0)

ADC Select

Changes the relationship between RAM column address and segment driver. The direction of segment driver
output pins can be reversed by software. This makes IC layout flexible in LCD module assembly.

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 0 1 0 0 0 0 ADC

ADC = 0: normal direction (SEG0 → SEG159)
ADC = 1: reverse direction (SEG159 → SEG0)

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S6B0719 PRELIMINARY SPEC. VER. 0.4 160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD

Set Static Indicator State

Consists of two bytes instruction. The first byte instruction (set Static Indicator mode) enables the second byte
instruction (set Static Indicator register) to be valid. The first byte sets the Static Indicator ON / OFF. When it is
on, the second byte updates the contents of Static Indicator register without issuing any other instruction and
this Static Indicator state is released after setting the data of indicator register.

The 1st Instruction: Set Static Indicator Mode (ON / OFF)

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 0 1 0 1 1 0 SM

SM = 0: static indicator OFF
SM = 1: static indicator ON

The 2nd Instruction: Set Static Indicator Register

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0

× × × × × ×

S1 S0

S1 S0 Status of static indicator output

0 0 OFF
0 1 ON (about 0.5 second blinking)
1 0 ON (about 1 second blinking )
1 1 ON (always ON)

Oscillator ON Start

This instruction enables the built-in oscillator circuit.

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 0 1 0 1 0 1 1

Reset

This instruction resets initial display line, column address, page address, and common output status select to
their initial status, but dose not affect the contents of display data RAM. This instruction cannot initialize the
LCD power supply that is initialized by the RESETB pin.

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 1 1 0 0 0 1 0

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160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.4 S6B0719

Release Standby Mode

Release Sleep Mode

Power Save

The S6B0719 enters the Power Save status to reduce the power consumption to the static power consumption
value and returns to the normal operation status by the following instructions.

Set Power Save Mode

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 0 1 0 1 0 0 P

P = 0: standby mode
P = 1: sleep mode

Release Power Save Mode

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 1 1 0 0 0 0 1

Set Power Save Mode

Sleep Mode

Oscillator Circuits: OFF
Static Driver: Disable
LCD Power Supply Circuits: OFF
All COM / SEG Output Level: VSS
Consumption Current < 2µA

Release Power Save Mode

Figure 33. Power Save Routine

Standby Mode

Oscillator Circuits: ON
Static Driver: Enable
LCD Power Supply Circuits: OFF
All COM / SEG Output Level: VSS
Consumption Current < 10µA

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S6B0719 PRELIMINARY SPEC. VER. 0.4 160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD

NOP

Non-operation

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 1 1 0 0 0 1 1

Test Instruction

This instruction is for testing IC. Please do not use it.

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 1 1 1

× × × ×

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160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.4 S6B0719

[Display Duty Select]

[ADC Select]

[SHL Select]

[Oscillator On]

[Regulator Resistor Select]

[Electronic Volume Register Select]

[Power Control]

Referential Instruction Setup Flow: Initializing with the Built-in Power Supply Circuits

User System Setup by External Pins

Start of Initialization

Power ON (VDD-VSS) Keeping the RESETB Pin = "L"

Waiting for Stabilizing the Power

RESETB pin = "H"

User Application Setup by Internal Instructions

[COM0 Register Select]

User LCD Power Setup by Internal Instructions

[DC-DC Step-up Register Select]

[LCD Bias Register Select]

Waiting for Stabilizing the LCD Power Levels

End of Initialization

Figure 34. Initializing with the Built-in Power Supply Circuits

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S6B0719 PRELIMINARY SPEC. VER. 0.4 160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD

Power ON (VDD-VSS) Keeping the RESETB Pin = "L"

Waiting for Stabilizing the Power

Set Power Save

[Display Duty Select]

[ADC Select]

[SHL Select]

[COM0 Register Select]

User LCD Power setup by internal instructions

[Power Control]

Waiting for Stabilizing the LCD Power Levels

RESETB Pin = "H"

Release Power Save

Referential Instruction Setup Flow: Initializing without the Built-in Power Supply Circuits

User System Setup by External Pins

Start of Initialization

User Application Setup by Internal Instructions

[Oscillator ON]

Regulator or Follower Register Select

End of Initialization

Figure 35. Initializing without the Built-in Power Supply Circuits

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160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.4 S6B0719

End of Initialization

Write Display Data by Instruction

[Display Data write]

Turn Display On/Off Instruction

[Display ON/Off]

End of Data Display

Display Data RAM Addressing by Instruction

[Initial Display Line]

[Set Page Address]

[Set Column Address]

Power Off (VDD-VSS)

Set Power Save by Instruction

Referential Instruction Setup Flow: Data Displaying

Figure 36. Data Displaying

Referential Instruction Setup Flow: Power OFF

Optional Status

End of Power Off

Figure 37. Power OFF

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S6B0719 PRELIMINARY SPEC. VER. 0.4 160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD

Referential Instruction Setup Flow: Partial Duty Changing

Start of Partial changing

Set Display OFF by Internal Instruction

[Display ON / OFF]

Set Standby Mode by Internal Instruction

[Power Save Mode]

Set Partial Duty by Internal Instructions

[Partial Display Duty Ratio Select]

[Initial Display Line Register]

[COM0 Register Select]

User LCD Power Setup by Internal Instructions

[DC-DC Step-up Register Select]

[Regulator Resistor Select]

[Electronic Volume Register Select]

[LCD Bias Register Select]

[Power Control]

Waiting for Discharging the LCD Power Levels

Release Power Save

Waiting for Stabilizing the LCD Power Levels

Write Display Data & Display ON by Internal Instruction

[Display Data Write]

[Display ON / OFF]

End of Partial Changing

Figure 38. Partial Duty Changing

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160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.4 S6B0719

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

Table 18. Absolute Maximum Ratings

(Vss = 0V)

Parameter Symbol Rating Unit

VDD - 0.3 ~ + 7.0 V

V0, VOUT + 0.3 ~ + 17.0 VSupply voltage range

V1, V2, V3, V4 + 0.3 ~ V0 V

External reference voltage VEXT +0.3 ~ VDD

Input voltage range VIN - 0.3 ~ VDD + 0.3 V

Operating temperature range TOPR - 40 ~ + 85

Storage temperature range TSTR - 55 ~ + 125

NOTES:

1. VDD, V0, VOUT, V1 to V4, VEXT and VCI are based on Vss = 0V.

2. Voltage VOUT ≥ V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS must always be satisfied.

3. If supply voltage exceeds its absolute maximum range, this LSI may be damaged permanently.
It is desirable to use this LSI under electrical characteristic conditions during general operation.
Otherwise, this LSI may malfunction or reduced LSI reliability may result.

°C
°C

50

S6B0719 PRELIMINARY SPEC. VER. 0.4 160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD

DC CHARACTERISTICS

Table 19. DC Characteristics

(VSS = 0V, VDD = 2.4 to 3.6V, Ta = -40~85°C)

Item Symbol Condition Min. Typ. Max. Unit Pin used

Operating voltage (1) VDD 2.4 - 3.6 V VDD *1
Operating voltage (2) V0 4.0 - 15.0 V V0, *2

Input voltage

Output

voltage

Input leakage current IIL VIN = VDD or VSS - 1.0 - + 1.0

Output leakage current IOZ VIN = VDD or VSS - 3.0 - + 3.0

LCD driver ON

resistance

Frame frequency fFR Ta = 25°C 70 85 100 Hz

Item Symbol Condition Min. Typ. Max. Unit Pin used

Voltage converter

circuit output voltage

Voltage regulator

circuit operating

voltage

Voltage follower circuit

operating voltage

High VIH 0.8VDD - VDD

Low VIL VSS - 0.2VDD

High VOH IOH = -0.5mA 0.8VDD - VDD

Low VOL IOL = 0.5mA VSS - 0.2VDD

RON Ta = 25°C, V0 = 8V - 2.0 3.0 kΩ

Table 20. DC Characteristics

×3 / ×4 / ×5 / ×6

VOUT

VOUT 6.0 - 17.0 V VOUT

V0 4.0 - 15.0 V V0 *8

voltage conversion

(no-load )

95 99 - % VOUT

V *3

V *4

µA
µA

SEGn

COMn *6

*3
*5

*7

FR

Reference voltage VREF

Ta = 25°C

1.94 2.00 2.06 V *9

51

160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.4 S6B0719

Dynamic Current Consumption (1) when an External Power Supply is used.

Table 21. Display OFF

(VDD = 3.0V, Ta = 25°C)

Item Symbol Condition Min. Typ. Max. Unit Pin used

Dynamic current

consumption (1)

IDD1

V0 - Vss = 7.0V, duty = 1/33 TBD
V0 - Vss = 10.0V, duty = 1/65 TBD
V0 - Vss = 13.0V, duty = 1/105 TBD

Table 22. Checker Pattern

Item Symbol Condition Min. Typ. Max. Unit Pin used

Dynamic current

consumption (1)

IDD1

V0 - Vss = 7.0V, duty = 1/33 TBD
V0 - Vss = 10.0V, duty = 1/65 TBD
V0 - Vss = 13.0V, duty = 1/105 TBD

Dynamic Current Consumption (2) when the Internal Power Supply is ON

Table 23. Display OFF

Item Symbol Condition Min. Typ. Max. Unit Pin used

Dynamic current

V0 - Vss = 7.0V, X3 boosting,

duty = 1/33, normal mode

V0 - Vss = 7.0V, X3 boosting,
duty = 1/33, high power mode

V0 - Vss = 10.0V, X4 boosting,

duty = 1/65, normal mode

- - TBD

- - TBD

- - TBD

consumption (2) IDD2

V0 - Vss = 10.0V, X4 boosting,

duty = 1/65, high power mode

V0 - Vss = 13.0V, X5 boosting,

duty = 1/105, normal mode

V0 - Vss = 13.0V, X5 boosting,

duty = 1/105, high power mode

- - TBD

- - TBD

- - TBD

µΑ

*10

(VDD = 3.0V, Ta = 25°C)

µΑ

*10

(VDD = 3.0V, Ta = 25°C)

µΑ *10

µΑ *10

µΑ *10

52

S6B0719 PRELIMINARY SPEC. VER. 0.4 160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD

Table 24. Check Pattern

(VDD = 3.0V, Ta = 25°C)

Item Symbol Condition Min. Typ. Max. Unit Pin used

V0 - Vss = 7.0V, X3 boosting,

duty = 1/33, normal mode

V0 - Vss = 7.0V, X3 boosting,

duty = 1/33, high power mode

V0 - Vss = 10.0V, X4 boosting,

Dynamic current

consumption (2)

IDD2

duty = 1/65, normal mode

V0 - Vss = 10.0V, X4 boosting,

duty = 1/65, high power mode

V0 - Vss = 13.0V, X5 boosting,

duty = 1/105, normal mode

V0 - Vss = 13.0V, X5 boosting,
duty = 1/105, high power mode

Dynamic Current Consumption during Power Save Mode

Table 25. Power Save Mode

Item Symbol Condition Min. Typ. Max. Unit Pin used

Sleep mode

current

Standby mode

current

IDDS1 During sleep - - 2 µΑ

IDDS2 During standby - - 10 µΑ

- - TBD
µΑ *10

- - TBD

- - TBD
µΑ *10

- - TBD

- - TBD
µΑ *10

- - TBD

(VDD = 3.0V, Ta = 25°C)

53

160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.4 S6B0719

Table 26. The Relationship between Oscillation Frequency and Frame Frequency

Duty ratio Item fCL Fosc

1/N

On-chip oscillator circuit is

used

fFR x N fFR x 4 x N

(fOSC: oscillation frequency, fCL: display clock frequency, fFR: frame frequency, N = 9 to 105)

[* Remark Solves]
*1. Though the wide range of operating voltages is guaranteed, a spike voltage change may affect the voltage assurance during
access from the MPU.
*2. In case of external power supply is applied.
*3. CS1B, CS2, RS, DB0 to DB7, E_RD, RW_WR, RESETB, MS, C68, PS, INTRS, HPMB, REF, CL, M and SYNC.
*4. DB0 to DB7, FR, FRS, SYNC, M and CL.
*5. Applies when the DB0 to DB7, SYNC, M, and CL pins are in high impedance.
*6. Resistance value when -0.1[mA] is applied during the On status of the output pin SEGn or COMn.
RON [kΩ] = ∆V[V] / 0.1[mA] (∆V : voltage change when -0.1[mA] is applied in the ON status.)
*7. See Table 26 for the relationship between oscillation frequency and frame frequency.
*8. The voltage regulator circuit adjusts V0 within the voltage follower operating voltage range.
*9. On-chip reference voltage source of the voltage regulator circuit to adjust V0.
*10. Applies to the case where the on-chip oscillation circuit is used and no access is made from the MPU.
The current consumption, when the built-in power supply circuit is on or OFF.
The current flowing through voltage regulation resistors (Rb and Ra) is not included.
It does not include the current of the LCD panel capacity, wiring capacity, etc.

54

S6B0719 PRELIMINARY SPEC. VER. 0.4 160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD

t

t

RS

AC CHARACTERISTICS

Read / Write Characteristics (8080-series MPU)

AS80

/RD, /WR

0.9VDD

DB0 to DB7

DB0 to DB7

Figure 39. Parallel Interface (8080-series MPU) Timing Diagram

Table 27. AC Characteristics (8080-series Parallel Mode)

Item Signal Symbol Condition Min. Max. Unit

Address setup time

Address hold time

RS

System cycle time t

Pulse width low for write

Pulse width High for write

Pulse width low for read

Pulse width high for read

RW_WR

(/WR)
E_RD

(/RD)

Data setup time

Data hold time

DB0

to

Read access time

DB7

Output disable time

tPWLW, tPWLR

0.1VDD

ACC80

t

t

AS80

t

AH80

CY80

t

PWLW

t

PWHW

t

PWLR

t

PWHR

t

DS80

t

DH80

t

ACC80

t

OD80

tCY80

tDS80

CL = 100 pF

AH80

tPWHW, tPWHR

tDH80

OD80

t

(VDD = 2.4 ~ 3.6V, Ta = -40 ~ +85°C)

0
0

-

-

300 - ns

60
60

120

60
40

15

-

10

-

-

-

-

-

-

140
100

ns

ns

ns

ns

ns

NOTE: *1. The input signal rise time and fall time (tr, tf) is specified at 15 ns or less.
(tr + tf) < (tCY80 - tPWLW - tPWHW ) for write, (tr + tf) < (tCY80 - tPWLR - tPWHR ) for read

55

160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.4 S6B0719

( Write )

( Read )

Read / Write Characteristics (6800-series Microprocessor)

RS, R/W

tAS68

tAH68

tCY68

tEWLW, tEWLR

CS1B

E

0.1VDD

0.9VDD
tEWHW, tEWHR

tDS68

tDH68

DB0 to DB7

tACC68

tOD68

DB0 to DB7

Figure 40. Parallel Interface (6800-series MPU) Timing Diagram

Table 28. AC Characteristics (6800-series Parallel Mode)

(VDD = 2.4 ~ 3.6V, Ta = -40 ~ +85°C)

Item Signal Symbol Condition Min. Max. Unit

Address setup time

Address hold time

RS

RW

tAS68
tAH68

0
0

-

-

System cycle time tCY68 300 - ns

Enable width high for write

Enable width low for write

Enable width high for read

Enable width low for read

Data setup time

Data hold time

E_RD

(E)

E_RD

(E)

DB0

tEWHW
tEWLW

tEWHR

tEWLR

tDS68
tDH68

60
60

120

60
40

15

-

-

-

-

-

-

to

Read access time

Output disable time

DB7

tACC68

tOD68

CL = 100 pF

10

-

140
100

ns

ns

ns

ns

ns

NOTE: *1. The input signal rise time and fall time (tr, tf) is specified at 15 ns or less.
(tr + tf) < (tCY68 - tEWHW - tEWLW ) for write, (tr + tf) < (tCY68 - tEWHR - tEWLR ) for read

56

S6B0719 PRELIMINARY SPEC. VER. 0.4 160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD

Serial Interface Characteristics

tCHStCSS

CS1B

(CS2 = 1 )

tAHStASS

RS

tCYS

DB6

( SCLK )

0.9VDD

0.1VDD
tWLS

tWHS

tDHStDSS

DB7

( SID )

Figure 41. Serial Interface Timing Diagram

Table 29. AC Characteristics (Serial Mode)

Item Signal Symbol Condition Min. Max. Unit

Serial clock cycle

SCLK high pulse width

SCLK low pulse width

Address setup time

Address hold time

Data setup time

Data hold time

CS1B setup time

CS1B hold time

NOTE: *1. The input signal rise time and fall time (tr, tf) is specified at 15 ns or less.

DB6

(SCLK)

RS

DB7

(SID)

CS1B

tsCY
tsHW
tsLW

tASS

tAHS

tDSS

tDHS

tCSS

tCHS

(VDD = 2.4 ~ 3.6V, Ta = -40 ~ +85°C)

250
100
100

150
150

100
100

150
150

-

-

ns

-

-

-

-

-

-

-

ns

ns

ns

57

160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.4 S6B0719

Reset Input Timing

tRW

RESETB

tR

Internal status

Reset completeDuring reset

Figure 42. Reset Input Timing Diagram

Table 30. AC Characteristics (Reset mode)

(VDD = 2.4 ~ 3.6V, Ta = -40 ~ +85°C)

Item Signal Symbol Condition Min. Max. Unit

Reset low pulse width RESETB tRW 1000 - ns

Reset time - tR - 1000 ns

58

S6B0719 PRELIMINARY SPEC. VER. 0.4 160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD

OPEN

RESETB

VSS

VDD or VSS

SCLK

SIDRSCS2

CS1B

REFERENCE APPLICATIONS

MICROPROCESSOR INTERFACE

6800-series

MPU

CS1B
CS2
RS
E
RW
DB0 to DB7
RESETB

VDD
V

DD

CS1B
CS2
RS
E_RD
RW_WR
DB0 to DB7
RESETB
C68
PS

S6B0719

Figure 43. In Case of Interfacing with 6800-series (PS = “H”, C68 = “H”)

8080-series

MPU

CS1B
CS2
RS
/RD
/WR
DB0 to DB7
RESETB

VSS

DD

V

CS1B
CS2
RS
E_RD
RW_WR
DB0 to DB7
RESETB
C68
PS

S6B0719

Figure 44. In Case of Interfacing with 8080-series (PS = “H”, C68 = “L”)

CS1B
CS2

MPU

RS
DB7(SID)
DB6(SCLK)
RESETB
DB0 to DB5
C68
PS

S6B0719

Figure 45. In Case of Serial Interface (PS = “L”, C68 = “H/L”)

59

160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.4 S6B0719

SEG159 SEG158 ← SEG1 SEG0

SEG0 SEG1 → SEG158 SEG159

SEG159 SEG158 ← SEG1 SEG0

SEG0 SEG1 → SEG158 SEG159

CONNECTIONS BETWEEN S6B0719 AND LCD PANEL

Single Chip Configuration (1/105 Duty configurations)

COMS

COM103

↑

COM52

S6B0719

(Bottom View)

♣ ♦ ♥ ♠ Ξ 

104 × 160 pixels

♣ ♦ ♥ ♠ Ξ 

COM51

↑

COM0

COMS

COM51

↑

COM0
COMS

S6B0719

(Top View)

♣ ♦ ♥ ♠ Ξ 

104 × 160 pixels

♣ ♦ ♥ ♠ Ξ 

COMS

COM103

↑

COM52

Figure 46. SHL = 0, ADC = 0 Figure 47. SHL = 0, ADC = 1

♣ ♦ ♥ ♠ Ξ 

104 × 160 pixels

♣ ♦ ♥ ♠ Ξ 

104 × 160 pixels

♣ ♦ ♥ ♠ Ξ 

S6B0719

(Top View)

COMS
COM0

↓

COM51

COMS
COM0

↓

COM51

♣ ♦ ♥ ♠ Ξ 

S6B0719

(Bottom View)

COM52

↓

COM103

COMS

COM52

↓

COM103
COMS

Figure 48. SHL = 1, ADC = 0 Figure 49. SHL = 1, ADC = 1

60

S6B0719 PRELIMINARY SPEC. VER. 0.4 160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD

SEG159 SEG158 ← SEG1 SEG0

SEG159 SEG158 ← SEG1 SEG0

SEG0 SEG1 → SEG158 SEG159

SEG0 SEG1 → SEG158 SEG159

Multiple Chip Configuration

COMS
COM103

↑

COM52

S6B0719

(Bottom View)

(Master)

COM51

↑

COM0

COMS

♣ ♦ ♥ ♠ Ξ 

COMS
COM103

↑

COM52

S6B0719

(Bottom View)

104 × 320 pixels

♣ ♦ ♥ ♠ Ξ 

Figure 50. SHL = 0, ADC = 1

♦ Connect the following pins of two chips each other:

- Display clock pins: CL, M, SYNC

- LCD power pins: V0, V1, V2, V3, V4

♣ ♦ ♥ ♠ Ξ 

(Slave)

COM51

↑

COM0

COMS

COMS
COM0

↓

COM51

104 × 320 pixels

♣ ♦ ♥ ♠ Ξ 

S6B0719

(Bottom View)

(Master)

COM52

↓

COM103

COMS

COMS
COM0

↓

COM51

S6B0719

(Bottom View)

(Slave)

Figure 51. SHL = 1, ADC = 0

♦ Connect the following pins of two chips each other:

- Display clock pins: CL, M, SYNC

- LCD power pins: V0, V1, V2, V3, V4

COM52

↓

COM103

COMS

61