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A/D, D/C Converters for Image Signal Processing
MN65771F
Low Power 10-Bit 5 V CMOS A/D Conv erter for Image Processing
Overview
The MN65771F is a high-speed 10-bit CMOS analog-
to-digital converter for image processing applications.
It uses a half flash structure based on chopper comparators to achieve both high speed and low power consumption.
Features
Maximum conversion rate: 18 MSPS (min.)
Linearity error: ±1.3 LSB (typ.)
Differential linearity error: ±1.0 LSB (typ.)
Power supply voltage: 5.0 V or 3.3 V
Power consumption: 115 mW (typ.) (f
=20 MHz)
CLK
Applications
Digital television receivers
Digital video equipment
Digital image processing equipment
Pin Assignment
RBSVRBVR3VR2VR1VRTVRTS
N.C.
V
N.C.
AV
V
N.C.
N.C.
N.C.
AV
DV
DV
LINDF
OVF
N.C.
DD
IN
SS
SS
DD
3635343332313029282726
37
38
39
40
41
42
43
44
45
46
47
48
1234567891011
D0D1D2D3D4
N.C.
SS
D5D6D7D8D9
DDL
DV
DV
(TOP VIEW)
QFH048-P-0707
DD
AVSSAVDDAV
25
24
23
22
21
20
19
18
17
16
15
14
13
12
POWD
NOE
CLK
MINV
LINV
N.C.
DV
DD
DV
SS
DV
SS
DV
DD
TEST1
TEST2
1
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MN65771F A/D, D/C Converters for Image Signal Processing
Block Diagram
SS
DVDDDV
45444339383534333231302927
AV
DD
SS
RBS
AV
RB
V
IN
V
31
RTS
V
VRTVR1VR2VR3V
29
DDAVSS
AV
AVDDLINV
262521
Pin NO.
19, 28, 36, 37,
( )
40, 41, 42, 48 are N.C.pin.
MINV
20
57
Lower comparator (5 bits)
Lower encoder (5 bits)
5
Upper comparator (5 bits)
31
Upper encoder (5 bits)
46
UNDF
47
OVF
123
(LSB)
D0
45678
D1
D2
D3
D4
SS
DV
DDL
DV
Clock generator
5
9
1011121314151617182223
TEST2
TEST1
DD
DV
DVSSDV
D5
D6D7D8
D9
SS
DV
Error
correction
and
data latch
DD
CLK
NOE
24
POWD
2
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A/D, D/C Converters for Image Signal Processing MN65771F
Pin Descriptions
Pin No. Symbol Function Description
1 D0 Digital code output (LSB)
2 D1 Digital code output
3 D2 Digital code output
4 D3 Digital code output
5 D4 Digital code output
6DVSSGround for digital circuits
7DV
DDL
8 D5 Digital code output
9 D6 Digital code output
10 D7 Digital code output
11 D8 Digital code output
12 D9 Digital code output
13 TEST2 Test mode selection
14 TEST1 Test mode selection
15 DV
16 DV
17 DV
18 DV
DD
SS
SS
DD
19 N.C. No connection
20 LINV Output inversion
21 MINV Output inversion
22 CLK Sampling clock
23 NOE Digital output enable
24 POWD Power down mode selection
25 AV
26 AV
27 AV
DD
DD
SS
28 N.C. No connection
29 V
30 V
31 V
32 V
33 V
34 V
35 V
RTS
RT
R1
R2
R3
RB
RBS
36 N.C. No connection
37 N.C. No connection
38 AV
39 V
DD
IN
40 N.C. No connection
Power supply for digital circuits
Power supply for digital circuits
Ground for digital circuits
Ground for digital circuits
Power supply for digital circuits
Power supply for analog circuits
Power supply for analog circuits
Ground for analog circuits
Reference voltage power supply (TOP)
Reference voltage input (TOP)
Intermediate reference voltage
Intermediate reference voltage
Intermediate reference voltage
Reference voltage input (BOTTOM)
Reference voltage power supply (BOTTOM)
Power supply for analog circuits
Analog signal input
3
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MN65771F A/D, D/C Converters for Image Signal Processing
Pin Descriptions (continued)
Pin No. Symbol Function Description
41 N.C. No connection
42 N.C. No connection
43 AV
44 DV
45 DV
SS
SS
DD
46 UNDF Underflow output
47 OVF Overflow output
48 N.C. No connection
Absolute Maximum Ratings Ta=25˚C
Parameter Symbol Rating Unit
Power supply voltage V
Input voltage V
Output voltage V
Operating ambient temperature T
Storage temperature T
Recommended Operating Conditions
Parameter Symbol min typ max Unit
Power supply voltage V
Power supply voltage for digital output circuits DV
Digital input "H" level V
voltage "L" level V
Reference voltage "H" level V
Clock "H" level pulse width t
Analog input voltage V
Electrical Characteristics V
Parameter Symbol Conditions min typ max Unit
Power consumption P
Resolution RES 10 bit
Linearity error E
Differential linearity error E
Maximum conversion rate F
Clock frequency f
Analog input dynamic range D
Output "H" level I
current "L" level I
Output delay time t
Analog input capacitance C
Sampling delay t
Ground for analog circuits
Ground for digital circuits
Power supply for digital circuits
"L" level V
"L" level pulse width t
=AVDD=DVDD=3.0V , AVSS=DVSS=0V, Ta=25˚C
DD
FC=20MSPS
C
(not including reference current)
f
L
D
C(max.)
CLK
R
OH
OL
d
I
sd
=18MSPS ±1.3 ±2.5 LSB
CLK
VRT=4.0V
VBB=2.0V
VOH=V
DD
VOL=0.4V 1.5 mA
CL=20pF 10 20 30 ns
DD
I
O
opr
stg
VDD=AVDD=DVDD=5.0V, DV
DD
DDL
IH
IL
RT
RB
WH
WL
AIN
– 0.3 to +7.0 V
– 0.3 to V
– 0.3 to V
+0.3 V
DD
+0.3 V
DD
–20 to +70 ˚C
–55 to +125 ˚C
=3.3V, VSS=AVSS=DVSS=0V, Ta=25˚C
DDL
4.50 5.00 5.50 V
3.00 3.30 5.50 V
2.4 V
V
SS
DD
0.8 V
4.0 V
2.0 V
25 ns
25 ns
V
SS
V
DD
115 200 mW
±1.0 ±1.5 LSB
18 MSPS
1 18 MHz
2V
RT
– V
RB
– 0.8V –1.5 mA
15 pF
7ns
V
V
V
4
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A/D, D/C Converters for Image Signal Processing MN65771F
Timing Chart
The chip samples the analog input at the falling edge of the clock signal and provides the corresponding digital
output 2.5 clock cycles later at the rising edge of the clock signal.
t
WHtWL
Clock
Analog input
Data output
Note: The circles indicate analog signal sampling points.
t
sd
N
(7ns)
N+1
N+2
N+3
N–3 N–2 N–1 N+1N
(20ns)
t
d
N+4
5
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MN65771F A/D, D/C Converters for Image Signal Processing
Package Dimensions (Unit:mm)
QFH048-P-0707
9.0±0.2
±0.2
7.0
36 25
37
48
(0.75)
24
(0.75)
7.0±0.2
9.0±0.2
13
1
0.5
12
0.2±0.1
(1.0)
±0.20.1±0.1
2.5
0.1
0.05
-
+0.10
2.9 max.
0.15
0.5±0.2
0 to 10°
SEATING PLANE
6
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