Page 1
For Information Equipment
MN89302
SVGA Display Controller
Overview
The MN89302 is an LCD/CRT display controller with
IBM™ VGA-compatible registers. It features all the necessary interfaces for a compact display system: ISA bus interface, local bus interface, DRAM interface, and LCD panel
interface. The built-in graphics acceleration functions include
support for bit-block transfers (BITBLT) and hardware cursor.
Note: IBM™ and VGA are registered trademarks of International
Business Machines Corporation.
Features
Monochrome STN LCD panel support
Maximum display size: 800 × 600
Support for single and dual panels
32-monochrome gradation
Color STN LCD panel support
Maximum display size: 800 × 600
Support for single and dual panels
32-gradation for each color (RGB)
Color TFT LCD panel support
Maximum display size: 800 × 600
5-bit output for red and blue; 6-bit output for green
Maximum number of colors in concurrent display
320 × 240: 64k (TFT, STN)
640 × 480: 256/260K palette (TFT, STN)
800 × 600: 256/260K palette (TFT, STN)
Built-in graphics acceleration functions
• Bit-block transfers (BITBLT) to and from
host video memory and within video memory
• Hardware cursor (16 × 16 or 32 × 32)
Built-in automatic display centering
Built-in gradation control table (rewritable) for
optimizing gradation to match panel
DRAM interface with 16-bit bus
• Support for 2CAS/2WE mode
• Refresh control
Host interfaces
• ISA bus (16-bit)
• i386/i486 local bus (16-bit)
Note: i386 and i486 are trademarks of Intel Corporation.
Applications
Point-of-sale terminals, Factory automation terminals,
word processors, and other terminals
Page 2
MN89302 For Information Equipment
Pin Assignment
ISA bus mode
VDDGND
LCAS
UCASWERAS
GND
MA9
MA8
MA7
MA6
MA5
MA4
MA3
MA2
MA1
MA0
VDDGND
UD7
UD6
UD5
UD4
UD3
UD2
UD1
UD0
VDDGND
LD7
LD6
LD5
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
GND
V
DD
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
96959493929190898887868584838281807978777675747372717069686766
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
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65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
LD4
LD3
LD2
LD1
LD0
V
DD
GND
DCLK
LP
FP
DISP
V
DD
GND
LOGICON
LCDON
BACKON
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
V
DD
SA0
GND
SD8
SD9
SD10
SD11
SD12
32
SA16
SA17
SA18
SA19
A20
A21
XIN
GND
GND
XOUT
TEST
RESET
MINTEST
SCANTEST
QFP128-P-1818
GND
MEMR
IOCS16
REFRESH
(TOP VIEW)
DD
SA1
V
MEMW
MEMCS16
IORD
IOWR
BIOSEN
IOCHRDY
AEN
GND
SBHE
SD15
SD14
SD13
Page 3
For Information Equipment MN89302
Block Diagram
UD[7:0]
LD[7:0]
BACKON
LCDON
LOGICON
LP
FP
DISP
DCLK
XIN
RESET
TEST/MINTEST
Address[21:0]
SD[15:0]
AEN
SBHE
IOWR
IORD
SMEMW
SMEMR
IOCHRDY
REFRESH
MEMCS 16
IOCS 16
8
13
12/14
27
28
24
25
22
16
23
15
19
18
Gray scale
engine
49
50
51
56
55
54
57
LCD panel
controller
RAM table
LCD/CRT
Hardware
cursor
Attribute
control
Video FIFO
controller
Host
interface
BITBLT
Memory
write
buffer
Memory
interface
Access
attributer
Graphics
controller
91
93
94
92
26
MA[9:0]
MD[15:0]
RAS
UCAS
LCAS
WE
BIOSEN
Page 4
MN89302 For Information Equipment
Pin Descriptions
Pin No. Symbol I/O Level Function Description
27 AEN I TTL Address Enable
"H" level input from this pin indicates that a DMA transfer is in
progress, so the chip does not respond to I/O access.
28 SBHE I TTL Byte High Enable
This input indicates the state of the 16-bit bus.
24 IOWR I TTL I/O Write
This input indicates an I/O write request.
25 IORD I TTL I/O Read
This input indicates an I/O read request.
22 SMEMW I TTL Memory Write
This input indicates a memory write request dedicated for an
address space in the first megabyte (000000 to 0FFFFFH).
16 SMEMR I TTL Memory Read
This input indicates a memory read request dedicated for an
address space in the first megabyte (000000 to 0FFFFFH).
6 to 5 A[21:20] I TTL Address[21:20]
These inputs give the address 21:20.
4 to 1, SA[19:0] I TTL Address[19:0]
128 to 115, These inputs give the address 19:0.
21 ,39
30 to 48 SD[15:0] I/O TTL Data[15:0]
These pins represent the host data bus.
23 IOCHRDY I/O TTL I/O Channel Ready
This pin is "L" level when I/O or memory access is given wait
states.
19 MEMCS16 O TTL Memory Chip Select 16
This output indicates to the system that 16-bit memory access is
available.
18 IOCS16 O TTL I/O Chip Select 16
This output indicates to the system that 16-bit I/O access is
available.
15 REFRESH I TTL Refresh
"L" level input indicates that the system is refreshing its DRAM.
89 to 80 MA[9:0] I/O CMOS Memory Address
These outputs give the address of the display memory .
91 RAS O CMOS Row Address Strobe (RAS).
This output is the strobe signal for the row address latch.
93 UCAS O CMOS Upper Column Address Strobe (UCAS)
This output is the strobe signal for the upper column address
latch. In the 2WE mode, however, it functions as the CAS
signal.
Page 5
For Information Equipment MN89302
Pin Descriptions (continued)
Pin No. Symbol I/O Level Function Description
94 LCAS O CMOS Lower Column Address Strobe (LCAS)
This output is the strobe signal for the lower column address
latch. In the 2WE mode, however, it functions as the LWE
signal.
92 WE O CMOS Write Enable
This output is the data write signal. In the 2WE mode, however,
it functions as the UWE signal.
112 to 97 MD[15:0] I/O TTL Memory Data
These pins represent the data bus to the DRAM.
26 BIOSEN O CMOS BIOS Enable
This output enables ROM BIOS output.
49 BACKON O CMOS Backlight ON
This output requests backlighting.
"L" level: OFF; "H" level: ON
50 LCDON O CMOS LCD Drive ON
This output requests power-ON for the LCD panel.
"L" level: OFF; "H" level: ON
51 LOGICON O CMOS LCD Logic ON
This output requests power-ON for LCD panel logic circuits.
"L" level: OFF; "H" level: ON
56 LP O CMOS Line Pulse
This output provides pulses indicating the end of a line of the
LCD panel.
55 FP O CMOS Frame Pulse
This output provides pulses indicating the start of a frame of the
LCD panel.
54 DISP O CMOS Display Enable
This output enables the LCD display. An external RAMDAC
uses this signal as a blanking signal. A TFT LCD uses it as an
enable signal.
57 DCLK O CMOS Data Shift Clock
This pin provides a data shift clock signal for an STN LCD panel
or a dot clock signal for a TFT LCD panel or external RAMDAC.
77 to 70 UD[7:0] O CMOS Upper Data[7:0]
67 to 60 LD[7:0] O CMOS Lower Data[7:0]
This pins provide display data. Usage varies with the LCD panel
type.
Page 6
MN89302 For Information Equipment
Pin Descriptions (continued)
Pin No. Symbol I/O Level Function Description
13 RESET I CMOS Reset
"H" level input from this pin reset and initializes the chip. If the
host is in a i386 mode, the chip aligns the clock phase with this
signal.
81 to 80 MA[1:0] I CMOS Host Type
During a reset, these pins select the host type.
MA[1:0] Host Type
0 0 ISA
0 1 i386SX
1 0 i386DX
1 1 i486
12/14 TEST/ CMOS Chip Test Condition
MINTEST
11 SCANTEST This pin selects the chip test mode.
8/9 XIN/XOUT I/O Clock IN/OUT
These pins are the clock I/O pins. Connect them to a crystal
oscillator.
Absolute Maximum Ratings
Parameter Symbol Ratings Unit
Power supply voltage V
Input pin voltage V
Output pin voltage V
Power dissipation P
Operating ambient temperature T
Storage temperature T
DD
I
O
D
opr
stg
– 0.3 to +7.0 V
– 0.3 to VDD+0.3 V
– 0.3 to VDD+0.3 V
1000 mW
0 to 70 ˚C
–55 to +150 ˚C
Recommended Operating Conditions
Parameter Symbol Conditions min typ max Unit
Power supply voltage V
DD
Ambient temperature Ta 0 70 ˚C
Rise time for input t
Fall time for input t
Operating frequency f
Operating frequency f
r
f
At character clock of 8 XIN 30 MHz
opr1
At character clock less than 8 XIN 25 MHz
opr2
4.75 5.00 5.25 V
0 150 ns
0 150 ns
Page 7
For Information Equipment MN89302
Electrical Characteristics
VDD=4.75 to 5.25V, VSS=0.00V, f=30MHz, Ta=0 to 70˚C
Parameter Symbol Conditions min typ max Unit
Power supply current I
during operation
Power supply current I
in the SUSPEND mode
Power supply current I
in the STANDBY mode
"H" level input voltage 1 V
AEN ,SBHE ,IOWR ,IORD ,
SMEMW ,SMEMR ,
REFRESH ,A21 to 20 ,
SA19 to 0 ,SD15 to 0 ,
MD15 to 0 ,BIOSEN ,
IOCHRDY
"H" level input voltage 2 V
TEST ,MINTEST ,
SCANTEST ,RAS ,UCAS ,
LCAS ,BACKON ,LCDON ,
LOGICON ,MA9 to 0 ,
RESET
"L" level input voltage 1 V
AEN ,SBHE ,IOWR ,IORD ,
SMEMW ,SMEMR ,
REFRESH ,A21 to 20 ,
SA19 to 0 ,SD15 to 0 ,
MD15 to 0 ,BIOSEN ,
IOCHRDY
"L" level input voltage 2 V
TEST ,MINTEST ,
SCANTEST ,RAS ,UCAS ,
LCAS ,BACKON ,LCDON ,
LOGICON ,MA9 to 0 ,
RESET
Input leakage current 1 I
TEST ,MINTEST ,
SCANTEST
Input leakage current 2 I
AEN ,SBHE ,IOWR ,IORD ,
SMEMW ,SMEMR ,
REFRESH ,A21 to 20 ,
SA19 to 0 ,RESET
VI=VDD or VSS ,VDD=5.0V 160 mA
DD0
VI=VDD or VSS ,VDD=5.0V 15 mA
DD1
VI=VDD or VSS ,VDD=5.0V 75 mA
DD2
IH1
IH2
IL1
IL2
LI1
LI2
VI=VDD or V
VI=VDD or V
SS
SS
2.0 V
V
× 0.7 V
DD
0 0.8 V
0V
DD
DD
× 0.3 V
DD
±20 µA
±10 µA
V
V
Page 8
MN89302 For Information Equipment
Electrical Characteristics (continued)
VDD=4.75 to 5.25V, VSS=0.00V, f=30MHz, Ta=0 to 70˚C
Parameter Symbol Conditions min typ max Unit
Pull-down resistance R
"H" level output voltage 1 V
BACKON ,LCDON , V
LOGICON ,SD15 to 0 ,
MD15 to 0 ,BIOSEN
"H" level output voltage 2 V
WE ,MA9 to 0 ,RAS , V
UCAS ,LCAS
"H" level output voltage 3 V
DCLK ,DISP ,LP ,FP , V
UD7 to 0 ,LD7 to 0
"H" level output voltage 4 V
IOCHRDY VI=VDD or V
"H" level output voltage 5 V
IOCS16 ,MEMCS16 VI=VDD or V
"L" level output voltage 1 V
BACKON ,LCDON , V
LOGICON ,MD15 to 0
"L" level output voltage 2 V
SD15 to 0 ,MA9 to 0 ,RAS , V
UCAS ,LCAS ,WE ,BIOSEN
"L" level output voltage 3 V
DCLK ,DISP ,LP ,FP , V
UD7 to 0 ,LD7 to 0
"L" level output voltage 4 V
IOCHRDY VI=VDD or V
"L" level output voltage 5 V
IOCS16 ,MEMCS16 VI=VDD or V
Output leakage current I
IOCS16 ,BACKON , V
MA9 to 0 ,MEMCS16 , VO=VDD or V
UCAS ,LCAS ,RAS ,
LOGICON ,LCDON ,
SD15 to 0 ,MD15 to 0 ,
BIOSEN ,IOCHRDY
VI=VDD ,VDD=5.0V 30 kΩ
PD1
OH1IO
OH2IO
OH3IO
OH4IO
OH5IO
OL1IO
OL2IO
OL3IO
OL4IO
OL5IO
LO
=–2.0mA VDD– 0.6 V
or V
I=VDD
SS
=–4.0mA VDD– 0.6 V
or V
I=VDD
SS
=–8.0mA VDD– 0.6 V
or V
I=VDD
SS
=–12.0mA VDD– 0.6 V
SS
=–16.0mA V
SS
– 0.6 V
DD
=2.0mA 0.4 V
or V
I=VDD
SS
=4.0mA 0.4 V
or V
I=VDD
SS
=8.0mA 0.4 V
or V
I=VDD
SS
=12.0mA 0.4 V
SS
=16.0mA 0.4 V
SS
VO=High-impedance state ±10 µA
or V
I=VDD
SS
SS
Page 9
For Information Equipment MN89302
Timing Chart for LCD Panel Outputs
FP
LP
DCLK
R1 B3 R1 B3 G6G638LD7/UD7
G1 R4 G1 R4G4B6B638LD6/UD6
B1 G4 B1 R7R639LD5/UD5
R2 B4 R2 B4 G7G639LD4/UD4
G2 R5 G2 R5 B7B639LD3/UD3
B2 G5 B2 G5 R8R640LD2/UD2
R3 B5 R3 B5 G8G640LD1/UD1
G3
R6 G3 R6 B8B640LD0/UD0
FP
LP
UD
LD
240 lines 1 line 2 lines 3 lines 4 lines 5 lines
480 lines
241 lines 242 lines 243 lines 244 lines 245 lines
1 line
2 lines
·
·
·
·
·
240 lines
241 lines
242 lines
·
·
·
·
·
·
·
480 lines
1
R1
G1
UD7
R1
LD7G1LD6B1LD5R2LD4G2LD3B2LD2R3LD1G3LD0B3LD7
B1
UD6
UD5R2UD4G2UD3B2UD2R3UD1G3UD0B3UD7
First byte of data
First byte of data
2 3
Upper screen
Lower screen
R640
UD2
R640
LD2
640
G640
UD1
G640
LD1
B640
UD0
B640
LD0
Page 10
MN89302 For Information Equipment
Application Circuit Example
BIOS
RESET
Address[21:0]
SD[15:0]
AEN
SBHE
IOWR
IORD
SMEMW
SMEMR
REFRESH
IOCHRDY
MEMCS16
IOCS16
CE(20)
XIN
MN89302
BIOSENWELCAS
XOUT
UCAS
RAS
BIOSEN
MD[15:0]
UD[7:0]
LD[7:0]
BACKON
LCDON
LOGICON
DISP
DCLK
MA[9:0]
LCD
panel
LP
FP
ISA bus
4MDRAM
Page 11
For Information Equipment MN89302
Package Dimensions (Unit: mm)
QFH128-P-1818
20.0±0.2
18.0
±0.2
96 65
97
(1.25)
64
(1.25)
18.0±0.2
20.0±0.2
33128
132
–0.05
+0.10
1.0±0.2
0.5
0.2±0.1
3.3±0.2
3.4±0.3
0.15
0.1
SEATING PLANE
0.1±0.1
0.5±0.2
0 to 10°
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