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A/D, D/C Converters for Image Signal Processing
MN65752H
Low Power 8-Bit, 2-Channel CMOS A/D Converter for Image Processing
Overview
The MN65752H is an 8-bit, 2-channel CMOS analog-
to-digital converter for image processing applications.
It uses a half flash structure based on chopper comparators and achieves both high speed and low power
consumption with multiplexing.
It provides separate power supply pins for the circuits
driving the low-voltage digital output pins.
Features
Maximum conversion rate: 20 MSPS (min.)
Linearity error: ±0.9 LSB (typ.)
Differential linearity error: ±0.5 LSB (typ.)
Power supply voltage: 3.6 V or 2.6 V
Power consumption: 50 mW (typ.) (f
=16 MHz)
CLK
Applications
Digital television receivers
Digital video equipment
Digital image processing equipment
Pin Assignment
RBSOVRBB
V
3635343332313029282726
RTB
DD
INB
DD
INA
DD
RTA
37
38
39
40
41
SS
42
43
SS
44
SS
45
46
47
48
1234567891011
RBA
RBSA
V
V
QFH048-P-0707
V
AV
AV
AV
AV
AV
AV
V
V
RTSB
V
V
V
RTSA
DVDDDVSSNPOWDB
DVSSCLK
SS
SS
DD
DV
DV
DV
TEST1
NPOWDA
(TOP VIEW)
NOE
DB7
DA0
TEST2
DB6
DA1
DB5
DA2
DB4
25
24
23
22
21
20
19
18
17
16
15
14
13
12
DA3
DB3
DB2
DB1
DB0
DV
DV
DV
DV
DA7
DA6
DA5
DA4
DD
DDL
DDL
DD
1
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MN65752H A/D, D/C Converters for Image Signal Processing
Block Diagram
V
V
AV
AV
AV
AV
AV
V
AV
V
V
RTSB
RTB
DD
V
INB
DD
INA
DD
RTA
RTSA
RBSBVRBB
V
36
SS
DVDDDV
35
34
33
NPOWDB
32
SS
DV
30
CLK
NOE
293128
DB6
DB7(MSB)
27
DB5
DB4
26
25
DB3
24
37
Data latch
38
39
Clock generator
40
SS
41
Encoder
42
SS
43
SS
44
(4 bits)
Encoder
(4 bits)
Upper
comparator
(4 bits)
Upper
comparator
(4 bits)
Reference
resistor
Reference
resistor
Lower comparator (4 bits)Lower comparator (4 bits)
Encoder (4 bits)Encoder (4 bits)
(Channel A) (Channel B)
45
Clock generator
46
47
Data latch
23
22
21
20
19
18
17
16
15
14
DB2
DB1
DB0(LSB)
DV
DD
DV
DD
DV
DD
DV
DD
DA7(MSB)
DA6
DA5
48
DA4
13
1
RBSA
V
2
3
4
SS
DD
RBA
V
DV
DV
6
5
NPOWDA
SS
DV
7
TEST1
8
TEST2
9
(LSB)DA0
10
DA1
11
DA2
12
DA3
2
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A/D, D/C Converters for Image Signal Processing MN65752H
Pin Descriptions
Pin No. Symbol Function Description
1V
2V
RBSA
RBA
3DVDDPower supply for digital circuits
4DVSSGround for digital circuits
5 NPOWDA Power down mode selection
6DVSSGround for digital circuits
7 TEST1 Test mode selection
8 TEST2 Test mode selection
9 DA0 Digital code output (LSB)
10 DA1 Digital code output
11 DA2 Digital code output
12 DA3 Digital code output
13 DA4 Digital code output
14 DA5 Digital code output
15 DA6 Digital code output
16 DA7 Digital code output (MSB)
17 DV
18 DV
19 DV
20 DV
DD
DDL
DDL
DD
21 DB0 Digital code output (LSB)
22 DB1 Digital code output
23 DB2 Digital code output
24 DB3 Digital code output
25 DB4 Digital code output
26 DB5 Digital code output
27 DB6 Digital code output
28 DB7 Digital code output (MSB)
29 NOE Digital output enable
30 CLK Sampling clock
31 DV
SS
32 NPOWDB Power down mode selection
33 DV
34 DV
35 V
36 V
37 V
38 V
39 AV
40 V
SS
DD
RBB
RBSB
RTSB
RTB
DD
INB
Reference voltage power supply (BOTTOM)
Reference voltage input (BOTTOM)
Power supply for digital circuits
Power supply for low-voltage digital outputs
Power supply for low-voltage digital outputs
Power supply for digital circuits
Ground for digital circuits
Ground for digital circuits
Power supply for digital circuits
Reference voltage input (BOTTOM)
Reference voltage power supply (BOTTOM)
Reference voltage power supply (TOP)
Reference voltage input (TOP)
Power supply for analog circuits
Ground for analog circuits
3
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MN65752H A/D, D/C Converters for Image Signal Processing
Pin Descriptions (continued)
Pin No. Symbol Function Description
41 AV
42 AV
43 AV
44 AV
45 V
46 AV
47 V
48 V
SS
DD
SS
SS
INA
DD
RTA
RTSA
Absolute Maximum Ratings Ta=25˚C
Parameter Symbol Rating Unit
Power supply voltage V
Power supply voltage for digital output circuits DV
Input voltage V
Output voltage V
Operating ambient temperature T
Storage temperature T
Ground for analog circuits
Power supply for analog circuits
Ground for analog circuits
Ground for analog circuits
Analog signal input
Power supply for analog circuits
Reference voltage input (TOP)
Reference voltage power supply (TOP)
DD
DDL
I
O
opr
stg
– 0.3 to +7.0 V
– 0.3 to VDD+0.3 V
– 0.3 to VDD+0.3 V
– 0.3 to VDD+0.3 V
–20 to +70 ˚C
–55 to +125 ˚C
Recommended Operating Conditions
VDD=AVDD=DVDD=3.6V, DV
=2..6V, VSS=AVSS=DVSS=0V, Ta=25˚C
DDL
Parameter Symbol min typ max Unit
Power supply voltage V
Power supply voltage for digital output circuits DV
Digital input "H" level V
voltage "L" level V
Reference voltage "H" level V
"L" level V
Clock "H" level pulse width t
"L" level pulse width t
Analog input voltage V
Electrical Characteristics V
=AVDD=DVDD=3.6V, DV
DD
DD
DDL
IH
IL
RT
RB
WH
WL
AIN
3.30 3.60 5.25 V
2.50 2.60 5.25 V
V
× 0.55 V
DD
V
SS
2.80 V
V
SS
1.30 V
DD
V
× 0.2 V
DD
DD
20 ns
20 ns
V
SS
=2.6V , AVSS=DVSS=0V, Ta=25˚C
DDL
V
DD
Parameter Symbol Conditions min typ max Unit
Power consumption P
f
C
= 16 MSPS
CLK
(not including reference current)
50 90 mW
Resolution RES 8 bit
Linearity error E
Differential linearity error E
Maximum conversion rate F
C(max.)
Clock frequency f
Analog input dynamic range D
Output "H" level I
current "L" level I
Output delay time t
Analog input capacitance C
f
L
D
=20MSPS ±0.9 ±1.8 LSB
CLK
VRT=2.8V, VRB=1.3V ±0.5 ±1.0 LSB
20 MSPS
CLK
R
VOH=DV
OH
VOL=0.4V 1.5 mA
OL
CL=20pF 10 25 40 ns
d
I
– 0.8V –1.5 mA
DDL
1 20 MHz
1.5 V
15 pF
RT –VRB
4
V
V
V
V
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A/D, D/C Converters for Image Signal Processing MN65752H
Timing Chart
The chip samples the analog input at the falling edge of the clock signal and provides the corresponding digital
output 2.5 clock cycles later at the rising edge of the clock signal.
t
WHtWL
Clock
Analog input
Data output
Note: The circles indicate analog signal sampling points.
N
N–3 N–2 N–1 N+1N
(25ns)
t
d
N+1
N+2
N+3
N+4
5
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MN65752H A/D, D/C Converters for Image Signal Processing
Package Dimensions (Unit:mm)
QFH048-P-0707
9.0±0.2
±0.2
7.0
36 25
37
48
(0.75)
24
(0.75)
7.0±0.2
9.0±0.2
13
1
0.5
12
0.2±0.1
(1.0)
±0.20.1±0.1
2.5
0.1
0.05
-
+0.10
2.9 max.
0.15
0.5±0.2
0 to 10°
SEATING PLANE
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