Apple MACBOOK AIR 11 A1465 Schematics

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

7

3456

REV ECN

DESCRIPTION OF REVISION

12

CK APPD

DATE

<ECO_DESCRIPTION>

J110 MLB SCHEMATIC

09/25/14

D

C

B

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

(.csa)

Contents

1

1 2 3 4 5 6 7 8 9

Table of Contents

2

BOM Configuration

3

BOM Variants

4

PD Parts

5

CPU GFX/NCTF/RSVD

6

CPU Misc/JTAG/CFG/RSVD

7

CPU DDR3/LPDDR3 Interfaces

8

CPU/PCH POWER

9

CPU/PCH GROUNDS

10

CPU Decoupling

12

PCH Decoupling

13

PCH Audio/JTAG/SATA/CLK

14

PCH PM/PCI/GFX

15

PCH PCIe/USB/LPC/SPI/SMBus

16

PCH GPIO/MISC/LPIO

18

CPU/PCH Merged XDP

19

Chipset Support

20

Project Chipset Support

22

DDR3 VREF MARGINING

23

LPDDR3 DRAM Channel A (0-31)

24

LPDDR3 DRAM Channel A (32-63)

25

LPDDR3 DRAM Channel B (0-31)

26

LPDDR3 DRAM Channel B (32-63)

27

LPDDR3 DRAM Termination

28

Thunderbolt Host (1 of 2)

29

Thunderbolt Host (2 of 2)

30

TBT Power Support

32

Thunderbolt Connector A

35

Wireless Connector

37

SSD Connector

39

Camera 1 of 2

40

Camera 2 of 2

46

External A USB3 Connector

48

IPD Connector

50

SMC

MASTER

J43_MLB

MASTER

WILL_J43

J43_MLB

LABEL_J41

WILL_J43

J43_MLB

WILL_J43

J43_MLB1

J43_MLB

WILL_J43

MASTER

J43_MLB

T29_RR

WILL_J43

T29_RR

J43_MLB

J43_MLB1

J43_MLB

WILL_J43

D

C

B

Page

TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

Date Date

Sync

MASTER

01/17/2013

MASTER

09/13/2012

10/02/2012

01/11/2013

09/13/2012

12/17/2012

02/20/2013

09/13/2012

01/14/2013

12/17/2012

01/09/2013

01/17/2013

02/04/2013

MASTER

09/21/2012

01/19/2013

12/17/2012

10/26/2012

10/02/2012

02/20/2013

01/09/2013

09/14/2012

02/20/2013

01/17/2013

12/17/2012

Page Sync

TABLE_TABLEOFCONTENTS_ITEM

36 37 38 39 40 41 42

44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73

(.csa)

Contents

51

SMC Shared Support

52

SMC Project Support

53

SMBus Connections

54

High Side Current Sensing

55

Voltage & Load Side Current Sensing

56

Debug Sensors 1

58

Thermal Sensors

60

Fan43

61

SPI Debug Connector

64

Audio: Speaker Amp

69

Battery Connector & Hall Effect

70

DC-In & G3H Supply

71

PBus Supply & Battery Charger

72

CPU VR12.6 VCC Regulator IC

73

CPU VR12.5 VCC Power Stage

74

LPDDR3 Supply

75

5V S4RS3 / 3.3V S5 Power Supply

76

1.05V S0 Power Supply

77

LCD/KBD Backlight Driver

78

Misc Power Supplies

80

Power FETs

81

Power Control

83

Internal DisplayPort Connector

95

LIO Connector

100

Power Aliases

102

Signal Aliases

104

Func Test / No Test

105

Project FCT/NC/Aliases

110

PCB Rule Definitions

111

CPU Constraints

112

PCH Constraints 1

113

PCH Constraints 2

114

Memory Constraints

115

Thunderbolt Constraints

116

Camera Constraints

117

SMC Constraints

118

Project Specific Constraints

120

Reference

WILL_J43

J43_MLB

SID_J41

J43_MLB

YHARTANTO_J44

J43_MLB

MASTER

J43_MLB

CLEAN_J41

WILL_J43

MASTER

WILL_J43

MASTER

J43_MLB

CLEAN_J41

J43_MLB

CHINMAY_J41

J43_MLB

MASTER

12/17/2012

02/20/2013

09/28/2012

02/26/2013

02/20/2013

09/13/2012

01/09/2013

09/04/2012

MASTER

09/13/2012

09/14/2012

10/09/2012

09/21/2012

09/17/2012

10/02/2012

09/10/2012

09/13/2012

10/04/2012

09/16/2012

09/11/2012

11/13/2012

12/17/2012

MASTER

12/17/2012

MASTER

10/24/2012

09/21/2012

11/13/2012

09/14/2012

09/07/2012

09/13/2012

MASTER

A

Schematic / PCB #’s

PART NUMBER

051-00384

820-00164

DRAWING

TITLE=MLB

ABBREV=DRAWING

LAST_MODIFIED=Thu Sep 25 10:26:20 2014

ALIASES RESOLVED

QTY

DESCRIPTION

SCHEM,MLB,J110

PCBF,MLB,J110

8

REFERENCE DES

SCH1

PCB1

CRITICAL

BOM OPTION

7 6 5 4 2 1

PRODUCT SAFETY REQUIREMENTS: PCB, UL RECOGNIZED, MIN. 130-C TEMP. RATING AND V-0 FLAME RATING PER UL 796 & UL 94. PCB TO BE SILK-SCREENED WITH UL/CUL RECOGNITION MARK, MANUFACTURER’S UL FILE NUMBER, UL PCB MATERIAL DESIGNATION, 130-C TEMP. RATING AND V-0 FLAME RATING.

SIZE

A

D

DRAWING TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

<PART_DESCRIPTION>

Apple Inc.

R

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

1 OF 120

SHEET

1 OF 73

3

8 7 6 5 4 3

12

BOM Groups

BOM GROUP

MLB_COMMON

MLB_MISC

MLB_DEVEL:ENG

MLB_DEVEL:PVT

MLB_DEBUG:ENG

MLB_DEBUG:PVT

D

MLB_DEBUG:PROD

Current Sensor Configuration

BOM GROUP

ISNS:ENG

ISNS:PROD

CPU DRAM SPD Straps

BOM GROUP

DDR3:HYNIX_4GB

DDR3:HYNIX_8GB

DDR3:SAMSUNG_4GB

DDR3:SAMSUNG_8GB

DDR3:ELPIDA_4GB

DDR3:ELPIDA_8GB

DDR3:MICRON_4GB

DDR3:MICRON_8GB

C

DDR3:HYNIX_16GB

DDR3:SAMSUNG_16GB

DDR3:ELPIDA_16GB

DDR3:MICRON_16GB

Programmable Parts

PART NUMBER

335S0915

341S00159

338S1214

335S00006

335S00007

341S00153

QTY

1

PP5V5_DCIN:NO,TBTHV:P15V,EDP,CAM_XTAL:NO,CAM_WAKE:NO,APCLKRQ:ISOL,TPAD_INTWAKE:SHARED,USB_PWR:S3,SD_ON_MLB,VCORE_FETS,SSD_LPSR:S3

CPU_HS_ISNS:YES,CPUVR_ISNS:YES,DRAM_ISNS:YES,P1V05_ISNS:YES,AIRPORT_ISNS:YES,SSD_ISNS:YES,LCDBKLT_ISNS:YES,P3V3S5_ISNS:YES,3V3S0_ISNS:YES,OTHER_HS_ISNS:YES,CAM_ISNS:YES,CPUDDR_ISNS:YES,PANEL_ISNS:YES

CPU_HS_ISNS:YES,CPUVR_ISNS:YES,DRAM_ISNS:YES,P1V05_ISNS:NO,AIRPORT_ISNS:NO,SSD_ISNS:YES,LCDBKLT_ISNS:NO,P3V3S5_ISNS:NO,3V3S0_ISNS:NO,OTHER_HS_ISNS:NO,CAM_ISNS:NO,CPUDDR_ISNS:NO,PANEL_ISNS:NO

DESCRIPTION

EEPROM,4MBIT,SPI,50MHZ,1.8V,USON8

T29,EEPROM,FALCON RIDGE(V27.1), PROtO 0,J110/J113

IC,SMC12-B1,40MHZ/50DMIPS MCU,157BGA

IC,SERIAL FLASH,64 MBIT 3V,WSON,QE=1

IC,EFI ROM(V0108), PROTO 0,J110/J113

BOM OPTIONS

ALTERNATE,COMMON,MLB_MISC,MLB_DEBUG:PVT,MLB_PROGPARTS

ALTERNATE,BKLT:ENG,XDP_CONN,DDRVREF_DAC,S0PGOOD_ISL,DBGLED,ISNS:ENG

XDP_CONN

XDP,SAMCONN

BKLT:PROD,XDP,SAMCONN,ISNS:ENG,DBGLED,XDP_CONN

BKLT:PROD,SAMCONN,XDP,ISNS:PROD

BOM OPTIONS

RAMCFG0:L,RAMCFG1:L,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:HYNIX_4GB

RAMCFG0:L,RAMCFG1:L,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:HYNIX_8GB

RAMCFG0:L,RAMCFG1:H,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:SAMSUNG_4GB

RAMCFG0:L,RAMCFG1:H,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:SAMSUNG_8GB

RAMCFG0:H,RAMCFG1:H,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:ELPIDA_4GB

RAMCFG0:H,RAMCFG1:H,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:ELPIDA_8GB

RAMCFG0:H,RAMCFG1:L,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:MICRON_4GB

RAMCFG0:H,RAMCFG1:L,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:MICRON_8GB

RAMCFG0:L,RAMCFG1:L,RAMCFG2:L,RAMCFG3:H,DRAM_TYPE:HYNIX_16GB

RAMCFG0:L,RAMCFG1:H,RAMCFG2:L,RAMCFG3:H,DRAM_TYPE:SAMSUNG_16GB

RAMCFG0:H,RAMCFG1:H,RAMCFG2:L,RAMCFG3:H,DRAM_TYPE:ELPIDA_16GB

RAMCFG0:H,RAMCFG1:L,RAMCFG2:L,RAMCFG3:H,DRAM_TYPE:MICRON_16GB

REFERENCE DES

U2890

U5000

U6100

CRITICAL

BOM OPTION

TBTROM:BLANK

TBTROM:PROG

SMC:BLANK

BOOTROM_MAC:BLANK

BOOTROM_NUM:BLANK

BOOTROM:PROG

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

CPU DRAM CFG Chart

VENDOR

HYNIX

SAMSUNG

MICRON

ELPIDA

SIZE

4GB

8GB

16GB

RSVD

CFG 1

1 0

0 1

1

CFG 3

0

1

CFG 0

00

1

CFG 2

0

1

0

1

Alternate Parts

PART NUMBER

376S1032 376S0855

376S1129

376S1089

372S0186

152S1821

197S0480

197S0481 197S0343

107S0254 107S0241

353S3452

128S0386

128S0397 128S0325

376S00014

107S0255 107S0240

870-5074 870-1938

860-3690

ALTERNATE FOR PART NUMBER

376S0855

376S1128

138S0660138S0684

138S0648138S0703

152S1301152S0586

372S0185

197S0478197S0479

376S0604376S1053

371S0558371S0713

128S0376128S0371

152S1757

197S0343

353S1286

128S0284

377S0104377S0155

128S0220128S0398

197S0544197S0542

197S0544197S0545

138S0638138S0681

138S0638138S0841

376S0761

152S1804152S1876

107S0248107S0250

870-1940870-5071

860-1327860-3428

860-1328

333S0677333S0787

333S0681333S0785

BOM OPTION

DRAM_TYPE:HYNIX_4GB

DRAM_TYPE:HYNIX_8GB

REF DES

ALL

COMMENTS:

Toshiba alt for Diodes dual

NXP alt for Diodes dual

NXP alt for Diodes single

Murata alt to Taiyo Yuden

Dale/Vishay alt to Cyntec

NXP alt to Diodes

200uW Epson alt to NDK

Diodes alt to Fairchild

Diodes alt to ST Micro

Kemet alt to Sanyo

Cyntec alt to NEC

NDK crystal alt to TXC

Epson crystal alt to TXC

Cyntec sense R alt to TFT

Maxim alt to Microchip

Kemet alt to Sanyo

OnSemi alt to Infineon

Kemet alt to Sanyo

NDK alt to TXC

Epson alt to TXC

Taiyo alt to Samsung

Murata alt to Samsung

Renesas alt to Vishay

TDK alt to Toko

Cyntec alt to TFT

ALT POGO PIN W_O CAP

ALT STANDOFF W_O MYLAR

TABLE_ALT_HEAD

TABLE_ALT_ITEM

D

C

B

A

Module Parts

PART NUMBER

337S00029

337S00073

338S00069

338S1264

QTY

1

946-5477 CRITICALGLUE

825-7670

376S00036

376S00037

376S1194

376S1193

900-0090

825-7987

1

2

1

DESCRIPTION

BDW,QGH9,D0,1.8,15W,2+2,0.7,4M,B1168

BDW,QGHB,D0,1.6,15W,2+2,0.6,4M,B1168

IC,TBT,FR-2C,288, 12X12 FC-CSP,TRAY

IC,BCM15700A2KFEB4G,S2 CMRA,8X8,208FCBGA

ASSEMBLY,SUBASSY,PCBA,HALL EFFECT,K99

UV GLUE,MLB,J41_J43

LABEL,TEXT,MLB,K21/K78

MOSFET,N-CH,25V,30A,9.6M,8P 3.3X3.3 DFN

MOSFET,N-CH,25V,30A,6.1M,8P 3.3X3.3 DFN

MOSFET,N-CH,30V,15.3A,12M,8P 3.3X3.3 DFN

MOSFET,N-CH,30V,22A,6.0M,8P 3.3X3.3 DFN

LABEL,MLB,J41/J43

DRAM Parts

PART NUMBER

333S0677

333S0681

333S00001

333S00003

333S0793

333S0791

333S0793

333S0789

QTY

4

DESCRIPTION

IC,SDRAM,8Gb,LPDDR3-1600,178P FBGA

IC,SDRAM,16Gb,LPDDR3-1600,178P FBGA

IC,SDRAM,23NM,8GB,LPDDR3-1600,178P FBGA

IC,SDRAM,23NM,16GB,LPDDR3-1600,178P FBGA

IC,SDRAM,8Gb,LPDDR3-1600,178P FBGA

IC,SDRAM,16Gb,LPDDR3-1600,178P FBGA

IC,SDRAM,8Gb,LPDDR3-1600,178P FBGA

IC,SDRAM,16GB,LPDDR3-1600,178P FBGA

IC,SDRAM,25nm,32Gb,LPDDR3-1600,178P FBGA

REFERENCE DES

U0500

U2800

U3900

J6955

LABEL

Q7310,Q7320

Q7311,Q7321

Q7310,Q7320

Q7311,Q7321

SOLDERPASTE

NEW_LABEL

REFERENCE DES

U2300,U2400,U2500,U2600

CRITICAL

CRITICAL333S0791

CRITICAL

BOM OPTION

CPU:2.1GHZ

CPU:1.6GHZ

J110_MLB607-6811

VCORE_FET:REN

VCORE_FET:VSHY

BOM OPTION

DRAM_TYPE:HYNIX_4GB

DRAM_TYPE:HYNIX_8GB

DRAM_TYPE:SAMSUNG_4GB

DRAM_TYPE:SAMSUNG_8GB

DRAM_TYPE:ELPIDA_4GB

DRAM_TYPE:ELPIDA_8GB

DRAM_TYPE:MICRON_4GB

DRAM_TYPE:MICRON_8GB

DRAM_TYPE:ELPIDA_16GB

6 3

SYNC_MASTER=J43_MLB

PAGE TITLE

BOM Configuration

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/17/2013

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

2 OF 120

SHEET

2 OF 73

124578

SIZE

B

A

D

8 7 6 5 4 3

12

D

C

BOM Variants

BOM NUMBER

639-00613

639-00614

639-00616

639-00617

639-00621

639-00622

639-00695

685-00043

685-00044

685-00045

BOM NAME

PCBA,MLB,BETTER,HY-4GB,X430

PCBA,MLB,BETTER,HY-8GB,X430

PCBA,MLB,BETTER,SM-4GB,X430

PCBA,MLB,BETTER,SM-8GB,X430

PCBA,MLB,BETTER,EL-4GB,X430

PCBA,MLB,BETTER,EL-8GB,X430

PCBA,MLB,BETTER,EL-16GB,X430

CMN PTS,PCBA,MLB,X430

VCORE FET,REN,X430

VCORE FET,VSHY,X430

BOM OPTIONS

MLB_CMNPTS,CPU:1.6GHZ,DDR3:HYNIX_4GB,ALTERNATE

MLB_CMNPTS,CPU:1.6GHZ,DDR3:HYNIX_8GB,ALTERNATE

MLB_CMNPTS,CPU:1.6GHZ,DDR3:SAMSUNG_4GB,ALTERNATE

MLB_CMNPTS,CPU:1.6GHZ,DDR3:SAMSUNG_8GB,ALTERNATE

MLB_CMNPTS,CPU:1.6GHZ,DDR3:ELPIDA_4GB

MLB_CMNPTS,CPU:1.6GHZ,DDR3:ELPIDA_8GB

MLB_CMNPTS,CPU:1.6GHZ,DDR3:ELPIDA_16GB

MLB_COMMON,J110_MLB

VCORE_FET:REN

VCORE_FET:VSHY

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

Alternate Parts

PART NUMBER

685-00044 685-00045

333S0704 333S0700

ALTERNATE FOR PART NUMBER

BOM OPTION

REF DES

ALL

COMMENTS:

Renesas alt to Vishay

Elpida CAM DRAM alt to Hynix

TABLE_ALT_HEAD

TABLE_ALT_ITEM

D

C

B

BOM Groups

BOM GROUP

MLB_PROGPARTS

Programmable Parts

A

PART NUMBER

341S00147

Sub-BOMs

PART NUMBER

685-00043

685-00045

QTY

1

QTY

1

DESCRIPTION

IC,SMC-A3,EXT,Vxxxx,PROTO 0,J110

DESCRIPTION

CMN PTS,PCBA,MLB,J110

VCORE FET,VSHY,J110

BOM OPTIONS

BOOTROM:PROG,SMC:PROG,TBTROM:PROG

REFERENCE DES

U5000

REFERENCE DES

CMNPTS

VCOREFETS

CRITICAL

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

BOM OPTION

SMC:PROG

BOM OPTION

MLB_CMNPTS

VCORE_FETS

6 3

SYNC_MASTER=MASTER

PAGE TITLE

BOM Variants

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=MASTER

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

3 OF 120

SHEET

3 OF 73

124578

SIZE

B

A

D

8 7 6 5 4 3

PD Module Parts

12

806-5107

806-5108

806-3215

806-3216

D

806-3083

725-1792

1

CAN,TOPSIDE,ALT,J41/J43

CAN,TOPSIDE,COVER,ALT,J41/J43

CAN,TBT,J11/J13

CAN,COVER,TBT,J11/J13

CAN,MDP,J11/J13

SHLD,USB,MLB,J11/J13

INSULATOR,CPU,J41/J43

TBTTOPSIDE_2P_FENCE

TBTTOPSIDE_2P_COVER

TBTFENCE806-3142

TBTCOVER CRITICAL

MDPCAN

USBCAN

CPU_INSULATOR

CRITICAL

D

Can Slots

SL0401

TH-NSP

CPU Heat Sink Mounting Bosses

Z0413

4.5OD1.85ID-1.78H-SM

C

4.5OD1.85ID-1.78H-SM

Z0411

1

4x 860-00165

Fan Boss

Z0405

STDOFF-4.5OD1.8H-SM

1

Z0410

4.5OD1.85ID-1.78H-SM

1

Z0412

4.5OD1.85ID-1.78H-SM

1

Z0414

STDOFF-4.5OD1.9H-SM

1

860-1327860-1327

SSD BossX21 Boss

Z0415

STDOFF-4.5OD1.9H-SM

1

860-1327

DisplayPort Pogo

CRITICAL

ZS0405

POGO-2.0OD-3.6H-K86-K87

SM

1

870-1938

EMI I/O Pogo Pins

USB/SD Card Pogo

CRITICAL

ZS0407

POGO-2.0OD-2.95H-K86-K87

SM

1

870-1940

1

SL-1.1X0.4-1.4x0.7

998-2691

SL0403

TH-NSP

1

SL-1.1X0.45-1.4x0.75

998-3975

SL0405

TH-NSP

1

SL-1.1X0.4-1.4x0.7

998-2691

SL0407

TH-NSP

1

SL-1.1X0.45-1.4x0.75

998-3975

SL0402

TH-NSP

1

SL-1.1X0.4-1.4x0.7

998-2691

SL0404

TH-NSP

1

SL-1.1X0.45-1.4x0.75

998-3975

SL0406

TH-NSP

1

SL-1.1X0.4-1.4x0.7

998-2691

SL0408

TH-NSP

1

SL-1.1X0.45-1.4x0.75

998-3975

2x MDP connector

2x USB connector

2x TBT pin diodes

2x TBT chip

C

SIZE

B

A

D

B

A

6 3

SYNC_MASTER=MASTER

PAGE TITLE

PD Parts

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=MASTER

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

4 OF 120

SHEET

4 OF 73

124578

8 7 6 5 4 3

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

BGA

DDI Port Assignments:

D

TBT Sink 0

TBT Sink 1 (MUXed with HDMI if necessary)

DP_TBTSNK0_ML_C_N<0>

25 65

OUT

DP_TBTSNK0_ML_C_P<0>

25 65

OUT

DP_TBTSNK0_ML_C_N<1>

25 65

OUT

DP_TBTSNK0_ML_C_P<1>

25 65

OUT

DP_TBTSNK0_ML_C_N<2>

25 65

OUT

DP_TBTSNK0_ML_C_P<2>

25 65

OUT

DP_TBTSNK0_ML_C_N<3>

25 65

OUT

DP_TBTSNK0_ML_C_P<3>

25 65

OUT

DP_TBTSNK1_ML_C_N<0>

18 25 65

OUT

DP_TBTSNK1_ML_C_P<0>

18 25 65

OUT

DP_TBTSNK1_ML_C_N<1>

18 25 65

OUT

DP_TBTSNK1_ML_C_P<1>

18 25 65

OUT

DP_TBTSNK1_ML_C_N<2>

18 25 65

OUT

DP_TBTSNK1_ML_C_P<2>

18 25 65

OUT

DP_TBTSNK1_ML_C_N<3>

18 25 65

OUT

DP_TBTSNK1_ML_C_P<3>

18 25 65

OUT

C54 C55 B58 C58 B55 A55 A57 B57

C51 C50 C53 B54 C49 B50 A53 B53

DDI1_TXN0 DDI1_TXP0 DDI1_TXN1 DDI1_TXP1 DDI1_TXN2 DDI1_TXP2 DDI1_TXN3 DDI1_TXP3

DDI2_TXN0 DDI2_TXP0 DDI2_TXN1 DDI2_TXP1 DDI2_TXN2 DDI2_TXP2 DDI2_TXN3 DDI2_TXP3

SYM 1 OF 19

DDI

EDP

EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1

EDP_TXN2 EDP_TXP2 EDP_TXN3 EDP_TXP3

EDP_AUXN EDP_AUXP

EDP_RCOMP

EDP_DISP_UTIL

C45 B46 A47 B47

C47 C46 A49 B49

A45 B45

D20 A43

DP_INT_ML_C_N<0> DP_INT_ML_C_P<0> NC_INT_ML_CN<1> NC_INT_ML_CP<1>

NC_INT_ML_CN<2> NC_INT_ML_CP<2> NC_INT_ML_CN<3> NC_INT_ML_CP<3>

DP_INT_AUXCH_C_N DP_INT_AUXCH_C_P

MCP_EDP_RCOMP TP_EDP_DISP_UTIL

58 65

OUT

58 65

OUT

62

OUT

62

OUT

62

OUT

62

OUT

62

OUT

62

OUT

58 65

BI

58 65

BI

eDP Port Assignment:

Internal panel

PPVCOMP_S0_CPU

1

R0530

24.9

1% 1/20W MF 201

2

8

12

D

CRITICAL

OMIT_TABLE

U0500

AT2 AU44 AV44

D15

F22

H22

J21

BROADWELL-ULT

2C+GT2

SYM 17 OF 19

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

SYM 18 OF 19

SPARE

RSVD RSVD RSVD RSVD

RSVD RSVD RSVD

BGA

DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF

N23

RSVD

R23

RSVD

T23

RSVD

U10

RSVD

AL1

RSVD

AM11

RSVD

AP7

RSVD

AU10

RSVD

AU15

RSVD

AW14

RSVD

AY14

RSVD

C

TRUE

AY2

DAISY_CHAIN_NCTF

AY3

DAISY_CHAIN_NCTF

AY60

DAISY_CHAIN_NCTF

AY61

DAISY_CHAIN_NCTF

AY62

DAISY_CHAIN_NCTF

B2

DAISY_CHAIN_NCTF

B3

DAISY_CHAIN_NCTF

B61

DAISY_CHAIN_NCTF

B62

DAISY_CHAIN_NCTF

B63

DAISY_CHAIN_NCTF

C1

DAISY_CHAIN_NCTF

C2

DAISY_CHAIN_NCTF

TP0531

TP0501

TP-P6

MCP_DC_AW2_AY2

5

MCP_DC_AW3_AY3

5

MCP_DC_AY60

1

TP

1

MCP_DC_AW61_AY61

5

MCP_DC_AW62_AY62

5

MCP_DC_B2 MCP_DC_A3_B3

5

MCP_DC_A61_B61

5

MCP_DC_B62_B63

MCP_DC_C1_C2

B

NC NC

MCP Daisy-Chain Strategy:

Each corner of CPU has two testpoints. Other corner test signals connected in daisy-chain fashion. Continuity should exist between both TP’s on each corner.

NO_TESTNO_TEST

A3 A4

A60 A61 A62 AV1 AW1 AW2 AW3 AW61 AW62 AW63

NCNC NCNC NCNC

NCNC NCNC NCNC NC NC NC NC

TRUE

TRUE TRUE

TRUE

MCP_DC_A3_B3 MCP_DC_A4

MCP_DC_A60 MCP_DC_A61_B61 MCP_DC_A62 MCP_DC_AV1 MCP_DC_AW1 MCP_DC_AW2_AY2 MCP_DC_AW3_AY3 MCP_DC_AW61_AY61 MCP_DC_AW62_AY62 MCP_DC_AW63

C

5

1

TP

TP0500

TP-P6

1

TP

TP0510

TP-P6

5

1

TP

TP0511

TP-P6

1

TP

TP0520

TP-P6

1

TP

1

TP-P6

TP

TP0521

TP0530

5

B

A

6 3

SYNC_MASTER=WILL_J43 SYNC_DATE=09/13/2012

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

CPU GFX/NCTF/RSVD

Apple Inc.

R

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

5 OF 120

SHEET

5 OF 73

124578

SIZE

A

D

8 7 6 5 4 3

CRITICAL

OMIT_TABLE

U0500

D

PP1V05_S0

8

11 15 16 17 36 40 49 53 56

57 60 62

R0650

PLACE_NEAR=U0500.AU60:12.7mm

PLACE_NEAR=U0500.AV60:12.7mm

1/20W

200

35 36 49 65

BI

1

1%

MF

201

2

R0610

CPU_PROCHOT_L

1

121

1%

1/20W

MF

201

2

PLACE_NEAR=U0500.C61:12.7mm

R0652

R0651

PLACE_NEAR=U0500.AU61:12.7mm

1/20W

100

1

62

5%

MF

201

2

R0611

56

2 1

5%

1/20W

MF

201

R0620

1/20W

10K

1

5%

MF

201

2

1

1%

MF

201

2

CPU_CATERR_L

35 65

OUT

CPU_PECI

36 65

BI

CPU_PROCHOT_R_L

CPU_PWRGD

65

CPU_SM_RCOMP<0>

65

CPU_SM_RCOMP<1>

65

CPU_SM_RCOMP<2>

65

TP_CPU_MEM_RESET_L

18

OUT

CPU_MEMVTT_PWR_EN_LSVDDQ

17

OUT

D61

PROC_DETECT*

NC

K61

CATERR*

N62

PECI

K63

PROCHOT*

C61

PROCPWRGD

AU60

SM_RCOMP0

AV60

SM_RCOMP1

AU61

SM_RCOMP2

AV15

SM_DRAMRST*

AV61

SM_PG_CNTL1

BROADWELL-ULT

2C+GT2

BGA

SYM 2 OF 19

MISC

PWR

(IPU)

JTAG

THERMAL

DDR3

(IPD)

(IPU)

PRDY*

(IPU)

PREQ*

(IPU)

PROC_TCK PROC_TMS

PROC_TRST*

PROC_TDI PROC_TDO

BPM0*

(IPU)

BPM1*

(IPU)

BPM2*

(IPU)

BPM3*

(IPU)

BPM4*

(IPU)

BPM5*

(IPU)

BPM6*

(IPU)

BPM7*

(IPU)

J62 K62

E60 E61 E59

F63 F62

J60 H60 H61 H62 K59 H63 K60 J61

XDP_CPU_PRDY_L XDP_CPU_PREQ_L

XDP_CPU_TCK XDP_CPU_TMS XDP_CPUPCH_TRST_L

XDP_CPU_TDI XDP_CPU_TDO

XDP_BPM_L<0> XDP_BPM_L<1> XDP_BPM_L<2> XDP_BPM_L<3> XDP_BPM_L<4> XDP_BPM_L<5> XDP_BPM_L<6> XDP_BPM_L<7>

OUT

IN

IN IN IN

IN

OUT

BI BI BI BI BI BI BI BI

16 62 65

12 16 62 65

16 62 65

16 65

12

D

C

B

CFG<10>:SAFE MODE BOOT 1 = NORMAL OPERATION 0 = POWER FEATURES NOT ACTIVE CFG<9> :NO SVID-CAPABLE VR 1 = VR SUPPORTS SVID 0 = VR DOES NOT SUPPORT SVID CFG<8> :ALLOW NOA ON LOCKED UNITS 1 = NORMAL OPERATION 0 = NOA ALWAYS UNLOCKED CFG<4> :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED CFG<1> :PCH-LESS MODE 1 = NORMAL OPERATION 0 = PCH-LESS MODE CFG<0> :RESET SEQUENCE STALL 1 = NORMAL OPERATION 0 = STALL AFTER PCU PLL LOCK

These can be placed close to J1800 and are only for debug access

NOSTUFF

R0640

A

HSW_PRE_ES2

1

R0639

1K

5%

1/20W

5% 1/20W

MF

201

2

NOTE: Pre-ES2 CPUs have issue with Sx cycling, must set CFG<9> low to avoid issue, but this locks CPU VR at 1.7V Vboot (CPU Sighting #4391569).

CPU_CFG<4>

EDP

1

R0634

1K

5% 1/20W MF 201

2

NOSTUFF

R0638

6

16 65

1/20W

NOSTUFF

1

R0631

1K

5%

5% 1/20W

MF

201

2

CPU_CFG<10> CPU_CFG<9> CPU_CFG<8> CPU_CFG<1> CPU_CFG<0>

NOSTUFF

1

R0630

1K

5% 1/20W MF 201

2

C

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

BGA

CPU_CFG<0>

6

16 65

BI

CPU_CFG<1>

6

16 65

BI

CPU_CFG<2>

16 65

BI

CPU_CFG<3>

16 62 65

BI

CPU_CFG<4>

6

16 65

BI

CPU_CFG<5>

16 65

BI

CPU_CFG<6>

16 65

BI

CPU_CFG<7>

16 65

BI

CPU_CFG<8>

6

16 65

BI

CPU_CFG<9>

6

16 65

BI

CPU_CFG<10>

6

16 65

BI

CPU_CFG<11>

16 65

BI

CPU_CFG<12>

16 65

BI

CPU_CFG<13>

16 65

BI

CPU_CFG<14>

16 65

BI

CPU_CFG<15>

16 65

BI

CPU_CFG<16>

16

BI

CPU_CFG<18>

16

BI

CPU_CFG<17>

16

BI

CPU_CFG<19>

16

BI

CPU_CFG_RCOMP

6

16 65

6

16 65

6

16 65

6

16 65

6

16 65

R0680

49.9

1/20W

PCH_TD_IREF

1

R0685

8.25K

1%

1% 1/20W

MF

201

2

AC60

CFG0

AC62

CFG1

AC63

CFG2

AA63

CFG3

AA60

CFG4

Y62

CFG5

Y61

CFG6

Y60

CFG7

V62

CFG8

V61

CFG9

V60

CFG10

U60

CFG11

T63

CFG12

T62

CFG13

T61

CFG14

T60

CFG15

AA62

CFG16

U63

CFG18

AA61

CFG17

U62

CFG19

V63

CFG_RCOMP

A5

J20 H18 B12

E1 D1

RSVD

RSVD RSVD RSVD RSVD TD_IREF

NC NC

NC NC NC

(IPU)

(IPU) (IPU)

(IPU)

(IPU) (IPU)

(IPU)

(IPU) (IPU)

(IPU)

(IPU) (IPU)

SYM 19 OF 19

RESERVED

PROC_OPI_COMP

6 3

RSVD_TP RSVD_TP

RSVD_B43

RSVD_TP RSVD_TP

RSVD_TP

RSVD

RSVD RSVD

VSS VSS

AV63 AU63

C63 C62

B43

A51 B51

L60

N60

W23 Y22

AY15

AV62 D58

P22 N21

P20 R20

NC

NC NC

TP_MCP_RSVD_AV63 TP_MCP_RSVD_AU63

TP_MCP_RSVD_C63 TP_MCP_RSVD_C62

TP_MCP_RSVD_A51 TP_MCP_RSVD_B51

TP_MCP_RSVD_L60

CPU_OPI_RCOMP

1

R0690

49.9

1% 1/20W MF 201

2

SYNC_MASTER=WILL_J43 SYNC_DATE=09/13/2012

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

CPU Misc/JTAG/CFG/RSVD

Apple Inc.

R

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

<SCH_NUM>

6 OF 120

6 OF 73

124578

SIZE

B

A

D

8 7 6 5 4 3

12

CRITICAL

MEM_A_DQ<0>

61 68

BI

MEM_A_DQ<1>

61 68

BI

MEM_A_DQ<2>

61 68

BI

MEM_A_DQ<3>

61 68

BI

MEM_A_DQ<4>

61 68

BI

MEM_A_DQ<5>

61 68

BI

MEM_A_DQ<6>

61 68

BI

MEM_A_DQ<7>

61 68

BI

MEM_A_DQ<8>

61 68

D

C

B

61 68

21 61 68

61 68

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

MEM_A_DQ<9> MEM_A_DQ<10> MEM_A_DQ<11> MEM_A_DQ<12> MEM_A_DQ<13> MEM_A_DQ<14> MEM_A_DQ<15> MEM_A_DQ<16> MEM_A_DQ<17> MEM_A_DQ<18> MEM_A_DQ<19> MEM_A_DQ<20> MEM_A_DQ<21> MEM_A_DQ<22> MEM_A_DQ<23> MEM_A_DQ<24> MEM_A_DQ<25> MEM_A_DQ<26> MEM_A_DQ<27> MEM_A_DQ<28> MEM_A_DQ<29> MEM_A_DQ<30> MEM_A_DQ<31> MEM_A_DQ<32> MEM_A_DQ<33> MEM_A_DQ<34> MEM_A_DQ<35> MEM_A_DQ<36> MEM_A_DQ<37> MEM_A_DQ<38> MEM_A_DQ<39> MEM_A_DQ<40> MEM_A_DQ<41> MEM_A_DQ<42> MEM_A_DQ<43> MEM_A_DQ<44> MEM_A_DQ<45> MEM_A_DQ<46> MEM_A_DQ<47> MEM_A_DQ<48> MEM_A_DQ<49> MEM_A_DQ<50> MEM_A_DQ<51> MEM_A_DQ<52> MEM_A_DQ<53> MEM_A_DQ<54> MEM_A_DQ<55> MEM_A_DQ<56> MEM_A_DQ<57> MEM_A_DQ<58> MEM_A_DQ<59> MEM_A_DQ<60> MEM_A_DQ<61> MEM_A_DQ<62> MEM_A_DQ<63>

AH63 AH62 AK63 AK62 AH61 AH60 AK61 AK60 AM63 AM62 AP63 AP62 AM61 AM60 AP61 AP60 AP58 AR58 AM57 AK57 AL58 AK58 AR57 AN57 AP55 AR55 AM54 AK54 AL55 AK55 AR54 AN54 AY58 AW58 AY56 AW56 AV58 AU58 AV56 AU56 AY54 AW54 AY52 AW52 AV54 AU54 AV52 AU52 AK40 AK42 AM43 AM45 AK45 AK43 AM40 AM42 AM46 AK46 AM49 AK49 AM48 AK48 AM51 AK51

SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 3 OF 19

MEMORY CHANNEL A

LPDDR3

RSVD1

RSVD2

SA_CLK0*

SA_CLK0

SA_CLK1*

SA_CLK1

SA_CKE0 SA_CKE1 SA_CKE2 SA_CKE3

SA_CS0* SA_CS1*

SA_ODT0

SA_RAS*

CAB3

SA_WE*

CAB2

SA_CAS*

CAB1

SA_BA0

CAB4

SA_BA1

CAB6

SA_BA2

CAA5

SA_MA0

CAB9

SA_MA1

CAB8

SA_MA2

CAB5

SA_MA3 SA_MA4 SA_MA5

CAA0

SA_MA6

CAA2

SA_MA7

CAA4

SA_MA8

CAA3

SA_MA9

CAA1

SA_MA10

CAB7

SA_MA11

CAA7

SA_MA12

CAA6

SA_MA13

CAB0

SA_MA14

CAA9

SA_MA15

CAA8

SA_DQSN0 SA_DQSN1 SA_DQSN2 SA_DQSN3 SA_DQSN4 SA_DQSN5 SA_DQSN6 SA_DQSN7

SA_DQSP0 SA_DQSP1 SA_DQSP2 SA_DQSP3 SA_DQSP4 SA_DQSP5 SA_DQSP6 SA_DQSP7

SM_VREF_CA

SM_VREF_DQ0

SM_VREF_DQ1

AU37 AV37 AW36 AY36

AU43 AW43 AY42 AY43

AP33 AR32

AP32

AY34 AW34 AU34

AU35 AV35 AY41

AU36 AY37 AR38 AP36 AU39 AR36 AV40 AW39 AY39 AU40 AP35 AW41 AU41 AR35 AV42 AU42

AJ61 AN62 AM58 AM55 AV57 AV53 AL43 AL48

AJ62 AN61 AN58 AN55 AW57 AW53 AL42 AL49

AP49

AR51

AP51

MEM_A_CLK_N<0> MEM_A_CLK_P<0> MEM_A_CLK_N<1> MEM_A_CLK_P<1>

MEM_A_CKE<0> MEM_A_CKE<1> MEM_A_CKE<2> MEM_A_CKE<3>

MEM_A_CS_L<0> MEM_A_CS_L<1>

MEM_A_ODT<0>

=MEM_A_RAS_L =MEM_A_WE_L =MEM_A_CAS_L

=MEM_A_BA<0> MEM_A_CAB<6> =MEM_A_BA<2>

=MEM_A_A<0> =MEM_A_A<1> =MEM_A_A<2> TP_LPDDR3_RSVD1 TP_LPDDR3_RSVD2 =MEM_A_A<5> =MEM_A_A<6> =MEM_A_A<7> =MEM_A_A<8> =MEM_A_A<9> =MEM_A_A<10> =MEM_A_A<11> MEM_A_CAA<6> =MEM_A_A<13> =MEM_A_A<14> =MEM_A_A<15>

MEM_A_DQS_N<0> MEM_A_DQS_N<1> MEM_A_DQS_N<2> MEM_A_DQS_N<3> MEM_A_DQS_N<4> MEM_A_DQS_N<5> MEM_A_DQS_N<6> MEM_A_DQS_N<7>

MEM_A_DQS_P<0> MEM_A_DQS_P<1> MEM_A_DQS_P<2> MEM_A_DQS_P<3> MEM_A_DQS_P<4> MEM_A_DQS_P<5> MEM_A_DQS_P<6> MEM_A_DQS_P<7>

CPU_DIMM_VREFCA

CPU_DIMMA_VREFDQ

CPU_DIMMB_VREFDQ

OUT OUT OUT OUT

OUT OUT

OUT

OUT OUT OUT

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

BI BI BI BI BI BI BI BI

OUT

20 24 68

21 24 68

20 24 68

21 24 68

20 21 24 68

20 21 24 61 68

61

21 24 61 68

61

20 24 61 68

61

61 68

21 61 68

61 68

21 61 68

61 68

19

MEM_B_DQ<0>

61 68

BI

MEM_B_DQ<1>

61 68

BI

MEM_B_DQ<2>

61 68

BI

MEM_B_DQ<3>

61 68

BI

MEM_B_DQ<4>

61 68

BI

MEM_B_DQ<5>

61 68

BI

MEM_B_DQ<6>

61 68

BI

MEM_B_DQ<7>

61 68

BI

MEM_B_DQ<8>

61 68

BI

MEM_B_DQ<9>

61 68

BI

MEM_B_DQ<10>

61 68

BI

MEM_B_DQ<11>

61 68

BI

MEM_B_DQ<12>

61 68

BI

MEM_B_DQ<13> MEM_B_ODT<0>

61 68

BI

MEM_B_DQ<14>

61 68

BI

MEM_B_DQ<15> =MEM_B_RAS_L

61 68

BI

MEM_B_DQ<16>

61 68

BI

MEM_B_DQ<17> =MEM_B_CAS_L

61 68

BI

MEM_B_DQ<18>

61 68

BI

MEM_B_DQ<19> =MEM_B_BA<0>

61 68

BI

MEM_B_DQ<20> MEM_B_CAB<6>

61 68

BI

MEM_B_DQ<21> =MEM_B_BA<2>

61 68

BI

MEM_B_DQ<22>

61 68

BI

MEM_B_DQ<23>

61 68

BI

MEM_B_DQ<24>

61 68

BI

MEM_B_DQ<25>

61 68

BI

MEM_B_DQ<26>

61 68

BI

MEM_B_DQ<27>

61 68

BI

MEM_B_DQ<28>

61 68

BI

MEM_B_DQ<29>

61 68

BI

MEM_B_DQ<30>

61 68

BI

MEM_B_DQ<31>

61 68

BI

MEM_B_DQ<32>

61 68

BI

MEM_B_DQ<33> =MEM_B_A<10>

23 61 68

BI

MEM_B_DQ<34> =MEM_B_A<11>

61 68

BI

MEM_B_DQ<35> MEM_B_CAA<6>

61 68

BI

MEM_B_DQ<36>

61 68

BI

MEM_B_DQ<37> =MEM_B_A<14>

61 68

BI

MEM_B_DQ<38> =MEM_B_A<15>

61 68

BI

MEM_B_DQ<39>

61 68

BI

MEM_B_DQ<40>

61 68

BI

MEM_B_DQ<41>

61 68

BI

MEM_B_DQ<42>

61 68

BI

MEM_B_DQ<43>

61 68

BI

MEM_B_DQ<44>

61 68

BI

MEM_B_DQ<45>

61 68

BI

MEM_B_DQ<46>

61 68

BI

MEM_B_DQ<47>

61 68

BI

MEM_B_DQ<48>

61 68

BI

MEM_B_DQ<49>

61 68

BI

MEM_B_DQ<50>

61 68

BI

MEM_B_DQ<51>

61 68

BI

MEM_B_DQ<52>

61 68

BI

MEM_B_DQ<53>

61 68

BI

MEM_B_DQ<54>

61 68

BI

MEM_B_DQ<55>

61 68

BI

MEM_B_DQ<56>

61 68

BI

MEM_B_DQ<57>

61 68

BI

MEM_B_DQ<58>

61 68

BI

MEM_B_DQ<59>

61 68

BI

MEM_B_DQ<60>

61 68

BI

MEM_B_DQ<61>

61 68

BI

MEM_B_DQ<62>

61 68

BI

MEM_B_DQ<63>

61 68

BI

AY31

SB_DQ0

AW31

SB_DQ1

AY29

SB_DQ2

AW29

SB_DQ3

AV31

SB_DQ4

AU31

SB_DQ5

AV29

SB_DQ6

AU29

SB_DQ7

AY27

SB_DQ8

AW27

SB_DQ9

AY25

SB_DQ10 SB_CS0*

AW25

SB_DQ11 SB_CS1*

AV27

SB_DQ12

AU27

SB_DQ13 SB_ODT0

AV25

SB_DQ14

AU25

SB_DQ15 SB_RAS*

AM29

SB_DQ16

AK29

SB_DQ17 SB_CAS*

AL28

SB_DQ18

AK28

SB_DQ19

AR29

SB_DQ20

AN29

SB_DQ21

AR28

SB_DQ22

AP28

SB_DQ23

AN26

SB_DQ24

AR26

SB_DQ25

AR25

SB_DQ26

AP25

SB_DQ27

AK26

SB_DQ28

AM26

SB_DQ29

AK25

SB_DQ30

AL25

SB_DQ31

AY23

SB_DQ32

AW23

SB_DQ33 SB_MA10

AY21

SB_DQ34 SB_MA11

AW21

SB_DQ35 SB_MA12

AV23

SB_DQ36

AU23

SB_DQ37 SB_MA14

AV21

SB_DQ38 SB_MA15

AU21

SB_DQ39

AY19

SB_DQ40

AW19

SB_DQ41

AY17

SB_DQ42

AW17

SB_DQ43

AV19

SB_DQ44

AU19

SB_DQ45

AV17

SB_DQ46

AU17

SB_DQ47

AR21

SB_DQ48

AR22

SB_DQ49

AL21

SB_DQ50

AM22

SB_DQ51

AN22

SB_DQ52

AP21

SB_DQ53

AK21

SB_DQ54

AK22

SB_DQ55

AN20

SB_DQ56

AR20

SB_DQ57

AK18

SB_DQ58

AL18

SB_DQ59

AK20

SB_DQ60

AM20

SB_DQ61

AR18

SB_DQ62

AP18

SB_DQ63

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 4 OF 19

MEMORY CHANNEL B

LPDDR3

RSVD3

RSVD4

CAB3

CAB2 CAB1

CAB4 CAB6

CAA5

CAB9

CAB8 CAB5

CAA0

CAA2

CAA4 CAA3

CAA1

CAB7 CAA7

CAA6 CAB0

CAA9

CAA8

SB_CK0*

SB_CK0

SB_CK1*

SB_CK1

SB_CKE0 SB_CKE1 SB_CKE2 SB_CKE3

SB_WE*

SB_BA0 SB_BA1 SB_BA2

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9

SB_MA13

SB_DQSN0 SB_DQSN1 SB_DQSN2 SB_DQSN3 SB_DQSN4 SB_DQSN5 SB_DQSN6 SB_DQSN7

SB_DQSP0 SB_DQSP1 SB_DQSP2 SB_DQSP3 SB_DQSP4 SB_DQSP5 SB_DQSP6 SB_DQSP7

AM38 AN38 AK38 AL38

AY49 AU50 AW49 AV50

AM32 AK32

AL32

AM35 AK35 AM33

AL35 AM36 AU49

AP40 AR40 AP42 AR42 AR45 AP45 AW46 AY46 AY47 AU46 AK36 AV47 AU47 AK33 AR46 AP46

AW30 AV26 AN28 AN25 AW22 AV18 AN21 AN18

AV30 AW26 AM28 AM25 AV22 AW18 AM21 AM18

MEM_B_CLK_N<0> MEM_B_CLK_P<0> MEM_B_CLK_N<1> MEM_B_CLK_P<1>

MEM_B_CKE<0> MEM_B_CKE<1> MEM_B_CKE<2> MEM_B_CKE<3>

MEM_B_CS_L<0> MEM_B_CS_L<1>

=MEM_B_WE_L

=MEM_B_A<0> =MEM_B_A<1> =MEM_B_A<2> TP_LPDDR3_RSVD3 TP_LPDDR3_RSVD4 =MEM_B_A<5> =MEM_B_A<6> =MEM_B_A<7> =MEM_B_A<8> =MEM_B_A<9>

=MEM_B_A<13>

MEM_B_DQS_N<0> MEM_B_DQS_N<1> MEM_B_DQS_N<2> MEM_B_DQS_N<3> MEM_B_DQS_N<4> MEM_B_DQS_N<5> MEM_B_DQS_N<6> MEM_B_DQS_N<7>

MEM_B_DQS_P<0> MEM_B_DQS_P<1> MEM_B_DQS_P<2> MEM_B_DQS_P<3> MEM_B_DQS_P<4> MEM_B_DQS_P<5> MEM_B_DQS_P<6> MEM_B_DQS_P<7>

OUT OUT OUT OUT

OUT OUT

OUT

OUT OUT OUT

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

BI BI BI BI BI BI BI BI

22 24 68

23 24 68

22 24 68

23 24 68

22 23 24 68

22 23 24 61 68

61

23 24 61 68

61

22 24 61 68

61

61 68

23 61 68

61 68

23 61 68

61 68

D

C

B

A

PAGE TITLE

CPU DDR3/LPDDR3 Interfaces

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

6 3

SYNC_DATE=09/13/2012SYNC_MASTER=WILL_J43

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

7 OF 120

SHEET

7 OF 73

124578

SIZE

A

D

8 7 6 5 4 3

HSW-ULT current estimates from Haswell Mobile ULT Processor EDS vol 1, doc #502406, v0.9. LPT-LP current estimates from Lynx Point-LP PCH EDS, doc #503118, v1.0. Note [1] current numbers from clarification email, from Srini, dated 9/10/2012 2:11pm.

D

C

PP1V05_S0SW_PCH_HSIO

11 56 60

1838mA Max

PP1V05_S0

6 8

11 15 16 17 36 40 49

53 56 57 60 62

29mA Max[1]

PP1V05_S0SW_PCH_VCCUSB3PLL

11 14

41mA Max

PP1V05_S0SW_PCH_VCCSATA3PLL

B

A

11 12

42mA Max

WF: RSVD on Sawtooth Peak rev 1.0

PP1V05_S0_PCH_VCCAPLL_OPI

11

57mA Max

PP1V5_S0SW_AUDIO_HDA

11 17 56

11mA Max

PP3V3_SUS

8

11 14 18 44 55 56 57 60

62

59mA Max[1]

PP3V3_S5

11 13 15 16 17 18 28 29 40 52 55 56 57 58 60 62 72

114mA Max

54 57 59 60 62 63 72

PP3V3_S0

8

11 12 13 15 17 18 26 30

34 36 37 38 39 40 41 42 43

40mA Max[1]

PP1V05_S0_PCH_VCC_ICC

11

VCCCLK: 200mA Max

PP1V05_S0_PCH_VCCACLKPLL

11 12

31mA Max

PP1V05_S0

6 8

11 15 16 17 36 40 49

53 56 57 60 62

VCCCLK: 200mA Max

WF: RSVD on Sawtooth Peak rev 1.0

PP3V3_SUS

8

11 14 18 44 55 56 57 60

62

K9

L10

M9

N8 P9

B18

B11

Y20

NC

AA21

W21

J13

NC

AH14

AH13

NC

AC9 AA9

AH10

V8 W9

J18 K19

A20

J17 R21 T21 K18

NC

M20

NC

V21

NC

AE20 AE21

VCCHSIO VCCHSIO VCCHSIO

VCC1_05 VCC1_05

VCCUSB3PLL

VCCSATA3PLL

VCCAPLL VCCAPLL VCCAPLL

DCPSUS3

AZALIA/HDA

VCCHDA

VRM/USB2/AZALIA

DCPSUS2

VCCSUS3_3 VCCSUS3_3

VCCDSW3_3

VCC3_3 VCC3_3

VCCCLK VCCCLK

VCCACLKPLL

VCCCLK VCCCLK VCCCLK RSVD RSVD RSVD

VCCSUS3_3 VCCSUS3_3

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 13 OF 19

SPI RTC

HSIO

OPI

USB3

CORE

GPIO/LCC

THERMAL SENSOR

SERIAL IO

SUS OSCILLATOR

ICC

USB2

LPT LP POWER

VCCSUS3_3

VCCRTC

DCPRTC

VCCSPI

VCCASW VCCASW

VCC1P05 VCC1P05 VCC1P05 VCC1P05 VCC1P05

DCPSUSBYP DCPSUSBYP

VCCASW VCCASW VCCASW

DCPSUS1 DCPSUS1

VCCTS1_5

VCC3_3 VCC3_3

VCCSDIO VCCSDIO

DCPSUS4

RSVD

VCC1_05 VCC1_05

PPVMEMIO_S0_CPU

10 40

1.4A Max (DDR3: 1.5-1.35V)

1.1A Max (LPDDR3: 1.2V)

PPVCC_S0_CPU

8

10 40 50 60 62

1

R0860

100

5%

1/20W

MF

201

2

CPU_VIDALERT_R_L CPU_VIDSCLK_R CPU_VIDSOUT_R CPU_VCCST_PWRGD

16 17

IN

CPU_VR_EN

17 49

OUT

CPU_VR_READY

17 49

IN

CPU_PWR_DEBUG

16

IN

TP_CPU_RSVD_P60 TP_CPU_RSVDP61

18

TP_CPU_RSVD_N59 TP_CPU_RSVDN61

18

PP1V05_S0

6 8

11 15 16 17 36 40 49 53

56 57 60 62

???mA Max

12 13 17 60 62

BYPASS=R0899:U0500:2.54mm

11 15 16 17 36 40 49 53

49 65

IN

49 65

OUT

49 65

BI

AH11

PP3V3_SUS

0.3mA Max[1]

AG10

AE7

PPVOUT_S0_PCH_DCPRTC

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

Y8

PP3V3_SUS

18mA Max

AG14

PP1V05_S0

AG13

185mA Max[1]

J11

PP1V05_S0

H11

1499mA Max[1]

H15 AE8 AF22

AG19

PPVOUT_S5_PCH_DCPSUSBYP_R

MIN_LINE_WIDTH=0.2 mm

AG20

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

AE9

PP1V05_S0

AF9

473mA Max[1]

AG8

AD10

NC

AD8

NC

J15

PP1V5_S0

3mA Max

K14

PP3V3_S0

K16

1mA Max[1]

U8

PP3V3_S0

T9

17mA Max

AB8

NC

AC20

AG16 AG17

WF: RSVD on Sawtooth Peak rev 1.0

NC

PP1V05_S0

213mA Max[1]3.3mA Max[1]

PP1V05_S0

6 8 56 57 60 62

CPU_VIDALERT_L

CPU_VIDSCLK

CPU_VIDSOUT

R0800

75

1%

1/20W

MF

201

R0811

0

5%

1/20W

MF

0201

8

11 14 18 44 55 56 57 60 62

BYPASS=U0500.AE7:6.35mm

8

11 14 18 44 55 56 57

60 62

6 8 53 56 57 60 62

6 8 57 60 62

Powered in DeepSx

6 8 57 60 62

55 56 57 60 62

60 62 63 72 8

11 12 13 15 17 18 26 30 34 36

37 38 39 40 41 42 43 54 57 59

60 62 63 72 8

11 12 13 15 17 18 26 30 34 36

37 38 39 40 41 42 43 54 57 59

6 8 57 60 62

1

R0810

2

43

21

5%

1/20W

MF

201

21

R0812

0

21

5%

1/20W

MF

0201

11 15 16 17 36 40 49

11 15 16 17 36 40 49 53 56

PLACE_NEAR=U0500.AG19:2.54mm

R0899

5.11

1/20W

11 15 16 17 36 40 49 53 56

MF-LF

1

R0802

130

1% 1/20W MF 201

2

R0802.2:

R0810.2: R0800.2:

1

C0895

0.1UF

20% 10V

2

CERM 402

21

PPVOUT_S5_PCH_DCPSUSBYP

MIN_LINE_WIDTH=0.2 mm

1%

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

201

PLACE_NEAR=U0500.C50:50.8mm

Max load: 300mA

PLACE_NEAR=U0500.L63:2.54mm

PLACE_NEAR=U0500.L62:38.1mm PLACE_NEAR=R0810.1:2.54mm

1

C0892

0.1UF

20% 10V

2

CERM

402

C0891

BYPASS=U0500.AG10:6.35mm

CPU_VCCSENSE_P

49 65

OUT

TP_PPVCCIO_S0_CPU

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

PPVCOMP_S0_CPU

5

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

NOTE: Aliases not used on CPU supply outputs to avoid any extraneous connections.

PPVRTC_G3H

1

0.1UF

20% 10V

CERM

402

C0890

1UF

10%

6.3V

2

CERM 402

BYPASS=U0500.AG10:6.35mm

1

C0899

1UF

10%

6.3V

2

CERM 402

6 3

12

CRITICAL

L59 J58

AH26 AJ31 AJ33 AJ37 AN33 AP43 AR48 AY35 AY40 AY44 AY50

F59 N58

AC58

E63

AB23

A59

E20 AD23 AA23 AE59

L62

N63

L63

B59

F60

C59

D63

H59

P62

P60

P61

N59

N61

T59 AD60 AD59 AA59 AE60 AC59 AG58

U59

V59

AC22 AE22 AE23

AB57 AD57 AG57

C24

C28

C32

RSVD RSVD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VCC RSVD RSVD

VCC_SENSE

RSVD VCCIO_OUT VCCIOA_OUT RSVD RSVD RSVD

VIDALERT* VIDSCLK VIDSOUT VCCST_PWRGD VR_EN VR_READY

VSS PWR_DEBUG* VSS RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

VCCST VCCST VCCST

VCC VCC VCC VCC VCC VCC

NC NC

NC

NC NC NC

NC NC NC NC NC NC NC NC NC

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 12 OF 19

HSW ULT POWER

SYNC_MASTER=J43_MLB

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

R

OMIT_TABLE

PPVCC_S0_CPU

C36 C40 C44 C48 C52 C56 E23 E25 E27 E29 E31 E33 E35 E37 E39 E41 E43 E45 E47 E49 E51 E53 E55 E57 F24 F28 F32 F36 F40 F44 F48 F52 F56 G23 G25 G27 G29 G31 G33 G35 G37 G39 G41 G43 G45 G47 G49 G51 G53 G55 G57 H23 J23 K23 K57 L22 M23 M57 P57 U57 W57

CPU/PCH POWER

Apple Inc.

32A Max

8

10 40 50 60 62

SYNC_DATE=10/02/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

8 OF 120

SHEET

8 OF 73

SIZE

D

C

B

A

D

124578

8 7 6 5 4 3

12

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 14 OF 19

A11

VSS

A14

VSS

A18

VSS

A24

VSS

A28

VSS

D

C

B

A32 A36 A40 A44 A48 A52 A56

AA1 AA58 AB10 AB20 AB22

AB7 AC61 AD21

AD3 AD63 AE10

AE5 AE58 AF11 AF12 AF14 AF15 AF17 AF18

AG1 AG11 AG21 AG23 AG60 AG61 AG62 AG63 AH17 AH19 AH20 AH22 AH24 AH28 AH30 AH32 AH34 AH36 AH38 AH40 AH42 AH44 AH49 AH51 AH53 AH55 AH57 AJ13 AJ14 AJ23 AJ25 AJ27 AJ29

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AJ35 AJ39 AJ41 AJ43 AJ45 AJ47 AJ50 AJ52 AJ54 AJ56 AJ58 AJ60 AJ63 AK23 AK3 AK52 AL10 AL13 AL17 AL20 AL22 AL23 AL26 AL29 AL31 AL33 AL36 AL39 AL40 AL45 AL46 AL51 AL52 AL54 AL57 AL60 AL61 AM1 AM17 AM23 AM31 AM52 AN17 AN23 AN31 AN32 AN35 AN36 AN39 AN40 AN42 AN43 AN45 AN46 AN48 AN49 AN51 AN52 AN60 AN63 AN7 AP10 AP17 AP20

AP22 AP23 AP26 AP29

AP3 AP31 AP38 AP39 AP48 AP52 AP54 AP57 AR11 AR15 AR17 AR23 AR31 AR33 AR39 AR43 AR49

AR5 AR52 AT13 AT35 AT37 AT40 AT42 AT43 AT46 AT49 AT61 AT62 AT63

AU1 AU16 AU18 AU20 AU22 AU24 AU26 AU28 AU30 AU33 AU51 AU53 AU55 AU57 AU59 AV14 AV16 AV20 AV24 AV28 AV33 AV34 AV36 AV39 AV41 AV43 AV46 AV49 AV51 AV55

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 15 OF 19 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AV59 AV8 AW16 AW24 AW33 AW35 AW37 AW4 AW40 AW42 AW44 AW47 AW50 AW51 AW59 AW60 AY11 AY16 AY18 AY22 AY24 AY26 AY30 AY33 AY4 AY51 AY53 AY57 AY59 AY6 B20 B24 B26 B28 B32 B36 B4 B40 B44 B48 B52 B56 B60 C11 C14 C18 C20 C25 C27 C38 C39 C57 D12 D14 D18 D2 D21 D23 D25 D26 D27 D29 D30 D31

D33 D34 D35 D37 D38 D39 D41 D42 D43 D45 D46 D47 D49

D50 D51 D53 D54 D55 D57 D59 D62

E11 E17 F20 F26 F30 F34 F38 F42 F46 F50 F54 F58 F61 G18 G22

H13

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

D5

VSS VSS VSS VSS VSS VSS VSS VSS VSS

D8

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

G3

VSS

G5

VSS

G6

VSS

G8

VSS VSS

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 16 OF 19

VSS_SENSE

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS

VSS

H17 H57 J10 J22 J59 J63 K1 K12 L13 L15 L17 L18 L20 L58 L61 L7 M22 N10 N3 P59 P63 R10 R22 R8 T1 T58 U20 U22 U61 U9 V10 V3 V7 W20 W22 Y10 Y59 Y63

V58 AH46 V23 E62 AH16

CPU_VCCSENSE_N

1

R0960

100

PLACE_NEAR=U0500.E62:50.8mm

5% 1/20W MF 201

2

D

C

49 65

OUT

B

A

SYNC_MASTER=J43_MLB

PAGE TITLE

CPU/PCH GROUNDS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

6 3

SYNC_DATE=10/02/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

9 OF 120

SHEET

9 OF 73

124578

SIZE

A

D

8 7 6 5 4 3

All Intel recommendations from Intel doc #503160 Shark Bay Ultrabook Platform Power Delivery Design Guide Rev 1.0 unless stated otherwise

CPU VCC Decoupling

PPVCC_S0_CPU

8

40 50 60 62

D

Intel recommendation (Table 5-1): 23x 22uF 0805 stuff, 7x 22uF 0805 nostuff Apple implementation : 18x 10uF 0402 mirrored stuff, 1x 470uF stuff, 50x 10uF mirrored no stuff, 50x 10uF single sided no stuff

NO STUFF

1

C1000

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1015

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1001

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1016

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1002

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1017

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1003

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1018

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1004

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1019

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1005

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1020

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1006

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1021

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1007

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1030

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1008

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C104A

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1009

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C104B

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1010

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C104C

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1011

10UF

20% 4V

2

X6S 0402

CRITICAL

1

C104D

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1012

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C104E

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1013

10UF

20% 4V

2

X6S 0402

CRITICAL

1

C104F

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1014

10UF

20% 4V

2

X6S 0402

CRITICAL

1

C106A

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C105A

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C106B

10UF

20% 4V

2

X6S 0402

CRITICAL

1

C105B

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C106C

10UF

20% 4V

2

X6S 0402

CRITICAL

1

C105C

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C106D

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C105D

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C106E

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C105E

10UF

20% 4V

2

X6S 0402

12

CRITICAL

1

C105F

10UF

20% 4V

2

X6S 0402

D

CRITICAL

1

C1070

10UF

20% 4V

2

X6S 0402

CRITICAL

1

C1085

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C

B

C1022

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1039

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1056

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C109B

10UF

20% 4V

2

X6S 0402

CRITICAL

1

C1031

470UF-0.0045OHM

20%

2.5V

3 2

POLY-TANT SM

CRITICAL

1

C1071

10UF

20% 4V

2

X6S 0402

CRITICAL

1

C1086

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1023

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1044

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1057

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C109C

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1072

10UF

20% 4V

2

X6S 0402

CRITICAL

1

C1087

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1024

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1045

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1058

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C109D

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1073

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1088

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1025

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1046

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1059

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C109E

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1074

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1089

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1026

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1047

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1062

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C109F

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1075

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1090

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1027

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1048

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1063

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C108A

10UF

20% 4V

2

X6S 0402

CRITICAL

1

C1076

10UF

20% 4V

2

X6S 0402

CRITICAL

1

C1091

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1028

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1049

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1064

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C108B

10UF

20% 4V

2

X6S 0402

CRITICAL

1

C1077

10UF

20% 4V

2

X6S 0402

CRITICAL

1

C1092

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1029

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1065

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C108C

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1078

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1093

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1032

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1066

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C108D

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1079

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1094

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1033

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1067

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C108E

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1080

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1095

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1034

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1068

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C108F

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1081

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1096

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1035

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1069

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C107A

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1082

10UF

20% 4V

2

X6S 0402

CRITICAL

1

C1097

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1036

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1098

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C107B

10UF

20% 4V

2

X6S 0402

CRITICAL

1

C1083

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1037

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1099

10UF

20% 4V

2

X6S 0402

CRITICAL

1

C1084

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1038

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C109A

10UF

20% 4V

2

X6S 0402

C

B

CPU VDDQ DECOUPLING

PPVMEMIO_S0_CPU

8

40

A

Intel recommendation (Table 5-4): 4x 2.2uF 0402, 6x 10uF 0603 Apple implementation : 4x 2.2uF 0402, 6x 10uF 0402, 2x 270uF B2 no stuff

1

C1040

2.2UF

20%

6.3V

2

CERM 402-LF

1

C1050

10UF

20%

6.3V

2

CERM-X5R 0402-1

1

C1060

270UF

20% 2V

2

TANT CASE-B2-SM

1

C1041

2.2UF

20%

6.3V

2

CERM 402-LF

1

C1051

10UF

20%

6.3V

2

CERM-X5R 0402-1

NO STUFF

1

C1061

270UF

20% 2V

2

TANT CASE-B2-SM

1

2

1

2

C1042

2.2UF

20%

6.3V CERM 402-LF

C1052

10UF

20%

6.3V CERM-X5R 0402-1

1

2

1

C1053

2

C1043

2.2UF

20%

6.3V CERM 402-LF

10UF

20%

6.3V CERM-X5R 0402-1

1

C1054

2

10UF

20%

6.3V CERM-X5R 0402-1

2x Bulk nostuff per Harris Beach v1.0 schematic

1

C1055

2

10UF

20%

6.3V CERM-X5R 0402-1

6 3

SYNC_MASTER=LABEL_J41

PAGE TITLE

CPU Decoupling

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/11/2013

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

10 OF 120

SHEET

10 OF 73

124578

SIZE

A

D

8 7 6 5 4 3

12

PCH VCCDSW3_3 BYPASS (PCH 3.3V DSW PWR)

PP3V3_S5

8

13 15 16 17 18 28 29 40 52

55 56 57 58 60 62 72

PCH VCCSPI BYPASS

D

(PCH 3.3V SPI PWR)

PP3V3_SUS

8

11 14 18 44 55 56 57 60 62

PCH VCCSUS3_3 BYPASS (PCH 3.3V SUSPEND PWR)

PP3V3_SUS

8

11 14 18 44 55 56 57 60 62

PCH VCCSUS3_3 BYPASS (PCH 3.3V SUSPEND RTC PWR)

PP3V3_SUS

8

11 14 18 44 55 56 57 60 62

C

PCH VCCSDIO BYPASS (PCH 3.3V/1.8V SDIO PWR)

59 60 62 63 72

PP3V3_S0

8

11 12 13 15 17 18 26 30 34

36 37 38 39 40 41 42 43 54 57

NO STUFF

C1200

BYPASS=U0500.AH10:6.35mm

NO STUFF

C1202

0.1UF

BYPASS=U0500.Y8:6.35mm

C1204

22UF

X5R-CERM-1

BYPASS=U0500.AC9:12.7mm

C1206

BYPASS=U0500.AH11:6.35mm

C1208

BYPASS=U0500.U8:6.35mm

1UF

6.3V CERM

CERM

6.3V

1UF

6.3V CERM

1UF

6.3V CERM

1

10%

2

402

1

20% 10V

2

402

1

20%

2

603

1

10%

2

402

1

10%

2

402

PCH VCC3_3 BYPASS (PCH 3.3V GPIO/LPC PWR)

59 60 62 63 72

PP3V3_S0

8

11 12 13 15 17 18 26 30 34

36 37 38 39 40 41 42 43 54 57

PCH VCC3_3 BYPASS (PCH 3.3V THERMAL PWR)

59 60 62 63 72

PP3V3_S0

8

11 12 13 15 17 18 26 30 34

36 37 38 39 40 41 42 43 54 57

11 15 16 17 36 40 49 53

PP1V05_S0

6 8 56 57 60 62

??mA Max

C1212

22UF

X5R-CERM-1

BYPASS=U0500.V8:12.7mm

C1214

0.1UF

BYPASS=U0500.K14:6.35mm

6.3V

CERM

1

20%

2

603

1

20% 10V

2

402

R1270

0

21

PP1V05_S0_PCH_VCCACLKPLL_R

MIN_LINE_WIDTH=0.2 MM

5%

MIN_NECK_WIDTH=0.2 MM

1/16W

VOLTAGE=1.05V

MF-LF

402

PCH VCCASW BYPASS (PCH 1.05V ME CORE PWR)

PP1V05_S0

6 8

11 15 16 17 36 40 49 53

56 57 60 62

PCH VCC BYPASS (PCH 1.05V CORE PWR)

PP1V05_S0

6 8

11 15 16 17 36 40 49 53

56 57 60 62

PCH VCCHSIO BYPASS (PCH 1.05V PCIe/SATA/USB3 PWR)

PP1V05_S0SW_PCH_HSIO

8

11 56 60

NO STUFF

C1250

22UF

20%

6.3V

X5R-CERM-1

BYPASS=U0500.AE9:12.7mm

BYPASS=U0500.J11:12.7mm

BYPASS=U0500.K9:6.35mm

2.2UH-240MA-0.221OHM

BYPASS=U0500.A20:12.7mm

603

BYPASS=U0500.AE9:6.35mm

C1255

10UF

20%

6.3V X5R 603

BYPASS=U0500.J11:6.35mm

C1260

1UF

10%

6.3V

CERM

402

CRITICAL

L1270

0603

C1270

47UF

CERM-X5R

0805-1

1

C1251

1UF

10%

6.3V

2

CERM 402

1

C1256

1UF

10%

6.3V

2

CERM

402

BYPASS=U0500.AE8:6.35mm

1

C1261

1UF

6.3V

2

CERM

BYPASS=U0500.L10:6.35mm

BYPASS=U0500.M9:6.35mm

21

1

C1271

20%

4V

BYPASS=U0500.A20:12.7mm

47UF

2

CERM-X5R

0805-1

BYPASS=U0500.A20:6.35mm

PCH VCCIO BYPASS (PCH 1.05V USB2 PWR)

PP1V05_S0

6 8

11 15 16 17 36 40 49 53

56 57 60 62

BYPASS=U0500.AG16:6.35mm

PCH VCCCLK BYPASS (PCH 1.05V CLK PWR)

PP1V05_S0

6 8

11 15 16 17 36 40 49 53

56 57 60 62

1

C1257

1UF

10%

6.3V

2

CERM 402

1

C1262

10%

402

10UF

20%

6.3V

2

CERM-X5R 0402-1

BYPASS=U0500.J17:6.35mm

1

C1266

1UF

10%

6.3V 2

CERM

402

BYPASS=U0500.R21:6.35mm

C1264

1UF

6.3V CERM

C1267

1UF

6.3V CERM

1

10%

2

402

D

1

10%

2

402

C

PCH VCCACLKPLL FILTER/BYPASS (PCH 1.05V ACLK PLL PWR)

PP1V05_S0_PCH_VCCACLKPLL

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.075 MM VOLTAGE=1.05V

1

C1272

20%

4V

1UF

10% 10V

2

X5R 402

31mA Max

8

12

PCH VCCSUSHDA BYPASS (PCH 3.3V/1.5V HDA PWR)

PP1V5_S0SW_AUDIO_HDA

8

17 56

B

A

LPT-LP current estimates from Lynx Point-LP PCH EDS, doc #503118, v1.0 as well as from clarification email, from Srini, dated 9/10/2012 2:11pm.

C1210

BYPASS=U0500.AH14:6.35mm

1UF

6.3V CERM

CRITICAL

L1275

R1275

0

21

PP1V05_S0_PCH_VCC_ICC_R

MIN_LINE_WIDTH=0.2 MM

5%

1

10%

2

402

PP1V05_S0SW_PCH_HSIO

8

11 56 60

R1280

BYPASS=U0500.B18:12.7mm

MIN_NECK_WIDTH=0.2 MM

1/16W

VOLTAGE=1.05V

MF-LF

402

0

21

5% 1/16W MF-LF

CRITICAL

402

NO STUFF

L1280

2.2UH-240MA-0.221OHM

0603

NO STUFF

C1280

CERM-X5R

BYPASS=U0500.AA21:12.7mm

CRITICAL

L1290

2.2UH-240MA-0.221OHM

0603

C1290

CERM-X5R

BYPASS=U0500.B11:12.7mm

CRITICAL

L1295

2.2UH-240MA-0.221OHM

0603

C1295

CERM-X5R

BYPASS=U0500.B18:12.7mm

21

NO STUFF

1

47UF

0805-1

47UF

0805-1

47UF

0805-1

C1281

20%

4V

2

BYPASS=U0500.AA21:12.7mm

BYPASS=U0500.AA21:6.35mm

21

NO STUFF

1

C1291

20%

4V

2

BYPASS=U0500.B11:12.7mm

BYPASS=U0500.B11:6.35mm

21

NO STUFF

1

C1296

20%

4V

2

BYPASS=U0500.B18:6.35mm

47UF

CERM-X5R

0805-1

47UF

CERM-X5R

0805-1

47UF

CERM-X5R

0805-1

1

20%

4V

2

1

20%

4V

2

1

20%

4V

2

2.2UH-240MA-0.221OHM

BYPASS=U0500.J18:12.7mm

PCH OPI VCCAPLL FILTER/BYPASS (PCH 1.05V OPI PLL PWR)

PP1V05_S0_PCH_VCCAPLL_OPI

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.075 MM VOLTAGE=1.05V

1

C1282

1UF

10% 10V

2

X5R 402

PCH VCCSATA3PLL FILTER/BYPASS (PCH 1.05V SATA3 PLL PWR)

PP1V05_S0SW_PCH_VCCSATA3PLL

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.075 MM VOLTAGE=1.05V

1

C1292

1UF

10% 10V

2

X5R 402

PCH VCCUSB3PLL FILTER/BYPASS (PCH 1.05V USB3 PLL PWR)

PP1V05_S0SW_PCH_VCCUSB3PLL

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.075 MM VOLTAGE=1.05V

1

C1297

1UF

10% 10V

2

X5R 402

0603

C1275

21

47UF

20%

4V

CERM-X5R

0805-1

BYPASS=U0500.J18:12.7mm

1

C1276

47UF

CERM-X5R

0805-1

20%

2

BYPASS=U0500.J18:6.35mm

57mA Max

42mA Max83mA Max

41mA Max

6 3

PCH VCCCLK FILTER/BYPASS (PCH 1.05V VCCCLK PWR)

PP1V05_S0_PCH_VCC_ICC

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.075 MM VOLTAGE=1.05V

1

C1277

4V

2

8

12

8

14

1UF

10% 10V X5R 402

??mA Max

8

PAGE TITLE

PCH Decoupling

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=09/13/2012SYNC_MASTER=WILL_J43

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

12 OF 120

SHEET

11 OF 73

124578

SIZE

B

A

D

8 7 6 5 4 3

PPVRTC_G3H

8

13 17 60 62

CRITICAL

BROADWELL-ULT

(IPD)

(IPU)

OMIT_TABLE

U0500

2C+GT2

BGA

SYM 5 OF 19

RTC

AUDIO

JTAG

SATA_RN0/PERN6_L3 SATA_RP0/PERP6_L3

SATA_TN0/PETN6_L3 SATA_TP0/PETP6_L3

SATA_RN1/PERN6_L2 SATA_RP1/PERP6_L2

SATA_TN1/PETN6_L2 SATA_TP1/PETP6_L2

SATA_RN2/PERN6_L1 SATA_RP2/PERP6_L1

SATA_TN2/PETN6_L1 SATA_TP2/PETP6_L1

SATA_RN3/PERN6_L0

SATA

SATA_RP3/PERP6_L0

SATA_TN3/PETN6_L0 SATA_TP3/PETP6_L0

SATA0GP/GPIO34 SATA1GP/GPIO35 SATA2GP/GPIO36 SATA3GP/GPIO37

(IPU)

SATA_IREF

SATA_RCOMP

RSVD

J5 H5

B15 A15

J8 H8

A17 B17

J6 H6

B14 C15

F5 E5

C17 D17

V1 U1 V6 AC1

A12

L11

K10

C12

U3

PCIE_SSD_D2R_N<3> PCIE_SSD_D2R_P<3>

PCIE_SSD_R2D_C_N<3> PCIE_SSD_R2D_C_P<3>

PCIE_SSD_D2R_N<2> PCIE_SSD_D2R_P<2>

PCIE_SSD_R2D_C_N<2> PCIE_SSD_R2D_C_P<2>

PCIE_SSD_D2R_N<1> PCIE_SSD_D2R_P<1>

PCIE_SSD_R2D_C_N<1> PCIE_SSD_R2D_C_P<1>

PCIE_SSD_D2R_N<0> PCIE_SSD_D2R_P<0>

PCIE_SSD_R2D_C_N<0> PCIE_SSD_R2D_C_P<0>

XDP_FW_PME_L XDP_PCH_GPIO35 XDP_PCH_UART_SSD_L_BT_H XDP_SSD_PCIE0_SEL_L

NC NC

PCH_SATA_RCOMP

PCH_SATALED_L

PCIe Port assignments:

30 62 65

IN

30 62 65

IN

OUT OUT

IN IN

OUT OUT

IN IN

OUT OUT

IN IN

OUT OUT

IN IN IN

30 65

30 62 65

30 65

30 62 65

30 65

30 62 65

30 65

15 16

12 16

16

SSD Lane 3

SSD Lane 2

SSD Lane 1

SSD Lane 0

PP1V05_S0SW_PCH_VCCSATA3PLL

1

R1370

3.01K

1% 1/20W MF 201

2

PLACE_NEAR=U0500.C12:2.54mm

12

SATA Port assignments:

Primary HDD/SSD

Reserved: ODD

Unused

Secondary HDD/SSD

8

11

1

R1300

1/20W

20K

1

R1303

20K

5%

5% 1/20W

MF

201

MF 201

2

R1302

D

1

C1300

1UF

10% 10V X5R 402

1

C1303

1UF

10% 10V

2

X5R 402

C

330K

1/20W

5%

MF

201

2

59 63 67

OUT

59 63 67

OUT

59 63 67

OUT

59 63 67

OUT

1

R1301

1M

5% 1/20W MF 201

2

PCH_INTRUDER_L

PCH_INTVRMEN

PCH_SRTCRST_L

RTC_RESET_L

HDA_BIT_CLK

HDA_SYNC

HDA_RST_L

HDA_SDOUT

R1310

R1311

R1312

R1313

PCH_CLK32K_RTCX1

17

IN

NC_RTC_CLK32K_RTCX2

17

OUT

33

21

HDA_BIT_CLK_R

67

5%

1/20W

PLACE_NEAR=U0500.AW8:1.27mm

21

HDA_SYNC_R

67

1/20W

5% MF

PLACE_NEAR=U0500.AV11:1.27mm

21

HDA_RST_R_L

67

1/20W

PLACE_NEAR=U0500.AU8:1.27mm

HDA_SDIN0

59 63 67

IN

NC_HDA_SDIN1

62

21

HDA_SDOUT_R

17 67

1/20W

PLACE_NEAR=U0500.AU11:1.27mm

TP_PCH_I2S1_TXD TP_PCH_I2S1_SFRM

MF

201

MF5%

201

TP_PCH_I2S1_SCLK

XDP_CPUPCH_TRST_L

6

16 62 65

IN

XDP_PCH_TCK

16 62 67

IN IN

XDP_PCH_TDI

16 62 67

IN

XDP_PCH_TDO

16 62 67

OUT

XDP_PCH_TMS

16 62 67

IN

PCH_JTAGX

16

BI

AW5

RTCX1

AY5

RTCX2

AU6

INTRUDER*

AV7

INTVRMEN

AV6

SRTCRST*

AU7

RTCRST*

AW8

HDA_BCLK/I2S0_SCLK

AV11

HDA_SYNC/I2S0_SFRM

AU8

AY10 AU12

AU11

AW10 AV10

AY8

AU62

AE62

AD61

AE61

AD62

AL11

NC

AC4

NC

AE63

AV2

NC

(IPD-PLTRST#)

HDA_RST*/I2S_MCLK

HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD

HDA_SDO/I2S0_TXD

(IPD-PLTRST#)

HDA_DOCK_EN*/I2S1_TXD HDA_DOCK_RST*/I2S1_SFRM

I2S1_SCLK

PCH_TRST*

PCH_TCK

PCH_TDI

PCH_TDO

PCH_TMS

RSVD

JTAGX

RSVD SATALED*

12

D

C

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

BGA

TP_PCIE_CLK100M_ENETSDN TP_PCIE_CLK100M_ENETSDP

ENETSD_CLKREQ_L

12

PCIE_CLK100M_CAMERA_N

32 67

OUT

PCIE_CLK100M_CAMERA_P

32 67

OUT

CAMERA_CLKREQ_L

12 31

IN

PCIE_CLK100M_AP_N

29 62 67

B

A

PP3V3_S0

R1377 R1376 R1375

R1340 R1341 R1342 R1343 R1344 R1345

100K 100K 100K

100K 100K 100K 100K 100K 100K

62 63 72 8

11 13 15 17 18 26 30 34 36 37

38 39 40 41 42 43 54 57 59 60

21

5% MF

21

5%

21

5%

21 21

5%

21

5%

21

5%

1/20W 1/20W

1/20W

1/20W 1/20W

1/20W

1/20W 1/20W

MF5%

MF

MF MF5%

MF

MF MF

XDP_PCH_UART_SSD_L_BT_H

201

XDP_PCH_GPIO35

201

PCH_SATALED_L

201

ENETSD_CLKREQ_L

201

CAMERA_CLKREQ_L

201

AP_CLKREQ_L

201

FW_CLKREQ_L

201

TBT_CLKREQ_L

201

SSD_CLKREQ_L

201

12 16

12

12 31

12 29

12

12 25

12 30

OUT

29 62 67

OUT

12 29

IN

62

12

25 67

OUT

25 67

OUT

12 25

IN

30 62 65

OUT

30 62 65

OUT

12 30

IN

PCIE_CLK100M_AP_P

AP_CLKREQ_L

NC_PCIE_CLK100M_FWN NC_PCIE_CLK100M_FWP

FW_CLKREQ_L

PCIE_CLK100M_TBT_N PCIE_CLK100M_TBT_P

TBT_CLKREQ_L

PCIE_CLK100M_SSD_N PCIE_CLK100M_SSD_P

SSD_CLKREQ_L

C43

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

U2

PCIECLKRQ0*/GPIO18

B41

CLKOUT_PCIE_N1

A41

CLKOUT_PCIE_P1

Y5

PCIECLKRQ1*/GPIO19

C41

CLKOUT_PCIE_N2

B42

CLKOUT_PCIE_P2

AD1

PCIECLKRQ2*/GPIO20

B38

CLKOUT_PCIE_N3

C37

CLKOUT_PCIE_P3

N1

PCIECLKRQ3*/GPIO21

A39

CLKOUT_PCIE_N4

B39

CLKOUT_PCIE_P4

U5

PCIECLKRQ4*/GPIO22

B37

CLKOUT_PCIE_N5

A37

CLKOUT_PCIE_P5

T2

PCIECLKRQ5*/GPIO23

XTAL24_IN

XTAL24_OUT

CLOCK SIGNALS

DIFFCLK_BIASREF

CLKOUT_LPC_0

CLKOUT_LPC_1

(IPD-PWROK)

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

6 3

SYM 6 OF 19

RSVD RSVD

TESTLOW TESTLOW TESTLOW TESTLOW

A25 B25

K21 M21

C26

C35 C34 AK8 AL8

AN15

AP15

B35 A35

PCH_CLK24M_XTALIN PCH_CLK24M_XTALOUT

NC NC

PCH_DIFFCLK_BIASREF

PCH_TESTLOW_C35 PCH_TESTLOW_C34 PCH_TESTLOW_AK8 PCH_TESTLOW_AL8

LPC_CLK24M_SMC_R

17

IN

17

OUT

PP1V05_S0_PCH_VCCACLKPLL

1

R1380

3.01K

1% 1/20W MF 201

2

PLACE_NEAR=U0500.C26:2.54mm

10K

R1390

10K

R1391

10K

R1392

10K

R1393

17 67

OUT

8

11

B

21

5%

1/20W

21

5%

1/20W

21

5%

1/20W

21

1/20W

5%

201

MF

201

MF

201 201

MF

TP_LPC_CLK24M_LPCPLUS_R

TP_ITPXDP_CLK100MN TP_ITPXDP_CLK100MP

SIZE

A

D

SYNC_MASTER=WILL_J43 SYNC_DATE=12/17/2012

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

PCH Audio/JTAG/SATA/CLK

Apple Inc.

R

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

<SCH_NUM>

13 OF 120

12 OF 73

124578

8 7 6 5 4 3

12

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

BGA

D

59 60 62 63 72 8

11 12 13 15 17 18 26 30 34

36 37 38 39 40 41 42 43 54 57

13 18 35

OUT

SLP_S0# Isolation

PP3V3_S0

PM_SLP_S0_L

CRITICAL

74LVC1G08

SOT891

4

6

U1420

08

1

C1420

0.1UF

10% 10V

2

X5R-CERM 0201

2

1

NC

53

R1400 kept for debug purposes.

37

IN

NO STUFF

R1400

1/20W

37

OUT

1

0

5%

MF

0201

2

17 35 62

16 17 35

13 17

15 16 18

57 62

13 16 35

35 36

13 27 35

PCH_SUSACK_L

PM_SYSRST_L

IN

PM_PCH_SYS_PWROK

IN

PM_PCH_PWROK

IN

PM_PCH_PWROK

IN

PLT_RESET_L

OUT

PM_RSMRST_L

IN

PCH_SUSWARN_L

PM_PWRBTN_L

IN

SMC_ADAPTER_EN

IN

PM_BATLOW_L

IN

PCH_PM_SLP_S0_L

TP_PCH_SLP_WLAN_L

AK2

SUSACK*

AC3

SYS_RESET*

AG2

SYS_PWROK

AY7

PCH_PWROK

AB5

APWROK

AG7

PLTRST*

AW6

RSMRST*

AV4

SUSWARN*/SUSPWRDNACK/GPIO30

AL7

PWRBTN*

AJ8

ACPRESENT/GPIO31

AN4

BATLOW*/GPIO72

AF3 AJ7

SLP_S0*

AM5

SLP_WLAN*/GPIO29

SYM 8 OF 19

SYSTEM POWER MANAGEMENT

(IPU)

(IPD-DeepSx)

(IPU)

(IPD-DeepSx)

DSWVRMEN

DPWROK

WAKE*

CLKRUN*/GPIO32

SUS_STAT*/GPIO61

SUSCLK/GPIO62

SLP_S5*/GPIO63

SLP_S4*

SLP_S3*

SLP_A*

SLP_SUS*

SLP_LAN*

AW7

AV5

AJ5

V5

AG4

AE6

AP5

AJ6

AT4

AL5

AP4

PCH_DSWVRMEN

PM_DSW_PWRGD

PCIE_WAKE_L

PM_CLKRUN_L

LPC_PWRDWN_L

PM_CLK32K_SUSCLK_R

PM_SLP_S5_L

PM_SLP_S4_L

PM_SLP_S3_L

TP_PM_SLP_A_L

PM_SLP_SUS_L

TP_PCH_SLP_LAN_L

13 29 31 62

IN

13 35 62

BI

35 62

OUT

36 67

OUT

13 35 57

OUT

13 18 29 34 35 57

OUT

13 17 18 35 57

OUT

13 40 57

OUT

PPVRTC_G3H

1

R1450

330K

5% 1/20W MF 201

2

IN

1

R1451

100K

5% 1/20W MF 201

2

8

12 17 60 62

D

35

NC

SLP_S0# can be driven high outside of S0 U1420 ensures signal will only be high in S0.

C

AD4

B8

A9

C6

U6 P4 N4 N2

U7 L1 L3 R5 L4

EDP_BKLCTL

EDP_BKLEN

EDP_VDDEN

PIRQA*/GPIO77 PIRQB*/GPIO78 PIRQC*/GPIO79 PIRQD*/GPIO80

PME*

GPIO55 GPIO52 GPIO54 GPIO51 GPIO53

54

OUT

13 54

OUT

13 58

OUT

13 26

IN

13 35

IN

13 62

IN

13 30

OUT

62

13 62

OUT

13 62

OUT

13 62

OUT

13 57 59 63

OUT

13 62

OUT

EDP_BKLT_PWM

EDP_BKLT_EN

EDP_PANEL_PWR

TBT_PWR_REQ_L SMC_RUNTIME_SCI_L HDMITBTMUX_FLAG SSD_BOOT

NC_PCI_PME_L

ODD_PWR_EN_L HDMITBTMUX_LATCH ENET_LOW_PWR AUD_PWR_EN AP_PCIE_DEV_WAKE

OMIT_TABLE

BROADWELL-ULT

SYM 9 OF 19

(IPU)

CRITICAL

U0500

2C+GT2

BGA

eDP

SIDEBAND

PCI

DDPB_CTRLCLK

DDPB_CTRLDATA

(IPD-PLTRST#)

DDPC_CTRLCLK

DDPC_CTRLDATA

(IPD-PLTRST#)

DISPLAY

DDPB_AUXN DDPC_AUXN

DDPB_AUXP DDPC_AUXP

DDPB_HPD

DDPC_HPD

EDP_HPD

B9 C9

D9 D11

C5 B6

B5 A6

C8

A8

D6

DP_TBTSNK0_DDC_CLK DP_TBTSNK0_DDC_DATA

DP_TBTSNK1_DDC_CLK DP_TBTSNK1_DDC_DATA

DP_TBTSNK0_AUXCH_C_N DP_TBTSNK1_AUXCH_C_N

DP_TBTSNK0_AUXCH_C_P DP_TBTSNK1_AUXCH_C_P

DP_TBTSNK0_HPD

DP_TBTSNK1_HPD

DP_INT_HPD

C

18 28

OUT

18 28

BI

18

OUT

18

BI

25 65

BI

18 25 65

BI

25 65

BI

18 25 65

BI

25

IN

18 25

IN

58

IN

SIZE

B

A

D

B

PP3V3_S5 PP3V3_S0

R1405 R1410 R1452 R1455 R1460

R1461 R1462 R1463 R1464

R1430

A

R1431 R1440

R1441 R1442 R1443

R1445 R1446 R1447 R1448 R1449

1K

10K

100K 100K 100K 100K 100K

100K 100K

100K 100K 100K 100K

100K 100K 100K 100K 100K

8

11 15 16 17 18 28 29 40 52 55

56 57 58 60 62 72 8

11 12 13 15 17 18 26 30 34 36

37 38 39 40 41 42 43 54 57 59

21

5%

21

5%

21

5%

21

5%

21

5%

21

5%

21

5%

21

5%

21

5%

21

5%

21

5%

21

5%

21

5%

21

5%

21

5%

21

5%

21

5%

21

5%

21

5%

21

5%

1/20W

1/20W 1/20W

1/20W

1/20W 1/20W

1/20W

60 62 63 72

MF

MF MF

MF

MF MF

MF

PM_PWRBTN_L

201

PM_BATLOW_L

201

PCIE_WAKE_L

201

PM_CLKRUN_L

201

PM_SLP_S5_L

201

PM_SLP_S4_L

201

PM_SLP_S3_L

201

PM_SLP_S0_L

201

PM_SLP_SUS_L

201

EDP_BKLT_EN

201

EDP_PANEL_PWR

201

TBT_PWR_REQ_L

201

SMC_RUNTIME_SCI_L

201

HDMITBTMUX_FLAG

201

SSD_BOOT

201

ODD_PWR_EN_L

201

HDMITBTMUX_LATCH

201

ENET_LOW_PWR

201

AUD_PWR_EN

201

AP_PCIE_DEV_WAKE

201

13 16 35

13 27 35

13 29 31 62

13 35 62

13 35 57

13 18 29 34 35 57

13 17 18 35 57

13 18 35

13 40 57

13 54

13 58

13 26

13 35

13 62

13 30

13 62

13 57 59 63

13 62

6 3

SYNC_MASTER=J43_MLB

PAGE TITLE

PCH PM/PCI/GFX

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=02/20/2013

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

14 OF 120

SHEET

13 OF 73

124578

8 7 6 5 4 3

12

PCIe Port Assignments:

PCIE_TBT_D2R_N<0>

25 67

IN

PCIE_TBT_D2R_P<0>

25 67

R1500

3.01K

1/20W

5% 5%

5%

201

1%

MF

1/20W 1/20W

1/20W

IN

25 67

OUT

25 67

OUT

25 67

IN

25 67

IN

25 67

OUT

25 67

OUT

25 67

IN

25 67

IN

25 67

OUT

25 67

OUT

25 67

IN

25 67

IN

25 67

OUT

25 67

OUT

29 62 67

IN

29 62 67

IN

29 67

OUT

29 67

OUT

62

63 66

IN

63 66

IN

63 66

OUT

63 66

OUT

32 67

IN

32 67

IN

32 67

OUT

32 67

OUT

1

2

MF MF

MF5%

MF

PCIE_TBT_R2D_C_N<0> PCIE_TBT_R2D_C_P<0>

PCIE_TBT_D2R_N<1> PCIE_TBT_D2R_P<1>

PCIE_TBT_R2D_C_N<1> PCIE_TBT_R2D_C_P<1>

PCIE_TBT_D2R_N<2> PCIE_TBT_D2R_P<2>

PCIE_TBT_R2D_C_N<2> PCIE_TBT_R2D_C_P<2>

PCIE_TBT_D2R_N<3> PCIE_TBT_D2R_P<3>

PCIE_TBT_R2D_C_N<3> PCIE_TBT_R2D_C_P<3>

PCIE_AP_D2R_N PCIE_AP_D2R_P

PCIE_AP_R2D_C_N PCIE_AP_R2D_C_P

NC_PCIE_FW_D2RN NC_PCIE_FW_D2RP

NC_PCIE_FW_R2D_CN NC_PCIE_FW_R2D_CP

NC_USB3RPCIE_SD_D2RN NC_USB3RPCIE_SD_D2RP

NC_USB3RPCIE_SD_R2D_CN NC_USB3RPCIE_SD_R2D_CP

PCIE_CAMERA_D2R_N PCIE_CAMERA_D2R_P

PCIE_CAMERA_R2D_C_N PCIE_CAMERA_R2D_C_P

PCH_PCIE_RCOMP

LPC_AD_R<0>

201

LPC_AD_R<1>

201

LPC_AD_R<2>

201

LPC_AD_R<3>

201

LPC_FRAME_R_L

201

SPI_CLK_R

44 67

OUT

SPI_CS0_R_L

44 67

OUT

Thunderbolt lane 0

D

Thunderbolt lane 1

Thunderbolt lane 2

Thunderbolt lane 3

AirPort

Reserved: FireWire

C

SD Card Reader (& Ethernet if combo)

Camera

PP1V05_S0SW_PCH_VCCUSB3PLL

8

11

PLACE_NEAR=U0500.A27:2.54mm

LPC_AD<0>

35 62 67

BI

LPC_AD<1>

35 62 67

BI

LPC_AD<2>

35 62 67

BI

B

LPC_AD<3>

35 62 67

BI

LPC_FRAME_L

35 62 67

OUT

R1540 R1541 R1542 R1543

R1544

33 33 33 33

33

21

21 21

21

TP_SPI_CS1_L

TP_SPI_CS2_L

SPI_MOSI_R

44 67

BI

SPI_MISO

44 67

BI

SPI_IO<2>

14 44 67

BI

SPI_IO<3>

14 44 67

BI

F10

PERN5_L0

E10

PERP5_L0

C23

PETN5_L0

C22

PETP5_L0

F8

PERN5_L1

E8

PERP5_L1

B23

PETN5_L1

A23

PETP5_L1

H10

PERN5_L2

G10

PERP5_L2

B21

PETN5_L2

C21

PETP5_L2

E6

PERN5_L3

F6

PERP5_L3

B22

PETN5_L3

A21

PETP5_L3

G11

PERN3

F11

PERP3

C29

PETN3

B30

PETP3

F13

PERN4

G13

PERP4

B29

PETN4

A29

PETP4

G17

PERN1/USB3RN3

F17

PERP1/USB3RP3

C30

PETN1/USB3TN3

C31

PETP1/USB3TP3

F15

PERN2/USB3RN4

G15

PERP2/USB3RP4

B31

PETN2/USB3TN4

A31

PETP2/USB3TP4

E15

NC NC

RSVD

E13

RSVD

A27

PCIE_RCOMP

B27 AV3

PCIE_IREF

(IPU)

AU14

LAD0

AW12

LAD1

AY12

LAD2

AW11

LAD3

AV12

LFRAME*

AA3

SPI_CLK

(IPU)

Y7

SPI_CS0*

(IPU)

Y4

SPI_CS1*

(IPU)

AC2

SPI_CS2*

(IPU)

AA2

SPI_MOSI

(IPU/IPD)

AA4

SPI_MISO

(IPU)

Y6

SPI_IO2

(IPU)

AF1

SPI_IO3

(IPU)

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 11 OF 19

USB

PCI-E

OC0*/GPIO40 OC1*/GPIO41 OC2*/GPIO42 OC3*/GPIO43

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 7 OF 19

SMBALERT*/GPIO11

LPC

SML0ALERT*/GPIO60

SMBUS

SML1ALERT*/PCHHOT*/GPIO73

SML1CLK_GPIO75

SML1DATA/GPIO74

SPI

(IPU/IPD)

C-LINK

USB2N0 USB2P0

USB2N1 USB2P1

USB2N2 USB2P2

USB2N3 USB2P3

USB2N4 USB2P4

USB2N5 USB2P5

USB2N6 USB2P6

USB2N7 USB2P7

(IPD)

USB3RN1 USB3RP1

USB3TN1 USB3TP1

USB3RN2 USB3RP2

USB3TN2 USB3TP2

USBRBIAS*

USBRBIAS

RSVD RSVD

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK

CL_DATA

CL_RST*

AN8 AM8

AR7 AT7

AR8 AP8

AR10 AT10

AM15 AL15

AM13 AN13

AP11 AN11

AR13 AP13

G20 H20

C33 B34

E18 F18

B33 A33

AJ10 AJ11

AN10 AM10

AL3 AT1 AH2

AN2

AP2 AH1

AL2

AN1 AK1

AU4

AU3 AH3

AF2

AD2

AF4

USB_EXTA_N USB_EXTA_P

USB_EXTB_N USB_EXTB_P

USB_BT_N USB_BT_P

NC_USB_IRN NC_USB_IRP

USB_TPAD_N USB_TPAD_P

TP_USB_5N TP_USB_5P

NC_USB_CAMERAN NC_USB_CAMERAP

NC_USB_SDN NC_USB_SDP

USB3_EXTA_D2R_N USB3_EXTA_D2R_P

USB3_EXTA_R2D_C_N USB3_EXTA_R2D_C_P

USB3_EXTB_D2R_N USB3_EXTB_D2R_P

USB3_EXTB_R2D_C_N USB3_EXTB_R2D_C_P

PCH_USB_RBIAS

66

NC NC

XDP_USB_EXTA_OC_L XDP_USB_EXTB_OC_L XDP_USB_EXTC_OC_L XDP_USB_EXTD_OC_L

PCH_SMBALERT_L

SMBUS_PCH_CLK SMBUS_PCH_DATA

WOL_EN

SML_PCH_0_CLK SML_PCH_0_DATA

PCH_SML1ALERT_L

SMBUS_SMC_1_S0_SCL SMBUS_SMC_1_S0_SDA

NC_CLINK_CLK

NC_CLINK_DATA

NC_CLINK_RESET_L

33 66

BI

33 66

BI

59 63 66

BI

59 63 66

BI

29 66

BI

29 66

BI

62

BI

62

BI

34 62 66

BI

34 62 66

BI

62

33 66

IN

33 66

IN

33 66

OUT

33 66

OUT

59 63 66

IN

59 63 66

IN

59 63 66

OUT

59 63 66

OUT

14 16 33

IN

14 16 59 63

IN

14 16

IN

14 16

IN

14

16 19 38 54 67

OUT

16 19 38 54 67

BI

14 62

OUT

38 67

OUT

38 67

BI

18 37

OUT

32 35 38 41 42 62 67 71

OUT

32 35 38 41 42 62 67 71

BI

62

USB Port Assignments:

Ext A (LS/FS/HS)

Ext B (LS/FS/HS)

BT

IR

Trackpad

Unused

Reserved: Camera

Reserved: SD (HS)

USB3 Port Assignments:

Ext A (SS)

Ext B (SS)

PLACE_NEAR=U0500.AJ10:2.54mm

1

R1570

22.6

1% 1/20W MF 201

2

SML1ALERT# pull-up not provided on this page, may be wire-ORed into other signals. Otherwise, 100k pull-up to 3.3V SUS required.

D

C

B

PP3V3_SUS

A

PP3V3_SUS

R1580 R1581 R1582 R1583

R1548 R1549

R1590 R1591

100K 100K 100K 100K

1K 1K

100K 100K

8

11 14 18 44 55 56 57 60 62

8

11 14 18 44 55 56 57 60 62

21

5% MF

1/20W

21

5%

1/20W

21

5%

1/20W

21

1/20W

21

5% MF

1/20W

21

5% MF

1/20W

21

5%

1/20W

21

1/20W

MF MF

MF5%

MF

MF5%

XDP_USB_EXTA_OC_L

201

XDP_USB_EXTB_OC_L

201

XDP_USB_EXTC_OC_L

201

XDP_USB_EXTD_OC_L

201

SPI_IO<2>

201

SPI_IO<3>

201

PCH_SMBALERT_L

201

WOL_EN

201

14 16 33

14 16 59 63

14 16

14 44 67

14

14 62

6 3

PAGE TITLE

PCH PCIe/USB/LPC/SPI/SMBus

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=09/13/2012SYNC_MASTER=WILL_J43

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

15 OF 120

SHEET

14 OF 73

124578

SIZE

A

D

8 7 6 5 4 3

BOM GROUP

RAMCFG_SLOT

PP3V3_S0

RAMCFG3:H

R1631

100K

1/20W

RAMCFG2:H

1

R1636

100K

5%

5% 1/20W

MF

201

2

RAMCFG1:H

D

GPIO12:

CR: TBT_GO2SX_BIDIR, requires 100k pull-up to SUS RR/FR: DPHDMIMUX_SEL_TBT, requires 100k pull-up to TBTLC

C

B

A

TPAD_SPI_INT_L

15 34

IN

11 12 13 15 17 18 26 30 34

PP3V3_S5 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3RS0_CAMERA PP3V3_S0 PP3V3_S0

TBTLC for CR, S0 for RR

R1610 R1614

R1615

R1616 R1617 R1618 R1619 R1620

R1622 R1623 R1624 R1625 R1626 R1627 R1628 R1629 R1630

R1632 R1633 R1634

R1637 R1638 R1640

R1652

R1691 R1693

R1694 R1695

59 60 62 63 72

PP3V3_S0

8 36 37 38 39 40 41 42 43 54 57

100K

100K 100K

100K 100K 100K 100K 100K

100K 100K 100K 100K 100K 100K 100K 100K 100K

100K 100K 100K

10K

100K

100K 100K 100K

SD_ON_MLB

SSD_LPSR:S0

60 62 63 72 8

11 12 13 15 17 18 26 30 34 36

37 38 39 40 41 42 43 54 57 59

1

100K

1/20W

1

5%

MF

201

2

R1635

TPAD_SPI_INT_GPIO28_L

1

R1681

0

5% 1/20W MF 0201

2

1

R1682

0

5% 1/20W MF 0201

2

TPAD_SPI_INT_GPIO46_L

8

11 13 16 17 18 28 29 40 52 55

56 57 58 60 62 72 15 18 19 34 38 39 56 60 62 63

15 18 19 34 38 39 56 60 62 63

31 39 60 62 63 72

8

11 12 13 15 17 18 26 30 34 36

37 38 39 40 41 42 43 54 57 59 8

11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57 59 62 63 72

21

1/20W

21

1/20W

5%

21

5% MF

1/20W

21

5%

1/20W

21

1/20W

5% MF

21

1/20W

5%

21

1/20W

21

1/20W

5% MF

21

5%

1/20W

21

5%

1/20W

21

1/20W

5%

21

1/20W

21

5%

1/20W

21

5%

1/20W

21

1/20W

21

1/20W

5%

21

5%

1/20W

21

1/20W

5%

21

5%

1/20W

21

1/20W

5%

NOSTUFF

21

1/20W

5%

21

1/20W

5%

21

1/20W

5%

21

5%

1/20W

21

1/20W

5%

21

5%

1/20W

21

5%

1/20W

21

5%

1/20W

RAMCFG0:H

R1611

100K

5% 1/20W MF 201

XDP_MLB_RAMCFG0 XDP_MLB_RAMCFG1 XDP_MLB_RAMCFG2 XDP_MLB_RAMCFG3

13 15 16 18

MF5%

MF

MF MF5%

MF

MF MF

MF5%

MF MF

MF5% MF

MF

MF MF

MF

MF MF

MF

BOM OPTIONS

RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H

15 16 18

PLT_RESET_L

IN

1

R1621

100K

5%

1/20W

MF

201

2

18 25

OUT

15

1

R1639

100K

5%

1/20W

MF

201

30

18 31

R1641

201

201 201

201

201 201

201

201 201

201

201 201

201

201 201

201

2

OUT

1K

60

XDP_PCH_GPIO76

XDP_LPCPLUS_GPIO XDP_PCH_GPIO17

SD_RESET_L SMC_WAKE_SCI_L TPAD_SPI_INT_L TPAD_USB_IF_EN SSD_PWR_EN

HDD_PWR_EN XDP_SDCONN_STATE_CHANGE_L SD_PWR_EN TBT_PWR_EN XDP_JTAG_ISP_TCK XDP_JTAG_ISP_TDI JTAG_TBT_TMS_PCH PCH_HSIO_PWR_EN TPAD_SPI_IF_EN

SPIROM_USE_MLB CAMERA_PWR_EN_PCH TPAD_SPI_INT_GPIO46_L

SSD_SR_EN_L AP_S0IX_WAKE_SEL XDP_FW_PME_L

LPC_SERIRQ

BT_PWRRST_L

ENET_MEDIA_SENSE LCD_IRQ_L LCD_PSR_EN

R1680

100K

1/20W

1

5%

MF

201

2

21

1/20W

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

11 16 17 36 40 49 53 56

PP1V05_S0

6 8 57 60 62

R1650

PP3V3_S3

15 18 19 34 38 39 56 60 62 63

IN

XDP_PCH_GPIO76

15 16

BI

XDP_MLB_RAMCFG0

15 16 18

BI

HDMITBTMUX_SEL_TBT

25

BI

TP_MEM_VDD_SEL_1V5_L

18

OUT

XDP_LPCPLUS_GPIO

15 16 62

BI

XDP_PCH_GPIO17

15 16

IN

SD_RESET_L

15 63

OUT

SMC_WAKE_SCI_L

15 35

IN

TPAD_SPI_INT_GPIO28_L

15

IN

TPAD_USB_IF_EN

15 34

OUT

SSD_PWR_EN

15 30 56 57 62

OUT

PCH_TBT_PCIE_RESET_L

HDD_PWR_EN

15 62

OUT

XDP_SDCONN_STATE_CHANGE_L

15 16 63

BI

SD_PWR_EN

15 63

OUT

TBT_PWR_EN

15 25

OUT

XDP_JTAG_ISP_TCK

15 16 18 25

OUT

XDP_JTAG_ISP_TDI

15 16 18 25

OUT

JTAG_TBT_TMS_PCH

15 18

OUT

PCH_HSIO_PWR_EN

15 56

OUT

TPAD_SPI_IF_EN

15 34

OUT

XDP_MLB_RAMCFG3

15 16 18

BI

SPIROM_USE_MLB

15 44 62

BI

CAMERA_PWR_EN_PCH

15 18

OUT

TPAD_SPI_INT_GPIO46_L

15

IN

XDP_MLB_RAMCFG1

15 16 18

BI

XDP_MLB_RAMCFG2

15 16 18

BI

SSD_SR_EN_L

15 30 62

OUT

AP_S0IX_WAKE_SEL

15 29

OUT

SSD_RESET_L

CAM_PCIE_RESET_L

PCH_TCO_TIMER_DISABLE

201

MF5%

15 16

15 16 62

15 16

R1616 should also be stuffed if

15 63

platform does not use SD card

15 35

15 34

SSD_LPSR:S0 BOM option is on R1620

15 30 56 57 62

15 62

15 16 63

15 63

15 25

15 16 18 25

15 18

15 56

15 34

15 44 62

15 18

15

15 30 62

15 29

12 16

15 35 62

15 62

Stuffed R1632

No-Stuffed R1634

SSD_LPSR:S3

R1696

100K

1/20W

1

5%

MF

201

2

P1

AU2

AM7

AD6

Y1

T3

AD5

AN5

AD7

AN3

AG6

AP1

AL4

AT5

AK4

AB6

U4

Y3

P3

Y2

AT3

AH4

AM4

AG5

AG3

AM3

AM2

P2

C4

L2

N5

V2

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 10 OF 19

BMBUSY*/GPIO76

GPIO8

LAN_PHY_PWR_CTRL/GPIO12

GPIO15

(IPD-RSMRST#)

GPIO16

GPIO17

GPIO24

GPIO27

(IPD-DeepSx)

GPIO28

GPIO26

GPIO56

GPIO57

GPIO58

GPIO59

GPIO44

GPIO47

GPIO48

GPIO49

GPIO50

HSIOPC/GPIO71

GPIO13

GPIO14

GPIO25

GPIO45

GPIO46

GPIO9

GPIO10

DEVSLP0/GPIO33

SDIO_POWER_EN/GPIO70

DEVSLP1/GPIO38

DEVSLP2/GPIO39

SPKR/GPIO81

(IPD-PLTRST#)

THERMTRIP*

RCIN*/GPIO82

PCH_OPI_COMP

CPU/MISC

GSPI0_CS*/GPIO83

GSPI0_CLK/GPIO84

GSPI0_MISO/GPIO85

(IPD)

GSPI0_MOSI/GPIO86

(IPD-PLTRST#)

GSPI1_CS*/GPIO87

GSPI1_CLK/GPIO88

GSPI1_MISO/GPIO89

(IPD)

GSPI_MOSI/GPIO90

UART0_RXD/GPIO91

UART0_TXD/GPIO92

UART0_RTS*/GPIO93

UART0_CTS*/GPIO94

UART1_RXD/GPIO0

LPIO

GPIO

UART1_TXD/GPIO1

UART1_RST*/GPIO2

UART1_CTS*/GPIO3

I2C0_SDA/GPIO4

I2C0_SCL/GPIO5

I2C1_SDA/GPIO6

I2C1_SCL/GPIO7

SDIO_CLK/GPIO64

SDIO_CMD/GPIO65

SDIO_D0/GPIO66

(IPD-PLTRST#)

SDIO_D1/GPIO67

SDIO_D2/GPIO68

SDIO_D3/GPIO69

SERIRQ

RSVD RSVD

D60

V4

T4

AW15

AF20 AB21

R6

L6

N6

L8

R7

L5

N7

K2

J1

K3

J2

G1

K4

G2

J3

J4

F2

F3

G4

F1

E3

F4

D3

E4

C3

E2

PM_THRMTRIP_L

TBT_CIO_PLUG_EVENT_L

LPC_SERIRQ

PCH_OPI_COMP

NC NC

AUD_SPI_CS_L

AUD_SPI_CLK

AUD_SPI_MISO

AUD_SPI_MOSI

TPAD_SPI_CS_L

TPAD_SPI_CLK

TPAD_SPI_MISO

TPAD_SPI_MOSI

PCH_BT_UART_D2R

PCH_BT_UART_R2D

PCH_BT_UART_RTS_L

PCH_BT_UART_CTS_L

PCH_UART1_RXD

PCH_UART1_TXD

JTAG_ISP_TDO

PCH_UART1_CTS_L

AP_S0IX_WAKE_L

AP_RESET_L

PCH_I2C1_SDA

PCH_I2C1_SCL

TBT_POC_RESET_L

BT_PWRRST_L

PCH_STRP_TOPBLK_SWP_L

ENET_MEDIA_SENSE

LCD_IRQ_L

LCD_PSR_EN

6 3

1/20W

12

1

1K

5%

MF

201

2

36 65

OUT

15 62

OUT

15 62

15

OUT

IN

BI

18 25

15 35 62

15 34

15 34 66

15 18

15 29

26

15 62

37

15 62

Pull-up/down on chipset support page (depends on TBT controller) Cactus Ridge: Alias to TBT_CIO_PLUG_EVENT, requires pull-down. Redwood Ridge: Alias to TBT_CIO_PLUG_EVENT_L, requires pull-up (S0).

PLACE_NEAR=U0500.AW15:2.54mm

1

R1655

49.9

1% 1/20W MF 201

2

PLT_RESET_L

1

R1671

100K

5% 1/20W MF 201

2

OUT

29

IN

13 15 16 18

Pull-up on TBT page

Requires connection to SMC via 1K series R

AUD_SPI_CS_L

15 62

AUD_SPI_CLK

15 62

AUD_SPI_MISO

15 62

AUD_SPI_MOSI

15 62

TPAD_SPI_CS_L

15 34

TPAD_SPI_CLK

15 34 66

TPAD_SPI_MISO

15 34 66

TPAD_SPI_MOSI

15 34 66

PCH_BT_UART_D2R

15 62

PCH_BT_UART_R2D

15 62

PCH_UART1_RXD

15

PCH_UART1_TXD

15

JTAG_ISP_TDO

15 18

PCH_UART1_CTS_L

15

AP_S0IX_WAKE_L

15 29

PCH_I2C1_SDA

15

PCH_I2C1_SCL

15

PCH_BT_UART_RTS_L

15 62

PCH_BT_UART_CTS_L

15 62

PAGE TITLE

R1660 R1661 R1662 R1663

R1664 R1665 R1666 R1667

R1668 R1669

R1672 R1673 R1674 R1675

R1676

R1678 R1679

R1670 R1677

100K 100K 100K 100K

47K 47K 47K 47K

47K 47K

100K

47K

100K

2.2K

47K 47K

PCH GPIO/MISC/LPIO

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

11 12 13 15 17 18 26 30 34

59 60 62 63 72

PP3V3_S0

8 36 37 38 39 40 41 42 43 54 57

21

21 21

21

21 21

21

21 21

21

21 21

5%

5% 5%

5%

5% 5%

5%

5% 5%

5%

5% 5%

5%

1/20W

MF

1/20W

MF MF

1/20W

MF

1/20W

MF

1/20W

MF MF

1/20W

MF

1/20W

MF MF

1/20W

MF

1/20W

MF

1/20W

MF

1/20W

MF

1/20W

MF

1/20W

MF

1/20W

SYNC_DATE=01/14/2013SYNC_MASTER=WILL_J43

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

16 OF 120

SHEET

15 OF 73

D

C

201

201 201

201

201 201

201

201 201

201

201 201

201

B

A

SIZE

D

124578

8 7 6 5 4 3

12

PP1V05_S0

6 8

11 15 16 17 36 40 49 53

0.1UF

6.3V 0201

XDP

56 57 60 62

1

R1830

150

5% 1/16W MF-LF 402

2

OBSFN_A0 OBSFN_A1

OBSDATA_A0 OBSDATA_A1

OBSDATA_A2 OBSDATA_A3

OBSFN_B0 OBSFN_B1

OBSDATA_B0 OBSDATA_B1

OBSDATA_B2 OBSDATA_B3

PWRGD/HOOK0

VCC_OBS_AB

XDP

1

R1831

1K

10%

5% 1/16W

2

MF-LF 402

2

C1800

0.1UF

CERM-X5R

Extra BPM Testpoints

XDP_BPM_L<2>

6

65

IN

XDP_BPM_L<3>

6

65

IN

XDP_BPM_L<4>

6

65

IN

XDP_BPM_L<5>

6

65

IN

XDP_BPM_L<6>

6

65

IN

XDP_BPM_L<7>

6

65

IN

D

CPU_VCCST_PWRGD

8

17

IN

PM_PWRBTN_L

13 35

OUT

PM_PCH_SYS_PWROK

13 17 35

OUT

XDP_CPU_TCK

6

16 62 65

C

OUT

PCH_JTAGX

12 16

OUT

1

TP

TP1802

TP-P6

1

TP

TP1803

TP-P6

1

TP

TP1804

TP-P6

1

TP

TP1805

TP-P6

1

TP

TP1806

TP-P6

1

TP

TP1807

TP-P6

PLACE_NEAR=U0500.C61:2.54mm

PLACE_NEAR=U5000.J3:2.54mm

R1800

R1802

R1804

R1835

XDP_CPU_PREQ_L

6

62 65

BI

XDP_CPU_PRDY_L

6

62 65

IN

CPU_CFG<0>

6

65

IN

CPU_CFG<1>

6

65

IN

CPU_CFG<2>

6

65

IN

CPU_CFG<3>

6

62 65

IN

XDP_BPM_L<0>

6

65

IN

XDP_BPM_L<1>

6

65

IN

CPU_CFG<4>

6

65

IN

CPU_CFG<5>

6

65

IN

CPU_CFG<6>

6

65

XDP

1K

0

XDP

21

5%

1/20W

MF

5%

1/20W

MF

5%

PLACE_NEAR=J1800.58:28mm

1/20W

MF-LF1/16W

MF

201

0201

402

0201

IN

6

65

IN

8

OUT

14 19 38 54 67

BI

14 19 38 54 67

IN

12 16 62 67

OUT

CPU_CFG<7>

XDP_CPU_VCCST_PWRGD

62

XDP_CPU_PWRBTN_L

CPU_PWR_DEBUG XDP_SYS_PWROK

62

SMBUS_PCH_DATA SMBUS_PCH_CLK XDP_PCH_TCK

C1804

CERM-X5R

XDP_CPU_PRESENT_L

PCH XDP Signals

These signals do not connect to XDP connector in this architecture, only accessible via Top-Side Probe. Nets are listed here to show XDP associations and to make clear what restrictions exist on PCH GPIOs when Top-Side Probe is used for PCH debug.

PCH/XDP Signals

XDP_MLB_RAMCFG0

15 18

B

A

BI

XDP_USB_EXTA_OC_L

14 16 33 14 16 33

OUT

XDP_USB_EXTB_OC_L

14 16 59 63

OUT

XDP_USB_EXTC_OC_L

14

OUT

XDP_USB_EXTD_OC_L

14

IN

XDP_SDCONN_STATE_CHANGE_L

15 16 63

OUT

XDP_MLB_RAMCFG1

15 18

BI

XDP_MLB_RAMCFG2

15 18

BI

XDP_MLB_RAMCFG3

15 18

BI

XDP_JTAG_ISP_TCK

15 16 18 25 15 16 18 25

IN

XDP_FW_PME_L

12 15

OUT

XDP_PCH_GPIO35

12

OUT

XDP_PCH_UART_SSD_L_BT_H

12

OUT

XDP_SSD_PCIE0_SEL_L

12

OUT

XDP_LPCPLUS_GPIO

15 16 62

BI

XDP_PCH_GPIO17

15

OUT

XDP_PCH_GPIO76

15

BI

XDP_JTAG_ISP_TDI

15 16 18 25 15 16 18 25

IN

MAKE_BASE=TRUE

R1884

MAKE_BASE=TRUE

Unused & MLB_RAMCFGx GPIOs have TPs.

USB Overcurrents are aliased, do not cause USB OC# events during PCH debug.

SDCONN_STATE_CHANGE_L is aliased, do not plug/unplug SD Cards during PCH debug.

JTAG_ISP (non-TMS) nets are aliased, do not attempt bit-banged JTAG during PCH debug.

NOTE: Should force PCH GPIO47 high to ensure TBT router powered to avoid leakage/clamping of signals.

SSD_PCIEx_SEL_L straps are connected via 1K to common net.

LPCPLUS_GPIO is aliased, do not attempt use during PCH debug.

1

TP

TP1870

TP-P6

1

TP

TP1873

TP-P6

1

TP

TP1874

TP-P6

1

TP

TP1876

TP-P6

1

TP

TP1877

TP-P6

1

TP

TP1878

TP-P6

1

TP

TP1879

TP-P6

1

TP

TP1880

TP-P6

1

TP

TP1881

TP-P6

1K

1

TP-P6

TP

21

5%

TP1886 TP1887

1/20W

MF

Non-XDP Signals

XDP_USB_EXTA_OC_L

XDP_USB_EXTB_OC_L

XDP_SDCONN_STATE_CHANGE_L

XDP_JTAG_ISP_TCK

NOTE: Must not short XDP pins together!

201

XDP_LPCPLUS_GPIO

XDP_JTAG_ISP_TDI

IN

OUT

BI

14 16 59 63

15 16 63

15 16 62

Merged (CPU/PCH) Micro2-XDP

CRITICAL XDP_CONN

J1800

DF40RC-60DP-0.4V

M-ST-SM1

62

61

1

8 7

9

10 12 11

14 13

16 15 18 17

20219

22 21 24 23

26 25

28 27 30329

32 31 34 33

36 35

38 37 40439

HOOK1

HOOK2 HOOK3

TCK1 TCK0

6.3V 0201

SDA SCL

XDP

1

10%

2

42 41

44 43 46 45

48 47

50549 52 51

54 53 56 55

58 57

60659

64 63

518S0847

CPU JTAG Isolation

PP5V_S0

17 32 43 49 50 54 56 57 59 60 62

PP3V3_S5

8

11 13 15 17 18 28 29 40 52

55 56 57 58 60 62 72

C1845

0.1UF

X5R-CERM

ALL_SYS_PWRGD

17 35 57

IN

NOTE: This is not the standard XDP pinout. Use with 921-0133 Adapter Flex to support chipset debug.

OBSFN_C0 OBSFN_C1

OBSDATA_C0 OBSDATA_C1

OBSDATA_C2 OBSDATA_C3

OBSFN_D0 OBSFN_D1

OBSDATA_D0 OBSDATA_D1

OBSDATA_D2 OBSDATA_D3

ITPCLK/HOOK4 ITPCLK#/HOOK5 VCC_OBS_CD RESET#/HOOK6 DBR#/HOOK7

TDO TRSTn TDI TMS XDP_PRESENT# XDP

1

C1801

0.1UF

10%

6.3V

2

CERM-X5R 0201

VCC

U1845

74LVC1G07GF

SOT891

2

A

1

NC NC

GND

6

Y

3

0201

1

10% 16V

2

NC

CPU_CFG<17> CPU_CFG<16>

CPU_CFG<8> CPU_CFG<9>

CPU_CFG<10> CPU_CFG<11>

CPU_CFG<19> CPU_CFG<18>

CPU_CFG<12> CPU_CFG<13>

CPU_CFG<14> CPU_CFG<15>

NC NC

XDP_CPURST_L

65

XDP_DBRESET_L

NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page

6

IN

6

IN

6

65

IN

6

65

IN

6

65

IN

6

65

IN

6

IN

6

IN

6

65

IN

6

65

IN

6

65

IN

6

65

IN

17 65

OUT

XDP_TRST_L

XDP

1

C1806

0.1UF

10%

6.3V

2

CERM-X5R 0201

PLACE_NEAR=J1800.51:28MM

PLACE_NEAR=J1800.55:28mm

1

R1845

330K

5% 1/20W MF 201

2

4

5

NC

XDP_JTAG_CPU_ISOL_L

R1805

CRITICAL

XDP

Q1840

DMN5L06VK-7

SOT563

CRITICAL

XDP

Q1840

DMN5L06VK-7

SOT563

CRITICAL

Q1842

DMN5L06VK-7

SOT563

CRITICAL

Q1842

DMN5L06VK-7

SOT563

3

6

XDP

3

XDP

6

16 62 65

6

16 62 65

XDP_CPU_TDO

XDP_CPU_TCK

R1810

PLACE_NEAR=U0500.F62:28mm

R1813

PLACE_NEAR=U0500.E60:28mm

TDI and TMS are terminated in CPU.

XDP

1K

21

PLT_RESET_L

5%

1/20W

PLACE_NEAR=U0500.AG7:2.54mm

201

MF

XDP_PCH_TDO

XDP_PCH_TDI XDP_PCH_TMS

5

VER 3

D

S G

4

2

VER 3

D

S G

1

5

VER 3

D

S G

4

2

VER 3

D

S G

1

MAKE_BASE=TRUE

PCH_JTAGX

12 16

XDP_PCH_TDO

12 16 62 67

XDP_PCH_TDI

12 16 62 67

XDP_PCH_TMS

12 16 62 67

XDP_PCH_TCK

12 16 62 67

XDP_CPUPCH_TRST_L

6

12 16 62 65

XDP_CPU_TDO

XDP_CPUPCH_TRST_L

XDP_CPUPCH_TRST_L XDP_CPUPCH_TRST_L

XDP_CPU_TDI

XDP_CPU_TMS

PLACE_NEAR=U0500.AE63:28mm

PLACE_NEAR=U0500.AE61:28mm

PLACE_NEAR=U0500.AD61:28mm

PLACE_NEAR=U0500.AD62:28mm

PLACE_NEAR=U0500.AE62:28mm

PLACE_NEAR=U0500.AU62:28mm

SYNC_MASTER=WILL_J43

PAGE TITLE

R1899

R1890

R1891

R1892

R1896

R1897

CPU/PCH Merged XDP

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

6 3

11 15 16 17 36 40 49 53

51

IN

OUT OUT

IN

6

12 16 62 65

OUT OUT

OUT

1K

51

PP1V05_S0

6 8 56 57 60 62

13 15 18

12 16 62 67

6

16 62 65

6

12 16 62 65

6

12 16 62 65

6

62 65

6

62 65

PP1V05_SUS

55 60

NO STUFF

XDP

21

5%

12

5%

12

5%

12

5%

12

5%

12

5%

12

5%

12

5%

1/20W

MF

1/20W

MF

1/20W

MF

1/20W

MF

1/20W

MF

1/20W

MF

1/20W

MF

1/20W

MF

SYNC_DATE=12/17/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

18 OF 120

SHEET

16 OF 73

124578

201

D

C

B

201

A

SIZE

D

8 7 6 5 4 3

This looks a little ugly to support new and old parts. With GreenCLK Rev C pin 5 must receive S5 power (Stuff R2042)

D

GreenCLK 25MHz Power Must be powered if any VDDIO is powered.

CAM XTAL Power TBT XTAL Power

C1905

12PF

2 1

5%

25V

NP0-C0G-CERM

NC

0201

NC

C1906

12PF

21

5%

25V

NP0-C0G-CERM

0201

C

C1915

6.8PF

21

+/-0.1PF

25V C0G

NC

0201

NC

C1916

6.8PF

21

+/-0.1PF

25V C0G

0201

LPC_CLK24M_SMC_R

12 67

IN

B

System RTC Power Source & 32kHz / 25MHz Clock Generator

Chipset uses 24MHz crystal, GreenCLK kept to save 1x 25MHz crystal & 1x 32kHz crystal

PP3V42_G3H

17 30 33 34 35 36 38 44 46 47 48 57 59 60 62 63

Coin-Cell: VBAT (300-ohm & 10uF RC) No Coin-Cell: 3.42V G3Hot (no RC)

PP3V3_S5

8

11 13 15 16 17 18 28 29 40

52 55 56 57 58 60 62 72

Coin-Cell & G3Hot: 3.42V G3Hot Coin-Cell & No G3Hot: 3.3V S5

PP3V3_S5RS3RS0_SYSCLKGEN

18

PP1V2_CAM_XTALPCIEVDD

31

PP3V3_TBTLC

18 25 26 60 62

C1924

0.1UF

10% 16V

X5R-CERM

0201

R1905

0

1/20W

0201

21

5% MF

SYSCLK_CLK25M_X2

67

CRITICAL

Y1905

42

25.000MHZ-12PF-20PPM

31

SM-3.2X2.5MM

NOTE: 30 PPM or better required for RTC accuracy

No Coin-Cell: 3.3V S5

1

C1922

0.1UF

10%

2

16V

X5R-CERM

0201

CKPLUS_WAIVE=PwrTerm2Gnd

SYSCLK_CLK25M_X2_R

67

NO STUFF

1

R1906

1M

5% 1/20W MF 201

2

SYSCLK_CLK25M_X1

67

1

2

No bypass necessary

C1902

1UF

20%

6.3V X5R 0201

PCH 24MHz Crystal

R1915

0

1/20W

0201

21

5%

MF

PCH_CLK24M_XTALOUT

1

R1916

1M

5% 1/20W MF 201

2

PCH_CLK24M_XTALIN

PCH_CLK24M_XTALOUT_R

CRITICAL

Y1915

NC

24.000MHZ-20PPM-6PF

NC

4 2

3 1

3.20X2.50MM-SM1

PCH 24MHz Outputs

LPC_CLK24M_SMC

MAKE_BASE=TRUE

LPC_CLK24M_SMC

PLACE_NEAR=U0500.AN15:5.1mm

R1927

22

5%

1/20W

MF

201

21

OUT

17 35 67

OUT

IN

17 35 67

NC

U1900

SLG3NB148CV

CRITICAL

11

VIOE_25M_A

6

VIOE_25M_B

14

VIOE_25M_C

3

X2

4

X1

7

NC_RTC_CLK32K_RTCX2

12 17

MAKE_BASE=TRUE

12

GND

TQFN

10

12

PCH Reset Button

59 60 62 63 72

PP3V3_S0

8

11 12 13 15 17 18 26 30 34

36 37 38 39 40 41 42 43 54 57

XDP

XDP_DBRESET_L

13

5

VDD

THRM

PAD

VG3HOT

32.768K

25M_A 25M_B 25M_C

VOUT

17216

NO_TEST=TRUE

VBAT and +V3.3A are internally ORed to create VDD_RTC_OUT.

+V3.3A should be first available ~3.3V power to reduce VBAT draw.

12

9

8

15

1

PCH_CLK32K_RTCX1

NC

SYSCLK_CLK25M_CAMERA SYSCLK_CLK25M_TBT PPVRTC_G3H

For SB RTC Power

1

C1910

1UF

20%

6.3V

2

X5R 0201

NC_RTC_CLK32K_RTCX2

8

12 13 60 62

12

OUT

32 67

OUT

25 67

OUT

12 17

IN

R1996

1/20W

0201

1

R1995

10K

5% 1/20W MF 201

2

0

21

PM_SYSRST_L

NO STUFF

MF 5%

1

R1997

0

5% 1/16W MF-LF 402

2

SILK_PART=SYS RESET

13 35 62 16 65

BIIN

8

11 56

PP1V5_S0SW_AUDIO_HDA

PP1V2_S3

19 20 21 22 23 40 51 60 68

CPU_MEMVTT_PWR_EN_LSVDDQ

6

IN

SPI_DESCRIPTOR_OVERRIDE_L

35

IN

PCH uses HDA_SDO as a power-up strap. If low, ME functions normally. If high, ME is disabled. This allows for full re-flashing of SPI ROM. SMC controls strap enable to allow in-field control of strap setting. Q1920 & 5V pull-up allows circuit to work regardless of HDA voltage.

8

11 13 15 16 17 18 28 29 40

52 55 56 57 58 60 62 72

Memory VTT Enable Level-Shifter

CPU output is on VDDQ rail (1.2V), TPS51916 has 1.8V Vih(min).

C1970

0.1UF

X5R-CERM

0201

1

10% 16V

2

NC

6

VCC

U1970

74AUP1G07GF

SOT891

2

A Y

1

NC NC

GND

3

4

5

PCH ME Disable Strap

PP3V3_S5

13 18 35 57

ALL_SYS_PWRGD

16 17 35 57

PM_SLP_S3_L

IN

Q1920

DMN5L06VK-7

SOT563

3

DMN5L06VK-7

VCCST (1.05V S0) PWRGD

C1930

0.1UF

10% 16V

X5R-CERM

0201

D

Q1920

SOT563

VER 3

1

2

VER 3

2

NC

5

SPI_DESCRIPTOR_OVERRIDE_LS5V

S G

SPI_DESCRIPTOR_OVERRIDE

4

6

D

SG

1

CRITICAL

U1930

74AUP1G09

6

SOT891

VCC

GND

4

YA

3

2

1

B

5

NC

16 32 43 49 50 54 56 57 59 60 62

PP3V3_S0

1

R1970

330K

5% 1/20W MF 201

2

PP5V_S0

1

R1931

10K

2

TPS51916 I(leak) = +/- 1uA, Vih(min) = 1.8V 33uW when driven-low

MEMVTT_PWR_EN

MAKE_BASE=TRUE

MEMVTT_PWR_EN

1

R1921

1K

5% 1/20W MF 201

2

HDA_SDOUT_R

IPD = 9-50k

PP1V05_S0

5% 1/20W MF 201

CPU_VCCST_PWRGD

60 62 63 72 8

11 12 13 15 17 18 26 30 34 36

37 38 39 40 41 42 43 54 57 59

17 51

OUT

1

R1920

100K

5% 1/20W MF 201

2

6 8

11 15 16 36 40 49 53 56 57

60 62

8

16

OUT

D

12 67

OUT

C

B

PP3V42_G3H

17 30 33 34 35 36 38 44 46 47 48 57 59 60 62 63

59 60 62 63 72

PP3V3_S0

8

11 12 13 15 17 18 26 30 34

36 37 38 39 40 41 42 43 54 57

CPU_VR_EN

8

49

IN

1

R1955

10K

5%

A

CPU_VR_READY

8

17 49

OUT

MAKE_BASE=TRUE

CPU_VR_READY

8

17 49

IN

1/20W

NO STUFF

MF

201

R1951

2

1/20W

0201

0

21

5%

MF

16 17 35 57

IN

26 27 35 36

IN

ALL_SYS_PWRGD

CPUVR_PGOOD_R

SMC_DELAYED_PWRGD

R1950

10K

1/20W

1

5%

MF

201

2

1

A

U1950

2

B

PCH PWROK Generation

BYPASS=U1950:5MM

1

C1950

0.1UF

10% 16V

08

74LVC2G08GT

8

4

2

SOT833

7

Y

X5R-CERM 0201

PM_S0_PGOOD

NO STUFF

R1961

R1963

100K

5%

1/20W

MF

201

1/20W

NO STUFF

2

R1960

0

5%

5% 1/20W

MF

0201

1

2

WF: Do we need this?

CKPLUS_WAIVE=UNCONNECTED_PINS

8

74LVC2G08GT

SOT833

5

A

3

Y

U1950

6

08

B

4

CKPLUS_WAIVE=UNCONNECTED_PINS

SYS_PWROK_R

R1962

1K

5%

1/20W

MF 201

6 3

21

PM_PCH_SYS_PWROK

PM_PCH_PWROK PM_PCH_PWROK

MAKE_BASE=TRUE

13 17

OUT

13 17

OUT

SIZE

A

D

13 16 35

OUT

PAGE TITLE

Chipset Support

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/09/2013SYNC_MASTER=J43_MLB1

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

19 OF 120

SHEET

17 OF 73

124578

8 7 6 5 4 3

12

R2016

1/20W

14 37

OUT

10K

1

5%

MF

201

2

DDC Pull-Ups

NO STUFF

1

2.2K

1/20W

1

R2021

2.2K

5%

5% 1/20W

MF

201

2

MAKE_BASE

TRUE

R2018

R2020

1

R2017

10K

5% 1/20W MF 201

2

TBT Aliases

MAKE_BASE

TRUE

MAKE_BASE

TRUE

TRUE TRUE

TRUE

PCH_SML1ALERT_L

NO STUFF

R2022

2.2K

1/20W

59 60 62 63 72

PP3V3_S0

8

11 12 13 15 17 18 26 30 34

36 37 38 39 40 41 42 43 54 57

TBT_CIO_PLUG_EVENT_L

1

R2019

10K

5%

1/20W

5% 1/20W

MF

201

2

DP_TBTSNK0_DDC_CLK DP_TBTSNK0_DDC_DATA

DP_TBTSNK1_HPD DP_TBTSNK1_ML_C_P<3..0> DP_TBTSNK1_ML_C_N<3..0> DP_TBTSNK1_AUXCH_C_P DP_TBTSNK1_AUXCH_C_N DP_TBTSNK1_DDC_CLK DP_TBTSNK1_DDC_DATA

XDP_JTAG_ISP_TCKXDP_JTAG_ISP_TCK

PP3V3_SUS

1

R2010

100K

5% 1/20W MF 201

2

1

R2023

2.2K

5%

5% 1/20W

MF

201

2

1

R2015

100K

5%

1/20W

MF

201

2

IN

D

C

1

R2014

10K

5% 1/20W MF 201

2

13 18 28

OUT

13 18 28

BI

13 18 25

IN

5

25 65

OUT

5

25 65

OUT

13 18 25

BI

65 13 18 25

BI

65

13 18

OUT OUT

8

11 14 44 55 56 57 60 62

15 16 18 25

B

Platform Reset Connections

Unbuffered

PLT_RESET_L

13 15 16

IN

R2071

0

21

5%

1/20W

MF

D

59 60 62 63 72 36 37 38 39 40

PP3V3_S0

8

11 12 13 15

17 18 26 30 34 41 42 43 54 57

1

C2071

0.1UF

10% 16V

2

X5R-CERM 0201

PP3V3_S5

8

11 13 15 16 17 18 28 29 40

52 55 56 57 58 60 62 72

NOSTUFF

BYPASS=U2030:3mm

C2030

C

PM_SLP_S4_L

13 18 29 34 35 57

IN

CAMERA_PWR_EN_PCH

15

IN

1

2

0.1UF

X5R-CERM

U2071

10% 10V

0201

CRITICAL

5

MC74VHC1G08

SC70-HF

4

3

1

2

U2030

1

NC

5 3

PLT_RST_BUF_L

1

R2070

100K

5% 1/20W MF 201

2

PCH_TBT_PCIE_RESET_L

IN

MAKE_BASE=TRUE

NOSTUFF

CRITICAL

74LVC1G08

6

SOT891

4

08

Scrub for Layout Optimization

Buffered

CAMERA_PWR_EN

R2072

0

5%

1/20W

MF

0201

NOSTUFF

R2089

0

5%

1/20W

MF

0201

OUT

31

0201

21

R2088

0

21

5%

1/20W

MF

0201

21

PCA9557D_RESET_L

SMC_LRESET_L

BKLT_PLT_RST_L

CAM_PCIE_RESET_L

PCH_TBT_PCIE_RESET_L

OUT

19

35

54

15 31

15 18 25 15 18 25

From RR

From PCH

Redwood Ridge JTAG Isolation

25

IN

15

IN

S0 pull-up on PCH page

PP3V3_S3

15 19 34 38 39 56 60 62 63

59 60 62 63 72

PP3V3_S0

8

11 12 13 15 17 18 26 30 34

36 37 38 39 40 41 42 43 54 57

PP3V3_S5

8

11 13 15 16 17 18 28 29 40

52 55 56 57 58 60 62 72

TBTLC can be on when S0 is off, and vice-versa

PP3V3_TBTLC

17 25 26 60 62

JTAG_TBT_TDO JTAG_ISP_TDO

JTAG_TBT_TMS_PCH

GreenCLK 25MHz Power

NO STUFF

R2040

0

21

5%

1/20W

MF

0201

NO STUFF

R2041

0

21

5%

1/20W

MF

0201

R2042

0

21

5%

1/20W

MF

0201

Isolation ensures no leakage to RR or PCH

1

R2061

100K

1/20W

C2060

0.1UF

20%

5%

10V

2

CERM

MF

201

402

2

52

VCC

U2060

74LVC2G07

SOT891

1

1A 1Y

3

2A 2Y

6

4

GND

PP3V3_S5RS3RS0_SYSCLKGEN

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V MAKE_BASE=TRUE

R2041/2 should be stuffed for GreekCLK A or B depending on S2 rail

R2042 should be stuffed for GreenCLK C

1

R2062

100K

5% 1/20W MF 201

2

S0 pull-up on PCH page

JTAG_TBT_TMS

OUT

To PCH

15

To RR

25

17 18

2.2k pull-ups are required by PCH to indicate active display interface.

DP++ spec violation, should remove!

59 60 62 63 72

PP3V3_S0

8

11 12 13 15 17 18 26 30 34

17 18

36 37 38 39 40 41 42 43 54 57

DP_TBTSNK0_DDC_CLK

13 18 28

DP_TBTSNK0_DDC_DATA

13 18 28

DP_TBTSNK1_DDC_CLK

13 18

DP_TBTSNK1_DDC_DATA

13 18

TBTSNK1_DDC is pulled-up just to indicate that DP port is used. No DDC on this port, AUX-only.

NOTE: Only DDC_DATA is sensed by PCH, so DDC_CLK pull-ups are unstuffed.

Thunderbolt Pull-up/downs

CR: TBT_GO2SX_BIDIR, requires 100k pull-up to SUS RR/FR: DPHDMIMUX_SEL_TBT, requires 100k pull-up to TBTLC (on TBT page)

Falcon Ridge PLUG_EVENT is active-low, always driven (pull-up)

TBT_CIO_PLUG_EVENT_L

15 18 25 15 18 25

OUT

Required for unused second TBT port

TBT_B_CIO_SEL

25

IN

DP_TBTPB_HPD

25

OUT

TBT_B_CONFIG2_RC

25

OUT

TBT_B_CONFIG1_BUF

25

OUT

TBT_B_LSRX

25

NC

NOTE: Solution shown is for LPT-LP. Other PCH’s may require isolation on TCK

R2030

0

21

5%

1/20W

MF

PP3V3_S5_DBGLED

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=3.3V

1

5%

MF

2

S4_PWR_EN

IN

PM_SLP_S4_L

IN

PM_SLP_S3_L

IN

PM_SLP_S0_L

IN

0201

DBGLED

A

D2091

GREEN-56MCD-2MA-2.65V LTQH9G-SM

K

PLACE_SIDE=BOTTOM SILK_PART=STBY_ON

DBGLED_S4_D

DBGLED

Q2090

DMN5L06VK-7

SOT563

VER 3

56 57 58 18 28 29

PP3V3_S5

8

11 13

15 16 17 40 52 55 60 62 72

PLACE_SIDE=BOTTOM

B

A

K

DBGLED

R2094

2 1

DBGLED_S5

DBGLED

D2090

GREEN-56MCD-2MA-2.65V LTQH9G-SM

PLACE_SIDE=BOTTOM SILK_PART=S5_ON

0

5% 1/16W MF-LF

402

DBGLED

R2090

1/20W

20K

201

28 56 57

13 18 29 34 35 57

13 17 35 57

13 35

Power State Debug LEDs

(For development only)

DBGLED

1

R2091

20K

5%

1/20W

MF

201

2

D

2

SG

DBGLED_S3DBGLED_S4

DBGLED

A

D2092

GREEN-56MCD-2MA-2.65V LTQH9G-SM

K

PLACE_SIDE=BOTTOM SILK_PART=S3_ON

DBGLED_S3_D

6

1

Q2090

DMN5L06VK-7

DBGLED

R2092

DBGLED

SOT563

VER 3

5

1/20W

20K

DBGLED

Q2091

DMN5L06VK-7

SOT563

VER 3

DBGLED

R2093

1/20W

2

20K

1

5%

MF

201

2

DBGLED_S0

DBGLED

A

D2095

GREEN-56MCD-2MA-2.65V LTQH9G-SM

K

PLACE_SIDE=BOTTOM SILK_PART=S0_ON

DBGLED_S0_D

6

D

SG

1

DBGLED

Q2091

DMN5L06VK-7

SOT563

VER 3

1

5%

MF

201

2

DBGLED_S0I3

DBGLED

A

D2093

GREEN-56MCD-2MA-2.65V LTQH9G-SM

K

PLACE_SIDE=BOTTOM SILK_PART=S0I3_ON

DBGLED_S0I3_D

3

D

SG

4

and TDI as well for PCH glitch-prevention.

NOTE: This reference schematic assumes PCH JTAG GPIOs are only used for Thunderbolt. If other ASIC JTAG signals are wired into these GPIOs different isolation techniques will likely be necessary.

DBGLED

1

R2095

1/20W

5

20K

5%

MF

201

2

3

D

SG

Renaming the pins N61 and P61 to remove automatic diffpari property

4

Pin N61 needs a TP for Power to perform iFDIM test

TP_CPU_RSVDN61

8

18

8

18

XDP_MLB_RAMCFG0

15 16

OUT

XDP_MLB_RAMCFG1

15 16

OUT

XDP_MLB_RAMCFG2

15 16

OUT

XDP_MLB_RAMCFG3

15 16

OUT

TP_CPU_RSVDN61

MAKE_BASE=TRUE

TP_CPU_RSVDP61TP_CPU_RSVDP61

MAKE_BASE=TRUE

8

18

8

18

RAM Configuration Straps

Pull-downs for chip-down RAM systems

RAMCFG3:L

R2050

1/20W

10K

RAMCFG2:L

1

5% MF

201

2

R2051

1/20W

10K

201

5% MF

RAMCFG1:L

1

2

R2052

10K

1/20W

DP_TBTSNK0_DDC_CLK

13 18 28

IN

DP_TBTSNK0_DDC_DATA

13 18 28

BI

DP_TBTSNK1_HPD

13 18 25

OUT

=DP_TBTSNK1_ML_C_P<3..0>

IN

=DP_TBTSNK1_ML_C_N<3..0>

IN

DP_TBTSNK1_AUXCH_C_P

13 18 25 65

BI

DP_TBTSNK1_AUXCH_C_N

13 18 25 65

BI

DP_TBTSNK1_DDC_CLK

13 18

IN

DP_TBTSNK1_DDC_DATA

13 18

BI

Single-port TBT implementation does not require DDC Crossbar

15 16 18 25

IN

XDP_JTAG_ISP_TDI XDP_JTAG_ISP_TDI

15 16 18 25

IN

No MAKE_BASE on TCK/TDI as these are provided on XDP page.

RAMCFG0:L

1

5% MF

201

2

R2053

1/20W

10K

1

5% MF

201

2

A

LPDDR3 Alias Support

TP_CPU_MEM_RESET_L

6

18

IN

TP_MEM_VDD_SEL_1V5_L

15 18

IN

PP0V6_S3_MEM_VREFDQ_A

18 19 20 21 68 18 19 20 21 68

PP0V6_S3_MEM_VREFCA_A PP0V6_S3_MEM_VREFCA_A

18 19 20 21 68 18 19 20 21 68

PP0V6_S3_MEM_VREFDQ_B PP0V6_S3_MEM_VREFDQ_B

18 19 22 23 68 18 19 22 23 68

PP0V6_S3_MEM_VREFCA_B PP0V6_S3_MEM_VREFCA_B

18 19 22 23 68 18 19 22 23 68

TP_CPU_MEM_RESET_L

MAKE_BASE=TRUE

TP_MEM_VDD_SEL_1V5_L

MAKE_BASE=TRUE

PP0V6_S3_MEM_VREFDQ_A

MAKE_BASE=TRUE

VOLTAGE=0.6V

6

15 18

18

6 3

SYNC_MASTER=J43_MLB

PAGE TITLE

Project Chipset Support

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/17/2013

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

20 OF 120

SHEET

18 OF 73

124578

SIZE

A

D

8 7 6 5 4 3

12

Page Notes

Power aliases required by this page:

- =PP3V3_S3_VREFMRGN

- =PPDDR_S3_MEMVREF

Signal aliases required by this page:

- =I2C_VREFDACS_SCL

- =I2C_VREFDACS_SDA

- =I2C_PCA9557D_SCL

- =I2C_PCA9557D_SDA

BOM options provided by this page:

- DDRVREF_DAC - Stuffs DAC margining circuit.

D

C

PP3V3_S3

15 18 19 34 38 39 56 60 62 63

B

A

DAC Channel:

PCA9557D Pin:

Nominal value

Margined target:

DAC range:

VRef current:

DAC step size:

MEM A VREF DQ

0.600V (DAC: 0x2E.5)

0.300V - 0.900V (+/- 300mV)

0.000V - 1.199V (0x00 - 0x5D)

+73uA - -73uA (- = sourced)

6.36mV / step @ output

DAC-Based Margining

DAC sets voltage level, PCA9557 & FETs enable outputs and disables margining after platform reset.

OMIT

R2218

SHORT

21

PP3V3_S3_VREFMRGN_DAC

402

MEM B VREF DQ

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

14 16 19 38 54

IN

67

14 16 19 38 54

BI

67

Addr=0x98(WR)/0x99(RD)

Addr=0x30(WR)/0x31(RD)

14 16 19 38 54 67

IN

14 16 19 38 54 67

BI

18

IN

BA

2

SMBUS_PCH_CLK

SMBUS_PCH_DATA

SMBUS_PCH_CLK SMBUS_PCH_DATA

PCA9557D_RESET_L

MEM A VREF CA

0.675V (DAC: 0x34)

0.337V - 1.013V (+/- 337.5mV)

0.000V - 1.354V (0x00 - 0x69) 0.000V - 2.694V (0x00 - 0xD1)

+82uA - -82uA (- = sourced)

6.36mV / step @ output

NONE NONE NONE

RST* on ’platform reset’ so that system watchdog will disable margining.

NOTE: Margining will be disabled across all soft-resets and sleep/wake cycles.

1

LPDDR3 (1.2V)

CPU-Based Margining

FETs for CPU isolation during DAC margining

CPU_DIMMA_VREFDQ

7

IN

CPU_DIMMB_VREFDQ

7

IN

NOTE: CPU DAC output step sizes: DDR3 (1.5V) 7.70mV per step DDR3L (1.35V) 6.99mV per step LPDDR3 (1.2V) ?.??mV per step

CPU_DIMM_VREFCA

7

1

2

C2202

CERM-X5R

0.1UF

1

2

10%

6.3V

0201

IN

DDRVREF_DAC

C2201

0.1UF

10%

6.3V CERM-X5R 0201

6

SCL

7

SDA

9

A0

10

A1

1

2

3

A0

4

A1

5

A2

1

SCL

2

SDA

MEM B VREF CA

C

4

NOTE: CPU has single output for VREFCA. Split into two signals for independent DAC margining support. When DAC margining VREFCA ensure VREFMRGN_CPU_EN is low to remove short due to CPU.

DDRVREF_DAC

C2200

2.2UF

20%

6.3V CERM

402-LF

DDRVREF_DAC

C

3

DDR3L (1.35V)

CPU_MEM_VREFDQ_A_ISOL

EN RC’s to avoid drain glitches May not be necessary due to C22x0

21

VREFMRGN_DQ_A_EN_RC

CPU_MEM_VREFDQ_B_ISOL

21

VREFMRGN_DQ_B_EN_RC

CPU_MEM_VREFCA_A_ISOL

21

VREFMRGN_CA_A_EN_RC

CPU_MEM_VREFCA_B_ISOL

21

VREFMRGN_CA_B_EN_RC

(All 4 R’s) DDRVREF_DAC

DDRVREF_DAC

21

VREFMRGN_DQ_A_RDIV

1%

1/20W

21

VREFMRGN_DQ_B_RDIV

1%

1/20W

21

VREFMRGN_CA_A_RDIV

1%

1/20W

21

VREFMRGN_CA_B_RDIV

1%

1/20W

DDRVREF_DAC

R2213

100K

1/20W

R2212

100K

1/20W

C2205

5%

MF

201

5%

MF

201

0.1UF

CERM-X5R

1

2

1

2

1

10%

6.3V 2

0201

DDRVREF_DAC

C2225

0.1UF

CERM-X5R

DDRVREF_DAC

C2245

0.1UF

CERM-X5R

DDRVREF_DAC

C2265

0.1UF

CERM-X5R

DDRVREF_DAC

C2285

0.1UF

CERM-X5R

MF

C2

C3

A2

A3

1

10%

6.3V 2

0201

1

10%

6.3V 2

0201

1

10%

6.3V 2

0201

1

10%

6.3V 2

0201

201

PP3V3_S3

CRITICAL DDRVREF_DAC

B1

U2204

MAX4253

V+

UCSP

C1

C4

V-

B4

CRITICAL DDRVREF_DAC

B1

U2204

MAX4253

V+

UCSP

A1

A4

V-

B4

Pins B1 & B4: CKPLUS_WAIVE=unconnected_pinsCKPLUS_WAIVE=unconnected_pins

THRM

PAD

CRITICAL DDRVREF_DAC

8

U2200

PCA9557

17

VDD

MSOP

GND

3

VCC

U2201

QFN

GND

1

VOUTA

2

VOUTB

4

VOUTC

DAC5574

5

VOUTD

NOTE: MEMVREG and SPARE share a DAC output, cannot enable both at the same time!

CRITICAL DDRVREF_DAC

16

6

P0

(OD)

7

P1

9

P2

10

P3

11

P4

12

P5

13

P6

14

P7

15

RESET*

8

2

S G

1

2

S G

1

5

S G

4

5

S G

4

VREFMRGN_DQ_A

VREFMRGN_DQ_B

VREFMRGN_CA_AB

VREFMRGN_MEMVREG

VREFMRGN_CPU_EN VREFMRGN_DQ_A_EN VREFMRGN_DQ_B_EN VREFMRGN_CA_A_EN VREFMRGN_CA_B_EN VREFMRGN_MEMVREG_EN VREFMRGN_SPARE_EN

NC

CRITICAL

Q2220

DMN5L06VK-7

VER 3

SOT563

D

6

CRITICAL

Q2260

DMN5L06VK-7

VER 3

SOT563

D

6

CRITICAL

Q2220

DMN5L06VK-7

VER 3

SOT563

D

3

CRITICAL

Q2260

DMN5L06VK-7

VER 3

SOT563

D

3

R2200

100K

1/20W

1

5%

MF

201

2

MEM VREG

DDRVREF_DAC

R2201

100K

1/20W

DDRVREF_DAC

R2202

100K

1/20W

DDRVREF_DAC

R2215

100K

1/20W

DDRVREF_DAC

R2207

100K

1/20W

R2226 R2246 R2266 R2286

1

5%

MF

201

2

1

5%

MF

201

2

1

5%

MF

201

2

1

5%

MF

201

2

DDRVREF_DAC

R2225

100K

5%

1/20W

MF

201

DDRVREF_DAC

R2245

100K

5%

1/20W

MF

201

DDRVREF_DAC

R2265

100K

5%

1/20W

MF

201

DDRVREF_DAC

R2285

100K

5%

1/20W

MF

201

4.02K

DDRVREF_DAC

D

LPDDR3 (1.2V)

1.200V (DAC: 0x5D)

0.800V - 1.600V (+/- 400mV)

5

DDR3L (1.35V)

1.343V (DAC: 0x68)

0.972V - 1.714V (+/- 371mV)

NOTE: LPDDR3 assumes TPS51916 supply with 28.7k/57.6k divider DDR3L assumes TPS51916 supply with 19.6k/57.6k divider

0.000V - 2.397V (0x00 - 0xBA)

+21uA - -21uA (- = sourced)

4.28mV / step @ output

+25uA - -25uA (- = sourced)

3.53mV / step @ output

6 3

DDRVREF_DAC

Q2225

2

DMN5L06VK-7

VER 3

SOT563

S G

1

Q2225 pin 6:

PLACE_NEAR=Q2220.6:2.54mm

DDRVREF_DAC

Q2265

2

DMN5L06VK-7

VER 3

SOT563

S G

1

Q2265 pin 6:

PLACE_NEAR=Q2260.6:2.54mm

DDRVREF_DAC

Q2225

5

DMN5L06VK-7

VER 3

SOT563

S G

4

DDRVREF_DAC

Q2265

5

DMN5L06VK-7

VER 3

SOT563

S G

4

R22x6 pin 2:

PLACE_NEAR=Q2225.1:2.54mm

PLACE_NEAR=Q2265.1:2.54mm

PLACE_NEAR=Q2225.4:2.54mm PLACE_NEAR=Q2265.4:2.54mm

15 18 19 34 38 39 56 60 62 63

VREFMRGN_MEMVREG_BUF

VREFMRGN_SPARE_BUF

CRITICAL

D

6

CRITICAL

D

6

CRITICAL

D

3

CRITICAL

D

3

VRef Dividers

Always used, regardless of margining option.

R2223

10

21

1%

1/20W

MF 201

PLACE_NEAR=Q2220.6:2mm

1

C2220

0.022UF

10%

6.3V

2

X5R-CERM 0201

MEM_VREFDQ_A_RC

R2243

10

1%

1/20W

MF 201

PLACE_NEAR=Q2260.6:2mm

1

C2240

0.022UF

10%

6.3V

2

X5R-CERM 0201

MEM_VREFDQ_B_RC

R2263

10

1%

1/20W

MF 201

PLACE_NEAR=Q2220.3:2mm

1

C2260

0.022UF

10%

6.3V

2

X5R-CERM 0201

MEM_VREFCA_A_RC

R2283

10

1%

1/20W

MF 201

PLACE_NEAR=Q2260.3:2mm

1

C2280

0.022UF

10%

6.3V

2

X5R-CERM 0201

MEM_VREFCA_B_RC

DDRVREF_DAC

R2214

38.3K

21

1%

1/20W

MF

201

DDRVREF_DAC

1

R2217

1M

5% 1/20W MF 201

2

21

PLACE_NEAR=R7415.2:1mm

PLACE_NEAR=R2221.2:1mm

PLACE_NEAR=R2241.2:1mm

PLACE_NEAR=R2261.2:1mm

PLACE_NEAR=R2281.2:1mm

DDRREG_FB

PP1V2_S3

1

R2221

8.2K

1% 1/20W MF 201

2

PLACE_NEAR=Q2220.6:3mm

PP0V6_S3_MEM_VREFDQ_A

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

1

R2222

8.2K

1%

1/20W

MF

201

2

R2220

24.9

21

1%

1/20W

MF

201

R2242

8.2K

1%

1/20W

MF

201

R2240

24.9

21

1%

1/20W

MF

201

R2262

8.2K

1%

1/20W

MF

201

R2260

24.9

21

1%

1/20W

MF

201

R2282

8.2K

1%

1/20W

MF

201

R2280

24.9

21

1%

1/20W

MF

201

51

OUT

SYNC_MASTER=WILL_J43

PAGE TITLE

1

2

1

2

1

2

1

R2241

8.2K

1% 1/20W MF 201

2

PLACE_NEAR=Q2260.6:3mm

PP0V6_S3_MEM_VREFDQ_B

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

1

R2261

8.2K

1% 1/20W MF 201

2

PLACE_NEAR=Q2220.3:3mm

PP0V6_S3_MEM_VREFCA_A

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

1

R2281

8.2K

1% 1/20W MF 201

2

PLACE_NEAR=Q2260.3:3mm

PP0V6_S3_MEM_VREFCA_B

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

DDR3 VREF MARGINING

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

17 20 21 22 23 40 51 60 68

SYNC_DATE=02/04/2013

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

22 OF 120

SHEET

19 OF 73

124578

18 20 21 68

18 22 23 68

18 20 21 68

18 22 23 68

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

D

LPDDR3 CHANNEL A (0-31)

U2300

LPDDR3-16GB

FBGA

NC NC NC NC NC NC NC NC NC NC NC NC

NC NC NC

1

C2300

0.1UF

10% 16V

2

X5R-CERM 0201

R2

P2 N2

N3

M3 F3

E3

E2 D2

C2

K3 K4

J3

J2

L3

L4

L8 G8

P8 D8

J8

B3

B4

H4

J11

A1

A2 A12

A13

B1 B13

T1

T13

U1

U2

U12 U13

C4

K9

R3

MEM_A_CAA<0>

24 61 68

IN

MEM_A_CAA<1>

24 61 68

IN

MEM_A_CAA<2>

24 61 68

IN

MEM_A_CAA<3>

24 61 68

IN

MEM_A_CAA<4>

24 61 68

IN

MEM_A_CAA<5>

24 61 68

IN

MEM_A_CAA<6>

7

24 61 68

IN

MEM_A_CAA<7>

24 61 68

IN

MEM_A_CAA<8>

24 61 68

IN

MEM_A_CAA<9>

24 61 68

IN

MEM_A_CKE<0>

7

24 68

IN

MEM_A_CKE<1>

7

24 68

IN

MEM_A_CLK_P<0>

7

24 68

IN

MEM_A_CLK_N<0>

7

24 68

IN

MEM_A_CS_L<0>

7

21 24 68

C

R2300

1/20W

243

1

1%

MF

201

2

R2301

1/20W

243

1

1%

MF

201

2

C2340

0.047UF

10%

6.3V X5R 201

1

C2341

0.047UF

10%

6.3V

2

X5R 201

IN

MEM_A_CS_L<1>

7

21 24 68

IN

MEM_A_ODT<0>

7

21 24 61 68

IN

MEM_A_ZQ<0> MEM_A_ZQ<1>

PP0V6_S3_MEM_VREFCA_A

18 19 21 68

PP0V6_S3_MEM_VREFDQ_A

18 19 21 68

B

PP1V2_S3

17 19 20 21 22 23 40 51 60 68

CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9

CKE0 CKE1

CK_T CK_C

CS0* CS1*

DM0 DM1 DM2 DM3

ODT

ZQ0 ZQ1

VREFCA VREFDQ

NU

NC

OMIT_TABLE

CRITICAL

1

C2301

0.1UF

10% 16V

2

X5R-CERM 0201

(1 OF 2)

EDFA232A1MA-GD-F

1

2

C2302

1UF

10% 10V X5R 402

DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQS0_C DQS1_C DQS2_C DQS3_C

DQS0_T DQS1_T DQS2_T DQS3_T

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9

P9

N9 N10

N11

M8 M9

M10

M11 F11

F10 F9

F8

E11 E10

E9

D9 T8

T9

T10 T11

R8 R9

R10

R11 C11

C10

C9 C8

B11

B10 B9

B8

L11 G11

P11

D11

L10 G10

P10

D10

1

C2303

1UF

10% 10V

2

X5R 402

=MEM_A_DQ<0> =MEM_A_DQ<1> =MEM_A_DQ<2> =MEM_A_DQ<3> =MEM_A_DQ<4> =MEM_A_DQ<5> =MEM_A_DQ<6> =MEM_A_DQ<7> =MEM_A_DQ<8> =MEM_A_DQ<9> =MEM_A_DQ<10> =MEM_A_DQ<11> =MEM_A_DQ<12> =MEM_A_DQ<13> =MEM_A_DQ<14> =MEM_A_DQ<15> =MEM_A_DQ<16> =MEM_A_DQ<17> =MEM_A_DQ<18> =MEM_A_DQ<19> =MEM_A_DQ<20> =MEM_A_DQ<21> =MEM_A_DQ<22> =MEM_A_DQ<23> =MEM_A_DQ<24> =MEM_A_DQ<25> =MEM_A_DQ<26> =MEM_A_DQ<27> =MEM_A_DQ<28> =MEM_A_DQ<29> =MEM_A_DQ<30> =MEM_A_DQ<31>

=MEM_A_DQS_N<0> =MEM_A_DQS_N<1> =MEM_A_DQS_N<2> =MEM_A_DQS_N<3>

=MEM_A_DQS_P<0> =MEM_A_DQS_P<1> =MEM_A_DQS_P<2> =MEM_A_DQS_P<3>

1

C2304

1UF

10% 10V

2

X5R 402

1

C2305

1UF

2

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

1

C2306

10UF

10% 10V X5R 402

2

20% 25V X5R-CERM 0603

1

C2307

2

10UF

20% 25V X5R-CERM 0603

20 21 22 23 55 60

17 19 20 21 22 23 40 51 60 68

PP1V8_S3

PP1V2_S3

A3

A4 A5

A6

A10

U3

U4

U5 U6

U10

A8 A9

D4

D5 D6

G5

H5 H6

H12

J5

J6

K5 K6

K12

L5 P4

P5

P6 U8

U9

F2 G2

H3

L2 M2

A11

C12

E8 E12

G12

H8

H9

H11

J9

J10

K8 K11

L12

N8 N12

R12 U11

VDD1

VDD2

VDDCA

VDDQ

U2300

LPDDR3-16GB

FBGA

(2 OF 2)

OMIT_TABLE

CRITICAL

EDFA232A1MA-GD-F

VSS

VSSCA

VSSQ

B2

B5 C5

E4

E5 F5

J12

K2 L6

M5 N4

N5

R4 R5

T2

T3 T4

T5

H2

C3

D3

F4 G3

G4

P3 M4

J4

B6

B12 C6

D12 E6

F6

F12 G6

G9

H10 K10

L9

M6 M12

N6 P12

R6

T6 T12

D

C

B

PP1V2_S3

17 19 20 21 22 23 40 51 60 68

1

C2320

1UF

10% 10V

2

X5R 402

PP1V2_S3

17 19 20 21 22 23 40 51 60 68

1

C2310

1UF

A

PP1V8_S3

20 21 22 23 55 60

10% 10V

2

X5R 402

1

C2330

1UF

10% 10V

2

X5R 402

1

C2321

2

1

C2311

2

1

C2331

2

1UF

10% 10V X5R 402

1UF

10% 10V X5R 402

1UF

10% 10V X5R 402

1

2

1

2

1

2

C2322

1UF

10% 10V X5R 402

C2312

10UF

20% 25V X5R-CERM 0603

C2332

10UF

20% 25V X5R-CERM 0603

1

C2323

2

1

C2333

2

10UF

20% 25V X5R-CERM 0603

10UF

20% 25V X5R-CERM 0603

1

C2324

10UF

20% 25V

2

X5R-CERM 0603

PLACEMENT_NOTE:

10uF caps are shared between DRAM. Distribute evenly.

6 3

SYNC_MASTER=MASTER

PAGE TITLE

LPDDR3 DRAM Channel A (0-31)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=MASTER

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

23 OF 120

SHEET

20 OF 73

124578

SIZE

A

D

8 7 6 5 4 3

12

D

LPDDR3 CHANNEL A (32-63)

U2400

LPDDR3-16GB

FBGA

NC NC NC NC NC NC NC NC NC NC NC NC

NC NC NC

1

C2400

0.1UF

10% 16V

2

X5R-CERM 0201

R2

P2 N2

N3

M3 F3

E3

E2 D2

C2

K3 K4

J3

J2

L3

L4

L8 G8

P8 D8

J8

B3

B4

H4

J11

A1

A2 A12

A13

B1 B13

T1

T13

U1

U2

U12 U13

C4

K9

R3

MEM_A_CAB<0>

24 61 68

IN

MEM_A_CAB<1>

24 61 68

IN

MEM_A_CAB<2>

24 61 68

IN

MEM_A_CAB<3>

24 61 68

IN

MEM_A_CAB<4>

24 61 68

IN

MEM_A_CAB<5>

24 61 68

IN

MEM_A_CAB<6>

7

24 61 68

IN

MEM_A_CAB<7>

24 61 68

IN

MEM_A_CAB<8>

24 61 68

IN

MEM_A_CAB<9>

24 61 68

IN

MEM_A_CKE<2>

7

24 68

IN

MEM_A_CKE<3>

7

24 68

IN

MEM_A_CLK_P<1>

7

24 68

IN

MEM_A_CLK_N<1>

7

24 68

IN

MEM_A_CS_L<0>

7

20 24 68

C

R2400

1/20W

243

1

1%

MF

201

2

R2401

1/20W

243

1

1%

MF

201

2

C2440

0.047UF

1

C2441

10%

6.3V X5R 201

0.047UF

10%

6.3V

2

X5R 201

IN

MEM_A_CS_L<1>

7

20 24 68

IN

MEM_A_ODT<0>

7

20 24 61 68

IN

MEM_A_ZQ<2> MEM_A_ZQ<3>

PP0V6_S3_MEM_VREFCA_A

18 19 20 68

PP0V6_S3_MEM_VREFDQ_A

18 19 20 68

B

PP1V2_S3

17 19 20 21 22 23 40 51 60 68

CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9

CKE0 CKE1

CK_T CK_C

CS0* CS1*

DM0 DM1 DM2 DM3

ODT

ZQ0 ZQ1

VREFCA VREFDQ

NU

NC

OMIT_TABLE

CRITICAL

1

C2401

0.1UF

10% 16V

2

X5R-CERM 0201

(1 OF 2)

EDFA232A1MA-GD-F

1

2

C2402

1UF

10% 10V X5R 402

DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQS0_C DQS1_C DQS2_C DQS3_C

DQS0_T DQS1_T DQS2_T DQS3_T

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9

P9

N9 N10

N11

M8 M9

M10

M11 F11

F10 F9

F8

E11 E10

E9

D9 T8

T9

T10 T11

R8 R9

R10

R11 C11

C10

C9 C8

B11

B10 B9

B8

L11 G11

P11

D11

L10 G10

P10

D10

1

C2403

1UF

10% 10V

2

X5R 402

=MEM_A_DQ<32> =MEM_A_DQ<33> =MEM_A_DQ<34> =MEM_A_DQ<35> =MEM_A_DQ<36> =MEM_A_DQ<37> =MEM_A_DQ<38> =MEM_A_DQ<39> =MEM_A_DQ<40> =MEM_A_DQ<41> =MEM_A_DQ<42> =MEM_A_DQ<43> MEM_A_DQ<32> =MEM_A_DQ<45> =MEM_A_DQ<46> =MEM_A_DQ<47> =MEM_A_DQ<48> =MEM_A_DQ<49> =MEM_A_DQ<50> =MEM_A_DQ<51> =MEM_A_DQ<52> =MEM_A_DQ<53> =MEM_A_DQ<54> =MEM_A_DQ<55> =MEM_A_DQ<56> =MEM_A_DQ<57> =MEM_A_DQ<58> =MEM_A_DQ<59> =MEM_A_DQ<60> =MEM_A_DQ<61> =MEM_A_DQ<62> =MEM_A_DQ<63>

=MEM_A_DQS_N<4> =MEM_A_DQS_N<5> MEM_A_DQS_N<6> =MEM_A_DQS_N<7>

=MEM_A_DQS_P<4> =MEM_A_DQS_P<5> MEM_A_DQS_P<6> =MEM_A_DQS_P<7>

1

C2404

1UF

10% 10V

2

X5R 402

1

C2405

1UF

2

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

7

61 68

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

7

61 68

BI

61

BI

61

BI

61

BI

7

61 68

BI

61

BI

1

C2406

10% 10V X5R 402

2

10UF

20% 25V X5R-CERM 0603

20 21 22 23 55 60

17 19 20 21 22 23 40 51 60 68

PP1V8_S3

PP1V2_S3

A3

A4 A5

A6

A10

U3

U4

U5 U6

U10

A8 A9

D4

D5 D6

G5

H5 H6

H12

J5

J6

K5 K6

K12

L5 P4

P5

P6 U8

U9

F2 G2

H3

L2 M2

A11

C12

E8 E12

G12

H8

H9

H11

J9

J10

K8 K11

L12

N8 N12

R12 U11

VDD1

VDD2

VDDCA

VDDQ

U2400

LPDDR3-16GB

FBGA

(2 OF 2)

OMIT_TABLE

CRITICAL

EDFA232A1MA-GD-F

VSS

VSSCA

VSSQ

B2

B5 C5

E4

E5 F5

J12

K2 L6

M5 N4

N5

R4 R5

T2

T3 T4

T5

H2

C3

D3

F4 G3

G4

P3 M4

J4

B6

B12 C6

D12 E6

F6

F12 G6

G9

H10 K10

L9

M6 M12

N6 P12

R6

T6 T12

D

C

B

PP1V2_S3

17 19 20 21 22 23 40 51 60 68

1

C2420

1UF

10% 10V

2

X5R 402

PP1V2_S3

17 19 20 21 22 23 40 51 60 68

1

C2410

1UF

A

PP1V8_S3

20 21 22 23 55 60

10% 10V

2

X5R 402

1

C2430

1UF

10% 10V

2

X5R 402

1

C2421

2

1

C2411

2

1

C2431

2

1UF

10% 10V X5R 402

1UF

10% 10V X5R 402

1UF

10% 10V X5R 402

1

2

1

2

1

2

C2422

1UF

10% 10V X5R 402

C2412

10UF

20% 25V X5R-CERM 0603

C2432

10UF

20% 25V X5R-CERM 0603

6 3

1

C2423

2

10UF

20% 25V X5R-CERM 0603

PLACEMENT_NOTE:

10uF caps are shared between DRAM. Distribute evenly.

SYNC_MASTER=MASTER

PAGE TITLE

LPDDR3 DRAM Channel A (32-63)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=MASTER

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

24 OF 120

SHEET

21 OF 73

124578

SIZE

A

D

8 7 6 5 4 3

12

D

LPDDR3 CHANNEL B (0-31)

U2500

LPDDR3-16GB

FBGA

NC NC NC NC NC NC NC NC NC NC NC NC

NC NC NC

1

C2500

0.1UF

10% 16V

2

X5R-CERM 0201

R2

P2 N2

N3

M3 F3

E3

E2 D2

C2

K3 K4

J3

J2

L3

L4

L8 G8

P8 D8

J8

B3

B4

H4

J11

A1

A2 A12

A13

B1 B13

T1

T13

U1

U2

U12 U13

C4

K9

R3

MEM_B_CAA<0>

24 61 68

IN

MEM_B_CAA<1>

24 61 68

IN

MEM_B_CAA<2>

24 61 68

IN

MEM_B_CAA<3>

24 61 68

IN

MEM_B_CAA<4>

24 61 68

IN

MEM_B_CAA<5>

24 61 68

IN

MEM_B_CAA<6>

7

24 61 68

IN

MEM_B_CAA<7>

24 61 68

IN

MEM_B_CAA<8>

24 61 68

IN

MEM_B_CAA<9>

24 61 68

IN

MEM_B_CKE<0>

7

24 68

IN

MEM_B_CKE<1>

7

24 68

IN

MEM_B_CLK_P<0>

7

24 68

IN

MEM_B_CLK_N<0>

7

24 68

IN

MEM_B_CS_L<0>

7

23 24 68

C

R2500

1/20W

243

1

1%

MF

201

2

R2501

1/20W

243

1

1%

MF

201

2

C2540

0.047UF

1

C2541

10%

6.3V X5R 201

0.047UF

10%

6.3V

2

X5R 201

IN

MEM_B_CS_L<1>

7

23 24 68

IN

MEM_B_ODT<0>

7

23 24 61 68

IN

MEM_B_ZQ<0> MEM_B_ZQ<1>

PP0V6_S3_MEM_VREFCA_B

18 19 23 68

PP0V6_S3_MEM_VREFDQ_B

18 19 23 68

B

PP1V2_S3

17 19 20 21 22 23 40 51 60 68

CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9

CKE0 CKE1

CK_T CK_C

CS0* CS1*

DM0 DM1 DM2 DM3

ODT

ZQ0 ZQ1

VREFCA VREFDQ

NU

NC

OMIT_TABLE

CRITICAL

1

C2501

0.1UF

10% 16V

2

X5R-CERM 0201

(1 OF 2)

EDFA232A1MA-GD-F

1

2

C2502

1UF

10% 10V X5R 402

DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQS0_C DQS1_C DQS2_C DQS3_C

DQS0_T DQS1_T DQS2_T DQS3_T

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9

P9

N9 N10

N11

M8 M9

M10

M11 F11

F10 F9

F8

E11 E10

E9

D9 T8

T9

T10 T11

R8 R9

R10

R11 C11

C10

C9 C8

B11

B10 B9

B8

L11 G11

P11

D11

L10 G10

P10

D10

1

C2503

1UF

10% 10V

2

X5R 402

=MEM_B_DQ<0> =MEM_B_DQ<1> =MEM_B_DQ<2> =MEM_B_DQ<3> =MEM_B_DQ<4> =MEM_B_DQ<5> =MEM_B_DQ<6> =MEM_B_DQ<7> =MEM_B_DQ<8> =MEM_B_DQ<9> =MEM_B_DQ<10> =MEM_B_DQ<11> =MEM_B_DQ<12> =MEM_B_DQ<13> =MEM_B_DQ<14> =MEM_B_DQ<15> =MEM_B_DQ<16> =MEM_B_DQ<17> =MEM_B_DQ<18> =MEM_B_DQ<19> =MEM_B_DQ<20> =MEM_B_DQ<21> =MEM_B_DQ<22> =MEM_B_DQ<23> =MEM_B_DQ<24> =MEM_B_DQ<25> =MEM_B_DQ<26> =MEM_B_DQ<27> =MEM_B_DQ<28> =MEM_B_DQ<29> =MEM_B_DQ<30> =MEM_B_DQ<31>

=MEM_B_DQS_N<0> =MEM_B_DQS_N<1> =MEM_B_DQS_N<2> =MEM_B_DQS_N<3>

=MEM_B_DQS_P<0> =MEM_B_DQS_P<1> =MEM_B_DQS_P<2> =MEM_B_DQS_P<3>

1

C2504

1UF

10% 10V

2

X5R 402

1

C2505

1UF

2

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

1

C2506

10% 10V X5R 402

2

10UF

20% 25V X5R-CERM 0603

20 21 22 23 55 60

17 19 20 21 22 23 40 51 60 68

PP1V8_S3

PP1V2_S3

A3

A4 A5

A6

A10

U3

U4

U5 U6

U10

A8 A9

D4

D5 D6

G5

H5 H6

H12

J5

J6

K5 K6

K12

L5 P4

P5

P6 U8

U9

F2 G2

H3

L2 M2

A11

C12

E8 E12

G12

H8

H9

H11

J9

J10

K8 K11

L12

N8 N12

R12 U11

VDD1

VDD2

VDDCA

VDDQ

U2500

LPDDR3-16GB

FBGA

(2 OF 2)

OMIT_TABLE

CRITICAL

EDFA232A1MA-GD-F

VSS

VSSCA

VSSQ

B2

B5 C5

E4

E5 F5

J12

K2 L6

M5 N4

N5

R4 R5

T2

T3 T4

T5

H2

C3

D3

F4 G3

G4

P3 M4

J4

B6

B12 C6

D12 E6

F6

F12 G6

G9

H10 K10

L9

M6 M12

N6 P12

R6

T6 T12

D

C

B

PP1V2_S3

17 19 20 21 22 23 40 51 60 68

1

C2520

1UF

10% 10V

2

X5R 402

PP1V2_S3

17 19 20 21 22 23 40 51 60 68

1

C2510

1UF

A

PP1V8_S3

20 21 22 23 55 60

10% 10V

2

X5R 402

1

C2530

1UF

10% 10V

2

X5R 402

1

C2521

2

1

C2511

2

1

C2531

2

1UF

10% 10V X5R 402

1UF

10% 10V X5R 402

1UF

10% 10V X5R 402

1

2

1

2

1

2

C2522

1UF

10% 10V X5R 402

C2512

10UF

20% 25V X5R-CERM 0603

C2532

10UF

20% 25V X5R-CERM 0603

6 3

1

C2523

2

10UF

20% 25V X5R-CERM 0603

PLACEMENT_NOTE:

10uF caps are shared between DRAM. Distribute evenly.

SYNC_MASTER=MASTER

PAGE TITLE

LPDDR3 DRAM Channel B (0-31)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=MASTER

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

25 OF 120

SHEET

22 OF 73

124578

SIZE

A

D

8 7 6 5 4 3

12

D

LPDDR3 CHANNEL B (32-63)

U2600

LPDDR3-16GB

FBGA

NC NC NC NC NC NC NC NC NC NC NC NC

NC NC NC

1

C2600

0.1UF

10% 16V

2

X5R-CERM 0201

R2

P2 N2

N3

M3 F3

E3

E2 D2

C2

K3 K4

J3

J2

L3

L4

L8 G8

P8 D8

J8

B3

B4

H4

J11

A1

A2 A12

A13

B1 B13

T1

T13

U1

U2

U12 U13

C4

K9

R3

MEM_B_CAB<0>

24 61 68

IN

MEM_B_CAB<1>

24 61 68

IN

MEM_B_CAB<2>

24 61 68

IN

MEM_B_CAB<3>

24 61 68

IN

MEM_B_CAB<4>

24 61 68

IN

MEM_B_CAB<5>

24 61 68

IN

MEM_B_CAB<6>

7

24 61 68

IN

MEM_B_CAB<7>

24 61 68

IN

MEM_B_CAB<8>

24 61 68

IN

MEM_B_CAB<9>

24 61 68

IN

MEM_B_CKE<2>

7

24 68

IN

MEM_B_CKE<3>

7

24 68

IN

MEM_B_CLK_P<1>

7

24 68

IN

MEM_B_CLK_N<1>

7

24 68

IN

MEM_B_CS_L<0>

7

22 24 68

C

R2600

1/20W

243

1

1%

MF

201

2

R2601

1/20W

243

1

1%

MF

201

2

C2640

0.047UF

1

C2641

10%

6.3V X5R 201

0.047UF

10%

6.3V

2

X5R 201

IN

MEM_B_CS_L<1>

7

22 24 68

IN

MEM_B_ODT<0>

7

22 24 61 68

IN

MEM_B_ZQ<2> MEM_B_ZQ<3>

PP0V6_S3_MEM_VREFCA_B

18 19 22 68

PP0V6_S3_MEM_VREFDQ_B

18 19 22 68

B

PP1V2_S3

17 19 20 21 22 23 40 51 60 68

CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9

CKE0 CKE1

CK_T CK_C

CS0* CS1*

DM0 DM1 DM2 DM3

ODT

ZQ0 ZQ1

VREFCA VREFDQ

NU

NC

OMIT_TABLE

CRITICAL

1

C2601

0.1UF

10% 16V

2

X5R-CERM 0201

(1 OF 2)

EDFA232A1MA-GD-F

1

2

C2602

1UF

10% 10V X5R 402

DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQS0_C DQS1_C DQS2_C DQS3_C

DQS0_T DQS1_T DQS2_T DQS3_T

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9

P9

N9 N10

N11

M8 M9

M10

M11 F11

F10 F9

F8

E11 E10

E9

D9 T8

T9

T10 T11

R8 R9

R10

R11 C11

C10

C9 C8

B11

B10 B9

B8

L11 G11

P11

D11

L10 G10

P10

D10

1

C2603

1UF

10% 10V

2

X5R 402

=MEM_B_DQ<32> =MEM_B_DQ<33> =MEM_B_DQ<34> =MEM_B_DQ<35> =MEM_B_DQ<36> =MEM_B_DQ<37> =MEM_B_DQ<38> =MEM_B_DQ<39> =MEM_B_DQ<40> MEM_B_DQ<33> =MEM_B_DQ<42> =MEM_B_DQ<43> =MEM_B_DQ<44> =MEM_B_DQ<45> =MEM_B_DQ<46> =MEM_B_DQ<47> =MEM_B_DQ<48> =MEM_B_DQ<49> =MEM_B_DQ<50> =MEM_B_DQ<51> =MEM_B_DQ<52> =MEM_B_DQ<53> =MEM_B_DQ<54> =MEM_B_DQ<55> =MEM_B_DQ<56> =MEM_B_DQ<57> =MEM_B_DQ<58> =MEM_B_DQ<59> =MEM_B_DQ<60> =MEM_B_DQ<61> =MEM_B_DQ<62> =MEM_B_DQ<63>

=MEM_B_DQS_N<4> =MEM_B_DQS_N<5> =MEM_B_DQS_N<6> MEM_B_DQS_N<6>

=MEM_B_DQS_P<4> =MEM_B_DQS_P<5> =MEM_B_DQS_P<6> MEM_B_DQS_P<6>

1

C2604

1UF

10% 10V

2

X5R 402

1

C2605

1UF

2

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

7

61 68

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

61

BI

7

61 68

BI

61

BI

61

BI

61

BI

7

61 68

BI

1

C2606

10% 10V X5R 402

2

10UF

20% 25V X5R-CERM 0603

20 21 22 23 55 60

17 19 20 21 22 23 40 51 60 68

PP1V8_S3

PP1V2_S3

A3

A4 A5

A6

A10

U3

U4

U5 U6

U10

A8 A9

D4

D5 D6

G5

H5 H6

H12

J5

J6

K5 K6

K12

L5 P4

P5

P6 U8

U9

F2 G2

H3

L2 M2

A11

C12

E8 E12

G12

H8

H9

H11

J9

J10

K8 K11

L12

N8 N12

R12 U11

VDD1

VDD2

VDDCA

VDDQ

U2600

LPDDR3-16GB

FBGA

(2 OF 2)

OMIT_TABLE

CRITICAL

EDFA232A1MA-GD-F

VSS

VSSCA

VSSQ

B2

B5 C5

E4

E5 F5

J12

K2 L6

M5 N4

N5

R4 R5

T2

T3 T4

T5

H2

C3

D3

F4 G3

G4

P3 M4

J4

B6

B12 C6

D12 E6

F6

F12 G6

G9

H10 K10

L9

M6 M12

N6 P12

R6

T6 T12

D

C

B

PP1V2_S3

17 19 20 21 22 23 40 51 60 68

1

C2620

1UF

10% 10V

2

X5R 402

PP1V2_S3

17 19 20 21 22 23 40 51 60 68

1

C2610

1UF

A

PP1V8_S3

20 21 22 23 55 60

10% 10V

2

X5R 402

1

C2630

1UF

10% 10V

2

X5R 402

1

C2621

2

1

C2611

2

1

C2631

2

1UF

10% 10V X5R 402

1UF

10% 10V X5R 402

1UF

10% 10V X5R 402

1

2

1

2

C2622

1UF

10% 10V X5R 402

C2632

10UF

20% 25V X5R-CERM 0603

6 3

1

C2623

2

10UF

20% 25V X5R-CERM 0603

PLACEMENT_NOTE:

10uF caps are shared between DRAM. Distribute evenly.

SYNC_MASTER=MASTER

PAGE TITLE

LPDDR3 DRAM Channel B (32-63)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=MASTER

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

26 OF 120

SHEET

23 OF 73

124578

SIZE

A

D

8 7 6 5 4 3

12

D

C

Intel reccomends 55 Ohm for CMD/ADDR, 80 Ohm for CTRL/CKE, 38 Ohm for CLK

PP0V6_S0_DDRVTT

24 51 60 24 51 60

MEM_A_CAA<9>

20 61 68

IN

MEM_A_CAA<8>

20 61 68

IN

MEM_A_CAA<6>

7

20 61 68

IN

MEM_A_CAA<7>

20 61 68

IN

MEM_A_CAA<5>

20 61 68

IN

MEM_A_CLK_P<0>

7

20 68

IN

MEM_A_CLK_N<0>

7

20 68

IN

MEM_A_CKE<1>

7

20 68

IN

MEM_A_CKE<0>

7

20 68

IN

MEM_A_CAA<4>

20 61 68

IN

MEM_A_CAA<3>

20 61 68

IN

MEM_A_CAA<2>

20 61 68

IN

MEM_A_CAA<1>

20 61 68

IN

MEM_A_CAA<0>

20 61 68

IN

MEM_A_CAB<9>

21 61 68

IN

MEM_A_CAB<8>

21 61 68

IN

MEM_A_CAB<6>

7

21 61 68

IN

MEM_A_CAB<7>

21 61 68

IN

MEM_A_CAB<5>

21 61 68

IN

MEM_A_CLK_P<1>

7

21 68

IN

MEM_A_CLK_N<1>

7

21 68

IN

MEM_A_CKE<2>

7

21 68

IN

MEM_A_CKE<3>

7

21 68

IN

MEM_A_CAB<4>

21 61 68

IN

MEM_A_CAB<2>

21 61 68

IN

MEM_A_CAB<3>

21 61 68

IN

MEM_A_CAB<1>

21 61 68

IN

MEM_A_CAB<0>

21 61 68

IN

MEM_A_CS_L<0>

7

20 21 68

IN

MEM_A_CS_L<1>

7

20 21 68

IN

MEM_A_ODT<0>

7

20 21 61 68

IN

RP2701 RP2701 RP2701

RP2701 R2700 R2701 R2702 R2703 R2704 R2705 R2706

RP2703

RP2703 R2725

RP2707

RP2707 R2707 R2708 R2709 R2720 R2721

RP2704

RP2704 R2722 R2723 R2724

NC NC NCNC

RP2703

56

5%

1/32W

4X0201-HF

56 56 56

56 39 39 82 82 56

56

39

82 82 56

82

81

54

5%561/32W

63

5%

72

5%

81

5%

21

5%

21

5%

21

5%

21

5% MF

21

5%

21

5%561/20WMF201

54

5%561/32W

63

5%561/32W

72

5%

21

5%561/20WMF201

54

5%561/32W

63

5%561/32W

72

5%561/32W

81

5%561/32W

21

5%

21

5%391/20WMF201

21

5%

21

5%

21

5%

54

5%561/32W

63

5%561/32W

72

5%561/32W

81

5%561/32W

21

5%

21

5%821/20W

21

5%

PLACE_NEAR=RP2701.5:4mm

1/32W 1/32W

1/32W 1/20W

1/20W5%201

1/20W 1/20W

1/20W

1/32W

1/20W

4X0201-HF

4X0201-HF 4X0201-HF

201

201 201

201

4X0201-HF

4X0201-HF 4X0201-HF

4X0201-HF

201

4X0201-HF 4X0201-HF

4X0201-HF

4X0201-HF 201 201

201

PP0V6_S0_DDRVTT

MEM_B_CAA<9>

22 61 68

1

C2700

0.47UF

20% 4V

2

CERM-X5R-1

MF

MF MF

MF

MF MF

MF

1

C2701

0.47UF

2

1

C2703

0.47UF

2

1

C2705

0.47UF

2

1

C2707

0.47UF

2

1

C2709

0.47UF

2

1

C2720

22UF

2

201

20% 4V CERM-X5R-1 201

CRITICAL

20%

6.3V X5R-CERM-1 603

1

C2702

2

1

C2704

2

1

C2706

2

1

C2708

2

0.47UF

20% 4V CERM-X5R-1 201

0.47UF

20% 4V CERM-X5R-1 201

0.47UF

20% 4V CERM-X5R-1 201

0.47UF

20% 4V CERM-X5R-1 201

IN

MEM_B_CAA<8>

22 61 68

IN

MEM_B_CAA<7>

22 61 68

IN

MEM_B_CAA<6>

7

22 61 68

IN

MEM_B_CAA<5>

22 61 68

IN

MEM_B_CLK_P<0>

7

22 68

IN

MEM_B_CLK_N<0>

7

22 68

IN

MEM_B_CKE<1>

7

22 68

IN

MEM_B_CKE<0>

7

22 68

IN

MEM_B_CAA<4>

22 61 68

IN

MEM_B_CAA<2>

22 61 68

IN

MEM_B_CAA<3>

22 61 68

IN

MEM_B_CAA<1>

22 61 68

IN

MEM_B_CAA<0>

22 61 68

IN

MEM_B_CAB<9>

23 61 68

IN

MEM_B_CAB<8>

23 61 68

IN

MEM_B_CAB<7>

23 61 68

IN

MEM_B_CAB<6>

7

23 61 68

IN

MEM_B_CAB<5>

23 61 68

IN

MEM_B_CLK_N<1>

7

23 68

IN

MEM_B_CLK_P<1>

7

23 68

IN

MEM_B_CKE<2>

7

23 68

IN

MEM_B_CKE<3>

7

23 68

IN

MEM_B_CAB<4>

23 61 68

IN

MEM_B_CAB<2>

23 61 68

IN

MEM_B_CAB<3>

23 61 68

IN

MEM_B_CAB<1>

23 61 68

IN

MEM_B_CAB<0>

23 61 68

IN

MEM_B_CS_L<0>

7

22 23 68

IN

MEM_B_CS_L<1>

7

22 23 68

IN

MEM_B_ODT<0>

7

22 23 61 68

IN

RP2712 RP2712 RP2712

RP2712 R2710 R2711 R2712 R2713 R2714 R2715 R2716

RP2713

RP2713 R2735

RP2717

RP2717 R2717 R2718 R2719 R2730 R2731

RP2714

RP2714 R2732 R2733 R2734

SpareSpare

RP2713

4X0201-HF

1/32W

56 39

82 82 56

56

39

82 82 56

82 82

56

81

5%

54

5%561/32W

63

5%561/32W

72

5%561/32W

81

5%561/32W

21

5%

21

5%

21

5%

21

5%

21

5%

21

5%

21

5%561/20WMF201

54

5%561/32W

63

5%561/32W

72

5%561/32W

21

5%

54

5%561/32W

63

5%561/32W

72

5%561/32W

81

5%561/32W

21

5%

21

5%

21

5%

21

5%

21

5%

54

5%561/32W

63

5%561/32W

72

5%561/32W

81

5%561/32W

21

5%

21

5%

21

5%

4X0201-HF

4X0201-HF 4X0201-HF

1/20W

201

1/20W

201

1/20W 1/20W

201

1/20W

201

1/20W

201

4X0201-HF

201

1/20W

4X0201-HF

4X0201-HF 4X0201-HF

4X0201-HF

1/20W

201

1/20W 1/20W

201

1/20W

201

1/20W

4X0201-HF 4X0201-HF

4X0201-HF

1/20W

201

1/20W

201

1/20W

PLACE_NEAR=RP2714.8:4mm

1

C2710

0.47UF

20% 4V

2

CERM-X5R-1

MF

MF39201 MF

MF

MF39201 MF

MF

MF MF

MF82201

201

1

C2711

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2713

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2715

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2717

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2719

0.47UF

20% 4V

2

CERM-X5R-1 201

CRITICAL

1

C2740

22UF

20%

6.3V

2

X5R-CERM-1 603

1

2

1

2

1

2

1

2

C2712

C2714

C2716

C2718

0.47UF

20% 4V CERM-X5R-1 201

0.47UF

20% 4V CERM-X5R-1 201

0.47UF

20% 4V CERM-X5R-1 201

0.47UF

20% 4V CERM-X5R-1 201

D

C

SIZE

B

A

D

B

A

6 3

SYNC_MASTER=J43_MLB

PAGE TITLE

LPDDR3 DRAM Termination

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=09/21/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

27 OF 120

SHEET

24 OF 73

124578

8 7 6 5 4 3

CRITICAL

21

16V X5R-CERM

10%

21

16V X5R-CERM

10%

21

16V X5R-CERM

10%

21

16V X5R-CERM

10%

21

16V X5R-CERM

10%

21

16V X5R-CERM

10%

21

16V X5R-CERM

10%

21

16V X5R-CERM

10%

OMIT

1

R2815

NOSTUFF

NONE NONE NONE 0201

2

1

5%

MF

201

2

1

R2825

100

5% 1/20W MF 201

2

13

OUT

1

R2830

100K

5%

1/20W

MF

201

2

13 18

OUT

1

R2831

100K

5%

1/20W

MF

201

2

PCIE_TBT_R2D_P<0>

67

0201

PCIE_TBT_R2D_N<0>

67

0201

PCIE_TBT_R2D_P<1>

67

0201

PCIE_TBT_R2D_N<1>

67

0201

PCIE_TBT_R2D_P<2>

67

0201

PCIE_TBT_R2D_N<2>

67

0201

PCIE_TBT_R2D_P<3>

67

0201

PCIE_TBT_R2D_N<3>

67

0201

PCH_TBT_PCIE_RESET_L

15 18

IN

TBT_PWR_ON_POC_RST_L

26

IN

TP_TBT_MONDC0 TP_TBT_MONDC1

DEBUG: For monitoring current/voltage

TBT_MONOBSP TBT_MONOBSN

DEBUG: For monitoring clock

TP_TBT_THERM_DP

Use AA8 GND ball for THERM_DN

TBT_SPI_MOSI

69

TBT_SPI_MISO

69

TBT_SPI_CS_L

69

TBT_SPI_CLK

69

XDP_JTAG_ISP_TDI

15 16 18

IN

JTAG_TBT_TMS

18

IN

XDP_JTAG_ISP_TCK

15 16 18

IN

JTAG_TBT_TDO

18

OUT

TBT_TEST_EN TBT_TEST_PWR_GOOD

DP_TBTSNK0_ML_P<3>

25 65

DP_TBTSNK0_ML_N<3>

25 65

DP_TBTSNK0_ML_P<2>

25 65

DP_TBTSNK0_ML_N<2>

25 65

DP_TBTSNK0_ML_P<1>

25 65

DP_TBTSNK0_ML_N<1>

25 65

DP_TBTSNK0_ML_P<0>

25 65

DP_TBTSNK0_ML_N<0>

25 65

DP_TBTSNK0_AUXCH_P

25 65

DP_TBTSNK0_AUXCH_N

25 65

DP_TBTSNK0_HPD

DP_TBTSNK1_ML_P<3>

25 65

DP_TBTSNK1_ML_N<3>

25 65

DP_TBTSNK1_ML_P<2>

25 65

DP_TBTSNK1_ML_N<2>

25 65

DP_TBTSNK1_ML_P<1>

25 65

DP_TBTSNK1_ML_N<1>

25 65

DP_TBTSNK1_ML_P<0>

25 65

DP_TBTSNK1_ML_N<0>

25 65

DP_TBTSNK1_AUXCH_P

25 65

DP_TBTSNK1_AUXCH_N

25 65

DP_TBTSNK1_HPD

TBT_A_R2D_C_P<0>

28 69

OUT

TBT_A_R2D_C_N<0>

28 69

OUT

TBT_A_D2R_P<0>

28 69

IN

TBT_A_D2R_N<0>

28 69

IN

TBT_A_CONFIG1_BUF

28

IN

TBT_A_CONFIG2_RC

28

IN

TBT_A_R2D_C_P<1>

28 69

OUT

TBT_A_R2D_C_N<1>

28 69

OUT

TBT_A_D2R_P<1>

28 69

IN

TBT_A_D2R_N<1>

28 69

IN

TBT_A_LSTX

28

OUT

TBT_A_LSRX

28

IN

DP_TBTPA_ML_C_P<1>

28 69

OUT

DP_TBTPA_ML_C_N<1>

28 69

OUT

DP_TBTPA_ML_C_P<3>

28 69

OUT

DP_TBTPA_ML_C_N<3>

28 69

OUT

DP_TBTPA_AUXCH_C_P

28 69

BI

DP_TBTPA_AUXCH_C_N

28 69

BI

DP_TBTPA_HPD

28

IN

TBT_A_HV_EN

25 27 28

OUT

TBT_A_CIO_SEL

28

OUT

TBT_A_DP_PWRDN

25 28

OUT

AB9

PERP_0

AA10

PERN_0

AA12

PERP_1

AB13

PERN_1

AB15

PERP_2

AA16

PERN_2

AA18

PERP_3

AB19

PERN_3

P5

PERST_OD_N

R4

PWR_ON_POC_RSTN

AD23

MONDC0

AC24

MONDC1

W18

MONOBSP

W16

MONOBSN

AB7

THERMDA

AA2

EE_DI

Y3

EE_DO

T5

EE_CS_N

U8

EE_CLK

W2

TDI

AB1

TMS

AA6

TCK

U6

TDO

R6

TEST_EN

W8

TEST_PWR_GOOD

E14

DPSNK0_3_P

D13

DPSNK0_3_N

E16

DPSNK0_2_P

D15

DPSNK0_2_N

E18

DPSNK0_1_P

D17

DPSNK0_1_N

E20

DPSNK0_0_P

D19

DPSNK0_0_N

G4

DPSNK0_AUX_P

G2

DPSNK0_AUX_N

AB5

DPSNK0_HPD

E6

DPSNK1_3_P

D5

DPSNK1_3_N

E8

DPSNK1_2_P

D7

DPSNK1_2_N

E10

DPSNK1_1_P

D9

DPSNK1_1_N

E12

DPSNK1_0_P

D11

DPSNK1_0_N

H3

DPSNK1_AUX_P

H1

DPSNK1_AUX_N

U4

DPSNK1_HPD

G24

PA_CIO0_TX_P/DPSRC_0_P

E24

PA_CIO0_TX_N/DPSRC_0_N

G22

PA_CIO0_RX_P

E22

PA_CIO0_RX_N

P1

PA_CONFIG1/CIO_0_LSEO

K5

PA_CONFIG2/CIO_0_LSOE

L24

PA_CIO1_TX_P/DPSRC_2_P

J24

PA_CIO1_TX_N/DPSRC_2_N

L22

PA_CIO1_RX_P

J22

PA_CIO1_RX_N

N8

PA_LSTX/CIO_1_LSEO

J6

PA_LSRX/CIO_1_LSOE

A16

PA_DPSRC_1_P

B17

PA_DPSRC_1_N

A18

PA_DPSRC_3_P

B19

PA_DPSRC_3_N

L4

PA_AUX_P

L2

PA_AUX_N

M3

PA_DPSRC_HPD

R8

GPIO_0/PA_HV_EN/BYP0 GPIO_10/PA_CIO_SEL/BYP1 GPIO_12/PA_DP_PWRDN/BYP2

For unused port, pull CONFIG1, CONFIG2, LSRX, HPD and CIO_SEL low (10k). All other port signals can be NC.

PP3V3_TBTLC

1

R2893

3.3K

5% 1/20W MF 201

2

C2800

C2801

C2802

C2803

C2804

C2805

C2806

C2807

R2829

1/20W

0.1UF

10K

PCIE_TBT_R2D_C_P<0>

14 67

IN

PCIE_TBT_R2D_C_N<0>

14 67

IN

PCIE_TBT_R2D_C_P<1>

14 67

IN

PCIE_TBT_R2D_C_N<1>

14 67

IN

PCIE_TBT_R2D_C_P<2>

14 67

D

R2890

3.3K

1/20W

1

5% MF

201

2

1

R2891

3.3K

5% 1/20W MF 201

2

BYPASS=U2890::2mm

(TBT_SPI_CLK)

(TBT_SPI_CS_L)

TBTROM_WP_L

C

TBTROM_HOLD_L

C2890

1UF

6.3V CERM

1

10%

2

402

6

1

3

7

DI/IO0

CLK

CS*

WP*

HOLD*

GND

8

VCC

U2890

4MBIT

W25X40CLXIG

USON

THRM_PAD

4

CRITICAL OMIT_TABLE

DO/IO1

9

IN

14 67

IN

14 67

IN

14 67

IN

25

(TBT_SPI_MISO)(TBT_SPI_MOSI)

PCIE_TBT_R2D_C_N<2>

PCIE_TBT_R2D_C_P<3>

PCIE_TBT_R2D_C_N<3>

1

R2892

3.3K

5%

1/20W

MF

201

2

17 18 25 26 60 62

SNK0 AC Coupling

DP_TBTSNK0_ML_C_P<0>

5

65

IN

DP_TBTSNK0_ML_C_N<0>

5

65

IN

DP_TBTSNK0_ML_C_P<1>

5

65

IN

DP_TBTSNK0_ML_C_N<1>

5

65

IN

B

5

65

IN

5

65

IN

5

65

IN

5

65

IN

13 65

BI

13 65

BI

DP_TBTSNK0_ML_C_P<2>

DP_TBTSNK0_ML_C_N<2>

DP_TBTSNK0_ML_C_P<3>

DP_TBTSNK0_ML_C_N<3>

DP_TBTSNK0_AUXCH_C_P

DP_TBTSNK0_AUXCH_C_N

C2820

C2821

C2822

C2823

C2824

C2825

C2826

C2827

C2828

C2829

0.1UF

21

10% 16V X5R-CERM

21

10% 16V X5R-CERM

21

X5R-CERM

21

10% 16V X5R-CERM

21

X5R-CERM

21

10% 16V X5R-CERM

21

X5R-CERM

21

10% 16V X5R-CERM

21

X5R-CERM

21

10% 16V X5R-CERM

16V10%

DP_TBTSNK0_ML_P<0>

0201

DP_TBTSNK0_ML_N<0>

0201

DP_TBTSNK0_ML_P<1>

0201

DP_TBTSNK0_ML_N<1>

0201

DP_TBTSNK0_ML_P<2>

0201

DP_TBTSNK0_ML_N<2>

0201

DP_TBTSNK0_ML_P<3>

0201

DP_TBTSNK0_ML_N<3>

0201

DP_TBTSNK0_AUXCH_P

0201

DP_TBTSNK0_AUXCH_N

0201

25 65

SNK1 AC Coupling

DP_TBTSNK1_ML_C_P<0>

5

18 65

IN

DP_TBTSNK1_ML_C_N<0>

5

18 65

IN

DP_TBTSNK1_ML_C_P<1>

5

18 65

IN

DP_TBTSNK1_ML_C_N<1>

5

18 65

IN

DP_TBTSNK1_ML_C_P<2>

5

18 65

A

IN

5

18 65

IN

5

18 65

IN

5

18 65

IN

13 18 65

BI

13 18 65

BI

DP_TBTSNK1_ML_C_N<2>

DP_TBTSNK1_ML_C_P<3>

DP_TBTSNK1_ML_C_N<3>

DP_TBTSNK1_AUXCH_C_P

DP_TBTSNK1_AUXCH_C_N

C2830

C2831

C2832

C2833

C2834

C2835

C2836

C2837

C2838

C2839

0.1UF

21

10% 16V X5R-CERM

21

10% 16V X5R-CERM

21

10% 16V X5R-CERM

21

10% 16V X5R-CERM

21

10% 16V X5R-CERM

21

10% 16V X5R-CERM

21

10% 16V X5R-CERM

21

10% 16V X5R-CERM

21

10% 16V X5R-CERM

21

10% 16V X5R-CERM

DP_TBTSNK1_ML_P<0>

0201

DP_TBTSNK1_ML_N<0>

0201

DP_TBTSNK1_ML_P<1>

0201

DP_TBTSNK1_ML_N<1>

0201

DP_TBTSNK1_ML_P<2>

0201

DP_TBTSNK1_ML_N<2>

0201

DP_TBTSNK1_ML_P<3>

0201

DP_TBTSNK1_ML_N<3>

0201

DP_TBTSNK1_AUXCH_P

0201

DP_TBTSNK1_AUXCH_N

0201

25 65

OMIT_TABLE

U2800

FALCON-RIDGE-FR2C

FCBGA

SYM 1 OF 2

PCIE GEN2

GPIO_16/DEVICE_PCIE_RST_N

MISC

PCIE_CLKREQ_OD_N

REFCLK_100_IN_P REFCLK_100_IN_N

DISPLAY PORT

GPIO_2/TMU_CLK_IN/AC_PRESENT

GPIO_5/CIO_PLUG_EVENT_N/HV_OK_OD

GPIO_3/FORCE_PWR GPIO_4/WAKE_OD_N

GPIO_6_OD/CIO_SDA_OD GPIO_7_OD/CIO_SCL_OD

GPIO_8/EN_CIO_PWR_N_OD

GPIO_9/SX_CTRL_OD*

PB_CIO2_TX_P/DPSRC_0_P PB_CIO2_TX_N/DPSRC_0_N

PB_CONFIG1/CIO_2_LSEO PB_CONFIG2/CIO_2_LSOE

PB_CIO3_TX_P/DPSRC_2_P PB_CIO3_TX_N/DPSRC_2_N

PB_LSTX/CIO_3_LSEO PB_LSRX/CIO_3_LSOE

PORTS

GPIO_1/PB_HV_EN/BYP0

GPIO_11/PB_CIO_SEL/BYP1

GPIO_13/PB_DP_PWRDN/BYP2

PETP_0 PETN_0

PETP_1 PETN_1

PETP_2 PETN_2

PETP_3 PETN_3

RSENSE

RBIAS

RSVD_GND

GPIO_17 GPIO_18 GPIO_19

XTAL_25_IN

XTAL_25_OUT

TMU_CLK_OUT

DPSRC_3_P DPSRC_3_N

DPSRC_2_P DPSRC_2_N

DPSRC_1_P DPSRC_1_N

DPSRC_0_P DPSRC_0_N

DPSRC_AUX_P DPSRC_AUX_N

DPSRC_HPD_OD

GPIO_14 GPIO_15

PB_CIO2_RX_P PB_CIO2_RX_N

PB_CIO3_RX_P PB_CIO3_RX_N

PB_DPSRC_1_P PB_DPSRC_1_N

PB_DPSRC_3_P PB_DPSRC_3_N

PB_AUX_P PB_AUX_N

PB_DPSRC_HPD

AD5

PCIE_TBT_D2R_C_P<0>

67

AD7

PCIE_TBT_D2R_C_N<0>

67

AD9

PCIE_TBT_D2R_C_P<1>

67

AD11

PCIE_TBT_D2R_C_N<1>

67

AD13

PCIE_TBT_D2R_C_P<2>

67

AD15

PCIE_TBT_D2R_C_N<2>

67

AD17

PCIE_TBT_D2R_C_P<3>

67

AD19

PCIE_TBT_D2R_C_N<3>

67

U20

TBT_RSENSE

W20

TBT_RBIAS

AD1 L8

Used for straps in host mode

W6

TP_TBT_PCIE_RESET0_L

AB3

TBT_DFT_STRAP_1

AD3

TBT_ROM_SECURITY_XOR

V1

TBT_DFT_STRAP_3

V3

TBT_CLKREQ_L

AB21

PCIE_CLK100M_TBT_P

AD21

PCIE_CLK100M_TBT_N

AA24

SYSCLK_CLK25M_TBT_R

67

AB23

TP_TBT_XTAL25OUT

AA4

TBT_TMU_CLK_OUT

A14

TP_DP_TBTSRC_ML_CP<3>

B15

TP_DP_TBTSRC_ML_CN<3>

A12

TP_DP_TBTSRC_ML_CP<2>

B13

TP_DP_TBTSRC_ML_CN<2>

A10

NC_DP_TBTSRC_ML_CP<1>

B11

NC_DP_TBTSRC_ML_CN<1>

A8

TP_DP_TBTSRC_ML_CP<0>

B9

TP_DP_TBTSRC_ML_CN<0>

J4

NC_DP_TBTSRC_AUXCH_CP

J2

NC_DP_TBTSRC_AUXCH_CN

AC2

DP_TBTSRC_HPD

U2

TBT_GPIO2

L6

TBT_PWR_EN

H5

SMC_PME_S4_DARK_L

Y7

TBT_CIO_PLUG_EVENT_L

Y1

HDMITBTMUX_SEL_TBT

T7

TBT_GPIO7

V7

TBT_EN_CIO_PWR_L

M7

TBT_BATLOW_L

T1

TBTDP_AUXIO_EN

T3

TBT_DDC_XBAR_EN_L

R24

NC_TBT_B_R2D_CP<0>

N24

NC_TBT_B_R2D_CN<0>

R22

NC_TBT_B_D2RP<0>

N22

NC_TBT_B_D2RN<0>

D3

TBT_B_CONFIG1_BUF

M1

TBT_B_CONFIG2_RC

W24

NC_TBT_B_R2D_CP<1>

U24

NC_TBT_B_R2D_CN<1>

W22

NC_TBT_B_D2RP<1>

U22

NC_TBT_B_D2RN<1>

M5

NC_TBT_B_LSTX

P7

TBT_B_LSRX

A20

DP_TBTPB_ML_C_P<1>

B21

DP_TBTPB_ML_C_N<1>

A22

DP_TBTPB_ML_C_P<3>

B23

DP_TBTPB_ML_C_N<3>

K3

NC_DP_TBTPB_AUXCH_CP

K1

NC_DP_TBTPB_AUXCH_CN

N6

DP_TBTPB_HPD

F1

TBT_B_HV_EN

R2N2

TBT_B_CIO_SEL

F3P3

TBT_B_DP_PWRDN

C2840

C2841

C2842

C2843

C2844

C2845

C2846

C2847

1

R2855

1K

1% 1/20W MF 201

2

OUT

IN IN

62

25

IN OUT OUT

IN

OUT

IN OUT OUT

OUT OUT

IN

OUT OUT

IN

OUT

IN

OUT OUT

BI

IN

OUT OUT OUT

12

12 67

15

35 36

15 18

15 25

25 26

25 27

25 28

25

62

18

62

18

62 69

18

25

18

25

0.1UF

21

PCIE_TBT_D2R_P<0>

X5R-CERM

10% 16V

21

PCIE_TBT_D2R_N<0>

X5R-CERM

10% 16V

21

PCIE_TBT_D2R_P<1>

X5R-CERM

10% 16V

21

PCIE_TBT_D2R_N<1>

X5R-CERM

10% 16V

21

PCIE_TBT_D2R_P<2>

X5R-CERM

10% 16V

21

PCIE_TBT_D2R_N<2>

X5R-CERM

10% 16V

21

PCIE_TBT_D2R_P<3>

X5R-CERM

16V10%

21

PCIE_TBT_D2R_N<3>

X5R-CERM

16V10%

Security strap setting is XORed with bit in the flash, so the active-level depends on the code in the flash.

0201

If strap != bit then security is enabled?

Divides 3.3V to 1.8V

R2895

806

21

1%

1/20W

MF

201

NO STUFF

R2899

1/20W

10K

1

R2896

1K

5%

1/20W MF

MF

201

2

PP3V3_TBTLC

1

R2878

1

100K

R2879

100K

5%

1/20W

5% 1/20W

MF

201

2

NOTE: The following pins require testpoints: 0 - GPIO_13 1 - GPIO_1 2 - GPIO_2 3 - GPIO_3 4 - GPIO_5 5 - PCIE_RST_1_N 6 - PCIE_RST_2_N 7 - PCIE_RST_3_N

SYNC_MASTER=T29_RR

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

14 67

OUT

14 67

OUT

14 67

OUT

14 67

OUT

14 67

OUT

14 67

OUT

14 67

OUT

14 67

OUT

PP3V3_TBTLC

17 18 25 26 60 62

1

R2861

10K

5% 1/20W MF 201

2

SYSCLK_CLK25M_TBT

PP3V3_TBTLC

17 18 25 26 60 62

PP3V3_S4

25 26 27 29 34 36 37 56 60 62

TBT_EN_CIO_PWR_L

25 26

TBT_DDC_XBAR_EN_L

25

HDMITBTMUX_SEL_TBT

15 25

TBTDP_AUXIO_EN

25 28

DP_TBTSRC_HPD

25

17 18 25 26 60 62

PP3V3_S4

25 26 27 29 34 36 37 56 60 62

TBT_BATLOW_L

25 27

TBT_A_DP_PWRDN

25 28

TBT_B_DP_PWRDN

25

TBT_A_HV_EN

25 27 28

TBT_B_HV_EN

25

8 - GPIO_15 9 - GPIO_11 10 - GPIO_14 11 - GPIO_0 12 - GPIO_12 13 - GPIO_10 14 - PB_LSTX 15 - PB_LSRX

IN

R2881

100K

1/20W

R2884

100K

1/20W

17 67

5%

MF

201

5%

MF

201

1

2

1

2

Thunderbolt Host (1 of 2)

Apple Inc.

R

6 3

12

NO STUFF

1

R2867

10K

5% 1/20W MF 201

2

1

R2862

10K

5% 1/20W MF 201

2

R2880

100K

5%

1/20W

MF

201

R2832

100K

5%

1/20W

MF

201

NO STUFF

R2885

10K

5%

1/20W

MF

201

R2888

10K

5%

1/20W

MF

201

SYNC_DATE=01/19/2013

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

SHEET

124578

1

R2863

10K

5% 1/20W MF 201

2

1

R2882

100K

5% 1/20W MF 201

2

1

R2883

100K

5% 1/20W MF 201

2

NO STUFF

1

R2886

10K

5% 1/20W MF 201

2

1

R2887

10K

5% 1/20W MF 201

2

28 OF 120

25 OF 73

SIZE

D

C

B

A

D

8 7 6 5 4 3

D

C2900

1.0UF

20%

6.3V X5R

0201-1

PP1V05_TBT

26 62

MIN_LINE_WIDTH=0.50 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=1.05V

1

2

C2901

1.0UF

0201-1

1

20%

6.3V 2

X5R

C2902

1.0UF

0201-1

1

C2903

1.0UF

0201-1

20%

6.3V X5R

20%

6.3V 2

X5R

C

1900 mA EDP

C2923

10UF

CERM-X5R

0402-1

1

20%

6.3V 2

C2922

10UF

CERM-X5R

0402-1

1

20%

6.3V 2

B

A

EDP current / power consumption figures copied from R68 schematic (Rev 2, dated October 28, 2012, not available on IBL).

1

2

C2921

10UF

CERM-X5R

0402-1

12

U2940

Part

Type

R(on)

1

C2980

1.0UF

20%

6.3V

2

X5R 0201-1

SMC_DELAYED_PWRGD

TBT_POC_RESET_L

@ 1.05V

Max Current = 4A (85C)

1

C2932

1.0UF

20%

6.3V 2

X5R

0201-1

CRITICAL

PP1V05_TBTRDV

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=1.05V

1

C2904

1.0UF

20%

6.3V 2

X5R

0201-1

1

C2920

10UF

20%

6.3V 2

CERM-X5R

0402-1

20%

6.3V

1

C2905

1.0UF

20%

6.3V 2

X5R

0201-1

CRITICAL

L2920

0.68UH-20%-4.2A-0.032OHM

PIMB041B-SM

1

2

NSR1020MW2T1G

C2906

1.0UF

0201-1

CRITICAL

D2920

SOD-323

20%

6.3V X5R

21

1

700 mA EDP

2

C2910

1.0UF

20%

6.3V X5R

0201-1

P1V05TBT_SW

MIN_LINE_WIDTH=0.50 MM MIN_NECK_WIDTH=0.20 MM DIDT=TRUE SWITCH_NODE=TRUE

K

A

1

C2911

1.0UF

20%

0201-1

6.3V X5R

2

G10 G12 G14 G16 G18 H19

H9 J18 K15 K17 K19

K7

VCC1P0_RDV_DECAP

L16 M19 P19 T19 U18 V15 V17 W12 W14

J8

K9

1

L14 M15

SVR_VCC1P0

M17

2

P17 V19

A4

A6

SVR_IND

B3

B5

SVR_AMON

NC

A2 A24

AA14 AA20 AA22

AB11 AB17 AC10 AC12 AC14 AC16 AC18 AC20 AC22

AC4 AC6 AC8

B1

B7

VSS

C10 C12 C14 C16 C18

C2 C20 C22 C24

C4

C6

C8 D21 D23

E4 F11 F13 F15 F17 F19 F21 F23

F5

F7

F9

OMIT_TABLE

U2800

FALCON-RIDGE-FR2C

FCBGA

SYM 2 OF 2

VCC

VCC3P3_RDV_DECAP

GND

VCC1P0_CIO

VCC3P3

VCC3P3_LC

VSS

J10 J12 K11 L10 M11 N10 N14 P11 P15 R10 R14 T11 T15 U10 U14 V11

SVR input to RR - 1100 mA EDP

D1 E2

POC input to RR - 150 mA EDP

H11 N4

Isolated to reduce noise from SVR

V5 W4

Y5

H13 H15 H17 H7 L18 N18 R18 W10

PP3V3_TBTRDV

MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V

25 mA EDP

G20 G6 G8 H21 H23 J14AA8 J16 J20 K13 K21 K23 L12 L20 M13 M21 M23 M9 N12 N16 N20 P13 P21 P23 P9 R12 R16 R20 T13 T17 T21 T23 T9 U12 U16 V13 V21 V23 V9 Y11 Y13 Y15 Y17 Y19 Y21 Y23 Y9

C2930

1.0UF

0201-1

C2970

1.0UF

0201-1

20%

6.3V X5R

20%

6.3V X5R

1

2

PP3V3_TBTLC

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

100 mA EDP

1

2

C2931

1.0UF

0201-1

1

20%

6.3V 2

X5R

17 27 35 36

IN

59 60 62 63 72

PP3V3_S0

8

11 12 13 15 17 18 26 30 34

36 37 38 39 40 41 42 43 54 57

15

IN

6 3

PP1V05_TBTCIO

60 62

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

1200 mA EDP

1

C2981

1.0UF

20%

6.3V

2

X5R 0201-1

R2995

TPS22920

Load Switch

8 mOhm Typ

11.5 mOhm Max

1

100K

5%

1/20W

MF

201

2

1.05V TBT "CIO" Switch

Internal switch not functional on RR.

C2950

CERM-X5R

0402-1

C2960

1.0UF

0201-1

10UF

PP1V05_TBT

U2940

TPS22920

CSP

A1

B1

VOUT

C1

CRITICAL

59 60 62 63 72 8

11 12 13 15 17 18 26 30 34

36 37 38 39 40 41 42 43 54 57

1

20%

6.3V

20%

6.3V X5R

C2951

2

CERM-X5R

1

C2961

2

VIN

ON

GND

D1

PP3V3_S0

13

OUT

Pull-up (S0) on PCH page

1

10UF

20%

6.3V 2

0402-1

PP3V3_S4_TBT_F

MIN_LINE_WIDTH=0.38 MMMIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V

1

1.0UF

20%

6.3V 2

X5R

0201-1

A2

B2

C2

D2

1

2

TBT_PWR_REQ_L

C2952

10UF

6.3V

CERM-X5R

0402-1

TBT_EN_CIO_PWR

C2940

1.0UF

20%

6.3V X5R 0201-1

1

20%

2

26 62

5

G

S D

4

DMN5L06VK-7

SOT563

Q2945

C2953

10UF

20%

6.3V

CERM-X5R

0402-1

1

2

PP3V3_TBTLC

1

R2945

100K

5% 1/20W MF 201

2

Q2945

DMN5L06VK-7

6

D

SOT563

VER 3

S G

1

VER 5

3

PP3V3_S4

3.1 W (Dual-Port)

2.4 W (Single-Port)

EDP: 1.25 A

PLACE_NEAR=C2953.1:1mm

2

XW2960

SM

1

2

TBT_EN_CIO_PWR_L

17 18 25 26 60 62

25 26 27 29 34 36 37 56 60 62 17 18 25 26 60 62

D

25

IN

C

B

PP3V3_S4

25 26 27 29 34 36 37 56 60 62

Q2995

DMN32D2LFB4

DFN1006H4-3

1

SYM_VER_3

D

S G

C2995

330PF

X7R-CERM

3

1

10% 16V

2

0201

2

TBT "POC" Power-up Reset

1

R2990

100K

5% 1/20W MF 201

2

TBTPOCRST_MR_L

TBTPOCRST_SENSE

1

R2991

24.9K

1% 1/20W MF 201

2

Vth = 2.508V nominal

R2992

100K

1/20W

1

5%

MF

201

2

4

5

CT

1

2

TBT_PWR_ON_POC_RST_L

TBTPOCRST_CT

Delay = 4.04ms nominal

6

CRITICAL

VCC

U2990

TPS3895ADRY

1

3

USON

ENABLE SENSE_OUT

SENSE

GND

2

SYNC_MASTER=T29_RR

PAGE TITLE

Thunderbolt Host (2 of 2)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

C2990

0.1UF

10% 25V X5R 402

Push-pull output

OUT

1

C2991

0.001UF

10% 50V

2

X7R-CERM

0402

SYNC_DATE=12/17/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

29 OF 120

SHEET

26 OF 73

25

A

SIZE

D

124578

Page Notes

Power aliases required by this page:

- =PPVIN_SW_TBTBST (8-13V Boost Input)

- =PP15V_TBT_REG (15V Boost Output)

Signal aliases required by this page:

(NONE)

BOM options provided by this page: (NONE)

D

C

8 7 6 5 4 3

SI8409DB: Vds(max): -30V

25 28

IN

TBT_A_HV_EN

Q3005

DMN32D2LFB4

DFN1006H4-3

SYM_VER_2

PPBUS_G3H

39 40 47 48 54 60 62

8-13V Input Changes required for 2S.

3

D

1

G S

2

TBTBST_PWREN_L

R3080

470K

1/20W

R3081

150K

1/20W

1

5%

MF

201

2

1

5%

MF

201

2

4

1

C3080

0.1UF

10% 25V

2

X5R 402

TBTBST_PWREN_DIV_L

1

C3081

2.2UF

20% 10V

2

X5R-CERM

402

1

R3092

73.2K

1% 1/20W MF 201

2

<R2>

UVLO(falling) = 1.22 * (R1 + R2) / R2 UVLO(rising) = UVLO(falling) + (2uA * R1) UVLO = 4.55V (falling), 4.95 (rising)

1

C3082

2

2.2UF

20% 10V X5R-CERM 402

CRITICAL

Q3080

SI8409DB

BGA

SGD

1

C3092

2.2UF

X5R-CERM

Vgs(max): +/-12V Vgs(th): -1.4V Rds(on): 46mOhm @ 4.5V Vgs Id(max): 3.7A @ 70C

32

PPVIN_S4SW_TBTBST_FET

60 62

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

Voltage not specified here, add property on another page.

1

C3087

47PF

20% 10V

402

5% 25V

2

NP0-C0G-CERM 0201

TBTBST_VC_RC

1

C3093

2

3300PF

10% 10V X7R-CERM 0201

R3093

1/20W

1

10K

1%

MF

201

2

R3094

41.2K

1/20W

1%

MF

201

R3091

200K

1/20W

<R1>

1

2

C3090

1

1%

MF

201

2

TBTBST_EN_UVLO

TBTBST_INTVCC

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

TBTBST_VC

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

TBTBST_RT

TBTBST_SS

1

C3094

0.33UF

10%

6.3V

2

CERM-X5R 402

GND_TBTBST_SGND

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V

10UF

X5R-CERM

1

20% 25V

2

0603

TBT 15V Boost Regulator

CRITICAL

L3095

6.8UH-4.0A

27

VIN

CRITICAL

U3090

LT3957

SGND shorted to

GND inside package, no XW necessary.

SGND

372423

PIMB062D-SM

QFN

12

C3091

10UF

X5R-CERM

1

20% 25V

2

0603

25

EN/UVLO

28

INTVCC

30

VC

33

RT

32

SS

34

SYNC

4

21

9

8

382120

SW

SNS1

SNS2

NC

FBX

GND

1716151413

TBTBST_BOOST

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE DIDT=TRUE

TBTBST_SNS1

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

TBTBST_SNS2

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

6

3

1 2

10

NC

35 36

31

TBTBST_VSNS_RC

1

C3088

22PF

5% 50V

2

CERM 0402

TBTBST_FBX

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

NO STUFF

1

C3089

100PF

5% 50V

2

CERM 402

R3090

Vout = 1.6V * (1 + Ra / Rb)

49.9K

1/16W MF-LF

R3095

R3096

15.8K

1%

402

133K

1/16W MF-LF

402

<Ra>

1/16W MF-LF

402

<Rb>

R3089

2

1

1%

0

21

5%

1/20W

MF

0201

TBTBST_VSNS

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

1

2

1

2

1

C3095

10UF

20% 25V

2

X5R-CERM 0603

1

C3084

10UF

20% 25V

2

X5R-CERM 0603

C3096

10UF

X5R-CERM

C3085

10UF

X5R-CERM

12

CRITICAL

D3095

POWERDI-123

DFLS230L

PP15V_TBT

KA

Vout = 15.1V Max Current = 1.0A

28 60 62

Freq = 300KHz

XW3095

SM

2 1

1

C3097

2

1

20% 25V

2

0603

1

C309A

2

1

20% 25V

2

0603

10UF

20% 25V X5R-CERM 0603

C3098

10UF

20% 25V X5R-CERM 0603

C309B

10UF

X5R-CERM

10UF

X5R-CERM

20% 25V

0603

20% 25V

0603

PLACE_NEAR=C3095.1:2 mm

1

2

1

C3099

0.001UF

10% 50V

2

X7R-CERM 0402

1

2

D

C

Q3088

6

D

DMN5L06VK-7

SOT563

VER 3

Max Vgs: 10V

2

S G

1

B

PM_BATLOW_L

13 35

IN

TBTBST_SHDN_DIV

1

R3087

330K

5% 1/20W MF 201

2

BATLOW# Isolation

Q3000

DMN32D2LFB4

DFN1006H4-3

SYM_VER_3

D

1

S G

3

2

PP3V3_S4

3

4

Pull-up on RR page

TBT_BATLOW_L

MAKE_BASE=TRUE

1

R3088

330K

5% 1/20W MF 201

2

Q3088

D

DMN5L06VK-7

SOT563

VER 3

5

S G

25 26 29 34 36 37 56 60 62

OUT

25 27

SMC_DELAYED_PWRGD

IN

17 26 35 36

B

A

6 3

SYNC_MASTER=WILL_J43 SYNC_DATE=12/17/2012

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

TBT Power Support

Apple Inc.

R

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

30 OF 120

SHEET

27 OF 73

124578

SIZE

A

D

V3P3 must be S4 to support

wake from Thunderbolt devices.

8

11 13 15 16 17 18 29 40

52 55 56 57 58 60 62 72

CRITICAL

C3287

POLY-TANT

D

C

CASE-B2-SM

27 60 62

15.75V Max

For 12V systems:

PART NUMBER

118S0145

Nominal Min Max IHVS0/S3 1120mA 1090mA 1170mA (12W minimum)

B

A

8 7 6 5 4 3

3.3V/HV Power MUX

PP3V3_S5

100UF

20%

6.3V

PP15V_TBT

1

2

25 69

OUT OUT

IN IN

C3215

4.7UF

X5R-CERM

18 56 57

25 27

55 57

X5R-CERM-1

10% 25V

0603

IN

QTY

1

C3280

22UF

20%

6.3V 2

603

1

2

S4_PWR_EN

TBT_A_HV_EN

PM_SLP_S3_BUF_L

2

TBT_A_D2R_P<0>

TBT_A_D2R_N<0>

DP_TBTPA_ML_C_P<3>

DP_TBTPA_ML_C_N<3>

1

C3281

0.1UF

10% 16V

2

X5R-CERM 0201

C3210

0.1UF

10% 25V X5R 402

DESCRIPTION

RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF

Nominal Min Max IV3P3 1100mA 1030mA 1200mA

IHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum)

IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W)

19

20

6 7

16

5

17

V3P3

VHV

CD3211A1RGP

ENHVU

EN

HV_EN

S0

CRITICAL

U3210

QFN

ISET_V3P3

GND

321

13

TBTHV:P15V

R3213

V3P3OUT

FAULTZ

ISET_S0

ISET_S3

15

22.6K

1%

1/20W

MF

201

OUT

THRM

PAD

1

2

21

18

12

14

C3285

X5R-CERM

4

8

1011

9

TBTAPWRSW_ISET_S3_R TBTAPWRSW_ISET_S0_R

TBTHV:P15V

1

R3214

22.6K

1% 1/20W MF 201

2

1

0.1UF

10% 16V

2

0201

TBTAPWRSW_ISET_V3P3

TBTAPWRSW_ISET_S0

TBTAPWRSW_ISET_S3

12V: See

below

REFERENCE DES

R3210,R3213

R3211,R3214

GND_VOID=TRUE

(Both C’s)

TBT_A_HPD

28

TBT_A_CONFIG1_RC

28

TBT_A_CONFIG2_RC

21 20%

CERM-X5R-1 21 20%

CERM-X5R-1

21 20%

X5R 21 20%

X5R

201

4V

201

6.3V 0201

1

R3252

1M

5%

1/20W

MF

201

2

C3274

C3275

C3278

C3279

25

0.47UF

0.22UF

OUT

1

C3286

10UF

20%

6.3V

2

CERM-X5R 0402

Single-fault protection

requires two R’s per HV ISET_Sx with CD3210.

Single R on ISET_V3P3 OK.

TBTHV:P15V

R3210

22.6K

1

2

1%

1/20W

MF

201

ILIM = 40000 / RISET

CRITICAL

TBT_A_D2R_C_P<0>

69

TBT_A_D2R_C_N<0>

69

NO_XNET_CONNECTION=TRUE

DP_TBTPA_ML_P<3>

69

DP_TBTPA_ML_N<3>

69

1

R3251

1M

5% 1/20W MF 201

2

PP3V3_S4_TBTAPWR

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V

PP3V3RHV_S4_TBTAPWR

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=15V

C3211

0.1UF

10% 25V X5R 402

TBTHV:P15V

1

R3211

22.6K

1% 1/20W MF 201

2

BOM OPTION

TBTHV:P12V

GND_VOID=TRUE

1

R3294

1K

5%

1/20W

MF

201

2

1

C3294

330PF

10% 16V

2

X7R-CERM

0201

1

R3212

36.5K

2

<RV3P3>

GND_VOID=TRUE

1

R3295

1K

5% 1/20W MF 201

2

NO_XNET_CONNECTION=TRUE

R3279

470K

1/20W

201

1

C3295

330PF

10% 16V

2

X7R-CERM 0201

28 60

1% 1/20W MF 201

1

5%

MF

2

TBT_A_D2R1_AUXDDC_P

28 69

TBT_A_D2R1_AUXDDC_N

28 69

1

R3241

100K

5% 1/20W MF 201

2

C3200

0.01UF

X7R-CERM

1

R3278

470K

5% 1/20W MF 201

2

GND_VOID=TRUE

(Both C’s)

TBT_A_D2R_N<1>

25 69

OUT

TBT_A_D2R_P<1>

25 69

OUT

DP_TBTPA_AUXCH_C_N

25 69

BI

DP_TBTPA_AUXCH_C_P

25 69

BI

DP_TBTPA_ML_C_P<1>

25 69

IN

DP_TBTPA_ML_C_N<1>

25 69

IN

CRITICAL

L3200

FERR-120-OHM-3A

1

10% 50V

2

0402

1

2

C3201

0.01UF

10% 50V X7R-CERM 0402

21

PP3V3RHV_S4_TBTAPWR_F

0603

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=15V

TBTACONN_20_RC

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=18V

TBT Dir

TBT: RX_0

TBT: Unused

DP Dir

R3201

12

5%

1/20W

MF

201

21

C3277

0.47UF

C3276

0.47UF

C3230

0.1UF

C3231

0.1UF

C3232

0.22UF

C3233

0.22UF

Thunderbolt Connector A

2

HOT_PLUG_DETECT

4

CONFIG1

6

CONFIG2

13 7

GND

10

ML_LANE3P

12

ML_LANE3N

14 8

GND

16

AUX_CHP

18

AUX_CHN

20

DP_PWR

21 20%

CERM-X5R-1 21 20%

CERM-X5R-1 21

X5R-CERM 21

X5R-CERM

21 20%

X5R 21 20%

X5R

J3200

MDP-J11

F-RT-TH

CRITICAL

514-0818

ML_LANE0P ML_LANE0N

ML_LANE1P ML_LANE1N

ML_LANE2P ML_LANE2N

4V

16V10%

0201

16V10%

0201

6.3V 0201

GND

RETURN

201

13 18

25

69

25

1 3 5

9 11

15 17 19

SHIELD PINS

1

2

C3202

0.01UF

10% 16V X5R-CERM 0201

TBT: RX_1

DP Source must pull

down HPD input with greater than or equal

to 100K (DPv1.1a).

Sink HPD range:

High: 2.0 - 5.0V

Low: 0 - 0.8V

28272625242322

21

6 3

28 60

TBT_A_D2R_C_N<1>

69

TBT_A_D2R_C_P<1>

69

DP_TBTPA_AUXCH_N

69

DP_TBTPA_AUXCH_P

69

DP_TBTSNK0_DDC_DATA

BI

DP_TBTSNK0_DDC_CLK

IN

TBT_A_CONFIG1_BUF

OUT

DP_TBTPA_ML_P<1>

DP_TBTPA_ML_N<1>

TBT_A_LSTX

IN

TBT_A_LSRX

OUT

DP_TBTPA_HPD

OUT

TBTACONN_1_C

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=18.9V

DP Dir

TBTACONN_7_C

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=18.9V

PP3V3_S4_TBTAPWR

TBT Dir

TBT: TX_0

TBT: LSX_R2P/P2R (P/N)

TBT: TX_1

(0-18.9V)

C3220

0.1UF

10% 16V

X5R-CERM

0201

TBT_A_R2D_P<0>

69

TBT_A_R2D_N<0>

69

TBT_A_R2D_P<1>

69

TBT_A_R2D_N<1>

69

1

2

7 15

8

1

2

4

5

16 18

11

10

14

13

12 17

GND_VOID=TRUE

TBTB+

AUXAUX+

DDC_DAT DDC_CLK

CA_DETOUT

DP+ DP-

LSTX

(IPU)

LSRX

(IPD)

HPDOUT

C3205

0.01UF

10% 25V

X5R-CERM

0201

C3206

0.01UF

10% 25V

X5R-CERM

0201

3

VDD

CRITICAL

U3220

CBTL05024

HVQFN24-COMBO

GND

9

1

2

1

2

(IPU)

(IPD)

21

SIGNAL_MODEL=TBT_MUX

HPD

R3270

470K

5% 1/20W MF 201

R3272

470K

5% 1/20W MF 201

C3270

C3271

C3272

C3273

24

6

23

22

19

20

0.22UF

TBTDP_AUXIO_EN

TBT_A_CIO_SEL

TBT_A_DP_PWRDN

TBT_A_D2R1_AUXDDC_N TBT_A_D2R1_AUXDDC_P

TBT: RX_1

TBT_A_CONFIG1_RC

DP_A_LSX_ML_P<1>

DP_A_LSX_ML_N<1>

TBT: LSX_A_R2P/P2R (P/N)

TBT_A_HPD

GND_VOID=TRUE

(Both C’s)

21

6.3V

20%

0201

X5R 21

6.3V

20%

0201

X5R

GND_VOID=TRUE

1

R3271

470K

5% 1/20W MF 201

2

GND_VOID=TRUE

(Both C’s)

21

6.3V

20%

0201

X5R 21

6.3V

20%

0201

X5R

GND_VOID=TRUE

1

R3273

470K

5% 1/20W MF 201

2

TB_ENA

AUXIO_EN

DP_PD

AUXIOAUXIO+

CA_DET

DPMLO+ DPMLO-

THMPAD

25

GND_VOID=TRUE

1

2

GND_VOID=TRUE

1

2

470k R’s for ESD protection

on AC-coupled signals.

SYNC_MASTER=T29_RR

PAGE TITLE

Thunderbolt Connector A

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

TBT_A_R2D_C_P<0>

TBT_A_R2D_C_N<0>

DP_A_LSX_ML_P<1>

DP_A_LSX_ML_N<1>

TBT_A_R2D_C_P<1> TBT_A_R2D_C_N<1>

28 69

28

28 69

28

25

IN

25

IN

25

IN

12

IN IN

28 69

IN IN

SYNC_DATE=10/26/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

32 OF 120

SHEET

28 OF 73

124578

25 69

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

3.3V WLAN Switch

Part

D

Type

R(on) @ 2.5V

TPS22924C

Load Switch

18.5 mOhm Typ

25.8 mOhm Max

D

Sense resistor on

PP3V3_WLAN

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

1

C3521

0.1UF

10%

6.3V

2

514S0335

CRITICAL

J3501

SSD-K99

F-RT-SM1

1

2 3

4

5 6

7 8

9

10

C

11

12

13 14

15

16 17

18

19

20 21

PCIE_AP_R2D_N

62 67

PCIE_AP_R2D_P

62 67

B

CERM-X5R 0201

BYPASS=J3501:5mm

1

2

56 57 58 18 28 29

PP3V3_S5

8

11 13

15 16 17 40 52 55 60 62 72

1

R3561

100K

5% 1/20W MF 201

2

AP_PCIE_WAKE_L

C3531

0.1UF

C3530

0.1UF

PP3V3_S4

C3532

0.1UF

10%

6.3V CERM-X5R 0201

BYPASS=J3501:1.5mm

21

10% X5R-CERM

21 10%

X5R-CERM

25 26 27 29 34 36 37 56 60 62

PCIe Wake Muxing

1

C3560

0.1UF

10%

6.3V 2

CERM-X5R

0201

4

A

AIRPORT

WIFI_EVENT_L

PCIE_AP_R2D_C_N

16V 0201

PCIE_AP_R2D_C_P

16V 0201

PCIE_CLK100M_AP_N PCIE_CLK100M_AP_P

PCIE_AP_D2R_P PCIE_AP_D2R_N

5

VCC

CRITICAL

U3560

NC7SB3157P6XG

SC70

VER-3

GND

2

SEL OUTPUT

L PCIE_WAKE_L (B0) H AP_S0IX_WAKE_L (B1)

6

AP_S0IX_WAKE_SEL

S

3

PCIE_WAKE_L

B0

1

AP_S0IX_WAKE_L

B1

35 36 62

OUT

14 67

IN

14 67

IN

12 62 67

IN

12 62 67

IN

14 62 67

OUT

14 62 67

OUT

62

AP_RESET_CONN_L

IN

OUT OUT

15

13 31 62

15

APCLKRQ:ISOL

R3553

100K

1/20W

R3558

0

21

5%

1/20W

MF

0201

5%

MF

201

NOSTUFF

R3560

0

21

5%

1/20W

MF

0201

USB_BT_CONN_P

A

62 66

USB_BT_CONN_N

62 66

SIGNAL_MODEL=BT_MUX

25 26 27 29 34 36 37 56 60 62

PP3V3_S4

5

VDD

U3510

USB3740

DFN

CRITICAL

10

DP

9

DM

GND

8

VOLTAGE=3.3V

1

R3554

232K

1% 1/20W MF 201

2

P3V3WLAN_VMON

AP_RESET_CONN_R_L

AP_CLKREQ_Q_L

62

1

R3555

100K

1% 1/20W MF 201

2

BLUETOOTH

6

DP_2

7

DM_2

2

DP_1

NC

1

DM_1

3

OE*

4

S

Supervisor & CLKREQ# Isolation

1

C3510

0.1UF

10%

6.3V

2

CERM-X5R 0201

USB_BT_P

USB_BT_N

BT_WAKE

PM_SLP_S4_L

SEL OUTPUT

L BT_WAKE (1) H USB_BT (2)

sensor page

35 36 37 39 62

Delay = 130 ms +/- 20%

1

VDD

U3540

SLG4AP041V

TDFN

SENSE VREF

RESET*

IN

THRM

PAD

14 66

13 18 34 35 57

CRITICAL

+

-

DLY

GND

9

5

NO_XNET_CONNECTION=TRUE

2

4

7

BI

IN

39

3

MR*

6

EN

8

OUT

(OD)

Q3510

DMN32D2LFB4

DFN1006H4-3

SYM_VER_2

PP3V3_WLAN_R

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

Max Current = 2A (85C)

PP3V3_S5

1

C3540

0.1UF

10%

6.3V

2

CERM-X5R 0201

SMC_WIFI_PWR_EN AP_CLKREQ_R_L

APCLKRQ:BIDIR

R3557

0

2 1

5%

1/20W

MF

0201

NOSTUFF

R3559

0

2 1

5%

1/20W

MF

0201

SMC_PME_S4_WAKE_L

3

D

1

G S

2

1

R3512

15K

1% 1/20W MF 201

2

8

11 13 15 16 17 18 28 29 40 52

55 56 57 58 60 62 72

IN

APCLKRQ:ISOL

1

R3556

0

5% 1/20W MF 0201

2

AP_CLKREQ_L

6 3

A1

B1

29 35 37

U3550

TPS22924

CSP

VOUTONVIN

CRITICAL

GND

C1

OUT

PP3V3_S5

A2

B2

C2

SMC_WIFI_PWR_EN

1

C3550

1.0UF

20%

6.3V

2

X5R 0201-1

BI

34 35 37

AP_RESET_L

12

SYNC_MASTER=J43_MLB

PAGE TITLE

IN

Wireless Connector

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

8

11 13 15 16 17 18 28 29 40 52

55 56 57 58 60 62 72

29 35 37

IN

15

SYNC_DATE=10/02/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

35 OF 120

SHEET

29 OF 73

124578

SIZE

C

B

A

D

8 7 6 5 4 3

12

D

PLACE_NEAR=J3700.1:3mm

CRITICAL

L3700

PP3V3_S0SW_SSD

30 39 60 62

1

C3701

0.1UF

10% 10V

2

X5R-CERM

PLACE_NEAR=L3700.1:1mm

0201

C

SSD_BOOT

13

FERR-26-OHM-6A

IN

12 65

IN

12 65

IN

12 65

IN

12 65

IN

12 65

IN

12 65

IN

12 65

IN

12 65

IN

PCIE_SSD_R2D_C_N<3>

PCIE_SSD_R2D_C_P<3>

PCIE_SSD_R2D_C_N<2>

PCIE_SSD_R2D_C_P<2>

PCIE_SSD_R2D_C_N<1>

PCIE_SSD_R2D_C_P<1>

PCIE_SSD_R2D_C_N<0>

PCIE_SSD_R2D_C_P<0>

C3710

C3711

C3712

C3713

C3714

C3715

C3716

C3717

0.1UF

Per Intel PDG, use PCIe style decoupling, when muxing PCIe & SATA

21 10%

21

10%

21

10%

21 10%

21

10%

21

10%

0603

GND_VOID=TRUE

16V

GND_VOID=TRUE

16V

GND_VOID=TRUE

16V

GND_VOID=TRUE

16V

GND_VOID=TRUE

16V

GND_VOID=TRUE

16V

GND_VOID=TRUE

16V

GND_VOID=TRUE

16V

21

R3701

X5R-CERM

1

C3702

0.1UF

10% 10V

2

X5R-CERM 0201

PLACE_NEAR=L3700.1:1mm

15 62

IN

0

MF

02015%1/20W

0201

PP3V3_S0SW_SSD_FLT

62

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.15mm VOLTAGE=3.3V

SSD_SR_EN_L SSD_RESET_CONN_L

62

21

SSD_BOOT_R

NOSTUFF

PCIE_SSD_R2D_N<3>

62 65

PCIE_SSD_R2D_P<3>

62 65

PCIE_SSD_R2D_N<2>

62 65

PCIE_SSD_R2D_P<2>

62 65

PCIE_SSD_R2D_N<1>

62 65

PCIE_SSD_R2D_P<1>

62 65

PCIE_SSD_R2D_N<0>

62 65

PCIE_SSD_R2D_P<0>

62 65

SSD_CLKREQ_CONN_L

62

514S0449 CRITICAL

J3700

SSD-GS3

GND_VOID

F-RT-SM 1

2

3 4

5 6

7

8 9

10

11

TRUE TRUE

12

TRUE

13

14

TRUE

15

TRUE

16

17

18

TRUE

19

TRUE

20

21

TRUE

22

TRUE

23

24 25

26

27 28

59 60 62 63 72

PP3V3_S0

8

11 12 13 15 17 18 26 30 34

36 37 38 39 40 41 42 43 54 57

GND_VOID

53 52

SMC_OOB1_R2D_CONN_L

62

51

SMC_OOB1_D2R_CONN_L

62

50

SSD_PCIE_SEL_L

49

TP_SSD_DEVSLP

48

SMC_PWRFAIL_WARN_L

47

SSD_PWR_EN

SMC_PWRFAIL_WARN_L Signal no connect on X31

46 45

PCIE_SSD_D2R_N<3>

44

TRUE

PCIE_SSD_D2R_P<3>

43

42

TRUE

PCIE_SSD_D2R_N<2>

41

TRUE

PCIE_SSD_D2R_P<2>

40

39

38

TRUE

PCIE_SSD_D2R_N<1>

37

TRUE

PCIE_SSD_D2R_P<1>

36 35

TRUE

PCIE_SSD_D2R_N<0>

34

TRUE

PCIE_SSD_D2R_P<0>

33

32

31

PCIE_CLK100M_SSD_N

30

PCIE_CLK100M_SSD_P

29

NOSTUFF

R3710

100K

1/20W

NOSTUFF

OUT

OUT OUT

IN IN

R3700

1

100K

1%

1/20W

MF

201

2

30 62

35 62

15 30 56 57 62

12 62 65

11 12 13 15 17 18

40 41 42 43 54 57 59

PP3V3_S0

8 26 30 34 36 37 38 39 60 62 63 72

R3703

1

5% MF

201

2

OOB Isolation

PP3V3_S0SW_SSD

30 39 60 62

CRITICAL

BYPASS=U3711:5 mm

100K

1/20W

C3719

0.1UF

X5R-CERM

1

1%

MF

201

2

74LVC1G08

SOT891

4

1

10% 10V

2

0201

2

1

NC

5 3

NC

SSD_PCIE_SEL_L

30 62

6

U3710

U3711

08

6

1

2

1

NC

53

NC

CRITICAL

74LVC1G08

SOT891

4

BYPASS=U3710:5 mm

C3718

0.1UF

10% 10V X5R-CERM 0201

SMC_OOB1_R2D_L

SMC_OOB1_D2R_L

R3702

0

5%

1/20W

MF

0201

35

IN

35

OUT

21

D

C

54

55

B

Supervisor & CLKREQ# Isolation

Delay = ~55ms

R3740

100K

1/20W

5%

MF

201

1

2

1

2

PP3V3_S0SW_SSD

R3741

232K

1% 1/20W MF 201

P3V3SSD_VMON

R3742

100K

1% 1/20W MF 201

30 39 60 62

CRITICAL

2

SENSE

0.7V

4

RESET*

7

IN

1

VDD

U3740

SLG4AP016V

TDFN

+

-

DLY

THRM

GND

PAD

9

PP3V42_G3H

1

C3740

0.1UF

10%

6.3V

2

CERM-X5R 0201

3

MR*

EN

OUT

(OD)

5

6 8

SSD_RESET_L

SSD_PWR_EN SSD_CLKREQ_L

17 33 34 35 36 38 44 46 47 48 57 59 60 62 63

15

IN

15 30 56 57 62

IN

12

OUT

Gumstick3 Connector

56

57

58

A

6 3

59 60

61

62

63

PCIe polarity inversion and lane reversal are only permitted on the device side, provided the device PHY supports it.

SYNC_MASTER=J43_MLB

PAGE TITLE

SSD Connector

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=02/20/2013

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

37 OF 120

SHEET

30 OF 73

SIZE

B

A

D

124578

8 7 6 5 4 3

PP1V8_CAM

L3902

17 31

C3970

0.1UF

10%

6.3V CERM-X5R 0201

1

2

13 29 62

C3937

0.1UF

10%

6.3V CERM-X5R 0201

1.0UH-1.6A-55MOHM

1008

PLACE_NEAR=U3900.K13:4MM

31 32

1

C3971

1000PF

10% 16V

2

X7R-CERM 0201

BYPASS=U3900.F6:2.54MM

BYPASS=U3900.F9:2.54MM

PP1V8_CAM

31 32

15 39

PCIE_WAKE_L

OUT

PP1V8_CAM

31 32

32 70

BI

32 70

BI

32 70

BI

32 70

BI

32 70

BI

32 70

BI

32 70

BI

32 70

BI

32 70

BI

32 70

BI

32 70

BI

32 70

BI

32 70

BI

32 70

BI

32 70

BI

32 70

BI

32 70

BI

32 70

BI

32 70

BI

32 70

BI

32 70

OUT

32 70

OUT

32 70

OUT

32

OUT

21

P1V35_CAM_SRVLXD_PHASE

PP1V8_CAM

1

2

BYPASS=U3900.F9:2.54MM

1

R3913

1K

5%

1/20W

MF

201

2

32 62

OUT

32 62

BI

C3972

0.1UF

10%

6.3V CERM-X5R 0201

R3914

NOSTUFF

R3991

1

R3990

100K

5% 1/20W MF 201

2

NOSTUFF

1

C3990

0.1UF

10%

6.3V

2

CERM-X5R 0201

1/20W

0201

31

1

R3920

100K

5% 1/20W MF 201

2

1

C3973

1000PF

10% 16V

2

X7R-CERM 0201

BYPASS=U3900.L9:2.54MM

32 70

IN

32 70

IN

32 70

IN

32 70

IN

32 67

IN

32 67

IN

32 67

IN

32 67

IN

32 67

OUT

32 67

OUT

1

1K

5%

1/20W

MF

201

2

0

21

5%

MF

32

18

PU on PCH page

CAM_XTAL_FREQ

PU = 25MHz

31

1

R3921

100K

5% 1/20W MF 201

2

I2C_CAM_SMBDBG_CLK I2C_CAM_SMBDBG_DAT

1

C3974

0.1UF

10%

6.3V

2

CERM-X5R 0201

MIPI_CLK_P MIPI_CLK_N

MIPI_DATA_P MIPI_DATA_N

PCIE_CAMERA_R2D_P PCIE_CAMERA_R2D_N

PCIE_CLK100M_CAMERA_C_P PCIE_CLK100M_CAMERA_C_N

PCIE_CAMERA_D2R_C_P PCIE_CAMERA_D2R_C_N

CLK25M_CAM_CLKP

32 67

OUT

CLK25M_CAM_CLKN

32 67

IN

I2C_CAM_SMBDBG_CLK

31

I2C_CAM_SCK I2C_CAM_SMBDBG_DAT

31

I2C_CAM_SDA

TP_CAM_JTAG_TCK TP_CAM_JTAG_TDI TP_CAM_JTAG_TDO TP_CAM_JTAG_TMS TP_CAM_JTAG_TRST_L CAM_JTAG_SRST_L

31

CAMERA_CLKREQ_L

12

OUT

CAM_PCIE_RESET_L

15 18

IN

CAM_PCIE_WAKE_L

CAM_PWR_SEL CAM_DEBUG_RESET_L

1

R3901

100K

PD = 1.35V

5% 1/20W MF 201

2

CAM_SENSOR_WAKE_L

IN

CAMERA_PWR_EN

IN

1

R3904

100K

5% 1/20W MF 201

2

31

1

C3975

0.1UF

10%

6.3V

2

CERM-X5R 0201

CAM_XTAL:YES

1

R3906

100K

5% 1/20W MF 201

2

CAM_XTAL_SEL

CAM_XTAL:NO

1

R3907

100K

5% 1/20W MF 201

2

PP1V35_CAM

31 32 70

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.35V

PP1V35_DDR_CLK

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

U3900

BCM15700

FBGA

MIPI_AGND

PCIE_GND

PMU_AVSS

SR_PVSSC

SR_PVSSD

VSSC

XTAL_AVSS

SYM 3 OF 3

CRITICAL

OMIT_TABLE

L3901:1 L3902:1

1

R3975

51K

5% 1/20W MF 201

2

DDR_VDDIO

DDR_VDDIO_CK

DDR_VREF

PCIE_VDD1P2

PCIE_PVDD1P2

DDR_AVDD1P8

MIPI_AVDD1P8

PLL_VDD1P8

OTP_VDD3P3

SR_VDD_3P3C

SR_VDD_3P3D

SR_VLXC_O

SR_VLXD_O

VDD_1P35A

VDD_3P3A

VDD1P2_O

VDD1P8_O

VDDC

VDDO18

VSENSE_C VSENSE_D

XTAL_AVDD1P2

1

2

R3976

51K

5% 1/20W MF 201

A4

D4 G4

K4 N4

G5

N5

C8

D9

J1

L7

D6

D7

M14

M15 N15

H14

H15

J13 J14

J15

M13

N14

K13

K14

F14

J11

F15

G15

F6

F7 F8

F9

L6 L5

L8

L9

B15

R11

M11

K12

B13

D

GND_CAM_PVSSC

31

GND_CAM_PVSSD

31

C

B

CAM_UARTCTS

31

CAM_UARTRXD

A

31

N7

N8

N6

C10

C7

G14 M12

N13 P14

P15

R15

K15 L12

L13

L14 L15

A1 A6

B6

D1 D5

E5 G1

G6

G7 G8

G9

H5 H6

H7

H8 H9

J5 J6

J7

J8 J9

K1

K5 K6

K7

K8 K9

A14

M9

N1

P5 R1

R5 E9

B12

VOLTAGE=1.35V

PP0V675_CAM_VREF

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

VOLTAGE=0.675V

PP1V2_CAM_PCIE_VDD_FLT

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.2V

PP1V2_CAM_PCIE_PVDD_FLT

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.2V

PP1V8_CAM

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

(=PP3V3_S3RS0_CAMERA)

VOLTAGE=1.8V

1

2

C3928

4.7UF

20%

6.3V X5R 402

(=PP3V3_S3RS0_CAMERA)

P1V2_CAM_SRVLXC_PHASE

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

P1V35_CAM_SRVLXD_PHASE

PP1V35_CAM

PP1V2_CAM_XTALPCIEVDD

PP1V8_CAM

PP1V2_CAM

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.2V

PP1V2_CAM

PP1V35_CAM

MAKE_BASE=TRUE

1

C3960

0.1UF

10%

6.3V

2

CERM-X5R 0201

31

31 32 70

PP1V2_CAM_XTALPCIEVDD

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.2V

PP1V2_CAM_XTALPCIEVDD

GND_CAM_PVSSC

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

VOLTAGE=0V

DIDT=TRUE

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

DIDT=TRUE

31 32 70

31

R3912

240

1%

1/20W

MF

201

1

C3900

0.1UF

10%

6.3V

2

CERM-X5R 0201

32 70

1

C3927

0.1UF

10%

6.3V

2

CERM-X5R 0201

BYPASS=U3900.D7:2.54MM

31

1

2

17 31

21

L3906

22NH

21

0402

1

C3938

1000PF

10% 16V

2

X7R-CERM 0201

PLACE_NEAR=U3900.M14:2.54MM

1

C3926

4.7UF

20%

6.3V

2

X5R 402

C3939

1UF

10%

10V

X5R

402

BYPASS=U3900.G15:2.54MM

32 70

OUT

32 70

OUT

32 70

OUT

32 70

OUT

32 70

OUT

32 70

OUT

32 70

OUT

32 70

OUT

32 70

OUT

32 70

OUT

32 70

OUT

32 70

OUT

32 70

OUT

32 70

OUT

32 70

OUT

32 70

OUT

32 70

OUT

32 70

OUT

32 70

OUT

32 70

OUT

32 70

OUT

32 70

OUT

32 70

OUT

32 70

OUT

XW3900

SM

21

1

C3941

2.2UF

20%

6.3V

2

CERM 402-LF

BYPASS=U3900.F15:2.54MM

MEM_CAM_A<0> MEM_CAM_A<1> MEM_CAM_A<2> MEM_CAM_A<3> MEM_CAM_A<4> MEM_CAM_A<5> MEM_CAM_A<6> MEM_CAM_A<7> MEM_CAM_A<8> MEM_CAM_A<9> MEM_CAM_A<10> MEM_CAM_A<11> MEM_CAM_A<12> MEM_CAM_A<13> MEM_CAM_A<14>

MEM_CAM_BA<0> MEM_CAM_BA<1> MEM_CAM_BA<2>

MEM_CAM_CLK_P MEM_CAM_CLK_N

MEM_CAM_DM<0> MEM_CAM_DM<1>

MEM_CAM_ZQ_S2 MEM_CAM_CKE MEM_CAM_CS_L

1

C3921

1.0UF

20%

6.3V

2

X5R 0201-1

1

C3930

1.0UF

20%

6.3V

2

X5R 0201-1

1

C3932

1.0UF

20%

6.3V

2

X5R 0201-1

1

C3919

0.1UF

10%

6.3V

2

CERM-X5R 0201

BYPASS=U3900.J1:2.54MM

GND_CAM_PVSSD

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

VOLTAGE=0V

1

C3922

0.1UF

10%

6.3V

2

CERM-X5R 0201

1

C3931

10UF

20%

6.3V

2

CERM-X5R 0402-1

1

C3933

10UF

20%

6.3V

2

CERM-X5R 0402-1

1

C3918

1000PF

10% 16V

2

X7R-CERM 0201

BYPASS=U3900.J1:2.54MM

1

C3942

4.7UF

20%

6.3V

2

X5R 402

BYPASS=U3900:7mm

BYPASS=U3900:5mm

L3

DDR_AD00

M4

DDR_AD01

N3

DDR_AD02

M3

DDR_AD03

M1

DDR_AD04

M2

DDR_AD05

P4

DDR_AD06

N2

DDR_AD07

P3

DDR_AD08

P2

DDR_AD09

J4

DDR_AD10

R2

DDR_AD11

L1

DDR_AD12

P1

DDR_AD13

R4

DDR_AD14

K3

DDR_BA0

L2

DDR_BA1

K2

DDR_BA2

H2

DDR_CK_P0

G2

DDR_CK_N0

C1

DDR_DM0

C4

DDR_DM1

G3

DDR_ZQ

J3

DDR_CKE

L4

DDR_CS*

XW3901

1

C3923

1.0UF

20%

6.3V

2

X5R 0201-1

L3903

220-OHM-1.4A

0603

L3904

220-OHM-1.4A

0603

1

C3916

0.1UF

10%

6.3V

2

CERM-X5R 0201

BYPASS=U3900.L7:2.54MM

SM

21

1

C3940

0.1UF

10%

6.3V

2

CERM-X5R 0201

BYPASS=U3900:3mm

SYM 2 OF 3

OMIT_TABLE

U3900

BCM15700

CRITICAL

31

21

BYPASS=U3900.D6:2.54MM

1

C3934

1000PF

10% 16V

2

X7R-CERM 0201

BYPASS=U3900:5mm

FBGA

1

C3924

0.1UF

2

GND_CAM_PVSSD

1

C3917

1000PF

10% 16V

2

X7R-CERM 0201

BYPASS=U3900.K13:2.54MM

10%

6.3V CERM-X5R 0201

1

2

BYPASS=U3900.D6:2.54MM

1

C3935

0.1UF

10%

6.3V

2

CERM-X5R 0201

BYPASS=U3900:3mm

DDR_DQ00 DDR_DQ01 DDR_DQ02 DDR_DQ03 DDR_DQ04 DDR_DQ05 DDR_DQ06 DDR_DQ07 DDR_DQ08 DDR_DQ09 DDR_DQ10 DDR_DQ11 DDR_DQ12 DDR_DQ13 DDR_DQ14 DDR_DQ15

DDR_DQS_P0 DDR_DQS_N0

DDR_DQS_P1 DDR_DQS_N1

DDR_RAS*

DDR_WE*

DDR_CAS*

DDR_RESET*

1

2

C3912

4.7UF

20%

6.3V X5R 402

1

2

C3913

4.7UF

20%

6.3V X5R 402

PP1V2_CAM_XTALPCIEVDD

PP1V2_CAM

31

C3910

0.1UF

10%

6.3V CERM-X5R 0201

1

C3951

0.1UF

6.3V

2

CERM-X5R 0201

10%

PP3V3_S3RS0_CAMERA

1

C3936

1000PF

10% 16V

2

X7R-CERM 0201

BYPASS=U3900:5mm

C2

MEM_CAM_DQ<0>

E3

MEM_CAM_DQ<1>

E4

MEM_CAM_DQ<2>

D3

MEM_CAM_DQ<3>

F3

MEM_CAM_DQ<4>

F1

MEM_CAM_DQ<5>

F4

MEM_CAM_DQ<6>

F2

MEM_CAM_DQ<7>

B5

MEM_CAM_DQ<8>

C3

MEM_CAM_DQ<9>

B1

MEM_CAM_DQ<10>

B4

MEM_CAM_DQ<11>

A5

MEM_CAM_DQ<12>

C5

MEM_CAM_DQ<13>

B2

MEM_CAM_DQ<14>

B3

MEM_CAM_DQ<15>

E2

MEM_CAM_DQS_P<0>

D2

MEM_CAM_DQS_N<0>

A2

MEM_CAM_DQS_P<1>

A3

MEM_CAM_DQS_N<1>

H3

MEM_CAM_RAS_L

J2

MEM_CAM_WE_L

H4

MEM_CAM_CAS_L

R3

MEM_CAM_RESET_L

1

2

BYPASS=U3900.F6:2.54MM

31

NC NC

PP1V8_CAM

NOSTUFF

1

R3930

100K

5% 1/20W MF 201

2

1

R3931

330K

5% 1/20W MF 201

2

GND_CAM_PVSSC

P7

MIPI_CP_CLK

R7

MIPI_CM_CLK

P8

MIPI_DP0

R8

MIPI_DM0

P6

MIPI_DP1

R6

MIPI_DM1

B7

PCIE_RDP0

A7

PCIE_RDN0

B10

PCIE_REFCLKP

A10

PCIE_REFCLKN

A8

PCIE_TDP0

B8

PCIE_TDN0

B9

PCIE_TESTP

C9

PCIE_TESTN

A13

XTAL_P

A12

XTAL_N

D15

I2C_CLK_DBG

R10

I2C_CLK_SENSOR

C15

I2C_DATA_DBG

R9

I2C_DATA_SENSOR

F13

JTAG_TCK

E12

JTAG_TDI

F12

JTAG_TDO

D12

JTAG_TMS

D11

JTAG_TRST*

C11

JTAG_SRST*

P13

PCIE_CLKREQ*

R14

PCIE_RST*

N12

PCIE_WAKE*

G12

PWR_MODE

E15

RESET*

R13

SENSOR_WAKE*

H12

SHUTDOWN*

31 32

NOSTUFF

1

R3932

100K

5% 1/20W MF 201

2

1

R3933

330K

5% 1/20W MF 201

2

1

C3914

4.7UF

20%

6.3V

2

X5R 402

OMIT_TABLE

PP1V8_CAM

31 32

NOSTUFF

1

R3934

100K

5% 1/20W MF 201

2

CAM_RAMCFG2 CAM_RAMCFG1 CAM_RAMCFG0

1

R3935

330K

5% 1/20W MF 201

2

1

C3915

4.7UF

20%

6.3V

2

X5R 402

PLACE_NEAR=U3900.M13:2.54MM

U3900

BCM15700

FBGA

SYM 1 OF 3

CRITICAL

STRAP_XTAL_FREQ

STRAP_XTAL_SEL

CAM_A1

1

R3915

100K

5% 1/20W MF 201

2

CAM_JTAG_SRST_L

L3901

1.0UH-1.6A-55MOHM

1008

DEBUG_00 DEBUG_01 DEBUG_02 DEBUG_03 DEBUG_04 DEBUG_05 DEBUG_06 DEBUG_07 DEBUG_08 DEBUG_09 DEBUG_10 DEBUG_11 DEBUG_12 DEBUG_13 DEBUG_14 DEBUG_15 DEBUG_16

GPIO_00 GPIO_01 GPIO_02 GPIO_03 GPIO_04 GPIO_05 GPIO_06 GPIO_07

UARTCTS UARTRTS

UARTRXD UARTTXD

TEST_OUT

TEST_MODE

CAM_TEST_OUT

31

21

P1V2_CAM_SRVLXC_PHASE

PLACE_NEAR=U3900.M13:4MM

B11

TP_CAM_TEST_MODE0

C14

TP_CAM_TEST_MODE1

B14

TP_CAM_TEST_MODE2

A15

TP_CAM_LV_JTAG_TCK

E11

TP_CAM_LV_JTAG_TDI

E10

TP_CAM_LV_JTAG_TDO

F11

TP_CAM_LV_JTAG_TMS

F10

TP_CAM_LV_JTAG_TRSTN

G11

NC

G10

NC

H11

NC

H10

NC

J10

NC

K11

NC

K10

NC

L11

NC

L10

NC

R12

CAM_RAMCFG0

P12

CAM_RAMCFG1

P11

CAM_RAMCFG2

P10

CAM_GPIO3

P9

TP_CAM_PLL_BYPASS

N11

NC

N10

NC

N9

NC

D13

CAM_UARTCTS

D14

TP_CAM_UARTRTS

E13

CAM_UARTRXD

E14

TP_CAM_UARTTXD

J12

CAM_TEST_OUT

M10

CAM_TEST_MODE

C13

CAM_XTAL_FREQ

C12

CAM_XTAL_SEL

CAM_TEST_MODE

31

A1 SILICON BUG

SYNC_MASTER=J43_MLB1

31

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

Camera 1 of 2

Apple Inc.

R

6 3

NO STUFF

1

R3910

100K

5% 1/20W MF 201

2

12

PP1V8_CAM

31 32

NOSTUFF

R3936

31

NOSTUFF

R3937

31

1

R3911

100K

5% 1/20W MF 201

2

SYNC_DATE=01/09/2013

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

39 OF 120

SHEET

31 OF 73

124578

100K

1/20W

100K

1/20W

D

31

C

1

5% MF

201

2

1

5% MF

201

2

B

A

SIZE

D

8 7 6 5 4 3

PP1V35_CAM

31 70

D

PP0V675_CAM_VREF

31 70

R4022

1/20W

R4023

1/20W

1K

1% MF

201

1K

1%

MF

201

C

31 70

IN

31 70

IN

31 70

IN

MEM_CAM_CKE_R

NO STUFF

1

R4006

100PF

5% 25V

2

NP0-CERM 0201

B

R4000

21

5%00201 MF

1

2

1

2

1/20W

1

R4020

84.5

1% 1/20W MF 201

2

NO STUFF

1

R4021

82

1% 1/20W MF 201

2

R4002

1/20W

NOSTUFF

R4003

1/20W

1K

5%

MF

201

1K

5%

MF

201

PP0V675_MEM_CAM_VREFDQ

70

PP0V675_MEM_CAM_VREFCA

70

1

2

1

2

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

VOLTAGE=0.675V

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

VOLTAGE=0.675V

1

R4004

240

1% 1/20W MF 201

2

C4010

0.1UF

CERM-X5R

31 70

31

10%

6.3V

0201

IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN

IN IN IN

IN

1

C4011

0.1UF

10%

6.3V

2

CERM-X5R 0201

MEM_CAM_A<0> MEM_CAM_A<1> MEM_CAM_A<2> MEM_CAM_A<3> MEM_CAM_A<4> MEM_CAM_A<5> MEM_CAM_A<6> MEM_CAM_A<7> MEM_CAM_A<8> MEM_CAM_A<9> MEM_CAM_A<10> MEM_CAM_A<11> MEM_CAM_A<12> MEM_CAM_A<13> MEM_CAM_A<14>

MEM_CAM_BA<0> MEM_CAM_BA<1> MEM_CAM_BA<2>

MEM_CAM_RAS_L MEM_CAM_CAS_L MEM_CAM_WE_L

MEM_CAM_CLK_P MEM_CAM_CLK_N

MEM_CAM_CKE MEM_CAM_CS_L

MEM_CAM_ODT

70

MEM_CAM_ZQ_DDR

MEM_CAM_RESET_L

BYPASS=U4000.A1:4mm

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC*

T3

A13

T7

A14

M2

BA0

N8

BA1

M3

BA2

J3

RAS*

K3

CAS*

L3

WE*

J7

CK

K7

CK*

K9

CKE

L2

CS*

K1

ODT

L8

ZQ

T2

RESET*

1

2

C4002

10UF

20%

6.3V CERM-X5R 0402-1

VDDQ

VSSQ

BYPASS=U4000.B2:4mm

1

C4003

10UF

20%

6.3V

2

CERM-X5R 0402-1

H9H2F1E9D2C9C1A8A1

U4000

4GB-DDR3-256MX16

FBGA

H5TC4G63AFR

CRITICAL

G9G1F9E8E2D8D1B9B1

E1

B3

A9

VDD

1

2

VSS

C4004

0.47UF

20% 4V CERM-X5R-1 201

1

C4005

0.1UF

10%

6.3V

2

CERM-X5R 0201

BYPASS=U4000.H9:4mm

H1

M8

R9R1N9N1K8K2G7D9B2

VREFCA

VREFDQ

NC

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQSL

DQSL*

DQSU

DQSU*

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

DML DMU

P9P1M9M1J8J2G8

T9

T1

J1

J9 L1

L9 M7

E3 F7

F2

F8 H3

H8

G2 H7

F3

G3

C7

B7

D7

C3

C8 C2

A7 A2

B8

A3

E7

D3

BYPASS=U4000.D2:4mm

1

C4006

2.2UF

20% 10V

2

X5R-CERM 402

NC NC NC NC NC

MEM_CAM_DQ<0> MEM_CAM_DQ<1> MEM_CAM_DQ<2> MEM_CAM_DQ<3> MEM_CAM_DQ<4> MEM_CAM_DQ<5> MEM_CAM_DQ<6> MEM_CAM_DQ<7>

MEM_CAM_DQS_P<0> MEM_CAM_DQS_N<0>

MEM_CAM_DQS_P<1> MEM_CAM_DQS_N<1>

MEM_CAM_DQ<8> MEM_CAM_DQ<9> MEM_CAM_DQ<10> MEM_CAM_DQ<11> MEM_CAM_DQ<12> MEM_CAM_DQ<13> MEM_CAM_DQ<14> MEM_CAM_DQ<15>

MEM_CAM_DM<0> MEM_CAM_DM<1>

1

C4007

2

0.1UF

10%

6.3V CERM-X5R 0201

BYPASS=U4000.R9:4mm

BI BI BI BI BI BI BI BI

BI BI

BI BI BI BI BI BI BI BI

31 70

IN

31 70

IN

1

C4008

2.2UF

20% 10V

2

X5R-CERM 402

CAM_XTAL:YES

31 70

BYPASS=U4000.K2:4mm

1

C4009

0.1UF

10%

6.3V

2

CERM-X5R 0201

C4015

12PF

5%

25V

NP0-C0G-CERM

0201

C4014

12PF

5%

25V

NP0-C0G-CERM

0201

21

CLK25M_CAM_XTALP

4 2

3 1

CAM_XTAL:YES

CAM_SENSOR_WAKE_L_CONN

32 62

CAM_WAKE:NO

SYSCLK_CLK25M_CAMERA

17 67

IN

CRITICAL

Y4000

NC

SM-3.2X2.5MM

NC

25.000MHZ-12PF-20PPM CAM_XTAL:YES

1

R4031

0

5%

1/20W

MF

0201

2

PCIE_CAMERA_R2D_C_P

14 67

IN

PCIE_CAMERA_R2D_C_N

14 67

IN

PCIE_CAMERA_D2R_C_P

31 67

IN

PCIE_CAMERA_D2R_C_N

31 67

IN

PCIE_CLK100M_CAMERA_P

12 67

IN

PCIE_CLK100M_CAMERA_N

12 67

IN

CAM_XTAL:YES

R4007

21

CLK25M_CAM_XTALP_R

67 67

5%00201

1/20W

1

MF

R4012

1M

1% 1/20W MF 201

2

67

NOTE: TBD PPM crystal required

CAM_WAKE:YES

R4030

21

31

5%00201

1/20W

MF

NOSTUFF

CLK25M_CAM_XTALN

CAM_SENSOR_WAKE_L

C4033

0.1UF

C4032

0.1UF

C4031

0.1UF

C4030

0.1UF

C4061

0.1UF

C4062

0.1UF

CAM_XTAL:NO

21

PCIE_CAMERA_R2D_P

10%

16V

X5R-CERM

21

PCIE_CAMERA_R2D_N

10%

16V

X5R-CERM

21

PCIE_CAMERA_D2R_P

10%

X5R-CERM

16V

21

PCIE_CAMERA_D2R_N

10%

X5R-CERM

16V

21

PCIE_CLK100M_CAMERA_C_P

10%

16V

X5R-CERM

21

PCIE_CLK100M_CAMERA_C_N

10%

16V

X5R-CERM

R4008

5%00201

1/20W

R4009

0

21

5%

CAM_XTAL:YES

1/20W

MF

0201

R4010

0

21

5%

CAM_XTAL:YES

1/20W

MF

0201

PP1V8_CAM

1

R4005

100K

5% 1/20W MF 201

2

21

CLK25M_CAM_CLKP

MF

CLK25M_CAM_CLKN

31

0201

12

OUT

CAM_XTAL:NO

1

C4016

100PF

5% 25V

2

NP0-CERM 0201

31 67

14 67

D

31 67

OUT

31 67

OUT

31 67

IN

31 67

OUT

C

B

L4009

CAMERA SENSOR

CRITICAL

J4002

CCR20-AK7100-1

F-RT-SM

14

1

2

MIPI_CLK_CONN_N

62 70

3

MIPI_CLK_CONN_P

62 70

4

CAM_SENSOR_WAKE_L_CONN

5

MIPI_DATA_CONN_N

62 70

6

MIPI_DATA_CONN_P

62 70

7

8

SMBUS_SMC_1_S0_SDA

9

A

ALS

SMBUS_SMC_1_S0_SCL

10

I2C_CAM_SCK

11

I2C_CAM_SDA

12

PP5V_S3RS0_ALSCAM_F

62

13

BI IN IN BI

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

VOLTAGE=5V

518S0892

32 62

14 35 38 41 42 62 67 71

31 62

C4013

0.1uF

20% 10V

CERM

402

L4010

FERR-120-OHM-1.5A

2 1

0402-LF

1

2

NOSTUFF

L4011

FERR-120-OHM-1.5A

2 1

0402-LF

90-OHM-0.1A

TCM0605

SYM_VER-1

1

PLACE_NEAR=J4002.2:2.54MM

CRITICAL

L4007

90-OHM-0.1A

TCM0605

SYM_VER-1

1

PLACE_NEAR=J4002.2:2.54MM

CRITICAL

PP5V_S0

PP5V_S4RS3

6 3

4

MIPI_CLK_N

32

MIPI_CLK_P

4

MIPI_DATA_N

32

MIPI_DATA_P

77.2 mA nominal max

96.2 mA peak

31 70

IN

31 70

IN

31 70

BI

31 70

BI

16 17 43 49 50 54 56 57 59 60 62

33 45 47 52 53 56 60 62

SYNC_MASTER=J43_MLB PAGE TITLE

Camera 2 of 2

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=09/14/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

40 OF 120

SHEET

32 OF 73

124578

SIZE

A

D

8 7 6 5 4 3

Right USB Port A

12

D

PP5V_S4RS3

32 45 47 52 53 56 60 62

XDP_USB_EXTA_OC_L

14 16

OUT

USB_PWR_EN

57 59 63

1

C4690

10UF

20%

6.3V

2

CERM-X5R

0402-1

Current limit per port (R4600+R4601): 2.19A min / 2.76A max

C

Mojo SMC Debug Mux

PP3V42_G3H

17 30 34 35 36 38 44 46 47 48 57 59 60 62 63

BYPASS=U4650.9:3:5mm

SMC_DEBUGPRT_RX_L

35 36 66

IN

SMC_DEBUGPRT_TX_L

35 36 66

OUT

USB_EXTA_P

14 66

BI

USB_EXTA_N

14 66

BI

SIGNAL_MODEL=MOJO_MUX_SMSC

B

USB Port Power Switch

U4600

TPS2557DRB

2

IN_0

3

IN_1

8

FAULT*

4

EN

1

2

C4691

0.1UF

10% 16V X5R-CERM 0201

C4650

0.1UF

X5R-CERM

1

C4696

220UF-35MOHM

20%

6.3V

2

POLY-TANT CASE-B2-SM1

10% 10V

0201

CRITICAL

1

2

5 4

7 6

8

VCC

M+ M-

U4650

PI3USB102EZLE

TQFN

D+

CRITICAL

D-

GND

1

9

3

CRITICAL

SON

THRM

PAD

9

SELOE*

OUT1 OUT2

ILIM

Y+ Y-

6 7

5

USB_ILIM

USB_ILIM_R

1

R4601

22.1K

1% 1/20W MF 201

2

1

R4650

100K

5% 1/20W MF 201

2

1 2

10

SMC_DEBUGPRT_EN_L

R4600

22.1K

1%

1/20W

MF

201

SEL OUTPUT

L SMC (M) H USB (D)

CRITICAL

L4605

PP5V_S3_RTUSB_A_ILIM

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.15 mm VOLTAGE=5V

1

C4695

10UF

2

CERM-X5R

0402-1

20%

6.3V 2

USB2_EXTA_MUXED_N

66

USB2_EXTA_MUXED_P

66

C4621

0.1UF

10%

OUT

21

6.3V

USB3_EXTA_D2R_N

USB3_EXTA_D2R_P

USB3_EXTA_R2D_N

66

USB3_EXTA_R2D_P

66

14 66

35

IN

GND_VOID=TRUE

C4620

0.1UF

14 66

USB3_EXTA_R2D_C_N

IN

USB3_EXTA_R2D_C_P

10%

CERM-X5R 0201

21

6.3V

CERM-X5R 0201

GND_VOID=TRUE

C4605

0.01UF

X5R-CERM

10% 16V

0201

FERR-120-OHM-3A

1

2

4 3

0603

CRITICAL

L4600

90-OHM DLP0NS

SYM_VER-1

21

CRITICAL

D4601

ESD0P2RF-02LS

TSSLP-2-1

GND_VOID=TRUE

ESD0P2RF-02LS

GND_VOID=TRUE

CRITICAL

D4611

ESD0P2RF-02LS

TSSLP-2-1

PP5V_S3_RTUSB_A_F

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.375 mm VOLTAGE=5V

CRITICAL

D4621

TSSLP-2-1

CRITICAL

J4600

USB3.0-J11-J13

F-RT-TH

1

VBUS

2

SSTX+

3

SSTX-

4

GND

USB2_EXTA_MUXED_F_N

66

USB2_EXTA_MUXED_F_P

66

CRITICAL

2

1

D4600

ESD0P2RF-02LS

TSSLP-2-1

1

5

D-

6

D+

7

GND

8

SXRX+

9

SSRX-

10

GND

11 12

13

14 15

16

17 18

APN: 514-0819

GND_VOID=TRUE

CRITICAL

2

1

2

1

2

D4610

ESD0P2RF-02LS

TSSLP-2-1

1

D4620

ESD0P2RF-02LS

TSSLP-2-1

GND_VOID=TRUE

CRITICAL

D

C

B

A

SYNC_MASTER=J43_MLB

PAGE TITLE

External A USB3 Connector

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

6 3

SYNC_DATE=02/20/2013

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

46 OF 120

SHEET

33 OF 73

124578

SIZE

A

D

8 7 6 5 4 3

PLACE_NEAR=J4800.10:1.5MM

R4830

0

PP3V3_S4

25 26 27 29 34 36 37 56 60 62

PLACE_NEAR=J4800.14:1.5MM

D

PP5V_S5

51 52 60

C4810

0.1UF

X5R-CERM

PLACE_NEAR=J4800.14:1.5MM

PLACE_NEAR=R4844.1:1.5MM

SMC_PME_S4_WAKE_L

29 35 37

OUT

To SMC

PLACE_NEAR=R4841.1:1.5MM

C

PP3V3_S3

15 18 19 34 38 39 56 60 62 63

TPAD_SPI_INT_L

15

OUT

To PCH

FERR-120-OHM-1.5A

1

10% 16V

2

0201

TPAD_INTWAKE:SPLIT

R4841

0

5%

1/20W

MF

0201

TPAD_INTWAKE:SHARED

R4843

0

5%

1/20W

MF

0201

TPAD_INTWAKE:SHARED

Q4800

1

DMN32D2LFB4

DFN1006H4-3

SYM_VER_3

S G

2

PLACE_NEAR=R4842.2:5MM

21

5%

1/20W

MF

C4800

0201

0.1UF

6.3V

CERM-X5R

0201

L4820

21

0402-LF

21

3

D

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V

PP3V42_G3H

17 30 33 35 36 38 44 46 47 48 57 59 60 62 63

(TPAD_WAKE_L)

(TPAD_SPI_INT_S4_WAKE_L_CONN)

VOLTAGE=3.3V MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.5 mm

1

10%

2

BYPASS=J4800.10:1.5MM

BYPASS=J4800.19:1.5MM

C4820

0.1UF

6.3V

CERM-X5R

0201

10%

1

2

TPAD_INTWAKE:SHARED

R4844

PLACE_NEAR=J4800.8:1.5MM

1/20W

IPD Flex Connector

CRITICAL

518S0884

J4800

TF13BS-20S-0.4SH

F-RT-SM-1

22

R4850

33

TPAD_SPI_MISO

15

OUT

66

TPAD_SPI_CLK

15

IN

66

TPAD_SPI_MOSI

15

IN

66

1

0

5%

MF

0201

2

1/20W

5%

PLACE_NEAR=J4800.2:2.54mm

1/20W

5%

PLACE_NEAR=J4800.7:2.54mm

1/20W

5%

PLACE_NEAR=J4800.9:2.54mm

1/20W

5%

PLACE_NEAR=J4800.12:2.54mm

21

MF

201

33

21

R4851

MF

201

33

21

R4852

MF

201

33

21

R4853

MF

201

SMC_LID

34 35 36 46 62

IN

TPAD_SPI_MISO_R

62

USB_TPAD_P

14 62 66

BI

USB_TPAD_N

14 62 66

BI

TPAD_SPI_CLK_R

62

TPAD_WAKE_L

62

TPAD_SPI_MOSI_R

62

PP3V3_S4_IPD

62

TPAD_SPI_CS_R_L

62

TPAD_SPI_IF_EN_CONN

62

TPAD_SPI_INT_S4_WAKE_L_CONN

62

PP5V_S4_IPD

62

TPAD_USB_IF_EN_CONN

62

SMBUS_SMC_3_SDA

34 35 38 42 62 71

BI

SMBUS_SMC_3_SCL

34 35 38 42 62 71

BI

SMC_LSOC_RST_L

34 36 62

OUT

(=PP3V42_G3H_IPD)

SMC_ONOFF_L

34 35 36 62

OUT

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

12

D

C

TPAD_INTWAKE:SPLIT

R4842

0

21

5%

1/20W

MF

0201

PLACE_NEAR=R4843.2:1.5MM

PP3V3_S4

25 26 27 29 34 36 37 56 60 62

BYPASS=U4810:3mm

13 18 29 34 35 57

IN

B

15

IN

From PCH

13 18 29 34 35 57

IN

15

IN

PM_SLP_S4_L

TPAD_USB_IF_EN

NOSTUFF

1

R4810

100K

5% 1/20W MF 201

2

PM_SLP_S4_L

TPAD_SPI_IF_EN

From PCH

C4841

0.1UF

6.3V

CERM-X5R

0201

1

10%

2

CRITICAL

74LVC2G08GT

8

SOT833

1

A

7

(TPAD_USB_IF_EN_CONN)

Y

U4810

2

08

B

4

CKPLUS_WAIVE=UNCONNECTED_PINS

74LVC2G08GT

8

SOT833

5

A

3

Y

U4810

6

08

B

4

CKPLUS_WAIVE=UNCONNECTED_PINS

(TPAD_SPI_IF_EN_CONN)

B

PP3V3_S3

15 18 19 34 38 39 56 60 62 63

1

60 62 63 72

PP3V3_S0

8

11 12 13 15 17 18 26 30 36

37 38 39 40 41 42 43 54 57 59

SMBUS_SMC_3_SDA

A

NOSTUFF

1

C4832

100PF

5% 25V

2

NP0-CERM 0201

BYPASS=J4800.6:1.5MM

NOSTUFF

1

C4833

100PF

5% 25V

2

NP0-CERM 0201

BYPASS=J4800.5:1.5mm

1

C4834

100PF

5% 25V

2

NP0-CERM 0201

BYPASS=J4800.4:1.5MM

1

C4835

100PF

5% 25V

2

NP0-CERM 0201

BYPASS=J4800.3:8.5MM

SMBUS_SMC_3_SCL SMC_ONOFF_L SMC_LID SMC_LSOC_RST_L

1

C4836

100PF

5% 25V

2

NP0-CERM 0201

BYPASS=J4800.1:1.5MM

34 35 38 42 62 71

34 35 36 62

34 35 36 46 62

34 36 62

15

IN

TPAD_SPI_CS_L

1

2

S G

Q4860

DMN32D2LFB4

DFN1006H4-3

SYM_VER_3

D

3

6 3

R4860

100K

5% 1/20W MF 201

2

TPAD_SPI_CS_CONN_L

SYNC_MASTER=J43_MLB

PAGE TITLE

IPD Connector

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/17/2013

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

48 OF 120

SHEET

34 OF 73

124578

SIZE

A

D

8 7 6 5 4 3

12

D

U5000

LM4FSXAH5BB

(PL7)

(PL6)

BGA

(1 OF 2)

OMIT_TABLE

T3CCP1/PJ5/C2T3CCP0/PJ4/C2+

AIN00 AIN01 AIN02 AIN03 AIN04 AIN05 AIN06 AIN07 AIN08 AIN09 AIN10 AIN11 AIN12 AIN13 AIN14 AIN15 AIN16 AIN17 AIN18 AIN19 AIN20 AIN21 AIN22 AIN23

PC5/C1+

SSI0CLK/PA2 SSI0FSS/PA3

SSI0RX/PA4 SSI0TX/PA5

U1RX/B0

U1TX/PB1 T0CCP0/PB6 T0CCP1/PB7

SSI1RX/PF0 SSI1TX/PF1

SSI1CLK/PF2 SSI1FSS/PF3

WT0CCP0/PG4 WT0CCP1/PG5

WT2CCP0/PH0 WT2CCP1/PH1

WT3CCP0/PH4 WT3CCP1/PH5 WT4CCP0/PH6 WT4CCP1/PH7

T1CCP0/PJ0 T1CCP1/PJ1 T2CCP0/PJ2 T2CCP1/PJ3

WT5CCP1/PM3

C0C0+ C1-

PF4 PF5

E2 E1

F2

F1 B3

A3

B4 A4

B5 A5

B6

A6 C1

C2

B1 B2

G2

G1 H1

H2 B7

A7

B8 A8

K2 K1

L2

L1 C5

D5

M2

M3 L4

N1

F11

E11

F4 F3

M9

N9

L10 K10

L9

K9

K7

L7

K3 K4

J3 H4

H3

G4

C9

B9 A9

C8

H10

SMC_HS_COMPUTING_ISENSE SMC_PBUS_VSENSE SMC_BMON_ISENSE SMC_DCIN_ISENSE SMC_DCIN_VSENSE SMC_BMON_DISCRETE_ISENSE SMC_CPU_ISENSE SMC_OTHER_HI_ISENSE SMC_PANEL_ISENSE SMC_1V2S3_ISENSE SMC_LCDBKLT_ISENSE SMC_P3V3S5_ISENSE SMC_WLAN_ISENSE SMC_SSD_ISENSE SMC_P3V3S0_ISENSE SMC_CAMERA_ISENSE NC_SMC_ADC16 SMC_P1V05S0_VSENSE SMC_CPUDDR_ISENSE SMC_P1V05S0_ISENSE SMC_CPU_VSENSE SMC_CPUVR_ADJUST_ISENSE SMC_CPU_IMON_ISENSE PP3V3_WLAN

CPU_PROCHOT_L SMC_VCCIO_CPU_DIV2 SMC_S5_PWRGD_VIN

SPI_DESCRIPTOR_OVERRIDE_L

CPU_CATERR_L CPU_THRMTRIP_3V3

SMC_PM_G2_EN PM_DSW_PWRGD SMC_DELAYED_PWRGD SMC_PROCHOT

SMC_DEBUGPRT_RX_L SMC_DEBUGPRT_TX_L NC_SMC_SYS_LED NC_SMC_GFX_THROTTLE_L

SPI_SMC_MISO SPI_SMC_MOSI SPI_SMC_CLK SPI_SMC_CS_L S5_PWRGD PM_PCH_SYS_PWROK

SMC_DEBUGPRT_EN_L NC_SMC_GFX_OVERTEMP

ALL_SYS_PWRGD SMC_THRMTRIP

PM_PWRBTN_L PM_SYSRST_L MEM_EVENT_L SMC_ADAPTER_EN

SMC_OOB1_D2R_L SMC_OOB1_R2D_L SMC_CPU_DBGPWR_RD_L NC_BDV_BKL_PWM

PM_BATLOW_L

37 39

IN

37 40

IN

37 39

IN

37 39

IN

37 40

IN

37 41

IN

37 40

IN

37 39

IN

37 41

IN

37 39

IN

37 39

IN

37 40

IN

37 39

IN

37 39

IN

37 39

IN

37 39

IN

37 63

IN

37 40

IN

37 40

IN

37 40

IN

37 40

IN

37 41

IN

37 41

IN

29 36 37 39 62

IN

6

36 49 65

IN

36

IN

36

IN

17

OUT

6

65

IN

36

IN

36 52 57

OUT

13

OUT

17 26 27 36

OUT

36

OUT

33 36 66

IN

33 36 66

OUT

62

OUT

62

BI

44 67

IN

44 67

OUT

44 67

OUT

44 67

OUT

52 57

IN

13 16 17

IN

33

OUT

62

IN

16 17 57

IN

36

OUT

13 16

OUT

13 17 62

(OD)

OUT

36

BI

13 36

OUT

30

IN

30

OUT

41

OUT

62

OUT

13 27

OUT

PP3V42_G3H

1

C5002

1UF

20%

6.3V

2

X5R 0201

17 30 33 34 36 38 44 46 47 48 57 59 60 62 63

1

C5003

0.1UF

10% 10V

2

X5R-CERM 0201

1

C5007

0.1UF

10% 10V

2

X5R-CERM 0201

1

C5004

2

1

C5008

2

0.1UF

10% 10V X5R-CERM 0201

0.1UF

10% 10V X5R-CERM 0201

1

C5005

2

1

C5009

2

0.1UF

10% 10V X5R-CERM 0201

0.1UF

10% 10V X5R-CERM 0201

1

C5006

2

0.1UF

10% 10V X5R-CERM 0201

1

R5002

1M

5% 1/20W MF 201

2

SMC_RESET_L

36 44 48

IN

62

WIFI_EVENT_L

29 36 62

BI

SMC_WAKE_L NC_SMC_HIB_L

SMC_CLK32K

36 67

IN

NC_SMC_XOSC1

SMC_EXTAL

36

SMC_XTAL

36

PP1V2_S5_SMC_VDDC

MIN_LINE_WIDTH=0.25MM MIN_NECK_WIDTH=0.1MM VOLTAGE=1.2V

PLACE_NEAR=U5000.D6:5MM

1

C5010

1.0UF

20%

6.3V

2

X5R 0201-1

PLACE_NEAR=U5000.D6:5MM

1

C5017

1.0UF

20%

6.3V

2

X5R 0201-1

L5001

30-OHM-1.7A

0402

RST*

B11

(OD)

PLACE_NEAR=U5000.K13:5MM

1

C5015

0.1UF

10% 10V

2

X5R-CERM 0201

N13

M12

M10

N10

G12

G13

K12

D7 E6

E8

E9

F10

J7 J9

J10

J1

J6

K13

D6

PK4/RTCCLK WAKE* HIB*

XOSC0 XOSC1

OSC0 OSC1

VBAT

21

PP3V3_S5_SMC_VDDA

MIN_LINE_WIDTH=0.25MM MIN_NECK_WIDTH=0.1MM VOLTAGE=3.3V

U5000

LM4FSXAH5BB

BGA

(2 OF 2)

SWCLK/TCK SWDIO/TMS

OMIT_TABLE

VDD

VDDC

PLACE_NEAR=U5000.K13:5MM

1

C5016

0.1UF

10% 10V

2

X5R-CERM 0201

C10G10 A10

A11

SWO/TDO

B10

TDI

A2

NC

D3

VDDA

D2

VREFA+

D1

VREFA-

PLACE_NEAR=U5000.J6:5MM

1

2

GNDA

GND

C5014

1.0UF

20%

6.3V X5R 0201-1

40 41 39

C3

36

E3

A1

C7 D9

E5 F9

H5

H9 J5

J8

J11

K11

SMC_TCK SMC_TMS SMC_TDO SMC_TDI

NC

PP3V3_S5_AVREF_SMC

GND_SMC_AVSS

PLACE_NEAR=U5000.J6:5MM

1

C5012

0.1UF

10% 10V

2

X5R-CERM 0201

36 44 62

36 62

BYPASS=U5000.D2:D1:1MM

PLACE_NEAR=U5000.J1:5MM

1

C5013

0.1UF

10% 10V

2

X5R-CERM 0201

1

C5001

0.1UF

10% 10V

2

X5R-CERM 0201

36

XW5000

SM

2 1

PLACE_NEAR=U5000.A1:4MM

1

C5020

0.01UF

10% 10V

2

X5R-CERM 0201

BYPASS=U5000.D2:D1:1MM

PLACE_NEAR=U5000.J1:5MM

1

C5011

0.1UF

10% 10V

2

X5R-CERM 0201

1

C5021

1UF

2

20%

6.3V X5R 0201

NC

B13

LPC0AD0

A13

LPC0AD1

C12

LPC0AD2

D11

LPC0AD3

H12

LPC0CLK

D12

LPC0FRAME*

C13

LPC0RESET*

H13

LPC0SERIRQ

G11

LPC0CLKRUN*

F13

LPC0PD*

F12

LPC0SCI*

B12

PK5

E10

I2C0SCL

D13

I2C0SDA

M4

I2C1SCL

N2

I2C1SDA

N8

I2C2SCL

M8

I2C2SDA

L8

I2C3SCL

K8

I2C3SDA

N7

I2C4SCL

M7

I2C4SDA

N4

I2C5SCL

N3

I2C5SDA

H11

PM6/FAN0PWM0

L13

PM7/FAN0TACH0

C11

PK6/FAN0PWM1

A12

PK7/FAN0TACH1

G3

PN2/FAN0PWM2

D10

PN3/FAN0TACH2

L11

PN4/FAN0PWM3

N12

PN5/FAN0TACH3

N11

PN6/FAN0PWM4

M11

PN7/FAN0TACH4

J4

PH2/FAN0PWM5

J2

PH3/FAN0TACH5

C4

PECI0RX

C6

PECI0TX

M13

PP0/IRQ116

L12

PP1/IRQ117

M5

PP2/IRQ118

J12

PP3/IRQ119

J13

PP4/IRQ120

L5

PP5/IRQ121

D8

PP6/IRQ122

K6

PP7/IRQ123

D4

PQ0/IRQ124

E4

PQ1/IRQ125

F5

PQ2/IRQ126

N5

PQ3/IRQ127

N6

PQ4/IRQ128

K5

PQ5/IRQ129

M6

PQ6/IRQ130

L6

PQ7/IRQ131

L3

U0RX

M1

U0TX

E13

USB0DM

E12

USB0DP

LPC_AD<0>

14 62 67

BI

LPC_AD<1>

14 62 67

BI

LPC_AD<2>

14 62 67

BI

LPC_AD<3>

14 62 67

BI

LPC_CLK24M_SMC

17 67

IN

LPC_FRAME_L

14 62 67

IN

SMC_LRESET_L

18

IN

LPC_SERIRQ

15 62

BI

PM_CLKRUN_L

13 62

OUT

LPC_PWRDWN_L

13 62

IN

SMC_RUNTIME_SCI_L

13

OUT

SMC_WAKE_SCI_L

15

OUT

SMBUS_SMC_0_S0_SCL

38 58 71

BI

SMBUS_SMC_0_S0_SDA

38 58 71

BI

SMBUS_SMC_1_S0_SCL

14 32 38 41 42 62 67 71

BI

SMBUS_SMC_1_S0_SDA

14 32 38 41 42 62 67 71

BI

SMBUS_SMC_2_S3_SCL

38 59 63 71

BI

SMBUS_SMC_2_S3_SDA

38 59 63 71

BI

SMBUS_SMC_3_SCL

34 38 42 62 71

BI

SMBUS_SMC_3_SDA

34 38 42 62 71

C

B

BI

NC_SMBUS_SMC_4_ASF_SCL

62

BI

NC_SMBUS_SMC_4_ASF_SDA

62

BI

SMBUS_SMC_5_G3_SCL

38 46 48 62 71

BI

SMBUS_SMC_5_G3_SDA

38 46 48 62 71

BI

SMC_FAN_0_CTL

43

OUT

SMC_FAN_0_TACH

43

IN

NC_SMC_FAN_1_CTL

62

OUT

NC_SMC_FAN_1_TACH

62

IN

SMC_TOPBLK_SWP_L

37

OUT

SMC_SENSOR_PWR_EN

37 40 56

OUT

SMC_SYS_KBDLED

54

OUT

NC_SMC_T25_EN_L

62

OUT

TP_SMC_5VSW_PWR_EN

37

OUT

SYS_ONEWIRE

59 63

IN

NC_SMC_FAN_5_CTL

62

OUT

SMC_PCH_SUSACK_L

37

OUT

CPU_PECI_R

36

BI

SMC_PECI_L

36

OUT

SMC_BIL_BUTTON_L

36

IN

NC_SMC_DP_HPD_L

62

IN

SMC_PME_S4_WAKE_L

29 34 37

IN

SMC_PME_S4_DARK_L

25 36

IN

SMC_S4_WAKESRC_EN

36 57

OUT

SMC_SENSOR_ALERT_L

36 37

IN

SMC_LID

34 36 46 62

IN

SMC_PCH_SUSWARN_L

37

IN

SMS_INT_L

36

IN

SMC_BC_ACOK

36 48 59 63

IN

PM_SLP_S0_L

13 18

IN

PM_SLP_S3_L

13 17 18 57

IN

PM_SLP_S4_L

13 18 29 34 57

IN

PM_SLP_S5_L

13 57

IN

SMC_ONOFF_L

34 36 62

IN

SMC_RX_L

36 62

IN

SMC_TX_L

36 62

OUT

SMC_PWRFAIL_WARN_L

30 62

OUT

SMC_WIFI_PWR_EN

29 37

OUT

(OD)

(OD) (OD)

(OD)

(OD) (OD)

(OD)

(OD) (OD)

(OD)

D

C

B

NOTE: SMS Interrupt can be active high or low, rename net accordingly. If SMS interrupt is not used, pull up to SMC rail.

A

NOTE: Unused pins have "SMC_Pxx" names. Unused pins designed as outputs can be left floating, those designated as inputs require pull-ups.

6 3

SYNC_MASTER=WILL_J43 SYNC_DATE=12/17/2012

PAGE TITLE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SMC

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

50 OF 120

SHEET

35 OF 73

124578

SIZE

A

D

8 7 6 5 4 3

12

SMC Reset "Button", Supervisor & AVREF Supply

CPU_PROCHOT_L

6

35 49 65

35 36 48 59 63

BI

PLACE_NEAR=Q5159.6:5MM

PM_THRMTRIP_L

15 36 65

OUT

35 36

OUT

C5131

47PF

5%

25V

NP0-C0G-CERM

0201

CPU_THRMTRIP_3V3

1

2

CRITICAL

MMBT3904LP-7

6

1

3

4

Q5158

DFN1006-3

D

S G

D

S G

3

2

Q5159

DMN5L06VK-7

SOT563

VER 3

2

SMC_PROCHOT

Q5159

DMN5L06VK-7

SOT563

VER 3

5

SMC_THRMTRIP

1

PM_THRMTRIP_R_L

IN

R5158

3.3K

1/20W

201

35

35 36

5%

MF

35

From SMC

21

SMC_PECI_L

IN

PM_THRMTRIP_L

SMC12 PECI Support

DMN32D2LFB4

R5152

0

21

SMC_PECI_L_R

5%

1/20W

MF

0201

CPU_PECI_R

35

OUT

To SMC

15 36 65

IN

CRITICAL

Q5150

DFN1006H4-3

SYM_VER_2

NOSTUFF

1

R5153

1.6K

2

D

1

G S

5% 1/20W MF 201

NOSTUFF

1

C5134

47PF

5% 25V

2

NP0-C0G-CERM 0201

PLACE_NEAR=Q5150.2:5MM

PP1V05_S0

3

2

1

R5151

330

5% 1/20W MF 201

2

R5134

1/20W

56 57 60 62 6 8

11 15 16

17 36 40 49 53

D

43

21

CPU_PECI

5%

MF

201

From/To CPU/PCH

6

BI

65

C

GND_SMC_AVSS

PP3V42_G3H

17 30 33 34 35 36 38 44 46 47 48 57 59 60 62 63

OMIT

1

R5116

0

5% 1/10W MF-LF

603

2

R5127

0

5% 1/16W MF-LF

402

C5101

SMC_ONOFF_L

OMIT

1

R5115

0

5% 1/10W MF-LF 603

2

SILK_PART=PWR_BTN

21

0.01UF

X5R-CERM

0201

PLACE_SIDE=TOP

NOSTUFF

1

C5127

4.7UF

20%

6.3V

2

X5R 402

C5120

0.47UF

CERM-X5R

10% 10V

PP3V42_G3H_SMC_SPVSR

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.1 mm VOLTAGE=3.42V

1

10%

6.3V 2

402

6

MR1*

7

MR2*

4

DELAY

1

2

OUT

1

V+

U5110

VREF-3.3V-VDET-3.0V

DFN

(IPU)

SN0903049

(IPU)

CRITICAL

GND

2

34 35 36 62

VIN

THRM

PAD

3

RESET*

REFOUT

9

5

8

C5125

10UF

X5R-CERM

0402-1

1

R5100

100K

5% 1/20W MF 201

2

SMC_RESET_L

PP3V3_S5_AVREF_SMC

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.1 mm VOLTAGE=3.3V

1

C5126

0.01UF

2

10% 10V

2

X5R-CERM 0201

GND_SMC_AVSS

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.1 mm VOLTAGE=0V

20% 10V

OUT

35

35 36 39 40 41

35 44 48 62

SMC_BC_ACOK

35 36 48 59 63

SMC_BC_ACOK

MAKE_BASE=TRUE

59 60 62 38 44 46

PP3V42_G3H

17 30 33 34 35 36 47 48 57 63

35 36 39 40 41

D

Desktops: 5V Mobiles: 3.42V

SMC_LSOC_RST_L

34 62

IN

SMC_ONOFF_L

34 35 36 62

IN

SMC_MANUAL_RST_L

OMIT

1

R5101

0

5% 1/10W MF-LF 603

2

SILK_PART=SMC_RST

PLACE_SIDE=BOTTOM

MR1* and MR2* must both be low to cause manual reset. Used on mobiles to support SMC reset via keyboard. NOTE: Internal pull-ups are to VIN, not V+.

Debug Power "Buttons"

PLACE_SIDE=BOTTOM

C

SILK_PART=PWR_BTN

PP3V42_G3H

17 30 33 34 35 36 38 44 46 47 48 57 59 60 62 63

SMC Crystal Circuit

SMC USB Clock require these crystal values:5,6,8,10,12,16,18,20,24,25 MHz

SMC_PME_S4_DARK_L

25 35 36

R5110

2.49K

1/20W

21

1%

MF

201

1

2

SMC_XTAL_R

12.000MHZ-30PPM-10PF-85C

C5110

12PF

5% 25V NP0-C0G-CERM 0201

CRITICAL

Y5110

3.2X2.5MM-SM

NCNC

31

42

1

C5111

12PF

5% 25V

2

NP0-C0G-CERM 0201

25 35 36

13 67

IN

SMC_PME_S4_DARK_L

MAKE_BASE=TRUE

PM_CLK32K_SUSCLK_R

PLACE_NEAR=U0500.AE6:5.1mm

R5112

22

SMC_PME_S4_DARK_L

21

SMC_CLK32K

5%

1/20W

25 35 36

IN

PP1V05_S0

6 8

11 15 16 17 36 40 49 53

56 57 60 62

35 67

201

MF

OUT

SMC_VCCIO_CPU_DIV2

35

1

R5197

100K

1% 1/20W MF 201

2

1

R5196

100K

1% 1/20W MF 201

2

SMC_ONOFF_L

34 35 36 62

SMC_SENSOR_ALERT_L

35 37

SMC_LID

34 35 46 62

SMC_TX_L

35 62

SMC_RX_L

35 62

SMC_DEBUGPRT_TX_L

33 35 66

SMC_DEBUGPRT_RX_L

33 35 66

SMC_TMS

35 44 62

SMC_TDO

35 62

SMC_TDI

35 62

SMC_TCK

35 44 62

SMC_BIL_BUTTON_L

35

SMC_BC_ACOK

35 36 48 59 63

SMC_S5_PWRGD_VIN

35

SMS_INT_L

35

MEM_EVENT_L

35

CPU_THRMTRIP_3V3

35 36

SMC_PM_G2_EN

35 52 57

SMC_ADAPTER_EN

13 35

SMC_THRMTRIP

35 36

SMC_DELAYED_PWRGD

17 26 27 35

SMC_S4_WAKESRC_EN

35 57

SMC_XTAL

35

SMC_EXTAL

35

B

Module has 3.3K PU

WIFI_EVENT_L

29 35 62

A

SYNC_MASTER=WILL_J43

PAGE TITLE

R5167

R5170 R5172 R5171 R5173 R5174 R5175 R5176 R5177 R5178 R5179 R5180 R5181 R5187 R5192 R5193

R5114 R5117

R5198 R5185 R5186

R5191 R5190

R5189

11 12 13 15 17 18 26 30 34

SMC Shared Support

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

6 3

60 62 63 72

PP3V3_S0

8 37 38 39 40 41 42 43 54 57 59

100K

10K 10K

100K

10K

100K

20K 20K 10K 10K 10K 10K

10K 100K 100K

10K

10K 100K

100K 100K

10K

100K

10K

PP3V3_S4

25 26 27 29 34 37 56 60 62

NO STUFF

21

21 21

21

21 21

21

21 21

21

21 21

21

PP3V3_WLAN

29 35 37 39 62

21

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5% 5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201 201

MF

201

MF

201

MF

201

MF

201

MF

SYNC_DATE=12/17/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

51 OF 120

SHEET

36 OF 73

124578

SIZE

B

A

D

8 7 6 5 4 3

12

SMC_HS_COMPUTING_ISENSE

35 37 39

SMC_PBUS_VSENSE

35 37 40

SMC_BMON_ISENSE

35 37 39

SMC_DCIN_ISENSE

35 37 39

SMC_DCIN_VSENSE

35 37 40

SMC_BMON_DISCRETE_ISENSE

35 37 41

SMC_CPU_ISENSE

35 37 40

SMC_OTHER_HI_ISENSE

D

35 37 39

SMC_PANEL_ISENSE

35 37 41

SMC_1V2S3_ISENSE

35 37 39

SMC_LCDBKLT_ISENSE

35 37 39

SMC_P3V3S5_ISENSE

35 37 40

SMC_WLAN_ISENSE

35 37 39

SMC_SSD_ISENSE

35 37 39

SMC_P3V3S0_ISENSE

35 37 39

SMC_CAMERA_ISENSE

35 37 39

NC_SMC_ADC16

SMC_P1V05S0_VSENSE

35 37 40

SMC_CPUDDR_ISENSE

35 37 40

SMC_P1V05S0_ISENSE

35 37 40

SMC_CPU_VSENSE

35 37 40

SMC_CPUVR_ADJUST_ISENSE

35 37 41

SMC_CPU_IMON_ISENSE

35 37 41

PP3V3_WLAN

29 35 36 37 39 62

C

SMC_SENSOR_PWR_EN

35 37 40 56

MAKE_BASE=TRUE

SMC_WIFI_PWR_EN

29 35 37 29 35 37

MAKE_BASE=TRUE

TP_SMC_5VSW_PWR_EN TP_SMC_5VSW_PWR_EN

35 37 35 37

MAKE_BASE=TRUE

SMC_PCH_SUSWARN_L

35 13

IN

MAKE_BASE=TRUE

Top-Block Swap

62 63 72 8

11 12 13 15 17 18 26 30 34 36

38 39 40 41 42 43 54 57 59 60

15 35

OUT

SMC_PCH_SUSACK_L

OUT

MAKE_BASE=TRUE

SMC_TOPBLK_SWP_L

IN

R5296

1/20W

1K

201

5%

MF

PP3V3_S0

1

2

R5283

1K

5%

1/20W

MF

201

21

PCH_STRP_TOPBLK_SWP_L

SMC_HS_COMPUTING_ISENSE

MAKE_BASE=TRUE

SMC_PBUS_VSENSE

MAKE_BASE=TRUE

SMC_BMON_ISENSE

MAKE_BASE=TRUE

SMC_DCIN_ISENSE

MAKE_BASE=TRUE

SMC_DCIN_VSENSE

MAKE_BASE=TRUE

SMC_BMON_DISCRETE_ISENSE

MAKE_BASE=TRUE

SMC_CPU_ISENSE

MAKE_BASE=TRUE

SMC_OTHER_HI_ISENSE

MAKE_BASE=TRUE

SMC_PANEL_ISENSE

MAKE_BASE=TRUE

SMC_1V2S3_ISENSE

MAKE_BASE=TRUE

SMC_LCDBKLT_ISENSE

MAKE_BASE=TRUE

SMC_P3V3S5_ISENSE

MAKE_BASE=TRUE

SMC_WLAN_ISENSE

MAKE_BASE=TRUE

SMC_SSD_ISENSE

MAKE_BASE=TRUE

SMC_P3V3S0_ISENSE

MAKE_BASE=TRUE

SMC_CAMERA_ISENSE

MAKE_BASE=TRUE

SD alias on page 103

35 63

OUT

SMC_P1V05S0_VSENSE

MAKE_BASE=TRUE

SMC_CPUDDR_ISENSE

MAKE_BASE=TRUE

SMC_P1V05S0_ISENSE

MAKE_BASE=TRUE

SMC_CPU_VSENSE

MAKE_BASE=TRUE

SMC_CPUVR_ADJUST_ISENSE

MAKE_BASE=TRUE

SMC_CPU_IMON_ISENSE

MAKE_BASE=TRUE

PP3V3_WLAN

MAKE_BASE=TRUE

SMC_SENSOR_PWR_EN SMC_SENSOR_PWR_EN

SMC_WIFI_PWR_EN

R5230

0

21

PCH_SUSWARN_L

5%

1/20W

MF

0201

R5231

0

21

PCH_SUSACK_L

5%

1/20W

MF

0201

35 37 40 56

35 37 39

35 37 40

35 37 39

35 37 40

35 37 41

35 37 40

35 37 39

35 37 41

35 37 39

35 37 40

35 37 39

35 37 40

35 37 41

29 35 36 37 39 62

OUT

13 35

IN

D

C

SIZE

B

A

D

B

R5216

100

21

R5213

R5214

21

R5212

1/20W

100

1/20W

100

1/20W

100

1/20W

21

5%

MF

201

21

5%

MF

201

21

5%

MF

201

21

5%

MF

201

SMC_SENSOR_ALERT_L

SYNC_MASTER=J43_MLB

PAGE TITLE

SMC Project Support

Apple Inc.

35 36

OUT

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

R

SYNC_DATE=02/20/2013

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

52 OF 120

SHEET

37 OF 73

124578

PP3V3_S4

25 26 27 29 34 36 37 56 60 62

SMC_WIFI_PWR_EN

29 35 37

SMC_SENSOR_PWR_EN

35 37 40 56

R5295

R5294

10K

21

NOSTUFF

5%

NOSTUFF

5%

1/20W

MF

201

MF

201

A

29 34 35

IN

37 29 34 35

IN

37

SMC_PME_S4_WAKE_L SMC_PME_S4_WAKE_L

PP3V3_S4

1

R5282

100K

5% 1/20W MF 201

2

SMC_PME_S4_WAKE_L

MAKE_BASE=TRUE

25 26 27 29 34 36 37 56 60 62

29 34 35 37

OUT

SMC_HS_COMP_ALERT_L

41

IN

PCH_SML1ALERT_L

14 18

IN

SMC_BMON_COMP_ALERT_L

41

IN

FINSTACKSNS_ALERT_L

59 63

IN

CPUTHMSNS_ALERT_L

42

IN

CPUBMONSNS_ALERT_L

42

IN

TBTMLBSNS_ALERT_L

42

IN

NOSTUFF

R5215

100

1/20W

201

R5210

100

1/20W

201

NOSTUFF

R5211

5%

MF

5%

MF

100

1/20W

5%

MF

201

6 3

8 7 6 5 4 3

12

LYNX POINT LP S0 SMBus "0" Connections

59 60 62 63 72

PP3V3_S0

8

11 12 13 15 17 18 26 30 34

36 37 38 39 40 41 42 43 54 57

1

1/20W

R5301

1K

5%

1/20W MF

MF

201

2

LCD BACKLIGHT

(Write: 0x58 Read: 0X59)

U7701

SMBUS_PCH_CLK

SMBUS_PCH_DATA

14 16 19 38 54 67

35 38 58 71

SMBUS_SMC_0_S0_SCL

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SDA

MAKE_BASE=TRUE

SMC

U5000

(MASTER)

LYNX POINT LP

U0500

(MASTER)

SMBUS_PCH_CLK

14 16 19 38 54 67

D

MAKE_BASE=TRUE

SMBUS_PCH_DATA

14 16 19 38 54 67

MAKE_BASE=TRUE

R5300

SMC "0" SMBus S0 Connections

Pullups are on eDP connector page and gated by EDP_PANEL_PWR

Internal DP

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_0_S0_SDA

J8300

(See Table)

35 38 58 71

SMBUS_SMC_5_G3_SCL

35 38 46 48 62 71

MAKE_BASE=TRUE

SMBUS_SMC_5_G3_SDA

35 38 46 48 62 71

MAKE_BASE=TRUE

SMC

U5000

(MASTER)

17 30 33 34 35 36 44 46 47 48 57 59 60 62 63

PP3V42_G3H

VRef DACs

U2200

(Write: 0x98 Read: 0x99)

SMBUS_PCH_CLK

14 16 19 38 54 67

SMBUS_PCH_DATA

14 16 19 38 54 67

Margin Control

U2201

(Write: 0x30 Read: 0x31)

SMBUS_PCH_CLK

14 16 19 38 54 67

SMBUS_PCH_DATA

14 16 19 38 54 67

SMBUS_PCH_CLK

14 16 19 38 54 67

SMBUS_PCH_DATA

14 16 19 38 54 67

XDP Connectors

J1800

(MASTER)

C

SMBUS_PCH_CLK

SMBUS_PCH_DATA

TBT

U2800

(Write: 0xFE Read: 0XFF)

14 16 19 38 54 67

Internal DP

Analogix T-con - (Write: 0x7B/0x87 Read: 0x7C/0x88) N Y * Y *

Parade T-con - (0x10-0x1F or 0x30-0x3F) Y N * N *

DVR - (Write: 0x4E Read: 0x4F) Y Y Y Y N

J43 J41

Samsung LGD Samsung LGD AUO

SMC "2" SMBus S3 Connections

PP3V3_S3

15 18 19 34 39 56 60 62 63

SMC

U5000

(MASTER)

SMBUS_SMC_2_S3_SCL

35 38 59 63

71

MAKE_BASE=TRUE

SMBUS_SMC_2_S3_SDA

35 38 59 63 71

MAKE_BASE=TRUE

R5370

1/20W

(* = Multiple options)

1

R5371

1K

5%

5% 1/20W

MF

201

2

LIO Finstack Temp

(Write: 0x92 Read 0x93)

SMBUS_SMC_2_S3_SCL

SMBUS_SMC_2_S3_SDA

J9500

35 38 59 63 71

Battery

Battery Manager - (Write: 0x16 Read: 0x17)

SMC

U5000

(MASTER)

SMBUS_SMC_3_SCL

34 35 38 42 62 71

MAKE_BASE=TRUE

SMBUS_SMC_3_SDA

34 35 38 42 62 71

MAKE_BASE=TRUE

59 60 62 63 72

PP3V3_S0

8

11 12 13 15 17 18 26 30 34

36 37 38 39 40 41 42 43 54 57

SMC "5" SMBus G3H Connections

1

R5380

2.0K

5%

1/20W

MF

201

2

SMC "3" SMBus S0 Connections

1

R5390

2.0K

5%

1/20W

MF

201

2

1

R5381

2.0K

5% 1/20W MF 201

2

1

R5391

2.0K

5% 1/20W MF 201

2

SMBUS_SMC_5_G3_SCL

SMBUS_SMC_5_G3_SDA

SMBUS_SMC_5_G3_SCL

SMBUS_SMC_5_G3_SDA

(Write: 0x90 Read: 0x91)

SMBUS_SMC_3_SCL

SMBUS_SMC_3_SDA

TBT & MLBBOT, TBD Temp

SMBUS_SMC_3_SCL

SMBUS_SMC_3_SDA

Battery Charger

ISL6259 - U7100

(Write: 0x12 Read: 0x13)

Battery

J6950

(See Table)

Trackpad

J4800

EMC1414: U5810

(Write: 0x98 Read: 0x99)

35 38 46 48 62 71

34 35 38 42 62 71

D

C

B

A

LYNX POINT LP

SML_PCH_0_CLK

14 67

MAKE_BASE=TRUE

SML_PCH_0_DATA

14 67

MAKE_BASE=TRUE

LYNX POINT LP

(Write: 0x88 Read: 0x89)

67 71

SMBUS_SMC_1_S0_SCL

14 32 35 38

41 42 62

71

SMBUS_SMC_1_S0_SDA

14 32 35 38 41 42 62 67

SMLink 1 is slave port to

access PCH

U0500

(MASTER)

U0500

LYNX POINT LP S0 "SMLink 0" Connections

59 60 62 63 72

PP3V3_S0

8

11 12 13 15 17 18 26 30 34

36 37 38 39 40 41 42 43 54 57

R5310

8.2K

1/20W

201

LYNX POINT LP S0 "SMLink 1" Connections

B

SMC S0 "1" SMBus Connections

SMC

U5000

(MASTER)

59 60 62 63 72

PP3V3_S0

8

11 12 13 15 17 18 26 30 34

36 37 38 39 40 41 42 43 54 57

1

R5360

2.0K

1/20W

R5361

2.0K

5%

1/20W MF

MF

201

2

CPU Temp, Inlet, DDR, BMON THR

EMC1704-02: U5800

(Write: 0x98 Read: 0x99)

SMBUS_SMC_1_S0_SCL

SMBUS_SMC_1_S0_SDA

14 32 35 38 41 42 62 67 71

Chipset current

PAC1921: U5620

(Write: 0x30 Read: 0x31)

SMBUS_SMC_1_S0_SCL

SMBUS_SMC_1_S0_SDA

(Write: 0x72 Read 0x73)

SMBUS_SMC_1_S0_SCL

SMBUS_SMC_1_S0_SDA

ALS

J4002

62 67 71 14 32 35 38 41 42

SYNC_MASTER=J43_MLB

PAGE TITLE

SMBus Connections

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=09/28/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

53 OF 120

SHEET

38 OF 73

SIZE

A

D

124578

1

R5311

8.2K

5%

5% 1/20W

MF

MF 201

2

71

SMBUS_SMC_1_S0_SCL

14 32 35 38 41 42 62 67

MAKE_BASE=TRUE

71

SMBUS_SMC_1_S0_SDA

14 32 35 38 41 42 62 67

MAKE_BASE=TRUE

6 3

8 7 6 5 4 3

12

EDP Current :12A

MAX Vdiff : 24 mV

GAIN : 100X

D

EDP Current :10.75A

MAX Vdiff : 53.75 mV

GAIN : 50X

52 60

OUT

62

48 54 27 39

IN

40 47 60 62

C

EDP Current :1.02A

MAX Vdiff : 3.06 mV

GAIN : 1000X

EDP Current : 0.82A

MAX Vdiff : 16.36 mV

GAIN : 200X

39

PP3V3_S3RS0_CAMERA

15 31

B

39

PP3V3_S3RS0_CAMERA

15 31

39

PP3V3_S3RS0_CAMERA

15 31

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

PP3V3_S0

63 38 56 15 18 19 34 60 62

A

IC0R : COMPUTING High Side Current Sense

60 62

PPBUS_S5_HS_COMPUTING_ISNS

49 50 51 53

48 54

PPBUS_G3H

27 39 40 47 60 62

APN: 107S0137

IO0R : OTHER High Side Current Sense

PP3V3_S4SW_SNS

39 40 41 56 60

PPBUS_S5_HS_OTHER_ISNS

OMIT

R5430

0.003

0612-SHORT

1% 1w

CYN

PPBUS_G3H

IR0C : 3.3V S0 FET Current Sense

72 38 39 40 41 42 43

PP3V3_S0

8

11 12 13 15 17

18 26 30 34 36 37 54 57 59 60 62 63

PP3V3_S0_FET_R

56

0612-SHORT

0.003

R5440

OMIT

CYN

IS2C : 3.3V Camera Current Sense

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V MAKE_BASE=TRUE

PP3V3_S3

PP3V3_S3RS0_CAMERA_R

VOLTAGE=3.3V

R5421

0

5% 1/16W MF-LF

402

NOSTUFF

R5423

1/16W MF-LF

0612-SHORT

21

0

21

5%

402

CHARGER BMON High Side Current Sense

CHGR_BMON SMC_BMON_ISENSE

IN

QTY

107S0248 CRITICAL

ISL6259 Gain: 36x

Scale: 2.78A / V

Max VOut: 3.3V at 9.167A

EDP Current: 310A

48

PART NUMBER

CRITICAL

R5450

1

1w 1%

1

0.020

R5420

OMIT

1

59 60 62 63 72 8

11 12 13 15 17 18 26 30 34

36 37 38 39 40 41 42 43 54 57

72

1

ISNS_HS_COMPUTING_N

41

1% 1W

41 72

MF

0612

432

ISNS_HS_OTHER_N

72

ISNS_HS_OTHER_P

72

PP3V3_S4SW_SNS

39 40 41 56 60

ISNS_P3V3_S0_N

72

ISNS_P3V3_S0_P

72

PP3V3_S4SW_SNS

432

ISNS_CAMERA_N

72

ISNS_CAMERA_P

72

1

PLACE_NEAR=U5000.A4:11MM

R5422

300K

1%

1/20W

MF 201

ISNS_HS_COMPUTING_P

PLACE_NEAR=R5430:5mm

432

0.5%

0.002

432

39 40 41 56 60

MF 1w

DESCRIPTION

RES,SENSE,0.003OHM,1W,4-TERM,1%,0612,TFT

PP3V3_S0

OTHER_HS_ISNS:YES

PLACE_NEAR=R5440:5mm

3V3S0_ISNS:YES

PLACE_NEAR=R8061:5mm

CAM_ISNS:YES

21

PLACE_NEAR=U5000.A4:11MM

1

C5422

3300PF

10% 10V

2

X7R-CERM 0201

GND_SMC_AVSS

5

IN-

4

5

IN-

4

5

IN-

4

CPU_HS_ISNS:YES

1

CPU_HS_ISNS:YES

5

4

3

V+

U5430

INA213

SC70

OUT

CRITICAL

(50V/V)

GND

2

3

V+

U5440

INA212

SC70

OUT

CRITICAL

(1000V/V)

GND

2

3

V+

U5420

INA210

SC70

OUT

CRITICAL

(200V/V)

GND

2

3

V+

U5450

INA214

SC70

IN-

IN+ REF

REFIN+

CRITICAL

(100V/V)

GND

2

1

C5430

2

6

1

C5440

2

6

ISNS_P3V3_S0_IOUT

1

C5420

2

6

ISNS_CAMERA_IOUT

1

OUT

OTHER_HS_ISNS:YES

0.1UF

10%

6.3V CERM-X5R 0201

HS_OTHER_IOUT

3V3S0_ISNS:YES

0.1UF

10%

6.3V CERM-X5R 0201

R5441

0.1UF

10%

6.3V CERM-X5R 0201

R5424

CAM_ISNS:YES

C5450

0.1UF

10%

6.3V

2

CERM-X5R 0201

6

ISNS_HS_COMPUTING_IOUT

41

1

R5451

1

R5432

20K

5%

1/20W

MF

201

2

1

20K

5%

1/20W

PLACEMENT_NOTEs:

MF

201

2

Place close to SMC

Place close to SMC (For R and C)

1

20K

5%

PLACEMENT_NOTEs:

1/20W

MF

201

2

Place close to SMC

Place close to SMC (For R and C)

1

20K

5%

1/20W

MF

201

2

OTHER_HS_ISNS:YES

PLACE_NEAR=U5000.A4:11mm

R5433

4.53K

1%

1/20W

MF

201

PLACEMENT_NOTEs:

Place close to SMC

Place close to SMC (For R and C)

PLACE_NEAR=U5000.B1:11mm

3V3S0_ISNS:YES

PLACE_NEAR=U5000.B2:11mm

CAM_ISNS:YES

PLACEMENT_NOTEs:

Place close to SMC

(For R and C)

21

SMC_OTHER_HI_ISENSE

R5445

4.53K

21

1%

1/20W

MF

201

R5425

4.53K

21

1%

1/20W

MF

201

CPU_HS_ISNS:YES

PLACE_NEAR=U5000.E2:11mm

R5455

4.53K

1%

1/20W

MF

201

PLACE_NEAR=U5000.A4:11mm

1

C5433

0.22UF

20%

6.3V

2

X5R 0201

GND_SMC_AVSS

SMC_P3V3S0_ISENSE

3V3S0_ISNS:YES

1

PLACE_NEAR=U5000.B1:11mm

C5445

0.22UF

20%

6.3V

2

X5R 0201

GND_SMC_AVSS

SMC_CAMERA_ISENSE

CAM_ISNS:YES

1

C5425

0.22UF

PLACE_NEAR=U5000.B2:11mm

20%

6.3V

2

X5R 0201

GND_SMC_AVSS

21

DC-IN (AMON) Current Sense

PLACE_NEAR=U5000.B3:11MM

R5431

45.3K

35 37 35 37

OUT OUT

Sense R is R7120, 20mOhm

ISL6259 Gain: 20x

35 36 39 40 41

REFERENCE DES

Max VOut: 1.4V at 8.25A

Scale: 2.5A / V

EDP Current: 3.5A

CRITICAL

CHGR_AMON

48

IN

BOM OPTION

1%

1/20W

MF 201

21

SMC_DCIN_ISENSE

1

2

GND_SMC_AVSS

PLACE_NEAR=U5000.B3:11MM

C5431

2.2NF

10% 10V X5R-CERM 0201

R5480

6 3

SMC_HS_COMPUTING_ISENSE

PLACE_NEAR=U5000.E2:11mm

1

C5455

0.22UF

20%

6.3V

2

X5R 0201

GND_SMC_AVSS

OTHER_HS_ISNS:YES

OUT

35 36 39 40 41

CPU_HS_ISNS:YES

35 36 39 40 41

35 37

OUT

35 37

OUT

PART NUMBER

EDP Current : 7.57A

MAX Vdiff : 15.14 mV

GAIN : 200X

SENSE R : R7450 0.002R

35 37

OUT

IAPC :AirPort Current Sense

EDP Current : 1.00A

MAX Vdiff : 25 mV

GAIN : 100X

PP3V3_WLAN

29 35 36 37 62

PP3V3_WLAN_R

29

APN: 104S0024

ISDC : SSD Current Sense

EDP Current : 3.00A

MAX Vdiff : 15 mV

GAIN : 200X

PP3V3_S0SW_SSD

30 60 62

PP3V3_S0SW_SSD_FET_R

56

PPVIN_S0SW_LCDBKLT

39 54

PPVIN_S0SW_LCDBKLT

39 54

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=8.6V MAKE_BASE=TRUE

PPVIN_S0SW_LCDBKLT_FET

39 54

PPVIN_S0SW_LCDBKLT_FET

39 54

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=8.6V MAKE_BASE=TRUE

Replacing caps with 100K PD on ISENSE SMC inputs

DESCRIPTION

RES,MF,1/20W,100K OHM,5,0201,SMD

117S0008

QTY

1

OMIT_TABLE

EDP Current : 0.67A

MAX Vdiff : 0.06 mV

GAIN : 500X

IM3C :DDR 1V2 Current Sense (LPDDR + CPUDDR)

PP3V3_S4SW_SNS

39 40 41 56 60

PLACE_NEAR=R7450:5mm

51 72

CRITICAL

R5470

CRITICAL

R5480

DRAM_ISNS:YES

ISNS_1V2_S3_N ISNS_1V2_IOUT

IN

ISNS_1V2_S3_P

IN

PP3V3_S4SW_SNS

39 40 41 56 60

432

ISNS_AIRPORT_N

72

0.025

1% 1W

ISNS_AIRPORT_P

72

MTL

0612

1

PP3V3_S4SW_SNS

39 40 41 56 60

1

ISNS_SSD_N

72

0.003

1% 1W

ISNS_SSD_P

72

MF

0612

432

5

4

PLACE_NEAR=R5470:5mm

AIRPORT_ISNS:YES

PLACE_NEAR=R5480:5mm

SSD_ISNS:YES

3

V+

U5460

INA210

SC70

IN-

CRITICAL

(200V/V)

GND

2

U5470

INA214

5

IN-

CRITICAL

4

IN+ REF

U5480

INA210

5

IN-

CRITICAL

4

(200V/V)

SC70

(100V/V)

GND

3

V+

SC70

GND

2

OUT

REFIN+

3

V+

OUT

2

OUT

REFIN+

IBLC : LCD Backlight Driver Input Current Sense

PP3V3_S4SW_SNS

39 40 41 56 60

PLACE_NEAR=R5490:5mm

0612-SHORT

0.020

R5490

OMIT

432

MF 1w

0.5%

1

LCDBKLT_ISNS:YES

ISNS_LCDBKLT_N

72

ISNS_LCDBKLT_P

72

REFERENCE DES

C5455

C5465

C5475

C5485

C5495

C5433

C5425

C5445

5

4

CRITICAL

IN-

3

V+

U5490

INA211

SC70

CRITICAL

(500V/V)

GND

2

OUT

REFIN+

BOM OPTION

CPU_HS_ISNS:NO

AIRPORT_ISNS:NO

LCDBKLT_ISNS:NO

OTHER_HS_ISNS:NO

3V3S0_ISNS:NO

1

2

6

1

6

1

6

1

6

1

DRAM_ISNS:NO

SSD_ISNS:NO

CAM_ISNS:NO

DRAM_ISNS:YES

C5460

0.1UF

10%

6.3V CERM-X5R 0201

1

R5461

20K

5%

1/20W

MF

201

2

AIRPORT_ISNS:YES

1

C5470

0.1UF

10%

6.3V

2

CERM-X5R 0201

ISNS_P5VWLAN_IOUT

R5471

20K

1/20W

SSD_ISNS:YES

1

C5480

0.1UF

10%

6.3V

2

CERM-X5R 0201

ISNS_P5VSSD_IOUT

R5481

20K

1/20W

201

LCDBKLT_ISNS:YES

1

C5490

0.1UF

10%

6.3V

2

CERM-X5R 0201

ISNS_LCDBKLT_IOUT

R5491

20K

1/20W

201

DRAM_ISNS:YES

PLACE_NEAR=U5000.A5:11mm

R5465

4.53K

21

SMC_1V2S3_ISENSE

PLACE_NEAR=U5000.A5:11mm

1

C5465

0.22UF

20%

6.3V

2

X5R 0201

GND_SMC_AVSS

PLACE_NEAR=U5000.C1:11mm

AIRPORT_ISNS:YES

R5475

4.53K

21

1%

1/20W

MF

201

SSD_ISNS:YES

R5485

4.53K

21

1%

1/20W

1

MF

201

2

PLACE_NEAR=U5000.B6:11mm

LCDBKLT_ISNS:YES

R5495

4.53K

21

1%

1/20W

1

MF

201

2

1

2

PLACEMENT_NOTEs:

Place close to SMC

Place close to SMC (For R and C)

1

5%

PLACEMENT_NOTEs:

MF

201

2

Place close to SMC

Place close to SMC (For R and C)

1

PLACEMENT_NOTEs:

5%

MF

Place close to SMC

2

(For R and C)

1

5%

PLACEMENT_NOTEs:

MF

2

Place close to SMC

Place close to SMC (For R and C)

SYNC_MASTER=SID_J41

PAGE TITLE

1%

1/20W

MF

201

PLACE_NEAR=U5000.C2:11mm

High Side Current Sensing

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

DRAM_ISNS:YES

SMC_WLAN_ISENSE

AIRPORT_ISNS:YES

C5475

0.22UF

PLACE_NEAR=U5000.C1:11mm

20%

6.3V X5R 0201

GND_SMC_AVSS

SMC_SSD_ISENSE

SSD_ISNS:YES

C5485

0.22UF

PLACE_NEAR=U5000.C2:11mm

20%

6.3V X5R 0201

GND_SMC_AVSS

SMC_LCDBKLT_ISENSE

LCDBKLT_ISNS:YES

C5495

0.22UF

PLACE_NEAR=U5000.B6:11mm

20%

6.3V X5R 0201

GND_SMC_AVSS

OUT

35 36 39 40 41

SYNC_DATE=02/26/2013

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

54 OF 120

SHEET

39 OF 73

124578

35 37

OUT

35 37

SIZE

D

C

B

A

D

C

B

A

56

SMC_SENSOR_PWR_EN

35

IN

37

PPBUS_G3H

27 39 47 48 54 60 62

Enables DC-In VSense

divider when SUS present.

PM_SLP_SUS_L

13

IN

57

60

PPDCIN_G3H_ISOL

47 48 62

62 8

10

50 60

62 36 49 53

PP1V05_S0

6 8

11

15 16 17 56 57 60

EDP Current : 1A

MAX Vdiff : 5.65 mV

GAIN : 500X

8 7 6 5 4 3

VP0R: PBUS Voltage Sense Enable & Filter

Q5500

NTUD3169CZ

SOT-963

N-CHANNEL

6

PBUSVSENS_EN_L

D

G

2

1

S

3

PBUS_S0_VSENSE

D

G

R5501

100K

1/20W

1

1%

MF

201

2

5

4

PBUSVSENS_EN_L_DIV

S

P-CHANNEL

PLACE_NEAR=U5000.A3:11MM

VD0R: DC-In Voltage Sense Enable & Filter

Q5510

NTUD3169CZ

SOT-963

2

1

N-CHANNEL

G

6

D

DCINVSENS_EN_L

R5512

S

3

DCIN_S5_VSENSE

D

G

R5511

100K

1/20W

1

1%

MF

201

2

5

4

PDCINVSENS_EN_L_DIV

S

P-CHANNEL

PLACE_NEAR=U5000.F1:11MM

CPU Vcore Voltage Sense / Filter

XW5520

SM

21

PLACE_NEAR=R7310.2:5 MM

PLACE_NEAR=U5000.B7:11MM

CPUVSENSE_INPPVCC_S0_CPU

R5520

4.53K

1%

1/20W

MF

201

21

1.05V Voltage Sense / Filter

XW5530

SM

21

PLACE_NEAR=R7640.2:5 MM

PLACE_NEAR=U5000.G1:11MM

P1V05VSENSE_IN

R5530

4.53K

1%

1/20W

MF

201

21

IC1C: 1.05V S0 CURRENT SENSE / FILTER

PP3V3_S4SW_SNS

53 72

IN

39 40 41 56 60

PLACE_NEAR=R7640.4:5MM

ISNS_1V05_S0_N

ISNS_1V05_S0_P

PLACE_NEAR=R7640.3:5MM

PLACE_NEAR=R7640:5mm

P1V05_ISNS:YES

3

V+

U5560

INA211

5

SC70

IN-

CRITICAL

4

(500V/V)

GND

2

OUT

6

1

REFIN+

1

R5502

100K

1%

1/20W

Max VOut: 3.3V at 19.77V Input

MF

201

2

R5503

R5504

1

100K

1%

1/20W

Max VOut: 3.3V at 19.77V Input

MF

201

2

R5513

27.4K

1/20W

R5514

5.49K

1/20W

SMC_CPU_VSENSE

PLACE_NEAR=U5000.B7:11MM

1

C5520

0.22UF

20%

6.3V

2

X5R 0201

GND_SMC_AVSS

SMC_P1V05S0_VSENSE

PLACE_NEAR=U5000.G1:11MM

1

C5530

0.22UF

20%

6.3V

2

X5R 0201

GND_SMC_AVSS

P1V05_ISNS:YES

1

C5560

0.1UF

10%

6.3V

2

CERM-X5R 0201

P1V05S0_IOUT

1

R5562

20K

5%

1/20W

MF

201

2

1

27.4K

1%

1/20W

MF

201

2

1

5.49K

1%

1/20W

MF

201

2

1

1%

MF

PLACE_NEAR=U5000.B3:11MM

RTHEVENIN = 4573 Ohms

201

2

1

1%

MF

201

2

OUT

PLACE_NEAR=U5000.E1:11MM RTHEVENIN = 4573 Ohms

SMC_PBUS_VSENSE

PLACE_NEAR=U5000.E1:11MM

1

C5504

0.22UF

20%

6.3V

2

X5R 0201

GND_SMC_AVSS

SMC_DCIN_VSENSE

PLACE_NEAR=U5000.B3:11MM

1

C5514

0.22UF

20%

6.3V

2

X5R 0201

GND_SMC_AVSS

35 37

35 36 39 40 41

OUT

35 36 39 40 41

PLACE_NEAR=U5000.H2:11MM

P1V05_ISNS:YES

R5561

4.53K

21

1%

1/20W

MF

201

35 36 39 40 41

35 37

SMC_P1V05S0_ISENSE

P1V05_ISNS:YES

1

C5561

0.22UF

20%

6.3V

2

X5R 0201

GND_SMC_AVSS

35 37

OUT

35 36 39 40 41

35 37

OUT

PLACE_NEAR=U5000.H2:11MM

50 72

IN

50 72

IN

50 72

IN

50 72

IN

35 37

OUT

35 36 39 40 41

CPUVR_ISNS1_P

CPUVR_ISNS2_P

CPUVR_ISNS1_N

CPUVR_ISNS2_N

CPUVR_ISNS:YES

PLACE_NEAR=R7310.3:5MM

CPUVR_ISNS:YES

PLACE_NEAR=R7320.3:5MM

CPUVR_ISNS:YES

PLACE_NEAR=R7310.3:5MM

CPUVR_ISNS:YES

PLACE_NEAR=R7320.3:5MM

EDP Current : 3.00A

MAX Vdiff : 12.60 mV

GAIN : 200X

EDP Current : 3.00A

MAX Vdiff : 30.00 mV

GAIN : 100X

PP3V3_S5

8

11 13 15 16 17 18 28 29 52

55 56 57 58 60 62 72

PP3V3_S5_REG_R

40 52

PP3V3_S5_REG_R

40 52 35 36 39 40 41

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V MAKE_BASE=TRUE

ICS0 : CPU VCore Load Side Current Sense

60 62 63 72

PP3V3_S0

8

11 12 13 15 17 18 26 30 34

36 37 38 39 41 42 43 54 57 59

CPUVR_ISNS:YES

R5540

4.42K

1% 1/16W MF-LF

402

R5541

4.42K

1% 1/16W MF-LF

402

CPUVR_ISNS1_P_R

41 72

21

R5544

1.43K

1% 1/16W MF-LF

402

21

72

CPUVR_ISNS:YES

R5542

4.42K

1% 1/16W MF-LF

402

R5543

4.42K

1/16W

MF-LF

402

21

CPUVR_ISNS1_N_R

41 72

21

1%

R5545

1.43K

1% 1/16W MF-LF

402

21

72

1

R5546

1M

1% 1/16W MF-LF 402

2

IM0C : CPU DDR Current Sense

PP3V3_S4SW_SNS

1w 1%

432

72

1

39 40 41 56 60

ISNS_CPUDDR_N

ISNS_CPUDDR_P

PPVMEMIO_S0_CPU

8

10 40

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.1 MM VOLTAGE=1.2V MAKE_BASE=TRUE

PPVMEMIO_S0_CPU

8

10 40

PP1V2_S3

17 19 20 21 22 23 51 60 68

0612-SHORT

0.003

R5570

OMIT

CYN

IR5C :3.3 S5 REG Current Sense

PP3V3_S4SW_SNS

39 40 41 56 60

OMIT

1

ISNS_P3V3S5_N

72

0.003

1% 1w

ISNS_P3V3S5_P

72

CYN

432

DESCRIPTION

RES,MF,1/20W,100K OHM,5,0201,SMD

PART NUMBER

117S0008

R5590

0612-SHORT

Replacing caps with 100K PD on ISENSE SMC inputs

QTY

1

CPUVR_ISUM_R_P

CPUVR_ISUM_R_N

CPUVR_ISNS:YES

PLACE_NEAR=R5570:5mm

CPUDDR_ISNS:YES

PLACE_NEAR=R5590:5mm

P3V3S5_ISNS:YES

REFERENCE DES

5

4

5

4

6 3

CPUVR_ISNS:YES

NO_XNET_CONNECTION=TRUE

3

V+

U5570

INA210

SC70

IN-

CRITICAL

IN+ REF

(200V/V)

GND

2

3

V+

U5590

INA214

SC70

(100V/V)

GND

2

OUT

REFIN+

OUT

C5541

C5561

C5595

C5575

1

+

V+

V-

3

-

R5547

1M

21

1% 1/16W MF-LF

402

6

1

6

1

CRITICAL

CPUVR_ISNS:YES

CRITICAL

U5540

OPA333DCKG4

5

SC70-5

4

2

CPUDDR_ISNS:YES

1

C5570

0.1UF

10%

6.3V

2

CERM-X5R 0201

ISNS_CPUDDR_IOUT

R5571

20K

1/20W

P3V3S5_ISNS:YES

1

C5590

0.1UF

10%

6.3V

2

CERM-X5R 0201

ISNS_P3V3S5_IOUT

R5591

20K

1/20W

CPUVR_ISUM_IOUT

1

5%

MF

201

2

PLACEMENT_NOTEs:

Place close to SMC

(For R and C)

1

5%

MF

201

2

PLACEMENT_NOTEs:

Place close to SMC

(For R and C)

BOM OPTION

CPUVR_ISNS:NO

P1V05_ISNS:NO

P3V3S5_ISNS:NO

CPUDDR_ISNS:NO

PLACE_NEAR=U5540.5:3MM

CPUVR_ISNS:YES

1

C5540

0.1UF

10%

6.3V

2

CERM-X5R 0201

Sense R is R7310, R7320

Sense R is 0.75mOhm each, combined 0.375mOhm

EDP: 32A TDP :28.05A

CPUVR_ISNS:YES

PLACE_NEAR=U5000.B4:11MM

R5548

4.53K

1%

1/20W

MF

201

PLACE_NEAR=U5000.H1:11mm

CPUDDR_ISNS:YES

R5575

4.53K

21

1%

1/20W

MF

201

PLACE_NEAR=U5000.A6:11mm

P3V3S5_ISNS:YES

R5595

4.53K

21

1%

1/20W

MF

201

21

SMC_CPUDDR_ISENSE

1

C5575

0.22UF

20%

6.3V

2

X5R 0201

GND_SMC_AVSS

SMC_P3V3S5_ISENSE

1

C5595

0.22UF

20%

6.3V

2

X5R 0201

SMC_CPU_ISENSE

CPUVR_ISNS:YES

PLACE_NEAR=U5000.B4:11MM

1

C5541

0.22UF

20%

6.3V

2

X5R 0201

GND_SMC_AVSS

CPUDDR_ISNS:YES

PLACE_NEAR=U5000.H1:11mm

P3V3S5_ISNS:YES

PLACE_NEAR=U5000.A6:11mm

35 36 39 40 41

GND_SMC_AVSS

SYNC_MASTER=SID_J41

PAGE TITLE

Voltage & Load Side Current Sensing

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

12

Gain:274.72x

35 37

OUT

35 37

OUT

35 37

OUT

SYNC_DATE=02/26/2013

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

55 OF 120

SHEET

40 OF 73

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

39 40 41 56 60

R5821: ADDR - 0x56/0x57 (r/w)

D

ILDC :LCD Panel Current Sense / Filter

PP3V3_S0SW_LCD

41 58

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V MAKE_BASE=TRUE

PP3V3_S0SW_LCD

41 58

C

PP3V3_S0SW_LCD_R

41 58

PP3V3_S0SW_LCD_R

41 58

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V MAKE_BASE=TRUE

72 59 60 42 43 38 39 30 34 15 17

PP3V3_S0

8

11

12 13 18 26 36 37 40 41 54 57 62 63

B

A

39

IN

PART NUMBER

117S0008

ICS3 : Adjustable Gain CPU VR Current

R5620

100

21

PP3V3_S4SW_SNS

CPUVRSNS_ADDR_SEL

1

R5621

4.3K

5%

1/20W

MF

201

2

CPUVR_ISNS1_P_R

40 72

IN

CPUVR_ISNS1_N_R

40 72

IN

PLACE_NEAR=U5540.1:5MM

PP3V3_S4SW_SNS

39 40 41 56 60

OMIT

1

ISNS_PANEL_N

0.5% 1w MF

72

ISNS_PANEL_P

72

432

EDP Current: 0.750 A

Max Vdiff: 15 mV

R5670

0.020

0612-SHORT

Discrete High side Current threshold

1

R5614

294K

1% 1/16W MF-LF 402

2

HS_COMP_VREF

1

R5615

49.9K

1% 1/16W MF-LF 402

2

NOSTUFF

1

R5617

0

5% 1/20W MF 0201

2

HS_IOUT_D

NOSTUFF

A

D5617

SM-201

RB521ZS-30

K

ISNS_HS_COMPUTING_IOUT

Replacing caps with 100K PD on ISENSE SMC inputs

QTY

1

DESCRIPTION

RES,MF,1/20W,100K OHM,5,0201,SMD

PP3V3_SNS_CPUVR_ADJUST_ISNS

1% 1/16W MF-LF

402

BYPASS=U5620.1:5:3MM

6

ADDR_SEL/GAIN_SEL

2

SENSE+

3

SENSE-

PLACE_NEAR=R5470:5mm

PANEL_ISNS:YES

5

IN-

CRITICAL

4

BYPASS=U5601:3MM

1

C5613

0.1UF

10%

6.3V

2

CERM-X5R 0201

R5616

10.2K

21

1% 1/16W MF-LF

402

HS_IOUT_R

1

R5610

0

5% 1/20W MF 0201

2

1

C5620

1.0UF

20%

6.3V

2

X5R 0201-1

U5620

PAC1921-1-AIA

GND

5

3

V+

U5670

INA210

SC70

OUT

REFIN+

(200V/V)

GND

2

3

4

NOSTUFF

1

C5610

0.1UF

10% 25V

2

X5R 402

REFERENCE DES

C5675

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm VOLTAGE=3.3V

1

VDD

DFN

SM_CLK/INT_SEL

SM_DATA/OUT_SEL

EPAD

11

1

C5670

0.1UF

10%

6.3V

2

CERM-X5R 0201

6

ISNS_PANEL_IOUT

1

HS_COMP_FB

U5611

5

MCP6541T SC70-5

1

2

READ*/INT

COMM_SEL

PANEL_ISNS:YES

R5671

4

OUT

8

10 9

7

1

20K

5%

Gain: 200x

1/20W

MF

Scale: 0.25A / V

201

2

MAX VOUT: 3V AT 0.825A PLACEMENT_NOTEs:

Place close to SMC

(For R and C)

HS_COMP_OUT

CRITICAL

Sense Pins gain stage for U5800 (EMC1704)

R5660

59 60 62 63 72

PP3V3_S0

8

11 12 13 15 17 18 26 30 34

36 37 38 39 40 41 42 43 54 57

0

21

5%

1/20W

MF

0201

PU: SMBus mode

SMC_CPUVR_ADJUST_ISENSE_R

SMC_CPU_DBGPWR_RD_L SMBUS_SMC_1_S0_SCL

SMBUS_SMC_1_S0_SDA

35

IN

14 32 35

BI

38 42 62 67 71 14 32 35 38 42 62 67 71

BI

PLACE_NEAR=U5000.A7:5MM

R5625

0

21

SMC_CPUVR_ADJUST_ISENSE

5%

1/20W

MF

0201

1

C5625

0.22UF

20%

6.3V

2

X5R 0201

NO STUFF

PLACE_NEAR=U5000.A7:5MM

GND_SMC_AVSS

35 37

OUT

CKPLUS_WAIVE=NdifPr_badTerm

39 41 72

IN

CKPLUS_WAIVE=NdifPr_badTerm

39 41 72

IN

35 36 39 40 41

ISNS_HS_COMPUTING_P

ISNS_HS_COMPUTING_N

PLACE_NEAR=R7150:5MM

5

4

IN-

U5660

INA211

SC70

CRITICAL

(500V/V)

GND

3

V+

6

OUT

1

REFIN+

2

GAIN: 500X

In battery discharge scenario negative voltage will be present on IN+/- pins with INA output voltage decreasing from 3.3V with increasing discharge current.

PLACE_NEAR=U5000.C1:11mm

PANEL_ISNS:YES

R5675

4.53K

21

NO STUFF

C5611

0.22UF

21

20%

6.3V X5R

0201

R5619

255K

21

1% 1/16W MF-LF

402

BOM OPTION

PANEL_ISNS:NO

1%

1/20W

MF

201

SMC_PANEL_ISENSE

PANEL_ISNS:YES

1

C5675

0.22UF

20%

PLACE_NEAR=U5000.C1:11mm

6.3V

2

X5R 0201

GND_SMC_AVSS

35 36 39 40 41

SMC_HS_COMP_ALERT_L

3

U5612

DMN32D2LFB4

DFN1006H4-3

SYM_VER_2

D

1

G S

2

CHGR_CSO_R_P/N are swapped on purpose to measure power into the system

35 37

OUT

59 60 62 63 72

PP3V3_S0

8

11 12 13 15 17 18 26 30 34

36 37 38 39 40 41 42 43 54 57

Gain: 50x Scale: 2A / V Max VOut: 3.3V at 6.6A

CKPLUS_WAIVE=NdifPr_badTerm

CHGR_CSO_R_P

48 71

IN

CHGR_CSO_R_N

48 71

IN

CKPLUS_WAIVE=NdifPr_badTerm

BMON : Discrete BMON Current Sense / Filter

BYPASS=U5601:3MM

1

C5603

0.1UF

10%

6.3V

2

CERM-X5R 0201

1

OUT

REFIN+

R5604

100K

1% 1/16W MF-LF 402

2

BMON_COMP_VREF

1

R5605

100K

1% 1/16W MF-LF 402

2

NOSTUFF

1

R5607

0

5% 1/20W MF 0201

2

BMON_IOUT_D

NOSTUFF

RB521ZS-30

6

BMON_IOUT

1

R5601

D5607

SM-201

20K

5%

1/20W

MF

201

1

2

A

K

R5606

10.2K

1% 1/16W MF-LF

402

BMON_IOUT_R

1

R5600

0

5% 1/20W MF 0201

2

PLACE_NEAR=U5000.A3:5MM

R5608

4.53K

1/20W

37

OUT

BYPASS=U5600:3MM

C5606

0.1UF

CERM-X5R

(50V/V)

1

10%

6.3V 2

0201

3

V+

U5600

INA213

5

SC70

IN-

CRITICAL

4

GND

2

6 3

1%

MF

201

PLACE_NEAR=U5660.3:5MM

1

C5660

0.1UF

10%

6.3V

2

CERM-X5R 0201

ISNS_HS_GAIN_OUT

R5663

20K

5%

1/20W

MF

201

49

IN

3

21

4

NOSTUFF

1

C5600

0.1UF

10% 25V

2

X5R 402

21

SMC_BMON_DISCRETE_ISENSE

PLACE_NEAR=U5000.A3:5MM

1

C5602

0.22UF

20%

6.3V

2

X5R 0201

GND_SMC_AVSS

1

2

CPUVR_IMON

5

2

ISNS_HS_GAIN_P_R

1

R5662

1K

1%

1/20W

MF

201

2

1

R5661

27K

1%

R5665

0

21

ISNS_HS_GAIN_OUT_R

5%

1/20W

MF

0201

With 100mA battery current, Will have 10.2mV difference going into sense pins of U5800. This will set the minumum current threshold at 0.100mA

NO STUFF

1

C5665

0.22UF

20%

6.3V

2

X5R 0201

1/20W

MF

201

2

VR IMON Current Sense Filter

PLACE_NEAR=U5000.B8:5MM

R5641

0

21

1/20W

0201

5%

MF

NO STUFF

PLACE_NEAR=U5000.B8:5MM

1

C5641

2.2NF

10% 10V

2

X5R-CERM 0201

GND_SMC_AVSS

Vref = 0.406mV Vth = 0.442 = 1A from Battery Vtl = 0.290mv = 0.687A from battery

Hysteresis TBD based on RC value changes

NO STUFF

C5601

0.22UF

21

20%

6.3V X5R

0201

R5609

200K

BMON_COMP_FB

U5601

MCP6541T SC70-5

1

41 39 35 36 40

21

1% 1/16W MF-LF

402

BMON_COMP_OUT

SYNC_MASTER=SID_J41

PAGE TITLE

35 37

OUT

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

72

ISNS_HS_COMPUTING_P

39

IN

41

ISNS_HS_GAIN_N_R

72

ISNS_HS_COMPUTING_N

39

IN

41

SMC_CPU_IMON_ISENSE

35 36 39 40 41

U5602

DMN32D2LFB4

DFN1006H4-3

SYM_VER_2

1

G S

Debug Sensors 1

Apple Inc.

R

R5666

0

21

ISNS_HS_GAIN_P

5%

1/20W

MF

0201

R5668

0

21

ISNS_HS_GAIN_N

5%

1/20W

MF

0201

NO STUFF

SMC_BMON_COMP_ALERT_L

3

D

2

NO STUFF

R5667

R5669

0

5%

1/20W

MF

0201

1/20W

0

21

5%

MF

0201

21

35 37

OUT

SYNC_DATE=02/26/2013

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

56 OF 120

SHEET

41 OF 73

124578

42 72

OUT

D

42 72

OUT

C

37

OUT

B

A

SIZE

D

8 7 6 5 4 3

12

CPU Proximity, Inlet ,DDR and BMON THR Sensor

VOLTAGE=3.3V

21

C5801

2200PF

X7R-CERM

1

10% 10V

2

0201

MIN_NECK_WIDTH=0.25 mm MIN_LINE_WIDTH=0.25 mm

PP3V3_S0_CPUTHMSNS_R

1

2

C5800

0.1UF

10%

6.3V CERM-X5R 0201

16

15

13 14

2

3

4

5

DP1

DN1

DP2/DN3

DN2/DP3

SENSE+ SENSE-

DUR_SEL TH_SEL

GND

1

CRITICAL

VDD

U5800

EMC1704-2

QFN

ADDR_SEL

THRM_PAD

8

THERM*

ALERT*

SMDATA

SMCLK

GPIO

17

NOSTUFF

1

R5802

100K

5% 1/20W MF 201

2

9

CPUBMONSNS_ALERT_L

10

CPUTHMSNS_ALERT_L

11

SMBUS_SMC_1_S0_SDA

12

SMBUS_SMC_1_S0_SCL

6

CPUTHMSNS_ADDR_SEL

7

NC

Placement note:

Place U5800 under CPU

Write Address: 0x98 Read Address: 0x99

1

R5806

100K

5% 1/20W MF 201

2

37

OUT

37

OUT

14 32 35 38 41 62 67 71

BI

14 32 35 38 41 62 67 71

BI

1

R5805

0

2

5% 1/20W MF 0201

D

R5800

1/20W

10K

5%

MF

201

1

2

47

5%

1/20W

MF

201

CPUTHMSNS_DUR_SEL

CPUTHMSNS_TH_SEL

59 60 62 63 72

PP3V3_S0

8

11 12 13 15 17 18 26 30 34

36 37 38 39 40 41 42 43 54 57

INLET_THMSNS_D1_P

C5802

2200PF

X7R-CERM

10% 10V

0201

NOSTUFF

72

NO_XNET_CONNECTION=TRUE

PLACE_NEAR=U5800.2:5mm

PLACE_NEAR=U5800.3:5mm

INLET_THMSNS_D1_N

72

CPUTHMSNS_D2_P

72

PLACE_NEAR=U5800.4:5mm

1

2

PLACE_NEAR=U5800.5:5mm

CPUTHMSNS_D2_N

72

ISNS_HS_GAIN_P

ISNS_HS_GAIN_N

1

R5803

10K

NOSTUFF

5%

1/20W

MF

201

2

R5804

D

Placement note:

Place Q5810 next to DDR/5V/3.3V supply on TOP side

PLACE_NEAR=Q5810:3MM

1

C5811

47PF

5% 25V

2

NP0-C0G-CERM 0201

Placement note:

Place Q5830 between near rear vent on bottom side

Q5810

BC846BLP

DFN1006H4-3

3

1

2

3

Q5830

BC846BLP

DFN1006H4-3

Detect DDR/5V/3.3V Proximity Temperature

1

2

PLACE_NEAR=Q5830:3MM

1

C5830

47PF

5% 25V

2

NP0-C0G-CERM 0201

C5860

NP0-C0G-CERM

PLACE_NEAR=Q5860:3MM

47PF

NO_XNET_CONNECTION=TRUE

1

5%

25V

2

0201

2

1

Q5860

DFN1006H4-3

BC846BLP

3

41 72

OUT

41 72

OUT

SIZE

C

B

A

D

C

B

Q5820

BC846BLP

DFN1006H4-3

Q5840

BC846BLP

DFN1006H4-3

A

Q5850

BC846BLP

DFN1006H4-3

TBT,MLB Bottom Proximity Sensors

R5840

0

21

3

2

3

2

3

2

42 72

72

1

2

72

1

2

1

2

TBDTHMSNS_D2_N

TBT_MLBBOT_THMSNS_P

TBT_MLBBOT_THMSNS_N

TBTTHMSNS_D2_R_P

PLACE_NEAR=Q5820:3MM

C5820

47PF

5% 25V NP0-C0G-CERM 0201

TBTTHMSNS_D2_R_N

TBT_MLBBOT_THMSNS_N

PLACE_NEAR=Q5840:3MM

C5840

47PF

5% 25V NP0-C0G-CERM 0201

TBT_MLBBOT_THMSNS_P

TBDTHMSNS_D2_P

PLACE_NEAR=Q5850:3MM

C5850

47PF

5% 25V NP0-C0G-CERM 0201

42 72

TBT_MLBBOT_THMSNS_P

MAKE_BASE=TRUE

TBT_MLBBOT_THMSNS_N

MAKE_BASE=TRUE

5%

1/20W

MF

0201

R5841

5%

1/20W

MF

0201

0

21

42 72

TBT_MLBBOT_THMSNS_P

TBT_MLBBOT_THMSNS_N

42 72

Placement note:

Place Q5820 close to TBT on TOP side

Placement note:

Place Q5840 on MLB bottom side opposite U5810

Placement note:

TBD

TBT_MLBBOT_THMSNS_P

TBT_MLBBOT_THMSNS_N

42 72

59 60 62 63 72

PP3V3_S0

8

11 12 13 15 17 18 26 30 34

36 37 38 39 40 41 42 43 54 57

BI

TBDTHMSNS_D2_P

TBDTHMSNS_D2_N

TBT_MLBBOT_THMSNS_P

TBT_MLBBOT_THMSNS_N

42 72

TBT, MLBBOT and TBD Temp Sensor

R5810

47

21

PP3V3_S0_TBTMLB_ISNS_R

MIN_LINE_WIDTH=0.5 mm

5%

MIN_NECK_WIDTH=0.20 mm

1/20W

VOLTAGE=3.3V

MF

201

NO_XNET_CONNECTION=TRUE

PLACE_NEAR=U5810.4:5mm

PLACE_NEAR=U5810.5:5mm

C5813

2200PF

X7R-CERM

1

10% 10V

2

0201

1

C5812

2200PF

10% 10V

2

X7R-CERM

0201

2

DP1

3 8

DN1

4

DP2/DN3

5

DN2/DP3

EMC1414-1-AIZL

6 3

U5810

CRITICAL

1

VDD

MSOP

THERM*/ADDR

GND

6

1

2

7

TBT_INLET_THM_L

ALERT*

9

SMDATA

10

SMCLK

Write Address: 0x39 Read Address: 0x38

C5810

0.1UF

10%

6.3V CERM-X5R 0201

TBTMLBSNS_ALERT_L

SMBUS_SMC_3_SDA

SMBUS_SMC_3_SCL

R5811

1/20W

1

22K

5%

MF

201

2

37

OUT

34 35 38 62 71

BI

34 35 38 62 71

BI

SYNC_MASTER=J43_MLB

PAGE TITLE

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

Thermal Sensors

Apple Inc.

SYNC_DATE=02/20/2013

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

58 OF 120

SHEET

42 OF 73

124578

8 7 6 5 4 3

12

D

FAN CONNECTOR

R6010

0

21

5%

1/20W

MF

0201

NOSTUFF

CRITICAL

74LVC1G08

6

SOT891

PP3V3_S0_FAN

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.1 MM

C

VOLTAGE=3.3V

4

U6010

2

08

1

NC

53

PP3V3_S0

1

2

PP5V_S0

NOSTUFF

C6010

0.1UF

10%

6.3V CERM-X5R 0201

BYPASS=U6010:3mm

62 63 72 8

11 12 13 15 17 18 26 30 34 36

37 38 39 40 41 42 54 57 59 60

16 17 32 49 50 54 56 57 59 60 62

D

C

NC

518S0793

1

R6060

47K

5%

1/20W

R6065

47K

1

2

5%

1/20W

MF

201

S G

21

FAN_RT_TACH

62

Q6060

DMN32D2LFB4

DFN1006H4-3

SYM_VER_3

D

3

FAN_RT_PWM

62

SMC_FAN_0_TACH

35

OUT

R6061

1

100K

5%

1/20W

MF

201

2

SMC_FAN_0_CTL

35

B

IN

MF

2

201

CRITICAL

J6000

FF14A-4C-R11DL-B-3H

F-RT-SM 5

NC

1

5V DC

2

TACH

3

MOTOR CONTROL

4

GND

6

NC

B

A

6 3

SYNC_MASTER=J43_MLB

PAGE TITLE

Fan

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=09/13/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

60 OF 120

SHEET

43 OF 73

124578

SIZE

A

D

8 7 6 5 4 3

SPI ROM

Quad-IO Mode (Mode 0 & 3) supported. SPI Frequency: 50MHz for CPU, 20MHz for SMC.

PP3V3_SUS

8

11 14 18 55 56 57 60 62

BYPASS=U6101::3mm

OE*

1

2

7

PLACE_NEAR=U6100.1:12MM

1

C6101

0.1UF

10% 16V X5R-CERM 0201

44 67

SPI_MLBROM_CS_L

44 67

BYPASS=U6100::3mm

SPI_MLB_CLK

SPI_MLB_IO2_WP_L SPI_MLB_IO3_HOLD_L

C6100

0.1UF

X5R-CERM

0201

8

1

10% 16V

2

6

CLK

1

CS*

3

WP*(IO2)

7

HOLD*(IO3)

CRITICAL

VCC

U6100

W25Q64FVZPIG

64MBIT

WSON

OMIT_TABLE

IO2

IO3

THRM_PAD

GND

4

9

DI(IO0)

DO(IO1)

IO0

IO1

5

SPI_MLB_IO0_MOSI

2

SPI_MLB_IO1_MISO

PP3V42_G3H

17 30 33 34 35 36 38 46 47 48 57 59 60 62 63

35 36 48 62

SPI_ALT_IO0_MOSI

44 62

SPI_ALT_IO1_MISO

44 62

SPI_ALT_IO2_WP_L

44 62

SPI_ALT_IO3_HOLD_L

44 62

SMC_RESET_L

44

D

8

VCC

U6101

74LVC1G99

2

SOT833

A Y

SPI_MLB_CS_L

44 67

SPIROM_USE_MLB

15 44 62

Quad SPI and QPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set. When QE=1, the /WP pin becomes IO2 and /HOLD pin becomes IO3.

3

B

CRITICAL

5

C

6

D

GND

4

NOTE: If HOLD* is asserted ROM will ignore SPI cycles in normal and Dual-IO modes.

SPI+SWD SAM Connector

SAMCONN

CRITICAL

J6100

DF40PC-12DP-0.4V-51

M-ST-SM

14 13

2

1

4 3

6 5

8 7

9

10

12 11

16

15

SPI_ALT_CLK SPI_ALT_CS_L

SPIROM_USE_MLB SMC_TMS SMC_TCK

(SWDIO) (SWCLK)

44 62

OUTOUT

15 44 62

BI

35 36 62

BI

35 36 62

12

D

SPI Bus Series Termination

SIZE

C

B

A

D

C

PLACE_NEAR=J6100.10:5mm

SAMCONN

1

R6133

43

5% 1/20W MF 201

2

R6110

15

21

SPI_CS0_R_L

14 67

IN

SPI_CLK_R

14 67

IN

PLACE_NEAR=U0500.AA3:5mm

CPU Master

SPI_MOSI_R

14 67

BI

SPI_MISO

14 67

B

BI

14 67

BI

14 67

BI

SPI_IO<2>

SPI_IO<3>

PLACE_NEAR=U0500.AA2:5mm

PLACE_NEAR=U0500.AF1:5mm

PLACE_NEAR=U0500.Y7:5mm

R6111

PLACE_NEAR=U0500.AA2:5mm

R6113

PLACE_NEAR=U0500.Y6:5mm

15

5%

1/20W

MF

201

15

5%

1/20W

MF

201

R6119

15

5%

1/20W

MF

201

21

R6112

21

5%

1/20W

MF

201

15

5%

1/20W

MF

201

R6118

15

5%

1/20W

MF

201

67

21

67

21

SPI_CS0_L

SPI_CLK

SPI_MOSI

SPI_MISO_R

SPI_IO2_R

67

SPI_IO3_R

67

SPI_SMC_MISO

35 67

OUT

SPI_SMC_MOSI

35 67

IN

SMC12 Master

SPI_SMC_CLK

35 67

IN

A

SPI_SMC_CS_L

35 67

IN

PLACE_NEAR=J6100.8:5mm

SAMCONN

1

R6132

43

5% 1/20W MF 201

2

R6114

24.9

1%

1/20W

MF

201

PLACE_NEAR=J6100.2:5mm

SAMCONN

1

R6128

24.9

1% 1/20W MF 201

2

R6123

24.9

21

PLACE_NEAR=U6100.2:5mm

1%

1/20W

MF

201

R6131

43

21

PLACE_NEAR=R6133.2:5mm

5%

1/20W

MF

201

21

PLACE_NEAR=U6100.2:1mm

R6115

15

5%

1/20W

MF

201

PLACE_NEAR=J6100.15:5mm

SAMCONN

1

R6127

43

5% 1/20W MF 201

2

R6122

43

21

PLACE_NEAR=R6127.2:5mm

5%

1/20W

MF

201

R6130

43

21

PLACE_NEAR=R6132.2:5mm

5%

1/20W

MF

201

21

PLACE_NEAR=U6100.5:1mm

R6116

15

5%

1/20W

MF

201

PLACE_NEAR=J6100.12:5mm

SAMCONN

1

R6126

43

5% 1/20W MF 201

2

R6121

43

21

5%

1/20W

MF

201

21

PLACE_NEAR=U6100.6:1mm

R6117

1/20W

6 3

SPI_ALT_IO3_HOLD_L SPI_ALT_IO2_WP_L

SPI_ALT_IO1_MISO SPI_ALT_IO0_MOSI

PLACE_NEAR=J6100.14:5mm

SAMCONN

1

R6125

43

5% 1/20W MF 201

2

R6120

43

5%

1/20W

MF

201

PLACE_NEAR=R6126.2:5mm

15

21

PLACE_NEAR=U6100.1:1mm

5% MF

201

SPI_ALT_CLK SPI_ALT_CS_L

21

PLACE_NEAR=R6125.2:5mm

44 62

SAM Card ROM Slave

44 62

SPI_MLB_CS_L

SPI_MLB_CLK

SPI_MLB_IO0_MOSI

SPI_MLB_IO1_MISO

SPI_MLB_IO2_WP_L

SPI_MLB_IO3_HOLD_L

BOM_COST_GROUP=CPU SUPPORT

44 67

OUT

44 67

OUT

MLB ROM Slave

44

BI

44

BI

44 67

BI

44 67

BI

SYNC_MASTER=YHARTANTO_J44

PAGE TITLE

SPI Debug Connector

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/09/2013

DRAWING NUMBER

<SCH_NUM>

REVISION

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61 OF 120

SHEET

44 OF 73

124578

8 7 6 5 4 3

SPEAKER AMPLIFIERS

APN:353S2888

12

SPEAKER LOWPASS

D

GAIN

80 HZ < FC < 132 HZ

6DB

D

Right Speaker Connector

ALIAS OF PP5VRT_S0, MIN_LINE_WIDTH=0.50MM, MIN_NECK_WIDTH=0.20MM

PP5V_S4RS3

32 33 47 52 53 56 60 62

OMIT_TABLE

CRITICAL

C6410

0.1UF

59 63 72

C

59 63

IN

SPKRAMP_INR_P

SPKRAMP_INR_N

SPKRAMP_SHDN_L

1

R6411

100K

5% 1/20W MF 201

2

OMIT_TABLE

CRITICAL

C6411

0.1UF

10% 16V

X5R-CERM

0201

21

10% 16V

X5R-CERM

0201

21

R6414

5% 1/10W MF-LF

603

0

21

MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.5 mm VOLTAGE=5V

PP5V_S3_U6210

1

C6407

0.1UF

10% 16V

2

X5R-CERM 0201

MAX98300_R_P

72 62 72

MAX98300_R_N

A1

PVDD

U6410

MAX98300

WLP

A3

IN+

CRITICAL

B3

IN-

C2

B2

NC

PGND

A2

OUT+ OUT-

GAINSHDN*

B1

C1

C3

NOSTUFF

R6413

100K

1/20W

R_AMP_GAIN

1

5%

MF

201

2

1

R6412

100K

2

CRITICAL

1

C6401

47UF

20%

6.3V

2

POLY-TANT 0805-LLP

5% 1/20W MF 201

MIN_NECK_WIDTH=0.20 mm MIN_LINE_WIDTH=0.30 mm

SPKRAMP_ROUT_P

SPKRAMP_ROUT_N

62 72 72

518S0519

CRITICAL

J6404

78171-0002

M-RT-SM

3

1

2

4

C

PART NUMBER

132S0460

QTY

2

DESCRIPTION

CAP,CER,X5R,0.1UF,10%,16V,0201,MURATA

B

A

6 3

REFERENCE DES

C6410,C6411

CRITICAL

BOM OPTION

SYNC_MASTER=J43_MLB

PAGE TITLE

Audio: Speaker Amp

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=09/04/2012

DRAWING NUMBER

<SCH_NUM>

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64 OF 120

SHEET

45 OF 73

124578

SIZE

B

A

D

8 7 6 5 4 3

12

Hall Effect Sensor

J6955

HALL-SENSOR-MLB-PADS-K99

PP3V42_G3H

17 30 33 34 35 36 38 44 47 48 57 59 60 62 63

SMC_LID_R

D

63

R6961

0

21

SMC_LID

5% 1/16W MF-LF

402

C6955

0.001UF

X7R-CERM

NC

10% 50V

0402

SM

8

7

6 5 4

OMIT_TABLE

1

2

OUT

1

2

3

NC

D

NC

34 35 36 62

11"-Specific

C

CRITICAL

J6950

BAT-K99

F-RT-TH

POS POS POS SCL SDA

SYS_DETECT

NEG NEG NEG

SHLD_PIN SHLD_PIN SHLD_PIN SHLD_PIN

Battery Connector

1

C6951

1UF

10% 16V

2

X5R

1 2

3

4 5

6 7

8

9

10 11

12

13

402

SMBUS_SMC_5_G3_SCL SMBUS_SMC_5_G3_SDA SYS_DETECT_L

62

R6950

PPVBAT_G3H_CONN

1

C6950

0.1UF

10% 25V

2

X5R 402

1

10K

5%

1/20W

MF

201

2

48 62

35 38 48 62 71

IN

35 38 48 62 71

BI

CRITICAL

2

1

3

NO STUFF

D6950

RCLAMP2402B

SC-75

C

518-0369

B

A

6 3

SYNC_MASTER=MASTER

PAGE TITLE

Battery Connector & Hall Effect

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

SHEET

124578

SYNC_DATE=MASTER

69 OF 120

46 OF 73

SIZE

A

D

8 7 6 5 4 3

12

MLB to LIO Power Cable Connector

CRITICAL

J7000

WTB-PWR-M82

M-RT-SM

1

2 3

D

4 5

6

518S0508

PP5V_S4RS3

1

C7006

0.1UF

10% 16V

2

X5R-CERM 0201

NO STUFF

CRITICAL

C7007

1UF

60 62 32 33 45 52 53 56

NO STUFF CRITICAL

1

C7008

1UF

1

10% 35V

2

10% 35V X5R 603

X5R 603

2

48 60 62

NO STUFF

C7005

0.1UF

603-1

PPDCIN_G3H

1

10% 50V

2

X7R

D

1

R7012

68K

1%

CRITICAL

Q7010

SI5419DU

POWERPAK

D

1

C

PPDCIN_G3H_ISOL

40 48 60 62

5A

S

5

CRITICAL

G

C7012

4

0.047UF

10% 25V X7R

0402

DCIN_ISOL_GATE_R

DCIN_ISOL_GATE

1

2

6.8V Zener

PPBUS_G3H

27 39 40 48 54 60 62

B

1/20W MF 201

2

R7011

10K

1%

1/20W

MF

201

R7005

10

5%

1/8W

MF-LF

805

CRITICAL

C7091

1

R7010

100K

2

21

K

A

R7006

21

PP18V5_DCIN_ISOL_R

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=18.5V

1UF

10% 25V X5R 402

Input impedance of 68K meets sparkitecture requirements for detection of B121 (16.5V)

5% 1/20W MF 201

CRITICAL

D7012

GDZT2R6.8

GDZ-0201

4.7

21

PPBUS_G3H_R

MIN_LINE_WIDTH=0.4 mm

5%

MIN_NECK_WIDTH=0.2 mm

1/8W

VOLTAGE=8.6V

MF-LF

805

1

2

CRITICAL

1

C7090

1UF

10% 25V

2

X5R 402

CRITICAL

D7005

BAT30CWFILM

SOT-323

1

2

CRITICAL

1

C7092

5.6UF

20% 25V

2

POLY-TANT CASE-B2-SM

3

PPVIN_G3H_P3V42G3H

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=18.5V

P3V42G3H_SHDN_L

1

R7080

0

5% 1/20W MF 0201

2

NO STUFF

1

R7081

49.9K

1% 1/20W MF 201

2

3.425V "G3Hot" Supply

Supply needs to guarantee 3.31V delivered to SMC VRef generator

3

6

BOOST

VIN

U7090

LT3470AED

DFN

NO STUFF

C7080

1000PF

CERM 0402

SHDN*

7

NC

1

5%

25V

2

CRITICAL

GND

5

BIAS

THRM

PAD

9

48

SW

2

1

FB

P3V42G3H_BOOST

DIDT=TRUE MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

P3V42G3H_SW

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE DIDT=TRUE

P3V42G3H_FB

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

C7094

0.22UF

10% 10V

CERM

402

1

2

1

2

10UH-20%-0.85A-0.46OHM

C7095

22PF

5% 50V NP0-C0G-CERM 0201

CRITICAL

L7095

2520

<Ra>

R7095

348K

1/20W

<Rb>

R7096

200K

1/20W

C

B

1

2

PP3V42_G3H

CRITICAL

1

C7098

10UF

20% 10V

2

X5R-CERM 0402-1

21

1

1%

MF

CRITICAL

201

2

C7099

10UF

20% 10V

X5R-CERM

0402-1

1

1%

MF

201

2

17 30 33 34 35 36 38 44 46 48 57 59 60 62 63

Vout = 3.425V 300mA Max Output (Switcher limit)

Vout = 1.25V * (1 + Ra / Rb)

A

SYNC_MASTER=J43_MLB

PAGE TITLE

DC-In & G3H Supply

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

6 3

SYNC_DATE=09/13/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

70 OF 120

SHEET

47 OF 73

124578

SIZE

A

D

8 7 6 5 4 3

Reverse-Current Protection

Inrush Limiter

1

R7185

FROM ADAPTER

PPDCIN_G3H

47 60 62

D

C7185

0.1UF

1

10% 25V

2

X5R 402

470K

1%

1/20W MF 201

2

CRITICAL

Q7180

IRF9395TRPBF

DIRECTFET-MC

CHGR_AGATE_DIV

1

R7186

332K

1%

1/20W

MF

3

201

2

48

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=18.5V

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm

PPCHGR_DCIN_D_R

PP5V5_DCIN:NO

PPDCIN_G3H_ISOL

40 47 60 62

CRITICAL

D7105

BAT30CWFILM

SOT-323

1

2

ACIN pin threshold is 3.2V, +/- 50mV

DIVIDER SETS ACIN THRESHOLD AT 13.55V

1

C

B

R7110

130K

1% 1/20W MF 201

2

1

R7111

46.4K

1% 1/20W MF 201

2

R7113

35 36 44 62

Float CELL for 1S

1

100

5%

1/20W

MF

201

2

SMC_RESET_L

IN

CHGR_ICOMP_R

1

C7142

0.1UF

10%

6.3V

2

CERM-X5R 0201

1

R7115

255K

1% 1/20W MF 201

2

CHGR_VCOMP_R

R7142

1/20W

CHGR_VNEG_R

1

C7116

470PF

10% 16V

2

X5R-X7R-CERM 0201

MIN_LINE_WIDTH=0.2 mm

1

1K

5%

MF

201

2

C7115

470PF

X5R-X7R-CERM

R7116

MIN_NECK_WIDTH=0.2 mm

10% 16V

0201

1

10K

1%

1/20W

MF

201

2

R7100

1/20W

1

2

0

5%

MF

0201

30mA max load

1

2

12

13 11

10

4

6

3

5 7

8 18 17

C7102

1UF

10% 10V X5R 402

R7101

VDD VHST SMB_RST_N SCL

SDA VFRQ CELL

ACIN

ICOMP VCOMP VNEG CSOP CSON

(AGND)

4.7

5% 1/16W MF-LF

402

19

CRITICAL

U7100

TQFN

THRM_PAD

29

PLACE_NEAR=U7100.22:1mm

21

20

VDDP

ISL6259

20V/V

36V/V

(OD)

22

XW7100

SM

48

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5.1V

SGATE AGATE

UGATE PHASE

LGATE

BGATE

PGND

PP5V1_CHGR_VDD

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm VOLTAGE=5.1V

PP3V42_G3H

17 30 33 34 35 36 38 44 46 47 57 59 60 62 63

NO STUFF

1

R7102

100K

5%

1/20W

MF

201

21

35 38 46 62 71

57

IN BI IN

CHGR_RST_L

SMBUS_SMC_5_G3_SCL SMBUS_SMC_5_G3_SDA

CHGR_VFRQ

CHGR_CELL

2

CHGR_ACIN

CHGR_ICOMP CHGR_VCOMP

71

1

2

CHGR_VNEG

CHGR_CSO_P CHGR_CSO_N

C7150

0.47UF

10% 10V X5R 0402

C7111

0.01UF

X5R-CERM

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

1

10% 10V

2

0201

1

2

C7100

1UF

10% 10V X5R 402-1

251

S

G

3

R7105

20

21

5% 1/10W MF-LF

603

PP5V1_CHGR_VDDP

2

DCIN

26

1 28

CSIP

27

CSIN

25

BOOT

24 23

21

16

9

AMON

15

BMON

14

ACOK

21

C7105

0.22UF

10% 50V

X5R-CERM

0603-1

NCNCNCNC

10

D

(CHGR_AGATE)

(CHGR_DCIN)

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

CHGR_DCIN

48

CHGR_SGATE

CHGR_AGATE

CHGR_CSI_P

71

CHGR_CSI_N

71

CHGR_BOOT

CHGR_UGATE

CHGR_PHASE

CHGR_LGATE

CHGR_BGATE CHGR_AMON

CHGR_BMON SMC_BC_ACOK

(GND)

(CHGR_CSO_P)

(CHGR_CSO_N)

(PPVBAT_G3H_CHGR_R)

1

2

GND_CHGR_AGND

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V

978

C7101

4

S

D

G

6

(CHGR_SGATE)

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

1

C7120

0.047UF

10% 16V

2

X7R-CERM 0402

1

1UF

10% 10V

2

X5R 402

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

39

OUT

39

OUT

35 36 59 63

OUT

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

C7126

1000PF

X7R-CERM

0201

10% 16V

DIDT=TRUE

GATE_NODE=TRUE

C7122

0.1UF

10% 25V X5R 402

GATE_NODE=TRUE

1

2

Need to stuff R7192 if either PP5V5_DCIN:YES or PP5V5_VDDP are used!

NO STUFF

MF-LF

CRITICAL

R7120

0.020

0.5% 1W MF-LF 0612

PPDCIN_G3H_CHGR

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.15 mm VOLTAGE=18.5V

Max Current = 8A

f = 400 kHz

MF

R7192

1/16W

NO STUFF

C7190

PPVBAT_G3H_CHGR_REG

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 MM VOLTAGE=8.6V

0201

PPDCIN_G3H_INRUSH

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=18.5V

1

R7180

100K

5%

1/20W

MF

201

2

CHGR_SGATE_DIV

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm

R7121

10

21

5%

1/20W

MF

201

R7122

10

21

5%

1/20W

MF

201

1

C7121

0.1UF

10% 25V

2

X5R 402

PLACE_NEAR=U7100.25:2mm

1

C7125

0.22UF

10% 10V

2

CERM 402

CHGR_CSI_R_P

71

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

CHGR_CSI_R_N

71

1

8

765

2.2

R7151

R7152

* R7151 HAS 2.2OHM TO COMPENSATE UNBALANCED VOLTAGE

DUE TO DIFFERENT CURRENT ON _P AND _N. (FROM INTERSIL)

0

9432

201

48

MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.5 mm

C7184

4.7UF

10% 25V

X5R-CERM

0603

1

R7181

62K

5% 1/20W MF 201

2

CRITICAL

Q7130

NTMFD4902NF

DFN

10

SWITCH_NODE=TRUE

DIDT=TRUE

21

41 71

5%

21

41 71

5%

(PPVBAT_G3H_CHGR_R)

(CHGR_BGATE)

PPCHGR_DCIN_D_R

1

2

4

321

MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.6 mm VOLTAGE=8.6V

CHGR_CSO_R_P

1/20W

CHGR_CSO_R_N

1/20W

MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.5 mm

21

40205%

4.7UF

10% 25V

X5R-CERM

0603

R7150

0.01

0.5% 1W MF

0612-4

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm

CHGR_DCIN_D

1

2

33UF-0.06OHM

CRITICAL

4.7UH-17A

PIMC104T4R7MN-SM

21 43

SHDN*

7

NC

CRITICAL

C7130

20% 25V

POLY-TANT

CASE-D3L

L7130

PPVBAT_G3H_CHGR_R

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 MM VOLTAGE=8.6V

5.5v "G3Hot" Supply

For Erp Lot6 spec

P5V1_BOOST

DIDT=TRUE

6

3

BOOST

VIN

NO STUFF

U7190

LT3470A

DFN

CRITICAL

GND

5

1

2

SW

BIAS

FB

THRM

PAD

9

CRITICAL

33UF-0.06OHM

48

2

1

C7131

POLY-TANT

CASE-D3L

P5V1_SW

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE DIDT=TRUE

P5V1_FB

1

20% 25V

2

NO STUFF

C7194

0.22UF

10% 10V

CERM

402

Vout = 1.25V * (1 + Ra / Rb)

1

C7135

1UF

10% 25V

2

X5R 603-1

1

2

1

2

1

2

C7195

22PF

5% 50V NP0-C0G-CERM

0201

C7136

1UF

10% 25V X5R 603-1

NO STUFF

CRITICAL

NO STUFF

L7195

10UH-20%-0.85A-0.46OHM

2520

NO STUFF

BYPASS=Q7130:1.5mm

1

C7137

0.001UF

10% 50V

2

X7R-CERM 0402

21

R7195

R7196

NO STUFF

CRITICAL

C7198

10UF

20% 10V X5R 603

1

2

1

<Ra>

1

681K

2

1%

1/20W

MF

201

2

<Rb>

1

200K

1%

1/20W

MF

201

2

NO STUFF

CRITICAL

C7199

10UF

20% 10V X5R 603

MF-LF

MF-LF05%

TO SYSTEM

CRITICAL

F7140

8AMP-24V

21

BYPASS=L7130:Q7130:1.5mm

C7140

62UF-0.023OHM

TANT-POLY

CASE-B2S

1

20% 11V

2

C7141

62UF-0.023OHM

TANT-POLY

CASE-B2S

1

C7143

62UF-0.023OHM 20% 11V

2

TANT-POLY

CASE-B2S

CRITICAL

Q7155

SI7137DP

SO-8

S

321

20% 11V

D

1

2

5

1

C7145

1000PF

10% 16V

2

X7R-CERM 0201

TO/FROM BATTERY

PPVBAT_G3H_CONN

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.15 mm VOLTAGE=8.6V

21

1206

46 62

PPBUS_G3H

G

4

C7117

10UF

1

C7114

1UF

10% 25V X5R 805

10% 25V

2

X5R 603-1

1

2

C7113

0.1UF

10% 25V X5R 402

1

2

C7112

0.01UF

10% 25V X7R 402

12

PP5V5_DCIN:YES

R7190

21

40205%

1/16W

PP5V5_VDDP

R7191

21

PP5V1_CHGR_VDDP

402

1/16W

PP5V5_CHGR_VDDP

MIN_NECK_WIDTH=0.25 mm MIN_LINE_WIDTH=0.5 mm VOLTAGE=5.5V

Vout = 5.50V 200MA MAX OUTPUT (Switcher limit)

CHGR_DCIN

48

27 39 40 47 54 60 62

D

C

B

A

6 3

SYNC_MASTER=J43_MLB

PAGE TITLE

PBus Supply & Battery Charger

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

.

SYNC_DATE=09/14/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

71 OF 120

SHEET

48 OF 73

124578

SIZE

A

D

8 7 6 5 4 3

12

D

PP5V_S0

62

R7220

6.04K

1% 1/20W MF 201

PLACE_NEAR=U7200.16:2mm

NO_XNET_CONNECTION=TRUE

R7235

9.31K

CPUVR_NTC_R

1

R7236

95.3K

1%

1/20W

MF

201

R7215

1%

1/20W

1

C7210

0.01UF

10% 10V

2

X7R-CERM 0201

R7243

845

1/20W

0201

2

21

201

MF

0

21

5%

MF

PP1V05_S0

6 8

11 15 16 17 36 40 53 56

57 60 62

1

1%

MF

2

C7214

220PF

X7R-CERM

C7213

CERM-X5R

10% 25V

201

0.1UF

1

R7280

130

1% 1/20W MF 201

2

PLACE_NEAR=U7200.30:2mm

1

2

1

10%

6.3V 2

0201

NO_XNET_CONNECTION=TRUE

1

C7278

0.1UF

PLACE_NEAR=R7279.32:2mm

8

65

C

BI

8

65

OUT

8

65

IN

50

IN

50

IN

50

IN

50

IN

10%

6.3V

CERM-X5R

0201

PLACE_NEAR=U7200.32:2mm

CPU_VIDSOUT CPU_VIDALERT_L CPU_VIDSCLK

CPUVR_ISUMP

NO_XNET_CONNECTION=TRUE

CPUVR_ISUMN

CPUVR_ISEN1 CPUVR_ISEN2

R7279

54.9

1/20W

2

201

B

CPU_VCCSENSE_P

8

65

IN

CPU_VCCSENSE_N

9

65

IN

1

2

CPUVR_ISUMN_RC

R7210

255

1/20W

1

C7211

0.01UF

10% 10V

2

X7R-CERM 0201

CPU_VCCSENSE_P_R

NO_XNET_CONNECTION=TRUE

1%

MF

201

C7242

100PF

2 1

NP0-CERM

R7237

100KOHM

0201

21

5%

25V

0201

NO_XNET_CONNECTION=TRUE

CPU_VCCSENSE_P_RC

NO_XNET_CONNECTION=TRUE

21

1%

1/20W

MF 201

1

R7223

16.9K

1% 1/20W MF 201

2

C7215

820PF

21

10% 25V

X7R-CERM

CPUVR_COMP_RC

XW7261

SM

21

0201

R7241

1.37K

1%

1/20W

MF

201

1

R7222

9.31K

1% 1/20W MF 201

2

C7240

1.2NF

+/-10%

0201-1

R7240

21

(GND)

10V

CERM

75K

1/20W

201

1%

MF

1

2

1

2

1

R7221

21K

1% 1/20W MF 201

2

C7216

5%

25V

C7241

NP0-C0G-CERM

R7242

1K

2 1

1%

1/20W

MF

201

47PF

21

0201

NP0-C0G-CERM

56PF

5%

25V

0201

1

2

1

2

NO_XNET_CONNECTION=TRUE

6

35 36 65

8

17

41

NOSTUFF

OUT

IN

OUT

R7250

2K

1%

1/20W

MF

201

R7201

1

21

PP5V_S0_CPUVR_VDD

5% 1/16W MF-LF

402

CPUVR_NTC

CPU_PROCHOT_L

CPUVR_SLOPE

CPUVR_PROG1 CPUVR_PROG2 CPUVR_PROG3

CPU_VR_EN

CPUVR_COMP

CPU_RTN

CPUVR_FB CPUVR_FB2

(CPUVR_ISUMP)

CPUVR_ISUMN_R

CPUVR_IMON

C7230

1800PF

X5R-CERM

21

CPUVR_FB_RC

1

2

1

10% 10V

2

201

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V

C7201

1UF

10% 10V X5R 402-1

1

2

R7230

95.3K

1% 1/20W MF 201

29

28

27

30

31 32

13

15 14

12

11

10

ISL95826HRZ-_R6200

5

NTC

4

VR_HOT*

SLOPE

PROG1 PROG2 PROG3

1

VR_ON

SDA ALERT* SCLK

CRITICAL

6

COMP

RTN

7

FB

8

FB2

ISUMP ISUMN

3

IMON

ISEN1 ISEN2 ISEN3

NOSTUFF

1

C7250

330PF

10% 16V

2

X7R-CERM 0201

PPVIN_S0_CPUVR_VIN

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=12.9V

17

16

VINVDD

U7200

LLP

PAD

THRM

33

FCCM

PWM3 PWM2 PWM1

DRSEL

PGOOD

NC NC NC NC

C7202

0.22UF

FCCM = 1: Forced CCM FCCM = 0: DCM FCCM = FLOATING: PS4

18

CPUVR_FCCM

23

NC

22

CPUVR_PWM2

2026

CPUVR_PWM1

25

CPUVR_DRSEL

2

CPU_VR_READY

9

NC

19

NC

21

NC

24

NC

10% 25V X7R

0402

R7202

1/16W

1

MF-LF

PLACE_NEAR=U7200.17:2mm

2

OUT

OUT OUT

OUT

10

21

PPBUS_S5_HS_COMPUTING_ISNS

5%

402

50

8

17

1

R7225

0

5% 1/20W MF 0201

2

NOSTUFF

R7224

0

5%

1/20W

MF

0201

39 50 51 53 60 62 16 17 32 43 50 54 56 57 59 60

21

D

C

B

1

C7260

330PF

10% 16V

2

X7R-CERM 0201

A

1

C7261

330PF

10% 16V

2

X7R-CERM 0201

6 3

SYNC_MASTER=J43_MLB

PAGE TITLE

CPU VR12.6 VCC Regulator IC

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=10/09/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

72 OF 120

SHEET

49 OF 73

124578

SIZE

A

D

8 7 6 5 4 3

PPBUS_S5_HS_COMPUTING_ISNS

39 49 51 53 60 62

CRITICAL

1

C7313

62UF-0.023OHM

20% 11V

2

TANT-POLY CASE-B2S

60 62

PP5V_S0

16 17 32 43 49 50 54 56 57 59

D

PHASE 1

CPUVR_PWM1

49

IN

CPUVR_FCCM

49 50

IN

C

16 17 32 43 49 50 54 56 57 59 60 62

PP5V_S0

3

7

353S3942

PHASE 2

CPUVR_PWM2

49

IN

CPUVR_FCCM

49 50

IN

3

7

353S3942

PWM

FCCM

PWM

FCCM

U7310

ISL6208D

CRITICAL

GND

4

U7320

ISL6208D

CRITICAL

GND

4

6

VCC

DFN

THRM

PAD

9

6

VCC

DFN

THRM

PAD

9

B

X6S-CERM

BOOT

UGATE

PHASE

LGATE

C7320

X6S-CERM

BOOT

UGATE

PHASE

LGATE

C7310

1UF

10% 16V

0402

1UF

10% 16V

0402

1

2

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

2

1

8

5

1

2

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

2

1

8

5

CPUVR_UGATE1

CPUVR_BOOT1

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

CPUVR_UGATE2

CPUVR_LGATE2 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

CPUVR_BOOT2

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

CPUVR_LGATE1 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

2 1

C7311

0.22UF

10% 16V

CERM

402

C7321

0.22UF

10% 16V

CERM

402

4

R7311

21

4

2 1

21

G

2.2

5% 1/16W MF-LF

402

G

R7321

2.2

5% 1/16W MF-LF

402

5

D

S

321

CPUVR_BOOT1_RC

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

5

D

S

321

CPUVR_BOOT2_RC

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

OMIT_TABLE

CRITICAL

Q7310

SISA18DN

PWRPAK-SM

4

OMIT_TABLE

CRITICAL

Q7320

SISA18DN

PWRPAK-SM

CPUVR_PHASE1

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

SWITCH_NODE=TRUE

5

OMIT_TABLE

CRITICAL

D

G

Q7311

SISA12DN

PWRPAK-SM

NOSTUFF

R7312

2.2

5% 1/10W MF-LF

603

S

321

CPUVR_PHASE2

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

SWITCH_NODE=TRUE

5

OMIT_TABLE

CRITICAL

D

G

4

Q7321

SISA12DN

PWRPAK-SM

S

321

1

2

NOSTUFF

R7322

2.2

5% 1/10W MF-LF

603

CRITICAL

L7310

0.40UH-20%-16A

MPCG0730-SM

152S1757

1

2

CRITICAL

L7320

0.40UH-20%-16A

MPCG0730-SM

152S1757

1

2

CPUVR_PH1_SNUB

DIDT=TRUE

C7312

0.001UF

10% 50V X7R-CERM 0402

CPUVR_PH2_SNUB

CRITICAL

1

C7314

62UF-0.023OHM

20% 11V

2

TANT-POLY CASE-B2S

PPVCC_S0_CPU_PH1

21

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=1.8V

NOSTUFF

CRITICAL

1

C7323

62UF-0.023OHM

20% 11V

2

TANT-POLY CASE-B2S

PPVCC_S0_CPU_PH2

21

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=1.8V

DIDT=TRUE

NOSTUFF

1

C7322

0.001UF

10% 50V

2

X7R-CERM 0402

1

2

CPUVR_ISNS1_P

R7315

CRITICAL

1

C7324

62UF-0.023OHM

20% 11V

2

TANT-POLY CASE-B2S

NOSTUFF

CRITICAL

C7315

10UF

20% 16V X6S-CERM 0603

1K

1%

1/20W

MF

201

CPUVR_ISNS2_P

R7325

1

2

CRITICAL

1

C7325

2

1/20W

1

2

CRITICAL

R7310

0.00075

1% 1W MF

0612

2 1 4 3

NOSTUFF

10UF

20% 16V X6S-CERM 0603

1

1K

1%

MF

201

2

CRITICAL

C7316

NOSTUFF

1

10UF

20% 16V

2

X6S-CERM 0603

CPUVR_ISNS1_N

1

R7314

1.00

1% 1/20W MF-LF 0201

2

CPUVR_ISUMN

NO_XNET_CONNECTION=TRUE

1

R7316

200K

1% 1/20W MF 201

2

CPUVR_ISEN1

CPUVR_ISUMP

NOSTUFF

CRITICAL

1

C7326

10UF

20% 16V

2

X6S-CERM 0603

CRITICAL

R7320

0.00075

1% 1W MF

0612

21 43

CPUVR_ISNS2_N

1

R7324

1.00

1% 1/20W MF-LF 0201

2

NO_XNET_CONNECTION=TRUE

1

R7326

200K

1% 1/20W MF 201

2

C7317

1UF

10% 16V X6S-CERM 0402

1

2

CPUVR_ISUMN

CPUVR_ISEN2

CPUVR_ISUMP

THESE TWO CAPS ARE FOR EMC

1

C7318

0.001UF

10% 50V

2

X7R-CERM 0402

40 50 72 40 72

OUTOUT

C7327

1UF

10% 16V X6S-CERM 0402

1

C7319

0.001UF

10% 50V

2

X7R-CERM 0402

THESE TWO CAPS ARE FOR EMC

1

C7328

0.001UF

10% 50V

2

X7R-CERM 0402

40 50 72 40 72

OUTOUT

49 50

49

49 50

OMIT

R7317

NOSTUFF

NONE NONE NONE 0201

21

CPUVR_ISNS2_N

NO_XNET_CONNECTION=TRUE

OMIT

R7327

NOSTUFF

21

NONE NONE NONE 0201

40 50 72

CPUVR_ISNS1_N

NO_XNET_CONNECTION=TRUE

49 50

OUT

49

OUT

49 50

OUT

1

C7329

0.001UF

10% 50V

2

X7R-CERM 0402

OUT

Additonal Input Bulk Caps

CRITICAL

1

C7370

62UF-0.023OHM

20% 11V

2

TANT-POLY CASE-B2S

40 50 72

1

2

CRITICAL

C7371

62UF-0.023OHM

20% 11V TANT-POLY CASE-B2S

1

2

CRITICAL

C7372

62UF-0.023OHM

20% 11V TANT-POLY CASE-B2S

1

2

CRITICAL

C7373

62UF-0.023OHM

20% 11V TANT-POLY CASE-B2S

1

2

CRITICAL

C7374

62UF-0.023OHM

20% 11V TANT-POLY CASE-B2S

1

2

CRITICAL

C7375

62UF-0.023OHM

20% 11V TANT-POLY CASE-B2S

PPVCC_S0_CPU

Vout = 1.85V max 32A max output f = 700kHz

1

2

CRITICAL

C7376

62UF-0.023OHM

20% 11V TANT-POLY CASE-B2S

8

12

10 40 60 62

1

2

CRITICAL

C7377

62UF-0.023OHM

20% 11V TANT-POLY CASE-B2S

D

C

B

A

SYNC_MASTER=J43_MLB

PAGE TITLE

CPU VR12.5 VCC Power Stage

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

6 3

.

SYNC_DATE=09/21/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

73 OF 120

SHEET

50 OF 73

124578

SIZE

A

D

8 7 6 5 4 3

12

D

PPBUS_S5_HS_COMPUTING_ISNS

39 49 50 53 60 62

1

C7430

62UF-0.023OHM

20% 11V

2

TANT-POLY

DIDT=TRUE

OUT

GATE_NODE=TRUE

SM

CASE-B2S

R7425

402

5%

0

57

21

PLACE_NEAR=C2720.1:3mm

MF-LF

1/16W

21

XW7460

PP1V2_S3

17 19 20 21 22 23 40 51 60 68

PP5V_S5

34 52 60

BYPASS=U7400.12:1mm

1

C7400

10UF

20% 10V

2

X5R 603

C

MEMVTT_PWR_EN

17

IN

DDRREG_EN

57

IN

DDRREG_1V8_VREF

1

C7415

0.1UF

10% 16V

2

X7R-CERM

0402

BYPASS=U7400.6:1mm

B

1

R7415

28.7K

1% 1/20W MF 201

2

1

R7416

57.6K

1% 1/20W MF 201

2

GND_DDRREG_SGND

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.15 mm VOLTAGE=0V

PLACE_NEAR=U7400.8:5mm

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

1

2

C7416

0.01UF

10% 16V X7R-CERM 0402

BYPASS=U7400.8:1mm

(VTT Enable) (VDDQ/VTTREF Enable)

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

PLACE_NEAR=U7400.19:3mm

1

R7417

200K

1% 1/20W MF 201

2

DDRREG_FB

19

DDRREG_MODE DDRREG_TRIP

PLACE_NEAR=U7400.18:3mm

1

R7418

49.9K

1% 1/20W MF 201

2

BYPASS=U7400.2:1mm

C7401

10UF

17 16

6

8

19

18

20% 10V X5R 603

V5IN

S3 S5

VREF

REFIN

MODE TRIP

1

2

PGND

10

2

VLDOIN

U7400

TPS51916

QFN

CRITICAL

GND

7

VTT

4

VBST DRVH

DRVL

PGOOD

VDDQSNS

VTTSNS

VTTREF

THRM

PADGND

21

SW

VTT

PLACE_NEAR=U7400.21:1mm

XW7400

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm

DDRREG_VBST

1512

DDRREG_DRVH

14

DDRREG_LL

13

SWITCH_NODE=TRUE

DDRREG_DRVL

11

DDRREG_PGOOD

20

DDRREG_VDDQSNS

9

60

PP0V6_S0_DDRVTT

24

3 1

DDRREG_VTTSNS

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

5

10mA max load

PPVTT_S3_DDR_BUF

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

VOLTAGE=0.6V

2

SM

1

C7450

0.22UF

CERM

GATE_NODE=TRUE

1

10% 10V

2

402

DIDT=TRUE

1

C7431

62UF-0.023OHM

20% 11V

2

TANT-POLY CASE-B2S

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

DDRREG_VBST_RC

MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

CRITICAL

1

C7462

10UF

20%

6.3V

2

X5R 603

BYPASS=U7400.3:3mm

(DDRREG_DRVH)

C7425

0.1UF

21

10% 25V X5R 402

(DDRREG_LL)

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

(DDRREG_DRVL)

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

(DDRREG_VDDQSNS)

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.17 mm

1

2

3

4

5

C7432

1UF

10% 25V X5R 603-1

CRITICAL

Q7430

CSD58873Q3D

TG

TGR

BG

1

C7433

0.001UF

10% 50V

2

X7R-CERM 0402

Q3D

VIN

VSW

PGND

9

R7460

1/20W

201

1

6

7

8

10

5%

MF

1

C7434

62UF-0.023OHM

20% 11V

2

TANT-POLY CASE-B2S

PDDR_S3_REG_L

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.1 MM

NOSTUFF

1

R7435

2.2

5% 1/10W MF-LF 603

2

PDDR_S3_REG_SNUB

DIDT=TRUE

21

DDRREG_VDDQSNS_R

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.17 mm

1.0UH-20%-11A-0.011OHM

DIDT=TRUE

NOSTUFF

C7435

0.001UF

X7R-CERM

1

10% 50V

2

0402

CRITICAL

L7430

FDSD0630-SM

39 72

OUT

39 72

OUT

21

PPDDR_S3_REG_R

VOLTAGE=1.2V MIN_LINE_WIDTH=0.8 MM MIN_NECK_WIDTH=0.1 MM

ISNS_1V2_S3_P

ISNS_1V2_S3_N

CRITICAL

R7450

0.002

MF-LF

1/4W

1206

1%

21 43

CRITICAL

1

C7440

330UF

20%

2.0V

2

POLY-TANT CASE-B2-SM1

CRITICAL

C7441

330UF

POLY-TANT

CASE-B2-SM1

2.0V

1

C7446

0.001UF

10% 50V

2

X7R-CERM

0402

1

C7445

10UF

20%

2

6.3V

2

X5R 603

PP1V2_S3

Vout = 1.35V

14.1A max output

(Q7435 limit)

f = 400 kHz

PLACE_NEAR=C7440.1:1mm

2

XW7401

SM

1

60 68 17 19 20 21 22 23 40 51

D

C

B

A

6 3

SYNC_MASTER=J43_MLB

PAGE TITLE

LPDDR3 Supply

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=09/17/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

74 OF 120

SHEET

51 OF 73

124578

SIZE

A

D

8 7 6 5 4 3

12

D

C

B

39 60 62

F=400KHZ

Vout = 5.0V

7.2A MAX OUTPUT

CRITICAL

1

C7554

62UF

20%

6.3V

2

ELEC

CASE-B2S

150UF-0.035OHM

20%

6.3V

POLY-TANT

CASE-B2-SM

PPBUS_S5_HS_OTHER_ISNS

62UF-0.023OHM

PP5V_S4RS3

32 33 45 47 52 53 56 60 62

CRITICAL

150UF-0.035OHM

1

C7552

20%

6.3V 2

POLY-TANT

CASE-B2-SM

1

CRITICAL

C7553

2

PLACE_NEAR=L7520.1:1.5mm

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

1

C7542

20% 11V

2

TANT-POLY

CASE-B2S

C7550

10UF

20%

1

C7571

1000PF

10% 16V

2

X7R-CERM 0201

P5V_S4RS3_VFB1_XW MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

P5V_S4RS3_VFB1_R

1

10V

2

X5R 603

R7523

1/20W

1

R7520

41.2K

1% 1/20W MF 201

2

1

R7521

10K

1% 1/20W MF 201

2

C7540

62UF-0.023OHM

20% 11V

TANT-POLY

CASE-B2S

2.2UH-20%-9A-0.012OHM

2

XW7520

1

PLACE_NEAR=L7520.1:3mm

2

XW7522

SM

1

10

5%

MF

201

2

BYPASS=Q7520.1:1.5mm

1

C7570

1000PF

10% 16V

2

X7R-CERM 0201

CRITICAL

L7520

PIME063T2R2MS-SM

152S1798

SM

PLACE_NEAR=L7520.1:3mm

PLACE_NEAR=L7520.2:3mm

21

XW7521

P5V_S4RS3_REG_L

DIDT=TRUE

2

SM

1

C7541

1UF

10% 16V

2

X5R 402

1

VIN

6 7

8

NOSTUFF

1

R7522

2.2

5% 1/10W MF-LF 603

2

P5V_S4RS3_REG_SNUB

DIDT=TRUE

Q7520

CSD58873Q3D

Q3D

VSW

CRITICAL

PGND

9

NOSTUFF

C7522

0.001UF

X7R-CERM

0402

P5V_S4RS3_CSP1_R MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

D

SKIPSEL Strap

VREF2 VREG3

1

C7500

1UF

10% 16V

2

X5R 402

P5V_S4RS3_VBST_R MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

1

C7524

0.1UF

10% 25V

2

X5R 402

3

TG

4

TGR

5

BG

1

10% 50V

2

R7556

4.22K

1

1%

1/20W

MF

201

2

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

C7518

0.1UF

21

10% 16V

X7R-CERM

0402

R7547

1.33K

1%

1/20W

MF

201

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

21

1

R7545

0

5% 1/16W MF-LF

402

2

P5VP3V3_VREG3

52

P5V_S4RS3_COMP1_R

C7536

4700PF

52

1

10% 10V

2

X7R 201

P5VP3V3_VREF2

57

35 57

Auto Skip (Higher Efficiency) OOA Auto Skip (Lower Efficiency)

PP5V_S4RS3

32 33 45 47 52 53 56 60 62

NOSTUFF

1

R7500

R7501

0

5%

1/20W

MF

0201

P5VP3V3_SKIPSEL

P5V_S4RS3_VBST

P5V_S4RS3_DRVH

P5V_S4RS3_LL

P5V_S4RS3_DRVL

P5V_S4RS3_CSP1

P5V_S4RS3_CSN1

P5V_S4RS3_FUNC

P5V_S4RS3_VFB1

P5V_S4RS3_COMP1

P5VS4RS3_EN_R

1

R7549

0

5% 1/20W

MF 0201

2

0201

2

GND_P5VP3V3_SGND MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

VOLTAGE=0V

DIDT=TRUE

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

1

R7536

7.5K

1% 1/20W MF

201

2

OUT

NO STUFF

R7548

1/20W

5%

MF

NO STUFF

1

R7537

20K

1% 1/20W

MF 201

2

P5VS4RS3_PGOOD

S5_PWRGD

0

C7537

X7R-CERM

270PF

0201-1

GATE_NODE=TRUE

SWITCH_NODE=TRUE

GATE_NODE=TRUE

21

0201

1

10% 16V

2

1

2

P5VS4RS3_EN

57 57

IN IN

2

V5SW

6

SKIPSEL1

19

SKIPSEL2

14

OCSEL

31

1

32

30

DRVL1

7

CSP1

8

11

MODE

9

VFB1 VFB2

10

4

5

PLACE_NEAR=U7501.4:2mm

R7551

0

5% 1/20W MF 0201

34 51 60

29

23

VIN

VREG5

CRITICAL

U7501

QFN

GND

28

XW7500

SM

PLACE_NEAR=U7501.28:1mm

PP5V_S5

TPS51980A

THRM_PAD

21

22

VREG3

33

52

VBST2VBST1

DRVH2DRVH1

DRVL2

CSP2 CSN2CSN1

COMP2COMP1

PGOOD2PGOOD1

353S3905

S5_PWR_EN

52

13

VREF2

SW2SW1

EN2EN1

P5VP3V3_VREG3

P5VP3V3_VREF2

EN

RF

12

26

24

25

27

18

17

3

16

15

21

20

SMC_PM_G2_EN

P3V3S5_EN_R

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

1

C7501

0.22UF

10% 10V

2

CERM

402

P3V3_S5_RF

PLACE_NEAR=U7501.21:2mm

1

R7552

0

5% 1/20W MF 0201

2

P3V3_S5_VBST

P3V3_S5_DRVH

GATE_NODE=TRUE

P3V3_S5_LL

SWITCH_NODE=TRUE

P3V3_S5_DRVL

GATE_NODE=TRUE

P3V3_S5_CSP2

P3V3_S5_CSN2

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

1

R7506

249K

1% 1/20W MF

201

2

C7538

4700PF

52

C7503

2.2UF

X5R-CERM

35 36 57

IN

P3V3_S5_VFB2

P3V3_S5_COMP2

1

10% 10V

2

X7R 201

P5VP3V3_VREF2

1

20%

10V

2

402

1

R7538

7.5K

1% 1/20W MF

201

2

P3V3_S5_COMP2_R

1

2

DIDT=TRUE

1

2

C7505

R7539

20K

1% 1/20W

MF 201

10UF

20%

10V

X5R

603

C7539

NP0-C0G

22PF

5%

6.3V

0201

P3V3_S5_VBST_R MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

2

R7564

0

5% 1/16W MF-LF 402

1

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mmDIDT=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

1

2

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

C7588

0.1UF

21

10% 16V

X7R-CERM

0402

R7546

1.54K

21

1%

1/20W

MF

201

1

C7564

0.1UF

10% 25V

2

X5R 402

1

R7516

6.65K

1% 1/20W MF 201

2

MIN_LINE_WIDTH=0.2 mm DIDT=TRUE MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

3

4

5

Q7560

CSD58873Q3D

TG

TGR

CRITICAL

BG

P3V3_S5_REG_SNUB

NOSTUFF

1

C7562

0.001UF

10% 50V

2

X7R-CERM 0402

P3V3_S5_CSP2_R

Q3D

62UF-0.023OHM

VIN

VSW

PGND

9

C7584

TANT-POLY

CASE-B2S

1

20% 11V

2

1

6 7

8

NOSTUFF

R7562

DIDT=TRUE

P3V3_S5_REG_L DIDT=TRUE

2.2

5% 1/10W MF-LF

603

C7582

62UF-0.023OHM

TANT-POLY

CASE-B2S

XW7560

PLACE_NEAR=L7560.1:3mm

1

2

1

20% 11V

2

150UF-0.018OHM-1.8A

CRITICAL

2.2UH-20%-9A-0.012OHM

PIME063T2R2MS-SM

152S1798

2

SM

1

PLACE_NEAR=L7560.2:3mm

1

2

L7560

C7581

1UF

10% 16V X5R 402

XW7561

C7593

CASE-B2-SM

21

2

SM

1

XW7562

CRITICAL

1

C7583

1000PF

10% 16V

2

X7R-CERM 0201

BYPASS=Q7560.1:1.5mm

1

20%

6.3V

2

TANT

1

2

SM

1

P3V3_S5_VFB2_XW MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

1

R7563

10

5% 1/20W MF 201

2

P3V3_S5_VFB2_R MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

1

R7560

23.2K

1% 1/20W MF 201

2

1

R7561

10K

1% 1/20W MF 201

2

PP3V3_S5

PP3V3_S5_REG_R

Vout = 3.3V

6.5A MAX OUTPUT F=400KHZ

150UF-0.018OHM-1.8A

C7590

10UF

20%

10V X5R 603

CASE-B2-SM

CRITICAL

1

C7592

20%

6.3V 2

TANT

PLACE_NEAR=L7560.2:1.5mm

1

C7572

1000PF

10% 16V

2

X7R-CERM 0201

29 40 55 56 57 8

11 13 15 16 17 18 28 58 60 62 72

C

40

B

A

SYNC_MASTER=J43_MLB

PAGE TITLE

5V S4RS3 / 3.3V S5 Power Supply

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

6 3

SYNC_DATE=10/02/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

75 OF 120

SHEET

52 OF 73

124578

SIZE

A

D

8 7 6 5 4 3

12

D

1.05V S0 Regulator

PPBUS_S5_HS_COMPUTING_ISNS

39 49 50 51 60 62

1

C7620

PP1V05_S0

6 8

11 15 16 17 36 40 49 53

56 57 60 62

P1V05S0_BOOT_RC

MIN_LINE_WIDTH=0.5 mm

0.22UF

CERM

P1V05S0_VBST

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

P1V05S0_DRVH

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE DIDT=TRUE

P1V05S0_LL

P1V05S0_DRVL

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE DIDT=TRUE

P1V05S0_PGOOD

1

10% 10V

2

402

MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

R7630

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE DIDT=TRUE

1

C7630

0.1UF

10%

21

P1V05S0_DRVH_R

57

16V

2

X7R-CERM 0402

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE DIDT=TRUE

1

2.2

5%

1/10W

MF-LF

603

2

R7631

0

5%

1/16W

MF-LF

402

OUT

PP5V_S4RS3

32 33 45 47 52 56 60 62

1

C

P1V05_S0_VREF

C7615

0.1UF

X7R-CERM

BYPASS=U7600.6:1mm

0402

1

10% 16V

2

1

R7611

35.7K

1% 1/20W MF 201

2

1

R7612

49.9K

1% 1/20W MF 201

2

PLACE_NEAR=U7600.8:5mm

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

1

C7616

0.01UF

10% 16V

2

X7R-CERM 0402

BYPASS=U7600.8:1mm

C7600

10UF

20% 10V

2

X5R 603

BYPASS=U7600.12:1mm

Scrub S3 & S5 pins connections!

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

1

R7610

1K

1% 1/20W MF 201

2

1

R7613

47.5K

1% 1/20W MF 201

2

PLACE_NEAR=U7600.19:3mm

P1V05S3_EN

P1V05S0_EN

57

P1V05S0_FB

P1V05S0_MODE

P1V05S0_TRIP

1

R7614

17.4K

1% 1/20W MF 201

2

PLACE_NEAR=U7600.18:3mm

B

C7601

10UF

BYPASS=U7600.2:1mm

17 16

6

8

19

18

20% 10V X5R 603

V5IN

S3 S5

VREF

REFIN

MODE TRIP

1

2

PGND

10

2

VLDOIN

U7600

TPS51916

QFN

CRITICAL

GND

7

VTT

4

VBST DRVH

DRVL

PGOOD

VDDQSNS

VTTSNS

VTTREF

THRM

PADGND

21

1512

14

13

SW

11 20

9

3

VTT

1

5

XW7600

P1V05S0_VTT

P1V05S0_VTTREF

2

SM

1

C7650

62UF-0.023OHM

V+

8

V+

9

LSG

7

20% 11V

2

TANT-POLY

CASE-B2S

CRITICAL

Q7630

FDPC1012S

LLP

GND

6

5

10

HSG

SW

C7621

62UF-0.023OHM

TANT-POLY

CASE-B2S

1

2

3 4

20% 11V

1

2

C7622

1000PF

CERM 0402

1

R7632

2.2

5% 1/10W MF-LF 603

2

P1V05S0_LL_SNUB

DIDT=TRUE

1

5%

25V

2

PLACE_NEAR=Q7630.8:1.5mm

1.0UH-20%-11A-0.011OHM

NOSTUFF

C7619

62UF-0.023OHM

20% 11V TANT-POLY CASE-B2S

L7630

FDSD0630-SM

CRITICAL

NOSTUFF

C7632

0.001UF

X7R-CERM

1

C7624

1UF

10% 16V

2

X5R 402

C

OMIT

R7640

0.003

1% 1w

CYN

21

PP1V05_S0_REG_R

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

ISNS_1V05_S0_P

40 72

OUT

ISNS_1V05_S0_N

40 72

OUT

1

10% 50V

2

0402

0612-SHORT

21 43

PLACE_NEAR=L7630.2:1.5mm

C7623

1000PF

CRITICAL

1

5%

25V

2

CERM 0402

1

2

CRITICAL

C7648

330UF

20%

2.0V POLY-TANT CASE-B2-SM1

C7649

POLY-TANT

CASE-B2-SM1

330UF

20%

2.0V

PP1V05_S0

Vout = 1.05V

21A Max Output

1

f = 300 kHz

2

PLACE_NEAR=C7648.1:1mm

XW7610

SM

62 40 49 53 6 8

11 15 16 17 36 56 57 60

2

1

B

P1V05S0_AGND

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V

A

6 3

PLACE_NEAR=U7600.21:1mm

P1V05S0_VDDQSNS

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.17 mm

R7641

10

5%

1/20W

MF

201

21

P1V05S0_VDDQSNS_R

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.17 mm

SYNC_MASTER=J43_MLB

PAGE TITLE

1.05V S0 Power Supply

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=09/10/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

76 OF 120

SHEET

53 OF 73

124578

SIZE

A

D

8 7 6 5 4 3

PPBUS S0 LCDBkLT FET

MOSFET

CHANNEL

CRITICAL

Q7706

FDC638APZ_SBMS001

F7700

PPBUS_G3H

27 39 40 47 48 60 62

D

3AMP-32V-467

PLACE_SIDE=BOTTOM

LCDBKLT_EN_L

13

IN

EDP_BKLT_EN

Q7707

DMN5L06VK-7

SOT563

VER 3

5

3

D

SG

4

LCDBKLT_DISABLE

C

BKLT_PLT_RST_L

18

IN

SMBUS_PCH_CLK

14 16 19 38 67

IN

SMBUS_PCH_DATA

14 16 19 38 67

BI

Addr: 0x58(Wr)/0x59(Rd)

PPVIN_S0SW_LCDBKLT

39 54

EDP_BKLT_PWM

13

IN

603-HF

Q7707

DMN5L06VK-7

21

PPVIN_S0SW_LCDBKLTFET

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V

1

R7788

301K

1% 1/20W MF 201

2

LCDBKLT_EN_DIV_L

1

R7789

147K

1% 1/20W MF 201

2

6

D

SOT563

VER 3

2

SG

R7757

0

5%

1/20W

MF

0201

R7704

33

5%

1/20W

MF

201

1

C7782

0.1UF

10% 16V

2

X7R-CERM

0402

1

R7753

0

21

5%

1/20W

MF

0201

21

1

C7704

33PF

5% 25V

2

NPO-C0G 0201

SSOT6-HF

4

3

60 62 63 72

PP3V3_S0

8

11 12 13 15 17 18 26 30 34

36 37 38 39 40 41 42 43 57 59

(GND_BKL_SGND)

R7741

10K

1/20W

201

21

R7731

200K

1%

1/20W

MF

201

5% MF

21

1

R7715

100K

1% 1/20W MF 201

2

6521

BYPASS=U7701.C4:4mm

B

RDS(ON)

LOADING

PPVIN_S0SW_LCDBKLT_FET

PPVIN_S0SW_LCDBKLT

39 54

PLACE_NEAR=L7701.1:3mm

PP5V_S0

16 17 32 43 49 50 54 56 57 59 60 62

BYPASS=U7701.D1:5mm

C7711

0.1UF

10%

6.3V

CERM-X5R

0201

PLACE_SIDE=BOTTOM

1

2

TP7701

C7710

TP-P6

I_LED=17.1mA

1

R7755

10K

5% 1/20W MF 201

2

R7714

21.5K

I_LED=369/Riset

(EEPROM should set EN_I_RES=1)

1

1UF

10% 25V

2

X5R

603-1

1

TP

1

1%

1/20W

MF

201

2

FDC638APZ

P-TYPE

43 mOhm @4.5V

0.65 A (EDP)

39

THERE IS A SENSE RESISTOR BETWEEN PPBUS_SW_LCDBKLT_PWR

AND PPBUS_SW_BKL

ON THE SENSOR PAGE

CRITICAL

1

C7712

10UF

BYPASS=U7701.D1:3mm

1

C7714

0.01UF

10% 10V

2

X5R-CERM 0201

1

10% 25V

2

X5R 805

BKL_VSYNC_R

BKL_FLTR

BKL_ISET

BKL_FSET

BKL_SCL BKL_SDA

BKL_PWM

BKL_EN

BKL_FAULT

Fpwm=9.62kHz

see spec for others

1

R7716

90.9K

1% 1/20W MF 201

2

GND_BKL_SGND

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0V

C7713

0.1UF

10% 25V X5R 402

PLACE_NEAR=L7701.1:3mm

D1

C4

VDDIO

VLDO

U7701

25-BUMP-MICRO

D2

VSYNC

C2

FILTER

B3

ISET

B4

FSET

D3

SCLK

D4

SDA

A4

PWM

A3

EN

C3

FAULT

CRITICAL

GND_S

GND_L

*C7797 AND C7799 SHOULD BE PLACED IN T-BONE FOR ACOUSTICS *PPBUS_SW_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.

*LCD_BKLT_PWM SHOULD BE AWAY FROM BOOST CIRCUIT

CRITICAL

L7701

15UH-2.8A

PIMB053T-SM

C1

VIN

SW_0 SW_1

21

LCDBKLT_BOOST

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.150 MM VOLTAGE=50V SWITCH_NODE=TRUE DIDT=TRUE

PPVOUT_SW_LCDBKLT_FB

VOLTAGE=50V MIN_LINE_WIDTH=0.1 MM MIN_NECK_WIDTH=0.1 MM

B1

B2

A5

FB

LP8550

E5

BKL_ISEN1

OUT1

D5

BKL_ISEN2

OUT2

C5

BKL_ISEN3

OUT3

E3

BKL_ISEN4

OUT4

E2

BKL_ISEN5

OUT5

E1

BKL_ISEN6

OUT6

GND_SW

A2

A1B5E4

XW7710

SM

21

PLACEMENT_NOTE=Keep away from noise nodes(E4, A1, A2, B1, B2 pins)

PART NUMBER

103S0198

PLACE_NEAR=L7701.2:3mm

CRITICAL

D7701

SOD-123

RB160M-60G

XW7720

SM

PLACE_NEAR=C7797.1:5mm

QTY

3

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm PLACE_NEAR=U7701.E5:10mm

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm PLACE_NEAR=U7701.D5:10mm

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm PLACE_NEAR=U7701.C5:10mm

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm PLACE_NEAR=U7701.E3:10mm

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm PLACE_NEAR=U7701.E2:10mm

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm PLACE_NEAR=U7701.E1:10mm

KA

1

C7796

220PF

10% 50V

2

X7R-CERM 0402

PLACE_NEAR=U7701.A5:3mm

21

CRITICAL

1

C7797

10UF

10% 50V

2

X5R 1210-1

PLACE_NEAR=D7701.2:3mm

10.2 ohm resistors for current measurement on LED strings.

DESCRIPTION

RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM

BKLT:PROD

R7717

R7718

R7719

R7720

R7721

R7722

0

BKLT:PROD

21

5%

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

21

1/16W MF-LF

5%

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

21

5%

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

21

1/16W MF-LF

5%

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

21

5%

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

21

1/16W MF-LF

5%

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

PPHV_S0SW_LCDBKLT

CRITICAL

1

C7799

10UF

10% 50V

2

X5R 1210-1

PLACE_NEAR=D7701.2:5mm

REFERENCE DES

R7717,R7718,R7719

R7720,R7721,R7722

LED_RETURN_1

MF-LF1/16W

402

LED_RETURN_2

LED_RETURN_3

LED_RETURN_4

LED_RETURN_5

LED_RETURN_6

402

MF-LF1/16W

402

MF-LF1/16W

402

OUT

CRITICAL

58 62

58 60 62

BOM OPTION

12

D

BKLT:ENG

C

B

Keyboard Backlight Driver & Detection

CRITICAL

L7750

SPN035007G

EN

FB

NC

GND

4

U7750

CRITICAL

8

10UH-0.58A-0.35OHM

1098AS-SM

2

VIN

MLF

THRM

PAD

7

SW

1

OUT

9

21

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.225 MM SWITCH_NODE=TRUE DIDT=TRUE

KBDLED_ANODE

62 62

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=40V

KBDLED_SW

1

C7755

0.22UF

2

10% 50V X5R-CERM 0603-1

1

C7756

2

0.22UF

10% 50V X5R-CERM 0603-1

Keyboard Backlight Connector

CRITICAL

J7715

FF14A-4C-R11DL-B-3H

F-RT-SM

5

NC

1

2

3

4

6

NC

518S0793

SYNC_MASTER=J43_MLB

PAGE TITLE

LCD/KBD Backlight Driver

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=09/13/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

77 OF 120

SHEET

54 OF 73

124578

SIZE

A

D

PP5V_S0

16 17 32 43 49 50 54 56 57 59 60 62

BYPASS=U7750.1:2:2 MM

35

BI

A

SMC_SYS_KBDLED

KBDLED_FB

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=40V

1

R7700

4.7

5% 1/16W MF-LF 402

2

C7750

1UF

402-1

1

10% 10V

2

X5R

3

6

5

NC

6 3

8 7 6 5 4 3

12

1.05V SUS LDO

Cougar Point requires JTAG pull-ups to be powered at 1.05V when SUS suspend well is active. Pull-ups (3) must be 51 ohms to support XDP (not required in production).

70mA is required to support pull-ups. Alternative is strong voltage

D

52 55 56 57

PP3V3_S5

8

11 13 15 16

17 18 28 29 40 58 60 62 72

1

C7824

1000PF

10% 16V

2

X7R-CERM

0201

C

CRITICAL

1

C7820

22UF

20%

6.3V 2

X5R-CERM-1

603

P1V8S3_EN

57

IN

P1V8S3_PGOOD

57

OUT

1

VIN

U7820

ISL8009B

DFN

2

EN

3

POR

4 5

SKIP

GND

7

CRITICAL

THRM_PAD

9

LX

VFB

RSI

8

P1V8S3_SW

SWITCH_NODE=TRUE DIDT=TRUE

6

P1V8S3_FB

1.8V S3 REGULATOR

152S1870

L7820

2.2UH-20%-2.0A-0.108OHM

2520-SM

CRITICAL

21

R7820

113K

1%

1/20W

MF

201

PP1V8_S3_REG_R

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=1.2V

1

2

1

2

C7823

47PF

5% 25V NP0-C0G-CERM 0201

1

2

CRITICAL

C7821

22UF

20%

6.3V X5R-CERM-1 603

CRITICAL

C7825

X5R-CERM-1

22UF

OMIT

R7829

0.002

1% 1W MF

0612-SHORT

21

PP1V8_S3

43

NC NC

1

20%

6.3V

2

603

Vout = 1.794V Max Current = 1.8A Freq = 1 MHz

20 21 22 23 55 60

dividers (200/100) to 3.3V S5, which burns 100mW in all S-states.

PP3V3_SUS

8

11 14 18 44 56 57 60 62

XDP

1

C7840

1UF

10%

6.3V 2

CERM

402

CRITICAL

XDP

U7840

TPS720105

SON

4

BIAS

6

IN

3

EN

OUT

NC

THRM

PADGND

7

5

1

2

NC

PP1V05_SUS

Vout = 1.05V

Max Current = 0.35A

XDP

1

C7841

2.2UF

10%

6.3V

2

X5R 402

16 60

<Ra>

D

C

R7821

90.9K

1/20W

<Rb>

1

1%

MF

201

2

CRITICAL

C7822

X5R-CERM-1

22UF

1

20%

6.3V 2

603

Vout = 0.8V * (1 + Ra / Rb)

B

1.5V S0 LDO

CRITICAL

U7870

TPS72015

SON

PP3V3_S5

8

11 13 15 16 17 18 28 29 40

52 55 56 57 58 60 62 72

PP1V8_S3

20 21 22 23 55 60

IN

PM_SLP_S3_BUF_L

28 57

IN

1

10%

2

402

BYPASS=U7870.6:1mm

C7871

C7870

1UF

6.3V

A

CERM

BYPASS=U7870.4:1mm

4

BIAS

6

IN

3

EN

1

1UF

10%

6.3V

2

CERM

402

OUT

NC

THRM

PADGND

7

5

1

2

NC

PP1V5_S0

Vout = 1.5V

Max Current = 0.02A

1

C7872

2.2UF

10%

6.3V

2

X5R 402

8

56 57 60 62

6 3

SYNC_MASTER=J43_MLB

PAGE TITLE

Misc Power Supplies

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=10/04/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

78 OF 120

SHEET

55 OF 73

124578

SIZE

A

D

8 7 6 5 4 3

12

1.5V S0 Audio Switch

PP1V5_S0

8

55 57

60 62

NOSTUFF

D

57

IN

P1V5S0SW_AUDIO_EN

R8040

1/20W

10K

5% MF

201

C8040

1.0UF

1

2

0201-1

6.3V

20% X5R

NOSTUFF

A1

B1

R8041

0

5%

1/20W

MF

0201

PP1V5_S0SW_AUDIO

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=1.5V MAKE_BASE=TRUE

Part

Type

R(on) @ 1.8V

R8042

0

21

5%

1/20W

MF

0201

U8040

TPS22924

CSP

A2

B2

C2

1

2

VIN

CRITICAL

ON

VOUT

GND

C1

Current

PP1V5_S0SW_AUDIO_HDA

21

PP1V5_S0SW_AUDIO_HDA

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=1.5V MAKE_BASE=TRUE

U8040

56 59 63

EDP: 35mA

TPS22924C

Load Switch

19.6 mOhm Typ

21.8 mOhm Max

2A Max

8

56 59 63

11 17 56

Loading specs per J41/43_PowerBudget_Riviera_rev0.99e

8

11 17 56

11 13 15 16 17 18 28 29 40

PP3V3_S5

8 52 55 56 57 58 60 62 72

3.3V SUS Switch

U8020

TPS22924

CSP

GND

A1

PP3V3_SUS_FET_R

B1

VOLTAGE=3.3V MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM

VOUT

U8020

C1

Part

Type

R(on) @ 2.5V

Current

A2

VIN

B2

CRITICAL

6.3V

C2

ON

1

20%

2

X5R

P3V3SUS_EN

57

IN

C8020

1.0UF

0201-1

OMIT

R8020

0.002

0612-SHORT

TPS22924C

Load Switch

18.5 mOhm Typ

25.8 mOhm Max

2A Max

1% 1W MF

NCNC

21 43

PP3V3_SUS

EDP: 112mA

8

11 14 18 44 55 57 60 62

D

1.05V PCH HSIO Switch

2

1

5

4

PP5V_S0

16 17 32 43 49 50 54 56 57 59 60 62

15 56

IN

11 15 16 17 36 40 49 53

Q8061

NTUD3169CZ

SOT-963

N-CHANNEL

G

P-CHANNEL

PCH_HSIO_PWR_EN

PP1V05_S0

6 8 56 57 60 62

D

S

D

S

1

C8005

1UF

10% 10V

2

X5R 402

ON S

HSIO has turn-on requirement of <0.1V/uS ramp rate and <65uS from EN to 95% (1.05V)

6

HSIOFET_DRV_L

3

HSIOFET_DRV_H

NOSTUFF

R8061

1/20W

R8062

1/20W

330

5%

MF

201

5%

MF

201

1

2

HSIOFET_EN

1

2

1

VDD

U8005

SLG5AP1471V

TDFN

CRITICAL

GND

8

2

D

3

59 7

PP1V05_S0

PP1V05_S0SW_PCH_HSIO

EDP: 1.84A

D

S

NOSTUFF

Q8060

IRFHM830DPBF

PQFN3.3X3.3

321

PP1V05_S0SW_PCH_HSIO

S

D

NOSTUFF

C8060

0.01UF

5

X5R-CERM

G

4

1

10% 10V

2

0201

NOSTUFF

1

R8060

300

5% 1/16W MF-LF 402

2

HSIOFET_DISCHARGE

(HSIOFET_EN_L)

SYNC_MASTER=J43_MLB

PAGE TITLE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

Part

Type

R(on) @ 4V Vgs

Current

CRITICAL

EDP: 1.84A

NOSTUFF

Q8062

DMN5L06VK-7

SOT563

VER 3

5

Power FETs

U8005

SLG5AP1417V

Load Switch

9.8 mOhm Typ TBD mOhm Max

6A Max

D

SG

3

4

SYNC_DATE=10/04/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

80 OF 120

SHEET

56 OF 73

124578

6 8

11 15 16 17 36 40 49 53

56 57 60 62

8

11 56 60

8

11 56 60

SIZE

C

B

A

D

3.3V S4 Switch

62 72 29 40 52 55

PP3V3_S5

8

11 13 15

16 17 18 28 56 57 58 60

S4_PWR_EN

18 28 57

IN

1

C8000

1.0UF

C

0201-1

6.3V

20%

2

X5R

U8000

TPS22924

CSP

GND

A1

PP3V3_S4_FET_R

B1

VOLTAGE=3.3V MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM

VOUT

U8000

C1

Part

A2

VIN

B2

CRITICAL

C2

ON

Type

R(on) @ 2.5V

Current

3.3V S3 Switch

11 13 15

62 72 29 40 52 55

PP3V3_S5

8 16 17 18 28 56 57 58 60

57

IN

P3V3S3_EN

C8010

1.0UF

0201-1

6.3V

1

20%

2

X5R

A2 B2

C2

TPS22924

VIN

CRITICAL

ON

U8010

CSP

GND

C1

VOUT

A1 B1

PP3V3_S3_FET_R

VOLTAGE=3.3V MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM

Part

Type

R(on) @ 2.5V

Current

U8010

TPS22924C

Load Switch

18.5 mOhm Typ

25.8 mOhm Max

2A Max

OMIT

R8000

0.002

0612-SHORT

NC NC

TPS22924C

Load Switch

18.5 mOhm Typ

25.8 mOhm Max

2A Max

OMIT

R8011

0.002

1% 1W MF

0612-SHORT

NC NC

1% 1W MF

21 43

21

PP3V3_S4

43

EDP: 119mA

PP3V3_S3

EDP: 1.02A

8

11 13 15 16 17 18 28 29 40

52 55 56 57 58 60 62 72

25 26 27 29 34 36 37 60 62

P3V3S0SW_SSD_FET_RAMP

15 30

1

C8071

4700PF

15 18 19 34 38 39 60 62 63

57 62

10% 10V

2

X7R 201

P3V3S0_EN

56 57

IN

PP3V3_S5

IN

B

3.3V S0 Switch

Sense R on sensor page

PP3V3_S0_FET_R

VOLTAGE=3.3V MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM

EDP: 1A

Part

Type

R(on) @ 2.5V

Current

U8030

TPS22924C

Load Switch

18.5 mOhm Typ

25.8 mOhm Max

2A Max

39

11 13

56 57 58 18 28 29

PP3V3_S5

8 15 16 17 40 52 55 60 62 72

56 57

IN

P3V3S0_EN

C8030

1.0UF

0201-1

6.3V

U8030

TPS22924

CSP

GND

A1

VOUT

B1

C1

A2

VIN

B2

CRITICAL

C2

ON

1

20%

2

X5R

3.3V Sensor Switch

62 57 52 28 16

PP3V3_S5

8

11

A

13 15 17 18 29 40 55 56 58 60 72

SMC_SENSOR_PWR_EN

35 37 40

IN

1

C8050

1.0UF

20%

6.3V 2

X5R

0201-1

A2 B2

C2

TPS22924

VIN

CRITICAL

ON

U8050

CSP

GND

C1

VOUT

A1 B1

PP3V3_S4SW_SNS_FET_R

VOLTAGE=3.3V MIN_LINE_WIDTH=0.5mm MIN_NECK_WIDTH=0.2mm

Part

Type

R(on) @ 2.5V

U8050

Current

TPS22924C

Load Switch

18.5 mOhm Typ

25.8 mOhm Max

2A Max

R8050

0

5% 1/16W MF-LF

402

21

PP3V3_S4SW_SNS

EDP: 50mA

39 40 41 60

C8081

4700PF

10% 10V X7R 201

1

2

3.3V SSD Switch

SSD_PWR_EN

NOSTUFF

R8070

0

5%

1/20W

MF

0201

21

CAP

5V S0 Switch

PP5V_S4RS3

32 33 45 47 52 53 60 62

P5VS0_FET_RAMP

P5VS0_EN

57

IN

1

VDD

U8070

SLG5AP1453V

TDFN

CRITICAL

GND

8

U8080

SLG5AP1443V

TDFN

CAP

CRITICAL

VDD

GND

1

C8070

0.1UF

10%

6.3V

2

CERM-X5R 0201

37

D

52

PP3V3_S0SW_SSD_FET_R

SON

VOLTAGE=3.3V MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM

39

EDP: 5A

Sense R on sensor page

U8070

Part

Type

R(on) @ 25C

Current

15 56

IN

1

D

SON

2

37

52

C8080

0.1UF

10% 16V X5R-CERM 0201

PP5V_S0_FET_R

VOLTAGE=5V MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM

1

8

SLG5AP1453V

Load Switch

7.8 mOhm Typ

8.5 mOhm Max

5.3A Max

PCH_HSIO_PWR_EN

NOSTUFF

Q8062

DMN5L06VK-7

SOT563

VER 3

PP5V_S0

16 17 32 43 49 50 54 56 57 59 60 62

2

R8081

0612-SHORT

NC NC

OMIT

0.002

1% 1W MF

D

SG

NOSTUFF

HSIOFET_EN_L

6

1

21

PP5V_S0

43

EDP: 300mA?

Part

Type

R(on)

Current

R8063

1/20W

10K

201

5%

MF

NOSTUFF

1

2

16 17 32 43 49 50 54 56 57 59 60 62

U8080

SLG5AP1438V

Load Switch

15 mOhm Typ 17 mOhm Max

2.5A

6 3

8 7 6 5 4 3

12

D

C

B

A

5V Divider:

3.19V @ 4.5Vmin

1.5V Divider:

0.718V @ 1.45Vmin

1.05V Divider:

0.723V @ 1.02Vmin

SMC_PM_G2_EN

35 36 52

OUT

57

SMC_PM_G2_EN

35 36 52

IN

57

MAKE_BASE=TRUE

46 47 48 57

PP3V42_G3H

17 30 33 34 35 36 38 44 59 60 62 63

PLACE_NEAR=U7501.20:7mm

S5_PWRGD S5_PWRGD

35 52 57

SSD_PWR_EN

IN

MAKE_BASE=TRUE

PP5V_S0

1

R8151

54.9K

1% 1/20W MF 201

2

5.0V Divider: 1.07V

1

R8152

15K

1% 1/20W MF 201

2

PP3V3_S0

1

R8158

15K

1% 1/20W MF 201

2

VMON_3V3_DIV

3.3V Divider: 1.07V

1

R8159

7.15K

1% 1/20W MF 201

2

Thresholds: VDD: 2.734V-3.010V V2MON: 2.815V-3.099V V3MON: 0.572V-0.630V V4MON: 0.572V-0.630V

PP1V5_S0

8

55 56 57 60 62

57 59 49 50

PP5V_S0

16 17 32 43 54 56 60 62

S5 Enables

PLACE_NEAR=U7501.21:7mm

S5 Power Good

R8141

100K

1/20W

201

SSD Enable

16 17 32 43 49 50 54 56 57 59 60 62

VMON_5V_DIV

C8159

1UF

10% 10V X5R 402

62 63 72 36 37 38 39 40 8 17 18 26 30 34 41 42 43 54 57 59 60

PP1V5_S0

8

55 56 57 60 62

PP1V05_S0

6 8

11 15 16 17 36 40 49 53

56 60 62

S0PGOOD_ISL

1

R8160

6.04K

1% 1/20W MF 201

2

S0PGOOD_ISL

1

R8161

15K

1% 1/20W MF 201

2

1

5%

MF

2

SSD_PWR_EN

1

2

11 12 13 15

R8140

100

21

S5_PWR_EN S5_PWR_EN

52 57

MAKE_BASE=TRUE

5%

1/20W

201

MF

NOSTUFF

1

C8142

0.47UF

10%

6.3V

2

CERM-X5R 402

PLACE_NEAR=U7501.21:7mm

S5_PWRGD-->SMC

SMC-->PM_DSW_PWRGD

MAKE_BASE=TRUE

35 52 57

OUT

15 30 56 57 62 15 30 56 57 62

OUT

S0 Rail PGOOD (BJT Version)

PP3V3_S5

8

11 13 15 16 17 18 28

R8153

1K

5%

1/20W

MF

201

29 40 52 55 56 57 58 60 62 72

21

R8156

150K

1/20W

201

9ms RC delay

VMON_Q2_BASE

R8154

1K

5%

1/20W

MF

201

21

R8155

1K

5%

1/20W

MF

201

VMON_Q3_BASE

21

VMON_Q4_BASE

NC

Vbe 0.7V max @ 2mA Vce(sat) 0.1V max @ 1mA Q1 Vth 0.7~1V @Id 250uA

S0 Rail PGOOD Circuitry

(ISL version used for development)

59 60 62 63 72

PP3V3_S0

8

11 12 13 15 17 18 26 30 34

36 37 38 39 40 41 42 43 54 57

S0PGOOD_ISL

1

R8170

15K

1% 1/20W MF 201

2

S0PGOOD_ISL

1

R8171

15K

1% 1/20W MF 201

2

S0PGOOD_ISL

1

R8172

6.04K

1% 1/20W MF 201

2

P5V_DIV_VMON P1V5_DIV_VMON P1V05_DIV_VMON

S0PGOOD_ISL

1

R8173

15K

1% 1/20W MF 201

2

1

1% MF

2

3 5

6

S0PGD_C

5

8

7

2

1

S0PGOOD_ISL

ISL88042IRTEZ

V2MON

CRITICAL

V3MON

GND

4

6

Q2

Q3

Q4

2

VDD

U8160

TDFN

THRM_PAD

52 57

OUT

3

S0PGD_BJT_GND_R

7

(IPU)

MR*

RST*V4MON

9

PP3V3_S5

8

11 13 15 16 17 18 28 29 40

52 55 56 57 58 60 62 72

BYPASS=U8170.6:2.3mm

PM_SLP_S5_L

13 35

IN

SMC_S4_WAKESRC_EN

35 36

IN

S4_PWR_EN

18 28 56 57

PM_SLP_S4_L

13 18 29 34 35 57

5V needs to be held up

so 1.05V can fall after 1.5V

ALL_SYS_PWRGD

4

CRITICAL

Q8150

Q1

ASMCC0179

DFN2015H4-8

376S0854

1

R8157

100

5%

1/20W

MF

201

2

S0PGOOD_ISL

C8160

0.1UF

6.3V

CERM-X5R

0201

353S2310

1

8

10%

NC

ALL_SYS_PWRGD_R

52

1

2

53

51

Standby Enables

NOSTUFF

U8170

6

74LVC1G32

SOT891

4

S4_PWR_EN

NC

5 3

NO STUFF

PLACE_NEAR=U7501.4:15mm

AUD_PWR_EN

D8146

SM-201

K A

RB521ZS-30

PM_SLP_S3_BUF_L

MAKE_BASE=TRUE

R8115

0

5%

1/20W

MF

0201

1

R8176

240

5%

1/20W

MF 201

13 17 18 35

2

21

1

2

PM_SLP_S3_L

IN

1.5V Codec Enable

PLACE_NEAR=U8040.2:C7mm

P1V5CODEC_EN_D

R8166

100

5%

100

1/20W

100

1/20W

MF

201

21

5%

MF

201

R8164

100

5%

1/20W

MF

201

21

5%

MF

201

R8165

R8168

21

R8175

0

5% 1/20W MF 0201

PLACE_NEAR=U7501.4:15mm

P5VS4RS3_EN

NO STUFF

C8175

2.2UF

10%

6.3V X5R 402

PLACE_NEAR=U7501.4:15mm

R8145

100K

5%

1/20W

MF

201

1

R8167

10K

5% 1/20W MF 201

2

21

R8178

100

5%

1/20W

MF

201

21

P1V5S0SW_AUDIO_EN

R8146

1/20W

16 17 35 57

OUT

21

1K

5%

MF

201

S4_PWR_EN

52

8

11 13 15 16 17 18 28 29 40

52 55 56 57 58 60 62 72

PM_SLP_S3_R_L

57

21

1

C8146

0.1UF

10% 25V

2

X5R 402

PLACE_NEAR=U8040.C2:7mm

PP3V3_S5

11 14 18 44 55 56 57 60 62

PP3V3_SUS

8

OUT

18 28 56 57

USB_PWR:STBY

1

R8114

100

5% 1/20W MF 201

2

PLACE_NEAR=U4600.4:6mm

USB_PWR_EN

33 57 59 63

MAKE_BASE=TRUE

NO STUFF

1

C8114

0.47UF

10%

6.3V

2

CERM-X5R 402

PLACE_NEAR=U4600.4:6mm

1

U8180

2

56

11 13 15 16 17 18 28 29 40

No stuff C8131, 12ms Min delay time

U8130 Sense input threhold is 3.07V

SUS_PGOOD_CT

NO STUFF

1

C8131

1000PF

10% 16V

2

X7R-CERM 0201

USB_PWR:S3

1

R8117

100

5% 1/20W MF 201

2

PLACE_NEAR=U4600.4:6mm

1

5

3

MC74VHC1G08

SC70-HF

4

2

PM_SLP_S3_BUF_L

28 55 57

NOSTUFF

1

R8180

330K

5% 1/20W MF 201

2

3.3V SUS Detect

PP3V3_S5

8 52 55 56 57 58 60 62 72

CRITICAL

2 6

SENSE

3

CT

PM_SLP_SUS_L

13 40 57

IN

MAKE_BASE=TRUE

USB_PWR_EN

BYPASS=U8180.6:3mm

C8180

0.1UF

10%

6.3V CERM-X5R 0201

MAKE_BASE=TRUE

P1V05_EN_D

BYPASS=U8130.6:2.3mm

1

VDD

RESET*

U8130

TPS3808G33

QFN

MR*

THRM

GND

PAD

5

7

SUS Enables

1

R8190

0

5% 1/20W MF 0201

2

P3V3SUS_EN P3V3SUS_EN

56 57

MAKE_BASE=TRUE

NO STUFF

1

C8190

0.1UF

10% 25V

2

X5R 402

33 57 59 63

OUT

NO STUFF

A

D8185

SM-201

RB521ZS-30

PLACE_NEAR=U7600.16:6mm

K

NO STUFF

R8138

1/20W

PLACE_NEAR=U7600.16:6mm

C8130

0.1UF

10%

6.3V

CERM-X5R

0201

PM_RSMRST_L

4

TP_SUS_PGOOD_MR_L

820

21

5%

MF

201

1

2

USB_PWR:STBY

R8177

0

5%

1/20W

MF

0201

USB_PWR:S3

R8179

0

5%

1/20W

MF

0201

P5VS4RS3_EN_D

16 17 35 57

P1V8S3_PGOOD

IN

P5VS4RS3_PGOOD

IN

P1V05S0_PGOOD

IN

DDRREG_PGOOD

IN

S0PGOOD_ISL

NOSTUFF

C8170

0.1UF

CERM-X5R

21

R8162

10%

6.3V

0201

P5VS4RS3_EN_RC

13 59 63

IN

330

21

5%

1/20W

MF

201

1

2

1

NC

PLACE_NEAR=U7501.4:15mm

NO STUFF

A

D8175

SM-201

RB521ZS-30

K

PLACE_NEAR=U8040.2:C7mm

28 55 57

ALL_SYS_PWRGD

6 3

13 18 29 34 35 57

IN

1

R8185

0

5% 1/20W MF 0201

2

PLACE_NEAR=U7600.16:6mm

NO STUFF

1

C8185

0.22UF

10% 10V

2

CERM 402

PLACE_NEAR=U7600.16:6mm

PM_SLP_SUS_L

PM_SLP_S4_L

Run (S0)

Sleep (S3AC)

Sleep (S3)

Deep Sleep (S4AC)

Deep Sleep (S4)

Deep Sleep (S5AC)

Deep Sleep (S5)

Battery Off (G3HotAC)

Battery Off (G3Hot)

S0 Enables

PP3V3_SUS

1

R8133

100K

5% 1/20W MF 201

2

13 62

OUT

State

1

2

PLACE_NEAR=U8030.2:6mm

P3V3S0_EN_D

R8184

330

5% 1/20W MF 201

OUT

1

R8111

20K

5% 1/20W MF 201

2

PLACE_NEAR=U7400.16:6mm

1

C8111

0.1UF

20% 10V

2

CERM 402

PLACE_NEAR=U7400.16:6mm

SMC_ADAPTER_EN

X

1

0

1

0

1

0

toggle 3Hz

1

RB521ZS-30

PLACE_NEAR=U8030.2:6mm

8

11 14 18 44 55 56 57 60 62

13 40 57

56 57

S3 Enables

1

R8116

0

5% 1/20W MF 0201

2

PLACE_NEAR=U7820.2:6mm

NO STUFF

1

2

PLACE_NEAR=U7820.2:6mm

Mobile System Power State Table

D8184

SM-201

K A

56 57

55 57

51 57

C8116

0.47UF

10%

6.3V CERM-X5R 402

SMC_PM_G2_ENABLE

1

0

1

R8186

20K

5% 1/20W MF 201

2

PLACE_NEAR=U8030.2:6mm

1

C8186

0.1UF

20% 10V

2

CERM 402

PLACE_NEAR=U8030.2:6mm

SYNC_MASTER=J43_MLB

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

1

R8112

0

5% 1/20W MF 0201

2

PLACE_NEAR=U8010.D2:6mm

P3V3S3_EN

MAKE_BASE=TRUE

P1V8S3_EN

MAKE_BASE=TRUE

DDRREG_EN

MAKE_BASE=TRUE

NO STUFF

1

C8112

0.47UF

10%

6.3V

2

CERM-X5R 402

PLACE_NEAR=U8010.D2:6mm

SMC_S4_WAKESRC_EN

1

0

1

R8187

0

5% 1/20W MF 0201

2

PLACE_NEAR=U8080.2:6mm

P5VS0_EN P5VS0_EN

56 57

MAKE_BASE=TRUE

P3V3S0_EN

56 57

MAKE_BASE=TRUE

P1V05S0_EN P1V05S0_EN

53 57

MAKE_BASE=TRUE

NO STUFF

1

C8187

0.68UF

10%

6.3V

2

CERM 402

PLACE_NEAR=U8080.2:6mm

P3V3S3_EN

P1V8S3_EN

DDRREG_EN

PM_SUS_EN

1

0

PM_SLP_S3_BUF_L PM_SLP_S3_BUF_L

P3V3S0_EN

CHGR VFRQ Generation

PP3V42_G3H

17 30 33 34 35 36 38 44 46 47 48 57 59 60 62 63

R8131

VFRQ Low: Fix Frequency

VFRQ High: Variable Frequency

Q8131

DMN32D2LFB4

DFN1006H4-3

SYM_VER_2

PM_SLP_S3_R_L

57

1

Power Control

Apple Inc.

R

1

11

1

0

330K

1/20W

201

G S

1

5%

MF

2

D

OUT

CHGR_VFRQ

3

2

56 57

55 57

51 57

PM_SLP_S3_LPM_SLP_S4_LPM_SLP_S5_L

1

0

28 55 57

OUT

28 55 57

OUT

56 57

OUT

56 57

OUT

53 57

OUT

SYNC_DATE=09/16/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

81 OF 120

SHEET

57 OF 73

124578

D

1

0

C

B

48

A

SIZE

D

8 7 6 5 4 3

12

D

1

R8363

4.7K

5% 1/20W MF 201

2

SMBUS_SMC_0_S0_SDA

35 38 71

BI

SMBUS_SMC_0_S0_SCL

35 38 71

IN

C

1

2

3

ON

VIN_1

VIN_2

CRITICAL

U8300

FPF1009

MFET-2X2-8IN

GND

6

VOUT_1

VOUT_2

THRM

PAD

7

4

5

C8311

0.1UF

CERM-X5R

PP3V3_S0SW_LCD_R

1

C8312

10UF

10%

6.3V

0201

20%

6.3V

2

X5R 603

Sense resistor on

41 41

PP3V3_S5

8

11 13 15 16 17 18 28 29 40

52 55 56 57 60 62 72

EDP_PANEL_PWR

13

IN

1

C8309

0.1UF

10%

6.3V

2

CERM-X5R 0201

13

OUT

sensor page

5

65

BI

5

65

BI

5

65

IN

5

65

IN

DP_INT_HPD

PP3V3_S0SW_LCD

C8324

DP_INT_AUXCH_C_N

DP_INT_AUXCH_C_P

C8320

DP_INT_ML_C_P<0>

DP_INT_ML_C_N<0>

B

0.1UF

10% 16V

X5R-CERM

0201

0.1UF

10% 16V

X5R-CERM

0201

1

R8364

4.7K

5% 1/20W MF 201

2

1

R8370

1M

5% 1/20W MF 201

2

PPHV_S0SW_LCDBKLT

54 60 62

LED_RETURN_6

54 62

OUT

LED_RETURN_5

54 62

OUT

LED_RETURN_4

54 62

OUT

LED_RETURN_3

54 62

OUT

LED_RETURN_2

54 62

OUT

LED_RETURN_1

54 62

OUT

DP_INT_HPD_CONN

62

PP3V3_S0SW_LCD_UF

62

MIN_LINE_WIDTH=0.30 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V

DP_INT_AUX_CH_C_N

62 65

DP_INT_AUX_CH_C_P

62 65

DP_INT_ML_P<0>

62 65

DP_INT_ML_N<0>

62 65

PLACE_NEAR=J8300.24:1mm

R8318

1/20W

1

1M

5%

MF

201

2

PLACE_NEAR=J8300.25:1mm

1

R8317

1M

5%

1/20W

MF

201

2

PLACE_NEAR=J8300.3:2mm

C8317

1000PF

R8361

0

21

I2C_TCON_SDA_R

62

5%

1/20W

MF

0201

R8362

0

21

I2C_TCON_SCL_R

62

5%

1/20W

MF

0201

21

C8325

0.1UF

10% 16V

X5R-CERM

0201

C8321

0.1UF

10% 16V

X5R-CERM

0201

21

(DP_INT_AUX_CH_C_N)

(DP_INT_AUX_CH_C_P)

Pull-ups on panel side,

4.7 kOhm to 3.3V

L8304

FERR-120-OHM-1.5A

21

0402-LF

C8315

1000PF

10% 16V

X7R-CERM

0201

PLACE_NEAR=J8300.14:2mm

R8350

100K

1/20W

R8360

0

21

5%

1/20W

MF

0201

1

2

1

R8380

1M

5%

5% 1/20W

MF

201

2

LCD Connector

Internal DP Connector: 518S0829

CRITICAL

J8300

20525-130E-01

F-RT-SM

31

1

2

NC

3

4

5

NC

6

7

8

LED Backlight I/F

9

10

11

12

NC

13

14

15

16

DisplayPort I/F

17

18

19

20

21

22

23

24

25

26

27

NC

28

NC

29

30

33

34

35

36

37

38

39

40

41

32

1

5%

50V

2

C0G-CERM

603

D

C

B

A

SYNC_MASTER=J43_MLB

PAGE TITLE

Internal DisplayPort Connector

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

6 3

SYNC_DATE=09/11/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

83 OF 120

SHEET

58 OF 73

124578

SIZE

A

D

8 7 6 5 4 3

12

D

LIO Connector

516S1036 (HIROSE 3.0mm RCPT)

CRITICAL

J9500

DF40CG3.0-48DS-0.4V

F-ST-SM

50

NOSTUFF

BYPASS=J9500:1.5mm

GND_VOID=TRUE

CRITICAL

2

D9510

ESD0P2RF-02LS

TSSLP-2-1

1

R9500

0

5%

1/20W

MF

0201

21

VOLTAGE=5V MIN_LINE_WIDTH=0.1MM MIN_NECK_WIDTH=0.1MM

C9520

0.1UF

10% 16V

X5R-CERM

0201

BYPASS=J9500:1.5mm

1

2

1

C9500

0.1UF

10% 16V

2

X5R-CERM

0201

GND_VOID=TRUE

CRITICAL

D9520

ESD0P2RF-02LS

TSSLP-2-1

PP5V_S0

16 17 32 43 49 50 54 56 57 60 62

C

USB3_EXTB_D2R_N

14 63 66

OUT

USB3_EXTB_D2R_P

14 63 66

OUT

USB3_EXTB_R2D_C_N

14 63 66

IN

USB3_EXTB_R2D_C_P

14 63 66

IN

GND_VOID=TRUE

1/20W

C9521

C9522

5%

15PF

5%

0.1UF

R9510

0

NOSTUFF

C9531

NOSTUFF

C9532

R9520

0

21

0201

MF

21 5%

NP0-CERM

25V

21 5%

25V

21

MF

21

16V

10%

X5R-CERM

21

16V

10%

X5R-CERM

NP0-CERM

0201

GND_VOID=TRUE

0201

ESD0P2RF-02LS

CRITICAL

D9511

TSSLP-2-1

2

1

AUD_PWR_EN

13 57 63

IN

PP5V_S0_ALT_AUD_LDO_EN

63

SPKRAMP_SHDN_L

45 63

OUT

PP1V5_S0SW_AUDIO

56 63

PP3V3_S0

SPKRAMP_INR_N

45 63 72

OUT

SPKRAMP_INR_P

45 63 72

OUT

USB3_EXTB_D2R_RC_N

63 66

USB3_EXTB_D2R_RC_P

63 66

USB_EXTB_N

14 63 66

BI

USB_EXTB_P

14 63 66

BI

USB3_EXTB_R2D_N

63 66

USB3_EXTB_R2D_P

63 66

CRITICAL

2

1

GND_VOID=TRUE

D9521

ESD0P2RF-02LS

TSSLP-2-1

GND_VOID=TRUE

2

4

6 8 7

10 12 11

14 13

16 15

20

22 21 24 23

26 25

28 27 30

32 31

36 35

38 37 40

42 41

44 43 46 45

48 47

52 51

49

60 62 63 46 47 48 57 35 36 38 44

1

17 30 33 34

3

SMBUS_SMC_2_S3_SCL

5

SMBUS_SMC_2_S3_SDA

9

SYS_ONEWIRE SMC_BC_ACOK XDP_USB_EXTB_OC_L

19

USB_PWR_EN FINSTACKSNS_ALERT_L

HDA_SYNC

29

HDA_RST_L

39

HDA_SDOUT HDA_SDIN0 HDA_BIT_CLK

PP3V42_G3H

NOSTUFF

C9550

10PF

C0G-CERM

35 38 63 71

IN

35 38 63 71

BI

35 63

BI

35 36 48 63

OUT

14 16 63

OUT

33 57 63

IN

37 63

OUT

12 63 67

IN

12 63 67

IN

12 63 67

IN

12 63 67

OUT

12 63 67

IN

1

5%

50V

2

0402

1

C9510

0.1UF

10% 16V

2

X5R-CERM 0201

BYPASS=J9500:1.5mm

C

SIZE

B

A

D

B

A

SYNC_MASTER=CLEAN_J41

PAGE TITLE

LIO Connector

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

6 3

SYNC_DATE=11/13/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

95 OF 120

SHEET

59 OF 73

124578

8 7 6 5 4 3

60 62

PPBUS_G3H

27 39 40 47 48 54

62

PPBUS_S5_HS_COMPUTING_ISNS

39 49 50 51 53 60

D

PPBUS_S5_HS_OTHER_ISNS

39 52 60 62

PPDCIN_G3H_ISOL

40 47 48 60 62

PPDCIN_G3H

47 48 60 62

59 60 62 38 44 46

PP3V42_G3H

17 30 33 34 35 36 47 48 57 63

C

PPVRTC_G3H

8

12 13

17 60 62

"G3Hot" (Always-Present) Rails

PPBUS_G3H

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=8.6V MAKE_BASE=TRUE

PPBUS_G3H PPBUS_G3H

PPBUS_G3H

PPBUS_G3H PPBUS_G3H

PPBUS_S5_HS_COMPUTING_ISNS

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=8.6V MAKE_BASE=TRUE

PPBUS_S5_HS_COMPUTING_ISNS

PPBUS_S5_HS_OTHER_ISNS

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=8.6V MAKE_BASE=TRUE

PPBUS_S5_HS_OTHER_ISNS

PPDCIN_G3H_ISOL

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=18.5V MAKE_BASE=TRUE

PPDCIN_G3H_ISOL

PPDCIN_G3H

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=18.5V MAKE_BASE=TRUE

PPDCIN_G3H

PP3V42_G3H

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.42V MAKE_BASE=TRUE

PP3V42_G3H

PP3V42_G3H PP3V42_G3H

PP3V42_G3H

PP3V42_G3H PP3V42_G3H

PP3V42_G3H

PP3V42_G3H PP3V42_G3H

PPVRTC_G3H

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3V MAKE_BASE=TRUE

PPVRTC_G3H

27 39 40 47 48 54 60 62

39 49 50 51 53 60 62

39 52 60 62

40 47 48 60 62

47 48 60 62

17 30 33 34 35 36 38 44 46 47 48 57 59 60 62 63

17 30 33 34 35 36 38 44 46 47

48 57 59 60 62 63 62 63 17 30 33 34 35 36 38 44 46 47

48 57 59 60 62 63 17 30 33 34 35 36 38 44 46 47

17 30 33 34 35 36 38 44 46 47 48 57 59 60 62 63

8

12 13 17 60 62

17 60 62 8

12 13

8

11 13 15 16 17 18 28 29 40

52 55 56 57 58 60 62 72

25 26 27 29 34 36 37 56 60 62

8

11 14 18 44 55 56 57 60 62

48 57 59 60

15 18 19 34 38 39 56 60 62 63

59 60 62 63 72 8

11 12 13 15 17 18 26 30 34

36 37 38 39 40 41 42 43 54 57

PP3V3_S5

PP3V3_SUS

PP3V3_S3

PP3V3_S0

PP3V3_S4

5V Rails

PP5V_S5

34 51 52 60

B

32 33 45 47 52 53 56 60 62

16 17 32 43 49 50 54 56 57 59 60 62

PP5V_S4RS3

PP5V_S0

A

PP5V_S5

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V MAKE_BASE=TRUE

PP5V_S5 PP5V_S5

PP5V_S4RS3

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.175 MM VOLTAGE=5V MAKE_BASE=TRUE

PP5V_S4RS3 PP5V_S4RS3

PP5V_S4RS3

PP5V_S4RS3 PP5V_S4RS3

PP5V_S4RS3

PP5V_S0

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V MAKE_BASE=TRUE

PP5V_S0

PP5V_S0 PP5V_S0

PP5V_S0

PP5V_S0 PP5V_S0

PP5V_S0

34 51 52 60

32 33 45 47 52 53 56 60 62

16 17 32 43 49 50 54 56 57 59 60 62

PP3V3_S4SW_SNS

3.3V Rails

PP3V3_S5

MIN_LINE_WIDTH=0.5 MM VOLTAGE=3.3V MIN_NECK_WIDTH=0.2 MM

PP3V3_S5 PP3V3_S5 PP3V3_S5

PP3V3_S5

PP3V3_S5 PP3V3_S5

PP3V3_S5

PP3V3_S5 PP3V3_S5

PP3V3_S5

PP3V3_S5 PP3V3_S5

PP3V3_S5

PP3V3_S4

MIN_LINE_WIDTH=0.60MM VOLTAGE=3.3V MIN_NECK_WIDTH=0.20MM

PP3V3_S4

PP3V3_SUS

MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM

PP3V3_SUS PP3V3_SUS

PP3V3_SUS

PP3V3_SUS PP3V3_SUS

PP3V3_SUS

PP3V3_SUS PP3V3_SUS

PP3V3_S3

MIN_LINE_WIDTH=0.50MM VOLTAGE=3.3V MIN_NECK_WIDTH=0.20MM

PP3V3_S3 PP3V3_S3

PP3V3_S3

PP3V3_S3 PP3V3_S3

PP3V3_S3

PP3V3_S3 PP3V3_S3

PP3V3_S0

MIN_LINE_WIDTH=0.5 MM VOLTAGE=3.3V MIN_NECK_WIDTH=0.20MM

PP3V3_S0

PP3V3_S0 PP3V3_S0

PP3V3_S0

PP3V3_S0 PP3V3_S0

PP3V3_S0

PP3V3_S0 PP3V3_S0

PP3V3_S0

PP3V3_S0 PP3V3_S0

PP3V3_S0

PP3V3_S0 PP3V3_S0

PP3V3_S0

PP3V3_S0 PP3V3_S0

PP3V3_S0

PP3V3_S0 PP3V3_S0 PP3V3_S0

PP3V3_S0

PP3V3_S0 PP3V3_S0

PP3V3_S4SW_SNS

MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM

PP3V3_S4SW_SNS

PP3V3_S4SW_SNS PP3V3_S4SW_SNS

PP3V3_S4SW_SNS

PP3V3_S4SW_SNS PP3V3_S4SW_SNS

PP3V3_S4SW_SNS

MAKE_BASE=TRUE

VOLTAGE=3.3V MAKE_BASE=TRUE

MAKE_BASE=TRUE

VOLTAGE=3.3V MAKE_BASE=TRUE

8

11 13 15 16 17 18 28 29 40 52

55 56 57 58 60 62 72

8

11 13 15 16 17 18 28 29 40 52

55 56 57 58 60 62 72 8

11 13 15 16 17 18 28 29 40 52

55 56 57 58 60 62 72 8

11 13 15 16 17 18 28 29 40 52

55 56 57 58 60 62 72 8

11 13 15 16 17 18 28 29 40 52

55 56 57 58 60 62 72 8

11 13 15 16 17 18 28 29 40 52

55 56 57 58 60 62 72 8

11 13 15 16 17 18 28 29 40 52

55 56 57 58 60 62 72 8

11 13 15 16 17 18 28 29 40 52

55 56 57 58 60 62 72 8

11 13 15 16 17 18 28 29 40 52

55 56 57 58 60 62 72 8

11 13 15 16 17 18 28 29 40 52

55 56 57 58 60 62 72 8

11 13 15 16 17 18 28

29 40 52 55 56 57 58 60 62 72 8

11 13 15 16 17 18 28 29 40 52

55 56 57 58 60 62 72 8

11 13 15 16 17 18 28 29 40 52

55 56 57 58 60 62 72 8

11 13 15 16 17 18 28 29 40 52

55 56 57 58 60 62 72 8

11 13 15 16 17 18 28 29 40 52

55 56 57 58 60 62 72 8

11 13 15 16 17 18 28 29 40 52

55 56 57 58 60 62 72 8

11 13 15 16 17 18 28 29 40 52

55 56 57 58 60 62 72

8

11 13 15 16 17 18 28 29 40 52

55 56 57 58 60 62 72 8

11 13 15 16 17 18 28 29 40 52

55 56 57 58 60 62 72 8

11 13 15 16 17 18 28 29 40 52

55 56 57 58 60 62 72 8

11 13 15 16 17 18 28 29 40 52

55 56 57 58 60 62 72

8

11 13 15 16 17 18 28 29 40 52

55 56 57 58 60 62 72

25 26 27 29 34 36 37 56 60 62

8

11 14 18 44 55 56 57 60 62

8

11 14 18 44 55 56 57 60 62

8

11 14 18 44 55 56 57 60 62

8

11 14 18 44 55 56 57 60 62

8

11 14 18 44 55 56 57 60 62

8

11 14 18 44 55 56 57 60 62

8

11 14 18 44 55 56 57 60 62

8

11 14 18 44 55 56 57 60 62

8

11 14 18 44 55 56 57 60 62

15 18 19 34 38 39 56 60 62 63

15 18 19 34 38 39 56 60 62 63 60 62 63 72

8

11 12 13 15 17 18 26 30 34 36

37 38 39 40 41 42 43 54 57 59

60 62 63 72 8

11 12 13 15 17 18 26 30 34 36

37 38 39 40 41 42 43 54 57 59

72 39 40 41 42 43 54 57 59 60 62 8

11 12 13 15 17 18 26 30 34 36

43 54 57 59 60 62 63 72 8

11 12 13 15 17 18 26 30 34 36

37 38 39 40 41 42 60 62 63 72 8

11 12 13 15 17 18 26 30 34 36

37 38 39 40 41 42 43 54 57 59 43 54 57 59 60 62 63 72

15 17 18 26 30 34 36 37 38 39 12

57 59 60 62 63 72

8

36 37 38 39 40 41 42 43 54

11

11 12 13 15 17 18 26 30 34

13

8 38 39 40 41 42 43 54 57 59 60 12 13 15 17 18 26 30 34 36 8

57 59 60 62 63 72

11

36 37 38 39 40 41 42 43 54

37

8

11 12 13 15 17 18 26 30 34 72 39 40 41 42 43 54 57 59 60 62 8

11 12 13 15 17 18 26 30 34 36

43 54 57 59 60 62 63 72 8

11 12 13 15 17 18 26 30 34 36

60 62 63 72 8

11 12 13 15 17 18 26 30 34 36

37 38 39 40 41 42 43 54 57 59 8

11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57 59 62 63 72

60 62 63 72 8

11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57 59

59 60 62 63 72 8

11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57

57 59 60 62 63 72

36 37 38 39 40 41 42 43 54

8

11 12 13 15 17 18 26 30 34 72 39 40 41 42 43 54 57 59 60 62 8

11 12 13 15 17 18 26 30 34 36

43 54 57 59 60 62 63 72 8

11 12 13 15 17 18 26 30 34 36

60 62 63 72 8

11 12 13 15 17 18 26 30 34 36

37 38 39 40 41 42 43 54 57 59 43 54 57 59 60 62 63 72

15 17 18 26 30 34 36 37 38 39 12

57 59 60 62 63 72

8

36 37 38 39 40 41 42 43 54

11

11 12 13 15 17 18 26 30 34

13

8 39 40 41 42 43 54 57 59 60 62 12 13 15 17 18 26 30 34 36 37 8

57 59 60 62 63 72

11

36 37 38 39 40 41 42 43 54

38

8

11 12 13 15 17 18 26 30 34 72 39 40 41 42 43 54 57 59 60 62 8

11 12 13 15 17 18 26 30 34 36

43 54 57 59 60 62 63 72 8

11 12 13 15 17 18 26 30 34 36

60 62 63 72 8

11 12 13 15 17 18 26 30 34 36

37 38 39 40 41 42 43 54 57 59

39 40 41 56 60

40 41 42

62 63 72

37 38 39 40 41 42

11 15 16 17 36 40 49 53

37 38 39 40 41 42

40 41 42

63 72

37 38 39 40 41 42

11 56 60

30 39 60 62

PP3V3_S4_TBTAPWR

28 60

PP1V8_S3

20 21 22 23 55 60

2A max supply

PP1V2_S3

17 19 20 21 22 23 40 51 60 68

PP1V05_SUS

PP1V5_S0

37 38

63

PP0V6_S0_DDRVTT

37 38

63

60

PP1V05_S0

6 8 56 57 60 62

? mA

37 38

63

37 38

63

PP1V05_S0SW_PCH_HSIO

8

1.84A

PP3V3_S0SW_SSD

MIN_LINE_WIDTH=0.5 MM VOLTAGE=3.3V MIN_NECK_WIDTH=0.20MM

PP3V3_S0SW_SSD

PP3V3_S4_TBTAPWR

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM

1.8V/1.5V/1.2V/1.05V Rails

PP1V8_S3

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=1.2V MAKE_BASE=TRUE

PP1V8_S3

PP1V2_S3

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.1 MM VOLTAGE=1.2V MAKE_BASE=TRUE

PP1V2_S3

PP1V2_S3 PP1V2_S3

PP1V2_S3

PP1V05_SUS

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE

PP1V05_SUS

PP1V5_S0

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=1.5V MAKE_BASE=TRUE

PP1V5_S0 PP1V5_S0

PP1V5_S0

PP0V6_S0_DDRVTT

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=0.75V MAKE_BASE=TRUE

PP0V6_S0_DDRVTT PP0V6_S0_DDRVTT

PP1V05_S0

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.175 MM VOLTAGE=1.05V MAKE_BASE=TRUE

PP1V05_S0 PP1V05_S0

PP1V05_S0

PP1V05_S0 PP1V05_S0

PP1V05_S0

PP1V05_S0 PP1V05_S0

PP1V05_S0

PP1V05_S0SW_PCH_HSIO

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE

PP1V05_S0SW_PCH_HSIO PP1V05_S0SW_PCH_HSIO

MAKE_BASE=TRUE

VOLTAGE=3.3V MAKE_BASE=TRUE

30 39 60 62

28 60

20 21 22 23 55 60

17 19 20 21 22 23 40 51 60 68

16 55 60

8

55 56 57 60 62

8

55 56 57 60 62

8

55 56 57 60 62

8

55 56 57 60 62

24 51 60

6 8

11 15 16 17 36 40 49 53 56

57 60 62

6 8

11 15 16 17 36 40 49 53 56

57 60 62 6 8

11 15 16 17 36 40 49 53 56

57 60 62 6 8

11 15 16 17 36 40 49 53 56

57 60 62 6 8

11 15 16 17 36 40 49 53 56

57 60 62 6 8

11 15 16 17 36 40 49 53 56

57 60 62 6 8

11 15 16 17 36 40 49 53 56

57 60 62 6 8

11 15 16 17 36 40 49 53 56

57 60 62

6 8

11 15 16 17 36 40 49 53 56

57 60 62 6 8

11 15 16 17 36 40 49 53 56

57 60 62 6 8

11 15 16 17 36 40 49 53 56

57 60 62 6 8

11 15 16 17 36 40 49 53 56

57 60 62 6 8

11 15 16 17 36 40 49 53 56

57 60 62 6 8

11 15 16 17 36 40 49 53 56

57 60 62

8

11 56 60

8

11 56 60

8

11 56 60

PPHV_S0SW_LCDBKLT

PP15V_TBT

27 28 60 62

PP3V3_TBTLC

17 18 25 26 60 62

PPVIN_S4SW_TBTBST_FET

27 62

VOLTAGE=8.6V

PPVIN_SW_TBTBST

VOLTAGE=12.8V

PPVCC_S0_CPU

8

10 40 50 60 62

LCDBKLT Rail

PPHV_S0SW_LCDBKLT

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.375 MM VOLTAGE=50V MAKE_BASE=TRUE

PPHV_S0SW_LCDBKLT

TBT Rails (off when no cable)

PP15V_TBT

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=17.8V MAKE_BASE=TRUE

PP15V_TBT

PP3V3_TBTLC

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V MAKE_BASE=TRUE

PP3V3_TBTLC

26 62

PP1V05_TBTCIO

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE

CPU "VCORE" RAILS

PPVCC_S0_CPU

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=1.8V MAKE_BASE=TRUE

PPVCC_S0_CPU PPVCC_S0_CPU

SYNC_MASTER=WILL_J43

PAGE TITLE

Power Aliases

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

6 3

12

Digital Ground

GND

VOLTAGE=0V MIN_NECK_WIDTH=0.075MM MIN_LINE_WIDTH=0.6MM

SYNC_DATE=12/17/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

100 OF 120

SHEET

60 OF 73

124578

54 58 60 62 54 58 60 62

54 58 60 62

27 28 60 62

17 18 25 26 60 62

8

10 40 50

60 62

8

10 40 50

60 62 8

10 40 50

60 62

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

Memory Bit/Byte Swizzle

LPDDR3 Command/Address

=MEM_A_A<5>

7

=MEM_A_A<9>

7

=MEM_A_A<6>

7

=MEM_A_A<8>

7

=MEM_A_A<7>

D

C

7

=MEM_A_BA<2>

7

MEM_A_CAA<6>

7

20 24 61 68

=MEM_A_A<11>

7

=MEM_A_A<15>

7

=MEM_A_A<14>

7

=MEM_A_A<13>

7

=MEM_A_CAS_L

7

=MEM_A_WE_L

7

=MEM_A_RAS_L

7

=MEM_A_BA<0>

7

=MEM_A_A<2>

7

MEM_A_CAB<6>

7

21 24 61 68

=MEM_A_A<10>

7

=MEM_A_A<1>

7

=MEM_A_A<0>

7

MEM_A_ODT<0>

7

20 21 24 61 68

TP_LPDDR3_RSVD1

7

61

TP_LPDDR3_RSVD2

7

61

=MEM_B_A<5>

7

=MEM_B_A<9>

7

=MEM_B_A<6>

7

=MEM_B_A<8>

7

=MEM_B_A<7>

7

=MEM_B_BA<2>

7

MEM_B_CAA<6>

7

22 24 61 68

=MEM_B_A<11>

7

=MEM_B_A<15>

7

=MEM_B_A<14>

7

=MEM_B_A<13>

7

=MEM_B_CAS_L

7

=MEM_B_WE_L

7

=MEM_B_RAS_L

7

=MEM_B_BA<0>

7

=MEM_B_A<2>

7

MEM_B_CAB<6>

7

23 24 61 68

=MEM_B_A<10>

7

=MEM_B_A<1>

7

=MEM_B_A<0>

7

MEM_B_ODT<0>

7

22 23 24 61 68

TP_LPDDR3_RSVD3

7

61

TP_LPDDR3_RSVD4

7

61

B

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

MEM_A_CAA<0> MEM_A_CAA<1> MEM_A_CAA<2> MEM_A_CAA<3> MEM_A_CAA<4> MEM_A_CAA<5> MEM_A_CAA<6> MEM_A_CAA<7> MEM_A_CAA<8> MEM_A_CAA<9>

MEM_A_CAB<0> MEM_A_CAB<1> MEM_A_CAB<2> MEM_A_CAB<3> MEM_A_CAB<4> MEM_A_CAB<5> MEM_A_CAB<6> MEM_A_CAB<7> MEM_A_CAB<8> MEM_A_CAB<9> MEM_A_ODT<0> TP_LPDDR3_RSVD1 TP_LPDDR3_RSVD2

MEM_B_CAA<0> MEM_B_CAA<1> MEM_B_CAA<2> MEM_B_CAA<3> MEM_B_CAA<4> MEM_B_CAA<5> MEM_B_CAA<6> MEM_B_CAA<7> MEM_B_CAA<8> MEM_B_CAA<9>

MEM_B_CAB<0> MEM_B_CAB<1> MEM_B_CAB<2> MEM_B_CAB<3> MEM_B_CAB<4> MEM_B_CAB<5> MEM_B_CAB<6> MEM_B_CAB<7> MEM_B_CAB<8> MEM_B_CAB<9> MEM_B_ODT<0> TP_LPDDR3_RSVD3 TP_LPDDR3_RSVD4

20 24 68

7

20 24 61 68

20 24 68

21 24 68

7

21 24 61 68

21 24 68

7

20 21 24 61 68

7

61

7

61

22 24 68

7

22 24 61 68

22 24 68

23 24 68

7

23 24 61 68

23 24 68

7

22 23 24 61 68

7

61

7

61

=MEM_A_DQ<0> =MEM_A_DQ<1> =MEM_A_DQ<2>

20

=MEM_A_DQ<3> =MEM_A_DQ<4>

=MEM_A_DQ<6>

20

=MEM_A_DQ<7> =MEM_A_DQ<8>

20

=MEM_A_DQ<9>

20

=MEM_A_DQ<10> =MEM_A_DQ<11>

20

=MEM_A_DQ<12> =MEM_A_DQ<13> =MEM_A_DQ<14> =MEM_A_DQ<15> =MEM_A_DQ<16>

20

=MEM_A_DQ<17> =MEM_A_DQ<18> =MEM_A_DQ<19> =MEM_A_DQ<20> =MEM_A_DQ<21> =MEM_A_DQ<22>

20

=MEM_A_DQ<23> =MEM_A_DQ<24> =MEM_A_DQ<25>

20

=MEM_A_DQ<26> =MEM_A_DQ<27> =MEM_A_DQ<28> =MEM_A_DQ<29>

20

=MEM_A_DQ<30> =MEM_A_DQ<31>

20

=MEM_A_DQ<32> =MEM_A_DQ<33>

21

=MEM_A_DQ<34>

21

=MEM_A_DQ<35>

21

=MEM_A_DQ<36> =MEM_A_DQ<37> =MEM_A_DQ<38> =MEM_A_DQ<39> =MEM_A_DQ<40> =MEM_A_DQ<41> =MEM_A_DQ<42> =MEM_A_DQ<43>

21

MEM_A_DQ<32>

7

21 61 68

=MEM_A_DQ<45>

21

=MEM_A_DQ<46>

21

=MEM_A_DQ<47> =MEM_A_DQ<48> =MEM_A_DQ<49> =MEM_A_DQ<50> =MEM_A_DQ<51> =MEM_A_DQ<52> =MEM_A_DQ<53> =MEM_A_DQ<54> =MEM_A_DQ<55> =MEM_A_DQ<56> =MEM_A_DQ<57> =MEM_A_DQ<58> =MEM_A_DQ<59> =MEM_A_DQ<60> =MEM_A_DQ<61> =MEM_A_DQ<62> =MEM_A_DQ<63>

=MEM_A_DQS_P<0> =MEM_A_DQS_N<0> =MEM_A_DQS_P<1> =MEM_A_DQS_N<1> =MEM_A_DQS_P<2> =MEM_A_DQS_N<2> =MEM_A_DQS_P<3> =MEM_A_DQS_N<3> =MEM_A_DQS_P<4> =MEM_A_DQS_N<4> =MEM_A_DQS_P<5> =MEM_A_DQS_N<5> MEM_A_DQS_P<6>

7

21 61 68

MEM_A_DQS_N<6>

7

21 61 68

=MEM_A_DQS_P<7> =MEM_A_DQS_N<7>

MAKE_BASE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

MEM_A_DQ<9> MEM_A_DQ<12> MEM_A_DQ<10> MEM_A_DQ<11> MEM_A_DQ<8> MEM_A_DQ<13>=MEM_A_DQ<5> MEM_A_DQ<14> MEM_A_DQ<15> MEM_A_DQ<0> MEM_A_DQ<1> MEM_A_DQ<2> MEM_A_DQ<7> MEM_A_DQ<4> MEM_A_DQ<5> MEM_A_DQ<3> MEM_A_DQ<6> MEM_A_DQ<29> MEM_A_DQ<28> MEM_A_DQ<27> MEM_A_DQ<31> MEM_A_DQ<24> MEM_A_DQ<25> MEM_A_DQ<26> MEM_A_DQ<30> MEM_A_DQ<18> MEM_A_DQ<21> MEM_A_DQ<16> MEM_A_DQ<23> MEM_A_DQ<20> MEM_A_DQ<19> MEM_A_DQ<22> MEM_A_DQ<17> MEM_A_DQ<41> MEM_A_DQ<44> MEM_A_DQ<46> MEM_A_DQ<47> MEM_A_DQ<40> MEM_A_DQ<45> MEM_A_DQ<42> MEM_A_DQ<43> MEM_A_DQ<36> MEM_A_DQ<37> MEM_A_DQ<34> MEM_A_DQ<39> MEM_A_DQ<32> MEM_A_DQ<33> MEM_A_DQ<35> MEM_A_DQ<38> MEM_A_DQ<52> MEM_A_DQ<51> MEM_A_DQ<48> MEM_A_DQ<49> MEM_A_DQ<53> MEM_A_DQ<50> MEM_A_DQ<54> MEM_A_DQ<55> MEM_A_DQ<58> MEM_A_DQ<62> MEM_A_DQ<60> MEM_A_DQ<61> MEM_A_DQ<59> MEM_A_DQ<63> MEM_A_DQ<57> MEM_A_DQ<56>

MEM_A_DQS_P<1> MEM_A_DQS_N<1> MEM_A_DQS_P<0> MEM_A_DQS_N<0> MEM_A_DQS_P<3> MEM_A_DQS_N<3> MEM_A_DQS_P<2> MEM_A_DQS_N<2> MEM_A_DQS_P<5> MEM_A_DQS_N<5> MEM_A_DQS_P<4> MEM_A_DQS_N<4> MEM_A_DQS_P<6> MEM_A_DQS_N<6> MEM_A_DQS_P<7> MEM_A_DQS_N<7>

7

68 20

68

68 20

68

68 20

68

68 20

68

68 20

68

68 20

68

68 20

68

68 20

68

68 20

68

68 21

68

68 21

68

21 61 68

68

68 21

68 20

68 21

21 61 68

68 21

=MEM_B_DQ<0> =MEM_B_DQ<1> =MEM_B_DQ<2> =MEM_B_DQ<3> =MEM_B_DQ<4> =MEM_B_DQ<5> =MEM_B_DQ<6>

22

=MEM_B_DQ<7> =MEM_B_DQ<8> =MEM_B_DQ<9> =MEM_B_DQ<10> =MEM_B_DQ<11> =MEM_B_DQ<12>

22

=MEM_B_DQ<13> =MEM_B_DQ<14> =MEM_B_DQ<15> =MEM_B_DQ<16> =MEM_B_DQ<17> =MEM_B_DQ<18> =MEM_B_DQ<19> =MEM_B_DQ<20> =MEM_B_DQ<21> =MEM_B_DQ<22> =MEM_B_DQ<23> =MEM_B_DQ<24> =MEM_B_DQ<25> =MEM_B_DQ<26> =MEM_B_DQ<27> =MEM_B_DQ<28>

22

=MEM_B_DQ<29> =MEM_B_DQ<30> =MEM_B_DQ<31>

22

=MEM_B_DQ<32> =MEM_B_DQ<33>

23

=MEM_B_DQ<34> =MEM_B_DQ<35>

23

=MEM_B_DQ<36>

23

=MEM_B_DQ<37>

23

=MEM_B_DQ<38>

23

=MEM_B_DQ<39>

23

=MEM_B_DQ<40>

23

MEM_B_DQ<33>

7

23 61 68

=MEM_B_DQ<42> =MEM_B_DQ<43> =MEM_B_DQ<44> =MEM_B_DQ<45> =MEM_B_DQ<46> =MEM_B_DQ<47> =MEM_B_DQ<48> =MEM_B_DQ<49> =MEM_B_DQ<50> =MEM_B_DQ<51> =MEM_B_DQ<52> =MEM_B_DQ<53> =MEM_B_DQ<54> =MEM_B_DQ<55> =MEM_B_DQ<56> =MEM_B_DQ<57> =MEM_B_DQ<58> =MEM_B_DQ<59> =MEM_B_DQ<60> =MEM_B_DQ<61> =MEM_B_DQ<62> =MEM_B_DQ<63>

=MEM_B_DQS_P<0> =MEM_B_DQS_N<0> =MEM_B_DQS_P<1> =MEM_B_DQS_N<1> =MEM_B_DQS_P<2> =MEM_B_DQS_N<2> =MEM_B_DQS_P<3> =MEM_B_DQS_N<3> =MEM_B_DQS_P<4> =MEM_B_DQS_N<4> =MEM_B_DQS_P<5> =MEM_B_DQS_N<5> =MEM_B_DQS_P<6> =MEM_B_DQS_N<6> MEM_B_DQS_P<6>

7

23 61 68

MEM_B_DQS_N<6>

7

23 61 68

MAKE_BASEMAKE_BASE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

MEM_B_DQ<12> MEM_B_DQ<9> MEM_B_DQ<10> MEM_B_DQ<11> MEM_B_DQ<13> MEM_B_DQ<8> MEM_B_DQ<14> MEM_B_DQ<15> MEM_B_DQ<0> MEM_B_DQ<1> MEM_B_DQ<2> MEM_B_DQ<7> MEM_B_DQ<4> MEM_B_DQ<5> MEM_B_DQ<6> MEM_B_DQ<3> MEM_B_DQ<28> MEM_B_DQ<29> MEM_B_DQ<30> MEM_B_DQ<27> MEM_B_DQ<24> MEM_B_DQ<25> MEM_B_DQ<31> MEM_B_DQ<26> MEM_B_DQ<20> MEM_B_DQ<16> MEM_B_DQ<23> MEM_B_DQ<22> MEM_B_DQ<21> MEM_B_DQ<17> MEM_B_DQ<18> MEM_B_DQ<19> MEM_B_DQ<44> MEM_B_DQ<41> MEM_B_DQ<42> MEM_B_DQ<43> MEM_B_DQ<45> MEM_B_DQ<40> MEM_B_DQ<46> MEM_B_DQ<47> MEM_B_DQ<32> MEM_B_DQ<33> MEM_B_DQ<34> MEM_B_DQ<39> MEM_B_DQ<36> MEM_B_DQ<37> MEM_B_DQ<38> MEM_B_DQ<35> MEM_B_DQ<57> MEM_B_DQ<56> MEM_B_DQ<60> MEM_B_DQ<59> MEM_B_DQ<63> MEM_B_DQ<62> MEM_B_DQ<58> MEM_B_DQ<61> MEM_B_DQ<49> MEM_B_DQ<51> MEM_B_DQ<48> MEM_B_DQ<53> MEM_B_DQ<52> MEM_B_DQ<55> MEM_B_DQ<50> MEM_B_DQ<54>

MEM_B_DQS_P<1> MEM_B_DQS_N<1> MEM_B_DQS_P<0> MEM_B_DQS_N<0> MEM_B_DQS_P<3> MEM_B_DQS_N<3> MEM_B_DQS_P<2> MEM_B_DQS_N<2> MEM_B_DQS_P<5> MEM_B_DQS_N<5> MEM_B_DQS_P<4> MEM_B_DQS_N<4> MEM_B_DQS_P<7> MEM_B_DQS_N<7> MEM_B_DQS_P<6> MEM_B_DQS_N<6>

7

68 22

7

68 22

7

68 22

7

68 22

7

68 22

7

68

7

68 22

7

68 22

7

68 22

7

68 22

7

68 22

7

68

7

68 22

7

68 22

7

68 22

7

68 22

7

68 22

7

68 22

7

68 22

7

68 22

7

68 22

7

68 22

7

68 22

7

68 22

7

68 22

7

68 22

7

68 22

7

68

7

68 22

7

68 22

7

68

7

68 23

7

68

7

68 23

7

68

7

68

7

68

7

68

7

68

7

68

7

23 61 68

7

68 23

7

68 23

7

68 23

7

68 23

7

68 23

7

68 23

7

68 23

7

68 23

7

68 23

7

68 23

7

68 23

7

68 23

7

68 23

7

68 23

7

68 23

7

68 23

7

68 23

7

68 23

7

68 23

7

68 23

7

68 23

7

68 23

7

68 22

7

68 22

7

68 22

7

68 22

7

68 22

7

68 22

7

68 22

7

68 22

7

68 23

7

68 23

7

68 23

7

68 23

7

68 23

7

68 23

7

23 61 68

7

23 61 68

68 22

D

C

B

A

SYNC_MASTER=MASTER

PAGE TITLE

Signal Aliases

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

6 3

SYNC_DATE=MASTER

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

102 OF 120

SHEET

61 OF 73

124578

SIZE

A

D

8 7 6 5 4 3

12

Functional Test Points

J3501: AirPort / BT Connector

FUNC_TEST FUNC_TEST

D

FUNC_TEST

C

FUNC_TEST

B

PP3V3_WLAN

TRUE

WIFI_EVENT_L

TRUE

PCIE_AP_R2D_N

TRUE

PCIE_AP_R2D_P

TRUE

PCIE_CLK100M_AP_N

TRUE

PCIE_CLK100M_AP_P

TRUE

PCIE_AP_D2R_P

TRUE

PCIE_AP_D2R_N

TRUE

PCIE_WAKE_L

TRUE

AP_RESET_CONN_L

TRUE

AP_CLKREQ_Q_L

TRUE

USB_BT_CONN_P

TRUE

USB_BT_CONN_N

TRUE

PP3V3_S4

TRUE

(Need to add 8 GND TPs)

J3700: SSD Connector

PP3V3_S0SW_SSD_FLT

TRUE

PCIE_SSD_R2D_N<3..0>

TRUE

PCIE_SSD_R2D_P<3..0>

TRUE

PP3V3_S0

TRUE

SSD_RESET_CONN_L

TRUE

SSD_CLKREQ_CONN_L

TRUE

SMC_OOB1_R2D_CONN_L

TRUE

SMC_OOB1_D2R_CONN_L

TRUE

SSD_PCIE_SEL_L

TRUE

SSD_SR_EN_L

TRUE

SMC_PWRFAIL_WARN_L

TRUE

SSD_PWR_EN

TRUE

PCIE_SSD_D2R_N<3..0>

TRUE

PCIE_SSD_D2R_P<3..0>

TRUE

PCIE_CLK100M_SSD_N

TRUE

PCIE_CLK100M_SSD_P

TRUE

(Need to add 6 GND TPs)

J4002: Camera Connector

MIPI_CLK_CONN_N

TRUE

MIPI_CLK_CONN_P

TRUE

CAM_SENSOR_WAKE_L_CONN

TRUE

MIPI_DATA_CONN_N

TRUE

MIPI_DATA_CONN_P

TRUE

SMBUS_SMC_1_S0_SDA

TRUE

SMBUS_SMC_1_S0_SCL

TRUE

I2C_CAM_SCK

TRUE

I2C_CAM_SDA

TRUE

PP5V_S3RS0_ALSCAM_F

TRUE

(Need to add TBD GND TPs)

J6100: LPC+SPI Connector

FUNC_TEST

SPI_ALT_IO3_HOLD_L

TRUE

SPI_ALT_IO2_WP_L

TRUE

LPC_AD<3..0>

TRUE

SPI_ALT_IO0_MOSI

TRUE

XDP_LPCPLUS_GPIO

TRUE

LPCPLUS_RESET_L

TRUE

SMC_TDO

TRUE

TP_SMC_TRST_L

TRUE

TP_SMC_MD1

TRUE

SMC_TX_L

TRUE

SPI_ALT_IO1_MISO

TRUE

LPC_FRAME_L

TRUE

SPIROM_USE_MLB

TRUE

PM_CLKRUN_L

TRUE

SPI_ALT_CLK

TRUE

SPI_ALT_CS_L

TRUE

LPC_SERIRQ

TRUE

LPC_PWRDWN_L

TRUE

SMC_TDI

TRUE

SMC_TCK

TRUE

SMC_RESET_L

TRUE

SMC_ROMBOOT

TRUE

SMC_RX_L

TRUE

SMC_TMS

TRUE

(Need to add 6 GND TPs)

(Need 6 TPs)

(Need 5 TPs)

(Need TBD TPs)

29 35 36 37 39

29 35 36

29 67

12 29 67

14 29 67

13 29 31

29

29 66

25 26 27 29 34 36 37 56 60 62

30

30 65

30 65 40 41 42 43 54 57 59

8

11 12 13 15 17 18 26 30 34 36 37 38 39 60 62 63 72

30

15 30

30 35

15 30 56 57

12 30 65

32 70

32

32 70

14 32 35 38 41 42 67 71

31 32

32

44

14 35 67

44

15 16

67

35 36

44

14 35 67

15 44

13 35

44

15 35

13 35

35 36

35 36 44

35 36 44 48

35 36

35 36 44

A

GND

TRUE

I793

J6000: Fan Connector

FUNC_TEST

I776

I777

I778

I779

I780

I781

I782

I783

I784

I785

I786

I787

I788

I789

I790

I791

I792

PP5V_S0

TRUE

FAN_RT_TACH

TRUE

FAN_RT_PWM

TRUE

(Need to add 1 GND TP)

J4800: IPD Flex Connector

SMC_LID

TRUE

TPAD_SPI_MISO_R

TRUE

USB_TPAD_P

TRUE

USB_TPAD_N

TRUE

TPAD_SPI_CLK_R

TRUE

TPAD_WAKE_L

TRUE

TPAD_SPI_MOSI_R

TRUE

PP3V3_S4_IPD

TRUE

TPAD_SPI_CS_R_L

TRUE

TPAD_SPI_IF_EN_CONN

TRUE

TPAD_SPI_INT_S4_WAKE_L_CONN

TRUE

PP5V_S4_IPD

TRUE

TPAD_USB_IF_EN_CONN

TRUE

SMBUS_SMC_3_SDA

TRUE

SMBUS_SMC_3_SCL

TRUE

SMC_LSOC_RST_L

TRUE

PP3V42_G3H

TRUE

SMC_ONOFF_L

TRUE

(Need to add 5 GND TPs)

J7000: DC-In Connector

PPDCIN_G3H

TRUE

PP5V_S4RS3

TRUE

(Need to add 5 GND TPs)

J6404: Speaker Connector

SPKRAMP_ROUT_P

TRUE

SPKRAMP_ROUT_N

TRUE

(Need to add 3 GND TPs)

J6950: Battery Connector

PPVBAT_G3H_CONN

TRUE

SMBUS_SMC_5_G3_SCL

TRUE

SMBUS_SMC_5_G3_SDA

TRUE

SYS_DETECT_L

TRUE

(Need to add 4 GND TPs near

J7050 and 1 for shield)

J8300: Internal DP Connector

PPHV_S0SW_LCDBKLT

TRUE

LED_RETURN_6

TRUE

LED_RETURN_5

TRUE

LED_RETURN_4

TRUE

LED_RETURN_3

TRUE

LED_RETURN_2

TRUE

LED_RETURN_1

TRUE

DP_INT_HPD_CONN

TRUE

I2C_TCON_SDA_R

TRUE

I2C_TCON_SCL_R

TRUE

PP3V3_S0SW_LCD_UF

TRUE

DP_INT_AUX_CH_C_N

TRUE

DP_INT_AUX_CH_C_P

TRUE

DP_INT_ML_P<0>

TRUE

DP_INT_ML_N<0>

TRUE

(Need to add 5 GND TPs)

J7715: KB BKLT Connector

KBDLED_ANODE

TRUE

KBDLED_FB

TRUE

(Need to add 2 GND TPs)

J1800: XDP Connector

XDP_CPU_TCK

TRUE

XDP_PCH_TCK

TRUE

XDP_CPU_TDI

TRUE

XDP_CPU_TDO

TRUE

XDP_CPUPCH_TRST_L

TRUE

XDP_CPU_TMS

TRUE

XDP_PCH_TMS

TRUE

XDP_PCH_TDI

TRUE

XDP_PCH_TDO

TRUE

XDP_CPU_PREQ_L

TRUE

XDP_CPU_PRDY_L

TRUE

XDP_CPU_VCCST_PWRGD

TRUE

PM_RSMRST_L

TRUE

XDP_SYS_PWROK

TRUE

PM_SYSRST_L

TRUE

CPU_CFG<3>

TRUE

PP1V05_S0

TRUE

(Need to add 2 GND TPs)

16 17 32 43 49 50 54 56 57 59 60

43

34 35 36 46

34

14 34 66

34

34 35 38 42 71

34 36

17 30 33 34 35 36 38 44 46 47 48 57 59 60 62 63

34 35 36

(Need 4 TPs) (Need 3 TPs)

(Need 4 TPs)

(Need 2 TPs)

(Only a subset are needed

for FCT HVM test fixture)

47 48 60 62

32 33 45 47 52 53 56 60

45 72

46 48

35 38 46 48 71

46

(Need 2 TPs)

54 58 60

54 58

58

58 65

54

6

12 16 67

6

12 16 67

6

16

13 57

16

13 17 35

6

6 8 57 60 62

16 65

12 16 65

16 65

11 15 16 17 36 40 49 53 56

Misc Voltages & Control Signals

PPBUS_G3H

TRUE

PPVIN_S4SW_TBTBST_FET

TRUE

PPBUS_S5_HS_COMPUTING_ISNS

TRUE

PPDCIN_G3H

TRUE

PP3V42_G3H

TRUE

PPVRTC_G3H

TRUE

PP3V3_S5

TRUE

PP3V3_SUS

TRUE

PP3V3_S3

TRUE

PP3V3_S0

TRUE

PP3V3_S0SW_SSD

TRUE

PP1V5_S0

TRUE

PP1V05_S0

TRUE

PP15V_TBT

TRUE

PP3V3_TBTLC

TRUE

PP1V05_TBT

TRUE

PPVCC_S0_CPU

TRUE

PP1V05_TBTCIO

TRUE

PPBUS_S5_HS_OTHER_ISNS

TRUE

PPDCIN_G3H_ISOL

TRUE

PP3V3_S4

TRUE

(Need to add 27 GND TPs)

27 39 40 47 48 54 60

27 60

39 49 50 51 53 60

47 48 60 62

17 30 33 34 35 36 38 44 46 47 48 57 59 60 62 63

8

12 13 17 60

8

11 13 15 16 17 18 28 29 40 52

55 56 57 58 60 72 8

11 14 18 44 55 56 57 60

15 18 19 34 38 39 56 60 63 60 62 63 72

8

11 12 13 15 17 18 26 30 34 36

37 38 39 40 41 42 43 54 57 59 30 39 60

8

55 56 57 60

6 8

11 15 16 17 36 40 49 53 56

57 60 62 27 28 60

17 18 25 26 60

26

8

10 40 50 60

26 60

39 52 60

40 47 48 60

25 26 27 29 34 36 37 56 60 62

Unused nets with offpage

(Nets with offpages not used on this project)

PCH_BT_UART_D2R PCH_BT_UART_R2D PCH_BT_UART_RTS_L PCH_BT_UART_CTS_L AUD_SPI_CS_L AUD_SPI_CLK AUD_SPI_MISO AUD_SPI_MOSI HDMITBTMUX_LATCH HDD_PWR_EN WOL_EN BT_PWRRST_L HDMITBTMUX_FLAG FW_PWR_EN FW_PME_L ENET_MEDIA_SENSE LCD_PSR_EN LCD_IRQ_L ODD_PWR_EN_L ENET_LOW_PWR AUD_IP_PERIPHERAL_DET AUD_I2C_INT_L AP_PCIE_DEV_WAKE

NC_PCIE_FW_D2RP NC_PCIE_FW_D2RN

NC_PCIE_FW_R2D_CN

NC_USB_CAMERAP

DP_INT_ML_C_P<3..1>

65

DP_INT_ML_C_N<3..1>

65

NC_PCI_PME_L

13 62

NC_CLINK_DATA

14 62

NC_CLINK_RESET_L

14 62

NC_USB_SMCP NC_USB_SMCN NC_SMC_GFX_OVERTEMP NC_SMC_GFX_THROTTLE_L NC_SMC_FAN_1_CTL

35 62

NC_SMC_FAN_1_TACH NC_SMC_FAN_5_CTL NC_ENET_ASF_GPIO

62

NC_SMC_MPM5_LED_PWR

NC_SMC_T25_EN_L

35 62

NC_SMC_DP_HPD_L

NC_SMBUS_SMC_4_ASF_SDA

35 62

TBT_B_R2D_C_P<1..0>

69 25

TBT_B_R2D_C_N<1..0>

69 25

TBT_B_D2R_P<1..0>

69 25

TBT_B_D2R_N<1..0>

69 25

NC_TBT_B_LSTX

25 62 25 62

NC_DP_TBTPB_ML_CP<3..1:2>

62 69 62 69

NC_DP_TBTPB_ML_CN<3..1:2>

62 69 62 69

NC_DP_TBTPB_AUXCH_CP

25 62 69 25 62 69

NC_DP_TBTPB_AUXCH_CN NC_DP_TBTPB_AUXCH_CN

25 62 69 25 62 69

TP_DP_TBTSRC_ML_CP<3>

25

TP_DP_TBTSRC_ML_CN<3>

25

TP_DP_TBTSRC_ML_CP<2>

25

TP_DP_TBTSRC_ML_CN<2>

25

NC_DP_TBTSRC_ML_CP<1>

25 62

NC_DP_TBTSRC_ML_CN<1>

25 62

TP_DP_TBTSRC_ML_CP<0>

25

TP_DP_TBTSRC_ML_CN<0>

25

NC_DP_TBTSRC_AUXCH_CP

25 62

NC_DP_TBTSRC_AUXCH_CN NC_DP_TBTSRC_AUXCH_CN

25 62 25 62

15

13

15

14

15

13

15

13

6 3

NO_TEST Nets

NO_TEST

MAKE_BASE TRUE TRUE

TRUE TRUE TRUE TRUE

TRUE TRUE

TRUETRUE

TRUE TRUE

TRUE TRUE TRUE TRUE

TRUE TRUE

TRUE

TRUE TRUE TRUE

TRUE TRUE TRUE TRUE

TRUETRUE

TRUE TRUE TRUE TRUE

TRUE TRUE

TRUE TRUE TRUE TRUE

TRUE

TRUE TRUE

TRUE TRUE TRUE TRUE

TRUETRUE

TRUE TRUE

TRUETRUE

TRUE

TRUETRUE

TRUE

TRUETRUE TRUETRUE

TRUETRUE

TRUE TRUE

TRUE TRUE TRUE TRUE

TRUE TRUE

TRUE TRUE TRUE TRUE

TRUE TRUE

TRUE TRUE TRUE TRUE

TRUE TRUE

TRUE TRUE TRUE TRUE

TRUE TRUE

TRUE

TRUE TRUE TRUE TRUE

SYNC_MASTER=WILL_J43 SYNC_DATE=12/17/2012

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

NC_PCIE_CLK100M_SDPNC_PCIE_CLK100M_SDP NC_PCIE_CLK100M_SDNNC_PCIE_CLK100M_SDN NC_PCIE_CLK100M_FWPNC_PCIE_CLK100M_FWP NC_PCIE_CLK100M_FWNNC_PCIE_CLK100M_FWN NC_PCIE_FW_D2RP NC_PCIE_FW_D2RN NC_PCIE_FW_R2D_CPNC_PCIE_FW_R2D_CP NC_PCIE_FW_R2D_CN NC_USB_IRPNC_USB_IRP NC_USB_IRNNC_USB_IRN NC_USB_CAMERAP NC_USB_CAMERANNC_USB_CAMERAN NC_USB_SDPNC_USB_SDP NC_USB_SDNNC_USB_SDN NC_INT_ML_CP<3..1> NC_INT_ML_CN<3..1> NC_HDA_SDIN1NC_HDA_SDIN1 NC_PCI_PME_L NC_CLINK_CLKNC_CLINK_CLK NC_CLINK_DATA NC_CLINK_RESET_L

NC_SMC_SYS_LEDNC_SMC_SYS_LED NC_IR_RX_OUT_RCNC_IR_RX_OUT_RC NC_USB_SMCP NC_USB_SMCN NC_SMC_GFX_OVERTEMP NC_SMC_GFX_THROTTLE_L NC_SMC_FAN_1_CTL NC_SMC_FAN_1_TACH NC_SMC_FAN_5_CTL NC_ENET_ASF_GPIO NC_SMC_MPM5_LED_PWR NC_SMC_MPM5_LED_CHGNC_SMC_MPM5_LED_CHG NC_SMC_T25_EN_L NC_SMC_DP_HPD_L NC_SMBUS_SMC_4_ASF_SCLNC_SMBUS_SMC_4_ASF_SCL NC_SMBUS_SMC_4_ASF_SDA NC_BDV_BKL_PWMNC_BDV_BKL_PWM

NC_TBT_B_R2D_CP<1..0> NC_TBT_B_R2D_CN<1..0> NC_TBT_B_D2RP<1..0> NC_TBT_B_D2RN<1..0> NC_TBT_B_LSTX NC_DP_TBTPB_ML_CP<3..1:2> NC_DP_TBTPB_ML_CN<3..1:2> NC_DP_TBTPB_AUXCH_CP

NC_DP_TBTSRC_ML_CP<3> NC_DP_TBTSRC_ML_CN<3> NC_DP_TBTSRC_ML_CP<2> NC_DP_TBTSRC_ML_CN<2> NC_DP_TBTSRC_ML_CP<1> NC_DP_TBTSRC_ML_CN<1> NC_DP_TBTSRC_ML_CP<0> NC_DP_TBTSRC_ML_CN<0> NC_DP_TBTSRC_AUXCH_CP

Func Test / No Test

Apple Inc.

R

62 62

12 62 12 62

14 62 14 62

CPU/PCH

14 62 14 62

5

12 62 12 62

13 62

14 62 14 62

14 62

35 62 35 62

62 62

35 62 35 62

35 62

35 62 35 62

SMC

62

62 62

35 62

35 62 35 62

35 62

35 62 35 62

TBT

25 62

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

104 OF 120

SHEET

62 OF 73

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

Functional Test Points

Power Aliases

J9500: LIO Connector

FUNC_TEST

D

FUNC_TEST

C

AUD_PWR_EN

TRUE

PP5V_S0_ALT_AUD_LDO_EN

TRUE

SPKRAMP_SHDN_L

TRUE

PP1V5_S0SW_AUDIO

TRUE

PP3V3_S0

TRUE

SPKRAMP_INR_N

TRUE

SPKRAMP_INR_P

TRUE

USB3_EXTB_D2R_RC_N

TRUE

USB3_EXTB_D2R_RC_P

TRUE

USB_EXTB_N

TRUE

USB_EXTB_P

TRUE

USB3_EXTB_R2D_N

TRUE

USB3_EXTB_R2D_P

TRUE

PP3V42_G3H

TRUE

SMBUS_SMC_2_S3_SCL

TRUE

SMBUS_SMC_2_S3_SDA

TRUE

SYS_ONEWIRE

TRUE

SMC_BC_ACOK

TRUE

XDP_USB_EXTB_OC_L

TRUE

USB_PWR_EN

TRUE

FINSTACKSNS_ALERT_L

TRUE

HDA_SYNC

TRUE

HDA_RST_L

TRUE

HDA_SDOUT

TRUE

HDA_SDIN0

TRUE

HDA_BIT_CLK

TRUE

(Need to add 5 GND TPs)

J6955: HALL EFFECT Connector

SMC_LID_R

TRUE

PP3V42_G3H

TRUE

13 57 59

59

45 59

56 59 60 62 72

8

11 12 13 15 17 18 26 30 34 36

37 38 39 40 41 42 43 54 57 59 45 59 72

45 59 72

59 63 66

14 59 66

59 63 66

17 30 33 34 35 36 38 44 46 47 48 57 59 60 62 63

35 38 59 71

35 59

35 36 48 59

14 16 59

33 57 59

37 59

12 59 67

46

17 30 33 34 35 36 38 44 46 47 48 57 59 60 62 63

PP3V3_S3 PP3V3_S3

15 18 19 34 38 39 56 60 62 63 15 18 19 34 38 39 56 60 62 63

NC_USB3RPCIE_SD_D2RP

14 63 66

NC_USB3RPCIE_SD_D2RN

14 63 66

NC_USB3RPCIE_SD_R2D_CP

14 63 66

NC_USB3RPCIE_SD_R2D_CN

NC_SMC_ADC16 NC_SMC_ADC16

35 37 63 35 37 63

NO_TEST Nets

NO_TEST

MAKE_BASE

TRUE TRUE

TRUETRUE TRUETRUE

TRUE TRUE

TRUETRUE

NC_USB3RPCIE_SD_D2RP NC_USB3RPCIE_SD_D2RN NC_USB3RPCIE_SD_R2D_CP NC_USB3RPCIE_SD_R2D_CN

14 63 66

14 63 66 14 63 66

CPU/PCH

SMC

D

C

Bead Probes

USB3_EXTB_D2R_N

14 59 66

USB3_EXTB_D2R_P

14 59 66

USB3_EXTB_D2R_RC_N

59 63 66

USB3_EXTB_D2R_RC_P

59 63 66

USB3_EXTB_R2D_C_N

14 59 66

USB3_EXTB_R2D_C_P

14 59 66

USB3_EXTB_R2D_N

59 63 66

USB3_EXTB_R2D_P

59 63 66

B

1

TP

BEAD-PROBE

SM

1

TP

BEAD-PROBE

SM

1

TP

BEAD-PROBE

SM

1

TP

BEAD-PROBE

SM

1

TP

BEAD-PROBE

SM

1

TP

BEAD-PROBE

SM

1

TP

BEAD-PROBE

SM

1

TP

BEAD-PROBE

SM

BPA511 BPA510 BPA520 BPA521 BPA513 BPA512 BPA523 BPA522

B

Unused nets with offpage

(Nets with offpages not used on this project)

SD_RESET_L XDP_SDCONN_STATE_CHANGE_L SD_PWR_EN

A

15

15 16

15

6 3

SYNC_MASTER=MASTER

PAGE TITLE

Project FCT/NC/Aliases

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=MASTER

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

105 OF 120

SHEET

63 OF 73

124578

SIZE

A

D

8 7 6 5 4 3

12

J41/J43 Board-Specific Spacing & Physical Constraints

BOARD LAYERS

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

LAYER

DEFAULT

D

DEFAULT

STANDARD =DEFAULT=DEFAULT

ISL2,ISL11

ISL3,ISL10

ISL4,ISL9

ALLOW ROUTE ON LAYER?

* N

*

=DEFAULT =DEFAULT=DEFAULT=DEFAULT

Y

MINIMUM LINE WIDTH

=50_OHM_SETOP,BOTTOM

Single-ended Physical Constraints

LAYER

27P4_OHM_SE

TOP,BOTTOM

ISL2,ISL11

ISL3,ISL10

ISL4,ISL9

LAYER

35_OHM_SE

35_OHM_SE ISL4,ISL9

35_OHM_SE

TOP,BOTTOM

ISL2,ISL11

ISL3,ISL10

C

LAYER

40_OHM_SE

45_OHM_SE

45_OHM_SE ISL4,ISL9

50_OHM_SE

B

50_OHM_SE =STANDARD =STANDARD=STANDARD

55_OHM_SE

TOP,BOTTOM

ISL2,ISL11

ISL3,ISL10

ISL4,ISL9

LAYER

TOP,BOTTOM

ISL2,ISL11

ISL3,ISL10

LAYER

TOP,BOTTOM

LAYER

TOP,BOTTOM

ALLOW ROUTE ON LAYER?

*

ALLOW ROUTE ON LAYER?

* N

ALLOW ROUTE ON LAYER?

* N

ALLOW ROUTE ON LAYER?

* N

ALLOW ROUTE ON LAYER?

* N

ALLOW ROUTE ON LAYER?

Y

N

Y

N*

MINIMUM LINE WIDTH

0.310 MM 0.310 MM

0.182 MM 0.182 MM

MINIMUM LINE WIDTH

0.195 MM 0.195 MM

0.125 MM

0.125 MM 0.125 MM

100 MM

MINIMUM LINE WIDTH

0.170 MM

0.096 MM

0.099 MM

100 MM

MINIMUM LINE WIDTH

0.135 MM

0.075 MM 0.075 MM

0.080 MM

100 MM 100 MM

MINIMUM LINE WIDTH

0.110 MM

100 MM 100 MM

MINIMUM LINE WIDTH

0.090 MM

MINIMUM NECK WIDTH

=50_OHM_SE

=45_OHM_SE=45_OHM_SE

100 MM100 MM

MINIMUM NECK WIDTH

0.182 MM0.182 MM

100 MM100 MM

MINIMUM NECK WIDTH

0.125 MM

0.125 MM0.125 MM

100 MM

MINIMUM NECK WIDTH

0.170 MM

0.096 MM

0.096 MM0.096 MM

0.099 MM

100 MM

MINIMUM NECK WIDTH

0.135 MM

0.080 MM

MINIMUM NECK WIDTH

0.110 MM

MINIMUM NECK WIDTH

0.090 MM

100 MM100 MM

0 MM

BOARD UNITS (MIL or MM)

BOARD AREAS

NO_TYPE,BGA,MEM_TERM

MAXIMUM NECK LENGTH

10 MM

MAXIMUM NECK LENGTH

=STANDARD =STANDARD =STANDARD

MAXIMUM NECK LENGTH

=STANDARD =STANDARD=STANDARD

MAXIMUM NECK LENGTH

=STANDARD =STANDARD45_OHM_SE =STANDARD

MAXIMUM NECK LENGTH

=STANDARD55_OHM_SE =STANDARD

DIFFPAIR PRIMARY GAP

TABLE_BOARD_INFO

ALLEGRO VERSION

MM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

16.2

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

0 MM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

=STANDARD40_OHM_SE =STANDARD=STANDARD

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

Spacing Constraints

SPACING_RULE_SET

1:1_SPACING

SPACING_RULE_SET

1x_DIELECTRIC

SPACING_RULE_SET

DEFAULT

STANDARD

BGA_P075MM

P070MM_BGA

LAYER

TOP,BOTTOM

ISL3,ISL10

ISL4,ISL9

LAYER

*

* *

LINE-TO-LINE SPACING

0.100 MM

LINE-TO-LINE SPACING

0.071 MM

0.053 MM

0.050 MM

0.090 MM

LINE-TO-LINE SPACING

0.1 MM

=DEFAULT

0.075 MM

ALLOW ROUTE ON LAYER?

MINIMUM LINE WIDTH

WEIGHT

? ? ?*

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?*

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

NET_SPACING_TYPE1 NET_SPACING_TYPE2

AREA_TYPE

* *

BGA

5 MM

PHYSICAL_RULE_SET

P070MM_BGA

DIFFPAIR PRIMARY GAP

NET_PHYSICAL_TYPE

AREA_TYPE

*

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

0.070 MM 0.075 MM

BGA

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

SPACING_RULE_SET

BGA_P075MM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

D

C

B

=STANDARD

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

Differential Pair Physical Constraints

LAYER

70_OHM_DIFF

TOP,BOTTOM

ISL2,ISL11

ISL3,ISL10

ISL4,ISL9

LAYER

80_OHM_DIFF

A

80_OHM_DIFF

TOP,BOTTOM

ISL2,ISL11

ISL3,ISL10

ISL4,ISL9

LAYER

90_OHM_DIFF

TOP,BOTTOM

ISL2,ISL11

ISL3,ISL10

ISL4,ISL9

ALLOW ROUTE ON LAYER?

*

Y

N*

Y

N*

Y

N

MINIMUM LINE WIDTH

0.105 MM 0.100 MM0.100 MM0.105 MM

0.110 MM 0.095 MM0.095 MM

100 MM 100 MM

MINIMUM LINE WIDTH

100 MM

MINIMUM LINE WIDTH

100 MM

MINIMUM NECK WIDTH

0.110MM

MINIMUM NECK WIDTH

0.132 MM

100 MM

MINIMUM NECK WIDTH

0.115 MM0.115 MM 0.200 MM0.200 MM

0.076 MM0.076 MM 0.180 MM 0.180 MM

100 MM

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD =STANDARD

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

=STANDARD =STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

0.110 MM0.110 MM0.165 MM0.165 MM

TABLE_PHYSICAL_RULE_ITEM

0.100 MM0.100 MM0.105 MM0.105 MM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

0.130 MM0.130 MM0.132 MM

TABLE_PHYSICAL_RULE_ITEM

0.115 MM0.115 MM0.081 MM0.081 MM

TABLE_PHYSICAL_RULE_ITEM

0.115 MM0.115 MM0.081 MM0.081 MM

TABLE_PHYSICAL_RULE_ITEM

0.110 MM0.110 MM0.088 MM0.088 MM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

0.180 MM0.180 MM0.070 MM 0.070 MM

TABLE_PHYSICAL_RULE_ITEM

0.180 MM0.180 MM0.070 MM0.070 MM

TABLE_PHYSICAL_RULE_ITEM

=STANDARD=STANDARD=STANDARD

73_OHM_DIFF

85_OHM_DIFF

LAYER

TOP,BOTTOM

ISL2,ISL11

ISL3,ISL10

ISL4,ISL9

LAYER

TOP,BOTTOM

ISL2,ISL11

ISL3,ISL10

ISL4,ISL9

ALLOW ROUTE ON LAYER?

* N

Y

N*

Y

MINIMUM LINE WIDTH

0.165 MM 0.165 MM

0.106 MM 0.106 MM

0.110 MM 0.110 MM

100 MM 100 MM

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

0.120 MM0.120 MM

100 MM100 MM

MAXIMUM NECK LENGTH

=STANDARD =STANDARD =STANDARD

MAXIMUM NECK LENGTH

6 3

DIFFPAIR PRIMARY GAP

0.150 MM 0.150 MM

DIFFPAIR PRIMARY GAP

0.150 MM 0.150 MM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

0.150 MM0.150 MM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

0.160 MM0.160 MM0.078 MM0.078 MM

TABLE_PHYSICAL_RULE_ITEM

0.160 MM0.160 MM0.078 MM0.078 MM

TABLE_PHYSICAL_RULE_ITEM

0.140 MM0.140 MM0.082 MM0.082 MM

TABLE_PHYSICAL_RULE_ITEM

=STANDARD=STANDARD=STANDARD

SYNC_MASTER=J43_MLB

PAGE TITLE

PCB Rule Definitions

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=10/24/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

110 OF 120

SHEET

64 OF 73

SIZE

A

D

124578

8 7 6 5 4 3

12

CPU Signal Constraints

CPU_45S

CPU_27P4S

SPACING_RULE_SET

CPU_AGTL

D

NET_SPACING_TYPE1 NET_SPACING_TYPE2

CPU_8MIL

NET_SPACING_TYPE1 NET_SPACING_TYPE2

CPU_ITP

NET_SPACING_TYPE1 NET_SPACING_TYPE2

CPU_COMP

NET_SPACING_TYPE1 NET_SPACING_TYPE2

CPU_VCCSENSE

LAYER

*

LAYER

TOP,BOTTOM

* *

CPU_COMPCPU_COMP

* *

CPU_VCCSENSE

* *

ALLOW ROUTE ON LAYER?

=27P4_OHM_SE

LINE-TO-LINE SPACING

MINIMUM LINE WIDTH

=2x_DIELECTRIC

=STANDARD

AREA_TYPE

**

AREA_TYPE

*

AREA_TYPE

*

C

PCI-Express Interface Constraints

LAYER

PCIE_80D

CLK_PCIE_80D

PCIE Clock Spacing

NET_SPACING_TYPE1 NET_SPACING_TYPE2

CLK_PCIE CLK_PCIE

CLK_PCIE

CPU PCIE Spacing

NET_SPACING_TYPE1 NET_SPACING_TYPE2

PCIE_CPU_TX

B

A

PCIE_CPU_RX

PCIE_CPU_TX

PCIE_CPU_RX

PCIE_CPU_TX

PCIE_CPU_RX

PCIE_CPU_TX

PCIE_CPU_RX

PCIE_CPU_TX

PCIE_CPU_RX

PCIE_CPU_TX

PCIE_CPU_RX

PCH PCIE Spacing

NET_SPACING_TYPE1 NET_SPACING_TYPE2

PCIE_PCH_RX PCIE_PCH_RX

PCIE_PCH_TX

PCIE_PCH_RX

PCIE_PCH_TX

PCIE_PCH_RX

PCIE_PCH_TX

PCIE_PCH_RX

PCIE_PCH_TX

PCIE_PCH_RX

PCIE_PCH_TX

PCIE_PCH_RX

SOURCE: 471984_Chief_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback.

*

PCIE_CPU_TX

PCIE_CPU_RX

*_CPU_TX

*_CPU_RX

*_CPU_TX

*_TX

*_RX

*

PCIE_PCH_TXPCIE_PCH_TX

*_PCH_TX

*_PCH_RX

*_PCH_TX

*_TX

*_RX

*

* *

ALLOW ROUTE ON LAYER?

=80_OHM_DIFF

AREA_TYPE

MINIMUM LINE WIDTH

*

**

*

MINIMUM NECK WIDTH

=45_OHM_SE

=27P4_OHM_SE =27P4_OHM_SE

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?*

SPACING_RULE_SET

CPU_8MIL_2ANY

SPACING_RULE_SET

CPU_ITP_2ANY

SPACING_RULE_SET

CPU_COMP_2SELF

CPU_COMP_2OTHER

=45_OHM_SE=45_OHM_SE =45_OHM_SE

TABLE_SPACING_ASSIGNMENT_HEAD

SPACING_RULE_SET

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

CPU_8MIL_2ANY

SPACING_RULE_SET

CPU_ITP_2ANY

SPACING_RULE_SET

CPU_COMP_2SELF

CPU_COMP_2OTHER

SPACING_RULE_SET

CPU_COMP_2SELF

CPU_COMP_2OTHER

TABLE_SPACING_ASSIGNMENT_HEAD

SPACING_RULE_SET

CPU_VCCSENSE_2SELF

CPU_VCCSENSE_2OTHER

TABLE_SPACING_ASSIGNMENT_ITEM

SPACING_RULE_SET

CPU_VCCSENSE_2SELF

CPU_VCCSENSE_2OTHER

SPACING_RULE_SET

CPU_VCCSENSE_2SELF

CPU_VCCSENSE_2OTHER

MINIMUM NECK WIDTH

=80_OHM_DIFF=80_OHM_DIFF

=80_OHM_DIFF =80_OHM_DIFF

TABLE_SPACING_ASSIGNMENT_HEAD

SPACING_RULE_SET

CLK_PCIE_2SELF

CLK_PCIE_2OTHER

TABLE_SPACING_ASSIGNMENT_ITEM

SPACING_RULE_SET

CLK_PCIE_2SELF =6x_DIELECTRIC

CLK_PCIE_2OTHER =10x_DIELECTRIC

SPACING_RULE_SET

CLK_PCIE_2SELF

CLK_PCIE_2OTHER

PCIE_TX2TX

PCIE_RX2RX

PCIE_TX2OTHERTX

PCIE_RX2OTHERRX

PCIE_TX2RX

PCIE_RX2TX

PCIE_2OTHERHS

PCIE_2OTHER

PCIE_TX2TX

PCIE_RX2RX

PCIE_TX2OTHERTX

PCIE_RX2OTHERRX

PCIE_TX2RX

PCIE_RX2TX

PCIE_2OTHERHS

PCIE_2OTHER

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

SPACING_RULE_SET

PCIE_TX2TX TOP,BOTTOM

PCIE_RX2RX

PCIE_TX2OTHERTX

PCIE_RX2OTHERRX

PCIE_TX2RX

PCIE_RX2TX TOP,BOTTOM

PCIE_2OTHERHS

PCIE_2OTHER

SPACING_RULE_SET

PCIE_TX2TX

PCIE_RX2RX

PCIE_TX2OTHERTX

PCIE_RX2OTHERRX

PCIE_TX2RX

PCIE_RX2TX

PCIE_2OTHERHS

PCIE_2OTHER

SPACING_RULE_SET

MAXIMUM NECK LENGTH

=27P4_OHM_SE

Note: CPU_8MIL and CPU_ITP can be converted

back to TABLE_SPACING_RULE

once rdar://10308147 is resolved

LAYER

*

LAYER

* ?

LAYER

TOP,BOTTOM

LAYER

* ?

LAYER

TOP,BOTTOM

LAYER

* ?

MAXIMUM NECK LENGTH

=80_OHM_DIFF

LAYER

TOP,BOTTOM

LAYER

* ?

LAYER

TOP,BOTTOM

LAYER

*

* ?

*

DIFFPAIR PRIMARY GAP

LINE-TO-LINE SPACING

8 MIL

LINE-TO-LINE SPACING

=4x_DIELECTRIC

LINE-TO-LINE SPACING

=6x_DIELECTRIC

=10x_DIELECTRIC

LINE-TO-LINE SPACING

=4x_DIELECTRIC

=6x_DIELECTRIC

LINE-TO-LINE SPACING

=6x_DIELECTRIC

=10x_DIELECTRIC

LINE-TO-LINE SPACING

=4x_DIELECTRIC

=6x_DIELECTRIC

DIFFPAIR PRIMARY GAP

=80_OHM_DIFF=80_OHM_DIFF =80_OHM_DIFF

LINE-TO-LINE SPACING

=4x_DIELECTRIC

=6x_DIELECTRIC

LINE-TO-LINE SPACING

=5x_DIELECTRIC

=7x_DIELECTRIC

=6x_DIELECTRIC

=5x_DIELECTRIC

LINE-TO-LINE SPACING

=2.5x_DIELECTRIC

=4x_DIELECTRIC

=6x_DIELECTRIC

=4x_DIELECTRIC

=3x_DIELECTRIC

CPU Net Properties

ELECTRICAL_CONSTRAINT_SET

PM_SYNC CPU_45S PM_MEM_PWRGD

CPU_SM_RCOMP CPU_SM_RCOMP

CPU_SM_RCOMP

CPU_CATERR_L

CPU_PROCHOT_L

CPU_PWRGD

PM_THRMTRIP_L DMI_CLK100M

DMI_CLK100M

ITPCPU_CLK100M ITPCPU_CLK100M

ITPCPU_CLK100M

ITPCPU_CLK100M ITPCPU_CLK100M

ITPCPU_CLK100M

XDP_TCK CPU_45S CPU_ITP XDP_TRST_L

XDP_BPM_L

(FSB_CPURST_L)

CPU_VCCSENSE CPU_VCCSENSE

CPU_VCCIOSENSE

CPU_VCCIOSENSE CPU_AXG_SENSE

CPU_AXG_SENSE CPU_VALSENSE CPU_VCCSENSE

CPU_VALSENSE CPU_VCCSENSE

CPU_SVIDALERT_L

CPU_SVIDSCLK CPU_SVIDSOUT

PCIE_CPU_SSD_R2D PCIE_80D

PCIE_CPU_SSD_R2D

PCIE_CPU_SSD_D2R

PCIE_CLK100M_SSD PCIE_CLK100M_SSD

DP_TBT_ML

I212

DP_TBT_ML

I211

I210

I209

DP_TBT_AUXCH DP_AUX

I208

DP_TBT_AUXCH DP_AUX

I206

I207

I205

DP_TBT_ML

I204

DP_TBT_ML

I203

I202

I201

DP_TBT_AUXCH DP_AUX

I200

DP_TBT_AUXCH DP_80D

I199

I198

I197

DP_INT_ML

I215

I214

DP_INT_AUXCH

DP_INT_AUXCH DP_80D DP_AUX

NET_TYPE

PHYSICAL

CPU_45S

CPU_45S CPU_ITP

CPU_27P4S

CPU_27P4S CPU_27P4S

CPU_27P4S

CPU_45S

CPU_45S CPU_45S

CPU_45S

CPU_45S CLK_PCIE_80D

CLK_PCIE_80D

CLK_PCIE_80D CLK_PCIE_80D

CLK_PCIE_80D

CLK_PCIE_80D CLK_PCIE_80D

CLK_PCIE_80D

CPU_45S CPU_ITPXDP_TDI

CPU_45S CPU_ITPXDP_TMS

CPU_45S CPU_ITP

CPU_45S

SENSE_1TO1_P2MM SENSE_1TO1_P2MM

SENSE_1TO1_P2MM

SENSE_1TO1_P2MM SENSE_1TO1_P2MM

SENSE_1TO1_P2MM CPU_27P4S

CPU_27P4S

CPU_27P4S CPU_27P4S

CPU_27P4S

CPU_45S

CPU_45S CPU_45S

PCIE_80D

PCIE_80D PCIE_80D

PCIE_80D

PCIE_80D PCIE_80D

PCIE_80D

CLK_PCIE_80D CLK_PCIE_80D

DP_80D

DP_80D DP_80D

DP_80D

DP_80D DP_80D

DP_80D

DP_80D DP_80D

DP_80D

DP_80D DP_80D

DP_80D DP_AUX

SPACING

CPU_COMPCPU_PECI

CPU_AGTL CPU_AGTL

CPU_ITPCPU_45S

CPU_COMP

CPU_COMP CPU_COMP

CPU_COMP CPU_ITPCPU_45S

CPU_AGTL

CPU_AGTL CPU_AGTL

CPU_AGTL

CPU_8MIL CLK_PCIE

CLK_PCIE

CLK_PCIEDPLL_REF_CLK120M CLK_PCIEDPLL_REF_CLK120M

CLK_PCIE CLK_PCIE

CLK_PCIE

CLK_PCIE CLK_PCIE

CLK_PCIE

CPU_ITPXDP_TDO CPU_45S

CPU_ITP CPU_ITPCPU_45S

CPU_ITPCPU_45S

CPU_ITPCPU_45S CPU_ITPCPU_45S

CPU_VCCSENSECPU_VCCSENSE

CPU_VCCSENSE

CPU_VCCSENSE CPU_VCCSENSE

CPU_VCCSENSE

CPU_VCCSENSECPU_VALSENSE

CPU_COMP

CPU_COMP CPU_COMP

PCIE_CPU_TX

PCIE_CPU_TX PCIE_CPU_TX

PCIE_CPU_RX

PCIE_CPU_RX PCIE_CPU_RX

PCIE_CPU_RX

CLK_PCIE CLK_PCIE

DP_TX

DP_TX DP_TX

DP_TX

DP_AUX

DP_TX DP_TX

DP_AUX DP_AUX

DP_AUX

DP_TX

DP_TX DP_TX

DP_AUXDP_80DDP_INT_AUXCH DP_AUXDP_80DDP_INT_AUXCH

DP_AUXDP_80D

=STANDARD

0.100 MM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

WEIGHT

?

WEIGHT

?

WEIGHT

?

WEIGHT

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

WEIGHT

?

WEIGHT

?

WEIGHT

?

?*

?

?*

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

=STANDARD

0.100 MM

=80_OHM_DIFF=80_OHM_DIFF

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

Note: DisplayPort tables are on Page 113

6 3

CPU_PECI PM_SYNC PM_MEM_PWRGD

XDP_DBRESET_L XDP_CPU_PRDY_L XDP_CPU_PREQ_L

EDP_COMP CPU_PEG_COMP CPU_SM_RCOMP<0> CPU_SM_RCOMP<1> CPU_SM_RCOMP<2> CPU_CFG<11..0> CPU_CATERR_L CPU_VCCIO_SEL CPU_PROCHOT_L CPU_PWRGD PM_THRMTRIP_L DMI_CLK100M_CPU_P DMI_CLK100M_CPU_N DPLL_REF_CLKP DPLL_REF_CLKN ITPCPU_CLK100M_P ITPCPU_CLK100M_N ITPXDP_CLK100M_P ITPXDP_CLK100M_N XDP_CPU_CLK100M_P XDP_CPU_CLK100M_N XDP_CPU_TDI XDP_CPU_TDO XDP_CPU_TMS XDP_CPU_TCK XDP_CPUPCH_TRST_L XDP_BPM_L<1..0> XDP_BPM_L<7..2> XDP_OBSDATA_B<3..0> CPU_CFG<15..12> XDP_CPURST_L

CPU_VCCSENSE_P CPU_VCCSENSE_N CPU_VCCIOSENSE_P CPU_VCCIOSENSE_N CPU_AXG_SENSE_P CPU_AXG_SENSE_N CPU_VDDQ_SENSE_P CPU_VDDQ_SENSE_N CPU_AXG_VALSENSE_P CPU_AXG_VALSENSE_N CPU_VCC_VALSENSE_P CPU_VCC_VALSENSE_N

CPU_VIDALERT_L CPU_VIDSCLK CPU_VIDSOUT

PCIE_SSD_R2D_C_P<3..0> PCIE_SSD_R2D_C_N<3..0> PCIE_SSD_R2D_P<3..0> PCIE_SSD_R2D_N<3..0> PCIE_SSD_D2R_C_P<3..0> PCIE_SSD_D2R_C_N<3..0> PCIE_SSD_D2R_P<3..0> PCIE_SSD_D2R_N<3..0> PCIE_CLK100M_SSD_P PCIE_CLK100M_SSD_N

DP_TBTSNK0_ML_P<3..0> DP_TBTSNK0_ML_N<3..0> DP_TBTSNK0_ML_C_P<3..0> DP_TBTSNK0_ML_C_N<3..0> DP_TBTSNK0_AUXCH_P DP_TBTSNK0_AUXCH_N DP_TBTSNK0_AUXCH_C_P DP_TBTSNK0_AUXCH_C_N

DP_TBTSNK1_ML_P<3..0> DP_TBTSNK1_ML_N<3..0> DP_TBTSNK1_ML_C_P<3..0> DP_TBTSNK1_ML_C_N<3..0> DP_TBTSNK1_AUXCH_P DP_TBTSNK1_AUXCH_N DP_TBTSNK1_AUXCH_C_P DP_TBTSNK1_AUXCH_C_N

DP_INT_ML_P<3..0> DP_INT_ML_N<3..0> DP_INT_ML_C_P<3..0> DP_INT_ML_C_N<3..0>

DP_INT_AUX_CH_C_P DP_INT_AUX_CH_C_N DP_INT_AUXCH_C_P DP_INT_AUXCH_C_N DP_INT_AUXCH_P DP_INT_AUXCH_N

6

36

16 17

6

16 62

6

16 62

6

16 62

6

35

6

35 36 49

6

15 36

6

16 62

6

16 62

6

16 62

6

16 62

6

12 16 62

6

16

6

16

6

16

8

49

9

49

8

49

8

49

8

49

12 30

30 62

12 30 62

58 62

5

58 62

5

58 62

5

58

5

58

25

5

25

5

25

13 25

25

5

18 25

5

18 25

25

13 18 25

PCIe SSD

DP

SYNC_MASTER=J43_MLB

PAGE TITLE

CPU Constraints

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=09/21/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

111 OF 120

SHEET

65 OF 73

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

SATA Interface Constraints

SATA_80D

SPACING_RULE_SET

SATA_ICOMP

LAYER

ALLOW ROUTE ON LAYER?

=80_OHM_DIFF

*

LINE-TO-LINE SPACING

* ?

MINIMUM LINE WIDTH

=4x_DIELECTRIC

D

SOURCE: 471984_Chief_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback.

C

UART Interface Constraints

LAYER

UART_45S

SPACING_RULE_SET

UART

LAYER

USB 2.0 Interface Constraints

LAYER

PCH_USB_RBIAS

USB_80D

SPACING_RULE_SET

USB

SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.8

LAYER

USB 3.0 Interface Constraints

NET_SPACING_TYPE1 NET_SPACING_TYPE2

B

USB3_PCH_TX

USB3_PCH_RX

USB3_PCH_TX

USB3_PCH_RX

USB3_PCH_TX

USB3_PCH_RX

USB3_PCH_TX

USB3_PCH_RX

A

SOURCE: 471984_Cheif_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback.

*

USB3_PCH_TXUSB3_PCH_TX

USB3_PCH_RXUSB3_PCH_RX

*_PCH_TX

*_PCH_RX

*_PCH_TX

*_TX

*_RX

ALLOW ROUTE ON LAYER?

=45_OHM_SE =45_OHM_SE=45_OHM_SE

MINIMUM LINE WIDTH

LINE-TO-LINE SPACING

=2x_DIELECTRIC

ALLOW ROUTE ON LAYER?

=STANDARD

=80_OHM_DIFF

MINIMUM LINE WIDTH

LINE-TO-LINE SPACING

=2x_DIELECTRIC

AREA_TYPE

*

**

MINIMUM NECK WIDTH

=80_OHM_DIFF =80_OHM_DIFF

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

MINIMUM NECK WIDTH

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?*

MINIMUM NECK WIDTH

8 MIL

=80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

USB3_TX2TX

USB3_RX2RX

USB3_TX2OTHERTX

USB3_RX2OTHERRX

USB3_TX2RX

USB3_RX2TX

USB3_2OTHERHS

USB3_2OTHERUSB3_PCH_TX

USB3_2OTHERUSB3_PCH_RX

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

SPACING_RULE_SET

8 MIL

SPACING_RULE_SET

USB

SPACING_RULE_SET

USB3_TX2TX

USB3_RX2RX

USB3_TX2OTHERTX

USB3_RX2OTHERRX

USB3_TX2RX TOP,BOTTOM

USB3_RX2TX

USB3_2OTHERHS

USB3_2OTHER

SPACING_RULE_SET

USB3_TX2TX

USB3_RX2RX

USB3_TX2OTHERTX

USB3_RX2OTHERRX

USB3_TX2RX

USB3_RX2TX

USB3_2OTHERHS

USB3_2OTHER

MAXIMUM NECK LENGTH

=80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF

MAXIMUM NECK LENGTH

=STANDARD

=80_OHM_DIFF =80_OHM_DIFF

LAYER

TOP,BOTTOM

LAYER

TOP,BOTTOM

LAYER

* ?

*

* ?

*

DIFFPAIR PRIMARY GAP

=STANDARD

LINE-TO-LINE SPACING

=4x_DIELECTRIC

LINE-TO-LINE SPACING

=5x_DIELECTRIC

=7x_DIELECTRIC

=6x_DIELECTRIC

=5x_DIELECTRIC

LINE-TO-LINE SPACING

=2.5x_DIELECTRIC

=4x_DIELECTRIC

=6x_DIELECTRIC

=4x_DIELECTRIC

=3x_DIELECTRIC

PCH Net Properties

ELECTRICAL_CONSTRAINT_SET

PCH_SATA_ICOMP

USB_HUB1_UP

USB_BT USB_BT

USB_TPAD USB_TPAD

USB_TPAD_M USB_TPAD_M

USB_SDCARD

USB_EXTA

USB2_EXTA USB2_EXTA

USB3_EXTA_RX

USB3_EXTA_RX USB3_EXTA_TX

USB3_EXTA_TX

USB_EXTB

USB_EXTB USB3_EXTB_RX

USB3_EXTB_RX

USB3_EXTB_TX

USB3_SD_RX

USB3_SD_TX USB3_SD_TX

PCH_USB_RBIAS PCH_USB_RBIAS PCH_DIFFCLK_UNUSED_

PCH_DIFFCLK_UNUSED_

PCH_DIFFCLK_UNUSED_ PCH_DIFFCLK_UNUSED_

PCH_DIFFCLK_UNUSED_

PHYSICAL

USB_80D

USB_80D USB_80D

USB_80D

USB_80D USB_80D

USB_80D

USB_80D USB_80D

USB_80D

USB_80D USB_80D

USB_80D

SPI_45S SPI_45S

SPI_45S

USB_80D

USB_80D UART_45S

UART_45S

USB_80D USB_80D

USB_80D

USB_80D USB_80D

USB_80D

USB_80D USB_80D

USB_80D

USB_80D USB_80D

USB_80D

USB_80D USB_80D

USB_80D

USB_80D USB_80D

USB_80D

USB_80D USB_80D

USB_80D

USB_80D USB_80D

USB_80D

USB_80D USB_80D

USB_80D

CLK_PCIE_80D

CLK_PCIE_80D CLK_PCIE_80D

CLK_PCIE_80D

CLK_PCIE_80D CPU_45S

NET_TYPE

SPACING

SATA_ICOMP

USB

USB USB

USB

USB USB

USB

USB USB

USB

USB USB

USB

SPI SPI

SPI

USB

USB UART

UART

USB USB

USB3_PCH_RX

USB3_PCH_RX USB3_PCH_TX

USB3_PCH_TX

USB3_PCH_RX USB3_PCH_RX

USB3_PCH_TX

USB3_PCH_TX USB3_PCH_TX

USB3_PCH_TX

USB

USB USB3_PCH_RX

USB3_PCH_RX

USB3_PCH_RX USB3_PCH_RX

USB3_PCH_TX

USB3_PCH_TX USB3_PCH_TX

USB3_PCH_TX

USB3_PCH_RX

USB3_PCH_TX USB3_PCH_TX

USB3_PCH_RX

USB3_PCH_RX USB3_PCH_TX

USB3_PCH_TX

CLK_PCIE

CLK_PCIE CLK_PCIE

CLK_PCIE

CLK_PCIE CLK_PCIE

PCH_SATAICOMP

USB_HUB_UP_P USB_HUB_UP_N USB_BT_P USB_BT_N USB_BT_CONN_P USB_BT_CONN_N USB_BT_WAKE_P USB_BT_WAKE_N USB_TPAD_P USB_TPAD_N USB_TPAD_CONN_P USB_TPAD_CONN_N

TPAD_SPI_MOSI_USB_P TPAD_SPI_MISO_USB_N USB_TPAD_M_P USB_TPAD_M_N USB_SDCARD_P USB_SDCARD_N

TPAD_SPI_MOSI TPAD_SPI_MISO TPAD_SPI_CLK

USB_EXTA_P USB_EXTA_N SMC_DEBUGPRT_TX_L SMC_DEBUGPRT_RX_L USB2_EXTA_MUXED_P USB2_EXTA_MUXED_N USB2_EXTA_MUXED_F_P USB2_EXTA_MUXED_F_N USB3_EXTA_D2R_P USB3_EXTA_D2R_N USB3_EXTA_R2D_P USB3_EXTA_R2D_N USB3_EXTA_D2R_F_P USB3_EXTA_D2R_F_N USB3_EXTA_R2D_F_P USB3_EXTA_R2D_F_N USB3_EXTA_R2D_C_P USB3_EXTA_R2D_C_N

USB_EXTB_P USB_EXTB_N USB3_EXTB_D2R_P USB3_EXTB_D2R_N USB3_EXTB_D2R_RC_P USB3_EXTB_D2R_RC_N USB3_EXTB_R2D_P USB3_EXTB_R2D_N USB3_EXTB_R2D_C_P USB3_EXTB_R2D_C_N

NC_USB3RPCIE_SD_D2RP NC_USB3RPCIE_SD_D2RN NC_USB3RPCIE_SD_R2D_CP NC_USB3RPCIE_SD_R2D_CN USB3_SD_D2R_C_P USB3_SD_D2R_C_N USB3_SD_R2D_P USB3_SD_R2D_N

PCH_USB_RBIAS PCIE_CLK100M_PCH_P PCIE_CLK100M_PCH_N PCH_CLK96M_DOT_P PCH_CLK96M_DOT_N PCH_CLK100M_SATA_P PCH_CLK100M_SATA_N PCH_CLK14P3M_REFCLK

WEIGHT

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

WEIGHT

?

WEIGHT

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

=45_OHM_SE=45_OHM_SE=45_OHM_SE

=STANDARD

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

6 3

14 29

29 62

14 34 62

15 34

14 33

33 35 36

33

14 33

33

14 33

14 59 63

59 63

14 59 63

14 63

14

USB Hucopyb nets

TP SPI nets

USB EXTA nets (Right USB port)

USB EXTB nets (Left USB port)

SYNC_MASTER=CLEAN_J41

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

PCH Constraints 1

Apple Inc.

R

SYNC_DATE=11/13/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

112 OF 120

SHEET

66 OF 73

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

LPC Bus Constraints

LAYER

LPC_45S

CLK_LPC_45S

SPACING_RULE_SET

LPC

CLK_LPC

SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.15

D

SMBus Interface Constraints

LAYER

SMB_45S_R_50S

SPACING_RULE_SET

SMB

TOP,BOTTOM =50_OHM_SE =50_OHM_SE =50_OHM_SE=50_OHM_SE

LAYER

HD Audio Interface Constraints

LAYER

HDA_45S

SPACING_RULE_SET

HDA

SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.15

LAYER

SIO Signal Constraints

LAYER

CLK_SLOW_45S

ALLOW ROUTE ON LAYER?

*

MINIMUM LINE WIDTH

LINE-TO-LINE SPACING

* ?

*

=3x_DIELECTRIC

=4x_DIELECTRIC

ALLOW ROUTE ON LAYER?

=45_OHM_SE

MINIMUM LINE WIDTH

LINE-TO-LINE SPACING

*

=2x_DIELECTRIC

ALLOW ROUTE ON LAYER?

MINIMUM LINE WIDTH

LINE-TO-LINE SPACING

*

=2x_DIELECTRIC

ALLOW ROUTE ON LAYER?

MINIMUM LINE WIDTH

C

SPACING_RULE_SET

CLK_SLOW

LAYER

SPI Interface Constraints

LAYER

SPI_45S

SPACING_RULE_SET

SPI

LAYER

XDP Constraints

LAYER

PCH_45S

SPACING_RULE_SET

PCH_ITP

LAYER

DisplayPort

B

SPACING_RULE_SET

DP_2DP

DP_2OTHERHS

DP_2OTHER

DP_AUX

NET_SPACING_TYPE1 NET_SPACING_TYPE2

DP_TX DP_TX

DP_TX

A

System Clock Signal Constraints

CLK_SLOW_45S

CLK_25M_45S

SPACING_RULE_SET

CLK_SLOW

CLK_25M

LAYER

LINE-TO-LINE SPACING

* ?

*

=4x_DIELECTRIC

ALLOW ROUTE ON LAYER?

MINIMUM LINE WIDTH

LINE-TO-LINE SPACING

*

=4x_DIELECTRIC

ALLOW ROUTE ON LAYER?

=45_OHM_SE =45_OHM_SE

MINIMUM LINE WIDTH

LINE-TO-LINE SPACING

*

=2:1_SPACING

ALLOW ROUTE ON LAYER?

=80_OHM_DIFF

MINIMUM LINE WIDTH

LINE-TO-LINE SPACING

* ?

*

=3x_DIELECTRIC

=4x_DIELECTRIC

=3x_DIELECTRIC

AREA_TYPE

*

*_TX

*_RX

*

ALLOW ROUTE ON LAYER?

=45_OHM_SE

*

MINIMUM LINE WIDTH

LINE-TO-LINE SPACING

* ?

*

=2x_DIELECTRIC

=5x_DIELECTRIC

MINIMUM NECK WIDTH

=45_OHM_SE=45_OHM_SE

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

=45_OHM_SE =45_OHM_SE

MINIMUM NECK WIDTH

=45_OHM_SE =45_OHM_SE =45_OHM_SE

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

MINIMUM NECK WIDTH

=45_OHM_SE=45_OHM_SE=45_OHM_SE

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

MINIMUM NECK WIDTH

=45_OHM_SE=45_OHM_SE=45_OHM_SE

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

MINIMUM NECK WIDTH

=45_OHM_SE

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

=45_OHM_SE =45_OHM_SE=45_OHM_SE

MINIMUM NECK WIDTH

=45_OHM_SE

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

=45_OHM_SE

MINIMUM NECK WIDTH

TABLE_SPACING_RULE_HEAD

?

?*

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

SPACING_RULE_SET

DP_2DP

DP_2OTHERHS

DP_2OTHER

DP_AUX

WEIGHT

SPACING_RULE_SET

DP_2DP

DP_2OTHERHS

DP_2OTHER

MINIMUM NECK WIDTH

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

NOTE: 25MHz system clocks very sensitive to noise.

?

MAXIMUM NECK LENGTH

=45_OHM_SE=45_OHM_SE =45_OHM_SE =45_OHM_SE

MAXIMUM NECK LENGTH

=45_OHM_SE

MAXIMUM NECK LENGTH

=45_OHM_SE

MAXIMUM NECK LENGTH

=80_OHM_DIFF=80_OHM_DIFF

LAYER

TOP,BOTTOM

MAXIMUM NECK LENGTH

=45_OHM_SE=45_OHM_SE=45_OHM_SE

=45_OHM_SE=45_OHM_SE=45_OHM_SE=45_OHM_SE

DIFFPAIR PRIMARY GAP

=STANDARD =STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD

DIFFPAIR PRIMARY GAP

LINE-TO-LINE SPACING

=4x_DIELECTRIC

=6x_DIELECTRIC

=4x_DIELECTRIC

DIFFPAIR PRIMARY GAP

=STANDARD =STANDARD

PCH Net Properties

ELECTRICAL_CONSTRAINT_SET

LPC_AD LPC_FRAME_L

LPC_CLK33M

SMBUS_PCH_CLK

SMBUS_PCH_DATA SMBUS_PCH_0_CLK

SMBUS_PCH_0_DATA SMBUS_SMC_1_S0_SCL

SMBUS_SMC_1_S0_SDA

HDA_BIT_CLK

HDA_SYNC

HDA_RST_L

HDA_SDIN0

HDA_SDOUT

PM_SUS_CLK

SPI_CLK

SPI_MOSI

SPI_MISO

SPI_CS0

PCIE_AP_R2D PCIE_AP_R2D

PCIE_AP_D2R PCIE_PCH_RX

PCIE_AP_D2R PCIE_PCH_RX PCIE_CLK100M_AP

PCIE_CLK100M_AP

PCIE_TBT_R2D

PCIE_TBT_D2R

PCIE_CLK100M_TBT

PCIE_CLK100M_TBT CLK_PCIE

XDP_TDI PCH_45S PCH_ITP

XDP_TDO PCH_ITPPCH_45S

PCIE_CAM PCIE_80D PCIE_CAM PCIE_80D

PCIE_CAM PCIE_80D

PCIE_CAM

PCIE_CLK100M_CAM

PHYSICAL

LPC_45S LPC_45S

LPC_45S CLK_LPC_45S

CLK_LPC_45S

CLK_LPC_45S CLK_LPC_45S

SMB_45S_R_50S

SMB_45S_R_50S SMB_45S_R_50S

SMB_45S_R_50S

HDA_45S

HDA_45S HDA_45S

HDA_45S

HDA_45S HDA_45S

CLK_SLOW_45S CLK_SLOW_45S

SPI_45S

SPI_45S SPI_45S

SPI_45S

SPI_45S SPI_45S

SPI_45S

SPI_45S SPI_45S

SPI_45S

SPI_45S SPI_45S

SPI_45S

SPI_45S SPI_45S

SPI_45S

PCIE_80D PCIE_80D

PCIE_80D

PCIE_80D PCIE_80D

PCIE_80D CLK_PCIE_80D

CLK_PCIE_80D

PCIE_80D

PCIE_80D PCIE_80D

PCIE_80D

PCIE_80D PCIE_80D

PCIE_80D CLK_PCIE_80D

CLK_PCIE_80D

PCH_45S PCH_ITPXDP_TMS PCH_45S PCH_ITPXDP_TCK

PCIE_80D

PCIE_80D PCIE_80D

CLK_PCIE_80D

CLK_PCIE_80D CLK_PCIE_80D

CLK_PCIE_80D

NET_TYPE

SPACING

LPC LPC

LPC CLK_LPC

CLK_LPC

CLK_LPC CLK_LPC

SMB

SMB SMB

SMB

HDA

HDA HDA

HDA

HDA HDA

CLK_SLOW CLK_SLOW

SPI

SPI SPI

SPI

SPI SPI

SPI

SPI SPI

SPI

SPI SPI

SPI

SPI SPI

SPI

PCIE_PCH_TX PCIE_PCH_TX

PCIE_PCH_TX

CLK_PCIE

PCIE_PCH_TX

PCIE_PCH_TX PCIE_PCH_TX

PCIE_PCH_RX

PCIE_PCH_RX PCIE_PCH_RX

PCIE_PCH_RX CLK_PCIE

CLK_PCIE

PCIE_PCH_TX PCIE_PCH_TX

PCIE_PCH_TX

PCIE_PCH_TX PCIE_PCH_RX

PCIE_PCH_RX

PCIE_PCH_RX PCIE_PCH_RX

CLK_PCIE

CLK_PCIE CLK_PCIE

CLK_PCIE

LPC_AD<3..0> LPC_FRAME_L LPCPLUS_RESET_L LPC_CLK24M_SMC LPC_CLK24M_SMC_R LPC_CLK24M_LPCPLUS LPC_CLK24M_LPCPLUS_R

SMBUS_PCH_CLK SMBUS_PCH_DATA SML_PCH_0_CLK SML_PCH_0_DATA SMBUS_SMC_1_S0_SCL SMBUS_SMC_1_S0_SDA

HDA_BIT_CLK HDA_BIT_CLK_R HDA_SYNC HDA_SYNC_R HDA_RST_R_L HDA_RST_L HDA_SDIN0 HDA_SDOUT HDA_SDOUT_R

PM_CLK32K_SUSCLK_R SMC_CLK32K SPI_CLK_R SPI_CLK SPI_MOSI_R SPI_MOSI SPI_MISO SPI_MISO_R SPI_CS0_R_L SPI_CS0_L SPI_SMC_CLK SPI_SMC_MOSI SPI_SMC_MISO SPI_SMC_CS_L

SPI_MLB_CLK SPI_MLB_IO2_WP_L SPI_MLB_IO3_HOLD_L

SPI_MLB_CS_L SPI_IO<2> SPI_IO2_R SPI_IO<3> SPI_IO3_R

PCIE_AP_R2D_P

PCIE_AP_R2D_N

PCIE_AP_R2D_C_P

PCIE_AP_R2D_C_N

PCIE_AP_D2R_P

PCIE_AP_D2R_N

PCIE_CLK100M_AP_P

PCIE_CLK100M_AP_N

PCIE_TBT_R2D_P<3..0>

PCIE_TBT_R2D_N<3..0>

PCIE_TBT_R2D_C_P<3..0>

PCIE_TBT_R2D_C_N<3..0>

PCIE_TBT_D2R_P<3..0>

PCIE_TBT_D2R_N<3..0>

PCIE_TBT_D2R_C_P<3..0>

PCIE_TBT_D2R_C_N<3..0>

PCIE_CLK100M_TBT_P

PCIE_CLK100M_TBT_N

PEG_CLK100M_P

PEG_CLK100M_N

XDP_PCH_TDI

XDP_PCH_TDO

XDP_PCH_TMS

XDP_PCH_TCK

PCIE_CAMERA_R2D_P

PCIE_CAMERA_R2D_N

PCIE_CAMERA_R2D_C_P

PCIE_CAMERA_R2D_C_N

PCIE_CAMERA_D2R_P

PCIE_CAMERA_D2R_N

PCIE_CAMERA_D2R_C_P

PCIE_CAMERA_D2R_C_N

PCIE_CLK100M_CAMERA_P

PCIE_CLK100M_CAMERA_N

PCIE_CLK100M_CAMERA_C_P

PCIE_CLK100M_CAMERA_C_N

14 35 62

62

17 35

12 17

14 16 19 38 54

14 38

14 32 35 38 41 42 62 71

12 59 63

12

12 59 63

12

12 59 63

12 17

13 36

35 36

14 44

44

14 44

44

14 44

44

14 44

44

35 44

44

14 44

44

14 44

44

29 62

14 29

14 29 62

12 29 62

25

14 25

25

12 25

12 16 62

WEIGHT

=STANDARD=STANDARD

=STANDARD

=STANDARD=STANDARD

=STANDARD

=80_OHM_DIFF=80_OHM_DIFFDP_80D =80_OHM_DIFF

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

6 3

31 32

14 32

31 32

12 32

31 32

Clock Net Properties

ELECTRICAL_CONSTRAINT_SET

SYSCLK_CLK32K_RTC

SYSCLK_CLK25M_SB

SYSCLK_CLK25M_TBT

SYSCLK_CLK25M_XTAL

NET_TYPE

PHYSICAL

CLK_SLOW_45S

CLK_25M_45S

CLK_25M_45S CLK_25M_45S

CLK_25M_45S

CLK_25M_45S CLK_25M_45S

CLK_25M_45S

CLK_25M_45S CLK_25M_45S

CLK_25M_45S

SYNC_MASTER=J43_MLB

PAGE TITLE

SPACING

CLK_SLOW

CLK_25M

CLK_25M CLK_25M

CLK_25M

CLK_25M CLK_25M

CLK_25M

CLK_25M CLK_25M

CLK_25M

SYSCLK_CLK32K_RTCX1

SYSCLK_CLK25M_CAMERA CLK25M_CAM_CLKP CLK25M_CAM_XTALP_R CLK25M_CAM_XTALP CLK25M_CAM_XTALN CLK25M_CAM_CLKN

SYSCLK_CLK25M_TBT SYSCLK_CLK25M_TBT_R

SYSCLK_CLK25M_X1 SYSCLK_CLK25M_X2

SYSCLK_CLK25M_X2_R SDCLK_CLK25M_X2 SDCLK_CLK25M_X2_R SDSCLK_CLK25M_X1

PCH Constraints 2

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

12

SYNC_DATE=09/14/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

113 OF 120

SHEET

67 OF 73

124578

17 32

31 32

32

31 32

17 25

25

17

SIZE

D

C

B

A

D

8 7 6 5 4 3

Memory Bus Constraints

LAYER

MEM_40S

MEM_50S

MEM_70D

MEM_73D

Spacing Rule Sets

D

SPACING_RULE_SET

MEM_DATA2SELF

MEM_DATA2OTHERMEM

MEM_DQS2OWNDATA

LAYER

MEM_CMD2CMD

MEM_CMD2CTRL

MEM_CTRL2CTRL

MEM_CLK2CLK

MEM_2OTHERMEM

MEM_2PWR

MEM_2GND

MEM_2OTHER

Memory to Power Spacing

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_PWR

MEM_PWR DEFAULT

C

Memory to GND Spacing

NET_SPACING_TYPE1 NET_SPACING_TYPE2

GND *

Memory Bus Spacing Group Assignments

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_A_DQS_0 MEM_A_DQS_0

MEM_A_DQS_1

MEM_A_DQS_2

MEM_A_DQS_3

MEM_A_DQS_4

MEM_A_DQS_5

MEM_A_DQS_6

MEM_A_DQS_7

MEM_B_DQS_0

MEM_B_DQS_1

MEM_B_DQS_2

B

MEM_B_DQS_3

MEM_B_DQS_4

MEM_B_DQS_5

MEM_B_DQS_6

MEM_B_DQS_7

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_*_DATA_*

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_*_DATA_*

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_CMD

MEM_CTRL

A

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_CLK

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_* MEM_*

MEM_A_DATA_0

MEM_A_DATA_1

MEM_A_DATA_2

MEM_A_DATA_3

MEM_A_DATA_4

MEM_A_DATA_5

MEM_A_DATA_6

MEM_A_DATA_7

MEM_B_DATA_0

MEM_B_DATA_1

MEM_B_DATA_2

MEM_B_DATA_3

MEM_B_DATA_4

MEM_B_DATA_5

MEM_B_DATA_6

MEM_B_DATA_7

*

ALLOW ROUTE ON LAYER?

=40_OHM_SE

=50_OHM_SE

=70_OHM_DIFF

=73_OHM_DIFF

LINE-TO-LINE SPACING

MINIMUM LINE WIDTH

=40_OHM_SE =40_OHM_SE =40_OHM_SE =40_OHM_SE

=50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE=50_OHM_SE

=70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF

=73_OHM_DIFF =73_OHM_DIFF =73_OHM_DIFF =73_OHM_DIFF =73_OHM_DIFF

=2x_DIELECTRIC

*

=8x_DIELECTRIC

=3x_DIELECTRIC

*

=3x_DIELECTRIC

=6x_DIELECTRIC

* ?

=4x_DIELECTRIC

=2x_DIELECTRIC

*

=2x_DIELECTRIC

*

=6x_DIELECTRIC

AREA_TYPE

MEM_*

*

AREA_TYPE

SPACING_RULE_SET

*

SPACING_RULE_SET

MEM_*

AREA_TYPE

=SAME

AREA_TYPE

MEM_*

AREA_TYPE

MEM_CMDMEM_CMD

MEM_CTRL

AREA_TYPE

MEM_CLK

AREA_TYPE

*

SPACING_RULE_SET

MEM_DQS2OWNDATA

SPACING_RULE_SET

MEM_DATA2OTHERMEM

SPACING_RULE_SET

MEM_CLK2CLK

SPACING_RULE_SET

*

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?*

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?*

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?*

TABLE_SPACING_RULE_ITEM

?*

TABLE_SPACING_RULE_ITEM

?*

TABLE_SPACING_RULE_ITEM

10000

TABLE_SPACING_RULE_ITEM

10000

TABLE_SPACING_RULE_ITEM

?*

MEM_2PWR

MEM_2GND

MEM_DATA2SELF

MEM_CMD2CMD

MEM_CMD2CTRL

MEM_CTRL2CTRL

MEM_2OTHERMEM

MINIMUM NECK WIDTH

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

MAXIMUM NECK LENGTH

=40_OHM_SE

NET_PHYSICAL_TYPE

MEM_70D MEM_40S

NET_SPACING_TYPE1 NET_SPACING_TYPE2

AREA_TYPE

MEM_TERM

PHYSICAL_RULE_SET

* *

MEM_A_DQS_1

MEM_A_DQS_2

MEM_A_DQS_3

MEM_A_DQS_4

MEM_A_DQS_5

MEM_A_DQS_6

MEM_A_DQS_7

MEM_B_DQS_0

MEM_B_DQS_1

* *

MEM_B_DQS_2

MEM_B_DQS_3

MEM_B_DQS_4

MEM_B_DQS_5

MEM_B_DQS_6

MEM_B_DQS_7

*

* *

*

MEM_A_DATA_0

MEM_A_DATA_1

MEM_A_DATA_2

MEM_A_DATA_3

MEM_A_DATA_4

MEM_A_DATA_5

MEM_A_DATA_6

MEM_A_DATA_7

* *

MEM_B_DATA_0

MEM_B_DATA_1

MEM_B_DATA_2

MEM_B_DATA_3

MEM_B_DATA_4

MEM_B_DATA_5

MEM_B_DATA_6

MEM_B_DATA_7

MEM_CMD

MEM_CTRL

*

MEM_CLK

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEMTABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_A_DATA_0 MEM_*_DATA_*

MEM_A_DATA_1 MEM_*_DATA_*

MEM_A_DATA_2 MEM_*_DATA_*

MEM_A_DATA_3 MEM_*_DATA_*

MEM_A_DATA_4 MEM_*_DATA_*

MEM_A_DATA_5 MEM_*_DATA_*

MEM_A_DATA_6 MEM_*_DATA_*

MEM_A_DATA_7*MEM_*_DATA_*

MEM_B_DATA_0 MEM_*_DATA_*

MEM_B_DATA_1 MEM_*_DATA_*

MEM_B_DATA_2 MEM_*_DATA_*

MEM_B_DATA_3 MEM_*_DATA_*

MEM_B_DATA_4 MEM_*_DATA_*

MEM_B_DATA_5 MEM_*_DATA_*

MEM_B_DATA_6 MEM_*_DATA_*

MEM_B_DATA_7 MEM_*_DATA_*

AREA_TYPE

*

MEM_2OTHERMEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

SPACING_RULE_SET

DIFFPAIR PRIMARY GAP

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

MEM_73D

TABLE_PHYSICAL_ASSIGNMENT_ITEM

MEM_50S

AREA_TYPE

**

*

**

*

**

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=70_OHM_DIFF

SPACING_RULE_SET

MEM_2OTHER

6 3

Memory Net Properties

ELECTRICAL_CONSTRAINT_SET

MEM_A_CLK0 MEM_A_CLK0 MEM_A_CLK1 MEM_A_CLK1 MEM_A_CTRL MEM_A_CTRL MEM_A_CKE0 MEM_A_CKE1 MEM_A_CMD0 MEM_A_CMD1 MEM_A_DQ_BYTE0 MEM_40S MEM_A_DQ_BYTE1 MEM_40S MEM_A_DQ_BYTE2 MEM_40S MEM_A_DQ_BYTE3 MEM_40S MEM_A_DQ_BYTE4 MEM_40S MEM_A_DQ_BYTE5 MEM_40S MEM_A_DQ_BYTE6 MEM_40S MEM_A_DQ_BYTE7 MEM_40S MEM_A_DQS0 MEM_A_DQS0 MEM_A_DQS1 MEM_A_DQS1 MEM_A_DQS2 MEM_A_DQS2 MEM_A_DQS3 MEM_A_DQS3 MEM_A_DQS4 MEM_A_DQS4 MEM_A_DQS5 MEM_A_DQS5 MEM_A_DQS6 MEM_A_DQS6 MEM_A_DQS7 MEM_A_DQS7

MEM_B_CLK0 MEM_B_CLK0 MEM_B_CLK1 MEM_B_CLK1 MEM_B_CTRL MEM_B_CTRL MEM_B_CKE0 MEM_B_CKE1 MEM_B_CMD0 MEM_B_CMD1 MEM_B_DQ_BYTE0 MEM_B_DQ_BYTE1 MEM_B_DQ_BYTE2 MEM_B_DQ_BYTE3

MEM_B_DQ_BYTE5 MEM_40S MEM_B_DQ_BYTE6 MEM_40S MEM_B_DQ_BYTE7 MEM_40S MEM_B_DQS0 MEM_B_DQS0 MEM_B_DQS1 MEM_B_DQS1 MEM_B_DQS2 MEM_B_DQS2 MEM_B_DQS3 MEM_B_DQS3 MEM_B_DQS4 MEM_B_DQS4 MEM_B_DQS5 MEM_B_DQS5 MEM_B_DQS6 MEM_B_DQS6 MEM_B_DQS7 MEM_B_DQS7

PHYSICAL

MEM_70D MEM_CLK MEM_70D MEM_CLK

MEM_40S MEM_40S

MEM_40S MEM_CMD MEM_40S MEM_40S

MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D

MEM_70D MEM_CLK MEM_70D MEM_CLK MEM_70D MEM_CLK MEM_70D MEM_CLK MEM_40S MEM_40S MEM_40S MEM_CMD MEM_40S MEM_CMD MEM_40S MEM_CMD MEM_40S MEM_CMD MEM_40S MEM_40S MEM_40S MEM_40S MEM_40SMEM_B_DQ_BYTE4

MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D

NET_TYPE

SPACING

MEM_CLKMEM_70D

MEM_CLKMEM_70D MEM_CTRL MEM_CTRL MEM_CMDMEM_40S

MEM_CMD MEM_CMD MEM_A_DATA_0 MEM_A_DATA_1 MEM_A_DATA_2 MEM_A_DATA_3 MEM_A_DATA_4 MEM_A_DATA_5 MEM_A_DATA_6 MEM_A_DATA_7 MEM_A_DQS_0 MEM_A_DQS_0 MEM_A_DQS_1 MEM_A_DQS_1 MEM_A_DQS_2 MEM_A_DQS_2 MEM_A_DQS_3 MEM_A_DQS_3 MEM_A_DQS_4 MEM_A_DQS_4 MEM_A_DQS_5 MEM_A_DQS_5 MEM_A_DQS_6 MEM_A_DQS_6 MEM_A_DQS_7 MEM_A_DQS_7

MEM_CTRL MEM_CTRL

MEM_B_DATA_0 MEM_B_DATA_1 MEM_B_DATA_2 MEM_B_DATA_3 MEM_B_DATA_4 MEM_B_DATA_5 MEM_B_DATA_6 MEM_B_DATA_7 MEM_B_DQS_0 MEM_B_DQS_0 MEM_B_DQS_1 MEM_B_DQS_1 MEM_B_DQS_2 MEM_B_DQS_2 MEM_B_DQS_3 MEM_B_DQS_3 MEM_B_DQS_4 MEM_B_DQS_4 MEM_B_DQS_5 MEM_B_DQS_5 MEM_B_DQS_6 MEM_B_DQS_6 MEM_B_DQS_7 MEM_B_DQS_7

MEM_PWR MEM_PWR MEM_PWR MEM_PWR MEM_PWR

MEM_A_CLK_P<0> MEM_A_CLK_N<0> MEM_A_CLK_P<1> MEM_A_CLK_N<1> MEM_A_CS_L<1..0> MEM_A_ODT<0> MEM_A_CKE<1..0> MEM_A_CKE<3..2> MEM_A_CAA<9..0> MEM_A_CAB<9..0> MEM_A_DQ<7..0> MEM_A_DQ<15..8> MEM_A_DQ<23..16> MEM_A_DQ<31..24> MEM_A_DQ<39..32> MEM_A_DQ<47..40> MEM_A_DQ<55..48> MEM_A_DQ<63..56> MEM_A_DQS_P<0> MEM_A_DQS_N<0> MEM_A_DQS_P<1> MEM_A_DQS_N<1> MEM_A_DQS_P<2> MEM_A_DQS_N<2> MEM_A_DQS_P<3> MEM_A_DQS_N<3> MEM_A_DQS_P<4> MEM_A_DQS_N<4> MEM_A_DQS_P<5> MEM_A_DQS_N<5> MEM_A_DQS_P<6> MEM_A_DQS_N<6> MEM_A_DQS_P<7> MEM_A_DQS_N<7>

MEM_B_CLK_P<0> MEM_B_CLK_N<0> MEM_B_CLK_P<1> MEM_B_CLK_N<1> MEM_B_CS_L<1..0> MEM_B_ODT<0> MEM_B_CKE<1..0> MEM_B_CKE<3..2> MEM_B_CAA<9..0> MEM_B_CAB<9..0> MEM_B_DQ<7..0> MEM_B_DQ<15..8> MEM_B_DQ<23..16> MEM_B_DQ<31..24> MEM_B_DQ<39..32> MEM_B_DQ<47..40> MEM_B_DQ<55..48> MEM_B_DQ<63..56> MEM_B_DQS_P<0> MEM_B_DQS_N<0> MEM_B_DQS_P<1> MEM_B_DQS_N<1> MEM_B_DQS_P<2> MEM_B_DQS_N<2> MEM_B_DQS_P<3> MEM_B_DQS_N<3> MEM_B_DQS_P<4> MEM_B_DQS_N<4> MEM_B_DQS_P<5> MEM_B_DQS_N<5> MEM_B_DQS_P<6> MEM_B_DQS_N<6> MEM_B_DQS_P<7> MEM_B_DQS_N<7>

PP1V2_S3 PP0V6_S3_MEM_VREFCA_A PP0V6_S3_MEM_VREFDQ_A PP0V6_S3_MEM_VREFCA_B PP0V6_S3_MEM_VREFDQ_B

SYNC_MASTER=CHINMAY_J41

PAGE TITLE

Memory Constraints

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

12

7

20 24

7

20 24

7

21 24

7

21 24

7

20 21 24

7

20 21 24 61

7

20 24

7

21 24

7

20 24 61

7

21 24 61

7

61

7

61

7

61

7

61

7

21 61

7

61

7

61

7

61

7

61

7

61

7

61

7

61

7

61

7

61

7

61

7

61

7

61

7

61

7

61

7

61

7

21 61

7

21 61

7

61

7

61

7

22 24

7

22 24

7

23 24

7

23 24

7

22 23 24

7

22 23 24 61

7

22 24

7

23 24

7

22 24 61

7

23 24 61

7

61

7

61

7

61

7

61

7

23 61

7

61

7

61

7

61

7

61

7

61

7

61

7

61

7

61

7

61

7

61

7

61

7

61

7

61

7

61

7

61

7

23 61

7

23 61

7

61

7

61

17 19 20 21 22 23 40 51 60

18 19 20 21

18 19 22 23

SYNC_DATE=09/07/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

114 OF 120

SHEET

68 OF 73

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

DisplayPort Signal Constraints

NOTE: DisplayPort Physical/Spacing Constraints provided by Chipset or GPU page.

Thunderbolt SPI Signal Constraints

LAYER

TBT_SPI_45S

SPACING_RULE_SET

TBT_SPI

D

Thunderbolt/DP Connector Signal Constraints

TBTDP_80D

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TBTDP_TX TBTDP_TX

TBTDP_RX TBTDP_RX

TBTDP_TX TBTDP_RX

TBTDP_RX

TBTDP_TX

TBTDP_RX

TBTDP_TX

TBTDP_RX

TBTDP_TX

TBTDP_RX

LAYER

ALLOW ROUTE ON LAYER?

*

=45_OHM_SE =45_OHM_SE =45_OHM_SE =45_OHM_SE

MINIMUM LINE WIDTH

LINE-TO-LINE SPACING

*

TBTDP_TX

=2x_DIELECTRIC

ALLOW ROUTE ON LAYER?

=80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF

*_TX

*_RX

*

AREA_TYPE

*

**

MINIMUM LINE WIDTH

=80_OHM_DIFF

SPACING_RULE_SET

TBTDP_TX2TX

TBTDP_RX2RX

TBTDP_TX2RX

TBTDP_2OTHERHS

TBTDP_2OTHER

C

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM NECK WIDTH

SPACING_RULE_SET

TBTDP_TX2TX

TBTDP_RX2RX

TBTDP_TX2RX

TBTDP_2OTHERHS

TBTDP_2OTHER

SPACING_RULE_SET

TBTDP_TX2TX

TBTDP_RX2RX

TBTDP_TX2RX

TBTDP_2OTHER

MAXIMUM NECK LENGTH

LAYER

TOP,BOTTOM

LAYER

*

DIFFPAIR PRIMARY GAP

=STANDARD =STANDARD

DIFFPAIR PRIMARY GAP

LINE-TO-LINE SPACING

=6x_DIELECTRIC

=10x_DIELECTRIC

=6x_DIELECTRIC

LINE-TO-LINE SPACING

=4x_DIELECTRIC

=6x_DIELECTRIC

=6x_DIELECTRICTBTDP_2OTHERHS

=4x_DIELECTRIC

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

WEIGHT

?

WEIGHT

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

Thunderbolt/DP Net Properties

ELECTRICAL_CONSTRAINT_SET

TBT_A_R2D TBTDP_80D TBT_A_R2D TBTDP_80D

DP_TBTPA_ML3 DP_TBTPA_ML3

TBT_A_D2R1

TBT_A_D2R1 TBT_A_D2R0

TBT_A_D2R0

TBT_A_AUXCH

TBT_B_R2D TBT_B_R2D TBTDP_80D

DP_TBTPB_ML DP_TBTPB_ML

TBT_B_D2R TBTDP_80D

TBT_B_AUXCH TBT_B_AUXCH

PHYSICAL

TBTDP_80D TBTDP_80D

DP_80DDP_TBTPA_ML1

DP_80D DP_80D

DP_80D

DP_80D DP_80D

DP_80D

TBTDP_80D TBTDP_80D

TBTDP_80D

TBTDP_80D TBTDP_80D

TBTDP_80D

DP_80D

DP_80D DP_80D

TBTDP_80D

DP_80D DP_80D

DP_80D

TBTDP_80D TBTDP_80D

TBTDP_80DTBT_B_D2R

DP_80D DP_80D

DP_80D

DP_80D TBTDP_80D

TBTDP_80D

NET_TYPE

TBTDP_TX TBTDP_TX

DP_TX

DP_TX DP_TX

DP_TX

DP_TX DP_TX

DP_TX

TBTDP_RX TBTDP_RX

TBTDP_RX

TBTDP_RX TBTDP_RX

TBTDP_RX

DP_AUX

DP_AUXDP_80D

DP_AUX DP_AUX

DP_AUXDP_80D DP_AUXDP_80D

TBTDP_RX

TBTDP_TX TBTDP_TX

TBTDP_TX

DP_TX DP_TX

DP_TX

TBTDP_RX TBTDP_RX

TBTDP_RX

DP_AUX DP_AUX

DP_AUX

DP_AUX TBTDP_RX

TBTDP_RX

SPACING

TBT_A_R2D_C_P<1..0> TBT_A_R2D_C_N<1..0> TBT_A_R2D_P<1..0> TBT_A_R2D_N<1..0>

DP_TBTPA_ML_C_P<1> DP_TBTPA_ML_C_N<1> DP_TBTPA_ML_C_P<3> DP_TBTPA_ML_C_N<3> DP_TBTPA_ML_P<3..1:2> DP_TBTPA_ML_N<3..1:2> DP_A_LSX_ML_P<1> DP_A_LSX_ML_N<1>

TBT_A_D2R_C_P<1..0> TBT_A_D2R_C_N<1..0> TBT_A_D2R_P<1> TBT_A_D2R_N<1> TBT_A_D2R_P<0> TBT_A_D2R_N<0>

DP_TBTPA_AUXCH_C_P DP_TBTPA_AUXCH_C_N DP_TBTPA_AUXCH_P DP_TBTPA_AUXCH_N DP_A_AUXCH_DDC_P DP_A_AUXCH_DDC_N TBT_A_D2R1_AUXDDC_P TBT_A_D2R1_AUXDDC_N

TBT_B_R2D_C_P<1..0> TBT_B_R2D_C_N<1..0> TBT_B_R2D_P<1..0> TBT_B_R2D_N<1..0>

NC_DP_TBTPB_ML_CP<3..1:2> NC_DP_TBTPB_ML_CN<3..1:2> DP_TBTPB_ML_P<3..1:2> DP_TBTPB_ML_N<3..1:2> DP_B_LSX_ML_P<1> DP_B_LSX_ML_N<1>

TBT_B_D2R_C_P<1..0> TBT_B_D2R_C_N<1..0> TBT_B_D2R_P<1..0> TBT_B_D2R_N<1..0>

NC_DP_TBTPB_AUXCH_CP NC_DP_TBTPB_AUXCH_CN DP_TBTPB_AUXCH_P DP_TBTPB_AUXCH_N DP_B_AUXCH_DDC_P DP_B_AUXCH_DDC_N TBT_B_D2R1_AUXDDC_P TBT_B_D2R1_AUXDDC_N

25 28

28

25 28

28

25 28

28

62

Only used on dual-port hosts.

62

25 62

12

D

C

Thunderbolt IC Net Properties

ELECTRICAL_CONSTRAINT_SET

B

TBT_SPI_CLK TBT_SPI_45S

TBT_SPI_MOSI

TBT_SPI_MISO TBT_SPI_CS_L

A

6 3

NET_TYPE

PHYSICAL

DP_80D

DP_80D DP_80D DP_AUX

DP_80D DP_AUX

TBT_SPI_45S

TBT_SPI_45S TBT_SPI_45S

DP_TX

TBT_SPI

TBT_SPI TBT_SPI

SPACING

DP_TBTSRC_ML_C_P<3..0> DP_TBTSRC_ML_C_N<3..0> DP_TBTSRC_AUXCH_C_P DP_TBTSRC_AUXCH_C_N

TBT_SPI_CLK TBT_SPI_MOSI TBT_SPI_MISO TBT_SPI_CS_L

Only used on hosts supporting Thunderbolt video-in

25

SYNC_MASTER=CHINMAY_J41

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

Thunderbolt Constraints

Apple Inc.

R

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

115 OF 120

SHEET

124578

SYNC_DATE=09/07/2012

69 OF 73

SIZE

B

A

D

8 7 6 5 4 3

12

Camera Net Properties

ELECTRICAL_CONSTRAINT_SET

MIPI Interface Constraints

*

ALLOW ROUTE ON LAYER?

=85_OHM_DIFF

LINE-TO-LINE SPACING

LAYER

D

MIPI_85D

SPACING_RULE_SET

MIPI_2OTHER

MIPI_2CLK

MIPICLK_2OTHER

LAYER

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MIPI_DATA

CLK_MIPI

* *

CLK_MIPI

*

=4X_DIELECTRIC

=6X_DIELECTRIC

=7X_DIELECTRIC

AREA_TYPE

*

MINIMUM LINE WIDTH

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

SPACING_RULE_SET

MIPI_2OTHER

MIPI_2CLK

MIPICLK_2OTHER

WEIGHT

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM NECK WIDTH

SPACING_RULE_SET

MIPI_2OTHER

MIPI_2CLK

MIPICLK_2OTHER

MAXIMUM NECK LENGTH

LAYER

TOP,BOTTOM

DIFFPAIR PRIMARY GAP

=85_OHM_DIFF =85_OHM_DIFF

LINE-TO-LINE SPACING

=6X_DIELECTRIC

=8X_DIELECTRIC

=10X_DIELECTRIC

WEIGHT

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

Memory Bus Constraints

LAYER

S2_MEM_45S =45_OHM_SE

S2_MEM_85D

C

Spacing Rule Sets

SPACING_RULE_SET

S2_DATA2SELF

S2_DQS2OWNDATA

LAYER

S2_CMD2CMD

S2_CMD2CTRL

S2_CTRL2CTRL

S2_2OTHERMEM

S2MEM_2PWR

S2MEM_2GND

S2MEM_2OTHER

ALLOW ROUTE ON LAYER?

=45_OHM_SE

*

=85_OHM_DIFF

LINE-TO-LINE SPACING

=2x_DIELECTRIC

* ?

=2x_DIELECTRIC

=4x_DIELECTRIC

* ?

=2x_DIELECTRIC

=6x_DIELECTRIC

* ?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=45_OHM_SE

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

TABLE_SPACING_RULE_HEAD

?*

SPACING_RULE_SET

TABLE_SPACING_RULE_ITEM

S2_DATA2SELF

S2_DQS2OWNDATA =4x_DIELECTRIC

S2_CMD2CMD

S2_CMD2CTRL

S2_CTRL2CTRL

S2_2OTHERMEM

S2MEM_2PWR

S2MEM_2GND TOP,BOTTOM

S2MEM_2OTHER

TOP,BOTTOM

WEIGHT

=45_OHM_SE

LAYER

DIFFPAIR PRIMARY GAP

=STANDARD

=85_OHM_DIFF =85_OHM_DIFF

LINE-TO-LINE SPACING

=4x_DIELECTRIC

=6x_DIELECTRIC

=4x_DIELECTRIC

=10x_DIELECTRIC

WEIGHT

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

=STANDARD

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

S2_MEM_CLK S2_MEM_CLKS2_MEM_85D S2_MEM_CLK S2_MEM_85D S2_MEM_CLK

S2_MEM_CNTL S2_MEM_CTRL

I101

I102

S2_MEM_CMD S2_MEM_45S

I103

I104

S2_MEM_CMD S2_MEM_45S

S2_MEM_DQS0

I106

S2_MEM_DQS0 S2_MEM_DQS1

I108

S2_MEM_DQS1

I107

S2_MEM_DATA_0

I109

S2_MEM_DATA_1

I110

S2_MEM_A

I147

S2_MEM_DATA_0

S2_MEM_DATA_1

MIPI_DATA_S2

I127

MIPI_DATA_S2

I128

I129

I130

MIPI_CLK_S2

I134

MIPI_CLK_S2

I133

I132

I131

I145

I146

I148

I149

PHYSICAL

S2_MEM_45S

S2_MEM_45SS2_MEM_CMD

S2_MEM_85D

S2_MEM_85D S2_MEM_85D

S2_MEM_85D

S2_MEM_45S S2_MEM_45S

S2_MEM_45S

MIPI_85D

MIPI_85D MIPI_85D

MIPI_85D

MIPI_85D MIPI_85D

NET_TYPE

SPACING

S2_MEM_CTRLS2_MEM_CNTL

S2_MEM_CTRL S2_MEM_CTRL

S2_MEM_CTRL

S2_MEM_CMDS2_MEM_45SS2_MEM_CMD S2_MEM_CMDS2_MEM_CMD S2_MEM_45S

S2_MEM_CMD S2_MEM_CMDS2_MEM_45SS2_MEM_CMD

S2_MEM_DQS0

S2_MEM_DQS0 S2_MEM_DQS1

S2_MEM_DQS1

S2_MEM_DATA0 S2_MEM_DATA1

S2_MEM_CMD

S2_MEM_DATA0

S2_MEM_DATA1

MIPI_DATA

MIPI_DATA MIPI_DATA

MIPI_DATA

CLK_MIPI

CLK_MIPI CLK_MIPI

S2_MEM_PWR

S2_MEM_PWR S2_MEM_PWR

MEM_CAM_CLK_P MEM_CAM_CLK_N

MEM_CAM_CKE MEM_CAM_CS_L MEM_CAM_ODT MEM_CAM_CAS_L MEM_CAM_RAS_L MEM_CAM_WE_L MEM_CAM_BA<0> MEM_CAM_BA<1> MEM_CAM_BA<2> MEM_CAM_DQS_P<0> MEM_CAM_DQS_N<0> MEM_CAM_DQS_P<1> MEM_CAM_DQS_N<1> MEM_CAM_DM<0> MEM_CAM_DM<1> MEM_CAM_A<14..0>

MEM_CAM_DQ<7..0> MEM_CAM_DQ<15..8>

MIPI_DATA_P MIPI_DATA_N MIPI_DATA_CONN_P MIPI_DATA_CONN_N

MIPI_CLK_P MIPI_CLK_N MIPI_CLK_CONN_P MIPI_CLK_CONN_N

PP1V35_CAM PP0V675_CAM_VREF PP0V675_MEM_CAM_VREFCA PP0V675_MEM_CAM_VREFDQ

31 32

32

31 32

32 62

31 32

32 62

31 32

32

D

C

Memory Bus Spacing Group Assignments

S2MEM_2OTHERS2_MEM_DATA*

S2MEM_2OTHER

S2_DATA2SELF

S2_CMD2CMD

S2_CMD2CTRL

S2_CTRL2CTRL

S2_2OTHERMEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

NET_SPACING_TYPE1 NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

* *

S2_MEM_DQS*

S2_MEM_CMD

B

S2_MEM_CTRL

S2_MEM_CLK

S2_MEM_DATA*

S2_MEM_CMD

* *

*

=SAME

S2_MEM_CMD

S2_MEM_CTRL

S2_MEM_CTRL S2_MEM_CTRL

S2_MEM_*S2_MEM_*

**

*

NET_SPACING_TYPE1 NET_SPACING_TYPE2

S2_MEM_DQS1

S2_MEM_DQS0

S2_MEM_DATA1

S2_MEM_DATA0

Memory to Power Spacing

NET_SPACING_TYPE1 NET_SPACING_TYPE2

S2_MEM_PWR

S2_MEM_*

AREA_TYPE

*

AREA_TYPE

*

**

SPACING_RULE_SET

S2_DQS2OWNDATA

S2MEM_2PWR

DEFAULT

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

B

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

Memory to GND Spacing

S2MEM_2GND

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

SYNC_MASTER=CHINMAY_J41

PAGE TITLE

Camera Constraints

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=09/07/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

116 OF 120

SHEET

70 OF 73

124578

SIZE

A

D

NET_SPACING_TYPE1 NET_SPACING_TYPE2

GND

S2_MEM_*

AREA_TYPE

SPACING_RULE_SET

*

A

6 3

8 7 6 5 4 3

1TO1_DIFFPAIR

2TO1_DIFFPAIR

LAYER

ALLOW ROUTE ON LAYER?

*

=STANDARD

MINIMUM LINE WIDTH

=STANDARD =STANDARD=STANDARD

0.2 MM

MINIMUM NECK WIDTH

0.1 MM

MAXIMUM NECK LENGTH

=STANDARD

DIFFPAIR PRIMARY GAP

0.1 MM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

0.1 MM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

D

SMC SMBus Net Properties

ELECTRICAL_CONSTRAINT_SET

SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA

SMBUS_SMC_1_S0_SCL SMBUS_SMC_1_S0_SDA

SMBUS_SMC_2_S3_SCL

SMBUS_SMC_2_S3_SDA SMBUS_SMC_3_SCL

SMBUS_SMC_3_SDA

SMBUS_SMC_5_G3_SCL SMBUS_SMC_5_G3_SDA

PHYSICAL

SMB_45S_R_50S SMB_45S_R_50S

SMB_45S_R_50S

SMB_45S_R_50S SMB_45S_R_50S

SMB_45S_R_50S

SMB_45S_R_50S SMB_45S_R_50S

NET_TYPE

SMB SMB

SMB

SMB SMB

SMB

SMB SMB

SPACING

SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_1_S0_SCL SMBUS_SMC_1_S0_SDA SMBUS_SMC_2_S3_SCL SMBUS_SMC_2_S3_SDA SMBUS_SMC_3_SCL SMBUS_SMC_3_SDA SMBUS_SMC_5_G3_SCL SMBUS_SMC_5_G3_SDA

35 38 58

14 32 35 38 41 42 62 67

35 38 59 63

34 35 38 42 62

35 38 46 48 62

12

D

SMBus Charger Net Properties

ELECTRICAL_CONSTRAINT_SET

SENSE_DIFFPAIR

SENSE_DIFFPAIR SENSE_DIFFPAIR

2TO1_DIFFPAIR

2TO1_DIFFPAIR 2TO1_DIFFPAIR

2TO1_DIFFPAIR

C

PHYSICAL

NET_TYPE

SPACING

CHGR_CSI_P CHGR_CSI_N CHGR_CSI_R_P CHGR_CSI_R_N

CHGR_CSO_P CHGR_CSO_N CHGR_CSO_R_P CHGR_CSO_R_N

48

41 48

C

SIZE

B

A

D

B

A

SYNC_MASTER=CHINMAY_J41

PAGE TITLE

SMC Constraints

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

6 3

SYNC_DATE=09/13/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

117 OF 120

SHEET

71 OF 73

124578

8 7 6 5 4 3

12

D

C

B

SENSE_1TO1_45S

SENSE_1TO1_P2MM

THERM_1TO1_45S

SPKR_DIFFPAIR

SPACING_RULE_SET

SENSE

THERM

AUDIO

SPACING_RULE_SET

GND

SPACING_RULE_SET

GND_P2MM

PWR_P2MM

LAYER

ALLOW ROUTE ON LAYER?

=1TO1_DIFFPAIR

*

=1TO1_DIFFPAIR

*

=1TO1_DIFFPAIR

*

=1TO1_DIFFPAIR

LINE-TO-LINE SPACING

*

LINE-TO-LINE SPACING

* ?

LINE-TO-LINE SPACING

*

MINIMUM LINE WIDTH

=45_OHM_SE

=2:1_SPACING

=STANDARD

0.20 MM

0.200 MM

0.300 MM

WEIGHT

10000

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM NECK WIDTH

=45_OHM_SE

0.100 MM

=45_OHM_SE

0.100 MM

NET_SPACING_TYPE1 NET_SPACING_TYPE2

CPU_COMP GND_P2MM

CPU_VCCSENSE

NET_SPACING_TYPE1 NET_SPACING_TYPE2

SB_POWER PWR_P2MM

GND

MAXIMUM NECK LENGTH

=45_OHM_SE

=1TO1_DIFFPAIR =1TO1_DIFFPAIR

=45_OHM_SE

=1TO1_DIFFPAIR

DIFFPAIR PRIMARY GAP

=1TO1_DIFFPAIR

AREA_TYPE

GND

AREA_TYPE

PCIE*

SATA*

USB*

LVDS*

CLK_PCIE

SATA*

*

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

GND_P2MM

GND_P2MMCLK_PCIE

GND_P2MM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

SPACING_RULE_SET

=1TO1_DIFFPAIR

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

J11/J13 Specific Net Properties

ELECTRICAL_CONSTRAINT_SET

SENSE_DIFFPAIR

SENSE_DIFFPAIR SENSE_DIFFPAIR

SENSE_DIFFPAIR

SENSE_DIFFPAIR SENSE_DIFFPAIR

SENSE_DIFFPAIR SENSE_1TO1_45S

SENSE_DIFFPAIR SENSE_DIFFPAIR

SENSE_DIFFPAIR SENSE_DIFFPAIR SENSE_1TO1_45S

SENSE_DIFFPAIR

SENSE_DIFFPAIR SENSE_DIFFPAIR

SENSE_DIFFPAIR

SENSE_DIFFPAIR SENSE_1TO1_45S

SENSE_DIFFPAIR

SENSE_DIFFPAIR SENSE_1TO1_45S SENSE_DIFFPAIR SENSE_1TO1_45S

SENSE_DIFFPAIR SENSE_DIFFPAIR SENSE_1TO1_45S

SENSE_DIFFPAIR SENSE_DIFFPAIR

SENSE_DIFFPAIR

I348

SENSE_DIFFPAIR

I349

AUD_DIFF

SPKR_OUT

THERM_1TO1_45S

PHYSICAL

THERM_1TO1_45S THERM_1TO1_45S

THERM_1TO1_45S

THERM_1TO1_45S THERM_1TO1_45SSENSE_DIFFPAIR

THERM_1TO1_45S

THERM_1TO1_45S THERM_1TO1_45SSENSE_DIFFPAIR

SENSE_1TO1_45S

SENSE_1TO1_45SSENSE_DIFFPAIR

SENSE_1TO1_45S

SENSE_1TO1_45SSENSE_DIFFPAIR

SENSE_1TO1_P2MM

SENSE_1TO1_P2MM SENSE_1TO1_45S

SENSE_1TO1_P2MM

SENSE_1TO1_45S SENSE_1TO1_45S

SENSE_1TO1_P2MM SENSE_1TO1_P2MM

SENSE_1TO1_45S

SENSE_1TO1_45S SENSE_1TO1_45S

SENSE_1TO1_P2MM

SENSE_1TO1_45SSENSE_DIFFPAIR

SENSE_1TO1_45S

SENSE_1TO1_45SSENSE_DIFFPAIR

SENSE_1TO1_45SSENSE_DIFFPAIR SENSE_1TO1_45SSENSE_DIFFPAIR

SENSE_1TO1_45S

SENSE_1TO1_45S SENSE_1TO1_45S

SENSE_1TO1_45S

1TO1_DIFFPAIR 1TO1_DIFFPAIR

1TO1_DIFFPAIR

1TO1_DIFFPAIR SPKR_DIFFPAIR

SPKR_DIFFPAIR

NET_TYPE

SPACING

THERM

THERM THERM

THERM

THERM THERM

THERM

THERM THERM

SENSE

SENSE SENSE

SENSE

SENSE SENSE

SENSE

SENSE SENSE

SENSE

SENSE SENSE

SENSE

SENSE SENSE

SENSE

AUDIO AUDIO

AUDIO

AUDIO AUDIO

AUDIO

SB_POWER

INLET_THMSNS_D1_P INLET_THMSNS_D1_N

TBTTHMSNS_D2_R_P TBTTHMSNS_D2_R_N TBTTHMSNS_D2_P TBTTHMSNS_D2_N TBT_MLBBOT_THMSNS_P TBT_MLBBOT_THMSNS_N MLBBOT_THMSNS_D3_P MLBBOT_THMSNS_D3_N

TBDTHMSNS_D2_P TBDTHMSNS_D2_N

CPUTHMSNS_D2_P CPUTHMSNS_D2_N

CPUVCCIOS0_CS_N CPUVCCIOS0_CS_P

CPUVR_ISNS1_P CPUVR_ISNS1_N CPUVR_ISNS2_P CPUVR_ISNS2_N

CPUVR_ISNS1_P_R CPUVR_ISNS1_N_R CPUVR_ISUM_R_P CPUVR_ISUM_R_N

ISNS_CPUDDR_P ISNS_CPUDDR_N ISNS_P3V3S5_N ISNS_P3V3S5_P

ISNS_3V3_S0_P ISNS_3V3_S0_N ISNS_CAMERA_P ISNS_CAMERA_N

ISNS_P3V3_S0_N ISNS_P3V3_S0_P

ISNS_1V05_S0_P ISNS_1V05_S0_N

ISNS_BMON_GAIN_P ISNS_BMON_GAIN_N

ISNS_HS_COMPUTING_N ISNS_HS_COMPUTING_P

ISNS_HS_OTHER_N ISNS_HS_OTHER_P

ISNS_1V2_S3_N ISNS_1V2_S3_P

ISNS_AIRPORT_N ISNS_AIRPORT_P

ISNS_SSD_N ISNS_SSD_P

ISNS_LCDBKLT_N ISNS_LCDBKLT_P

ISNS_PANEL_N ISNS_PANEL_P

ISNS_HS_GAIN_N ISNS_HS_GAIN_P

SPKRAMP_INR_P SPKRAMP_INR_N MAX98300_R_P MAX98300_R_N SPKRAMP_ROUT_P SPKRAMP_ROUT_N

PP3V3_S5 PP3V3_S0

42

40 50

40 41

40

39

40 53

39 41

39

39 51

39

41

41 42

45 59 63

45

45 62

8

11 13 15 16 17 18 28 29 40 52

55 56 57 58 60 62 60 62 63 8

11 12 13 15 17 18 26 30 34 36

37 38 39 40 41 42 43 54 57 59

D

C

B

A

GND

6 3

GND

SYNC_MASTER=J43_MLB

PAGE TITLE

Project Specific Constraints

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=09/13/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

118 OF 120

SHEET

72 OF 73

124578

SIZE

A

D

8 7 6 5 4 3

12

Change List:

<rdar://component/508389> J41 HW EE Schematic | Proto 0 <rdar://component/512995> J41 HW EE Schematic | Pre Proto 1 <rdar://component/508412> J41 HW EE Schematic | Proto 1

D

<rdar://component/508413> J41 HW EE Schematic | EVT <rdar://component/508414> J41 HW EE Schematic | DVT

D

Kismet:

afp://kismet.apple.com/Kismet-Projects/J41-J43

Useful Wiki Links:

Schematic Conventions - https://hmts.ecs.apple.com/wiki/index.php/User:Wferry/SchConventions Schematic Design Wiki - https://hmts.ecs.apple.com/wiki/index.php/Schematic_Design

MobileMac HW Radar:

<rdar://component/497591> MobileMac HW | Task <rdar://component/497587> MobileMac HW | Schematic

C

<rdar://component/497585> MobileMac HW | New Bugs <rdar://component/497588> MobileMac HW | Layout <rdar://component/497590> MobileMac HW | Investigation <rdar://component/497589> MobileMac HW | Architecture

C

Other Info:

Page Allocations - <rdar://problem/11791318> 2012 Schematic Page Allocations

B

A

6 3

SYNC_MASTER=MASTER

PAGE TITLE

Reference

Apple Inc.

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Apple MACBOOK AIR 11 A1465 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual