Apple d Schematics
TABLE_TABLEOFCONTENTS_ITEM
DRAWING
DRAWING
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_HEAD
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
PROPRIETARY PROPERTY OF APPLE INC.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
DESCRIPTION OF REVISION
CK
APPD
21
1245678
B
D
6543
C
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
THE INFORMATION CONTAINED HEREIN IS THE
C
A
D
DATE
R
SHEET
Apple Inc.
THE POSESSOR AGREES TO THE FOLLOWING:
DRAWING TITLE
D
SIZE
REVISION
DRAWING NUMBER
BRANCH
REV ECN
7
B
3
II NOT TO REPRODUCE OR COPY IT
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
IV ALL RIGHTS RESERVED
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
8
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TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
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TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
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TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
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TABLE_TABLEOFCONTENTS_ITEM
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D8 MLB
1 OF 117
2012-08-28
ENGINEERING RELEASED
1 OF 143
7.0.0
051-9504
7
0001607307
prefsb
60
65
D8_DIRK
AUDIO: Jack, Mikey, CHS Switch
06/29/2012
TITLE=K22
ABBREV=DRAWING
LAST_MODIFIED=Mon Aug 27 13:24:34 2012
LAST_MODIFIED=Mon Aug 27 13:24:34 2012
N/A
1
1
MASTER
Table of Contents
Contents
Date
(.csa)
SyncPage Sync
Date
Page
(.csa)
Contents
SCH,D8,MLB
61
66
D8_DAVID
Audio: Spkr/Mic Conn.
06/13/2012
62
67
D8_DAVID
AUDIO: Detects/Grounding
06/13/2012
63
68
D8_DAVID
AUDIO: Speaker ID
06/13/2012
64
69
D8_MARK
PM Regulator Enables
04/23/2012
65
70
D8_MARK
PM Power Good
04/23/2012
66
71
D8_MLB
VReg CPU Core/AXG Cntl
02/28/2012
67
72
D8_MLB
VReg CPU Core Phases
02/28/2012
68
73
D8_MLB
VReg CPU AXG Phases
02/28/2012
69
74
D8_KOSECOFF
VReg CPU 1.05V S0
02/25/2012
70
75
D8_KOSECOFF
VReg CPU VccSA S0
02/25/2012
71
76
D8_MLB
VReg 3.3V S5/5V S4
02/28/2012
72
77
D8_KOSECOFF
VReg VDDQ and 1.8V S0
02/25/2012
73
78
D8_MLB
VREG 3.42V G3HOT
04/11/2012
74
79
D8_MLB
FET-Controlled S0 and S4
05/14/2012
75
80
D8_AARON
KEPLER PCI-E
03/13/2012
76
81
D8_YAN
KEPLER CORE/FB POWER
04/09/2012
77
82
D8_YAN
KEPLER FRAME BUFFER I/F
05/15/2012
78
83
D8_YAN
GPU SIGNAL & POWER ALIASES
04/09/2012
79
84
D8_YAN
GDDR5 Frame Buffer A
04/09/2012
80
85
D8_YAN
GDDR5 Frame Buffer B
04/09/2012
81
86
D8_YAN
KEPLER EDP/DP/GPIO
04/09/2012
82
87
D8_YAN
KEPLER GPIOS,CLK & STRAPS
07/27/2012
83
88
D8_YAN
KEPLER PEX PWR/GNDS
04/09/2012
84
92
D8_AARON
Internal DP MUXing
03/13/2012
85
93
D7_MLB
TBT DDC Crossbar
03/15/2012
86
94
D8_AARON
Thunderbolt Connector A
03/13/2012
87
95
D8_MLB
Internal DP Support
03/21/2012
88
96
D8_AARON
Thunderbolt Connector B
03/13/2012
89
97
D8_MLB
Backlight Controller MCU
04/23/2012
90
98
D8_MLB
Backlight LED Driver
04/23/2012
91
99
D8_MLB
Backlight Controller
04/23/2012
92
114
D8_MLB
VReg GPU Core Phases
02/28/2012
93
115
D8_MLB
VReg GPU Core Phases
02/25/2012
94
116
D8_MLB
VREG GPU CORE PHASE 4
02/06/2012
95
117
D8_MLB
GPU VDDQ AND 1V05 GPU/PCH/TBT VREGS
04/18/2012
96
120
D8_KOSECOFF
D8 RULE DEFINITIONS
03/19/2012
97
121
D8_KOSECOFF
DDR3 Constraints
03/19/2012
98
122
D8_AARON
CPU PCIe Constraints
03/13/2012
99
123
D8_ROSITA
CPU MISC/DMI/FDI/XDP Constraints
03/23/2012
100
124
D8_MARK
SATA/FDI/XDP Constraints
02/10/2012
101
125
D8_MARK
PCH and BR Constraints
02/10/2012
102
126
D8_KOSECOFF
USB/Camera Constraints
06/22/2012
103
127
D8_MARK
SMBus/Sensor Constraints
04/23/2012
104
128
D8_MARK
VReg Constraints
02/10/2012
105
129
D8_MARK
CPU VReg Constraints
02/10/2012
106
130
D8_MARK
Platform VReg Constraints
02/10/2012
107
131
D8_AARON
TBT/DP Constraints
03/13/2012
108
132
D8_AARON
GDDR5/GPU Constraints
03/13/2012
109
134
D8_MLB
BLC Constraints
12/19/2011
110
135
D8_MARK
GPU VREG CONSTRAINTS
02/10/2012
111
136
D8_FIYIN
ETHERNET/SD CONSTRAINTS
07/02/2012
112
138
D8_MARK
AUTO-CONSTRAINTS 1
04/23/2012
113
139
D8_MARK
AUTO-CONSTRAINTS 2
04/23/2012
114
140
D8_MARK
AUTO-CONSTRAINTS 3
04/23/2012
115
141
D8_MARK
AUTO-CONSTRAINTS 4
04/23/2012
116
142
D8_MARK
AUTO-CONSTRAINTS 5
04/23/2012
117
143
D8_MARK
AUTO-CONSTRAINTS 6
04/23/2012
01/05/2012
2
2
D8_MLB
System Block Diagram
04/23/2012
3
3
D8_MARK
Power Block Diagram
12/19/2011
4
4
D8_MLB
BOM Configuration
06/22/2012
5
5
D8_TAVYS
DEBUG LEDS
06/20/2012
6
6
D8_DOUG
Power Connectors/Aliases
03/25/2012
7
7
D8_MLB
Holes/PD parts
04/02/2012
8
8
D8_MLB_ULTIMATE
Unused Signal Aliases
08/23/2011
9
9
K70_MLB
Signal Aliases
03/23/2012
10
10
D8_ROSITA
CPU DMI/PEG/FDI/RSVD
03/15/2012
11
11
D7_MLB
CPU CLOCK/MISC/JTAG
03/15/2012
12
12
D7_MLB
CPU DDR3 INTERFACES
03/15/2012
13
13
D7_MLB
CPU POWER
03/15/2012
14
14
D7_MLB
CPU GROUNDS
03/29/2012
15
15
D8_MLB
STRAPS,PULL UPS,PULL DOWNS FOR PCH AND CPU
12/20/2011
16
16
D7_MLB
CPU NON-GFX DECOUPLING
01/26/2012
17
17
D8_KOSECOFF
GFX DECOUPLING & PCH PWR ALIAS
N/A
18
18
D8_MLB
PCH SATA/PCIE/CLK/LPC/SPI
03/15/2012
19
19
D7_MLB
PCH DMI/FDI/GRAPHICS
03/15/2012
20
20
D7_MLB
PCH PCI/USB
N/A
21
21
D8_MLB
PCH MISC
N/A
22
22
D8_MLB
PCH POWER
03/15/2012
23
23
D7_MLB
PCH GROUNDS
N/A
24
24
D8_MLB
PCH DECOUPLING
01/26/2012
25
25
D7_MLB
CPU and PCH XDP
N/A
26
26
D8_MLB
CHIPSET SUPPORT
03/23/2012
27
27
D8_ROSITA
USB 2.0 HUB (BT/SMC)
04/23/2012
28
28
D8_MARK
CPU Memory S3 Support
03/19/2012
29
29
D8_KOSECOFF
DDR3 SO-DIMM Connector A Slot0
03/19/2012
30
30
D8_KOSECOFF
DDR3 SO-DIMM Connector A Slot1
03/19/2012
31
31
D8_KOSECOFF
DDR3 SO-DIMM CONNECTOR B SLOT0
03/19/2012
32
32
D8_KOSECOFF
DDR3 SO-DIMM CONNECTOR B SLOT1
03/19/2012
33
33
D8_KOSECOFF
DDR3 ALIASES AND BITSWAPS
03/19/2012
34
34
D8_KOSECOFF
DDR3/FRAMEBUF VREF MARGINING
07/02/2012
35
35
D8_FIYIN
AIRPORT/BT
N/A
36
36
D8_MLB
Thunderbolt Host (1 of 2)
03/15/2012
37
37
D7_MLB
Thunderbolt Host (2 of 2)
03/15/2012
38
38
D7_MLB
Thunderbolt Power Support
07/02/2012
39
39
D8_FIYIN
ETHERNET PHY (CAESAR IV+)
07/02/2012
40
40
D8_FIYIN
Ethernet Support & Connector
07/02/2012
41
41
D8_FIYIN
SD READER CONNECTOR
03/23/2012
42
42
D8_ROSITA
Camera Controller
03/15/2012
43
43
D7_MLB
Camera Controller Support
01/31/2012
45
44
D8_JERRY
SATA Connectors
03/23/2012
46
45
D8_ROSITA
EXTERNAL USB PORTS A & B
03/23/2012
47
46
D8_ROSITA
EXTERNAL USB PORTS C & D
03/22/2012
49
47
D8_MARK
SMC
07/19/2012
50
48
D8_DOUG
SMC Support
N/A
51
49
D8_MLB
SPI and Debug Connector
06/22/2012
52
50
D8_TAVYS
SMBus Connections
06/20/2012
53
51
D8_DOUG
I and V Sense 1
02/25/2012
54
52
D8_JERRY
HDD/SSD Temp Sense
06/07/2012
55
53
D8_DOUG
Temperature Sensors
07/19/2012
56
54
D8_DOUG
System Fan
04/23/2012
59
55
D8_MARK
I and V Sense 2
06/13/2012
61
56
D8_DAVID
AUDIO: CODEC/REGULATORS
06/13/2012
62
57
D8_DAVID
AUDIO: HEADPHONE AMP
06/13/2012
63
58
D8_DAVID
AUDIO: LEFT SPKR AMP
06/13/2012
64
59
D8_DAVID
AUDIO: RIGHT SPKR AMP
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
System Block diagram can be found on Kismet
PATH: Kismet > K70/72 > Block Diagrams > K70 Block Diagram
D8_MLB
01/05/2012
System Block Diagram
prefsb
051-9504
7.0.0
2 OF 143
2 OF 117
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
Regulator
U7600
PP3V42_G3H
IW0R
Fan
TBT IO
Speaker amps
GPU
LCD
PPVCCSA_S0
PP1V05_S0_CPU
PPVCORE_S0_CPU
PPVAXG_S0
PPFBVDDQ_S0_GPU
PPVCORE_S0_GPU
GPU (Core)
GPU (FB)
CPU (AXG)
CPU
CPU (Core)
CPU (VccIO)
PP1V05_TBTCIO
PP1V05_TBTLC
P1V05_S0_PCH
P1V05_S0
TBT Router
TBT Router
GPU (IOVDD, PLLVDD)
PCH (VCC, VccIO)
PP12V_S0_HDD
HDD (12V)
PH0R
PGTR
=
=
PH02+PH05
=
PCTR
SMC, RTC, MojoMux
PP12V_G3H
en
Regulator
VD2R
PR1R
IR1R
RegS0
Vin
UB700
en
S0
1V05
SD Card, DP Mux, DP X-bar
VD2R
PG0F
VD2R
IG0F
PC0S
Regulator
S0
FBVDDQ
GPU
3.3V
PCH, PwrCtl
Regulator
U7801
Reg
Vin
G3H G3H
3V42
VccIO
S0S0 Reg
Vin
en
Regulator
U7400
Bootrom, PCH, SMC, XDP,
Audio, LCD TCON, SnsCtl, VRD, PCH
PP5V_S0
VRegCtl, SnsCtl
Audio, PCH
PP5V_S0_HDD
HDD (5V)
PP5V_S4
CAM, USB Ports, VRegCtl
PH05
IH05
VH05
SSD
PP3V3_S0_SSD
PH1R
IW1R
V3V3
PP3V3_S0
VG0C
VC0C
USB Hub, SMC, TBT I/O
PP3V3_S4_ENET
PP3V3_S4
WIFI
PP3V3_S4_AP
PW0R
V3V3
SD Card, USB Mux, VRD, PwrCtl
PP3V3_TBTLC
TBT Router
Ethernet
IC0S
S4RegS4
en 5V
S0LDOS0
en
VTT
VTT
LDO S3
S3Reg
en
S3
Regulator
U7700
Vin
VDDQ
IM0R
VM0R
PM0R
PPDDRVTT_S0
DIMM (VTT)
DIMM VREF Margining CA
IC0M
VC0M
PC0M
PPDDRVTT_S3
PP1V5_S0
PPVDDQ_S3_DDR
PP1V5_S0_CPU_MEM
CPU (Mem)
Audio
DIMM (1V5)
Vin
PH02
IH02
VD2R
UB750
Regulator
Loads
IN1R
VN1R
PN1R
en
S0 Reg
GPU
S0
UB400
Vin
en
S0Reg
IG0C
PG0C
U7100
Vin
S0
Regulator
AXG
VC0G
IC0G
PC0G
S0Reg
Core
IC0C
PC0C
en
Reg
VccSA
S0
VD2R
VD2R
IC0I
PC0I
Regulator
U7500
Vin
PPHV_SW_TBTAPWR
PPHV_SW_TBTBPWR
TBT Port A
TBT Port B
PD2R
ID2R
Supply Module
PP5V_S0
en
Vin
S0
U7750
Regulator
Reg S0
1.8V
PP1V8_S0_REG
CPU PLL
en
PP12V_S5
S5Reg
Vin
PP5V_S5
PP12V_S0_BLC
S5 LDO5VS5
PP12V_ACDC
12V
G3H
AC/DC
Reg
ALS, CAM, BT
en
PP3V3_S5
S0
PP12V_S0
S0Reg
PC0I
+
PC0S
+
)
PC0MPC0G
+
PC0C
(
+
5.7 (GK104/GK107_BLENDED_CONSTANT)
+
PG0F
+
PG0C
1.176 *
1.176 *
High-side Component Total Power Keys
SYNC_DATE=04/23/2012
SYNC_MASTER=D8_MARK
Power Block Diagram
prefsb
051-9504
7.0.0
3 OF 143
3 OF 117
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_BOMGROUP_ITEM
BOM OPTIONS
BOM GROUP
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
TABLE_5_ITEM
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
TABLE_5_ITEM
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_ALT_ITEM
BOM OPTIONS
BOM NAME
BOM NUMBER
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_5_ITEM
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_ALT_ITEM
TABLE_5_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
BOM Groups
CPUs
Programmable Parts
ALTERNATE:335S0854
ASICs
ALTERNATE:335S0812
BOM Variants
CPU SOCKET ALTERNATES
D8 SCHEMATIC / PCB #’S
CPU SOCKET
D8 ALTERNATES
VRAM MODULE PARTS
Bar Code Labels / EEEE #’s
D8_COMMON,D8,CPU:4C_3P1GHZ,GPU:107EGE,FB:BOTH_SAMSUNG,EEEE:F49T
639-3952
PCBA,MLB,3.1G,4C,GK107,SAM,D8
D8_COMMON,D8,CPU:4C_2P9GHZ,GPU:107EGE,FB:BOTH_HYNIX,EEEE:F653
639-4092
PCBA,MLB,2.9G,4C,GK107,HYN.D8
639-4093
D8_COMMON,D8,CPU:4C_3P1GHZ,GPU:107EGE,FB:BOTH_HYNIX,EEEE:F654
PCBA,MLB,3.1G,4C,GK107,HYN.D8
PCBA,MLB,DEV,D8
085-4433
DEVELOPMENT,D8_DEVEL
IC, GPU, NV GK107-GE-PS-A2
337S4280
U8000
CRITICAL
GPU:107EGE
1
825-7896
LABEL,MLB,2D
EEEE_DHNM
CRITICAL
1
EEEE:DHNM
CRITICAL
FB:BOTH_SAMSUNG
333S0619
IC,SGRAM,GDDR5,32MX32,1.5GHz,G-DIE,HF
U8400,U8450,U8500,U8550
4
333S0620
4
IC,GDDR5,32MX32,1.5GHZ,VEGA 44NM,B-DIE
FB:BOTH_HYNIX
U8400,U8450,U8500,U8550
CRITICAL
377S0147
ALL
USB diodes
377S0126
U3990
CRITICAL
CIVROM:PROG
1
341S3645
IC,ENET 1MBIT, SPI,ROM, V1.13 D8
CAMROM:BLANK
CRITICAL
1
U4202
335S0852
IC,FLASH,SPI,1MBIT,3V3
338S1098
U4900
SMC:BLANK
IC,SMC,LX4FS1AH5BBCIGA3
1
CRITICAL
SMC:PROGCRITICAL
1
U4900
341S3394
IC,PROGRMD,SMC,A3,V2.2A32,D8
CRITICAL
U4202
CAMROM:PROG
1
341S3675
IC,CAMERA FLASH,V7228,D7/D8
511S0071
ALL
511S0073
TYCO SOCKET
511S0073
ALL
511S0072
FOXCONN SOCKET
U1000
511S0073 CRITICAL
1
SOCKET,MOLEX,LGA1155,CPU-LF
D8_COMMON,D8,CPU:4C_2P9GHZ,GPU:107EGE,FB:BOTH_SAMSUNG,EEEE:F2FR
639-3816
PCBA,MLB,2.9G,4C,GK107,SAM,D8
157S0084
Enet Magnetics
ALL
157S0058
IC,BCM57766A1,ENET&SD,8X8
343S0616
1
U3900
CRITICAL
IC,TBT,CR-4C,B1,PRQ,288 FCBGA,12X12MM
338S1113
U3600
CRITICAL
1
IC,PANTHER POINT,C1,SLJC7,PRQ,BD82Z77
337S4277
U1800
CRITICAL
1
1
337S3978
CRITICAL
BLCMCU:BLANK
U9700
IC,BLC MCU LPC2132FBD64/01, LQFP64
TBTROM:PROG
CRITICAL
1
U3690
341S3672
IC,EEPROM,CR,V14.1 (B1),D8
1
CRITICAL
U3690
TBTROM:BLANK
IC,EEPROM,SERIAL,8KB,MLP8
335S0865
U9700
BLCMCU:PROG
CRITICAL
341S3674
IC,BLC,MCU, PRPOGRAMMED, V0204, D8
1
1
U3990
CRITICAL
CIVROM:BLANK
335S0862
IC,SERIAL FLASH,2MBIT, 2.7V, REF F
335S0807
1
BOOTROM:BLANK
CRITICAL
U5110
IC,64 MBIT SPI SERIAL FLASH
CRITICAL
BOOTROM:PROG
1
U5110
IC,PROGRMD,EFI ROM,V00FC,D7/D8
341S3673
376S0975
ALL
376S1081
P/NCH DUAL FET
PCBF,MLB,D8
CRITICALPCB1
1
D8820-3298
1
CRITICALSCH1 D8SCH,MLB,D8051-9504
341S3644
U3990
CIVROM
341S3645
150UF CAPS BLK
128S0368128S0365
ALL
102S0880
0.010 OHM,1%,1206
102S0879
ALL
ALL
138S0804
2.2UF CAPS SOFT
138S0803
825-7896
LABEL,MLB,2D
EEEE_F2FR
1
CRITICAL
EEEE:F2FR
LABEL,MLB,2D
CRITICAL
1
EEEE:F49VEEEE_F49V
825-7896
337S4372 CRITICAL
1
CPU
IVB,SR0T9,PRQ,N0,3.1,65W,4+1,1.1,6M,LGA
CPU:4C_3P1GHZ
BOM Configuration
SYNC_MASTER=D8_MLB
SYNC_DATE=12/19/2011
1
LABEL,MLB,2D
CRITICAL
EEEE:F653EEEE_F653
825-7896
337S4355
CPU
1
CRITICAL
IVB,SR0TA,PRQ,N1,2.9,65W,4+1,1.1,6M,LGA
CPU:4C_2P9GHZ
D8_DEVEL
XDP_CONN,LPCPLUS,VREFMRGN:EXT,DEVEL_AUDIO,TEMPSNSDEV
SMC:PROG,BOOTROM:PROG,TBTROM:PROG,CIVROM:PROG,CAMROM:PROG,BLCMCU:PROG
D8_PROGPARTS
XDP,RSMRST:GATE,SPEAKERID,VREF:CPU,TBTHV:P12V,FBA,FBB
D8_COMMON1
D8_PRODUCTION
VREFMRGN:N,PRODUCTION
D8_COMMON
COMMON,ALTERNATE,D8_COMMON1,D8_PROGPARTS,D8_PRODUCTION
825-7896
EEEE:F654EEEE_F654
CRITICAL
LABEL,MLB,2D
1
825-7896
LABEL,MLB,2D
EEEE_F49T
CRITICAL
1
EEEE:F49T
prefsb
051-9504
7.0.0
4 OF 143
4 OF 117
IN
G
D
S
IN
G
D
S
IN
G
D
S
IN
G
D
S
G
D
S
IN
IN
G
D
S
IN
G
D
S
IN
G
D
S
IN
G
D
S
IN
G
D
S
IN
G
D
S
IN
G
D
S
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
MEM 1V5_S3 LED
LED GND ISOLATION SWITCH
ALL_SYS_PWRGD LED
S5 LED
CPU 1V05_S0 LED
S4 (SLEEP) LED
GPU FBVDD LED
CPU VCORE LED
BLC_EN LED
CPU AXG LED
PCH/GPU 1V05 LED
GPU_GOOD LED VIDEO_ON LED
GPU VCORE LED
SLP_S3 LED
APN: 705S0137
64 69
115
5%
1/16W
1K
402
R507
DEVELOPMENT
MF-LF
2.0X1.25MM-SM
GREEN-3.6MCD
LED507
DEVELOPMENT
SOT-363
Q507
2N7002DW-X-G
DEVELOPMENT
64 95
115
402
MF-LF
5%
1/16W
1K
R502
DEVELOPMENT
2.0X1.25MM-SM
GREEN-3.6MCD
LED502
DEVELOPMENT
1/16W
MF-LF
5%
402
1K
R512
LED512
GREEN-3.6MCD
SILK_PART=3
2.0X1.25MM-SM
PLACE_SIDE=BOTTOM
2N7002DW-X-G
SOT-363
Q511
1/16W
1K
5%
402
R511
MF-LF
SILK_PART=2
LED511
PLACE_SIDE=BOTTOM
GREEN-3.6MCD
2.0X1.25MM-SM
21 99
Q511
SOT-363
2N7002DW-X-G
47 65
112
MF-LF
402
1K
5%
1/16W
R501
2.0X1.25MM-SM
SILK_PART=1
LED501
PLACE_SIDE=BOTTOM
GREEN-3.6MCD
5%
1/16W
R513
1K
MF-LF
402
GREEN-3.6MCD
2.0X1.25MM-SM
LED513
SILK_PART=4
PLACE_SIDE=BOTTOM
SOT-363
2N7002DW-X-G
Q513
1/16W
MF-LF
5%
1K
402
R514
DEVELOPMENT
2.0X1.25MM-SM
GREEN-3.6MCD
LED514
DEVELOPMENT
SOT-363
2N7002DW-X-G
Q513
DEVELOPMENT
89
87
107
SM
SW500
KMT221GLHS
DEVELOPMENT
1/16W
1K
5%
R505
402
MF-LF
DEVELOPMENT
GREEN-3.6MCD
2.0X1.25MM-SM
LED505
DEVELOPMENT
SOT-363
Q505
2N7002DW-X-G
DEVELOPMENT
64 92
110
402
MF-LF
1/16W
5%
R506
1K
DEVELOPMENT
GREEN-3.6MCD
2.0X1.25MM-SM
LED506
DEVELOPMENT
Q505
SOT-363
2N7002DW-X-G
DEVELOPMENT
64 95
115
402
5%
1K
1/16W
MF-LF
R503
DEVELOPMENT
LED503
2.0X1.25MM-SM
GREEN-3.6MCD
DEVELOPMENT
SOT-363
Q503
2N7002DW-X-G
DEVELOPMENT
64 72
115
1/16W
MF-LF
5%
1K
402
R504
DEVELOPMENT
GREEN-3.6MCD
LED504
DEVELOPMENT
2.0X1.25MM-SM
2N7002DW-X-G
Q503
SOT-363
DEVELOPMENT
15 19 28 40 47 48 64
115
5%
1K
MF-LF
1/16W
402
R510
DEVELOPMENT
2.0X1.25MM-SM
GREEN-3.6MCD
LED510
DEVELOPMENT
GREEN-3.6MCD
LED509
2.0X1.25MM-SM
DEVELOPMENT
402
1K
5%
1/16W
MF-LF
R509
DEVELOPMENT
SOT-363
2N7002DW-X-G
Q509
DEVELOPMENT
25 65 66
115
Q509
SOT-363
2N7002DW-X-G
DEVELOPMENT
1/16W
MF-LF
5%
1K
402
R508
DEVELOPMENT
GREEN-3.6MCD
LED508
DEVELOPMENT
2.0X1.25MM-SM
66
116
2N7002DW-X-G
Q507
DEVELOPMENT
SOT-363
SYNC_MASTER=D8_TAVYS
DEBUG LEDS
SYNC_DATE=06/22/2012
ALL_SYS_PWRGD
PM_LED_A_PGOOD_REG_GPUCORE_S0
=PP3V3_S5_LED
GPU_GOOD
PM_LED_K_ALL_SYS_PWRGD
PM_LED_K_GPU_GOOD
=PP3V3_S4_LED =PP3V3_S0_LED =PP3V3_S0_LED
PM_LED_A_VIDEO_ON
VIDEO_ON_L
NO_TEST=TRUE
NC_Q513_1
NO_TEST=TRUE
NC_Q513_6
NC_Q513_2
NO_TEST=TRUE
PM_PGOOD_REG_P1V05_S0
=PP3V3_S0_LED
PM_PGOOD_REG_VDDQ_S3
=PP3V3_S5_LED
PM_LED_A_PGOOD_REG_VDDQ_S3
PM_LED_K_PGOOD_REG_VDDQ_S3
LED_GND
PM_LED_K_PGOOD_REG_P1V05
LED_GND
PM_LED_A_PGOOD_REG_P1V05
PM_PGOOD_REG_CPU_P1V05_S0
LED_GND
PM_SLP_S3_L
=PP3V3_S0_LED
PM_LED_K_PGOOD_CPU_P1V05_S0
LED_GND
PM_LED_K_SLP_S3
PM_LED_A_SLP_S3
REG_CPUAXG_PGOOD
LED_GND
PM_PGOOD_REG_GPUCORE_S0
PM_LED_A_CPUAXG_PGOOD
PM_LED_K_CPUAXG_PGOOD
=PP3V3_S0_LED
LED_GND
PM_LED_K_PGOOD_REG_GPUCORE_S0
=PP3V3_S5_LED
PM_PGOOD_REG_CPUCORE_S0
PM_PGOOD_REG_FBVDDQ_S0
BLC_GOOD
LED_GND
=PP3V3_S0_LED
LED_GND
PM_LED_K_BLC_GOOD
PM_LED_A_BLC_GOOD
PM_LED_K_PGOOD_CPUCORE_S0
PM_LED_A_PGOOD_CPUCORE_S0
=PP3V3_S0_LED
LED_GND
PM_LED_K_PGOOD_REG_FBVDDQ_S0
=PP3V3_S5_LED
PM_LED_A_PGOOD_REG_FBVDDQ_S0
LED_GND
=PP3V3_S4_LED
PM_LED_A_S4
PM_LED_A_PGOOD_CPU_P1V05_S0
PM_LED_A_GPU_GOOD
PM_LED_A_ALL_SYS_PWRGD
PM_LED_A_S5
=PP3V3_S5_LED
MIN_NECK_WIDTH=0.2 MM
LED_GND
MIN_LINE_WIDTH=0.3 MM
prefsb
051-9504
7.0.0
5 OF 143
5 OF 117
1
2
K
A
6
2
1
1
2
K
A
1
2
K
A
3
5
4
1
2
K
A
6
2
1
1
2
K
A
1
2
K
A
6
2
1
1
2
K
A
3
5
4
13
24
5
1
2
K
A
6
2
1
1
2
K
A
3
5
4
1
2
K
A
6
2
1
1
2
K
A
3
5
4
1
2
K
A
K
A
1
2
3
5
4
6
2
1
1
2
K
A
3
5
4
5 6
115
5 6 5 6 5 6
115
5 6
5 6
5
5 5
5 6
5
115
115
5
115
115
5 6
5
5 6
5
5 6
5
115
115
5 6
5
5 6
5
5 6
115
115 115
115
5 6
5
OUT
OUT
OUT
IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
FILTER ADDED TO BURSTMODE_EN_L TO PASS SURGE RDAR://11059712
MLB to AC-DC Supplemental Signal Connector
MLB to AC-DC Connector
S5 Rails
On when in S5
G3 Rails
518-0389
518S0863
Always on: Keeps the PCH RTC alive
THIS IS 1.5V RAIL
THIS IS 1.5V RAIL
THIS IS 1.5V RAIL
S3 Rails
Enabled when system is in run or sleep
GPU Rails (S0)
Enabled when system is in run
Ground/Common
S0 Rails
Enabled when system is in run
Enabled when Thunderbolt cable is plugged in
Thunderbolt Rails (S0)
G3H Rails
On with AC/DC plugged in
Enabled when system has AC and is in run or sleep
S4 Rails
J600.5:10MM
EMC
25V
5%
402
NP0-C0G
1000PF
C603
J600.5:10MM
EMC
402
25V
5%
C602
1000PF
NP0-C0G
C601
10%
805
X5R
25V
10UF
J600.4:10MM
53
117
J601
504050-0791
M-RT-SM
SILK_PART=PWRSIG
PLACE_NEAR=J601.3:30MM
R603
402
1/16W
MF-LF
10K
5%
53
117
5%
R606
PLACE_NEAR=J601.1:3MM
1/16W
402
MF-LF
1K
6.8V-100PF
402
D600
PLACE_NEAR=J601.1:3MM
48
116
MF-LF
PLACE_NEAR=J601.3:3MM
1K
402
R604
1/16W
5%
PLACE_NEAR=R604.2:3MM
C604
20%
X7R-CERM
0402
0.01UF
16V
PLACE_NEAR=J601.1:4MM
402
6.8V-100PF
D601
48 71
112
PLACE_NEAR=J601.7:3MM
R600
5%
402
1/16W
1K
MF-LF
PLACE_NEAR=J601.7:3MM
D602
6.8V-100PF
402
43045-1201
CRITICAL
M-RT-TH-1
J600
PLACE_NEAR=R606.1:3MM
X7R-CERM
16V
10%
C600
0.1UF
0402
PLACE_NEAR=R600.1:3MM
16V
0402
X7R-CERM
0.1UF
10%
C605
SYNC_MASTER=D8_DOUG
Power Connectors/Aliases
SYNC_DATE=06/20/2012
PP1V8_S0
MAKE_BASE=TRUE
=PP1V8_S0_PCH_VCC_VRM
=PP1V8_S0_PCH_CLK
PP1V8_S0_REG
=PP1V8_S0_CPU_PLL
=PP1V8_S0_PCH
=PP1V8_S0_PCH_VCC_DFTERM
=PP1V5_S0_DP
PP1V5_S0_CPU_MEM_SNS
=PP1V5_S0_CPU_MEM
=PP12V_S0_FAN
=PP12V_S0_HDD_PWR
=PP12V_S0_REG_CPU_P1V05_PWR
SMC_ACDC_ID
PP12V_S0
MAKE_BASE=TRUE
=PP12V_S0_PWRCTL
=PP12V_S0_REG_P1V05_PWR
=PP12V_S0_REG_CPU_VCCSA_PWR
=PP5V_S0_VRD
MAKE_BASE=TRUE
PP5V_S0
=PP12V_S0_REG_CPUCORE
=PP12V_S0_LCD
=PP12V_S0_REG_GPUCORE
=PP12V_S0_FBVDDQ_PWR
PP12V_S0_FET
=PP12V_S0_AUDIO_SPKRAMP
PP5V_S4_REG
=PP5V_S4_REG_VDDQ_S3
=PP3V3_S0_VRD
TSNS_ACDC_N
TSNS_ACDC_P
PWR_BTN_R
MAKE_BASE=TRUE
PP3V3_G3
MAKE_BASE=TRUE
PP12V_G3H
MAKE_BASE=TRUE
PP3V42_G3H
SMC_ACDC_ID_R
SMC_ACDC_ID_R
=PP3V3_G3H_LPCPLUS
=PPVIN_G3H_SMCVREF
PP3V42_G3H_REG
=PP3V3_G3H_BT
=PP12V_G3H_FET_P12V_S5
=PP3V3_G3_PCH
PP12V_ACDC
MAKE_BASE=TRUE
=PP3V3_S0_PCH_GPIO
=PP3V3_S0_PCH_VCC_GPIO
=PP3V3_S0_PCH_VCC_ADAC
=PP3V3_S0_PCH_STRAPS
PP12V_S5_FET
=PP3V3_TBT_CLK
PPVCCSA_S0_REG
PPCPUAXG_S0_REG
PPCPUCORE_S0_REG
=PP3V3_S0_SMBUS_TCON
PP3V3_S0_SSD_SNS
=PP3V3_S0_TBTPWRCTL
=PP3V3_S0_SMC
=PP3V3_S0_SMBUS_SMC
=PP5V_S0_HDD_PWR
=PP3V3_S0_DP
=PP3V3_S0_ENET
=PP3V3_S0_FAN
=PP3V3_S0_GPU
=PP3V3_S0_INTDPMUX
=PP3V3_S0_LED
=PP3V3_S0_MEM_A_SPD
=PP3V3_S0_PCH
=PP3V3_S0_PCH_VCC
PP5V_S0_HDD_SNS
=PP5V_S0_HDD
=PP3V3_S0_GPU_IFPX_PLLVDD
PP3V3_S0_FET
=PP1V05_S0_GPU_IFPEF_IOVDD
=PP1V05_S0_GPU_PEX_PLLVDD
=PP1V05_S0_GPU_PEX_IOVDD
=PP1V05_S0_GPU_IFPCD_IOVDD
=PP1V05_S0_PCH_PWR
=PP1V05_S0_P1V05TBTFET
PP1V05_S0_REG
=PPVCCIO_S0_CPU
=PPVCCIO_S0_SMC
=PPVCCIO_S0_XDP
PP1V05_S0_CPU_REG
=PPVAXG_S0_CPU
=PPVCORE_S0_CPU
=PPVCCSA_S0_CPU
PPDDRVREF_DQ_MEM_B
=PPDDRVREF_DQ_MEM_B
PPDDRVREF_CA_MEM_B
=PP3V3_TBTLC_RTR
PP12V_S0_REG_CPU_P1V05_SNS
=PP1V05_S0_PCH_VCCIO_DMI
=PPDDRVREF_CA_MEM_B
PP5V_S0_FET
=PP12V_S0_REG_P1V05
=PP12V_S0_REG_VCCSA
=PPDDRVTT_S0_MEM_A
=PPDDRVTT_S0_MEM_B
=PP1V5_S0_CPU_MEM_PWR
=PPVCORE_S0_GPU
=PP1V05_S0_PCH_VCCIO_USB
PPDDRVREF_DQ_MEM_A
=PP3V3_S0_MEM_B_SPD
=PP3V3_S0_AUDIO
=PP3V3_S0_AUDIO_DIG
PP12V_S0_REG_CPU_VCCSA_SNS
=PP5V_S0_REG_P1V05
PP12V_S0_REG_P1V05_SNS
=PPDDRVREF_CA_MEM_A
PP1V05_S0_PCH_SNS
=PP1V05_S0_PCH
=PPDDRVREF_DQ_MEM_A
=PP1V05_S0_PCH_VCC_DMI
=PP1V05_S0_PCH_VCC_DIFFCLK
=PP1V05_S0_PCH_VCC_ADPLL
=PP1V05_S0_PCH_VCCIO_SATA
=PP1V05_S0_PCH_VCCIO_PCIE
=PP1V05_S0_PCH_VCCCLKDMI
=PP1V05_S0_PCH_VCC_SSC
=PP1V05_S0_PCH_V_PROC_IO
=PP1V35_S0_GPU_FBVDDQ
PPGPUCORE_S0_REG
=PP3V3_S0_PCH_PM
=PP3V3_S0_P3V3TBTFET
PP1V5R1V35_S0_GPU_REG
=PP5V_S0_REG_FBVDDQ
=PP1V05_S0_PCH_VCC_CORE
=PP1V05_S0_PCH_VCC_ASW
PP1V5_S0_FET
=PP1V5_S0_AUD_DIG
=PP3V3_S0_GPU_MISC
=PP3V3_S0_GPU_VDD33
PP12V_S0_FBVDDQ_SNS
=PP3V3_S0_PCH_VCC_PCI
=PP3V3_S0_SDCARD
=PP3V3_S0_RSTBUF
=PP3V3_S0_SSD_PWR
=PPDDRVTT_S0_CLAMP
=PP12V_S0_REG_FBVDDQ
=PP12V_S0_BLC
=PP12V_S0_HDD
PP12V_S0_BLC_FET
PPDDRVTT_S0_LDO
PP12V_S0_HDD_SNS
=PP12V_S0_REG_CPU_P1V05
=PP3V3_S0_PWRCTL
=PP3V3_S0_PCH_VCC_HVCMOS
=PP3V3_S0_LED_SATA
PP5V_S0_HDD
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PPDDRVTT_S0
PPDDRVREF_DQ_MEM_A_S3
MAKE_BASE=TRUE
PP1V5_S0
MAKE_BASE=TRUE
PPVCORE_S0_GPU
MAKE_BASE=TRUE
PP12V_S0_FBVDDQ
MAKE_BASE=TRUE
PP1V05_TBTLC
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PPFBVDDQ_S0_GPU
MAKE_BASE=TRUE
PP12V_S0_CPU_P1V05
PP12V_S0_VCCSA
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PPDDRVREF_CA_MEM_A_S3
MAKE_BASE=TRUE
PP3V3_S0_SSD
MAKE_BASE=TRUE
PP12V_S0_BLC
MAKE_BASE=TRUE
PP12V_S0_HDD
PPDDRVREF_CA_MEM_B_S3
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PPVAXG_S0
MAKE_BASE=TRUE
PPVCCSA_S0
PPVCORE_S0_CPU
MAKE_BASE=TRUE
PP1V05_S0_CPU
MAKE_BASE=TRUE
PP1V05_S0_PCH
MAKE_BASE=TRUE
PPDDRVREF_DQ_MEM_B_S3
MAKE_BASE=TRUE
PP1V05_S0
MAKE_BASE=TRUE
PP1V5_S0_CPU_MEM
MAKE_BASE=TRUE
PP12V_S0_P1V05
MAKE_BASE=TRUE
PP3V3_TBTLC
MAKE_BASE=TRUE
=PP3V3_TBT_PCH_GPIO
=PP3V3_S0_SENSE
=PP3V3_S0_SMBUS
=PP3V3_TBTLC_FET
=PP1V05_TBTCIO_RTR
=PP1V05_TBTLC_RTR
=PP1V05_TBTLC_FET
=PP3V3_S0_BLC
=PP1V05_TBTCIO_FET
PP1V05_TBTCIO
MAKE_BASE=TRUE
PPVDDQ_S3
MAKE_BASE=TRUE
PPVDDQ_S3_DDR
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PPDDRVTT_S3
=PP5V_S4_MEMRESET
PP3V3_S4_FET
=PP3V3_S4_ALS
=PP3V3_S4_AP_PWR
=PP3V3_S4_ENET
=PP3V3_S4_LED
=PP3V3_S4_MEMRESET
=PP3V3_S4_PWRCTL
=PP3V3_S4_PM
=PP3V3_S4_SENSE
=PP3V3_S4_SMBUS_SMC
=PP3V3_S4_SMC
=PP3V3_S4_TBT
PP3V3_S4_AP_SNS
=PP3V3_S4_AP
PP3V3_S4_ENET_FET
=PP3V3_S4_ENET_SYSCLK
=PP3V3_S4_ENET_FET
=PP3V3_S4_ENET_CLK
PPVDDQ_S3_REG
=PPVDDQ_S3_FET_VDDQ_S0
=PPVDDQ_S3_DDR_PWR
=PPVDDQ_S3_LDO_DDRVTT
PPVDDQ_S3_DDR_SNS
=PPVDDQ_S3_DDR_VREF
=PPVDDQ_S3_MEM_A
=PPVDDQ_S3_MEM_B
=PPVDDQ_S3_MEMRESET
PPDDRVTT_S3_LDO
=PPDDRVTT_S3_VREFCA
PP3V3_G3_RTC
=PP3V3_G3_PCH_RTC
=PP12V_G3H_PWR
PP12V_G3H_SNS
=PP12V_G3H_P3V42
=PP12V_S5_REG_P3V3P5V_S5
=PP12V_S5_REG_VDDQ_S3
=PP5V_S0_REG_CPU_P1V05
=PP5V_S0_REG_CPUCORE
=PP5V_S0_LPCPLUS
=PP5V_S0_ISENSE
=PP5V_S0_PCH
=PP5V_S0_REG_P1V8
=PP5V_S0_REG_VCCSA
=PP5V_S0_AUDIO
=PP5V_S0_BLC
BURSTMODE_EN_R_L
PPDDRVREF_CA_MEM_A
=PP3V3_S0_SSD
=PP3V3_S0_VRD
PP3V3_S0
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PP5V_S4
PP12V_G3H_ACDC
MAKE_BASE=TRUE
PP3V3_S4_ENET
=PP3V3_S4_CAMERA
=PP5V_S4_USB
=PP5V_S4_FET_P5V_S0
=PP5V_S4_CAMERA
PP3V3_S4_AP
MAKE_BASE=TRUE
PP12V_G3H_ACDC
=PP12V_S5_PWRCTL
=PPHV_SW_TBTAPWRSW
MAKE_BASE=TRUE
PP3V3_S5
=PP5V_S5_PWRCTL
PP5V_S5_LDO
=PP5V_S5_PCH
PP3V3_S5_REG
=PP3V3_S5_FET_P3V3_S0
=PP3V3_S5_FET_P3V3_S4
=PP3V3_S5_SMC
=PP3V3_S5_LED
=PP3V3_S5_PCH_STRAPS
=PP3V3_S5_PCH
=PP3V3_S5_PCH_VCCSUS_HDA
=PP3V3_S5_PCH_VCC_DSW
=PP3V3_S5_PCH_VCCSUS_USB
=PP3V3_S5_PWRCTL
=PP3V3_S5_ROM
=PP3V3_S5_PCH_VCC_SPI
=PP3V3_S5_VRD
=PP3V3_S5_XDP
=PP3V3_S5_SMC_USBMUX
=PP3V3_S5_SDCARD
=PP3V3_S5_SENSE
=PPHV_SW_TBTBPWRSW
=PP12V_S5_SNS
PP12V_S5
MAKE_BASE=TRUE
=PP3V3_G3H_SMC_USBMUX
=PP3V3_G3H_SMC
MAKE_BASE=TRUE
PP5V_S5
=PP3V3_G3H_RTC_D
=PP12V_G3H_FET_P12V_S0
PP12V_G3H_ACDC
PWR_BTN
BURSTMODE_EN_L
=PP3V3_S4_SMBUS
=PP3V3_S4_USB_HUB
=PP3V3_S4_TBTAPWRSW
=PP3V3_S4_TBTBPWRSW
=PP3V3_S4_VREFMRGN
=PP3V3_S4_AUDIO_DIG
MAKE_BASE=TRUE
PP3V3_S4
GND
MAKE_BASE=TRUE
prefsb
051-9504
7.0.0
6 OF 143
6 OF 117
2
1
2
1
2
1
8
9
4
2
3
5
6
7
1
1
2
12
1
2
12
2
1
1
2
12
1
2
1
2
3
4
5
6
12
7
8
10
11
9
2
1
2
1
106
24
26
72
13 16
19
22 24
84
51
11 13 16
54
51
55
48
116
106
65
55
55
72 92
106
67
87
92
51
74
58 59
71
72
6
66 69 70 72 92 95
116
106
106
106
6
116
6
116
49
48
73
35
74
18 19
106
15 19 20 38
22 24
17
15
74
26
70
17 68
67 68
50
51
38
48 51 82
50
51
85 87
39
54
78 92
84
5
29 30
18 21 24
22 24
51
52
78
74
78
78
78
78
51
38
95
10 11 13 16 28 66
48
25
69
13 17 51 66
13 16 51 66
13 16
34
31 32
34
15 36 37 38 50
55
22 24
31 32
74
95
70
29 30
31 32
51
51 78
22 24
34
31 32
42 56 58 59 62
60
55
95
55
29 30
51
18 29 30
22 24
22 24
17
18 22 24
18 19 22 24
22 24
22 24
22 24
78
93 94
26
38
95
110
95
22 24
22 24
74
56
78
78
51
22 24
41
26
51
28
95
91
52
74
72
51
69
28 74
22 24
15 44
106
106
106
106
110
106
38
104
106
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106
106
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106
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104
105
104
104
106
104
106
106
106
15
51 52 53 55
50
38
37
37
38
89
38
104
106
106
106
28
74
42
55
40
5
28
65 72 74
28
51
50
48
36 37 38 86 88
55
15 35
40
26
39 40
26
72
74
51
72
51
34
29 30
31 32
28
72
34
26
115
22
51
51
73
71
72
69
66
49
51
24
72
70
56 63
91
34
44
6
66 69 70 72 92 95
106
106
6
106
42 43
45 46
74
42
106
6
64 65 74
86
106
71
71
24
71
74
74
48
5
15
19 24 26
22 24
22 24
22 24
64 65
49
22 24
71
25
45 46
41
51
88
51
106
45
47 48 50
106
26
74
6
50
27
48 86
48 88
34
60
106
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
GPU HEATSINK MOUNTING FEATURES
(998-5013. PLATED HOLE, 3.2MM DIA, 6MM PAD TOP/BOT)
998-4640 (PLATED HOLES, 10MM DIA, 12MM PAD)
HEATPIPE MTG HOLES
WIRELESS CARD MTG HOLES
998-4938 (PLATED HOLES, 1.9MM INNER DIAMETER, 4.3MM PAD)
APN: 860-1461
860-1487 (PCB STANDOFF)
SSD STANDOFF
Rear Cover
Rear Cover
998-5014 (PLATED HOLES, 4MM DRILL, 8.5MM TOP, 8MM BOT)
4MM PLATED HOLES (998-4158)
CPU Heatsink
ZH0700
8P5R5-NSP
OMIT
8P5R5-NSP
OMIT
ZH0701 ZH0702
8P5R5-NSP
OMIT
8P5R5-NSP
OMIT
ZH0703
STDOFF-4.5OD2.2ID-5.6H-SM
NUT0713
CRITICAL
ZH0715
STDOFF-7.14OD16.45H-TH-1.5-5.2
CRITICAL
STDOFF-7.14OD16.45H-TH-1.5-5.2
CRITICAL
ZH0718
ZH0722
CRITICAL
5P5R1P9-4P3B-NSP
CRITICAL
5P5R1P9-4P3B-NSP
ZH0721
10R12
ZH0726
6P0R3P2-NSP
CRITICAL
ZH0725
CRITICAL
6P0R3P2-NSP
ZH0724
6P0R3P2-NSP
CRITICAL
ZH0723
ZH0717
8P5R4P0-8P0B-NSP
CRITICAL
ZH0716
8P5R4P0-8P0B-NSP
CRITICAL
CRITICAL
8P5R4P0-8P0B-NSP
ZH0714
CRITICAL
8P5R4P0-8P0B-NSP
ZH0713
CRITICAL
ZH0720
6P0R3P2-NSP
SYNC_MASTER=D8_MLB
Holes/PD parts
SYNC_DATE=03/25/2012
prefsb
051-9504
7.0.0
7 OF 143
7 OF 117
1111
1
1
1
11
1
11
1
11
1
1
1
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
PCH Clocks
PCH PCIe
PCH USB
CPU Memory
PCH PCI
PCH Unused Display
PCH Test Points
PCH SATA
PCH and CPU FDI
PCH Miscellaneous
CPU Reserved
PCH Reserved
SYNC_DATE=04/02/2012
Unused Signal Aliases
SYNC_MASTER=D8_MLB_ULTIMATE
TP_MEM_A_DQS_P<8>
TP_MEM_A_DQ_CB<7..0>
NC_DMI_MIDBUS_CLK100NX
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCIE2_R2D_CNX
MAKE_BASE=TRUE
NO_TEST=TRUE
TP_PCIE2_R2D_CN
TP_PCIE2_R2D_CP
TP_PCI_CLK33M_OUT2
TP_PCI_CLK33M_OUT3
TP_PCH_PWM3
TP_PCH_SST
TP_PCH_RESERVE_0
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_DP_IG_C_AUXNX
DP_IG_C_MLP<3..0>
NC_PCIE_CLK100M_PE5NX
NO_TEST=TRUE
MAKE_BASE=TRUE
TP_PCIE_CLK100M_PE5N
TP_PCIE_CLK100M_PE6P
DMI_MIDBUS_CLK100M_N
NC_DMI_MIDBUS_CLK100PX
MAKE_BASE=TRUE
NO_TEST=TRUE
DMI_MIDBUS_CLK100M_P
TP_PCIE_CLK100M_PE0N
TP_PCIE2_D2RP
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PE_TNX<3..0>
DP_IG_D_CTRL_DATA
DP_IG_D_HPD
TP_PCIE1_D2RN
TP_PCIE1_R2D_CN
TP_MEM_B_DQ_CB<7..0>
CPU_CFG<15..12>
TP_CPU_RSVD<46..19>
TP_CPU_RSVD<16..1>
TP_SATA_D_R2D_CN
TP_SATA_D_R2D_CP
TP_SATA_D_D2RN
TP_SATA_E_D2RN
TP_SATA_F_R2D_CN
TP_MEM_A_DQS_N<8>
TP_PCH_PWM0
TP_HDA_SDIN2
PCH_FDI_FSYNC<1..0>
PCH_FDI_LSYNC<1..0>
PCH_FDI_INT
PCH_FDI_RX_N<7..0>
PCH_FDI_RX_P<7..0>
TP_CPU_FDI_TX_N<7..0>
TP_CPU_FDI_TX_P<7..0>
TP_SDVO_STALLP
TP_SDVO_INTN
TP_CPU_FDI_FSYNC<1..0>
TP_CPU_FDI_LSYNC<1..0>
TP_CPU_FDI_INT
TP_PCH_CL_DATA1
TP_PCH_CL_CLK1
TP_HDA_SDIN3
TP_PCH_RESERVE_8
TP_PCH_L_VDD_EN
TP_PCH_L_BKLTEN
TP_PCH_RESERVE_27
TP_PCH_RESERVE_25
DP_IG_C_MLN<3..0>
DP_IG_B_DDC_DATA
DP_IG_C_AUX_N
TP_SDVO_INTP
TP_PCH_CL_RST1
TP_PCH_PWM2
TP_PCH_PWM1
TP_PCH_RESERVE_20
TP_PCH_RESERVE_23
TP_PCH_RESERVE_7
TP_PCH_RESERVE_19
TP_PCH_RESERVE_21
TP_PCH_RESERVE_28
TP_PCH_RESERVE_24
TP_PCH_RESERVE_17
TP_PCH_RESERVE_18
TP_PCH_RESERVE_15
TP_PCH_RESERVE_16
TP_PCH_RESERVE_14
TP_PCH_RESERVE_13
TP_PCH_RESERVE_12
TP_PCH_RESERVE_10
TP_PCH_RESERVE_11
TP_PCH_RESERVE_9
TP_PCH_RESERVE_5
TP_PCH_RESERVE_6
TP_PCH_RESERVE_3
TP_PCH_RESERVE_4
TP_SDVO_TVCLKINP
DP_IG_C_AUX_P
DP_IG_C_CTRL_CLK
TP_PCH_L_BKLTCTL
TP_SDVO_STALLN
DP_IG_D_MLP<3..0>
TP_SDVO_TVCLKINN
DP_IG_D_AUXN
DP_IG_D_AUXP
DP_IG_D_MLN<3..0>
TP_SATA_F_D2RP
TP_CRT_IG_DDC_DATA
TP_CRT_IG_VSYNC
TP_CRT_IG_BLUE
TP_CRT_IG_RED
TP_CRT_IG_GREEN
TP_SATA_E_R2D_CP
TP_SATA_C_D2RN
TP_SATA_C_D2RP
TP_SATA_C_R2D_CN
TP_PCH_TP20
TP_PCH_TP19
TP_PCH_TP18
TP_PCH_TP17
TP_PCH_TP16
TP_PCH_TP15
TP_PCH_TP13
TP_PCH_TP14
TP_PCH_TP12
TP_PCH_TP11
TP_PCH_TP10
TP_PCH_TP9
TP_PCH_TP8
TP_PCH_TP7
TP_PCH_TP6
TP_PCH_TP5
TP_PCH_TP4
TP_PCH_TP3
TP_SATA_D_D2RP
TP_PCH_TP2
TP_SATA_C_R2D_CP
TP_SATA_E_D2RP
DP_IG_C_HPD
DP_IG_D_CTRL_CLK
DP_IG_C_CTRL_DATA
TP_LPC_DREQ0_L
TP_PCH_INIT3V3_L
TP_HDA_SDIN1
TP_CRT_IG_HSYNC
TP_SATA_F_R2D_CP
TP_PCH_RESERVE_22
TP_PCH_RESERVE_26
TP_SATA_E_R2D_CN
TP_PCH_TP1
TP_SATA_F_D2RN
DP_IG_B_DDC_CLK
TP_PCI_AD<31..0>
TP_PCI_C_BE_L<3..0>
TP_PCI_PAR
TP_PCI_RESET_L
TP_PCH_PCI_GNT0_L
TP_PCH_RESERVE_2
TP_PCH_RESERVE_1
DP_IG_B_AUX_P
DP_IG_B_MLN<3..0>
DP_IG_B_MLP<3..0>TP_MEM_B_DQS_N<8>
TP_MEM_B_DQS_P<8>
DP_IG_B_HPD
TP_PCIE_CLK100M_PE6N
TP_PCIE_CLK100M_PE7P
TP_PE_TX_N<3..0>
TP_PE_RX_N<3..0>
TP_PE_TX_P<3..0>
TP_PE_RX_P<3..0>
USB_PCH_4_P
USB_PCH_6_N
USB_PCH_6_P
USB_PCH_11_P
USB_PCH_12_P
USB_PCH_12_N
USB_PCH_13_P
USB_PCH_13_N
TP_PCH_CLKOUT_DPP
TP_PCIE_CLK100M_PE7N
TP_PCIE2_D2RN
TP_PCIE1_D2RP
TP_CRT_IG_DDC_CLK
TP_PCIE1_R2D_CP
DP_IG_B_AUX_N
MAKE_BASE=TRUE
NC_PCIE2_R2D_PNX
NO_TEST=TRUE
NO_TEST=TRUE
NC_PCIE1_D2RNX
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MEM_B_DQSNX<8>
MAKE_BASE=TRUE
NC_CPU_RSVD<46..19>
NO_TEST=TRUE
NC_PCH_RESERVE_6
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_SATA_C_R2D_CNX
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_SATA_D_R2D_CNX
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_PWM0
NC_HDA_SDIN3
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_FDI_INT
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_SDVO_TVCLKINNX
MAKE_BASE=TRUE
NC_PCH_FDI_FSYNC<1..0>
NO_TEST=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_DP_IG_D_AUXPX
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_CPU_FDI_LSYNC<1..0>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_CPU_FDI_FSYNC<1..0>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_FDI_RPX<7..0>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_FDI_RNX<7..0>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_CPU_FDI_TPX<7..0>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_L_BKLTEN
NC_PCH_L_VDD_EN
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCI_CLK33M_OUT2
MAKE_BASE=TRUE
NC_PCH_CL_CLK1
NO_TEST=TRUE
NC_PCH_L_BKLTCTL
NO_TEST=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_PCI_CLK33M_OUT3
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_CL_RST1
NO_TEST=TRUE
NO_TEST=TRUE
NC_PCH_CL_DATA1
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_SST
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_PCH_PWM3
NO_TEST=TRUE
NO_TEST=TRUE
NC_PCH_PWM2
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_PWM1
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_DP_IG_D_AUXNX
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_DP_IG_D_MLPX<3..0>
NC_PCH_FDI_LSYNC<1..0>
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NC_CPU_FDI_INT
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_CPU_FDI_TNX<7..0>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_RESERVE_17
NO_TEST=TRUE
NC_PCH_RESERVE_18
MAKE_BASE=TRUE
NC_PCH_RESERVE_14
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_RESERVE_13
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NC_PCH_RESERVE_12
MAKE_BASE=TRUE
NC_PCH_RESERVE_10
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_RESERVE_11
NC_PCH_RESERVE_9
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_RESERVE_8
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_RESERVE_7
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_PCH_RESERVE_5
NO_TEST=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_RESERVE_3
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_RESERVE_4
MAKE_BASE=TRUE
NC_PCH_RESERVE_2
NO_TEST=TRUE
NC_PCH_RESERVE_0
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_RESERVE_1
NO_TEST=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_SDVO_STALLNX
NC_DP_IG_C_HPD
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_DP_IG_D_CTRL_CLK
MAKE_BASE=TRUE
NC_DP_IG_D_HPD
NO_TEST=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_DP_IG_D_MLNX<3..0>
NO_TEST=TRUE
NC_DP_IG_C_CTRL_CLK
MAKE_BASE=TRUE
NC_DP_IG_C_CTRL_DATA
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_DP_IG_C_MLPX<3..0>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_DP_IG_C_MLNX<3..0>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_SATA_F_D2RPX
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_SATA_F_D2RNX
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_SATA_F_R2D_CPX
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_DP_IG_B_CTRL_CLK
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_DP_IG_B_MLPX<3..0>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_DP_IG_B_MLNX<3..0>
NC_CRT_IG_DDC_CLK
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_CRT_IG_VSYNC
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_CRT_IG_BLUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_CRT_IG_HSYNC
NC_CRT_IG_RED
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_CRT_IG_GREEN
NO_TEST=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_SATA_E_D2RNX
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_SATA_E_R2D_CPX
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_SATA_D_D2RPX
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_SATA_D_D2RNX
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_SATA_D_R2D_CPX
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_SATA_C_D2RNX
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_SATA_C_D2RPX
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_TP19
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_TP18
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_TP17
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_TP16
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_TP15
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_TP13
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_TP14
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_TP12
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_TP11
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_TP10
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_TP9
MAKE_BASE=TRUE
NC_PCH_TP8
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_TP7
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_TP6
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_TP5
MAKE_BASE=TRUE
NC_PCH_TP4
NO_TEST=TRUE
NO_TEST=TRUE
NC_PCH_TP1
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_PCH_TP2
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_TP3
NC_CRT_IG_DDC_DATA
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_DP_IG_C_AUXPX
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_DP_IG_B_HPD
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_DP_IG_B_AUXPX
NC_PCI_AD<31..0>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCI_PAR
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NC_PCI_C_BE_L<3..0>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_PCI_RESET_L
NO_TEST=TRUE
NC_PCI_GNT0_L
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_LPC_DREQ0_L
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_INIT3V3_L
NC_HDA_SDIN1
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NC_HDA_SDIN2
MAKE_BASE=TRUE
NC_CPU_RSVD<16..1>
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_DP_IG_D_CTRL_DATA
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_SDVO_STALLPX
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_SDVO_INTNX
MAKE_BASE=TRUE
NC_MEM_A_DQ_CB<7..0>
NO_TEST=TRUE
NC_MEM_B_DQ_CB<7..0>
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_SDVO_TVCLKINPX
MAKE_BASE=TRUE
NC_SDVO_INTPX
NO_TEST=TRUE
NO_TEST=TRUE
NC_PCH_RESERVE_27
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_RESERVE_16
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_RESERVE_15
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_SATA_E_D2RPX
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_SATA_F_R2D_CNX
NO_TEST=TRUE
NC_PCH_RESERVE_19
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_PCH_RESERVE_20
NO_TEST=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_RESERVE_21
MAKE_BASE=TRUE
NC_PCH_RESERVE_22
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_SATA_E_R2D_CNX
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_RESERVE_23
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_RESERVE_24
NO_TEST=TRUE
NC_PCH_RESERVE_25
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_RESERVE_26
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_RESERVE_28
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_TP20
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_DP_IG_B_CTRL_DATA
MAKE_BASE=TRUE
NC_MEM_A_DQSNX<8>
NO_TEST=TRUE
NC_MEM_A_DQSPX<8>
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_DP_IG_B_AUXNX
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_SATA_C_R2D_CPX
MAKE_BASE=TRUE
TP_CPU_CFG<15..12>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MEM_B_DQSPX<8>
MAKE_BASE=TRUE
NC_PCIE_CLK100M_PE4PX
NO_TEST=TRUE
NC_PCIE_CLK100M_PE4NX
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCIE_CLK100M_PE5PX
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCIE_CLK100M_PE6NX
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NC_PCIE_CLK100M_PE6PX
MAKE_BASE=TRUE
NC_PCIE_CLK100M_PE7PX
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCIE_CLK100M_PE7NX
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PE_RNX<3..0>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PE_TPX<3..0>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PE_RPX<3..0>
NC_USB_PCH_4NX
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_USB_PCH_4PX
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_USB_PCH_5PX
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_USB_PCH_5NX
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_USB_PCH_6NX
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_USB_PCH_6PX
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_USB_PCH_11PX
NC_USB_PCH_11NX
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_USB_PCH_12PX
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_USB_PCH_12NX
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_USB_PCH_13PX
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_USB_PCH_13NX
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_CLKOUT_DPNX
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCIE2_D2RNX
NO_TEST=TRUE
NC_PCIE2_D2RPX
MAKE_BASE=TRUE
NC_PCIE1_D2RPX
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCIE1_R2D_CNX
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCIE1_R2D_CPX
TP_PCIE_CLK100M_PE5P
NC_PCH_CLKOUT_DPPX
NO_TEST=TRUE
MAKE_BASE=TRUE
TP_PCH_CLKOUT_DPN
USB_PCH_4_N
USB_PCH_5_N
USB_PCH_5_P
USB_PCH_11_N
NO_TEST=TRUE
NC_PCH_GPIO65_CLKOUTFLEX1
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_GPIO66_CLKOUTFLEX2
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_GPIO67_CLKOUTFLEX3TP_PCH_GPIO67_CLKOUTFLEX3
TP_PCH_GPIO66_CLKOUTFLEX2
TP_PCH_GPIO65_CLKOUTFLEX1
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_GPIO64_CLKOUTFLEX0TP_PCH_GPIO64_CLKOUTFLEX0
PCH_CLK25M_XTALOUT
NO_TEST=TRUE
NC_PCH_CLK25M_XTALOUT
MAKE_BASE=TRUE
NC_PCIE_CLK100M_PE0PX
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCIE_CLK100M_PE0NX
NO_TEST=TRUE
MAKE_BASE=TRUE
TP_PCIE_CLK100M_PE4P
TP_PCIE_CLK100M_PE4N
TP_PCIE_CLK100M_PE0P
prefsb
051-9504
7.0.0
8 OF 143
8 OF 117
12
12
18
18
20
20
21
21
19
19
18
21
18
18
18
18
19
19
18
18
12
10
10
10
18
18
18
18
18
12
21
18
19
19
19
19
19
10
10
19
19
10
10
10
18
18
18
19
18
18
19
19
19
19
19
19
18
21
21
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
18
19
19
19
19
19
19
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19
19
19
19
19
18
18
18
18
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
18
21 18
18
19
19
19
18
19
18
19
18
19
19
18
21
18
19
20
20
20
20
20
19
19
19
19
19 12
12
19
21
21
10
10
10
10
20
20
20
20
20
20
20
20
18
21
18
18
19
18
19
18
18
20
20
20
20
18
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18
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
ALIASES (BLANK)
SYNC_MASTER=K70_MLB
SYNC_DATE=08/23/2011
Signal Aliases
prefsb
051-9504
7.0.0
9 OF 143
9 OF 117
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
DMI_TX_1*
PE_TX_3*
PE_TX_3
PE_TX_2*
PE_TX_2
PE_TX_1*
PE_TX_1
PE_TX_0*
PE_TX_0
PE_RX_3*
PE_RX_3
PE_RX_2*
PE_RX_2
PE_RX_1*
PE_RX_1
PE_RX_0*
PE_RX_0
PEG_TX_15*
PEG_TX_15
PEG_TX_14*
PEG_TX_14
PEG_TX_13*
PEG_TX_13
PEG_TX_12*
PEG_TX_12
PEG_TX_11*
PEG_TX_11
PEG_TX_10*
PEG_TX_10
PEG_TX_9*
PEG_TX_9
PEG_TX_8*
PEG_TX_8
PEG_TX_7*
PEG_TX_7
PEG_TX_6
PEG_TX_5*
PEG_TX_5
PEG_TX_4*
PEG_TX_4
PEG_TX_3*
PEG_TX_3
PEG_TX_2*
PEG_TX_2
PEG_TX_1*
PEG_TX_1
PEG_TX_0*
PEG_TX_0
PEG_RX_15*
PEG_RX_15
PEG_RX_13*
PEG_RX_12
PEG_RX_11*
PEG_RX_11
PEG_RX_10
PEG_RX_9
PEG_RX_8
PEG_RX_7
PEG_RX_6
PEG_RX_5
PEG_RX_4*
PEG_RX_4
PEG_RX_3*
PEG_RX_3
PEG_RX_2
PEG_RX_1*
PEG_RX_0
FDI_TX_7*
FDI_TX_7
FDI_TX_6*
FDI_TX_6
FDI_TX_5*
FDI_TX_5
FDI_TX_4*
FDI_TX_4
FDI_TX_3*
FDI_TX_3
FDI_TX_2*
FDI_TX_2
FDI_TX_1*
FDI_TX_1
FDI_TX_0*
FDI_TX_0
FDI_LSYNC_1
FDI_LSYNC_0
FDI_FSYNC_1
FDI_FSYNC_0
DMI_TX_3*
DMI_TX_3
DMI_TX_2*
DMI_TX_2
DMI_TX_1
DMI_TX_0*
DMI_TX_0
DMI_RX_3*
DMI_RX_3
DMI_RX_2*
DMI_RX_2
DMI_RX_1
DMI_RX_0*
FDI_COMPIO
FDI_ICOMPO
FDI_INT
PEG_COMPI
PEG_ICOMPO
PEG_RX_1
PEG_RX_14*
PEG_RX_12*
PEG_RX_6*
PEG_RX_13
PEG_RX_14
PEG_RCOMPO
PEG_RX_10*
PEG_RX_9*
PEG_RX_8*
PEG_RX_7*
PEG_RX_2*
PEG_RX_0*
PEG_RX_5*
PEG_TX_6*
DMI_RX_0
DMI_RX_1*
SYM 1 OF 10
FLEXIBLE DISPLAY INTERFACE
PCI EXPRESS -- GRAPHICS
DMI
PCI EXPRESS
RSVD_NCTF_AV1
RSVD_NCTF_AW2
RSVD_NCTF_AY3
RSVD_NCTF_B39
NCTF_AW38
NCTF_AU40
NCTF_D1
NCTF_C2
NCTF_A38
CFG_8
RSVD_J34
RSVD_J33
RSVD_J31
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
RSVD_K9
RSVD_K31
RSVD_K34
RSVD_L9
RSVD_L31
RSVD_L33
RSVD_L34
RSVD_M34
RSVD_N33
RSVD_N34
RSVD_P35
RSVD_P37
RSVD_P39
RSVD_R34
RSVD_R36
RSVD_R38
RSVD_R40
RSVD_AB6
RSVD_AB7
RSVD_AD34
RSVD_AD35
RSVD_AD37
RSVD_AE6
RSVD_AF4
RSVD_AG4
RSVD_AJ11
RSVD_AJ29
RSVD_AJ30
RSVD_AJ31
RSVD_AN20
RSVD_AP20
RSVD_AT11
RSVD_AT14
RSVD_AU10
RSVD_AV34
RSVD_AW34
RSVD_AY10
RSVD_J9
RSVD_H8
RSVD_H7
RSVD_C38
RSVD_D38
RSVD_C39
SYM 5 OF 10
RESERVED
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
(Available for Workstation only)
CFG [6:5] PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = 1 X8, 2 X4
CFG [3] PCIE STATIC X4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED
CFG [1:0] RESERVED CONFIGURATION LANE
( IVY BRIDGE EDS #473717 TABLE 6-5 )
CFG [17:7] RESERVED CONFIGURATION LANE
CFG [4] RESERVED CONFIGURATION LANE
INTEL SUGGESTS TO KEEP THESE TPS
ThermDA
ThermDC
(Unused)
ROUTE B5 TO R1010.1 AS A SEPERATE 12 MIL TRACE.
SHORT B4 & C4 TOGETHER, ROUTE AS A SINGLE 4 MIL TRACE TO R1010.1
CFG [2] PCIE STATIC X16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED
19 99
19 99
19 99
19 99
19 99
19 99
19 99
19 99
19 99
19 99
19 99
19 99
19 99
19 99
19 99
19 99
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
75 98
402
MF-LF
24.9
1%
PLACE_NEAR=U1000.B4:12.7MM
R1010
1/16W
25 99
25 99
8
8
8
8
25 99
25 99
25 99
25 99
25 99
15 25 99
15 25 99
25 99
15 25 99
15 25 99
25 99
25 99
BGA-SKT-K70
IVY-BRIDGE
OMIT_TABLE
U1000
BGA-SKT-K70
OMIT_TABLE
IVY-BRIDGE
U1000
PLACE_NEAR=U1000.AE2:6.3MM
MF-LF
1/16W
402
5%
0
R1011
CPU DMI/PEG/FDI/RSVD
SYNC_DATE=03/23/2012
SYNC_MASTER=D8_ROSITA
CPU_FDI_COMPIO
TP_PE_TX_P<3>
TP_PE_TX_P<2>
TP_CPU_FDI_TX_N<2>
PEG_D2R_C_P<5>
CPU_PEG_COMP
PEG_D2R_C_N<1>
PEG_D2R_C_N<2>
PEG_D2R_C_N<3>
=PPVCCIO_S0_CPU
PEG_D2R_C_P<3>
PEG_D2R_C_N<12>
PEG_D2R_C_N<11>
PEG_D2R_C_N<5>
CPU_CFG<7>
TP_PE_RX_P<1>
TP_CPU_FDI_TX_P<7>
TP_CPU_FDI_TX_P<2>
TP_PE_RX_N<0>
TP_PE_RX_N<3>
TP_PE_RX_P<2>
PEG_R2D_P<14>
TP_CPU_FDI_TX_P<4>
PEG_D2R_C_P<14>
TP_PE_TX_P<0>
DMI_S2N_N<3>
DMI_S2N_N<0>
PEG_R2D_P<11>
PEG_R2D_P<13>
PEG_R2D_P<7>
PEG_D2R_C_N<15>
PEG_D2R_C_P<0>
DMI_S2N_P<2>
DMI_N2S_P<2>
PEG_D2R_C_N<8>
CPU_CFG<15>
PEG_D2R_C_N<4>
CPU_CFG<0>
CPU_CFG<3>
TP_CPU_RSVD<16>
PEG_D2R_C_N<14>
PEG_D2R_C_P<2>
PEG_D2R_C_N<6>
DMI_S2N_P<1>
TP_CPU_FDI_TX_N<6>
PEG_R2D_P<0>
DMI_N2S_N<0>
TP_CPU_FDI_TX_N<3>
TP_CPU_RSVD<30>
DMI_N2S_N<2>
PEG_D2R_C_N<13>
TP_CPU_FDI_FSYNC<1>
TP_PE_RX_P<0>
TP_PE_TX_N<0>
DMI_N2S_P<1>
DMI_N2S_N<1>
PEG_R2D_P<3>
PEG_R2D_P<2>
PEG_R2D_P<1>
DMI_N2S_P<3>
PEG_R2D_N<0>
PEG_D2R_C_P<7>
PEG_D2R_C_P<15>
CPU_CFG<17>
CPU_CFG<16>
CPU_CFG<14>
DMI_S2N_N<1>
DMI_S2N_P<3>
TP_CPU_FDI_LSYNC<0>
TP_CPU_FDI_TX_P<5>
PEG_R2D_P<12>
PEG_R2D_N<10>
TP_CPU_FDI_TX_P<0>
TP_PE_TX_N<2>
CPU_CFG<12>
CPU_CFG<9>
CPU_CFG<6>
TP_CPU_RSVD<8>
PEG_D2R_C_P<11>
PEG_R2D_P<5>
PEG_R2D_P<8>
PEG_R2D_N<14>
TP_PE_TX_P<1>
TP_CPU_RSVD<2>
TP_CPU_RSVD<3>
TP_CPU_RSVD<1>
TP_CPU_RSVD<4>
TP_CPU_RSVD<46>
TP_CPU_RSVD<40>
TP_CPU_RSVD<39>
TP_CPU_RSVD<38>
TP_CPU_RSVD<37>
TP_CPU_RSVD<35>
TP_CPU_RSVD<34>
TP_CPU_RSVD<33>
TP_CPU_RSVD<32>
TP_CPU_RSVD<31>
TP_CPU_RSVD<28>
TP_CPU_RSVD<27>
TP_CPU_RSVD<25>
TP_CPU_RSVD<24>
TP_CPU_RSVD<23>
TP_CPU_RSVD<22>
TP_CPU_RSVD<21>
TP_CPU_RSVD<20>
CPU_CFG<11>
CPU_CFG<10>
CPU_CFG<4>
TP_CPU_RSVD<7>
TP_CPU_RSVD<9>
TP_CPU_NCTF<1>
TP_CPU_NCTF<2>
TP_CPU_NCTF<4>
CPU_CFG<13>
CPU_CFG<8>
TP_CPU_RSVD<15>
TP_CPU_RSVD<14>
TP_CPU_RSVD<13>
TP_CPU_RSVD<12>
TP_CPU_RSVD<10>
TP_CPU_RSVD<5>
TP_CPU_RSVD<6>
TP_CPU_RSVD<26>
TP_PE_TX_N<1>
TP_CPU_FDI_TX_P<1>
DMI_S2N_P<0>
TP_CPU_RSVD<36>
TP_CPU_RSVD<43>
TP_CPU_NCTF<3>
TP_CPU_NCTF<5>
TP_CPU_RSVD<29>
PEG_R2D_P<10>
PEG_R2D_P<9>
TP_CPU_RSVD<19>
TP_CPU_RSVD<45>
TP_CPU_RSVD_NCTF<4>
TP_CPU_RSVD_NCTF<3>
TP_CPU_RSVD_NCTF<2>
TP_CPU_RSVD_NCTF<1>
TP_CPU_RSVD<44>
TP_CPU_RSVD<42>
TP_CPU_RSVD<41>
CPU_CFG<2>
CPU_CFG<1>
DMI_N2S_N<3>
TP_CPU_FDI_TX_P<3>
TP_CPU_FDI_TX_N<4>
PEG_R2D_N<1>
TP_PE_RX_P<3>
TP_CPU_FDI_INT
TP_CPU_FDI_TX_N<0>
TP_CPU_FDI_TX_N<1>
PEG_D2R_C_N<9>
PEG_D2R_C_N<10>
PEG_R2D_N<2>
PEG_R2D_N<15>
PEG_R2D_P<6>
TP_CPU_FDI_LSYNC<1>
TP_CPU_FDI_FSYNC<0>
TP_CPU_FDI_TX_P<6>
PEG_D2R_C_P<12>
PEG_R2D_N<5>
TP_CPU_RSVD<11>
PEG_D2R_C_N<7>
TP_CPU_FDI_TX_N<5>
PEG_D2R_C_P<4>
PEG_D2R_C_P<1>
PEG_R2D_N<4>
PEG_R2D_P<4>
TP_PE_TX_N<3>
PEG_R2D_P<15>
PEG_R2D_N<13>
PEG_R2D_N<8>
PEG_R2D_N<6>
DMI_N2S_P<0>
PEG_R2D_N<12>
PEG_R2D_N<11>
PEG_R2D_N<9>
PEG_D2R_C_P<6>
PEG_D2R_C_P<9>
PEG_D2R_C_P<8>
DMI_S2N_N<2>
PEG_R2D_N<3>
PEG_R2D_N<7>
TP_CPU_FDI_TX_N<7>
PEG_D2R_C_P<10>
PEG_D2R_C_P<13>
NC_SNS_CPU_THERMDP
NO_TEST=TRUE
NC_SNS_CPU_THERMDN
NO_TEST=TRUE
CPU_CFG<5>
PEG_D2R_C_N<0>
TP_PE_RX_N<2>
TP_PE_RX_N<1>
prefsb
051-9504
7.0.0
10 OF 143
10 OF 117
12
W8
U6
U5
R5
R6
T8
T7
P7
P8
U1
U2
T3
T4
R1
R2
P4
P3
N6
N5
L5
L6
M7
M8
J6
J5
K8
K7
G6
G5
G9
G10
F7
F8
E5
E6
D3
D7
D8
J13
J14
F11
F12
G13
G14
E13
E14
C14
C13
N2
N1
L2
K3
J2
J1
H3
G2
F4
E2
A5
C6
B7
B8
E9
E10
C10
D11
B11
AG1
AG2
AF2
AF3
AE8
AE7
AD6
AD7
AD3
AD4
AD1
AD2
AC3
AC2
AC7
AC8
AE4
AC4
AE5
AC5
AA8
AA7
Y7
Y6
W7
V6
V7
AA5
AA4
Y4
Y3
V3
W4
AE2
AE1
AG3
B4
B5
D12
M4
K4
A6
L1
M3
C4
H4
G1
F3
E1
C9
B12
C5
C3
W5
V4
AV1
AW2
AY3
B39
AW38
AU40
D1
C2
A38
J38
J34
J33
J31
H36
J36
J37
K36
L36
N35
L37
M36
L35
M38
N36
N38
N39
N37
N40
G37
G36
K9
K31
K34
L9
L31
L33
L34
M34
N33
N34
P35
P37
P39
R34
R36
R38
R40
AB6
AB7
AD34
AD35
AD37
AE6
AF4
AG4
AJ11
AJ29
AJ30
AJ31
AN20
AP20
AT11
AT14
AU10
AV34
AW34
AY10
J9
H8
H7
C38
D38
C39
1
2
99
8
8
8
98
6
11 13 16 28 66
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
BI
BI
BI
BI
BI
IN
IN
OUT
OUT
OUT
IN
IN
OUT
OUT
BI
BI
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
SM_VREF
SM_DRAMRST*
SM_DRAMPWROK
PM_SYNC
PREQ*
TMS
TRST*
TDI
TDO
DBR*
BPM[0]*
BPM[1]*
BPM[2]*
BPM[3]*
BPM[4]*
BPM[5]*
BPM[6]*
BPM[7]*
TCK
PRDY*
BCLK_ITP
BCLK_0
BCLK_ITP*
BCLK_0*
UNCOREPWRGOOD
SKTOCC*
RESET*
THERMTRIP*
CATERR*
PECI
PROCHOT*
PROC_SEL
SYM 2 OF 10
CLOCKS
THERMAL
DDR3 MISC
PWR MGMT
JTAG & BPM
OUT
IN
OUT
IN
IN
IN
OUT
IN
IN
IN
IN
IN
OUT
OUT
BI
BI
BI
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
BASED ON INTEL MOBILE SOLUTION
FROM PCH
25 99
25 99
25 99
25 99
25 99
R1111
1/16W
5%
402
MF-LF
1K
19 28 99
21 25 28 99
34
106
34
106
28 99
15 99
15 99
19 99
48 99
47 48 66 99
21 47 48 99
R1124
1/16W
5%
402
75
PLACE_NEAR=U1000.F36:50mm
MF-LF
U1000
BGA-SKT-K70
OMIT_TABLE
IVY-BRIDGE
R1141
1/16W
1%
1K
402
MF-LF
R1140
1/16W
1%
402
MF-LF
1K
10%
X7R-CERM
16V
0.1UF
C1140
0402
48 99
R1102
MF-LF
5%
0
1/16W
402
R1101
1/16W
5%
402
MF-LF
51
25 99
25 99
25 99
25 99
25 99
25 99
25 99
R1120
1/16W
1%
402
MF-LF
200
R1121
130
MF-LF
402
1%
1/16W
18 99
18 99
19 99
R1125
402
1/16W
5%
MF-LF
43
26 99
64 99
25 99
25 99
25 99
25 99
SYNC_DATE=03/15/2012
SYNC_MASTER=D7_MLB
CPU CLOCK/MISC/JTAG
CPU_DDR_VREF
=PP1V5_S0_CPU_MEM
DMI_CLK100M_CPU_N
ITPCPU_CLK100M_N
DMI_CLK100M_CPU_P
ITPCPU_CLK100M_P
XDP_CPU_PRDY_L
XDP_CPU_TCK
XDP_BPM_L<7>
XDP_BPM_L<6>
XDP_BPM_L<5>
XDP_BPM_L<4>
XDP_BPM_L<3>
XDP_BPM_L<2>
XDP_BPM_L<1>
XDP_BPM_L<0>
XDP_DBRESET_L
XDP_CPU_TDO
XDP_CPU_TDI
XDP_CPU_TRST_L
XDP_CPU_TMS
XDP_CPU_PREQ_L
=PP1V5_S0_CPU_MEM
=PPVCCIO_S0_CPU
PM_MEM_PWRGD_R
CPU_DDR_VREF
PM_MEM_PWRGD
CPU_RESET_L
CPU_DIMM_VREF_DAC_A
CPU_DIMM_VREF_DAC_B
CPU_MEM_RESET_L
PLT_RESET_LS1V05_L
PM_SYNC
CPU_PWRGD
CPU_THRMTRIP_L
CPU_PECI
CPU_CATERR_L
CPU_PROC_SEL
CPU_SKTOCC_L
CPU_PROCHOT_R_L
=PPVCCIO_S0_CPU
CPU_PROCHOT_L
prefsb
051-9504
7.0.0
11 OF 143
11 OF 117
1
2
1
2
AH4
AH1
AJ22
AW18
AJ19
E38
K40
L38
J39
L40
L39
E39
H40
H38
G38
G40
G39
F38
E40
F40
M40
K38
C40
W2
D40
W1
J40
AJ33
F36
G35
E37
J35
H34
K32
1
2
1
2
2
1
12
1
2
1
2
12
12
11
106
6
11 13 16
6
11 13 16
6
10 11 13 16 28 66
99
11
106
99
99
6
10 11 13 16 28 66
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT OUT
SA_DQ_32
SA_DQ_33
SA_DQS_8*
SA_BS_2
SA_CAS*
SA_BS_1
SA_BS_0
SA_DQ_63
SA_DQ_62
SA_DQ_61
SA_DQ_60
SA_DQ_9
SA_CK_1
SA_ODT_2
SA_ODT_1
SA_ODT_0
SA_RAS*
SA_WE*
SA_CK_0
SA_CK_0*
SA_CK_1*
SA_CK_2
SA_CK_2*
SA_CK_3
SA_CK_3*
SA_CKE_0
SA_CKE_1
SA_CKE_2
SA_CKE_3
SA_CS_0*
SA_CS_1*
SA_CS_2*
SA_CS_3*
SA_DQ_0
SA_DQ_1
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_2
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_3
SA_DQ_30
SA_DQ_31
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_4
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_5
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQS_0
SA_DQS_0*
SA_DQS_1
SA_DQS_1*
SA_DQS_2
SA_DQS_2*
SA_DQS_3
SA_DQS_3*
SA_DQS_4
SA_DQS_4*
SA_DQS_5
SA_DQS_5*
SA_DQS_6
SA_DQS_6*
SA_DQS_7
SA_DQS_7*
SA_DQS_8
SA_ECC_CB_0
SA_ECC_CB_1
SA_ECC_CB_2
SA_ECC_CB_3
SA_ECC_CB_4
SA_ECC_CB_5
SA_ECC_CB_6
SA_ECC_CB_7
SA_MA_0
SA_MA_1
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
SA_MA_15
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_ODT_3
SYM 3 OF 10
DDR SYSTEM MEMORY A
SB_CK_1*
SB_DQS_3*
SB_DQ_33
SB_DQS_4
SB_DQS_2
SB_DQS_8*
SB_CKE_3
SB_CS_0*
SB_CS_1*
SB_CS_2*
SB_CS_3*
SB_CAS*
SB_RAS*
SB_WE*
SB_BS_0
SB_BS_1
SB_BS_2
SB_CK_0
SB_CK_0*
SB_CK_1
SB_CK_2
SB_CK_2*
SB_CK_3
SB_CK_3*
SB_CKE_0
SB_CKE_1
SB_CKE_2
SB_DQ_0
SB_DQ_1
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_2
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_3
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_4
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_5
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_6
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQS_0
SB_DQS_0*
SB_DQS_1
SB_DQS_1*
SB_DQS_2*
SB_DQS_3
SB_DQS_4*
SB_DQS_5
SB_DQS_5*
SB_DQS_6
SB_DQS_6*
SB_DQS_7
SB_DQS_7*
SB_DQS_8
SB_ECC_CB_0
SB_ECC_CB_1
SB_ECC_CB_2
SB_ECC_CB_3
SB_ECC_CB_4
SB_ECC_CB_5
SB_ECC_CB_6
SB_ECC_CB_7
SB_MA_0
SB_MA_1
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
SB_MA_15
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_ODT_0
SB_ODT_1
SB_ODT_2
SB_ODT_3
SYM 4 OF 10
DDR SYSTEM MEMORY B
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
29 30 97
29 30 97
29 30 97
29 30 97
29 30 97
29 30 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
29 30 97
29 30 97
29 30 97
29 30 97
29 30 97
29 30 97
29 30 97
29 30 97
29 30 97
29 30 97
29 30 97
29 30 97
29 30 97
29 30 97
29 30 97
29 97
29 97
29 97
29 97
29 97
29 97
29 97
29 97
29 97
29 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
33 97
31 32 97
31 32 97
31 32 97
31 32 97
31 32 97
31 32 97
31 97
31 97
31 97
31 97
31 97
31 97
31 97
31 97
31 97
31 97
33 97
33 97
33 97
33 97
33 97
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33 97
33 97
33 97
33 97
33 97
33 97
31 32 97
31 32 97
31 32 97
31 32 97
31 32 97
31 32 97
31 32 97
31 32 97
31 32 97
31 32 97
31 32 97
31 32 97
31 32 97
31 32 97
31 32 97
30 97
30 97
30 97
30 97
30 97
30 97
30 97
30 97
30 97
30 97
32 97
32 97
32 97
32 97
32 97
32 97
32 97
32 97
32 97
32 97
29 30 97 31 32 97
U1000
BGA-SKT-K70
OMIT_TABLE
IVY-BRIDGE
U1000
BGA-SKT-K70
OMIT_TABLE
IVY-BRIDGE
SYNC_DATE=03/15/2012
SYNC_MASTER=D7_MLB
CPU DDR3 INTERFACES
MEM_B_DQ<53>
MEM_A_CLK_P<0>
MEM_A_DQ<8>
MEM_A_DQ<6>
MEM_A_DQS_P<3>
MEM_A_DQ<11> MEM_B_DQ<11>
MEM_B_DQ<12>
MEM_A_DQ<9>
MEM_A_DQ<5>
MEM_A_DQ<4>
MEM_A_DQ<3>
MEM_A_DQ<2>
MEM_A_DQ<10>
MEM_A_ODT<3>
MEM_A_A<9>
MEM_A_A<8>
MEM_A_A<7>
MEM_A_A<6>
MEM_A_A<5>
MEM_A_A<4>
MEM_A_A<3>
MEM_A_A<2>
MEM_A_A<15>
MEM_A_A<14>
MEM_A_A<13>
MEM_A_A<12>
MEM_A_A<11>
MEM_A_A<10>
MEM_A_A<1>
MEM_A_A<0>
TP_MEM_A_DQ_CB<7>
TP_MEM_A_DQ_CB<6>
TP_MEM_A_DQ_CB<5>
TP_MEM_A_DQ_CB<4>
TP_MEM_A_DQ_CB<3>
TP_MEM_A_DQ_CB<2>
TP_MEM_A_DQ_CB<1>
TP_MEM_A_DQ_CB<0>
TP_MEM_A_DQS_P<8>
MEM_A_DQS_N<7>
MEM_A_DQS_P<7>
MEM_A_DQS_N<6>
MEM_A_DQS_P<6>
MEM_A_DQS_N<5>
MEM_A_DQS_P<5>
MEM_A_DQS_N<4>
MEM_A_DQS_P<4>
MEM_A_DQS_N<3>
MEM_A_DQS_N<2>
MEM_A_DQS_P<2>
MEM_A_DQS_N<1>
MEM_A_DQS_P<1>
MEM_A_DQS_N<0>
MEM_A_DQS_P<0>
MEM_A_DQ<7>
MEM_A_DQ<59>
MEM_A_DQ<58>
MEM_A_DQ<57>
MEM_A_DQ<56>
MEM_A_DQ<55>
MEM_A_DQ<54>
MEM_A_DQ<53>
MEM_A_DQ<52>
MEM_A_DQ<51>
MEM_A_DQ<50>
MEM_A_DQ<49>
MEM_A_DQ<48>
MEM_A_DQ<47>
MEM_A_DQ<46>
MEM_A_DQ<45>
MEM_A_DQ<44>
MEM_A_DQ<43>
MEM_A_DQ<42>
MEM_A_DQ<41>
MEM_A_DQ<40>
MEM_A_DQ<39>
MEM_A_DQ<38>
MEM_A_DQ<37>
MEM_A_DQ<36>
MEM_A_DQ<35>
MEM_A_DQ<34>
MEM_A_DQ<31>
MEM_A_DQ<30>
MEM_A_DQ<29>
MEM_A_DQ<28>
MEM_A_DQ<27>
MEM_A_DQ<25>
MEM_A_DQ<24>
MEM_A_DQ<23>
MEM_A_DQ<22>
MEM_A_DQ<21>
MEM_A_DQ<20>
MEM_A_DQ<18>
MEM_A_DQ<17>
MEM_A_DQ<16>
MEM_A_DQ<15>
MEM_A_DQ<14>
MEM_A_DQ<13>
MEM_A_DQ<12>
MEM_A_DQ<1>
MEM_A_DQ<0>
MEM_A_CS_L<3>
MEM_A_CS_L<2>
MEM_A_CS_L<0>
MEM_A_CKE<0>
MEM_A_CLK_P<3>
MEM_A_CLK_N<0>
MEM_A_WE_L
MEM_A_RAS_L
MEM_A_ODT<0>
MEM_A_ODT<1>
MEM_A_DQ<60>
MEM_A_DQ<61>
MEM_A_DQ<62>
MEM_A_DQ<63>
MEM_A_BA<0>
MEM_A_BA<1>
MEM_A_CAS_L
MEM_A_BA<2>
TP_MEM_A_DQS_N<8>
MEM_A_DQ<33>
MEM_A_DQ<32>
MEM_B_ODT<3>
MEM_B_ODT<2>
MEM_B_ODT<1>
MEM_B_ODT<0>
MEM_B_A<9>
MEM_B_A<8>
MEM_B_A<7>
MEM_B_A<6>
MEM_B_A<5>
MEM_B_A<4>
MEM_B_A<3>
MEM_B_A<2>
MEM_B_A<15>
MEM_B_A<14>
MEM_B_A<13>
MEM_B_A<12>
MEM_B_A<11>
MEM_B_A<10>
MEM_B_A<1>
MEM_B_A<0>
TP_MEM_B_DQ_CB<7>
TP_MEM_B_DQ_CB<6>
TP_MEM_B_DQ_CB<5>
TP_MEM_B_DQ_CB<4>
TP_MEM_B_DQ_CB<3>
TP_MEM_B_DQ_CB<2>
TP_MEM_B_DQ_CB<1>
TP_MEM_B_DQ_CB<0>
TP_MEM_B_DQS_P<8>
MEM_B_DQS_N<7>
MEM_B_DQS_P<7>
MEM_B_DQS_N<6>
MEM_B_DQS_P<6>
MEM_B_DQS_N<5>
MEM_B_DQS_P<5>
MEM_B_DQS_N<4>
MEM_B_DQS_P<3>
MEM_B_DQS_N<2>
MEM_B_DQS_P<1>
MEM_B_DQS_N<0>
MEM_B_DQS_P<0>
MEM_B_DQ<9>
MEM_B_DQ<8>
MEM_B_DQ<7>
MEM_B_DQ<63>
MEM_B_DQ<62>
MEM_B_DQ<61>
MEM_B_DQ<6>
MEM_B_DQ<59>
MEM_B_DQ<58>
MEM_B_DQ<57>
MEM_B_DQ<56>
MEM_B_DQ<55>
MEM_B_DQ<54>
MEM_B_DQ<52>
MEM_B_DQ<51>
MEM_B_DQ<50>
MEM_B_DQ<5>
MEM_B_DQ<49>
MEM_B_DQ<48>
MEM_B_DQ<47>
MEM_B_DQ<46>
MEM_B_DQ<45>
MEM_B_DQ<44>
MEM_B_DQ<43>
MEM_B_DQ<42>
MEM_B_DQ<41>
MEM_B_DQ<40>
MEM_B_DQ<4>
MEM_B_DQ<39>
MEM_B_DQ<38>
MEM_B_DQ<37>
MEM_B_DQ<36>
MEM_B_DQ<35>
MEM_B_DQ<34>
MEM_B_DQ<32>
MEM_B_DQ<31>
MEM_B_DQ<30>
MEM_B_DQ<3>
MEM_B_DQ<29>
MEM_B_DQ<28>
MEM_B_DQ<27>
MEM_B_DQ<26>
MEM_B_DQ<25>
MEM_B_DQ<24>
MEM_B_DQ<23>
MEM_B_DQ<22>
MEM_B_DQ<21>
MEM_B_DQ<2>
MEM_B_DQ<19>
MEM_B_DQ<18>
MEM_B_DQ<17>
MEM_B_DQ<16>
MEM_B_DQ<15>
MEM_B_DQ<14>
MEM_B_DQ<13>
MEM_B_DQ<10>
MEM_B_DQ<1>
MEM_B_DQ<0>
MEM_B_CKE<0>
MEM_B_CLK_N<0>
MEM_B_CLK_P<0>
MEM_B_BA<2>
MEM_B_BA<1>
MEM_B_BA<0>
MEM_B_WE_L
MEM_B_RAS_L
MEM_B_CAS_L
TP_MEM_B_DQS_N<8>
MEM_B_DQS_P<2>
MEM_B_DQS_P<4>
MEM_B_DQ<33>
MEM_B_DQS_N<3>
MEM_B_CLK_N<1>
MEM_B_DQ<60>
MEM_B_DQS_N<1>
MEM_A_DQ<19>
MEM_A_DQ<26>
MEM_B_CLK_P<2>
MEM_A_CLK_N<2>
MEM_A_CLK_P<2>
MEM_A_CKE<3>
MEM_A_CLK_N<3>
MEM_A_CKE<2>
MEM_A_CLK_P<1>
MEM_A_CLK_N<1>
MEM_A_CKE<1>
MEM_A_CS_L<1>
MEM_A_ODT<2>
MEM_B_DQ<20>
MEM_B_CS_L<3>
MEM_B_CS_L<2>
MEM_B_CS_L<1>
MEM_B_CKE<2>
MEM_B_CLK_N<3>
MEM_B_CKE<3>
MEM_B_CS_L<0>
MEM_B_CLK_P<1>
MEM_B_CKE<1>
MEM_B_CLK_N<2>
MEM_B_CLK_P<3>
prefsb
051-9504
7.0.0
12 OF 143
12 OF 117
AU35
AW37
AV12
AV20
AV30
AW28
AY29
AE40
AE39
AG38
AG39
AN4
AU24
AU30
AU32
AV31
AU28
AW29
AY25
AW25
AU25
AW27
AY27
AV26
AW26
AV19
AT19
AU18
AV18
AU29
AV32
AW30
AU33
AJ3
AJ4
AR3
AR4
AN2
AN3
AR2
AR1
AV2
AW3
AV5
AW5
AL3
AU2
AU3
AU5
AY5
AY7
AU7
AV9
AU9
AV7
AW7
AL4
AW9
AY9
AU39
AU36
AW35
AY36
AU38
AU37
AJ2
AR40
AR37
AN38
AN37
AR39
AR38
AN39
AN40
AL40
AL37
AJ1
AJ38
AJ37
AL39
AL38
AJ39
AJ40
AG40
AG37
AE38
AE37
AL2
AL1
AN1
AK3
AK2
AP3
AP2
AW4
AV4
AV8
AW8
AV37
AV36
AP38
AP39
AK38
AK39
AF38
AF39
AV13
AU12
AU14
AW13
AY13
AU13
AU11
AY12
AW12
AV27
AY24
AV28
AU21
AT21
AW32
AU20
AT20
AW24
AW23
AV23
AT24
AT23
AU22
AV22
AT22
AW33
AK20
AN12
AR29
AN29
AR8
AN15
AV15
AN25
AN26
AL25
AT26
AK25
AP24
AR25
AP23
AM24
AW17
AL21
AL22
AL20
AL23
AM22
AP21
AN21
AU16
AY15
AW15
AG7
AG8
AM10
AL10
AL6
AM6
AL9
AM9
AP7
AR7
AP10
AR10
AJ9
AP6
AR6
AP9
AR9
AM12
AM13
AR13
AP13
AL12
AL13
AJ8
AR12
AP12
AR28
AL28
AL29
AP28
AP29
AM28
AM29
AG5
AP32
AP31
AP35
AP34
AR32
AR31
AR35
AR34
AM32
AM31
AG6
AL35
AL32
AM34
AL31
AM35
AL34
AH35
AH34
AE34
AE35
AJ6
AJ35
AJ34
AF33
AF35
AJ7
AL7
AM7
AH7
AH6
AM8
AL8
AP8
AN13
AN28
AP33
AR33
AL33
AM33
AG35
AG34
AN16
AL16
AM16
AP16
AR16
AL15
AM15
AR15
AP15
AK24
AM20
AN23
AU17
AT18
AR26
AY16
AV16
AM19
AK18
AP19
AP18
AM18
AL18
AN18
AY17
AL26
AP26
AM26
AK26
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
VCCIO_31
VCCIO_44
VCCIO_SEL
VCCIO_45
VCCIO_30
VSSAXG_SENSE
VCCAXG_SENSE
VSSIO_SENSE
VCCIO_SENSE
VCC_024
VCC_038
VCCIO_42
VCCIO_29
VCCIO_28
VCCIO_09
VCC_001
VCC_002
VCC_003
VCC_004
VCCIO_27
VCC_012
VCC_015
VCC_005
VCC_006
VCC_007
VCC_008
VCC_009
VCC_010
VCC_011
VCC_013
VCC_014
VCC_016
VCC_017
VCC_018
VCC_020
VCC_021
VCC_022
VCC_023
VCC_025
VCC_026
VCC_027
VCC_028
VCC_029
VCC_030
VCC_031
VCC_032
VCC_033
VCC_034
VCC_035
VCC_036
VCC_037
VCC_039
VCC_040
VCC_041
VCC_042
VCC_043
VCC_044
VCC_045
VCC_046
VCC_047
VCC_048
VCC_049
VCC_050
VCC_051
VCC_052
VCC_057
VCC_058
VCC_059
VCC_060
VCC_061
VCC_062
VCC_063
VCC_064
VCC_065
VCC_066
VCC_067
VCC_068
VCC_069
VCC_070
VCCIO_02
VCCIO_01
VCCIO_20
VCCIO_26
VCCIO_33
VCCIO_34
VCCIO_35
VCCIO_36
VCCIO_40
VCCIO_43
VCCIO_04
VCCIO_05
VCCIO_06
VCCIO_07
VCCIO_08
VCCIO_10
VCCIO_11
VCCIO_12
VCCIO_13
VCCIO_14
VCCIO_16
VCCIO_19
VCCSA_SENSE
VIDALERT*
VIDSCLK
VIDSOUT
VSS_SENSE
VCCIO_41
VCC_SENSE
VCC_056
VCC_055
VCC_054
VCC_053
VCCIO_03
VCC_019
VCCIO_15
VCCIO_17
VCCIO_18
VCCIO_22
VCCIO_21
VCCIO_23
VCCIO_24
VCCIO_25
VCCIO_32
VCCIO_37
VCCIO_38
VCCIO_39
VCCSA_VID
SYM 6 OF 10
CPU VIDS
POWER
IO POWER
CPU CORE SUPPLY
SENSE LINES
VCCAXG_44
VCCAXG_43
VCCAXG_02
VCCAXG_03
VDDQ10
VCCPLL1
VCCPLL0
VDDQ22
VDDQ21
VDDQ20
VDDQ19
VDDQ16
VDDQ14
VDDQ13
VDDQ12
VDDQ11
VDDQ9
VDDQ8
VDDQ7
VDDQ6
VDDQ4
VDDQ3
VDDQ2
VDDQ1
VDDQ0
VCCAXG_16
VCCAXG_15
VCCAXG_14
VCCAXG_13
VCCAXG_12
VCCAXG_11
VCCAXG_10
VCCAXG_09
VCCAXG_07
VCCAXG_06
VCCAXG_05
VCCAXG_04
VCCAXG_42
VCCAXG_41
VCCAXG_40
VCCAXG_39
VCCAXG_38
VCCAXG_37
VCCAXG_36
VCCAXG_35
VCCAXG_34
VCCAXG_33
VCCAXG_32
VCCAXG_31
VCCAXG_30
VCCAXG_29
VCCAXG_28
VCCAXG_27
VCCAXG_26
VCCAXG_25
VCCAXG_24
VCCAXG_22
VCCAXG_21
VCCAXG_19
VCCAXG_18
VCCAXG_17
VCCAXG_23
VCCAXG_20
VDDQ15
VDDQ17
VDDQ18
VDDQ5
VCCAXG_01
VCCAXG_08
SYM 7 OF 10
1.8V
POWER
DDR3-1.5V RAILS
GRAPHICS
VCC_092
VSS_NCTF2
VSS_NCTF3
VCC_097
VCC_091
VCC_090
VCC_089
VCC_088
VCC_087
VCC_083
VCC_112
VCC_117
VCC_113
VCC_114
VCC_115
VCC_116
VCC_118
VCC_119
VCC_120
VCC_121
VCC_122
VCC_123
VCC_124
VCC_125
VCC_128
VCC_129
VCC_130
VCC_131
VCC_132
VCC_133
VCC_134
VCC_135
VCC_136
VCC_137
VCC_138
VCC_139
VCC_140
VCC_141
VCC_142
VCC_143
VCC_144
VCC_145
VCC_146
VCC_147
VCC_148
VCC_149
VCC_150
VCC_151
VCC_152
VCC_153
VCC_156
VCC_157
VCC_158
VCC_159
VCC_160
VCCSA0
VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA8
VCCSA9
VSS_NCTF1
VCC_073
VCC_072
VCC_071
VCC_155
VCC_154
VCC_084
VCC_093
VSS_NCTF0
VCC_100
VCC_101
VCC_104
VCC_106
VCC_105
VCC_096
VCC_095
VCC_094
VCC_086
VCC_085
VCCSA7
VCCSA10
VCC_107
VCC_082
VCC_077
VCC_074
VCC_076
VCC_161
VCC_126
VCC_127
VCC_111
VCC_098
VCC_099
VCC_075
VCC_081
VCC_103
VCC_102
VCC_078
VCC_079
VCC_080
VCC_108
VCC_109
VCC_110
SYM 10 OF 10
CPU CORE SUPPLY
VCCSA
CPU CORE SUPPLY
POWER
NCTF
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
BI
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
U1000
BGA-SKT-K70
OMIT_TABLE
IVY-BRIDGE
U1000
IVY-BRIDGE
OMIT_TABLE
BGA-SKT-K70
U1000
BGA-SKT-K70
OMIT_TABLE
IVY-BRIDGE
70
104
66
105
66
105
69
104
69
104
66
105
66
105
R1311
402
5%
MF-LF
1/16W
0
R1310
44.2
MF-LF
1%
1/16W
402
R1312
402
1/16W
MF-LF
0
5%
PLACE_NEAR=U1000.A37:10mm
MF-LF
R1300
1/16W
1%
75
402
PLACE_NEAR=U1000.B37:10mm
402
R1302
110
1%
1/16W
MF-LF
66
105
66
105
66
105
SYNC_DATE=03/15/2012
SYNC_MASTER=D7_MLB
CPU POWER
CPU_VIDSOUT
CPU_VIDALERT_R_L
=PPVCORE_S0_CPU
=PPVAXG_S0_CPU
=PP1V8_S0_CPU_PLL
=PP1V5_S0_CPU_MEM
CPU_VIDSCLK
CPU_VIDSOUT_R
=PPVCCIO_S0_CPU
CPU_VIDSCLK_R
CPU_VIDALERT_L
SNS_CPU_VCORE_N
SNS_CPU_VCCSA
SNS_CPU_VAXG_P
=PPVCCSA_S0_CPU
=PPVCORE_S0_CPU
=PPVCCIO_S0_CPU
SNS_CPU_VCORE_P
SNS_CPU_VAXG_N
SNS_CPU_VCCIO_N
SNS_CPU_VCCIO_P
NO_TEST=TRUE
NC_CPU_VCCIO_VID
NC_CPU_VCCSA_VID
NO_TEST=TRUE
prefsb
051-9504
7.0.0
13 OF 143
13 OF 117
L3
V8
P33
W3
J8
M32
L32
AB3
AB4
C18
D14
U4
J7
J4
AJ26
A12
A13
A14
A15
J3
B16
B25
A16
A18
A24
A25
A27
A28
B15
B18
B24
B27
B28
B30
B33
B34
C15
C16
C19
C21
C22
C24
C25
C27
C28
C30
C31
C33
C34
C36
D13
D15
D16
D18
D19
D21
D22
D24
D25
D27
D28
D30
D31
D33
D34
E18
E19
E21
E22
E24
E25
E27
E28
E30
E31
E33
E34
E35
F15
A7
A11
B9
G4
L7
M13
N3
N4
R7
U7
AB8
AF8
AG33
AJ16
AJ17
AJ28
AJ32
AK15
AK17
AK19
AK23
AK30
T2
A37
C37
B37
B36
U3
A36
E16
E15
D36
D35
AA3
B31
AK21
AK27
AK29
D6
D10
E3
E4
G3
L4
N7
R3
R4
P34
Y38
Y37
AB34
AB35
AU19
AK12
AK11
AY28
AY26
AY23
AW31
AV25
AV21
AU31
AU27
AU23
AR24
AR23
AR22
AR21
AJ24
AJ23
AJ20
AJ14
AJ13
AC40
AC39
AC38
AC37
AC36
AC35
AC34
AC33
AB39
AB38
AB37
AB36
Y36
Y35
Y34
Y33
W38
W37
W36
W35
W34
W33
U40
U39
U38
U37
U36
U35
U34
U33
T40
T38
T37
T35
T34
T33
T39
T36
AV24
AV29
AV33
AR20
AB33
AB40
G25
AV39
AY37
G32
G24
G22
G21
G19
G18
F33
H31
J18
H32
J12
J15
J16
J19
J21
J22
J24
J25
J27
J28
J30
K18
K19
K21
K22
K24
K25
K27
K28
K30
L13
L14
L15
L16
L18
L19
L21
L22
L24
L25
L27
L28
L30
M14
M15
M16
M18
M22
M24
M25
M27
M28
H10
H11
H12
J10
K10
K11
L11
M10
M11
B3
F19
F18
F16
M21
M19
F34
G27
A4
H14
H15
H19
H22
H21
G31
G30
G28
G16
G15
L12
M12
H24
F32
F25
F21
F24
M30
K15
K16
H30
G33
H13
F22
F31
H18
H16
F27
F28
F30
H25
H27
H28
12
12
12
1
2
1
2
105
6
13 16 51 66
6
17 51 66
6
16
6
11 16
105
6
10 11 13 16 28 66
105
6
16
6
13 16 51 66
6
10 11 13 16 28 66
VSS_180
VSS_179
VSS_178
VSS_177
VSS_176
VSS_175
VSS_174
VSS_173
VSS_172
VSS_171
VSS_170
VSS_169
VSS_168
VSS_167
VSS_166
VSS_165
VSS_164
VSS_163
VSS_162
VSS_161
VSS_160
VSS_159
VSS_158
VSS_157
VSS_156
VSS_155
VSS_154
VSS_153
VSS_152
VSS_151
VSS_150
VSS_149
VSS_148
VSS_147
VSS_146
VSS_145
VSS_144
VSS_143
VSS_142
VSS_141
VSS_140
VSS_139
VSS_138
VSS_137
VSS_136
VSS_135
VSS_134
VSS_133
VSS_132
VSS_131
VSS_130
VSS_129
VSS_128
VSS_127
VSS_126
VSS_125
VSS_124
VSS_123
VSS_122
VSS_121
VSS_120
VSS_119
VSS_118
VSS_117
VSS_116
VSS_115
VSS_114
VSS_113
VSS_112
VSS_111
VSS_110
VSS_109
VSS_108
VSS_107
VSS_106
VSS_105
VSS_104
VSS_103
VSS_102
VSS_101
VSS_100
VSS_099
VSS_098
VSS_097
VSS_096
VSS_095
VSS_094
VSS_093
VSS_092
VSS_091
VSS_090
VSS_089
VSS_088
VSS_087
VSS_086
VSS_085
VSS_084
VSS_083
VSS_082
VSS_081
VSS_080
VSS_079
VSS_078
VSS_077
VSS_076
VSS_075
VSS_074
VSS_073
VSS_072
VSS_071
VSS_070
VSS_069
VSS_068
VSS_067
VSS_066
VSS_065
VSS_064
VSS_063
VSS_062
VSS_061
VSS_060
VSS_059
VSS_058
VSS_057
VSS_056
VSS_055
VSS_054
VSS_053
VSS_052
VSS_051
VSS_050
VSS_049
VSS_048
VSS_047
VSS_046
VSS_045
VSS_044
VSS_043
VSS_042
VSS_041
VSS_040
VSS_039
VSS_038
VSS_037
VSS_036
VSS_035
VSS_034
VSS_033
VSS_032
VSS_031
VSS_030
VSS_029
VSS_028
VSS_027
VSS_026
VSS_025
VSS_024
VSS_023
VSS_020
VSS_019
VSS_001
VSS_002
VSS_003
VSS_004
VSS_005
VSS_012
VSS_006
VSS_007
VSS_008
VSS_009
VSS_010
VSS_011
VSS_013
VSS_014
VSS_015
VSS_021
VSS_022
VSS_016
VSS_017
VSS_018
SYM 8 OF 10
VSS
VSS_360
VSS_359
VSS_358
VSS_357
VSS_356
VSS_355
VSS_354
VSS_353
VSS_352
VSS_351
VSS_350
VSS_349
VSS_348
VSS_347
VSS_346
VSS_345
VSS_344
VSS_343
VSS_342
VSS_341
VSS_340
VSS_339
VSS_338
VSS_337
VSS_336
VSS_335
VSS_334
VSS_333
VSS_332
VSS_331
VSS_330
VSS_329
VSS_328
VSS_327
VSS_326
VSS_325
VSS_324
VSS_323
VSS_322
VSS_321
VSS_320
VSS_319
VSS_318
VSS_317
VSS_316
VSS_315
VSS_314
VSS_313
VSS_312
VSS_311
VSS_310
VSS_309
VSS_308
VSS_307
VSS_306
VSS_305
VSS_304
VSS_303
VSS_302
VSS_301
VSS_300
VSS_299
VSS_298
VSS_297
VSS_296
VSS_295
VSS_294
VSS_293
VSS_292
VSS_291
VSS_290
VSS_289
VSS_288
VSS_287
VSS_286
VSS_285
VSS_284
VSS_283
VSS_282
VSS_281
VSS_280
VSS_279
VSS_278
VSS_277
VSS_276
VSS_275
VSS_274
VSS_273
VSS_272
VSS_271
VSS_270
VSS_269
VSS_268
VSS_267
VSS_266
VSS_265
VSS_264
VSS_263
VSS_262
VSS_261
VSS_260
VSS_259
VSS_258
VSS_257
VSS_256
VSS_255
VSS_254
VSS_253
VSS_252
VSS_251
VSS_250
VSS_249
VSS_248
VSS_247
VSS_246
VSS_245
VSS_244
VSS_243
VSS_242
VSS_241
VSS_240
VSS_239
VSS_238
VSS_237
VSS_236
VSS_235
VSS_234
VSS_233
VSS_232
VSS_231
VSS_230
VSS_229
VSS_228
VSS_227
VSS_226
VSS_225
VSS_224
VSS_223
VSS_222
VSS_221
VSS_220
VSS_219
VSS_218
VSS_217
VSS_216
VSS_215
VSS_214
VSS_213
VSS_212
VSS_211
VSS_210
VSS_209
VSS_208
VSS_207
VSS_206
VSS_205
VSS_204
VSS_203
VSS_202
VSS_201
VSS_196
VSS_195
VSS_194
VSS_200
VSS_199
VSS_198
VSS_197
VSS_188
VSS_193
VSS_192
VSS_191
VSS_190
VSS_189
VSS_182
VSS_187
VSS_186
VSS_181
VSS_185
VSS_184
VSS_183
SYM 9 OF 10
VSS
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
U1000
BGA-SKT-K70
OMIT_TABLE
IVY-BRIDGE
U1000
BGA-SKT-K70
OMIT_TABLE
IVY-BRIDGE
SYNC_DATE=03/15/2012
SYNC_MASTER=D7_MLB
CPU GROUNDS
prefsb
051-9504
7.0.0
14 OF 143
14 OF 117
AV10
AU8
AU6
AU4
AU34
AU26
AU15
AU1
AT9
AT8
AT7
AT6
AT5
AT40
AT4
AT39
AT38
AT37
AT36
AT35
AT34
AT33
AT32
AT31
AT30
AT3
AT29
AT28
AT27
AT25
AT2
AT17
AT16
AT15
AT13
AT12
AT10
AT1
AR5
AR36
AR30
AR27
AR19
AR18
AR17
AR14
AR11
AP5
AP40
AP4
AP37
AP36
AP30
AP27
AP25
AP22
AP17
AP14
AP11
AP1
AN9
AN8
AN7
AN6
AN5
AN36
AN35
AN34
AN33
AN32
AN31
AN30
AN27
AN24
AN22
AN19
AN17
AN14
AN11
AN10
AM5
AM40
AM4
AM39
AM38
AM37
AM36
AM30
AM3
AM27
AM25
AM23
AM21
AM2
AM17
AM14
AM11
AM1
AL5
AL36
AL30
AL27
AL24
AL19
AL17
AL14
AL11
AK9
AK8
AK7
AK6
AK5
AK40
AK4
AK37
AK36
AK35
AK34
AK33
AK32
AK31
AK28
AK22
AK16
AK14
AK13
AK10
AK1
AJ5
AJ36
AJ27
AJ25
AJ21
AJ18
AJ15
AJ12
AH8
AH5
AH40
AH39
AH38
AH37
AH36
AH33
AH3
AH2
AG36
AF7
AF6
AF5
AF40
AF37
AF36
AF34
AF1
AE36
AE33
AE3
AD40
AD39
A17
A23
A26
A29
A35
AA6
AA33
AA34
AA35
AA36
AA37
AA38
AB5
AC1
AC6
AD5
AD8
AD33
AD36
AD38
Y8
Y5
W6
V5
V40
V39
V38
V37
V36
V35
V34
V33
V2
V1
U8
T6
T5
T1
R8
R39
R37
R35
R33
P6
P5
P40
P38
P36
P2
P1
N8
M9
M6
M5
M39
M37
M35
M33
M29
M26
M23
M20
M2
M17
M1
L8
L29
L26
L23
L20
L17
L10
K6
K5
K39
K37
K35
K33
K29
K26
K23
K20
K2
K17
K14
K13
K12
K1
J32
J29
J26
J23
J20
J17
J11
H9
H6
H5
H39
H37
H35
H33
H29
H26
H23
H20
H2
H17
H1
G8
G7
G34
G29
G26
G23
G20
G17
G12
G11
F9
F6
F5
F39
F37
F35
F29
F26
F23
F20
F2
F17
F14
F13
F10
F1
E8
E7
E36
E32
E29
E26
E23
E20
E17
E12
E11
D9
D5
D4
D39
D37
D32
D29
D26
D23
D20
D2
D17
C8
C7
C35
C32
C29
C26
C23
C20
C17
C12
C11
B6
B38
B35
B32
B29
B26
B23
B17
B14
B13
B10
AY18
AY14
AY11
AY8
AY6
AY4
AY35
AW10
AW6
AW36
AW16
AW14
AW11
AV14
AV6
AV38
AV11
AV35
AV3
AV17
OUT
S
G
D
IN
D
GS
D
GS
OUT
D
GS
D
SG
D
SG
B
Y
A
OUT
IN
D
GS
OUT
D
GS
OUT
B
Y
A
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
DP_AUXIO_EN GLITCHES ON S0/S3 TRANSITIONS RDAR://11085566
D8: ISOLATION FET TO PREVENT TBT 3V3_TBTLC LEAKAGE RDAR://10885566
D7/D7I: CHECK CACTUSRIDGE POWER SEQUENCING & LEAKAGE RDAR://10739300
AP CLKREQ# ISOLATION
ISOLATION FET TO PREVENT LEAKAGE ON AP_PWR_EN AND AP_CLKREQ_L RDAR://11068662
UNUSED clock terminations for FCIM MODE
DP_AUXCH_ISOL IS ACTIVE LOW!
Inverts PCH GPIO DP_AUXCH_ISOL to drive DP_AUXIO_EN for external DP
DP_AUXIO_EN Inversion
TBT CLKREQ# ISOLATION
CFG[5:6] = Sel PCIe Cfg CFG[3]=Direct/Rev for X4 CFG[2]= Direct/Rev for x16
11 = 1x16 (default) 1 = DIR 1 = DIR
10 = 2x8 0 = REV 0 = REV
IVB PCIe Straps configuration:
00 = 1x8,2x4
TBT JTAG_TCK ISOLATION
AP PWR_EN ISOLATION
1/16W
10K
402
MF-LF
5%
R1501
10K
402
MF-LF
5%
1/16W
R1502
10K
MF-LF
5%
R1504
1/16W
402
R1509
402
5%
MF-LF
10K
1/16W
R1510
10K
MF-LF
402
5%
1/16W
5%
402
10K
MF-LF
R1511
1/16W
402
R1528
1/16W MF-LF
5%
10K
402
MF-LF
1K
5%
NOSTUFF
R1512
1/16W
PLACE_NEAR=U1000.N35:20MM
R1513
NOSTUFF
5%
402
1K
MF-LF1/16W
PLACE_NEAR=U1000.L37:20MM
PLACE_NEAR=U1000.K36:20MM
402
1K
5%
MF-LF
NOSTUFF
R1523
1/16W
PLACE_NEAR=U1000.J37:20MM
1/16W
5%
1K
402
MF-LF
R1522
5%
10K
1/16W
R1531
402
MF-LF
10K
5%
1/16W
R1534
MF-LF
402
10K
5%
1/16W
R1533
402
MF-LF
R1530
10K
5%
1/16W MF-LF
402
1/16W
10K
402
MF-LF
R1555
5%
5%
10K
R1542
1/16W MF-LF
402
402
1/16W
5%
10K
MF-LF
R1505
402
5%
R1556
1/16W
10K
MF-LF
1/16W
10K
5%
R1557
MF-LF
402
1/16W
10K
5%
MF-LF
402
R1558
5%
MF-LF
10K
1/16W
402
R1517
R1520
10K
MF-LF1/16W
402
5%
1/16W MF-LF
5%
10K
R1519
402
10K
R1518
402
MF-LF
5%
1/16W
1/16W
402
10K
MF-LF
5%
R1516
R1537
MF-LF
402
5%
1K
1/16W
R1536
1/16W
1K
5%
MF-LF
402
1K
5%
1/16W MF-LF
402
R1514
4.7K
R1529
1/16W
5%
402
MF-LF
402
1/16W
R1538
10K
MF-LF
5%
5%
R1540
10K
MF-LF1/16W
402
MF-LF
R1539
1/16W
402
5%
10K
R1541
10K
5%
MF-LF
402
1/16W
10K
5%
R1508
402
MF-LF1/16W
5%
R1535
1/16W
402
MF-LF
100K
10K
5%
1/16W
R1563
402
MF-LF
20K
5%
1/16W MF-LF
R1532
402
18
101
R1552
330
5%
402
MF-LF1/16W
PLACE_NEAR=R1805.1:3MM
SOT23-3-HF
Q1500
NTR1P02L
47
117
5%
1/16W MF-LF
402
100K
R1570
5%
402
100K
1/16W MF-LF
R1571
10K
5%
1/16W
402
MF-LF
R1551
10K
5%
1/16W
R1548
MF-LF
402
PLACE_NEAR=U1800.P33:5mm
5%
1/16W MF-LF
402
R1549
10K
5%
402
MF-LF
10K
1/16W
R1550
5%
10K
1/16W
R1547
MF-LF
402
PLACE_NEAR=U1800.R33:5mm
10K
402
R1546
MF-LF1/16W
5%
PLACE_NEAR=U1800.AF55:6MM
1/16W
5%
10K
402
PLACE_NEAR=U1800.AG56:5mm
MF-LF
R1545
10K
5%
1/16W MF-LF
402
PLACE_NEAR=U1800.BD38:5mm
R1544
10K
5%
1/16W MF-LF
R1543
402
PLACE_NEAR=U1800.BF38:5mm
5%
402
1/16W
4.7K
MF-LF
R1564
1/16W
MF-LF
5%
402
10K
R1590
CRITICAL
Q1509
VESM
SSM3K15AMFVAPE
10K
5%
MF-LF
R1591
402
1/16W
MF-LF
5%
1/16W
402
10K
R1592
SOD-VESM-HF
Q1510
SSM3K15FV
15 21
117
R1565
NOSTUFF
5%
1/16W
402
10K
MF-LF
402
MF-LF
5%
1/16W
R1526
10K
5%
402
10K
MF-LF
R1527
1/16W
R1594
MF-LF
10K
5%
1/16W
402
Q1530
SOD-VESM-HF
SSM3K15FV
SOT563
CRITICAL
SSM6N15AFE
Q1540
1/16W
MF-LF
R1561
10K
5%
402
402
MF-LF
1/16W
5%
10K
R1562
CRITICAL
Q1540
SSM6N15AFE
SOT563
R1595
1/16W
MF-LF
10K
5%
402
R1596
5%
MF-LF
402
10K
1/16W
R1597
10K
402
MF-LF
5%
1/16W
402
R1598
MF-LF1/16W
5%
NOSTUFF
0
0
1/16W
R1599
MF-LF
402
5%
NOSTUFF
402
0
NOSTUFF
5%
1/16W MF-LF
R1500
10K
5%
1/16W
MF-LF
402
R1593
U1500
SOT353
74LVC1G08GW
21 99
5%
10K
MF-LF
R1521
402
1/16W
1/16W
5%
NOSTUFF
0
MF-LF
402
R1584
SOD-523
BAT54XV2T1
D1521
36
MF-LF
1/16W
5%
402
R1583
10K
MF-LF
5%
1/16W
0
R1585
NOSTUFF
402
1/16W
5%
MF-LF
402
10K
R1586
MF-LF
R1587
5%
1/16W
402
10K
Q1550
SSM3K15FV
SOD-VESM-HF
15 21
112
R1588
MF-LF
5%
1/16W
402
10K
Q1560
SOD-VESM-HF
SSM3K15FV
15 20 99
SOT353
U1501
74LVC1G08GW
86 88
112
U1500.5:3MM
C1500
16V
0402
0.1UF
X7R-CERM
10%
U1501.5:3MM
0.1UF
0402
16V
X7R-CERM
C1501
10%
R1524
1%
402
MF-LF1/16W
2.0K
R1525
2.0K
1%
402
MF-LF1/16W
MF-LF
402
1/16W
NOSTUFF
R1554
0
5%
5%
1/16W
NOSTUFF
0
MF-LF
402
R1553
SYNC_MASTER=D8_MLB
STRAPS,PULL UPS,PULL DOWNS FOR PCH AND CPU
SYNC_DATE=03/29/2012
PCH_BLC_MCU_RESET_R
PCH_BLC_EXT_BOOT_R
=PP3V3_TBT_PCH_GPIO
PCH_CAM_EXT_BOOT_L
PCH_CAM_RESET
PCH_GPIO6
USB_EXTA_OC_L
=PP3V3_S4_AP
TBT_PWR_EN
TBT_PWR_EN_R
JTAG_TBT_TCK_ISOL
JTAG_TBT_TCK
=PP3V3_TBT_PCH_GPIO
TBT_CIO_PLUG_EVENT_ISOL
TBT_CIO_PLUG_EVENT
=PP3V3_S0_PCH_GPIO
=PP3V3_S5_PCH_STRAPS
PCH_GPIO1
DP_AUXCH_ISOL
SSD_CLKREQ_L
ENET_CLKREQ_L
TBT_PCH_CLKREQ_L
=PP3V3_TBT_PCH_GPIO
CPU_CFG<2>
CPU_CFG<6>
USB_EXTD_OC_EHCI_L
PCH_SATALED_L
=PP3V3_S0_LED_SATA
PCH_SMBALERT_L
USB_EXTC_OC_L
=PP3V3_S5_PCH_STRAPS
PCH_SPKR
SATARDRVR_EN
PEG_CLKREQ_L
SMC_RUNTIME_SCI_L
=PP3V3_S0_PCH_STRAPS
PCH_GPIO48
PM_SLP_S4_L
PM_SLP_S5_L
ENET_LOW_PWR_PCH
PCH_GPIO22
ENET_MEDIA_SENSE
WOL_EN
PCH_GPIO29
PCH_CLK14P3M_REFCLK
PCH_CLK100M_DMIN
=PP3V3_S0_PCH_GPIO
=PP3V3_S0_PCH_GPIO
=PP3V3_S0_PCH_GPIO
JTAG_TBT_TDO_ISOL
JTAG_TBT_TMS_ISOL
=PP3V3_TBT_PCH_GPIO
JTAG_TBT_TDO
JTAG_TBT_TMS
JTAG_TBT_TDI_ISOL
TBT_PCH_CLKREQ_L
TBT_CLKREQ_L
HDA_SYNC
ITPXDP_CLK100M_N ITPCPU_CLK100M_N
ITPXDP_CLK100M_P ITPCPU_CLK100M_P
TBT_PWR_REQ_L
BT_PWR_RST_L
AP_PWR_EN_ISO
AP_PWR_EN
USB_EXTB_OC_EHCI_L
=PP3V3_S4_AP
=PP3V3_S5_PCH_STRAPS
SMC_WAKE_SCI_L
PCH_SUSWARN_L
PCH_GPIO72
PM_PWRBTN_L
TBT_SW_RESET_R_L
AP_CLKREQ_L
AP_PWR_EN
AP_CLKREQ_L
TBT_GO2SX_BIDIR
=PP3V3_S0_PCH_STRAPS
=PP3V3_S5_PCH_STRAPS
AP_CLKREQ_L_ISO
SPI_DESCRIPTOR_OVERRIDE_L
DP_AUXCH_ISOL
PM_PCH_PWROK
DP_AUXIO_EN
SPI_DESCRIPTOR_OVERRIDE_R
=PP3V3_S0_PCH_STRAPS
PM_SLP_S3_L
PCH_CLKIN_GND0
PCH_CLK100M_SATAP
PCH_CLK96M_DOTP
PCH_CLK96M_DOTN
PCH_CLK100M_SATAN
HDA_SDOUT_R
SDCONN_STATE_CHANGE
USB_EXTD_OC_L
=PP3V3_TBT_PCH_GPIO
=PP3V3_TBTLC_RTR
PCH_CLK100M_DMIP
PCH_CLKIN_GND1
CPU_CFG<5>
CPU_CFG<3>
USB_EXTB_OC_L
JTAG_TBT_TDI
=PP3V3_S0_PCH_GPIO
DP_AUXCH_ISOL_EN
=PP3V3_S0_PCH_GPIO
prefsb
051-9504
7.0.0
15 OF 143
15 OF 117
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
2
1
3
12
12
12
12
12
12
12
12
12
12
12
12
1
2
1
2
3
12
1
2
1
2
3
12
12
12
1
2
1
2
3
3
4
5
1
2
1
2
6
1
2
1
2
1
2
1
2
12
12
12
1
2
4
3
1
2
5
1
2
12
AK
1
2
12
1
2
1
2
1
2
3
1
2
1
2
3
4
3
1
2
5
2
1
2
1
12
12
12
12
21
114
21
114
6
15
21
21
114
21
20 45 99
6
15 35
26 36
117
36 99
21 99
6
15
6
15 19 20 38
6
15
21
15 18 99
18
117
18 40
113
15 21
117
6
15
10 25 99
10 25 99
20 99
18 44
6
44
18
114
20 46 99
6
15
18
18 99
18 75
114
21 47
117
6
15
21
19 47 64
115
19 47 64
115
21 26 99
21
18 39
111
21 40
117
19
18
18
6
15 19 20 38
6
15 19 20 38
6
15 19 20 38
36
114
36
114
6
15
21
114
18
114
36
114
38
117
18 56
101
18 25 99 11 99
18 25 99 11 99
20 36
117
20 35
112
35
112
15 20 99
20 99
6
15 35
6
15
21 47
117
19
114
19
19 25 47
115
21
15 21
112
21 36
6
15
6
15
35
112
15 18 99
19 26 35 43 65 89
115
101
6
15
5
19 28 40 47 48 64
115
18
18
18
18
18
20 41 99
20 46 99
6
15
6
36 37 38 50
18
18
10 25 99
10 25 99
20 45 99
21
114
6
15 19 20 38
99
6
15 19 20 38
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
PLL (CPU VCCSFR) DECOUPLING
Memory (CPU VCCDDR) DECOUPLING
PLACEMENT_NOTE (C1660-C1665):
PLACEMENT_NOTE (C1650-C1657):
CPU VCCIO DECOUPLING
8X 22UF 0805, 6X 10UF 0805
10x 10UF and 10x 1UF CAPACITORS
BULK CAPS ON VTT REG PAGE 77
INTEL RECOMMENDATION 9X22UF 0805,16X 0805 placeholders
PLACEMENT_NOTE (C1600-C1613):
Bulk decoupling is on VCCSA reg page 75
2x 10uF 0603. INTEL RECOMMENDATION 2X 10uF 0805
CPU VCCSA DECOUPLING
BULK CAPS ON CPU VREG PAGE 74
BULK CAPS ON CPU VREG PAGE 72
2x 47uF, 1x 22uF 0805, 1x 10uF 0603, 1x 4.7uF 0603, 1x 2.2uF 0402, 2x 1uF 0402. INTEL RECOMMENDATION 1x 10uF 0805
CPU VCORE DECOUPLING
14x 22UF,0805 INTEL RECOMMENDATION 18X 22UF 0805 (14 Inside cavity and 4 North of processor)
REPLACED WITH 603 PER RDAR://10700439
10V
10%
402
X5R
1UF
C1693
6.3V
10%
402
X5R
2.2UF
C1692 C1691
603
X5R-CERM
6.3V
10%
4.7UF
10V
20%
603
X5R
10UF
Place inside socket cavity
C1629
10V
20%
603
X5R
10UF
Place inside socket cavity
C1628
10V
20%
603
X5R
10UF
Place inside socket cavity
C1627
10V
20%
603
X5R
10UF
Place inside socket cavity
C1626
10V
20%
603
X5R
10UF
Place inside socket cavity
C1624
10V
20%
603
X5R
10UF
Place inside socket cavity
C1623
10V
20%
603
X5R
10UF
Place inside socket cavity
C1622
10V
20%
603
X5R
Place inside socket cavity
10UF
C1621
10V
20%
603
X5R
10UF
Place inside socket cavity
C1620
16V
10%
402
X5R
1UF
Place inside socket cavity
C1630
10V
20%
603
X5R
10UF
Place inside socket cavity
C1625
16V
10%
X5R
1UF
Place inside socket cavity
C1631
402
16V
10%
X5R
Place inside socket cavity
C1632
402
1UF
16V
Place inside socket cavity
C1633
402
X5R
10%
1UF
16V
10%
402
X5R
1UF
Place inside socket cavity
C1634
16V
10%
402
X5R
1UF
Place inside socket cavity
C1635
16V
10%
402
X5R
1UF
Place inside socket cavity
C1636
16V
10%
402
X5R
1UF
Place inside socket cavity
C1637
16V
10%
402
X5R
1UF
Place inside socket cavity
C1638
16V
10%
402
X5R
1UF
Place inside socket cavity
C1639
330UF-0.0045OHM
CRITICAL
C1670
20%
CASE-D2-SM
POLY
2V
6.3V
X5R
603
10UF
20%
C1695
0201
X5R
20%
1UF
6.3V
C1682
0201
6.3V
20%
X5R
1UF
C1683
6.3V
20%
0201
X5R
1UF
C1684
6.3V
20%
0201
X5R
1UF
C1685
1UF
6.3V
20%
0201
X5R
C1686
CRITICAL
CASE-D2-SM
330UF-0.0045OHM
NOSTUFF
POLY
2V
20%
C1687
6.3V
603
10uF
X5R
20%
C1667C1666
X5R
603
6.3V
20%
10uF
0603
22UF
20%
6.3V
X5R-CERM2
C1600 C1601
22UF
0603
20%
6.3V
X5R-CERM2 X5R-CERM2
0603
C1602
22UF
20%
6.3V
0603
22UF
20%
6.3V
X5R-CERM2
C1603
0603
22UF
20%
6.3V
X5R-CERM2
C1604 C1605
0603
X5R-CERM2
6.3V
20%
22UF
0603
C1606
22UF
20%
6.3V
X5R-CERM2
C1607
0603
22UF
20%
6.3V
X5R-CERM2
C1608
0603
22UF
20%
6.3V
X5R-CERM2
C1609
0603
22UF
20%
6.3V
X5R-CERM2
X5R-CERM2
6.3V
20%
22UF
0603
C1610 C1611
X5R-CERM2
6.3V
20%
22UF
0603
C1612
6.3V
X5R-CERM2
20%
0603
22UF
X5R-CERM2
6.3V
20%
22UF
0603
C1613
22UF
20%
6.3V
X5R-CERM2
C1650
0603 0603
C1651
X5R-CERM2
6.3V
20%
22UF
6.3V
0603
C1652
X5R-CERM2
20%
22UF
C1653
0603
22UF
20%
6.3V
X5R-CERM2 X5R-CERM2
0603
C1654
6.3V
20%
22UF
0603
C1655
X5R-CERM2
6.3V
20%
22UF
0603
C1656
X5R-CERM2
6.3V
20%
22UF
0603
C1657
X5R-CERM2
6.3V
20%
22UF
X5R-CERM2
6.3V
20%
22UF
0603
C1676 C1677
22UF
0603
20%
6.3V
X5R-CERM2 X5R-CERM2
C1678
0603
22UF
20%
6.3V
C1679
0603
22UF
20%
6.3V
X5R-CERM2
C1680
22UF
20%
6.3V
X5R-CERM2
0603
X5R-CERM2
6.3V
20%
22UF
0603
C1681
6.3V
C1690
0603
22UF
20%
X5R-CERM2
X5R
6.3V
20%
0805
47UF
C1696
X5R
20%
6.3V
0805
47UF
C1697
Place at edge of socket.
10uF
X5R
603
20%
6.3V
C1665
Place at edge of socket.
10uF
X5R
603
20%
6.3V
C1664
6.3V
10uF
C1663
20%
603
X5R
Place at edge of socket.
C1662
10uF
X5R
603
6.3V
Place at edge of socket.
20%
C1661
X5R
6.3V
20%
603
10uF
Place at edge of socket.
C1660
Place at edge of socket.
10uF
6.3V
20%
603
X5R
10V
10%
402
X5R
1UF
C1694
SYNC_MASTER=D7_MLB
CPU NON-GFX DECOUPLING
SYNC_DATE=12/20/2011
=PPVCORE_S0_CPU
=PP1V8_S0_CPU_PLL
=PPVCCIO_S0_CPU
=PPVCCSA_S0_CPU
=PP1V5_S0_CPU_MEM
=PPVCORE_S0_CPU
prefsb
051-9504
7.0.0
16 OF 143
16 OF 117
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
2
1
2
1
2
1
2
1
2
1
2
1
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
6
13 16
51 66
6
13
6
10 11 13
28 66
6
13
6
11 13
6
13 16 51 66
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
PLACEMENT_NOTE (C1704-C1709):
AXG BULK CAPS
INTEL RECOMMENDATION 4X22UF 0805,3X 4.7UF
VAXG DECOUPLING
R1730
0
MF-LF
402
5%
1/16W
R1740
1/16W
5%
402
MF-LF
0
C1710
4.7UF
Place inside socket cavity
X5R-CERM
603
10%
6.3V
C1711
4.7UF
X5R-CERM
Place inside socket cavity
603
10%
6.3V
C1712
Place inside socket cavity
10%
603
X5R-CERM
6.3V
4.7UF
R1720
402
0
MF-LF
1/16W
5%
603
C1795
X5R
20%
10UF
10V
603
C1794
10V
10UF
20%
X5R
CASE-D2-SM
CRITICAL
C1793
POLY
20%
2V
330UF-0.006OHM
CASE-D2-SM
2V
C1792
330UF-0.006OHM
20%
POLY
CRITICAL
CASE-D2-SM
C1791
20%
2V
POLY
330UF-0.006OHM
CRITICALCRITICAL
2V
C1790
CASE-D2-SM
POLY
20%
330UF-0.006OHM
CASE-D2-SM
330UF-0.006OHM
C1789
POLY
20%
2V
CRITICAL
330UF-0.006OHM
CASE-D2-SM
C1788
POLY
20%
2V
CRITICAL
0603
C1704
X5R-CERM2
6.3V
20%
22UF
0603
C1705
X5R-CERM2
6.3V
20%
22UF
0603
C1706
X5R-CERM2
6.3V
20%
22UF
0603
C1707
X5R-CERM2
6.3V
20%
22UF
0603
C1708
X5R-CERM2
6.3V
20%
22UF
0603
C1709
X5R-CERM2
6.3V
20%
22UF
1UF
6.3V
CERM
402
10%
C1731
PLACE C1731 AT BALL U1800.AB1
1UF
10%
6.3V
CERM
402
C1741
PLACE C1741 AT BALL U1800.AC2
SYNC_DATE=01/26/2012
GFX DECOUPLING & PCH PWR ALIAS
SYNC_MASTER=D8_KOSECOFF
=PP1V05_S0_PCH_VCC_ADPLL
=PP3V3_S0_PCH_VCC_ADAC
PPCPUAXG_S0_REG
=PPVAXG_S0_CPU
MAKE_BASE=TRUE
PP1V05_S0_PCH_VCCADPLLB_F
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.05V
VOLTAGE=1.05V
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.4MM
MAKE_BASE=TRUE
PP1V05_S0_PCH_VCCADPLLA_F
PP3V3_S0_PCH_VCCA_DAC_F
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
prefsb
051-9504
7.0.0
17 OF 143
17 OF 117
12
12
2
1
2
1
2
1
12
2
1
2
11
2
1
2
1
2
1
2
1
2
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
6
6
6
68
6
13 51 66
22
115
22
115
22
115
IN
IN
OUT
OUT
OUT
IN
BI
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
BI
OUT
BI
IN
IN
OUT
OUT
OUT
OUT
IN
OUT
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
BI
BI
BI
BI
OUT
SATA3COMPI
SATA3RCOMP0
SATA3RBIAS
SATA3RXP
HDA_SYNC
INTRUDER*
LDRQ1*/GPIO23
SATA1TXN
SATA3RXN
SATA1RXN
SATA1TXP
SATA0RXN
SERIRQ
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
FWH4/LFRAME*
SATA1RXP
SATA2TXN
SATA2TXP
SATA3TXN
SATA3TXP
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
SATA5RXN
SATA5TXN
SATA5TXP
SATAICOMPO
SATAICOMPI
SATALED*
SATA0GP/GPIO21
SATA1GP/GPIO19
L_BKLTCTL
HDA_RST*
SPKR
HDA_SDIN1
HDA_SDIN3
HDA_SDIN2
HDA_SDO
GPIO33
GPIO13
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
SPI_CS0*
SPI_MOSI
SPI_MISO
RTCX1
RTCX2
SATA0TXP
SATA0TXN
SATA2RXN
SATA2RXP
SATA5RXP
SATA0RXP
LDRQ0*
L_BKLTEN
L_VDD_EN
FWH0/LAD0
INTVRMEN
SPI_CS1*
HDA_SDIN0
SRTCRST*
SPI_CLK
RTCRST*
HDA_BCLK
(1 OF 10)
LPC
RTC
IHDA
SATA
JTAG
SPI
CLKIN_DMI_P
PETN2
CLKOUT_PEG_A_N
CL_RST1*
CLKIN_DMI_N
PERP3
CLKOUT_PEG_B_N
CLKIN_DOT_96P
CL_DATA1
CL_CLK1
CLKIN_GND1_P
CLKIN_GND1_N
CLKIN_GND0_P
CLKOUT_ITPXDP_N
CLKOUTFLEX3/GPIO67
CLKOUTFLEX2/GPIO66
CLKOUTFLEX1/GPIO65
CLKOUTFLEX0/GPIO64
XCLK_RCOMP
XTAL25_OUT
XTAL25_IN
CLKIN_PCILOOPBACK
REFCLK14IN
CLKIN_SATA_P
CLKIN_DOT_96N
CLKOUT_DP_N
CLKOUT_DP_P
CLKOUT_DMI_P
CLKOUT_DMI_N
CLKOUT_PEG_A_P
SMBCLK
SMBALERT*/GPIO11
SML1DATA/GPIO75
SML1CLK/GPIO58
SML1ALERT*/PCHHOT*/GPIO74
SML0DATA
SML0ALERT*/GPIO60
SML0CLK
SMBDATA
PERN3
PETP2
CLKOUT_PCIE5P
PCIECLKRQ5*/GPIO44
CLKOUT_PCIE4P
CLKOUT_PCIE5N
CLKOUT_PCIE3P
CLKOUT_PCIE4N
CLKOUT_PCIE3N
PCIECLKRQ2*/GPIO20/SMI*
CLKOUT_PCIE2P
CLKOUT_PCIE2N
CLKOUT_PCIE1N
CLKOUT_PCIE1P
CLKOUT_PCIE0N
CLKOUT_PCIE0P
PETP8
PERP8
PETN8
PETP7
PERN8
PETN7
PERP7
PERN7
PETN6
PETP6
PERP5
PETP4
PERN5
PETN4
PERP4
PETP3
PERN4
PETN3
PERP2
CLKIN_SATA_N
CLKIN_GND0_N
CLKOUT_ITPXDP_P
CLKOUT_PEG_B_P
PETN5
PETP5
PERN6
PERP6
PERP1
PERN1
PETN1
PETP1
PERN2
FLEX
CLOCK
PCI-E*
PEG
FROM CLK BUFFER
SMBUS
(2 0F 10)
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
DOES THIS NEED LENGTH MATCH???
TIE THEM TOGETHER VERY CLOSE TO PINS. PLACE THE RESISTOR LESS THAN 200MILS FROM THE PINS
PLACE THIS RESISTOR PACK CLOSE TO PCH (MIN 500MIL)
26
101
56
101
49
101
49
101
49
101
49
101
47 49
114
44
100
44
100
44
100
44
100
44
100
44
100
44
100
44
100
8
8
8
8
39 98
39 98
8
8
8
8
39 98
39 98
8
8
35 98
35 98
36 98
36 98
15 75
114
11 99
11 99
75 98
75 98
8
8
15
15
15
15
15
15
15
26
101
26
101
26
101
50
117
50
117
50
116
50
116
35 98
35 98
35 98
35 98
R1830
PLACE_NEAR=U1800.AJ53:2mm
37.4
MF-LF
1%
402
1/16W
R1820
MF-LF
402
5%
1/16W
10K
39 98
39 98
R1890
1/16W
PLACE_NEAR=U1800.AL2:2mm
MF-LF
402
1%
90.9
18
114
50
117
50
117
8
8
36 98
36 98
36 98
36 98
36 98
36 98
36 98
36 98
36 98
36 98
36 98
36 98
36 98
36 98
36 98
36 98
R1832
PLACE_NEAR=U1800.AC52:2mm
1/16W
750
MF-LF
1%
402
R1831
49.9
1%
1/16W
402
MF-LF
PLACE_NEAR=U1800.AE52:2mm
8
8
R1860
5%
402
MF-LF
33
1/16W
47 49
101
47 49
101
R1861
1/16W
33
5%
402
MF-LF
47 49
101
R1862
5%
MF-LF
402
33
1/16W
47 49
101
R1863
1/16W
33
5%
402
MF-LF
47 49
101
U1800
PANTHER-POINT
OMIT_TABLE
FCBGA
U1800
PANTHER-POINT
FCBGA
OMIT_TABLE
R1864
MF-LF
33
5%
402
1/16W
MF-LF
R1803
20K
1/16W
5%
402402
5%
MF-LF
20K
R1802
1/16W
C1803
1UF
X5R
10V
402
10%
C1802
1UF
10V
10%
402
X5R
R1801
1M
1/16W
MF-LF
402
5%
402
R1800
MF-LF
5%
1/16W
390K
45
46
56
101
56
101
15 56
101
56
101
R1805
33
1/16W
SM-LF
5%
5%
402
1/16W
MF-LF
0
R1851
NOSTUFF
MF-LF
1/16W
402
5%
0
R1852
15 99
15 99
R1841
SIGNAL_MODEL=EMPTY
0
5% MF
201
1/20W
R1842
SIGNAL_MODEL=EMPTY
1/20W
0
5%
201
MF
8
8
SYNC_MASTER=D8_MLB
PCH SATA/PCIE/CLK/LPC/SPI
SYNC_DATE=N/A
DMI_MIDBUS_CLK100M_N
ITPXDP_CLK100M_N
TP_PCH_GPIO65_CLKOUTFLEX1
TP_PCH_GPIO64_CLKOUTFLEX0
PCH_CLKIN_GND1
TP_PCH_GPIO67_CLKOUTFLEX3
TP_PCH_GPIO66_CLKOUTFLEX2
TP_PCH_CL_CLK1
TP_PCH_CL_DATA1
PCH_CLK100M_SATAP
TP_PCIE2_R2D_CP
TP_PCIE1_D2RN
TP_PCIE1_D2RP
TP_PCIE1_R2D_CN
TP_PCIE1_R2D_CP
TP_PCIE2_R2D_CN
TP_PCIE2_D2RN
TP_PCIE2_D2RP
TP_PCIE_CLK100M_PE0N
TP_PCIE_CLK100M_PE0P
PCIE_AP_D2R_P
PCIE_CLK100M_AP_N
TP_SATA_D_R2D_CP
TP_SATA_E_D2RN
TP_SATA_E_D2RP
TP_SATA_E_R2D_CN
XDP_PCH_TDI
TP_SATA_C_R2D_CP
TP_SATA_C_D2RP
TP_SATA_C_D2RN
SATA_SSD_R2D_N
SATA_SSD_R2D_P
TP_SATA_C_R2D_CN
PCIE_CLK100M_TBT_N
PEG_CLKREQ_L
PCIE_TBT_R2D_C_P<3>
PCIE_ENET_D2R_P
HDA_RST_R_L
HDA_SDIN0
TP_HDA_SDIN3
PCIE_TBT_R2D_C_N<2>
PCIE_TBT_D2R_P<2>
PCIE_TBT_D2R_N<2>
TP_PCH_CLKOUT_DPN
DMI_CLK100M_CPU_N
XDP_PCH_TMS
HDA_SYNC_R
PCH_SPKR
TP_HDA_SDIN2
ENET_MEDIA_SENSE
TP_PCH_CLKOUT_DPP
XDP_PCH_TCK
HDA_SDOUT_R
PCH_CLK14P3M_REFCLK
=PP1V05_S0_PCH
SML_PCH_0_CLK
DMI_CLK100M_CPU_P
PCH_CLK100M_DMIN
DP_AUXCH_ISOL
DP_AUXCH_ISOL_R
SATARDRVR_EN_R
TP_SATA_F_R2D_CN
TP_SATA_F_D2RP
TP_PCH_L_VDD_EN
LPC_AD<1>
SPI_MOSI_R
PCH_SATA3COMP
HDA_BIT_CLK_R
HDA_SDOUT_R
SATA_SSD_D2R_P
SATA_HDD_R2D_C_N
SATA_HDD_D2R_P
PCH_INTRUDER_L
TP_PCH_CL_RST1
PCH_CLK96M_DOTN
SML_PCH_1_DATA
TP_SATA_F_D2RN
TP_PCH_L_BKLTEN
TP_PCH_L_BKLTCTL
=PP3V3_G3_PCH
PCIE_TBT_D2R_P<0>
PCIE_TBT_R2D_C_P<1>
PCH_CLK96M_DOTP
PCH_CLK100M_SATAN
HDA_SYNC_R
HDA_SYNC
HDA_RST_L
PCH_CLK100M_DMIP
PCIE_AP_R2D_C_N
PCIE_AP_R2D_C_P
TP_LPC_DREQ0_L
TBT_PWR_EN_PCH
LPC_SERIRQ
SATA_SSD_D2R_N
PCH_CLK32K_RTCX1
SSD_CLKREQ_L
ENET_CLKREQ_L
TP_HDA_SDIN1
HDA_RST_R_L
HDA_BIT_CLK
HDA_SDOUT
SATA_HDD_R2D_C_P
SATA_HDD_D2R_N
=PP3V3_S0_PCH
PCH_CLK32K_RTCX2
LPC_FRAME_L
LFRAME_L
LPC_AD<2>
LPC_R_AD<2>
LPC_AD<0>
LPC_R_AD<0>
LPC_R_AD<1>
LPC_AD<3>
LPC_R_AD<3>
SPI_MISO
HDA_BIT_CLK_R
RTC_RESET_L
PCH_SRTCRST_L
PCH_INTVRMEN
JTAG_TBT_TMS
TP_SATA_D_R2D_CN
TP_SATA_D_D2RN
PCH_SATA3RBIAS
PCH_SATAICOMP
PCIE_TBT_D2R_N<0>
PCIE_CLK100M_TBT_P
USB_EXTB_SEL_XHCI
SML_PCH_0_DATA
USB_EXTD_SEL_XHCI
SML_PCH_1_CLK
PCH_CLK33M_PCIIN
PCH_CLK25M_XTALOUT
PCH_CLKIN_GND0
=PP1V05_S0_PCH_VCCIO_PCIE
SPI_CS0_R_L
PEG_CLK100M_P
PCIE_ENET_R2D_C_P
ITPXDP_CLK100M_P
PCIE_TBT_R2D_C_P<2>
PCIE_TBT_D2R_P<1>
PCIE_TBT_R2D_C_N<0>
PCIE_TBT_R2D_C_P<0>
PCIE_CLK100M_AP_P
PCIE_TBT_R2D_C_N<3>
PCIE_TBT_D2R_P<3>
PCIE_TBT_D2R_N<3>
SMBUS_PCH_DATA
SMBUS_PCH_CLK
PCH_SMBALERT_L
PCIE_ENET_D2R_N
PCIE_ENET_R2D_C_N
SATARDRVR_EN
PCH_CLK25M_XTALIN
TP_SATA_D_D2RP
TP_SATA_E_R2D_CP
TP_SATA_F_R2D_CP
PCH_SATALED_L
=PP1V05_S0_PCH_VCCIO_SATA
PCIE_CLK100M_ENET_P
PCIE_CLK100M_ENET_N
PCIE_CLKREQ5_GPIO44_L
PCIE_AP_D2R_N
PCIE_TBT_D2R_N<1>
PCIE_TBT_R2D_C_N<1>
PEG_CLK100M_N
DMI_MIDBUS_CLK100M_P
TP_PCIE_CLK100M_PE4N
TP_PCIE_CLK100M_PE4P
TP_PCIE_CLK100M_PE5P
TP_PCIE_CLK100M_PE5N
PCH_INTVRMEN
PCH_INTRUDER_L
PCH_SRTCRST_L
RTC_RESET_L
NO_TEST=TRUE
NC_SPI_CS1_L
SPI_CLK_R
PCH_XCLK_RCOMP
XDP_PCH_TDO
PCIE_CLKREQ5_GPIO44_L
prefsb
051-9504
7.0.0
18 OF 143
18 OF 117
1
2
1
2
1
2
1
2
1
2
12
12
12
12
AE54
AE52
AC52
AN44
BP23
BM38 BA20
AG49
AN46
AA53
AG47
AC56
AV52
BJ17
BJ20
BG20
BG17
AA56
AL56
AL53
AN56
AM55
AN49
AN50
AT50
AT49
AT46
AV50
AV49
AJ53
AJ55
BF57
BC54
AY52
AG12
BC22
BE56
BF22
BJ22
BK22
BT23
BC25
BA25
BA43
BC50
BC52
BF47
AT57
AU53
AT55
BR39
BN39
AE44
AE46
AL50
AL49
AT44
AB55
BK17
AG18
AG17
BK15
BN41
AR56
BD22
BN37
AR54
BT41
BU22
R33
C22
AG8
BF49
P33
J17
AE12
BF38
BF50
BA50
P27
R27
V52
R52
BA2
AW5
BA5
AT9
AL2
AJ5
AJ3
BD15
AN8
AG56
BD38
N56
M55
R31
P31
AG9
BT47
BN49
BK46
BJ46
BR46
BM50
BU49
BT51
BR49
H17
A22
AG2
BL54
Y8
AF3
AB8
Y9
AB9
AV43
AB14
AB12
AA5
W5
AE6
AC6
D13
J10
B13
F13
H10
F15
H12
J12
A16
B15
M15
E17
N15
F18
M17
B21
P17
E21
R20
AF55
W53
N52
AE11
B17
C16
J15
L15
L20
J20
F25
F23
P20
12
1
2
1
2
2
1
2
1
121
2
1
2
3
4
8
7
6
5
12
12
12
12
15 25 99
8
8
15
8
8
8
8
8
8
8
8
25 99
8
8
8
8
18
101
8
25 99
18
101
15
8
15 39
111
25 99
15 18
101
6
25
99
25
99
8
8
8
100
18
101
15 18
101
18
8
8
8
8
6
19
18
101
8
26
117
15
117
15 40
113
8
18
101
6
21 24
101
101
101
101
101
18
101
18 26 48
116
18
114
18
15
114
8
8
100
100
8
15
6
19 22 24
15 25 99
15
114
8
8
8
15 44
6
22 24
18
18
18
114
18 26 48
116
101
25 99
18
114
IN
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
OUT
OUT
INIT3_3V*
GPIO32
DMI2TXP
PWRBTN*
RSMRST*
SYS_RESET*
DMI3RXN
DMI2RXN
DMI2RXP
DMI3RXP
DMI_ZCOMP
SUSACK*
SLP_SUS*
DSWVRMEN
DF_TVS
SLP_LAN*/GPIO29
PMSYNCH
SLP_A*
SLP_S3*
SLP_S4*
SUSCLK/GPIO62
SUS_STAT*/GPIO61
FDI_LSYNC0
FDI_FSYNC1
FDI_INT
FDI_RXP7
FDI_RXP6
FDI_RXP5
FDI_RXP4
FDI_RXP3
FDI_RXP1
FDI_RXN7
FDI_RXN6
FDI_RXN5
FDI_RXN4
FDI_RXN3
FDI_RXN2
FDI_RXN1
FDI_RXN0
RI*
SUSWARN*/GPIO30
PWROK
SYS_PWROK
DMI_IRCOMP
DMI2RBIAS
DMI1TXN
DMI0TXN
DMI1RXP
DMI0RXP
FDI_RXP0
FDI_LSYNC1
DMI0RXN
FDI_RXP2
DMI1RXN
FDI_FSYNC0
APWROK
DMI2TXN
DMI3TXN
DMI0TXP
DMI1TXP
GPIO31
GPIO72
DMI3TXP
SLP_S5*/GPIO63
WAKE*
DPWROK
DRAMPWROK
DMI
FDI
(3 OF 10)
SYSTEM POWER
MANAGEMENT
DDPB_AUXN
DDPB_AUXP
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_3N
DDPB_3P
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DDPC_0N
DDPD_CTRLCLK
DDPD_CTRLDATA
DDPD_HPD
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_3P
CRT_BLUE
CRT_GREEN
CRT_RED
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_VSYNC
DAC_IREF
CRT_IRTN
SDVO_TVCLKINN
SDVO_TVCLKINP
SDVO_STALLN
SDVO_STALLP
SDVO_INTN
SDVO_INTP
SDVO_CTRLCLK
SDVO_CTRLDATA
DDPB_HPD
DDPB_0N
DDPB_2N
DDPB_2P
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
DDPD_AUXN
DDPD_AUXP
DDPD_2P
DDPD_3N
RESERVED
(4 OF 10)
CRT
DIGITAL DISPLAY INTERFACE
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
PLACE CLOSE TO U1800 PIN
SHORT THESE TWO PINS VERY NEAR THE PINS
PLACE THE RESISTOR VERY CLOSE TO COMMON POINT
KEEPING TP, IF NEED TO USE IT LATER
10 99
8
8
8
8
8
PLACE_NEAR=U1800.E31:5MM
R1900
1/16W
1%
402
MF-LF
49.9
19 35 40
114
48
101
15 47 64
115
15 47 64
115
5
15 28 40 47 48 64
115
11 28 99
65
115
15 25 47
115
65
115
15 26 35 43 65 89
115
48 65
115
25 26 47
115
10 99
10 99
10 99
10 99
10 99
10 99
10 99
10 99
10 99
10 99
10 99
10 99
10 99
10 99
10 99
R1905
10K
402
MF-LF
1/16W
5%
11 99
26 47 49
114
R1925
MF-LF
1K
1%
1/16W
402
PLACE_NEAR=U1800.AT3:3mm
R1951
402
1K
5%
1/16W
MF-LF
R1909
402
MF-LF
1/16W
10K
5%
R1915
MF-LF
1/16W
402
5%
390K
PLACE_NEAR=U1800.A32:5MM
R1920
750
1%
1/16W
402
MF-LF
R1981
1/16W
MF-LF
402
2.2K
5%
R1980
402
MF-LF
1/16W
5%
4.7K
U1800
FCBGA
PANTHER-POINT
OMIT_TABLE
U1800
FCBGA
PANTHER-POINT
OMIT_TABLE
R1999
1/16W
MF-LF
402
10K
5%
R1998
10K
MF-LF
402
5%
1/16W
SYNC_DATE=03/15/2012
SYNC_MASTER=D7_MLB
PCH DMI/FDI/GRAPHICS
PCH_RI_L
PCH_DMI2RBIAS
CPU_PROC_SEL
PCIE_WAKE_L
MAKE_BASE=TRUE
PM_RSMRST_PCH_L
PCH_SUSWARN_L
PCH_GPIO31_ACPRESENT
PCH_DF_TVS
PM_SLP_S4_L
PCH_GPIO29
PCH_DSWVRMEN
PCH_FDI_FSYNC<0>
DMI_N2S_N<2>
PCH_GPIO32
LPC_PWRDWN_L
PCIE_WAKE_L
PCH_FDI_LSYNC<1>
DP_IG_D_CTRL_DATA
TP_PCH_RESERVE_6
TP_PCH_RESERVE_14
DP_IG_D_CTRL_CLK
TP_PCH_RESERVE_11
TP_PCH_RESERVE_10
TP_PCH_RESERVE_9
DP_IG_B_MLN<2>
=PP3V3_G3_PCH
TP_PM_SLP_A_L
DP_IG_C_MLP<3>
DP_IG_B_MLP<3>
PCH_DSWVRMEN
PCH_DF_TVS
TP_PCH_SUSACK_L
=PP3V3_S5_PCH
DMI_S2N_P<0>
PM_PCH_APWROK
=PP1V05_S0_PCH_VCCIO_PCIE
PM_PCH_PWROK
PM_MEM_PWRGD
PM_SYSRST_L
DMI_S2N_P<3>
PM_SLP_S5_L
DMI_S2N_N<3>
DMI_S2N_N<2>
DMI_N2S_N<1>
DMI_N2S_N<0>
DMI_N2S_P<0>
DMI_N2S_P<1>
DMI_S2N_N<1>
PCH_FDI_RX_N<0>
PM_SLP_S3_L
TP_PCH_SLP_SUS_L
DMI_N2S_P<3>
DMI_N2S_N<3>
DMI_S2N_P<2>
=PP1V8_S0_PCH
DP_IG_D_MLN<3>
DP_IG_D_MLP<2>
DP_IG_D_AUXP
DP_IG_D_AUXN
DP_IG_C_MLN<3>
DP_IG_C_MLP<2>
DP_IG_C_MLN<2>
DP_IG_C_MLP<1>
DP_IG_C_MLN<1>
DP_IG_C_MLP<0>
DP_IG_B_MLP<2>
DP_IG_B_MLN<0>
DP_IG_B_DDC_DATA
DP_IG_B_DDC_CLK
TP_SDVO_INTP
TP_SDVO_INTN
TP_SDVO_STALLP
TP_SDVO_STALLN
TP_SDVO_TVCLKINP
TP_SDVO_TVCLKINN
DP_IG_D_MLP<3>
DP_IG_D_MLN<2>
DP_IG_D_MLP<1>
DP_IG_D_MLN<1>
DP_IG_D_MLP<0>
DP_IG_D_MLN<0>
DP_IG_D_HPD
DP_IG_C_MLN<0>
DP_IG_C_HPD
DP_IG_C_AUX_P
DP_IG_C_AUX_N
DP_IG_C_CTRL_DATA
DP_IG_C_CTRL_CLK
DP_IG_B_MLP<1>
DP_IG_B_AUX_P
DP_IG_B_MLP<0>
DP_IG_B_MLN<3>
DP_IG_B_MLN<1>
PM_PCH_SYS_PWROK
PCH_DMI_COMP
DMI_S2N_P<1>
DP_IG_B_HPD
DP_IG_B_AUX_N
DMI_N2S_P<2>
DMI_S2N_N<0>
TP_PCH_RESERVE_7
TP_PCH_RESERVE_5
TP_PCH_RESERVE_4
TP_PCH_RESERVE_3
TP_PCH_RESERVE_1
TP_PCH_RESERVE_2
TP_PCH_RESERVE_8
TP_PCH_RESERVE_12
TP_PCH_RESERVE_15
TP_PCH_RESERVE_16
TP_PCH_RESERVE_17
TP_PCH_RESERVE_0
TP_PCH_RESERVE_13
TP_PCH_RESERVE_20
TP_PCH_RESERVE_21
TP_PCH_RESERVE_19
TP_PCH_RESERVE_18
TP_PCH_RESERVE_26
TP_PCH_RESERVE_28
TP_PCH_RESERVE_27
TP_CRT_IG_BLUE
TP_CRT_IG_GREEN
TP_CRT_IG_DDC_CLK
TP_CRT_IG_HSYNC
TP_CRT_IG_VSYNC
=PP3V3_S0_PCH_GPIO
PCH_FDI_RX_N<1>
PM_SYNC
PCH_GPIO72
PM_PWRBTN_L
PM_CLK32K_SUSCLK_R
PCH_DAC_IREF
=PP3V3_S5_PCH
=TBT_WAKE_L
PCH_FDI_RX_N<5>
PCH_FDI_RX_N<4>
PCH_FDI_RX_N<3>
PCH_FDI_RX_N<2>
PCH_FDI_RX_N<6>
PCH_FDI_RX_N<7>
PCH_FDI_RX_P<6>
PCH_FDI_INT
PCH_FDI_FSYNC<1>
PCH_FDI_LSYNC<0>
PCH_FDI_RX_P<7>
PCH_FDI_RX_P<2>
PCH_FDI_RX_P<0>
PCH_FDI_RX_P<1>
PCH_FDI_RX_P<3>
TP_PCH_RESERVE_22
TP_PCH_RESERVE_23
TP_PCH_RESERVE_24
TP_PCH_RESERVE_25
PCH_FDI_RX_P<4>
PCH_FDI_RX_P<5>
TP_PCH_INIT3V3_L
TP_CRT_IG_DDC_DATA
TP_CRT_IG_RED
prefsb
051-9504
7.0.0
19 OF 143
19 OF 117
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
12
BN56
BC56
J38
BT43
BK38
BE52
E37
B37
C36
F38
E31
BP45
BD43
BR42
R47
BH49
F55
BC41
BM53
BN52
BA47
BN54
E49
C52
H46
P43
H43
C49
A46
D47
F43
M43
J43
B47
B45
C46
H41
F45
C42
BJ48
BU46
BJ38
BJ53
B31
A32
P38
J36
B35
B33
B43
D51
D33
J41
A36
B51
BC46
H38
M41
H36
R38
BG43
AV46
P41
BH50
BC44
BT37
BG46
Y50
R9
R8
R14
M12
M11
M3
L5
AL12
AL14
U12
U14
N2
J3
AL9
AL8
M1
B5
D5
D7
C6
C9
E11
U43
M49
M50
R50
U44
U46
U50
R44
U49
AB44
AB49
E52
H52
F53
J55
L56
K46
AB50
L53
Y44
G56
AB46
K49
K50
M48
AM1
AN2
AN6
AW3
AW1
AR4
AR2
AT3
AM6
U9
U8
U5
W3
T3
U2
AL15
AL17
T1
R12
K8
H8
L2
G4
G2
F5
F3
E2
E4
R6
N6
B7
B11
Y41
H50
J57
1
2
1
2
114
99
11 99
19 35 40
114
15
114
19
15
19
114
8
8
8
8
8
8
8
8
6
18
8
8
19
114
19
6
19 24 26
6
18 22 24
8
6
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
99
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
6
15 20 38
8
15
6
19 24 26
36
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
BI
BI
BI
BI
BI
BI
IN
OUT
IN
OUT
OUT
IN
IN
OUT
IN
IN
OUT
OUT
OUT
OUT
IN
USB3TN1
USB3TP1
USB3RN1
USB3RN2
USB3RP2
CLKOUT_PCI0
CLKOUT_PCI1
USBP13P
AD0
AD1
AD2
AD3
AD18
USBP8P
USBP8N
USBP7P
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
PIRQD*
REQ0*
REQ2*/GPIO52
REQ3*/GPIO54
GNT0*
GNT3*/GPIO55
PIRQE*/GPIO2
PIRQF*/GPIO3
PIRQG*/GPIO4
PIRQH*/GPIO5
PCIRST*
SERR*
PERR*
IRDY*
PAR
DEVSEL*
FRAME*
PLOCK*
STOP*
TRDY*
PME*
PLTRST*
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP9N
USBP9P
USBP10N
USBP11N
USBP11P
USBP12N
USBP13N
USBRBIAS*
REQ1*/GPIO50
AD29
AD30
AD31
USBP12P
USBP10P
C/BE3*
C/BE0*
C/BE1*
C/BE2*
PIRQA*
GNT2*/GPIO53
GNT1*/GPIO51
PIRQC*
PIRQB*
USBRBIAS
USB3RP1
CLKOUT_PCI4
CLKOUT_PCI3
CLKOUT_PCI2
USB3TN2
USB3TP2
USB3RP3
USB3RN3
USB3TP3
USB3TN3
USB3RN4
USB3RP4
USB3TP4
USB3TN4
OC0*/GPIO59
OC2*/GPIO41
OC1*/GPIO40
OC3*/GPIO42
OC4*/GPIO43
OC5*/GPIO9
OC7*/GPIO14
OC6*/GPIO10
USB
(5 OF 10)
PCI
IN
IN
IN
IN
OUT
IN
IN
IN
IN
OUT
IN
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
BI
BI
BI
BI
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
UNUSED
UNUSED
CAMERA
INTERNAL HUB (BT,SMC12)
EHCI - EXT D
UNUSED
EHCI - EXT B
UNUSED
UNUSED
UNUSED
EXT D
EXT C
EXT B
EXT A
TIE TRACES TOGETHER CLOSE TO PINS
PLACE THE RESISTOR CLOSE TO COMMON POINT
45
102
45
102
8
8
45
102
45
102
45
102
45
102
45
102
45
102
45
102
45
102
45
102
45
102
46
102
46
102
46
102
46
102
46
102
46
102
46
102
OMIT_TABLE
PANTHER-POINT
FCBGA
U1800
46
102
10K
5%
1/16W
MF-LF
402
NOSTUFF
R2019
60
62
15 36
117
15 35
112
15 45 99
15 45 99
15 46 99
15 46 99
15 99
15 99
15 99
15 41 99
SIGNAL_MODEL=EMPTY
201
1/20W
5% MF
0
R2001
SIGNAL_MODEL=EMPTY
0
201
1/20W
5% MF
R2002
R2003
1/20W
5% MF
0
SIGNAL_MODEL=EMPTY
201
1/20W
5%
0
MF
201
SIGNAL_MODEL=EMPTY
R2007
201
1/20W
5% MF
0
SIGNAL_MODEL=EMPTY
R2004
SIGNAL_MODEL=EMPTY
R2005
1/20W
5%
0
MF
201
SIGNAL_MODEL=EMPTY
R2006
201
1/20W
5%
0
MF
SIGNAL_MODEL=EMPTY
5% MF
1/20W
0
201
R2008
45
102
45
102
46
102
46
102
46
102
8
46
102
8
8
8
8
8
42
42
46
102
46
102
8
8
1/16W
22.6
MF-LF
402
1%
PLACE_NEAR=U1800.BM25:2mm
R2070
10K
MF-LF
4025%
1/16W
R2010
1/16W MF-LF
4025%
10K
R2011
MF-LF
402
1/16W
10K
5%
R2012
402
MF-LF
5%
1/16W
10K
R2013
10K
MF-LF
5%
1/16W
402
R2015
10K
MF-LF1/16W
4025%
R2016
10K
MF-LF
4025%
1/16W
R2017
5%
10K
1/16W
402
MF-LF
R2020
5%
10K
1/16W MF-LF
402
R2021
10K
5%
1/16W
402
MF-LF
R2022
26
114
26
101
26
101
26
101
10K
5%
1/16W
402
MF-LF
R2023
402
10K
5%
1/16W MF-LF
R2024
1/16W MF-LF
4025%
10K
R2026
402
1/16W
10K
MF-LF
5%
R2025
402
1/16W
5%
10K
MF-LF
R2027
27
102
27
102
8
8
MF-LF
5%
1/16W
10K
402
R2030
PCH PCI/USB
SYNC_MASTER=D7_MLB
SYNC_DATE=03/15/2012
AP_PWR_EN
USB_EXTB_OC_EHCI_L
USB_EXTC_OC_L
PCI_PERR_L
PCI_INTB_L
PCI_INTC_L
PCI_INTD_L
PCI_REQ0_L
USB_EXTB_OC_R_L
USB_EXTA_OC_L
SDCONN_STATE_CHANGE
USB3_EXTC_RX_F_N
USB_PCH_13_P
USB3_EXTA_TX_N
USB3_EXTD_TX_P
USB3_EXTD_TX_N
USB_EXTA_OC_R_L
USB_EXTC_OC_R_L
USB_EXTD_OC_R_L
USB_EXTB_OC_EHCI_R_L
AP_PWR_EN_R
USB_EXTD_OC_EHCI_L
USB3_EXTD_RX_F_P
USB3_EXTD_RX_F_N
TP_PCI_CLK33M_OUT2
PCI_DEVSEL_L
USB3_EXTB_TX_P
TP_PCI_C_BE_L<0>
TP_PCI_C_BE_L<2>
TP_PCI_C_BE_L<3>
PCI_INTA_L
PCH_USB_RBIAS
TP_PCI_AD<29>
SDCONN_STATE_CHANGE_R
USB_EXTD_OC_EHCI_R_L
USB_EXTB_OC_L
TP_PCI_PME_L
USB3_EXTA_TX_P
PCH_CLK33M_PCIOUT
PCI_FRAME_L
TP_PCI_PAR
TP_PCI_AD<30>
TP_PCI_AD<31>
TP_PCI_C_BE_L<1>
PCI_PLOCK_L
TP_PCI_AD<11>
TP_PCI_AD<12>
TP_PCI_AD<13>
USB_PCH_9_N
USB_PCH_12_N
TP_PCI_AD<2>
TP_PCI_AD<0>
TP_PCI_AD<3>
TP_PCI_AD<4>
TP_PCI_RESET_L
AUD_IP_PERIPHERAL_DET
TP_PCH_PCI_GNT0_L
AUD_I2C_INT_L
LPC_CLK33M_SMC_R
LPC_CLK33M_LPCPLUS_R
TBT_PWR_REQ_L
PCI_IRDY_L
PCI_TRDY_L
PCI_STOP_L
BLC_GPIO
TP_PCI_AD<6>
BT_PWR_RST_L
TP_PCH_STRP_ESI_L
TP_PCH_STRP_BBS1
JTAG_GMUX_TMS
TP_PCI_AD<28>
TP_PCI_CLK33M_OUT3
USB_PCH_11_N
USB3_EXTC_TX_P
PLT_RESET_L
USB3_EXTA_RX_F_P
USB_PCH_10_P
USB_PCH_12_P
USB_PCH_13_N
USB_PCH_11_P
USB_PCH_10_N
USB_PCH_9_P
USB_PCH_7_N
USB_PCH_6_P
USB_PCH_6_N
USB_PCH_5_P
USB_PCH_5_N
USB_PCH_4_P
USB_PCH_4_N
USB_PCH_3_P
USB_PCH_3_N
USB_PCH_2_P
USB_PCH_2_N
USB_PCH_1_P
USB_PCH_1_N
USB_PCH_0_P
USB_PCH_0_N
TP_PCI_AD<27>
TP_PCI_AD<26>
TP_PCI_AD<25>
TP_PCI_AD<24>
TP_PCI_AD<23>
TP_PCI_AD<22>
TP_PCI_AD<21>
TP_PCI_AD<20>
TP_PCI_AD<19>
TP_PCI_AD<17>
TP_PCI_AD<16>
TP_PCI_AD<15>
TP_PCI_AD<14>
TP_PCI_AD<10>
TP_PCI_AD<9>
TP_PCI_AD<8>
TP_PCI_AD<7>
TP_PCI_AD<5>
USB_PCH_7_P
USB_PCH_8_N
USB_PCH_8_P
TP_PCI_AD<18>
TP_PCI_AD<1>
USB3_EXTB_RX_F_P
USB3_EXTB_RX_F_N
USB3_EXTA_RX_F_N
PCH_STRP_TOPBLK_SWP_L
PCI_SERR_L
USB3_EXTC_TX_N
USB3_EXTC_RX_F_P
USB3_EXTB_TX_N
=PP3V3_S0_PCH_GPIO
BLC_I2C_MUX_SEL
USB_EXTD_OC_L
prefsb
051-9504
7.0.0
20 OF 143
20 OF 117
C29
E29
H31
J27
L27
AT11
AN14
BK27
BF15
BF17
BT7
BT13
BC6
BR29
BN27
BD31
BG12
BN11
BJ12
BU9
BR12
BJ3
BR9
BJ10
BM8
BF3
BN2
BE4
BE6
BG15
BT11
BA14
BL2
BC4
BL4
BC2
BM13
BA9
BF9
BA8
BP5
BG5
BK8
AV11
BA15
BE2
BN9
AV9
BT15
BR4
AV14
BR6
BM3
BF11
BH8
BH9
BC11
BA17
BC12
BC8
AV15
BK48
BF36
BD36
BC33
BA33
BM33
BM35
BT33
BU32
BR32
BT31
BN29
BM30
BK33
BJ33
BF31
BR26
BT27
BK25
BJ31
BK31
BF27
BJ27
BP25
BT5
BF8
AV17
BK12
BD27
BJ25
BP13
BN4
BP7
BG2
BK10
BU12
AV8
BM15
BJ5
BM25
J31
AT14
AT17
AT12
F28
E27
L25
J25
B27
C26
L22
J22
D25
B25
BM43
BG41
BD41
BK43
BP43
BJ41
BM45
BT45
1
2
12
12
12
12
12
12
12
12
1
2
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
25 99
25 99
25 99
25 99
25
99
25
99
8
8
8
8
102
8
25
99
25 99
8
8
8
8
8
8
8
8
8
8
8
8
8
8
114
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
114
6
15 19 38
OUT
IN
OUT
IN
NCTF
RSVD
GPIO
MISC
CPU
NCTF
(6 OF 10)
VSS_NCTF
SDATAOUT0/GPIO39
SLOAD/GPIO38
SATA4GP/GPIO16
PCIECLKRQ6*/GPIO45
TACH4/GPIO68
A20GATE
BMBUSY*/GPIO0 CLKOUT_PCIE6N
CLKOUT_PCIE6P
CLKOUT_PCIE7N
CLKOUT_PCIE7P
GPIO27
GPIO28
GPIO35/NMI*
GPIO57
GPIO8
NC_5
PCIECLKRQ7*/GPIO46
PECI
PROCPWRGD
PWM0
PWM1
PWM2
PWM3
RCIN*
SATA3GP/GPIO37
SATA5GP_GPIO49
SCLOCK/GPIO22
SDATAOUT1/GPIO48
SST
STP_PCI*/GPIO34
TACH0/GPIO17
TACH1/GPIO1
TACH2/GPIO6
TACH3/GPIO7
TACH5/GPIO69
TACH6/GPIO70
TACH7/GPIO71
THRMTRIP*
TP1
TP10
TP11
TP12
TP13
TP14
TP16
TP17
TP18
TP19
TP2
TP20
TP3
TP4
TP5
TP6
TP7
TP8
TP9
NC_1
NC_2
NC_3
NC_4
VSSADAC
GPIO15
LAN_PHY_PWR_CTRL/GPIO12
GPIO24/PROC_MISSING
SATA2GP/GPIO36
TP15
BI
OUT
IN
OUT
OUT
OUT
OUT
IN
IN
IN
OUT
IN
NC
OUT
OUT
OUT
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
RDAR://11363991 D7/D7I/D8/J35/J36: RENAME GPU/TBT MUX SELECT TO DP_TBT_SEL
Place this near the T point
X
11 25 28 99
48
115
5%
1/16W
MF-LF
10K
402
R2155
402
MF-LF
1/16W
10K
5%
R2150
28 34 99
5%
100K
MF-LF
1/16W
402
R2190
49
114
NOSTUFF
0
5%
402
1/16W MF-LF
R2170
0
1/16W
5%
402
MF-LF
R2140
FCBGA
PANTHER-POINT
OMIT_TABLE
U1800
11 47 48 99
5
99
15 47
117
38
117
26 99
62 84 99
15 99
15
114
15
112
15
117
15 26 99
49
101
5%
0
201
R2106
SIGNAL_MODEL=EMPTY
1/20W
MF
SIGNAL_MODEL=EMPTY
201
5%
1/20W
MF
0
R2101
R2104
201
5% MF
1/20W
0
SIGNAL_MODEL=EMPTY
1/20W
R2107
0
5%
201
SIGNAL_MODEL=EMPTY
MF
SIGNAL_MODEL=EMPTY
0
5%
201
MF
1/20W
R2108
0
5%
1/20W
201
MF
SIGNAL_MODEL=EMPTY
R2103
MF
1/20W
5%
0
201
SIGNAL_MODEL=EMPTY
R2109
R2105
5%
201
0
1/20W
MF
SIGNAL_MODEL=EMPTY
5%
1/20W
MF
201
33
R2110
5%
1/20W
33
201
MF
R2111
43
102
43
114
MF5%
33
201
R2113
1/20W
89
114
89
114
R2112
MF
201
1/20W335%
PCH MISC
SYNC_DATE=N/A
SYNC_MASTER=D8_MLB
TP_PCH_TP20
JTAG_TBT_TCK_R
TBT_PCH_CLKREQ_L
TBT_GO2SX_BIDIR
SMC_WAKE_SCI_L
ISOLATE_CPU_MEM_R_L
JTAG_TBT_TDI
AUD_IPHS_SWITCH_EN_PCH
CPU_PWRGD
CPU_PECI
=PP3V3_S0_PCH
JTAG_TBT_TCK
=PP3V3_S0_PCH
TBT_CIO_PLUG_EVENT
DP_TBT_SEL
PCH_CAM_RESET_R
ENET_LOW_PWR_PCH
JTAG_TBT_TDO
AUD_IPHS_SWITCH_EN_PCH_R
AP_CLKREQ_L
PCH_A20GATE
TBT_CIO_PLUG_EVENT_R TP_PCIE_CLK100M_PE6N
TP_PCIE_CLK100M_PE6P
TP_PCIE_CLK100M_PE7N
TP_PCIE_CLK100M_PE7P
HDD_PWR_EN
PCH_PECI
PCH_PROCPWRGD
TP_PCH_PWM0
TP_PCH_PWM1
TP_PCH_PWM2
TP_PCH_PWM3
PCH_RCIN_L
ENET_LOW_PWR_PCH_R
PCH_GPIO22
TP_PCH_SST
TBT_SW_RESET_R_L
LPCPLUS_GPIO
PCH_GPIO1
PCH_GPIO6
SMC_RUNTIME_SCI_L
PM_THRMTRIP_L
TP_PCH_TP1
TP_PCH_TP10
TP_PCH_TP11
TP_PCH_TP12
TP_PCH_TP13
TP_PCH_TP14
TP_PCH_TP16
TP_PCH_TP17
TP_PCH_TP18
TP_PCH_TP19
TP_PCH_TP2
TP_PCH_TP3
TP_PCH_TP4
TP_PCH_TP5
TP_PCH_TP6
TP_PCH_TP7
TP_PCH_TP8
TP_PCH_TP9
XDP_PIN03
WOL_EN
TP_PCH_TP15
PCH_CAM_RESET
SPIROM_USE_MLB
PCH_GPIO48
PCH_CAM_EXT_BOOT_L
PCH_BLC_MCU_RESET
PCH_BLC_EXT_BOOT_R
PCH_BLC_EXT_BOOT
ISOLATE_CPU_MEM_L
GPU_GOOD
GPU_GOOD_R
DP_TBT_SEL_R
TBT_SW_RESET_L
PCH_CAM_EXT_BOOT_R_L
PCH_BLC_MCU_RESET_R
prefsb
051-9504
7.0.0
21 OF 143
21 OF 117
1
2
1
2
1
2
12
12
A6
A4
BF55
BE54
AU56
AV44
BU16
BM57
B2
BB57
AW55
AB3
AA2
AE2
AF1
BJ43
BJ55
BJ57
BT53
BP51
AY20
BP55
H48
D53
BN21
BT21
BM20
BN19
BG56
BG53
BA56
BA53
AW53
BC43
BL56
BT17
BR19
BA22
BR16
BM18
BN17
BP15
E56
P22
BM46
BA27
BC49
AE49
AE41
AE50
BA36
AY36
Y14
L31
Y12
L33
M38
L36
Y18
Y17
AB18
AB17
A54
A52
F57
D57
BU54
BU6
BM1
BP1
BU4
BU52
AU2
BM55
BK50
BT2
BP57
BP53
BB55
AE43
F1
D1
12
12
12
12
12
12
12
12
12
12
12
12
8
25 99
15 36
15 47
117
25 99
15
114
6
18 21 24
6
18 21 24
15 99
25 99
25 99
8
8
8
8
52
113
114
8
8
8
8
114
25 99
15
8
15
15
15
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
25 99
15 40
117
8
15
114
15
15
15
114
25 99
25 99
VCCAPLLEXP
VCCCLKDMI
VCCAPLLDMI2
VCCIO
VCCADAC
VCCVRM1
VCCIO
VCC3_3_0
VCCVRM0
VCCASW
VCCCORE
VCC3_3
VCCAFDIPLL
VCCDMI
(7 OF 10)
VCCIO_DMI/CLK
VCC CORE
CRTDMI
FDI
VCCASW
VCCIO_PCIE
HVCMOS
V_PROC_IO_NCTF
VCCRTC
V5REF_SUS
VCCADPLLB
VCCSPI
VCCIO
V5REF
VCCAPLLSATA
VCC3_3
DCPSUSBYP
VCCACLK
DCPRTC
VCCADPLLA
DCPSST
V_PROC_IO
VCCDFTERM0
VCCDFTERM1
VCCDIFFCLKN
VCCDSW3_3
VCCIO
VCCVRM3
VCCSUSHDA
VCCVRM2
DCPRTC_NCTF
VCCSUS3_3
VCCSSC
VCC3_3
DCPSUS
SATA
PCI/GPIO/LPC
PCI/GPIO/LPC
(10 OF 10)
USB
CPURTC
HDA
CLOCK AND MISCELLANEOUS
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
PCH output, for decoupling only
Max and Idle = 1mA
20mA Max, 10mA Idle
(VCCIO[1-31] total)
3.456A Max, 426mA Idle
PCH output, for decoupling only
57 mA Max, 30mA Idle
1.44 A Max, 474mA Idle
55mA Max, 5mA Idle
20mA Max, 1mA Idle
3mA Max, 1mA Idle
200 mA Max, 2mA Idle
(VCCSUS3_3 - 11 TOTAL)
Need to check layout decoupling
409 mA Max, 42mA Idle
Max and Idle = 1 MA
40mA Max, 10mA Idle
40mA Max, 5mA Idle
Max and Idle = 1mA
97mA Max, 15mA Idle
(VCCVRM 4 total)
159mA Max, 114mA Idle
105mA Max, 90mA Idle
10 mA Max, 1mA Idle
1.61A Max, 433mA Idle
(VCC3_3[1-9] total)
Max and Idle = 1mA
PLACE_NEAR=U1800.BR54:4MM
C2210
0.1UF
402
20%
CERM
10V
C2222
PLACE_NEAR=U1800.BA46:2mm
0.1UF
6.3V
X5R
201
10%
0.1UF
PLACE_NEAR=U1800.BU42:2mm
C2232
402
CERM
10V
20%
C2231
CERM
402
PLACE_NEAR=U1800.BU42:2mm
10%
6.3V
1UF
U1800
OMIT_TABLE
FCBGA
PANTHER-POINT
U1800
OMIT_TABLE
FCBGA
PANTHER-POINT
SYNC_MASTER=D8_MLB
SYNC_DATE=N/A
PCH POWER
=PP3V3_G3_PCH_RTC
PPVOUT_S0_PCH_DCPSST
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm
=PP5V_S5_PCH_V5REFSUS
=PP5V_S0_PCH_V5REF
TP_PP1V05_S0_PCH_VCCAPLL_SATA
=PP1V05_S0_PCH_VCCIO_SATA
=PP3V3_S5_PCH_VCCSUS_USB
TP_PP1V05_S0_PCH_FDIPLL
=PP3V3_S0_PCH_VCC_PCI
=PP1V05_S0_PCH_VCC_ASW
=PP3V3_S0_PCH_VCC_HVCMOS
=PP1V05_S0_PCH_VCC_CORE
PP1V05_S0_PCH_VCCADPLLB_F
PP1V8_S0_PCH_VCCVRM_F
TP_PP1V05_S0_PCH_VCCAPLL_EXP
TP_DCPSUS_0
=PP1V05_S0_PCH_VCC_SSC
PP1V8_S0_PCH_VCCVRM_F
=PP3V3_S5_PCH_VCC_DSW
=PP1V05_S0_PCH_VCC_DIFFCLK
=PP1V8_S0_PCH_VCC_DFTERM
PP1V05_S0_PCH_VCCADPLLA_F
=PP3V3_S5_PCH_VCC_SPI
PP1V8_S0_PCH_VCCVRM_F
PP3V3_S0_PCH_VCCA_DAC_FTP_PPVOUT_PCH_DCPSUSBYP
=PP1V05_S0_PCH_VCC_DMI
=PP3V3_S0_PCH_VCC
TP_DCPSUS_2
=PP3V3_S0_PCH_VCC_GPIO
=PP1V05_S0_PCH_VCCIO_DMI
PP1V8_S0_PCH_VCCVRM_F
=PP1V05_S0_PCH_VCCCLKDMI
TP_PP1V05_S0_PCH_VCCAPLLDMI2
=PP1V05_S0_PCH_VCCIO_PCIE
=PP3V3_S5_PCH_VCCSUS_HDA
TP_DCPSUS_1
=PP1V05_S0_PCH_V_PROC_IO
PPVOUT_G3_PCH_DCPRTC
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.2 mm
=PP1V05_S0_PCH_VCCIO_USB
TP_PP1V05_S0_PCH_VCC_A_CLK
prefsb
051-9504
7.0.0
22 OF 143
22 OF 117
2
1
2
1
2
1
2
1
AG26
AG28
AJ24
AN34
AL34
AJ28
AJ26
B53
AJ20
A19
AN32
AC32
Y26
V33
AA36
Y20
Y22
Y24
Y28
V22
V25
V27
F20
AT1
R56
B41
Y30
Y32
Y34
Y36
V36
V31
F30
AF57
AJ1
AU32
AV36
AU34
AG24
AL24
AL28
AN22
AN24
AN26
AN28
AR24
AR26
AR28
AR30
AR36
AR38
AU30
AU36
AC24
AC26
AC28
AC30
AE24
AE28
AE30
AE32
AE34
AE36
AJ32
AJ34
AJ36
AL32
AR32
AR34
BC17
BD17
BD20
C54
E41
AG32
AG34
AA34
B56
BU42
BT25
AC2
AN52
AG40
AG38
AG41
BA38
AN40
AN41
BF1
U56
AV20
AU20
A12
AN38
AV41
AL5
BR54
AB1
BA46
AT41
AU22
D55
T55
T57
AE15
AE17
AG15
AV40
AY25
AY27
AV24
AV26
AV30
AV32
AY31
AY33
BJ36
BK36
BM36
AT40
AU38
BT35
AJ38
AE40
AL40
R2
AV28
R54
BT56
U31
AC20
AE20
AL38
AA32
A39
6
24
24
6
18 24
6
24
6
24
6
24
6
24
6
24
17
115
22 24
115
6
24
22 24
115
6
24
6
24
6
24
17
115
6
24
22 24
115
17
115
6
24
6
24
6
24
6
24
22 24
115
6
24
6
18 19 24
6
24
6
24
6
24
VSS
VSS
(8 OF 10)
VSS
VSS
(9 OF 10)
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
U1800
OMIT_TABLE
PANTHER-POINT
FCBGA
U1800
OMIT_TABLE
PANTHER-POINT
FCBGA
SYNC_MASTER=D7_MLB
SYNC_DATE=03/15/2012
PCH GROUNDS
prefsb
051-9504
7.0.0
23 OF 143
23 OF 117
AE56
BR36
AB15
AB43
AA28
AN11
AM57
AM52
AM3
AL47
AL46
AL41
AL36
AL30
AL26
AL22
AL20
AL18
AL11
AJ22
AJ30
AK6
AK52
AJ57
AG5
AG50
AG53
AH52
AH6
AG30
AG36
AG43
AG44
AG46
AF6
AG11
AG14
AG20
AG22
AF52
AE4
AE47
AE8
AE9
AE38
AE14
AE18
AE22
AE26
AC54
AC34
AC36
AC4
AC22
AB47
AB52
AB57
AB6
AB11
AA38
AB40
AB41
AA30
AA26
AA24
AA22
AA20
A9
A49
A42
A26
BG33
BG36
BG31
BF25
BF33
BF41
BF43
BF46
BF52
BF6
BG22
BG25
BG27
BC27
BC31
BC36
BC38
BC47
BC9
BD25
BD33
BF12
BF20
BA41
BA44
BA49
BB1
BB3
BB52
BB6
BC14
BC15
BC20
BA31
AV47
AV6
AW57
AY38
AY6
B23
BA11
BA12
AV34
AT52
AT6
AT8
AU24
AU26
AU28
AU5
AV12
AV18
AV22
AN54
AN9
AR20
AR22
AR52
AR6
AT15
AT18
AT43
AT47
AN12
AN15
AN17
AN18
AN20
AN30
AN36
AN4
AN43
AN47
AC38
AV38
A29
AY22
C12
J46
J48
J5
J53
K52
K6
K9
L12
L17
L38
L41
L43
M20
M22
M25
M27
M31
M33
M36
M46
M52
M57
M6
M8
M9
N4
N54
R11
R15
R17
R22
R4
R41
R43
R46
R49
T6
U11
U15
U17
U20
U22
U25
U27
U33
U36
U38
U41
U47
U53
V20
V38
V6
W1
W55
W57
Y11
Y15
Y38
Y40
Y43
Y46
Y47
Y49
Y52
Y6
AL43
AL44
R36
P36
R25
P25
BH52
BH6
BJ1
BJ15
BK20
BK41
BK52
BK6
BM10
BM12
BM16
BM22
BM23
BM26
BM28
BM32
BM40
BM42
BM48
BN47
BN6
BP3
BP33
BP35
BR22
BR52
BU19
BU26
BU29
BU36
BU39
C19
C32
C39
C4
D15
D23
D3
D35
D43
D45
E19
E39
E54
E6
E9
F10
F12
F16
F22
F26
F32
F33
F35
F36
F40
F42
F46
F48
F50
F8
G54
H15
H20
H22
H25
H27
H33
H6
J1
J33
T52
BN31
BM5
BG38
NC
NC
NC
NC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
1 mA S0-S5
PLACEMENT_NOTE:
PLACEMENT_NOTEs:
PLACEMENT_NOTE:
PLACEMENT_NOTE:
<1 MA
PCH V5REF_SUS Filter & Follower
(PCH Reference for 5V Tolerance on USB)
<1 MA S0-S5
PLACEMENT_NOTEs:
(PCH PCI 3.3V PWR)
PCH VCC3_3 BYPASS
PLACEMENT_NOTEs:
PLACEMENT_NOTE:
PLACEMENT_NOTEs:
PLACEMENT_NOTEs:
1 mA
(PCH DMI 1.05V PWR)
PCH VCCIO BYPASS
INTEL PDG: 1X 0.1UF
INTEL PDG: 1X 0.1UF
PLACEMENT_NOTE:
INTEL PDG: 2X 1UF
PLACEMENT_NOTES:
PCH VCCIO BYPASS
(PCH USB 1.05V PWR)
PLACEMENT_NOTEs:
(PCH HD Audio 3.3V/1.5V PWR)
PLACEMENT_NOTE:
INTEL PDG: 1X 0.1UF
PLACEMENT_NOTEs:
INTEL PDG: 4X 1UF AND 2X 10UF
FOR PCH_VCC_DIFFCLK AND PCH_VCC_CORE
(PCH 1.05V CORE PWR)
PLACEMENT_NOTEs:
PCH VCCCORE BYPASS
PCH VCCSUS3_3 BYPASS
PLACEMENT_NOTEs:
(PCH Reference for 5V Tolerance on PCI)
INTEL PDG: 1X 1UF
INTEL PDG: 2X 0.1UF AND 1X 2.2UF
PLACEMENT_NOTEs:
PCH VCCSUSHDA BYPASS
(PCH SUSPEND USB 3.3V PWR)
PLACEMENT_NOTE:
INTEL PDG: 2X 0.1UF AND 1X 4.7UF
PLACEMENT_NOTEs (all 3):
PLACEMENT_NOTEs:
PLACEMENT_NOTEs:
PLACEMENT_NOTE:
PCH V5REF Filter & Follower
1UF
402
10V
10%
X5R
C2439
PLACE C2439 AT BALL BF1
100
5%
402
1/16W
MF-LF
R2405
2
1
20%
402
CERM
0.1UF
10V
C2438
PLACE C2438 AT BALL BT25
SOT-363
BAT54DW-X-G
D2400
402
5%
MF-LF
1/16W
10
2
1
R2404
BAT54DW-X-G
SOT-363
D2400
MF-LF
R2400
0
1/16W
5%
402
PLACE C2440 AT BALL T55
C2440
0.1UF
402
20%
CERM
10V
0.1UF
20%
CERM
402
10V
C2441
PLACE C2441 AT BALL AV28
PLACE C2450 AT BALL AV26
1UF
CERM
402
10%
6.3V
C2450
PLACE C2419 AT BALL B41
402
10%
1UF
6.3V
CERM
C2419
C2422
PLACE C2422 AT BALL AU20
402
CERM
1UF
6.3V
10%
PLACE C2449 AT BALL AY27
CERM
402
1UF
10%
6.3V
C2449
PLACE C2416 AT BALL D55
C2416
4.7UF
6.3V
20%
402
X5R
PLACE C2485 AT BALL AL38
X5R
10%
25V
0.1UF
402
C2485
PLACE C2410 AT BALL Y20
10UF
C2410
CERM
20%
6.3V
805-1
PLACE C2463 AT BALL V25
402
1UF
10%
6.3V
CERM
C2463
PLACE C2480 AT BALL AC20
6.3V
CERM
20%
805-1
C2480
10UF
PLACE C2475 AT BALL AE20
402
CERM
6.3V
C2475
1UF
10%
PLACE C2437 AT BALL AE15
10UF
CERM
20%
6.3V
805-1
C2437
PLACE C2435 AT BALL AE17
CERM
1UF
10%
6.3V
402
C2435
PLACE C2434 AT BALL AE15
1UF
6.3V
402
CERM
10%
C2434
PLACE C2471 AT BALL AA34
805-1
10UF
20%
6.3V
CERM
C2471
PLACE C2469 AT BALL V36
10%
CERM
6.3V
402
C2469
1UF
PLACE C2414 AT BALL Y26
C2414
1UF
402
10%
6.3V
CERM
PLACE C2401 AT BALL V22
C2401
20%
6.3V
CERM
10UF
805
PLACE C2487 AT BALL E41
10%
402
CERM
6.3V
C2487
1UF
PLACE C2452 AT BALL AG38
1UF
CERM
6.3V
402
10%
C2452
PLACE C2453 AT BALL AJ38
C2453
1UF
CERM
6.3V
402
10%
2.2UF
C2412
402
X5R
6.3V
10%
PLACE C2412 AT BALL AT40
PLACE C2499 AT BALL AV40
402
20%
CERM
10V
0.1UF
C2499
CERM
10%
1UF
402
C2442
6.3V
PLACE C2442 AT BALL AN52
C2445
10UF
PLACE C2445 AT BALL R2
805-1
CERM
6.3V
20%
C2443
PLACE C2443 AT BALL AJ1
6.3V
402
1UF
10%
CERM
402
CERM
6.3V
C2436
10%
1UF
PLACE C2436 AT BALL R54
X5R
PLACE C2486 AT BALL AU22
0.1UF
10%
402
25V
C2486
PLACE C2444 AT BALL BA38
10%
402
6.3V
CERM
1UF
C2444
PLACE C2446 AT BALL AY25
1UF
402
CERM
6.3V
10%
C2446
805-1
20%
CERM
6.3V
C2472
PLACE C2472 AT BALL V31
10UF
1UF
402
10%
PLACE C2470 AT BALL Y32
6.3V
CERM
C2470
CERM
6.3V
10UF
805-1
PLACE C2473 AT BALL F30
20%
C2473
10%
402
6.3V
1UF
PLACE C2425 AT BALL BD20
CERM
C2425
10%
402
6.3V
PLACE C2427 AT BALL BD17
CERM
1UF
C2427
C2461
805-1
CERM
20%
10UF
6.3V
PLACE C2461 AT BALL AR32
C2460
PLACE C2460 AT BALL AJ34
6.3V
10UF
CERM
805-1
20%
PLACE C2482 AT BALL AC24
C2482
CERM
10%
1UF
6.3V
402
PLACE C2481 AT BALL AC32
6.3V
402
1UF
10%
CERM
C2481
CERM
C2483
6.3V
1UF
10%
402
PLACE C2483 AT BALL AL34
PLACE C2407 AT BALL Y28
402
CERM
6.3V
1UF
10%
C2407
PLACE C2415 AT BALL F20
10UF
20%
CERM
805-1
C2415
6.3V
402
C2429
PLACE C2429 AT BALL Y24
10%
1UF
6.3V
CERM
PLACE C2428 AT BALL AJ24
10UF
6.3V
CERM
20%
805-1
C2428
PLACE C2420 AT BALL AU32
6.3V
20%
CERM
10UF
805-1
C2420
PLACE C2418 AT BALL AN22
C2418
CERM
6.3V
20%
10UF
805-1
PLACE C2498 AT BALL AR24
CERM
6.3V
10%
1UF
402
C2498
PLACE C2496 AT BALL AR36
C2496
1UF
6.3V
10%
CERM
402
6.3V
C2456
PLACE C2456 AT BALL AG28
CERM
402
1UF
10%
PLACE C2426 AT BALL AU30
C2426
1UF
402
CERM
6.3V
10%
C2411
10%
X5R
16V
402
1UF
PLACE C2411 AT BALL AJ20
2.2UF
10%
X5R
6.3V
PLACE C2412 AT BALL AV30
C2455
402
C2490
0.1UF
10%
16V
X7R-CERM
0402
C2413
0.1UF
10%
16V
X7R-CERM
0402
C2484
0.1UF
10%
16V
X7R-CERM
0402
C2430
0402
X7R-CERM
16V
10%
0.1UF
C2417
X7R-CERM
0.1UF
10%
16V
0402
C2421
0.1UF
10%
16V
X7R-CERM
0402
C2423
0402
X7R-CERM
16V
0.1UF
10%
C2424
0.1UF
0402
X7R-CERM
16V
10%
C2447
X7R-CERM
10%
0402
16V
0.1UF
SYNC_DATE=N/A
SYNC_MASTER=D8_MLB
PCH DECOUPLING
PP1V8_S0_PCH_VCCVRM_F
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM
MAKE_BASE=TRUE
VOLTAGE=1.8V
VOLTAGE=5V
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.25MM
PP5V_S5_PCH_V5REFSUS
MAKE_BASE=TRUE
=PP3V3_S0_PCH_VCC_HVCMOS
=PP3V3_S0_PCH_VCC
=PP1V05_S0_PCH_V_PROC_IO
=PP3V3_S0_PCH_VCC_PCI
=PP3V3_S5_PCH_VCCSUS_USB
=PP5V_S0_PCH
=PP5V_S0_PCH_V5REF
=PP1V05_S0_PCH_VCC_ASW
=PP1V05_S0_PCH_VCC_CORE
=PP1V05_S0_PCH_VCCIO_DMI
=PP1V05_S0_PCH_VCCIO_PCIE
=PP1V05_S0_PCH_VCC_DIFFCLK
=PP1V05_S0_PCH_VCCIO_USB
=PP3V3_S5_PCH_VCCSUS_HDA
=PP1V05_S0_PCH_VCCIO_SATA
=PP3V3_S5_PCH_VCC_DSW
=PP1V05_S0_PCH_VCC_DMI
=PP3V3_S0_PCH
=PP1V05_S0_PCH_VCC_SSC
=PP3V3_S5_PCH
=PP5V_S5_PCH
=PP1V8_S0_PCH_VCC_VRM
=PP1V8_S0_PCH_VCC_DFTERM
=PP3V3_S5_PCH_VCC_SPI
=PP3V3_S0_PCH_VCC_GPIO
=PP1V05_S0_PCH_VCCCLKDMI
=PP5V_S5_PCH_V5REFSUS
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.3MM
VOLTAGE=5V
MAKE_BASE=TRUE
PP5V_S0_PCH_V5REF
prefsb
051-9504
7.0.0
24 OF 143
24 OF 117
2
1
2
1
6
1
5
3
4
2
12
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
22
115
115
6
22
6
22
6
22
6
22
6
22
6
22
6
22
6
22
6
22
6
18 19 22
6
22
6
22
6
22
6
18 22
6
22
6
22
6
18 21
6
22
6
19 26
6
6
6
22
6
22
6
22
6
22
22
115
BI
IN
IN
IN
IN
IN
IN
IN
NC
IN
BI
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
IN
IN
IN
IN
NC
BI
IN
OUT
IN
IN
IN
IN
OUT
IN
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
- Unused GPIOs 0 & 15 not isolated.
be replaced with aliases. Otherwise these R’s must
and path to non-XDP signal destination.
Pull-up to 3.3V on csa 26 (PCH Support)
1K series resistor on csa 26 (PCH Support)
Connects to PCH XDP Conn
- For isolated GPIOs:
- MXM_GOOD not isolated as only LED is affected.
needs to split between route from PCH to J2550
- ’Output’ PCH/XDP signals require pulls.
PCH Signals
oc7#/gpio14
xdp_present#
obsdata_c1
sata2gp/gpio36
sata3gp/gpio37
gpio15
PCH Micro2-XDP
1K series resistor on csa 26 (PCH Support)
obsdata_b0
obsdata_c2
obsdata_c3
obsen_d1
obsen_c0
obsdata_c2
obsen_d0
obsdata_c1
obsdata_a2
trstn
itpclk/hook4
obsen_a1
obsdata_d3
itpclk#/hook5
reset#/hook6
obsdata_c3
obsen_d1
tms
tdi
tdo
dbr#/hook7
vcc_obs_cd
obsen_c0
obsen_d0
obsdata_c0
obsen_c1
itpclk/hook4
tdo
tdi
tms
obsdata_a2
obsdata_a3
obsen_b0
vcc_obs_ab
pwrgd/hook0
scl
sda
hook3
hook1
obsdata_b2
obsen_b1
hook2
obsdata_b0
tck0
tck1
scl
sda
vcc_obs_ab
hook2
hook3
hook1
pwrgd/hook0
obsdata_b3
obsdata_b2
obsdata_b1
obsdata_a1
obsdata_a0
obsdata_a0
obsen_a1
obsen_a0
obsdata_b1
obsdata_b3
CPU Micro2-XDP
obsdata_a1
PCH/XDP Signal Isolation Notes:
events while using PCH XDP.
obsdata_d0
obsdata_d1
obsdata_d2
obsdata_c0
obsen_c1
obsen_a0
XDP Signals
- ’Output’ non-XDP signals require pulls.
If PCH XDP not implemented, all of R2524-R2537 can
connect to appropriate non-XDP signals on PCB.
obsen_b1
obsen_b0
oc3#/gpio42
oc2#/gpio41
oc0#/gpio59
oc6#/gpio10
oc5#/gpio9
sata1gp/gpio19
sata0gp/gpio21
gpio0
gpio35
sata5gp/gpio49
sata4gp/gpio16
mgpio7/gpio28
xdp_present#
trstn
dbr#/hook7
itpclk#/hook5
obsdata_d2
obsdata_d1
obsdata_d0
oc4#/gpio43
oc1#/gpio40
obsdata_a3
obsdata_d3
vcc_obs_cd
reset#/hook6
be stuffed even in production so that PCH pins
R2524-R2537 should be placed where signal path
- USB OC#’s not isolated, avoid USB port overcurrent
tck0
tck1
998-2516
998-2516
11 99
11 99
11 99
11 99
11 99
11 99
10 99
10 99
25 50
25 50
11 25 99
10 99
10 99
10 99
10 25 99
10 15 99
10 15 99
10 99
10 99
10 15 99
10 99
10 15 99
10 99
26 99
11 25 99
11 25 99
11 25 99
11 25 99
SW2600.2:350MM
0
R2506
XDP
1/16W
5%
MF-LF
402
19 26 47
115
R1553.1:5MM
402
MF-LF
0
R2505
5%
XDP
1/16W
R1554.1:5MM
0
XDP
1/16W
402
5%
R2504
MF-LF
15 18 99
15 18 99
11 99
11 99
11 99
11 99
U1000.J40:25MM
XDP
R2500
1/16W5%402
MF-LF
1K
MF-LF
U4900.D10:350MM
0
R2501
402
1/16W
XDP
5%
MF-LF
U1000.H36:25MM
1K
5%
1/16W
402
XDP
R2502
5%
XDP
1/16W
402
MF-LF
0
R2503
J2500.47:10MM
5
65 66
115
10 25 99
15 19 25 47
115
11 21 28 99
J2500.52:10MM
402
1/16W
51
MF-LF
5%
XDP
R2510
MF-LF
U1000.L40:10MM
402
1/16W
5%
51
XDP
R2511
U1000.L38:10MM
402
MF-LF
1/16W
5%
51
XDP
R2512
U1000.J39:10MM
402
MF-LF
1/16W
5%
51
XDP
R2513
U1000.M40:10MM
402
MF-LF
1/16W
5%
51
XDP
R2514
25 99
25 99
25 99
25 99
25 99
25 99
25 99
25 99
25 99
25 99
26 99
18 25 99
18 25 99
18 25 99
25 99
25 99
25 99
25 99
25 50
25 50
18 25 99
25 99
25 99
25 99
25 99
15 19 25 47
115
J2550.30:10MM
XDP
402
MF-LF
1/16W
5%
1K
R2550
6
25
402
5%
U1800.BC50:10MM
200
1/16W
MF-LF
XDP
R2562
MF-LF
5%
1/16W
402
200
U1800.BC52:10MM
XDP
R2561
51
5%
402
1/16W
MF-LF
U1800.BA43:10MM
XDP
R2566
J2500.52:121MM
XDP
MF-LF
5%
200
1/16W
R2560
402
20 99
20 99
20 99
20 99
20 99
20 99
20 99
20 99
21 99
21 99
21 99
18 99
18 99
21 99
21 99
21 99
21 99
CRITICAL
M-ST-SM
XDP_CONN
DF40RC-60DP-0.4V
J2500
CRITICAL
DF40RC-60DP-0.4V
XDP_CONN
M-ST-SM
J2550
NOSTUFF
R2567
402
0
5%
MF-LF
1/16W
1/16W
MF-LF
402
5%
100
U1800.BA43:10MM
XDP
R2565
1/16W
5%
402
MF-LF
100
U1800.BA43:10MM
XDP
R2564
J2500.52:121MM
R2563
XDP
100
1/16W
MF-LF
402
5%
R2520
5%
402
MF-LF
1/16W
33
5%
402
MF-LF
33
1/16W
R2521
5%
MF-LF
33
402
1/16W
R2522
MF-LF
402
1/16W
5%
33
R2523
R2524
1/16W
5%
402
MF-LF
33
5%
1/16W
402
MF-LF
33
R2525
4025%1/16W
MF-LF
33
R2526
5%
1/16W
MF-LF
33
402
R2527
402
1/16W
MF-LF
33
5%
R2537
1/16W
33
402
MF-LF
R2528
5%
33
402
MF-LF
1/16W
5%
R2529
33
MF-LF
4025%1/16W
R2530
1/16W
5%33MF-LF
402
R2533
402
MF-LF335%
1/16W
R2534
402
MF-LF
5%
33
1/16W
R2535
MF-LF
1/16W
5%
33
402
R2536
21 99
MF-LF
33
402
1/16W
5%
R2531
402
MF-LF
1/16W
5%
33
R2532
11 25 99
11 25 99
U4900.D10:117MM
XDP
R2551
0
1/16W
MF-LF
402
5%
0402
XDP
X7R-CERM
C2500
0.1UF
10%
16V
X7R-CERM
16V
10%
0402
0.1UF
C2501
XDP
C2551
X7R-CERM
16V
10%
0402
0.1UF
XDP
C2550
0.1UF
0402
XDP
X7R-CERM
10%
16V
CPU and PCH XDP
SYNC_MASTER=D7_MLB
SYNC_DATE=01/26/2012
=PP3V3_S5_XDP
=PPVCCIO_S0_XDP
=SMBUS_XDP_SCL
XDP_CPU_PWRGD
XDP_CPU_PWRBTN_L
XDP_CPU_TMS
=PP3V3_S5_XDP
XDP_CPU_TDI
VOLTAGE=3.3V
PP3V3_S5_XDP_R
MAX_NECK_LENGTH=3MM
MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.2MM
ISOLATE_CPU_MEM_R_L
XDP_PIN03
XDP_DA3_USB_EXTD_OC_L
USB_EXTD_OC_R_L
USB_EXTB_OC_EHCI_R_L
USB_EXTD_OC_EHCI_R_L
USB_EXTA_OC_R_L
USB_EXTB_OC_R_L
USB_EXTC_OC_R_L
PM_PWRBTN_L
=PP3V3_S5_XDP
XDP_PCH_PWRGD
CPU_CFG<2>
CPU_CFG<7>
XDP_FC0_PCH_GPIO15
XDP_FC1_TBT_CIO_PLUG_EVENT
XDP_DD3_ENET_LOW_PWR_PCH
XDP_DB2_AP_PWR_EN
CPU_CFG<3>
CPU_CFG<8>
CPU_CFG<9>
XDP_CPU_TDO
XDP_DBRESET_L
XDP_PCH_TCK
XDP_DA1_USB_EXTB_OC_L
XDP_FC0_PCH_GPIO15
GPU_GOOD_R
DP_TBT_SEL_R
XDP_DB3_SDCONN_STATE_CHANGE
XDP_DB1_USB_EXTD_OC_EHCI_L
XDP_DB0_USB_EXTB_OC_EHCI_L
XDP_DA0_USB_EXTA_OC_L
XDP_DA2_USB_EXTC_OC_L
XDP_DA1_USB_EXTB_OC_L
SDCONN_STATE_CHANGE_R
XDP_DB0_USB_EXTB_OC_EHCI_L
XDP_CPU_PLTRST_L
XDP_DA0_USB_EXTA_OC_L
XDP_DD3_ENET_LOW_PWR_PCH
XDP_DC1_GPU_GOOD
XDP_PCH_PLTRST_L
XDP_PCH_TMS
XDP_DB1_USB_EXTD_OC_EHCI_L
=SMBUS_XDP_SDA
XDP_PCH_TCK
XDP_DB2_AP_PWR_EN
XDP_DB3_SDCONN_STATE_CHANGE
CPU_CFG<1>
CPU_CFG<17>
CPU_CFG<0>
XDP_BPM_L<0>
XDP_BPM_L<1>
XDP_BPM_L<2>
CPU_CFG<4>
XDP_CPU_PRDY_L
CPU_CFG<10>
CPU_CFG<11>
=SMBUS_XDP_SDA
XDP_CPU_TCK
XDP_BPM_L<3>
XDP_CPU_PREQ_L
=PPVCCIO_S0_XDP
ITPXDP_CLK100M_P
XDP_CPU_TDO
XDP_CPU_TRST_L
XDP_CPU_TDI
XDP_CPU_TMS
XDP_CPU_TCK
XDP_CPU_CFG<0>
PM_SYSRST_L
CPU_CFG<16>
XDP_DD2_AUD_IPHS_SWITCH_EN_PCH
XDP_DD1_JTAG_TBT_TCK
XDP_DD0_DP_TBT_SEL
XDP_DC0_ISOLATE_CPU_MEM_L
XDP_DD1_JTAG_TBT_TCK
TBT_CIO_PLUG_EVENT_R
XDP_FC1_TBT_CIO_PLUG_EVENT
XDP_PCH_TDI
XDP_DC3_SATARDRVR_EN
XDP_DC2_DP_AUXCH_ISOL
XDP_DC0_ISOLATE_CPU_MEM_L
XDP_PCH_TDI
XDP_PCH_TDO
XDP_DC2_DP_AUXCH_ISOL
XDP_DC1_GPU_GOOD
XDP_DA3_USB_EXTD_OC_L
AUD_IPHS_SWITCH_EN_PCH_R
ENET_LOW_PWR_PCH_R
PM_PGOOD_REG_CPUCORE_S0
XDP_BPM_L<7>
XDP_BPM_L<5>
XDP_BPM_L<4>
XDP_PCH_TDO
=SMBUS_XDP_SCL
XDP_PCH_PWRBTN_L
AP_PWR_EN_R
XDP_DD0_DP_TBT_SEL
XDP_DA2_USB_EXTC_OC_L
XDP_BPM_L<6>
CPU_CFG<0>
XDP_PCH_TMS
XDP_DD2_AUD_IPHS_SWITCH_EN_PCH
XDP_DC3_SATARDRVR_EN
ITPXDP_CLK100M_N
CPU_CFG<6>
CPU_CFG<5>
SATARDRVR_EN_R
CPU_PWRGD
JTAG_TBT_TCK_R
XDP_VR_READY
XDP_CPU_TRST_L
XDP_DBRESET_L
XDP_CPU_CLK100M_N
XDP_CPU_CLK100M_P
DP_AUXCH_ISOL_R
PM_PWRBTN_L
prefsb
051-9504
7.0.0
25 OF 143
25 OF 117
12
12
12
12
12
12
12
1
2
1
2
1
2
1
2
1
2
12
1
2
1
2
1
2
1
2
53
51
43
41
35
29
23
19
17
15
11
7
5
9
3
2
13
10
12
14
16
8
1
21
27
33
37
39
45
47
49
57
55
59
6
20
22
24
26
32
30
38
42
44
48
46
50
52
54
58
56
60
28
40
18
4
34
36
25
31
61
62
6364
53
51
43
41
35
29
23
19
17
15
11
7
5
9
3
2
13
10
12
14
16
8
1
21
27
33
37
39
45
47
49
57
55
59
6
20
22
24
26
32
30
38
42
44
48
46
50
52
54
58
56
60
28
40
18
4
34
36
25
31
61
62
6364
12
1
2
1
2
1
2
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
2
1
2
1
2
1
2
1
6
25
6
25
99
99
6
25
115
99
25 99
25 99
18 25 99
25 99
25 99
25 99
25 99
25 99
25 99
6
25
11 25 99
11 25 99
11 25 99
11 25 99
11 25 99
99
25 99
25 99
25 99
18 25 99
18 25 99
25 99
25 99
25 99
99
25 99
25 99
18 25 99
25 99
25 99
99
99
99
OUT
NCNC
OUT
OUT
IN
OUT
IN
IN
NCNC
OUT
OUT
IN
OUT
IN
OUT
OUT
NC
OUT
OUT
OUT
OUT
NC
NC
OUT
GND
VDD
25MHZ_A
VDDIO_B
VDDIO_A
VDDIO_C
25MHZ_B
25MHZ_C
THRM
XIN
XOUT
PAD
NC
OUT
OUT
OUT
OUT
OUT
Y
A
B
08
OUT
Y
A
B
08
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
MAY NEED TO MOVE LONGER TRACE ONES TO BUFFERED
PCH RTC Crystal
Reset Button
OPEN-DRAIN BUFFER
System 25MHz Clock Generator
PCH 25MHZ CLOCK
From GreenClk @ 1.8V
To PCH @ 1.1V
Ethernet XTAL Power
SB XTAL Power
TBT XTAL Power
Unbuffered
Platform Reset Connections
Buffered
ENET > S0 > TBT, so ENET is used here.
VDD must be powered if any VDDIO is.
GreenClk 25MHz Power
VTT VOLTAGE DIVIDER AND PU ON CPU PAGE
Clock series termination
511-0054
RDAR://11218892 TESTPOINT TO RESET RTC FOR APPLE CARE
GPIO Isolation to prevent glitches on critical core well GPIOs
Coin-Cell Holder
RTC Power Sources
NOTE: 30 PPM crystal required
19 25 47
115
1
1K
402
2
MF-LF
5%
1/16W
R2602
BAT54DW-X-G
SOT-363
D2600
33
MF-LF
402
5%
1/16W
R2681
MF-LF
R2690
1/16W
5%
402
33
49
112
75 82
113
18
101
18
101
20
114
PLACE_NEAR=U1800.AN14:10mm
MF-LF
33
5%
1/16W
402
R2626
PLACE_NEAR=U1800.AT11:10mm
MF-LF
402
33
5%
1/16W
R2625
20
101
49
101
47
101
20
101
18
101
R2627
PLACE_NEAR=U1800.AT14:10mm
33
402
1/16W
5%
MF-LF
20
101
20%
C2680
0.1UF
10V
CERM
402
MF-LF
5%
100K
1/16W
402
R2680
J2600
SM
BB10201-C1403-7H
MF-LF
402
10M
1/16W
5%
R2611
MC74VHC1G08
SOT23-5-HF
U2680
0.1UF
20%
10V
CERM
402
C2690
402
MF-LF
0
R2610
1/16W
5%
25 99
402
1K
XDP
MF-LF
R2699
5%
1/16W
35
112
1/16W
5%
402
MF-LF
33
R2688
1/16W
5%
402
MF-LF
33
R2655
SC70
U2690
74LVC1G07
XDP
R2698
1/16W
MF-LF
5%
1K
402
25 99
41
113
402
MF-LF
5%
1/16W
33
R2692
18
101
36
101
CERM
10V
20%
402
0.1UF
C2620
402
CERM
20%
0.1UF
10V
C2622C2624
0.1UF
402
20%
10V
CERM
0
5%
MF-LF
1/16W
R2605
402
NO STUFF
5%
MF-LF
402
1M
R2606
1/16W
39
101
PLACE_NEAR=U2600.4:10MM
MF-LF
1/16W
402
5%
33
R2628
CERM
6.3V
10%
1UF
402
C2602
U2600
CRITICAL
TDFN
SLG3NB146V
CRITICAL
32.768K-12.5PF
SM-HF
Y2610
SILK_PART=SYS RESET
0
5%
MF-LF
402
1/16W
R2696
NOSTUFF
47
116
R2694
VREFMRGN:EXT
33
5%
1/16W
MF-LF
402
28 34
114
11 99
38
15 36
117
PLACE_NEAR=U2650.8:2MM
C2650
20%
0.1UF
CERM
402
10V
74LVC2G08GT
U2650
8
4
CRITICAL
SOT833
60
PLACE_NEAR=U2660.5:2MM
C2660
20%
10V
CERM
0.1UF
402
SOT833
74LVC2G08GT
8
4
CRITICAL
U2650
U2660
SOT23-5-HF
MC74VHC1G08
39 41
113
MF-LF
402
5%
1/16W
4.7K
R2697
1/16W
402
MF-LF
140
1%
R2672
1%
402
MF-LF
1/16W
40.2
R2671
SW2600
NTC020AA1JB260T
SM
SILK_PART=SYS RESET
DEVELOPMENT
R2691
1/16W
MF-LF
5%
402
33
C2605
12PF
5%
50V
0402
C0G-CERM
0402
C0G-CERM
50V
5%
12PF
C2606
12PF
5%
50V
C0G-CERM
0402
C2610
PLACE_NEAR=Y2610.3:7MM
C2611
5%
50V
C0G-CERM
0402
PLACE_NEAR=Y2610.1:2MM
12PF
TP2601
1.97X2.02MM-NSP
OMIT
SMT-PAD
TP2603
1.4-SQ-NSP
SM-PAD
OMIT
SMT-PAD
OMIT
TP2600
1.97X2.02MM-NSP
TP2602
1.4-SQ-NSP
OMIT
SM-PAD
CRITICAL
3.2X2.5MM-SM
25.000MHZ-20PPM-12PF-85C
Y2605
SYNC_DATE=N/A
CHIPSET SUPPORT
SYNC_MASTER=D8_MLB
=PP3V3_S5_PCH
AUD_IPHS_SWITCH_EN
LPC_CLK33M_LPCPLUS
LPC_CLK33M_LPCPLUS_R
SYSCLK_CLK25M_X2
PCH_CLK32K_RTCX1
PM_PCH_PWROK
SYSCLK_CLK25M_X1
=PP3V3_G3H_RTC_D
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
PPVBATT_G3_RTC_R
PP3V3_G3_RTC
MIN_NECK_WIDTH=0.2MM
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.6MM
RTC_RESET_L
VOLTAGE=3.3V
PPVBATT_G3_RTC
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 MM
PCH_CLK33M_PCIOUT
ENET_LOW_PWR
PLT_RESET_L
MAKE_BASE=TRUE
TBT_PLT_RST_L
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SMC_LRESET_L
=PP3V3_S0_RSTBUF
PLT_RST_BUF_L
=TBT_RESET_L
AP_RESET_L
ENET_SD_RESET_L
=PP3V3_S5_PCH
LPC_PWRDWN_L
LPC_CLK33M_SMC_R
=PP1V8_S0_PCH_CLK
=PP3V3_TBT_CLK
SYSCLK_CLK25M_X2_R
GPU_RESET_L
DEBUG_RESET_L
LPC_CLK33M_SMC
SYSCLK_CLK25M_ENET_R
SYSCLK_CLK25M_ENET
SYSCLK_CLK25M_TBT
AUD_IPHS_SWITCH_EN_PCH
PM_PCH_PWROK
ENET_LOW_PWR_PCH
PCH_CLK25M_XTALIN
TBT_PWR_EN
=PP3V3_S5_PCH
TBT_PWR_EN_PCH
SYSCLK_CLK25M_SB
XDP_PCH_PLTRST_L
=PP3V3_S4_ENET_SYSCLK
SYSCLK_CLK25M_SB
PCH_CLK33M_PCIIN
=PP3V3_S0_RSTBUF
=PP3V3_S0_PCH_PM
=PP3V3_S4_ENET_CLK
SYSCLK_CLK25M_ENET_R
CPU_RESET_L
PM_SYSRST_L
PCH_CLK32K_RTCX2
PCH_CLK32K_RTCX2_R
XDP_CPU_PLTRST_L
PCA9557D_RESET_L
prefsb
051-9504
7.0.0
26 OF 143
26 OF 117
3
6
2
4
1
5
12
12
12
12
12
2
1
1
2
1
2
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2
5
1
2
3
4
2
1
12
12
12
12
4
13
2
5
12
12
2
1
2
1
2
1
12
1
2
12
2
1
9
2
5
367
4
8
11
1
10
41
1
2
12
2
1
7
2
1
2
1
3
6
5
5
1
2
3
4
1
2
1
2
12
132
4
12
12
12
12
12
1
1
1
1
42
13
6
19 24 26
101
15 19 26 35 43 65 89
115
101
6
116
6
115
18 48
116
116
6
26
114
6
19 24 26
19 47 49
114
6
6
101
26
101
21 99
15 19 26 35 43 65 89
115
15 21 99
6
19 24 26
18
117
26
101
6
26
101
6
26
6
6
26
101
101
BI
BI
BI
BI
NC
NC
NC
NC
TEST1
USBDM_DN1
USBDP_DN1
VBUS_DET
USBDP_DN2
USBDM_DN2
SUSP_IND/NON_REM0
VDD33
NC
XTALOUT
XTALIN/CLKIN
TEST
RESET*
HS_IND
NON_REM1
PLLFILT
CRFILT
VDD33
VDD33
VDD33
USBDM_UP
USBDP_UP
PRTPWR1
PRTPWR2
OCS1*
OCS2*
RBIAS
VDD33
EPAD
IN
NC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
NON_REM 0 and 1 are used to indicate whether the
downstream ports are removable or captive
NON_REM[1:0] = 1x ---> ports 1 and 2 are non-removable
via array to GND
NON_REM[1:0] = 01 ---> port 1 is non-removable
ePad needs a minimum of 3x3
NON_REM[1:0] = 00 ---> ports 1 and 2 are removable
155S0220
338S1076
50mV P-P spec @ 100k-1MHz
PLACE_NEAR=U2700.26:2MM
1%
402
1/16W
12K
R2707
MF
20
102
20
102
35
102
35
102
R2705
1/16W
5%
402
MF-LF
100K
R2708
402
100K
MF-LF
5%
1/16W
5%
10K
MF-LF
1/16W
402
R2703
C2705
6.3V
603
4.7UF
10%
X5R-CERM
1UF
10%
C2708
X5R
16V
402
402
MF-LF
5%
1M
1/16W
R2706
R2711
201
5%
1/20W
MF
4.7K
1/16W
402
R2704
100K
5%
MF-LF
USB2412-DZK
QFN
CRITICAL
U2700
MF-LF
0
5%
402
R2709
1/16W
35 64 74
115
5%
1/20W
R2710
MF
201
4.7K
0402
L2700
FERR-120-OHM-1.5A
50V
C2701
0402
C0G-CERM
5%
18PF
18PF
0402
50V
C0G-CERM
5%
C2702
MF-LF
5%
1K
402
R2712
1/16W
10%
0.01UF
402
C2712
16V
CERM
CRITICAL
Y2700
5X3.2X1.5-SM
24.000M-50PPM-16PF
X7R-CERM
16V
10%
0.1UF
0402
C2709
X7R-CERM
16V
10%
0.1UF
0402
C2710
X7R-CERM
16V
10%
0.1UF
0402
C2711
C2703
10%
0.1UF
0402
16V
X7R-CERM
10%
0.1UF
0402
16V
X7R-CERM
C2704
C2707
X7R-CERM
16V
10%
0.1UF
0402 0402
0.1UF
10%
16V
X7R-CERM
C2706
SYNC_DATE=03/23/2012
SYNC_MASTER=D8_ROSITA
USB 2.0 HUB (BT/SMC)
MIN_NECK_WIDTH=0.25MM
MAX_NECK_LENGTH=3MM
PP3V3_S4_USB_HUB_VDD
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.4MM
MAX_NECK_LENGTH=3MM
VOLTAGE=1.2V
PP1V2_USB_HUB_PLLFILT
MIN_LINE_WIDTH=0.4MM
PP1V2_USB_HUB_CRFILT
VOLTAGE=1.2V
MAX_NECK_LENGTH=3MM
MIN_NECK_WIDTH=0.2MM
USB_HUB_XTAL2_R
USB_HUB_XTAL1
PM_PGOOD_P3V3_S4_FET
USB_HUB_RESET_L
USB_HUB_NON_REM1
USB_HUB_XTAL2
USB_HUB_NON_REM0
USB_PCH_7_P
USB_HUB_RBIAS
USB_HUB_2N
USB_BT_P
=PP3V3_S4_USB_HUB
=PP3V3_S4_USB_HUB
USB_PCH_7_N
USB_BT_N
=PP3V3_S4_USB_HUB
=PP3V3_S4_USB_HUB
USB_HUB_HS_IND
USB_HUB_VBUS_DET
USB_HUB_2P
prefsb
051-9504
7.0.0
27 OF 143
27 OF 117
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2
1
2
1
2
1
2
2
1
2
1
1
2
1
2
1
2
15
28
1
18
3
2
19
14
5
23
24
6
17
16
13
25
92027
10
21
22
7
11
8
12
26
4
29
12
1
2
21
12
12
12
2
1
21
2
1
2
1
2
1
2
1
2
1
2
1
2
1
115
115
115
102
102
102
102
102
102
102
102
6
27
6
27
6
27
6
27
102
102
102
OUT
IN
G
D
S
OUT
D
SG
D
SG
D
SG
D
SG
NC
NC
IN
D
S
G
G
D
S
G
D
S
OUT
IN
IN
AY
NC NC
VCC
GND
NCNC
IN
IN
IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
MEMVTT_EN = CPU_PWRGD * PM_SLP_S3_L (VTT is enabled when PCH tells CPU to enable VCCORE)
MEMVTT Clamp actively holds MEMVTT rail low until MEMVTT is enabled.
Clamping MEMVTT will keep the MEM_CKE low until CPU actively controls it.
CPU does not drive MEM_CKE until VCCORE activated but CPU 1V5 (VDDQ) leaks into it.
MEMVTT_EN Generator
Enables MEMVTT when PCH drives CPU PWRGD.
MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L (Block CPU from driving MEM_RESET_L in S3)
as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.
The circuits below handle MEMVTT power during S0->S3->S0 transitions, as well
WHEN LOW: MEM_RESET_L IS ISOLATED.
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0 (*)
X
X
CPU_MEM_RESET_L
MEMVTT_EN
1
1
0
1
1
1
1
1
0
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
7
6
5
4
3
2
1
0
PM_SLP_S3_L
ISOLATE_CPU_MEM_L
Step
Rails will power-up as if from S3, but MEM_RESET_L now needs to be asserted in S0. Software
S0
to
S0
to
NOTE: On a S5->S0 transition, ISOLATE_CPU_MEM_L will default low.
must de-assert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.
(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO.
Ensures CKE signals are held low in S3 and in S0 before CPU PWRGD
75mA max load @ 0.75V
60mW max power
MEMVTT Clamp
PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page
With optional delay from 1V5 S0 PGOOD
1V5 S0 "PGOOD" for CPU
ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behaviour of signals.
WHEN HIGH: MEM_RESET_L NOT ISOLATED.
MEM_RESET_L Generator
rdar://11117167
S3
PLT_RESET_L equivalent
Open-drain buffer
CPU_PWRGD
CPU_MEM_RESET_L
CPU_MEM_RESET_L
1
MEM_RESET_L
0
Vih = 0.65 * Vcc = 0.65 * 1.05 = 0.68V
MF-LF
5%
1/16W
402
10K
R2802
28 64
114
28 64
114
100K
MF-LF
402
5%
1/16W
R2851
MF-LF
1/10W
10
603
5%
R2850
MF-LF
402
1/16W
R2820
5%
10K
CRITICAL
Q2820
SOT-563
DMB53D0UV
10K
MF-LF
5%
402
1/16W
R2822
SOT-563
DMB53D0UV
Q2820
CRITICAL
11 19 99
MF-LF
402
5%
10K
1/16W
R2810
Q2810
CRITICAL
SOT563
SSM6N15AFE
CRITICAL
Q2850
SSM6N15AFE
SOT563
Q2850
CRITICAL
SSM6N15AFE
SOT563
Q2810
SOT563
SSM6N15AFE
CRITICAL
74LVC1G07
SC70
U2820
64 74
115
R2985
402
MF-LF
5%
1/16W
20K
50V
C2899
402
10%
CERM
0.0022UF
Q2899
2N7002
SOT23-HF1
5%
1/16W
402
MF-LF
20K
R2897
Q2898
2N7002DW-X-G
SOT-363
R2898
20K
5%
1/16W
402
MF-LF
R2899
1/16W
5%
402
MF-LF
20K
Q2898
SOT-363
2N7002DW-X-G
29 30 31 32 97
21 34 99
11 99
C2821
X7R-CERM
16V
0402
20%
0.01UF
0.001UF
20%
0402
NOSTUFF
C2820
50V
CERM
50V
CERM
C2851
0.001UF
20%
0402
NOSTUFF
74AUP1G07GF
U2830
SOT891
CRITICAL
C2830
0.01UF
0402
X7R-CERM
16V
20%
402
5%
MF-LF
1/16W
0
R2831
402
0
1/16W
MF-LF
5%
NOSTUFF
R2832
R2830
1/16W
MF-LF
402
10K
5%
5
15 19 40 47 48 64
115
26 34
114
11 21
25 99
MF-LF
1/16W
0
5%
402
R2833
20%
0.01UF
16V
C2831
NOSTUFF
X7R-CERM
0402
SYNC_DATE=04/23/2012
CPU Memory S3 Support
SYNC_MASTER=D8_MARK
PM_PGOOD_REG_ALL_P1V05_S0_R
=PPVCCIO_S0_CPU
CPU_PWRGD
MEMVTT_EN
PCA9557D_RESET_L
CPU_PWRGD_3V3_R
PM_SLP_S3_L
=PPDDRVTT_S0_CLAMP
ISOLATE_CPU_MEM_5V
ISOLATE_CPU_MEM_L
CPU_MEM_RESET_L
MEM_RESET_L
=PP5V_S4_MEMRESET
=PPVDDQ_S3_MEMRESET
=PP3V3_S4_MEMRESET
=PP3V3_S4_PM
PM_MEM_PWRGD_L
PM_MEM_PWRGD
PM_PGOOD_FET_VDDQ_S0
MEMVTT_EN
PGOOD_P1V5_S0_DLY
=PP3V3_S0_PWRCTL
VTTCLAMP_EN
=PP3V3_S0_PWRCTL
=PP3V3_S4_MEMRESET
MIN_NECK_WIDTH=0.25mm
MIN_LINE_WIDTH=0.25mm
VTTCLAMP_L
CPU_PWRGD_1V05_R
ISOLATE_CPU_MEM_5V_L
CPU_PWRGD_3V3
MEMVTT_EN_L
prefsb
051-9504
7.0.0
28 OF 143
28 OF 117
1
2
1
2
1
2
1
2
4
5
3
1
2
6
2
1
1
2
3
4
5
6
1
2
3
4
5
6
1
2
4
13
2
5
1
2
2
1
1
32
1
2
3
5
4
1
2
1
2
6
2
1
2
1
2
1
2
1
2
4
1
5
63
2
1
12
12
1
2
12
2
1
64
115
6
10 11 13 16 66
112
6
114
6 6 6
28
6
115
114
6
28 74
117
6
28 74
6
28
117
114
112
114
BI
BIBI
BI
IN
BI
BI
BI
BI
BI
BI
BI
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
BI
BI
BI
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
NC
NC
NC
BI
DQ0
VREFDQ
VSS_1
VSS_3
DM0
VSS_12
DQ16
VSS_14
DQ18
VSS_21
VSS_24
DQ27
EVENT*
DQS7*
DQS6*
DQS5*
DQS4*
S1*
CAS*
S0*WE*
RAS*
CK1*CK0*
DQS3*
DQS2*
RESET*
DQS1*
DQS0*
DQ31
VDD_0
NC_0
BA2
VDD_2
A12/BC*
A9
A8
VSS_50
VTT_0
VDDSPD
SA1
SA0
DQ59
VSS_48
DQ58
DM7
VSS_47
DQ57
DQ56
VSS_45
DQ50
DQ51
DQ49
VSS_40
DQS6
VSS_43
DQ48
VSS_36
DQ42
DQ43
VSS_38
DM5
DQ40
VSS_35
VSS_33
DQ41
DQ35
VSS_28
DQS4
VSS_31
DQ34
DQ32
TEST
VDD_16
VSS_26
DQ33
VDD_10
VDD_6
A1
VDD_8
CK0
VDD_4
A5
CKE0
VSS_22
DM3
DQ26
VSS_19
DQ19
DQ25
DQ24
VSS_17
DQS2
DQ17
DQ10
DQ11
VSS_10
DQS1
VSS_8
DQ9
DQ8
VSS_6
DQ3
DQ2
SCL
SDA
VSS_49
DQ62
DQ63
VSS_51
DQS7
VTT_1
DM6
DQ53
VSS_41
VSS_42
DQ60
DQ61
VSS_46
DQ52
DQ45
VSS_34
VSS_39
DQS5
VSS_37
DQ46
DQ44
DQ47
VSS_32
DM4
VDD_17
VREFCA
VSS_27
DQ36
DQ37
VSS_29
VSS_30
DQ38
DQ39
BA1
VDD_11
VDD_13
ODT0
VDD_15
ODT1
NC_1
CK1
A0
A2
A6
A4
A11
A7
VDD_7
VDD_5
VDD_9
VDD_3
A14
A15
CKE1
VDD_1
VSS_25
DQ30
DQS3
VSS_23
DM2
DQ29
VSS_20
DQ28
DQ23
VSS_18
VSS_16
DQ22
VSS_15
DQ21
DM1
DQ13
VSS_9
VSS_11
DQ14
DQ15
VSS_13
DQ20
DQ12
VSS_7
VSS_4
DQ1
DQ7
DQ6
DQ4
DQ5
DQS0
VSS_5
VSS_2
VSS_0
VSS_44
DQ55
DQ54
A3
A10_AP
BA0
VDD_12
VDD_14
A13
KEY
SYM 1 OF 2
SYM 2 OF 2
MTG HOLE
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
P/N: 516S1030
Power aliases required by this page:
- =PPDDRVTT_S0_MEM_A
- =I2C_SODIMMA_SDA
BOM options provided by this page:
- =PPVDDQ_S3_MEM_A
- =PP1V5_S0_MEM_A
(NONE)
Page Notes
- =I2C_SODIMMA_SCL
- =PPSPD_S0_MEM_A (2.5 - 3.3V)
Signal aliases required by this page:
DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)
30 33
30 33
10V
CERM
C2931
20%
0.1UF
402
CERM
20%
402-LF
2.2UF
C2930
6.3V
30 33
30 33
12 97
30 33
30 33
30 33
30 33
30 33
30 33
30 33
28 30 31 32 97
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
12 30 97
12 30 97
12 30 97
12 30 97
12 30 97
12 30 97
12 30 97
12 30 97
12 97
12 97
12 30 97
12 30 97
12 97
12 97
30 33
30 33
30 33
30 33
30 33
12 97
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
10V
20%
402
CERM
0.1UF
C2936
6.3V
C2935
20%
402-LF
CERM
2.2UF
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 31 32 47 48
114
30
50
30 50
12 97
12 30 97
12 30 97
12 30 97
12 30 97
12 30 97
12 30 97
12 30 97
12 97
12 97
12 30 97
12 30 97
12 30 97
12 30 97
12 30 97
12 97
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
10K
5%
R2941
MF-LF
402
1/16W
10K
R2940
1/16W
5%
402
MF-LF
20%
6.3V
CERM
402-LF
C2940
2.2UF
C2900
6.3V
20%
603
X5R
10UF
C2901
6.3V
603
X5R
10UF
20%
C2910
0.1UF
CERM
20%
10V
402
C2911
0.1UF
402
20%
10V
CERM
C2912
10V
20%
402
CERM
0.1UF
C2913
0.1UF
CERM
402
20%
10V 10V
20%
C2914
CERM
402
0.1UF
C2915
10V
20%
402
CERM
0.1UF
20%
C2916
10V
402
CERM
0.1UF
CERM
C2917
0.1UF
402
20%
10V
C2918
10V
20%
402
CERM
0.1UF
C2919
10V
20%
402
CERM
0.1UF
10V
20%
402
CERM
0.1UF
C2920 C2921
402
20%
10V
CERM
0.1UF
C2922
10V
20%
402
CERM
0.1UF
C2923
20%
402
CERM
0.1UF
10V
1UF
X5R
402
10%
10V
C2953C2952
10V
10%
402
X5R
1UF
C2951
1UF
X5R
402
10%
10V
C2950
10V
10%
402
X5R
1UF
30 33
F-ANG-SM-2
J2900
SODIMM-P0.60-D8
F-ANG-SM-2
J2900
SODIMM-P0.60-D8
SYNC_MASTER=D8_KOSECOFF
DDR3 SO-DIMM Connector A Slot0
SYNC_DATE=03/19/2012
=MEM_A_DQ<4>
MEM_A_CKE<0>
=PPVDDQ_S3_MEM_A
MEM_A_WE_L
=MEM_A_DQ<0>
=PPDDRVREF_DQ_MEM_A
=MEM_A_DQ<16>
=MEM_A_DQ<18>
=MEM_A_DQ<27>
MEM_EVENT_L
=MEM_A_DQS_N<7>
=MEM_A_DQS_N<6>
=MEM_A_DQS_N<5>
=MEM_A_DQS_N<4>
MEM_A_CS_L<1>
MEM_A_CAS_L
MEM_A_CS_L<0>
MEM_A_RAS_L
MEM_A_CLK_N<1>MEM_A_CLK_N<0>
=MEM_A_DQS_N<3>
=MEM_A_DQS_N<2>
=MEM_A_DQS_N<0>
=MEM_A_DQ<31>
MEM_A_BA<2>
MEM_A_A<12>
MEM_A_A<9>
MEM_A_A<8>
=PPDDRVTT_S0_MEM_A
=PP3V3_S0_MEM_A_SPD
MEM_DIMM0_SA<1>
MEM_DIMM0_SA<0>
=MEM_A_DQ<59>
=MEM_A_DQ<58>
=MEM_A_DQ<57>
=MEM_A_DQ<56>
=MEM_A_DQ<50>
=MEM_A_DQ<51>
=MEM_A_DQ<49>
=MEM_A_DQS_P<6>
=MEM_A_DQ<48>
=MEM_A_DQ<42>
=MEM_A_DQ<43>
=MEM_A_DQ<40>
=MEM_A_DQ<41>
=MEM_A_DQ<35>
=MEM_A_DQS_P<4>
=MEM_A_DQ<34>
=MEM_A_DQ<32>
=MEM_A_DQ<33>
MEM_A_A<1>
MEM_A_CLK_P<0>
MEM_A_A<5>
=MEM_A_DQ<26>
=MEM_A_DQ<19>
=MEM_A_DQ<25>
=MEM_A_DQ<24>
=MEM_A_DQS_P<2>
=MEM_A_DQ<17>
=MEM_A_DQ<10>
=MEM_A_DQ<11>
=MEM_A_DQS_P<1>
=MEM_A_DQ<8>
=I2C_SODIMMA_SCL
=I2C_SODIMMA_SDA
=MEM_A_DQ<62>
=MEM_A_DQ<63>
=MEM_A_DQS_P<7>
=PPDDRVTT_S0_MEM_A
=MEM_A_DQ<53>
=MEM_A_DQ<60>
=MEM_A_DQ<61>
=MEM_A_DQ<52>
=MEM_A_DQ<45>
=MEM_A_DQS_P<5>
=MEM_A_DQ<46>
=MEM_A_DQ<44>
=MEM_A_DQ<47>
=PPVDDQ_S3_MEM_A
=PPDDRVREF_CA_MEM_A
=MEM_A_DQ<36>
=MEM_A_DQ<37>
=MEM_A_DQ<38>
=MEM_A_DQ<39>
MEM_A_BA<1>
MEM_A_ODT<0>
MEM_A_ODT<1>
MEM_A_CLK_P<1>
MEM_A_A<0>
MEM_A_A<2>
MEM_A_A<6>
MEM_A_A<4>
MEM_A_A<11>
MEM_A_A<7>
MEM_A_A<14>
MEM_A_A<15>
MEM_A_CKE<1>
=MEM_A_DQ<30>
=MEM_A_DQS_P<3>
=MEM_A_DQ<29>
=MEM_A_DQ<28>
=MEM_A_DQ<23>
=MEM_A_DQ<22>
=MEM_A_DQ<21>
=MEM_A_DQ<13>
=MEM_A_DQ<14>
=MEM_A_DQ<20>
=MEM_A_DQ<12>
=MEM_A_DQ<1>
=MEM_A_DQ<7>
=MEM_A_DQ<6>
=MEM_A_DQ<5>
=MEM_A_DQS_P<0>
=MEM_A_DQ<55>
=MEM_A_DQ<54>
MEM_A_A<3>
MEM_A_A<10>
MEM_A_BA<0>
MEM_A_A<13>
MEM_DIMM0_SA<0>
=PP3V3_S0_MEM_A_SPD
MEM_DIMM0_SA<1>
MEM_RESET_L
=MEM_A_DQ<15>
=MEM_A_DQS_N<1>
=MEM_A_DQ<9>
=MEM_A_DQ<2>
=MEM_A_DQ<3>
prefsb
051-9504
7.0.0
29 OF 143
29 OF 117
2
1
2
1
2
1
2
1
1
2
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
5
1
3
9
11
37
39
43
51
61
71
69
198
186
169
152
135
121
115
114113
110
104103
62
45
30
27
10
70
75
77
79
81
83
85
89
195
203
199
201
197
193
189
191
187
185
183
181
179
175
177
165
167
171
173
163
155
157
159
161
153
147
151
145
149
143
133
137
139
141
129
125
123
127
131
105
93
97
99
101
87
91
73
65
63
67
55
53
59
57
49
47
41
33
35
31
29
25
23
21
19
17
15
202
200
190
192
194
196
188
204
170
166
168
172
180
182
184
164
148
150
162
154
156
158
146
160
144
136
124
126
128
130
132
134
138
140
142
108
106
112
116
118
120
122
102
98
96
90
92
84
86
94
88
100
82
80
78
74
76
72
68
64
66
46
58
60
56
52
54
48
50
44
42
28
24
26
32
34
36
38
40
22
20
13
7
18
16
4
6
12
14
8
2
178
176
174
95
107
109
111
117
119
205
206
207
208
209
6
29 30
6
30
6
29 30
6
29 30
29
29
6
29 30
6
29 30
6
30
29
6
29 30
29
BI
BIBI
BI
IN
BI
BI
BI
BI
BI
BI
BI
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
BI
BI
BI
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
NC
NC
NC
BI
DQ0
VREFDQ
VSS_1
VSS_3
DM0
VSS_12
DQ16
VSS_14
DQ18
VSS_21
VSS_24
DQ27
EVENT*
DQS7*
DQS6*
DQS5*
DQS4*
S1*
CAS*
S0*WE*
RAS*
CK1*CK0*
DQS3*
DQS2*
RESET*
DQS1*
DQS0*
DQ31
VDD_0
NC_0
BA2
VDD_2
A12/BC*
A9
A8
VSS_50
VTT_0
VDDSPD
SA1
SA0
DQ59
VSS_48
DQ58
DM7
VSS_47
DQ57
DQ56
VSS_45
DQ50
DQ51
DQ49
VSS_40
DQS6
VSS_43
DQ48
VSS_36
DQ42
DQ43
VSS_38
DM5
DQ40
VSS_35
VSS_33
DQ41
DQ35
VSS_28
DQS4
VSS_31
DQ34
DQ32
TEST
VDD_16
VSS_26
DQ33
VDD_10
VDD_6
A1
VDD_8
CK0
VDD_4
A5
CKE0
VSS_22
DM3
DQ26
VSS_19
DQ19
DQ25
DQ24
VSS_17
DQS2
DQ17
DQ10
DQ11
VSS_10
DQS1
VSS_8
DQ9
DQ8
VSS_6
DQ3
DQ2
SCL
SDA
VSS_49
DQ62
DQ63
VSS_51
DQS7
VTT_1
DM6
DQ53
VSS_41
VSS_42
DQ60
DQ61
VSS_46
DQ52
DQ45
VSS_34
VSS_39
DQS5
VSS_37
DQ46
DQ44
DQ47
VSS_32
DM4
VDD_17
VREFCA
VSS_27
DQ36
DQ37
VSS_29
VSS_30
DQ38
DQ39
BA1
VDD_11
VDD_13
ODT0
VDD_15
ODT1
NC_1
CK1
A0
A2
A6
A4
A11
A7
VDD_7
VDD_5
VDD_9
VDD_3
A14
A15
CKE1
VDD_1
VSS_25
DQ30
DQS3
VSS_23
DM2
DQ29
VSS_20
DQ28
DQ23
VSS_18
VSS_16
DQ22
VSS_15
DQ21
DM1
DQ13
VSS_9
VSS_11
DQ14
DQ15
VSS_13
DQ20
DQ12
VSS_7
VSS_4
DQ1
DQ7
DQ6
DQ4
DQ5
DQS0
VSS_5
VSS_2
VSS_0
VSS_44
DQ55
DQ54
A3
A10_AP
BA0
VDD_12
VDD_14
A13
KEY
SYM 1 OF 2
SYM 2 OF 2
MTG HOLE
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
- =I2C_SODIMMA_SDA
- =PPDDRVTT_S0_MEM_A
Page Notes
- =PP1V5_S0_MEM_A
- =PPSPD_S0_MEM_A (2.5 - 3.3V)
- =I2C_SODIMMA_SCL
BOM options provided by this page:
(NONE)
Signal aliases required by this page:
- =PPVDDQ_S3_MEM_A
Power aliases required by this page:
DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)
P/N: 516S1030
29 33
29 33
402
CERM
C3031
20%
10V
0.1UF
CERM
2.2UF
402-LF
20%
6.3V
C3030
29 33
29 33
12 97
29 33
29 33
29 33
29 33
29 33
29 33
29 33
28 29 31 32 97
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
12 29 97
12 29 97
12 29 97
12 29 97
12 29 97
12 29 97
12 29 97
12 29 97
12 97
12 97
12 29 97
12 29 97
12 97
12 97
29 33
29 33
29 33
29 33
29 33
12 97
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
C3036
0.1UF
CERM
402
20%
10V
402-LF
CERM
C3035
2.2UF
20%
6.3V
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 31 32 47 48
114
29
50
29 50
12 97
12 29 97
12 29 97
12 29 97
12 29 97
12 29 97
12 29 97
12 29 97
12 97
12 97
12 29 97
12 29 97
12 29 97
12 29 97
12 29 97
12 97
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
R3041
10K
MF-LF
402
5%
1/16W
1/16W
R3040
10K
MF-LF
5%
402
C3040
6.3V
20%
402-LF
CERM
2.2UF
C3000
6.3V
20%
603
X5R
10UF
C3001
6.3V
20%
603
X5R
10UF
C3010
0.1UF
CERM
402
20%
10V
C3011
0.1UF
CERM
402
20%
10V
C3012
0.1UF
CERM
402
20%
10V
C3013
0.1UF
CERM
402
20%
10V
C3014
0.1UF
CERM
402
20%
10V
C3015
0.1UF
CERM
402
20%
10V
C3016
0.1UF
10V
20%
402
CERM
C3017
0.1UF
20%
10V
CERM
402
C3018
CERM
402
10V
20%
0.1UF 0.1UF
CERM
10V
C3019
20%
402
C3020
402
CERM
10V
20%
0.1UF
C3021
10V
20%
402
CERM
0.1UF
C3022
10V
20%
402
CERM
0.1UF 0.1UF
C3023
10V
20%
402
CERM
C3053
10V
10%
1UF
X5R
402
C3052
10V
10%
402
X5R
1UF1UF
C3051
10V
10%
X5R
402402
C3050
1UF
10%
X5R
10V
29 33
F-ANG-SM-2
J3000
SODIMM-P0.60-D8
F-ANG-SM-2
J3000
SODIMM-P0.60-D8
SYNC_DATE=03/19/2012
DDR3 SO-DIMM Connector A Slot1
SYNC_MASTER=D8_KOSECOFF
=PP3V3_S0_MEM_A_SPD
=PP3V3_S0_MEM_A_SPD
MEM_DIMM1_SA<0>
MEM_DIMM1_SA<1>
MEM_A_A<13>
MEM_A_BA<0>
MEM_A_A<10>
MEM_A_A<3>
=MEM_A_DQ<54>
=MEM_A_DQ<55>
=MEM_A_DQS_P<0>
=MEM_A_DQ<5>
=MEM_A_DQ<4>
=MEM_A_DQ<6>
=MEM_A_DQ<7>
=MEM_A_DQ<1>
=MEM_A_DQ<12>
=MEM_A_DQ<20>
=MEM_A_DQ<15>
=MEM_A_DQ<14>
=MEM_A_DQ<13>
=MEM_A_DQ<21>
=MEM_A_DQ<22>
=MEM_A_DQ<23>
=MEM_A_DQ<28>
=MEM_A_DQ<29>
=MEM_A_DQS_P<3>
=MEM_A_DQ<30>
MEM_A_CKE<3>
MEM_A_A<15>
MEM_A_A<14>
MEM_A_A<7>
MEM_A_A<11>
MEM_A_A<4>
MEM_A_A<6>
MEM_A_A<2>
MEM_A_A<0>
MEM_A_CLK_P<3>
MEM_A_ODT<3>
MEM_A_ODT<2>
MEM_A_BA<1>
=MEM_A_DQ<39>
=MEM_A_DQ<38>
=MEM_A_DQ<37>
=MEM_A_DQ<36>
=PPDDRVREF_CA_MEM_A
=PPVDDQ_S3_MEM_A
=MEM_A_DQ<47>
=MEM_A_DQ<44>
=MEM_A_DQ<46>
=MEM_A_DQS_P<5>
=MEM_A_DQ<45>
=MEM_A_DQ<52>
=MEM_A_DQ<61>
=MEM_A_DQ<60>
=MEM_A_DQ<53>
=PPDDRVTT_S0_MEM_A
=MEM_A_DQS_P<7>
=MEM_A_DQ<63>
=MEM_A_DQ<62>
=I2C_SODIMMA_SDA
=I2C_SODIMMA_SCL
=MEM_A_DQ<2>
=MEM_A_DQ<3>
=MEM_A_DQ<8>
=MEM_A_DQ<9>
=MEM_A_DQS_P<1>
=MEM_A_DQ<11>
=MEM_A_DQ<10>
=MEM_A_DQ<17>
=MEM_A_DQS_P<2>
=MEM_A_DQ<24>
=MEM_A_DQ<25>
=MEM_A_DQ<19>
=MEM_A_DQ<26>
MEM_A_CKE<2>
MEM_A_A<5>
MEM_A_CLK_P<2>
MEM_A_A<1>
=MEM_A_DQ<33>
=MEM_A_DQ<32>
=MEM_A_DQ<34>
=MEM_A_DQS_P<4>
=MEM_A_DQ<35>
=MEM_A_DQ<41>
=MEM_A_DQ<40>
=MEM_A_DQ<43>
=MEM_A_DQ<42>
=MEM_A_DQ<48>
=MEM_A_DQS_P<6>
=MEM_A_DQ<49>
=MEM_A_DQ<51>
=MEM_A_DQ<50>
=MEM_A_DQ<56>
=MEM_A_DQ<57>
=MEM_A_DQ<58>
=MEM_A_DQ<59>
MEM_DIMM1_SA<0>
MEM_DIMM1_SA<1>
=PP3V3_S0_MEM_A_SPD
=PPDDRVTT_S0_MEM_A
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<12>
MEM_A_BA<2>
=PPVDDQ_S3_MEM_A
=MEM_A_DQ<31>
=MEM_A_DQS_N<0>
=MEM_A_DQS_N<1>
MEM_RESET_L
=MEM_A_DQS_N<2>
=MEM_A_DQS_N<3>
MEM_A_CLK_N<2> MEM_A_CLK_N<3>
MEM_A_RAS_L
MEM_A_WE_L
MEM_A_CS_L<2>
MEM_A_CAS_L
MEM_A_CS_L<3>
=MEM_A_DQS_N<4>
=MEM_A_DQS_N<5>
=MEM_A_DQS_N<6>
=MEM_A_DQS_N<7>
MEM_EVENT_L
=MEM_A_DQ<27>
=MEM_A_DQ<18>
=MEM_A_DQ<16>
=PPDDRVREF_DQ_MEM_A
=MEM_A_DQ<0>
prefsb
051-9504
7.0.0
30 OF 143
30 OF 117
2
1
2
1
2
1
2
1
1
2
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
5
1
3
9
11
37
39
43
51
61
71
69
198
186
169
152
135
121
115
114113
110
104103
62
45
30
27
10
70
75
77
79
81
83
85
89
195
203
199
201
197
193
189
191
187
185
183
181
179
175
177
165
167
171
173
163
155
157
159
161
153
147
151
145
149
143
133
137
139
141
129
125
123
127
131
105
93
97
99
101
87
91
73
65
63
67
55
53
59
57
49
47
41
33
35
31
29
25
23
21
19
17
15
202
200
190
192
194
196
188
204
170
166
168
172
180
182
184
164
148
150
162
154
156
158
146
160
144
136
124
126
128
130
132
134
138
140
142
108
106
112
116
118
120
122
102
98
96
90
92
84
86
94
88
100
82
80
78
74
76
72
68
64
66
46
58
60
56
52
54
48
50
44
42
28
24
26
32
34
36
38
40
22
20
13
7
18
16
4
6
12
14
8
2
178
176
174
95
107
109
111
117
119
205
206
207
208
209
6
29 30
6
29 30
30
30
6
29
6
29 30
6
29 30
30
30
6
29 30
6
29 30
6
29 30
6
29
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