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CORNHOLIO
User Manual
83 pgs1.78 Mb0

Apple CORNHOLIO User Manual

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8 7
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
6
5
4
SCHEMATIC,CORNHOLIO
3
REV
? ?
ZONE
DESCRIPTION OF CHANGE
ECN
?
CK APPD
DATE
? ?
ENG APPD
DATE
5/12/2009
D
Page
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B
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10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
(.csa)
1
1 2 3 4 5 6 7 8 9
Table of Contents
2
System Block Diagram
3
Power Block Diagram
4
BOM Configuration
5
Revision History
7
Functional / ICT Test
8
Power Aliases
9
Signal Aliases
10
CPU FSB
11
CPU Power & Ground
12
CPU Decoupling
13
eXtended Debug Port(MiniXDP)
14
MCP CPU Interface
15
MCP Memory Interface
16
MCP Memory Misc
17
MCP PCIe Interfaces
18
MCP Ethernet & Graphics
19
MCP PCI & LPC
20
MCP SATA & USB
21
MCP HDA & MISC
22
MCP Power & Ground
25
MCP Standard Decoupling
26
MCP Graphics Support
28
SB Misc
29
FSB/DDR3 Vref Margining
31
DDR3 SO-DIMM Connector A
32
DDR3 SO-DIMM Connector B
33
DDR3 Support
34
Right Clutch Connector
35
SECUREDIGITAL CARD READER
37
Ethernet PHY (RTL8211CL)
38
Ethernet & AirPort Support
39
Ethernet Connector
41
FireWire LLC/PHY (FW643E)
42
FireWire Port Power
43
FireWire Ports
45
SATA Connectors
46
External USB Connectors
48
Front Flex Support
49
SMC
50
SMC Support
51
LPC+SPI Debug Connector
Contents
Sync
N/A
N/A
DRAGON
N/A
N/A
N/A
N/A
WFERRY_K19I
K24_MLB
K24_MLB
K24_MLB
K19_MLB
T18_MLB
T18_MLB
T18_MLB
T18_MLB
T18_MLB
T18_MLB
T18_MLB
T18_MLB
T18_MLB
T18_MLB
K19_MLB
WFERRY_K19I
K24_MLB
K19_MLB
K19_MLB
T18_MLB
K19_MLB
K19_MLB
(K19I_MLB)
K19_MLB
K19_MLB
T18_MLB
K19_MLB
K19_MLB
K19_MLB
K19_MLB
K19_MLB
T18_MLB
(K19_MLB)
K19_MLB
Date
N/A
N/A
03/13/2008
N/A
N/A
N/A
N/A
01/13/2009
02/05/2009
02/05/2009
02/05/2009
02/05/2009
02/05/2009
02/05/2009
02/05/2009
02/05/2009
02/05/2009
02/05/2009
02/05/2009
02/05/2009
02/05/2009
02/05/2009
02/05/2009
01/06/2009
02/05/2009
02/05/2009
02/05/2009
02/05/2009
03/04/2009
03/23/2009
02/05/2009
02/05/2009
03/13/2009
02/05/2009
03/18/2009
02/05/2009
03/23/2009
02/05/2009
02/05/2009
02/05/2009
(11/25/2008)
02/05/2009
Page
TABLE_TABLEOFCONTENTS_HEAD
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
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TABLE_TABLEOFCONTENTS_ITEM
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TABLE_TABLEOFCONTENTS_ITEM
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TABLE_TABLEOFCONTENTS_ITEM
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43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83
(.csa)
52
K19i SMBus Connections
53
VOLTAGE SENSING
54
Current Sensing
55
Thermal Sensors
56
Fan
57
WELLSPRING 1
58
WELLSPRING 2
59
Sudden Motion Sensor (SMS)
60
DEBUG SENSORS AND ADC
61
SPI ROM
62
AUDIO: CODEC/REGULATOR
63
AUDIO: LINE INPUT FILTER
65
AUDIO: HEADPHONE FILTER
66
AUDIO:SPEAKER AMP
67
AUDIO: JACKS
68
AUDIO: JACK TRANSLATORS
69
DC-In & Battery Connectors
70
PBus Supply & Battery Charger
71
IMVP6 CPU VCore Regulator
72
5V / 3.3V Power Supply
73
1.5V DDR3 Supply
75
MCP CORE REGULATOR
76
CPU VTT Power Supply
77
MISC POWER SUPPLIES
78
POWER SEQUENCING
79
POWER FETS
90
LVDS Display Connector
93
DISPLAYPORT SUPPORT
94
DisplayPort Connector
97
LCD BACKLIGHT DRIVER
98
LCD Backlight Support
99
LCD Backlight Driver (MC34845)
100
CPU/FSB Constraints
101
Memory Constraints
102
MCP Constraints 1
103
MCP Constraints 2
104
Ethernet Constraints
105
FireWire Constraints
106
SMC Constraints
108
K19i Specific Constraints
109
K19i PCB Rule Definitions
Contents
Sync
WFERRY_K19I
K24_MLB
WFERRY_K19I
K24_MLB
K24_MLB
K24_MLB
K24_MLB
K19_MLB
K19_MLB
K19_MLB
K19_MLB
K19_MLB
K19_MLB
K19_MLB
CASEYHARDY_K19
K19_MLB
K19_MLB
K19_MLB
K19_MLB
WFERRY_K19I
K19_MLB
K19_MLB
(K19_MLB)
K24_MLB
K24_MLB
K24_MLB
K19_MLB
K24_MLB
K19_MLB
K19_MLB
K24_MLB
VEMURI_K19I
T18_MLB
T18_MLB
T18_MLB
T18_MLB
T18_MLB
T18_MLB
T18_MLB
WFERRY_K19I
WFERRY_K19I
Date
12/12/2008
02/05/2009
12/16/2008
02/05/2009
02/05/2009
02/05/2009
02/25/2009
02/05/2009
03/25/2009
02/05/2009
03/17/2009
03/02/2009
02/05/2009
02/05/2009
03/20/2009
03/17/2009
03/18/2009
03/18/2009
02/05/2009
01/13/2009
02/04/2009
02/03/2009
(12/05/2008)
02/25/2009
02/05/2009
03/12/2009
02/05/2009
12/19/2008
02/05/2009
02/10/2009
03/16/2009
02/09/2009
02/05/2009
02/05/2009
02/05/2009
02/05/2009
02/05/2009
02/05/2009
02/05/2009
01/08/2009
12/12/2008
D
C
B
DIMENSIONS ARE IN MILLIMETERS
XX
A
Integration Issues to be Resolved
IN
MAKE_BASE=TRUE
XDP_TDO
IN
MAKE_BASE=TRUE
(Should rename J1300 nets now that JTAG level-shifter is gone)
8
JTAG_MCP_TDOJTAG_MCP_TDO XDP_TDO
7 6
OUT
OUT
5
4
X.XX
X.XXX
ANGLES
DO NOT SCALE DRAWING
THIRD ANGLE PROJECTION
DRAFTER
ENG APPD
QA APPD
RELEASE
3
METRIC
MATERIAL/FINISH
NOTED AS
APPLICABLE
DESIGN CK
MFG APPD
DESIGNER
SCALE
NONE
SIZE
2
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
TITLE
DRAWING NUMBER
D
APPLE INC.
051-7903
SHT
1
REV.
A
OF
1 83
A
8 7
6
U1000
INTEL CPU
2.X OR 3.X GHZ PENRYN
PG 9
5
U1300
XDP CONN
PG 12
4
3
FSB
D
PG 13
GPIOs
FSB INTERFACE
64-Bit
800/1067/1333 MHz
MAIN
MEMORY
PG 14
2 UDIMMs
DDR2-800MHZ
DDR3-1067/1333MHZ
J2900
DIMM
PG 25,26
J6950
U4900
DC/BATT
PG 60
D
POWER SUPPLY
TEMP SENSOR
CLK
SYNTH
J4510
SATA Conn
PG 38
HD
J4520
SATA Conn
PG 38
C
ODD
1.05V/3GHZ.
1.05V/3GHZ.
SATA
PG 19
NVIDIA
MCP79
U1400
J9000
LVDS CONN
PG 71
J9400
DISPLAY PORT
CONN
PG 71
LVDS OUT
RGB OUT
DP OUT
HDMI OUT
DVI OUT
TMDS OUT
PG 17
UP TO 20 LANES3
PCI-E
PG 16
B
RGMII
PG 17
PCI
(UP TO FOUR PORTS)
PG 18
Misc
PG 24
SPI
PG 20
LPC
PG 18
PWR
CTRL
J4720
Bluetooth
USB
PG 19
4 3 8 9 2
(UP TO 12 DEVICES)
10 5 6 7
SMB
PG 20
HDA
PG 20
PG 40
U6100
SPI
Boot ROM
PG 52
J4700
TRACKPAD/
KEYBOARD
PG 40
DIMM’s
J4710
J4900
IR
PG 40
B,0
BSB
SMC
PG 41
J4710
FanADC
CAMERA
PG 40
SMB
CONN
PG 44
J5650,5600,5610,5611,5660,5720,5730,5750
FAN CONN AND CONTROL
Ser Prt
J3900,4635,4655
EXTERNAL
USB
Connectors
PG 41
POWER SENSE
PG 45
PG 48,49
J5100
Port80,serial
PG 39
LPC Conn
PG 43
C
B
U6200
U3700
A
J3400 U3900
Mini PCI-E
AirPort
PG 28
8
7 6
GB
E-NET
88E1116
PG 31
E-NET
Conn
PG 33
5
U6301 U6500U6400
Line In
Amp
PG 54
HEADPHONE
Amp Amp
J6800,6801,6802,6803
4
Audio Codec
PG 53
Audio Conns
PG 59
Line Out
PG 56PG 55
U6600,6605,6610,6620
Speaker
Amps
PG 57
System Block Diagram
OF
2
1
SYNC_DATE=N/A
REV.
A
83
A
SYNC_MASTER=N/A
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
APPLE INC.
3
2
SCALE
D
NONE
051-7903
SHT
8 7
6
5
4
POWER SYSTEM ARCHITECTURE
3
D
ADAPTER
3S2P
(9 TO 12.6V)
C
PCI_RESET0#
15-1
B
A
AC
IN
J6950
MCP79
PM_SLP_S4_L
SLP_S3#
U1400
PM_SLP_S3_L
RC
DELAY
RC
DELAY
RC
DELAY
RC
DELAY
DCIN(16.5V)
11
15
15
Q3801
PM_SLP_S3_L
P1V8S0_EN
MCPDDR_EN
CPUVTTS0_EN
MCPCORES0_EN
6A FUSE
SMC_DCIN_ISENSE
BATT_POS_F
11-1
11-3
RC DELAY
11-2
RC DELAY
PM_ENET_EN_L
Q3802
16-3
16-2
16-3
16-4
01
U7970
A
Q7050
P3V3S3_EN
DDRREG_EN
P5VLTS3_EN
16
WOL_EN SMC_ADAPTER_EN
P1V05S0_EN
(S0)
P3V3S0_EN
(S0)
PBUSVSENS_EN
(S0)
P5VRTS0_EN_L
(S0)
CHGR_EN
(S5)
ENABLES
VIN
PBUS SUPPLY/ BATTERY CHARGER
ISL6258A
U7000
PPVBAT_G3H_CHGR_OUT
CHGR_BGATE
04-1
=DDRREG_EN
=DDTVTT_EN
16-2
16-2
16-2
16-1
SMC
U4900
BKLT_EN
VOUT
P16
P60
PPVBAT_G3H_CHGR_REG
01
PPBUS_G3H
04
SMC_PM_G2_EN
(S5)
02
VIN
GOSHAWK6P
U9701
ENA
ENETADD_EN
P1V2ENET_EN
02
VIN
1.5V
S5 S3
0.75V
TPS51116
U7300
MCPCORES0_EN
P5VLTS3_EN
11-2
D6905
D6905
U5403
SMC_BATT_ISENSE
A
RC DELAY
Q7800
PPVOUT_S0_LCDBKLT
VOUT
1.2V YUKON
U3850
VIN
RUN1
LTC34074
RUN2
VOUT1
VOUT2
14
02
7A FUSE
02
IMVP_VR_ON
25
06
P1V05_S5_EN
P5VRTS0_EN_L
05
P3V3S5_EN_L
SMC_PM_G2_EN
(1.9V) PPVOUT_ENET_AVDD_REG
VOUT1
(0.8A MAX CURRENT)
PP1V2_ENET_REG
VOUT2
(0.8A MAX CURRENT)
S3 TO S0
FETS
(Q7901 & Q7971)
MCP_CORE
EN2
EN1
VIN
5V (LT)
ISL6236
U7500
VOUT2
VOUT1
PPVIN_G3H_P3V42G3H
PBUS_VSENSE
PPBUS_G3H
CPUVTTS0_EN
(S0)
CPU VCORE
VIN
ISL9504B
VR_ON
PP1V5_S0_FET
PPVCORE_S0_MCP_REG_R
(25A MAX CURRENT)
PP5VLT_S3_REG
(7A MAX CURRENT)
VOUT
PGOOD
U7400
06
02
VIN
5V
(RT)
3.3V
VOUT1
VOUT2
EN1
EN2
TPS51125
U7200
PGOOD1,2
VREG3
P5V3V3_PGOOD
PP1V5_S3_REG
(12A MAX CURRENT)
PP0V75_S0_REG
(1A MAX CURRENT)
02
Q5315
V
EN_PSV
U5480
A
SMC_CPU_ISENSE
VR_PWRGOOD_DELAY
P1V05S0_EN
1.05V (S5)
TPS62510
VOUT
U7750
PP5VRT_S0_REG
(4A MAX CURRENT)
PP3V3_S5_REG
20
12
CURRENT)
PP1V5_S0
R5490
(4A MAX
R5491
ENABLE
3.425V G3HOT LT3470
U6990
02
VIN
VOUT
CPUVTT
(1.05V)
TPS51117
U7600
PGOOD
CPUVTTS0_PGOOD
SMC_CPU_VSENSE
V
1.05V SO
FETS
(Q7951 TO Q7953)
PP1V05_S5_REG
08
Q7910
Q7930
Q3810
21
PPVCORE_S0_MCP
PP5VLT_S3
PP3V42_G3H_REG
VOUT
PPCPUVTT_S0_REG_R
(8A MAX CURRENT)
PPVCORE_CPU_S0_REG
(44A MAX CURRENT)
28
PP1V05_S0_FET
P3V3S3_EN
P3V3S0_EN
P3V3_ENET_FET
P3V3ENET_EN_L
1.8V LDO
TPS79918DRV
U7760
PP1V8_S0_REG
03
23
26
22
PP3V3_S0_FET
PP3V3_S0 PP1V5_S0 PP1V05_S0
RN5VD30A-F
R5492
19-1
SMC PWRGD
U5000
PPCPUVTT_S0
4.6V AUDIO MAX8902A
VIN
U6201
EN
PP5VRT_S0
PP3V3_S5
PP3V3_S3_FET
18
CPUVTTS0_PGOOD
P5V_LT_S3_PGOOD
S0PGOOD_PWROK
V1 V2 V3
04
PP4V6_AUDIO_ANALOG
VOUT
17
07
13
ALL_SYS_PWRGD
P5V3V3_PGOOD
MCPCORESO_PGOOD
RST*
LTC2909
U7870
MCP_PS_PWRGD
U2850
24
RSMRST_PWRGD
09
SMC_ONOFF_L
05
SLP_S5_L SLP_S4_L SLP_S3_L
29
MCP79
PWRBTN*
PLTRST* RSMRST*
PS_PWRGD
CPUPWRGD(GPIO49)
CPU_RESET#
U1400
CPU
PWRGOOD
RESET*
U1000
SMC
RSMRST_OUT(P15)
PWRGD(P12)
RSMRST_IN(P13)
PWR_BUTTON(P90)
SLP_S5_L(P95) SLP_S4_L(P94) SLP_S3_L(P93)
99ms DLY
IMVP_VR_ON(P16)
PLT_RST*
P17(BTN_OUT)
RST*
U4900
Power Block Diagram
SYNC_MASTER=DRAGON
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
APPLE INC.
SCALE
06-1
31
LPC_RESET_L
CPU_PWRGD
30
FSB_CPURST_L
32
PM_RSMRST_L
IMVP_VR_ON
PM_PWRBTN_L SMC_RESET_L
DRAWING NUMBER
D
NONE
10
25
SYNC_DATE=03/13/2008
051-7903
SHT
OF
3
D
C
B
A
REV.
A
83
8
7 6
5
4
3
2
1
8 7
6
5
4
3
BOM Variant
BOM NUMBER
630-9977 085-0737
BOM Groups
D
BOM GROUP
K19_COMMON
K19_PROGPARTS K19_DEVEL_ENG K19_DEVEL_PVT K19_DEBUG_ENG K19_DEBUG_PVT
K19_DEBUG_PROD
Module Parts
PART NUMBER
337S3693 337S3704
337S3756
C
337S3641 338S0710 338S0694 338S0654
K19_MCP
K19_MISC
BOM NAME
PCBA,CORNHOLIO,MLB,K19I
K19I MLB DEVELOPMENT
QTY
1 1 1 1 1 1 1 1 1
DESCRIPTION
PDC,SLGE3,PRQ,2.00,25W,1066,R0,3M,BGA
PDC,SLGE2,PRQ,2.26,25W,1066,R0,3M,BGA
PDC,LGDZ,PRQ,2.40,25W,1066,R0,3M,BGA
PDC,SL3BX,PRQ,2.5,35W,1066,C0,6M,BGA
PDC,SLCFG,PRQ,2.53,25W,1066,R0,3M,BGA
PDC,SLB43,PRQ,2.8,35W,1066,C0,6M,BGA
IC,MCP79MXT-B3,35x35MM,BGA1437
IC,RTL8251CA-VB-GR,GIGE TRANSCEIVER,48P
IC-FW643-E,1394B PHY/OHCI LINK/PCI-E,12
BOM OPTIONS
K19_COMMON,CPU_2_53GHZ,EEE_6Z9
K19_DEVEL_PVT
BOM OPTIONS
COMMON,ALTERNATE,K19_MCP,K19_MISC,K19_DEBUG_PVT,K19_PROGPARTS
MCP_B03,BOOT_MODE_USER
DP_ESD,EXTRACT_BUFF,ISL6258A,K19I,KB_BL,MIKEY,LDO_YES
BOOTROM_PROG,SMC_PROG,IR_PROG,WELLSPRING_PROG
BMON_ENG,DEBUG_ADC,XDP_CONN,LPCPLUS,VREFMRGN,BKLT_FS
LPCPLUS
DEVEL_BOM,SMC_DEBUG_YES,XDP
DEVEL_BOM,BMON_PROD,SMC_DEBUG_YES,XDP,NO_VREFMRGN
BMON_PROD,SMC_DEBUG_YES,XDP,LPCPLUS_NOT,NO_VREFMRGN
REFERENCE DES
U1000 U1000 U1000 U1000 U1000 U1000 U1400 U3700 U4100
CRITICAL
CRITICAL CRITICAL CRITICAL337S3680 CRITICAL337S3640 CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
BOM OPTION
CPU_2_0GHZ
CPU_2_26GHZ
CPU_2_4GHZ CPU_2_5GHZ
CPU_2_53GHZ
CPU_2_8GHZ
MCP_B03
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
Bar Code Label / EEE #
PART NUMBER
826-4393
QTY
1
DESCRIPTION
LBL,P/N LABEL,PCB,28MM X 6 MM
REFERENCE DES
[EEE:6Z9]
CRITICAL
CRITICAL
BOM OPTION
EEE_6Z9
D
C
Programmable Parts
335S0610 341S2458 338S0633 341S2384
Development BOM
PART NUMBER
085-0737 CRITICAL
B
Alternate Parts
PART NUMBER
138S0603 152S0968 128S0220 152S0778 152S0796 152S0685
157S0058 157S0055
128S0093 152S0874 152S0847
ALTERNATE FOR PART NUMBER
138S0602 152S0966 128S0262 152S0693
152S0138152S0694
104S0023104S0018 128S0218 152S0516 152S0586
1 1 1 1 1 1 1
QTY
1
IC,SMC,HS8/2117,9X9MM,TLP,HF
IC,PRGRM,SMC EXTERNAL,K19I
IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP
IC,PRGRM,UNLOCK,K19I
IC,CYPRS,CY7C63803-LQXC,4X4MM,USB,24-QFN
IR,ENCORE II,CY7C63803-LQXC
IC,PSOC+ W/ USB,56 PIN,MLF,CY8C24794
IC,TP PSOC,M97,M98
DESCRIPTION
K19I MLB DEVELOPMENT
BOM OPTION
REF DES
ALL ALL ALL ALL ALL ALL ALL ALL ALL ALL ALL
COMMENTS:
Murata alt to Samsung
Maglayer alt to Delta
KEMET alt to SANYO
CYNTEC AS ALTERNATE
CYNTEC AS ALTERNATE
MAGLAYERS AS ALTERNATE
DELTA AS ALTERNATE
DALE/VISHAY AS ALTERNATE
KEMET AS ALTERNATE
MAGLAYERS AS ALTERNATE
MAGLAYERS AS ALTERNATE
U4900 U4900 U6100 U6100 U4800 U4800 U5701
U57011341S2503 CRITICAL
REFERENCE DES
DEVEL
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
CRITICAL338S0563 CRITICAL341S2460 CRITICAL CRITICAL
CRITICAL CRITICAL337S2983
CRITICAL
SMC_BLANK
SMC_PROG
BOOTROM_BLANK
BOOTROM_PROG
IR_BLANKCRITICAL
IR_PROG
WELLSPRING_BLANK
WELLSPRING_PROG
BOM OPTION
DEVEL_BOM
B
A
PART NUMBER
820-2533
BOM Configuration
SYNC_MASTER=N/A
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
QTY
1 1
DESCRIPTION
SCHEM,CORNHOLIO,K19
PCBF,MLB IG,K19
8
REFERENCE DES
SCH PCB
CRITICAL
CRITICAL051-7903 CRITICAL
BOM OPTION
7 6
APPLE INC.
5
4
3
2
SIZE
D
SCALE
NONE
051-7903
SHT
OF
4
1
SYNC_DATE=N/A
REV.
A
83
A
8 7
Revision History
6
5
4
3
D
C
D
C
B
A
NOTE: All page numbers are .csa, not PDF. See page 1 for .csa -> PDF mapping.
8
7 6
5
B
Revision History
SYNC_MASTER=N/A
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
APPLE INC.
4
3
2
SCALE
D
NONE
051-7903
SHT
OF
5
1
SYNC_DATE=N/A
REV.
A
83
A
8 7
6
5
4
3
Fan Connectors
FUNC_TEST
TRUE
TRUE TRUE
TRUE
PP5V_S0 FAN_RT_PWM
FAN_RT_TACH GND
LVDS Connector
D
C
FUNC_TEST
TRUE TRUE TRUE
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
TRUE
PP3V3_S0 PP3V3_SW_LCD PPVOUT_S0_LCDBKLT
LVDS_DDC_CLK LVDS_DDC_DATA LVDS_CONN_A_DATA_N<0> LVDS_CONN_A_DATA_P<0> LVDS_CONN_A_DATA_N<1> LVDS_CONN_A_DATA_P<1> LVDS_CONN_A_DATA_N<2> LVDS_CONN_A_DATA_P<2> LVDS_CONN_A_CLK_F_N LVDS_CONN_A_CLK_F_P LVDS_CONN_B_DATA_N<0> LVDS_CONN_B_DATA_P<0> LVDS_CONN_B_DATA_N<1> LVDS_CONN_B_DATA_P<1> LVDS_CONN_B_DATA_N<2> LVDS_CONN_B_DATA_P<2> LVDS_CONN_B_CLK_F_N LVDS_CONN_B_CLK_F_P LED_RETURN_1 LED_RETURN_2 LED_RETURN_3 LED_RETURN_4 LED_RETURN_5 LED_RETURN_6 BKL_ISEN1 BKL_ISEN2 BKL_ISEN3 BKL_ISEN4 BKL_ISEN5 BKL_ISEN6
GND
IPD Flex Connector
FUNC_TEST
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
B
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
TRUE
PP3V3_S3_LDO PP18V5_S3 Z2_CS_L Z2_DEBUG3 Z2_MOSI Z2_MISO Z2_SCLK Z2_BOOST_EN Z2_HOST_INTN Z2_CLKIN Z2_KEY_ACT_L Z2_RESET PSOC_MISO PSOC_MOSI PSOC_SCLK SMBUS_SMC_A_S3_SDA SMBUS_SMC_A_S3_SCL PSOC_F_CS_L PICKB_L
GND
SD Card Connector
FUNC_TEST
TRUE TRUE TRUE TRUE TRUE
TRUE
SD_D<7..0> SD_CMD SD_CLK SD_CD_L SD_WP
GND
Speaker Connectors
A
FUNC_TEST
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
TRUE
BI_MIC_LO BI_MIC_SHIELD BI_MIC_HI SPKRCONN_L_OUT_P SPKRCONN_L_OUT_N SPKRCONN_R_OUT_P SPKRCONN_R_OUT_N SPKRCONN_S_OUT_P SPKRCONN_S_OUT_N
GND
72 64 65 67
3 TPs
7
37 42 47 49 61 68 70
47
47
5 TPs
58 61 66 67 68 69 71 72 82 6 7
12 17 18 20 21 22 23 26 27
35 37 41 43 45 46 47 49 53 57 69
6
51 69 72 74
8
17 69
8
17 69
8
69
8
69
8
69
8
69
8
69
8
69
69 82
69 82
8
69
8
69
8
69
8
69
8
69
8
69
69 82
69 82
69 72 74
69 72 74
69 72 74
69 72 74
69 72 74
69 72 74
72
72
72
72
72
72
5 TPs
6
49
6
49
48 49
48 49
48 49
48 49
48 49
49
48 49
48 49
48 49
48 49
48 49
48 49
48 49
6
29 40 43 49 81
6
29 40 43 49 81
48 49
48 49
2 TPs
30 82
30 82
30 82
30
30
2 TPs
57 58
57 58
57 58
56 57 82
56 57 82
56 57 82
56 57 82
56 57 82
56 57 82
6 TPs
SATA ODD Connectors
FUNC_TEST
TRUE
TRUE TRUE TRUE TRUE TRUE
TRUE
PP5V_SW_ODD
SMC_ODD_DETECT SATA_ODD_R2D_P SATA_ODD_R2D_N SATA_ODD_D2R_C_N SATA_ODD_D2R_C_P
GND
Keyboard Connector
FUNC_TEST
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
TRUE
PP3V3_S3 PP3V42_G3H WS_KBD1 WS_KBD2 WS_KBD3 WS_KBD4 WS_KBD5 WS_KBD6 WS_KBD7 WS_KBD8 WS_KBD9 WS_KBD10 WS_KBD11 WS_KBD12 WS_KBD13 WS_KBD14 WS_KBD15_CAP WS_KBD16_NUM WS_KBD17 WS_KBD18 WS_KBD19 WS_KBD20 WS_KBD21 WS_KBD22 WS_KBD23 WS_KBD_ONOFF_L WS_LEFT_SHIFT_KBD WS_LEFT_OPTION_KBD WS_CONTROL_KBD KBDLED_ANODE
GND
Airport/BT/Camera Conn.
FUNC_TEST
PCIE_MINI_D2R_P
TRUE
PCIE_MINI_D2R_N
TRUE
PCIE_MINI_R2D_P
TRUE
PCIE_MINI_R2D_N
TRUE
PCIE_CLK100M_MINI_CONN_P
TRUE
PCIE_CLK100M_MINI_CONN_N
TRUE
MINI_CLKREQ_Q_L
TRUE
PCIE_WAKE_L
TRUE
MINI_RESET_CONN_L
TRUE
PP5V_WLAN
TRUE
PP5V_S3_BTCAMERA_F
TRUE
SMBUS_SMC_A_S3_SDA
TRUE
SMBUS_SMC_A_S3_SCL
TRUE
USB_CAMERA_CONN_P
TRUE
USB_CAMERA_CONN_N
TRUE
CONN_USB2_BT_P
TRUE
CONN_USB2_BT_N
TRUE
GND
TRUE
SATA HDD Connector
FUNC_TEST
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
TRUE
PP5V_S0_HDD_FLT PP5V_S3_IR_R SATA_HDD_R2D_P SATA_HDD_R2D_N SATA_HDD_D2R_C_P SATA_HDD_D2R_C_N IR_RX_OUT SYS_LED_ANODE_R
GND
KBD Backlight Conn.
FUNC_TEST
TRUE TRUE
TRUE
Functional Test Points
DC Power Connector
FUNC_TEST
TRUE TRUE
TRUE
Battery Connector
FUNC_TEST
TRUE TRUE TRUE TRUE TRUE
FUNC_TEST
TRUE TRUE TRUE TRUE TRUE
TRUE
FUNC_TEST
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
TRUE
KBDLED_ANODE SMC_KDBLED_PRESENT_L
GND
4 TPs
6
37 51
37 40
37 77
37 77
37 77
37 77
3 TPs
6 7
20 25 29 30 43 48 50 68
6 7
20 21 24 38 40 41 42 43 45
48 59 60 67 48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
6
49
2 TPs
16 29 77
16 29 77
29 77 82
29 77 82
29 82
29 82
29
16 29
29
29
29
6
29 40 43 49 81
6
29 40 43 49 81
29 82
29 82
29 82
29 82
10 TPs
4 TPs
6
37
37
37 77
37 77
37 77
37 77
37 39
37
6 TPs
6
49
49
2 TPs
PP18V5_DCIN_FUSE ADAPTER_SENSE
GND
PPVBAT_G3H_CONN SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SYS_DETECT_L GND_BATT_CHGND
BIL Connector
PP3V42_G3H SMC_LID_R SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SMC_BIL_BUTTON_L
GND
Power Nets
PPVCORE_S0_CPU PPVCORE_S0_MCP PP0V75_S0_DDRVTT PP1V05_S0 PP1V5_S0 PP1V8_S0 PP3V3_S0 PP1V5_S3 PP3V3_S3 PP1V05_S5 PP3V3_S5 PP3V42_G3H PPBUS_G3H PP3V3_ENET PP1V05_ENET PP5V_S3 PP3V3_S5_AVREF_SMC PP18V5_S3 PP3V3_S3_LDO PPVOUT_S0_LCDBKLT PP4V5_AUDIO_ANALOG SMC_PM_G2_EN PM_SLP_S4_L PM_SLP_S3_L PP1V05_S5 PP5V_SW_ODD PP5V_S0_HDD_FLT BKL_VLDO
GND
3 TPs
59
59
3 TPs
3 TPs
59 60
6
40 43 59 60 81
6
40 43 59 60 81
59
8
59
6 TPs
43 45 48 59 60 67 42 41 38 40
3 TPs
6 7
20
21 24 59
6
40 43 59 60 81
6
40 43 59 60 81
40 41 59
3 TPs
7
10 11 44 61
7
21 22 44 64
7
26 27 63 68
7 9
10 11 12 13 16 17 19 21 22
23 35 61 65 66 67 7
10 11 15 22 37 66 67 68 82
7
17 23 53 66
58 61 66 67 68 69 71 72 82 6 7
12 17 18 20 21 22 23 26 27
35 37 41 43 45 46 47 49 53 57 7
26 27 28 63 68
6 7
20 25 29 30 43 48 50 68
6 7
21 22 32 66
7
17 19 21 22 24 28 32 35 36 42
52 62 66 67 68 69 71 82 6 7
20 21 24 38 40 41 42 43 45
48 59 60 67 7
35 44 45 59 60 62 63 64 73
7
17 22 31 32
7
17 22 31 32
7 8
29 37 38 39 41 49 51 53 62
63 68 40 41
6
49
6
49
6
51 69 72 74
53
8
40 62 67
20 38 40 41 67
20 32 35 40 67 71
6 7
21 22 32 66
6
37 51
6
37
72
6 TPs
NO_TEST
TRUE TRUE TRUE
TRUE
TRUE
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
ICT Test Points
NC_AUD_LO1_N_L
6
53
NC_AUD_LO1_P_L NC_AUD_LO1_P_L
6
53
NC_USB_10N
6
19
NC_USB_10P
6
19
NC_ENET_INTR_L
6
17
NC_ENET_PWRDWN_L
6
17
NC_ISSP_SCLK_P1_1
6
48
NC_ISSP_SDATA_P1_0
6
48
NC_LCDBKLT_FAIL
6
NC_LPC_DRQ0_L
6
18
TP_MEM_A_CKE<3..2> NC_MEM_A_CLK2N
6
14
NC_MEM_A_CLK3N
6
15
NC_MEM_A_CLK3P
6
15
NC_MEM_A_CLK4P
6
15
NC_MEM_A_CS_L<3>
6
15
TP_MEM_A_ODT<3..2>
NC_MEM_B_CKE<2>
6
15
NC_MEM_B_CLK3P
6
15
NC_MEM_B_CLK4N
6
15
NC_MEM_B_CLK4P
6
15
NC_MEM_B_CLK5N
6
15
NC_MEM_B_ODT<2>
6
15
NC_MLB_RAM_SIZE
6
20
NC_P7_7
6
48
TP_PCI_AD<31..8>
TP_PCI_C_BE_L<3..0>
NC_PCI_CLK0
6
18
NC_PCI_CLK1
6
18
NC_PCI_DEVSEL_L
6
18
NC_PCI_FRAME_L
6
18
NC_PCI_GNT0_L
6
18
NC_PCI_GNT1_L
6
18
NC_PCI_INTW_L
6
18
NC_PCI_INTX_L
6
18
NC_PCI_INTZ_L
6
18
NC_PCI_IRDY_L
6
18
NC_PCI_PERR_L
6
18
NC_PCI_RESET1_L
6
18
NC_PCI_SERR_L
6
18
NC_PCI_STOP_L
6
18
NC_PCI_TRDY_L
6
18
NC_PCIE_CLK100M_PE4N
6
16
NC_PCIE_CLK100M_PE4P
6
16
NC_PCIE_CLK100M_PE5N
6
16
NC_PCIE_CLK100M_PE5P
6
16
NC_PCIE_CLK100M_PE6P
6
16
NC_PCIE_PE4_D2RN
6
16
NC_PCIE_PE4_R2D_CN
6
16
NC_PE4_PRSNT_L
6
16
NC_PSOC_P1_3
6
48
NC_PSOC_SDA
6
48
NC_SATA_C_D2RP
6
19
NC_SATA_C_R2D_CN
6
19
NC_SATA_C_R2D_CP
6
19
NC_SATA_D_D2RN
6
19
NC_SATA_D_D2RP
6
19
NC_SB_A20GATE
6
20
FSB_A_L<31..3> FSB_ADS_L FSB_ADSTB_L<1..0>
FSB_D_L<63..0> FSB_DINV_L<3..0> FSB_DSTB_L_N<3..0>
FSB_DSTB_L_P<3..0> FSB_HIT_L FSB_HITM_L FSB_LOCK_L FSB_REQ_L<4..0> MCPCORES0_OCSET USB_BT_N USB_BT_P USB_CAMERA_N USB_CAMERA_P SATA_ODD_D2R_UF_N SATA_ODD_D2R_UF_P DP_ML_C_P<3..0>
9
13 75
9
13 75
9
13 75
9
13 75
9
13 75
9
13 75
9
13 75
9
13 75
9
13 75
9
13 75
13 75 9
19 29 78
19 29 78
19 29 78
19 29 78
37 82
37 82
71 82
NC_AUD_LO1_N_L
NC_USB_10N NC_USB_10P NC_ENET_INTR_L NC_ENET_PWRDWN_L
NC_ISSP_SCLK_P1_1 NC_ISSP_SDATA_P1_0 NC_LCDBKLT_FAIL NC_LPC_DRQ0_L
NC_MEM_A_CKE<3..2> NC_MEM_A_CLK2N NC_MEM_A_CLK3N NC_MEM_A_CLK3P NC_MEM_A_CLK4P NC_MEM_A_CS_L<3> NC_MEM_A_ODT<3..2>
NC_MEM_B_CKE<2> NC_MEM_B_CLK3P NC_MEM_B_CLK4N NC_MEM_B_CLK4P NC_MEM_B_CLK5N NC_MEM_B_ODT<2> NC_MLB_RAM_SIZE NC_P7_7 NC_PCI_AD<31..8>
NC_PCI_C_BE_L<3..0>
NC_PCI_CLK0 NC_PCI_CLK1 NC_PCI_DEVSEL_L NC_PCI_FRAME_L NC_PCI_GNT0_L NC_PCI_GNT1_L NC_PCI_INTW_L NC_PCI_INTX_L NC_PCI_INTZ_L NC_PCI_IRDY_L NC_PCI_PERR_L NC_PCI_RESET1_L NC_PCI_SERR_L NC_PCI_STOP_L NC_PCI_TRDY_L NC_PCIE_CLK100M_PE4N NC_PCIE_CLK100M_PE4P NC_PCIE_CLK100M_PE5N NC_PCIE_CLK100M_PE5P NC_PCIE_CLK100M_PE6P NC_PCIE_PE4_D2RN NC_PCIE_PE4_R2D_CN NC_PE4_PRSNT_L NC_PSOC_P1_3 NC_PSOC_SDA NC_SATA_C_D2RP NC_SATA_C_R2D_CN NC_SATA_C_R2D_CP NC_SATA_D_D2RN NC_SATA_D_D2RP NC_SB_A20GATE
NO_TEST
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
TRUE TRUE TRUE TRUE TRUE TRUE
TRUE TRUE TRUE TRUE
TRUE TRUE TRUE TRUE TRUE TRUE TRUE
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
TRUE
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
Note.
NO_TEST properties are also on page9,26,43,50
Functional / ICT Test
SYNC_MASTER=N/A
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
APPLE INC.
D
SCALE
NONE
051-7903
SHT
6
6
53
6
53
6
19
6
19
6
17
6
17
6
48
6
48
6
6
18
15
6
14
6
15
6
15
6
15
6
15
15
6
15
6
15
6
15
6
15
6
15
6
15
6
20
6
48
18
18
6
18
6
18
6
18
6
18
6
18
6
18
6
18
6
18
6
18
6
18
6
18
6
18
6
18
6
18
6
18
6
16
6
16
6
16
6
16
6
16
6
16
6
16
6
16
6
48
6
48
6
19
6
19
6
19
6
19
6
19
6
20
SYNC_DATE=N/A
REV.
A
OF
83
D
C
B
A
8
7 6
5
4
3
2
1
PP1V5_S0
MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.2mm VOLTAGE=1.5V MAKE_BASE=TRUE
PP1V5_S0 PP1V5_S0 PP1V5_S0
PP1V5_S0 PP1V5_S0
GND GND
K19i uses GND reference for ALL DDR3 signals.
PP1V05_S5
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE
PP1V05_S5 PP1V05_S5
PP1V05_ENETPP1V05_ENET
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE
PP1V05_ENET PP1V05_ENET PP1V05_ENET
PP1V05_S0
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE
4500 mA
1182 mA
1034 mA
PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0
PP1V05_S0_MCP_PLL_UF
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE
PP1V05_S0_MCP_PLL_UF PP1V05_FW
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE
PP1V05_FW PP1V05_FW
PPVCORE_S0_CPU
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.25V MAKE_BASE=TRUE
PPVCORE_S0_CPU PPVCORE_S0_CPU
PPVCORE_S0_MCP
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE
PPVCORE_S0_MCP PPVCORE_S0_MCP
PPVTTDDR_S3
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V MAKE_BASE=TRUE
PP0V75_S0_DDRVTT
MIN_LINE_WIDTH=2 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=0.75V MAKE_BASE=TRUE
PP0V75_S0_DDRVTT PP0V75_S0_DDRVTT PP0V75_S0_DDRVTT
Power Aliases
SYNC_MASTER=N/A
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
APPLE INC.
SCALE
D
NONE
DRAWING NUMBER
051-7903
SHT
6 7
10 11 15 22 37 66 67 68
82
6 7
10 11 15 22 37 66 67 68
82 6 7
10 11 15 22 37 66 67 68
82 6 7
10 11 15 22 37 66 67 68
82
6 7
10 11 15 22 37 66 67 68
82 6 7
10 11 15 22 37 66 67 68
82
6 7
21 22 32 66
6 7
21 22 32 66
6 7
21 22 32 66
6 7
17 22 31 32
6 7
17 22 31 32
6 7
17 22 31 32
6 7
17 22 31 32
6 7 9
10 11 12 13 16 17 19 21
22 23 35 61 65 66 67
6 7 9
10 11 12 13 16 17 19 21
22 23 35 61 65 66 67 6 7 9
10 11 12 13 16 17 19 21
22 23 35 61 65 66 67 6 7 9
10 11 12 13 16 17 19 21
22 23 35 61 65 66 67 6 7 9
10 11 12 13 16 17 19 21
22 23 35 61 65 66 67 6 7 9
10 11 12 13 16 17 19 21
22 23 35 61 65 66 67 6 7 9
10 11 12 13 16 17 19 21
22 23 35 61 65 66 67 6 7 9
10 11 12 13 16 17 19 21
22 23 35 61 65 66 67 6 7 9
10 11 12 13 16 17 19 21
22 23 35 61 65 66 67 6 7 9
10 11 12 13 16 17 19 21
22 23 35 61 65 66 67 6 7 9
10 11 12 13 16 17 19 21
22 23 35 61 65 66 67
7
22 66
7
22 66
7
34 35
7
34 35
7
34 35
6 7
10 11 44 61
6 7
10 11 44 61
6 7
10 11 44 61
6 7
21 22 44 64
6 7
21 22 44 64
6 7
21 22 44 64
7
25 63
6 7
26 27 63 68
6 7
26 27 63 68
6 7
26 27 63 68
6 7
26 27 63 68
SYNC_DATE=N/A
OF
7
D
C
B
A
REV.
A
83
58 61 66
66 67 68
58 61 66
66 67 68
3
PP1V5_S0
6 7
10 11 15 22 37 66 67 68
82
PP1V05_S5
6 7
21 22 32 66
6 7
17 22 31 32
PP1V05_S0
6 7 9
10 11 12 13 16 17 19 21
22 23 35 61 65 66 67
6600 MA
241 mA max load
PP1V05_S0_MCP_PLL_UF
7
22 66
35
PP1V05_FW
7
34 35
35
PPVCORE_S0_CPU
6 7
10 11 44 61
PPVCORE_S0_MCP
6 7
21 22 44 64
35
PPVTTDDR_S3
7
25 63
PP0V75_S0_DDRVTT
6 7
26 27 63 68
1.5V S0 Rail
130 mA
4771 mA
DDR3 Reference Plane
1.05V Rails
105 mA/241 mA 139 mA/ 0 mA
Chipset "VCore" Rails
0.75V Rails
8 7
PPBUS_G3H
6 7
35 44 45 59 60 62 63 64
73
D
C
PPBUS_CPU_IMVP_ISNS
7
45 61 65
PP3V42_G3H
6 7
20 21 24 38 40 41 42 43
45 48 59 60 67
PPDCIN_S5
7
59 60
DCIN Rail
"FW" (FireWire) Rail
"G3Hot" (Always-Present) Rails
PPVP_FW
7
35 36
5V Rails
PP5V_S3
6 7 8
29 37 38 39 41 49 51 53
62 63 68
B
PP5V_S0
6 7
37 42 47 49 61 64 65 67
68 70 72
MCP79 PCIe/SATA Rails
A
6 7 9
10 11 12 13 16 17 19 21
22 23 35 61 65 66 67
PP1V05_S0_MCP_PEX_AVDD
7
16 22
MAKE_BASE=TRUE
6 7 9
10 11 12 13 16 17 19 21
22 23 35 61 65 66 67
7
19 22
MAKE_BASE=TRUE
PPBUS_G3H
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V MAKE_BASE=TRUE
PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H
PPBUS_CPU_IMVP_ISNS
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V MAKE_BASE=TRUE
PPBUS_CPU_IMVP_ISNS PPBUS_CPU_IMVP_ISNS
PP3V42_G3H
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.42V MAKE_BASE=TRUE
PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H
PPDCIN_S5
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=18.5V MAKE_BASE=TRUE
PPDCIN_S5
PPVP_FW
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=12.6V MAKE_BASE=TRUE
PPVP_FW PPVP_FW
PP5V_S3
MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.2MM VOLTAGE=5V MAKE_BASE=TRUE
PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3
PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3
PP5V_S3
PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3
PP5V_S0
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V MAKE_BASE=TRUE
PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0
GND PP1V05_S0PP1V05_S0
GND PP1V05_S0_MCP_PEX_AVDD
PP1V05_S0PP1V05_S0 GND
PP1V05_S0_MCP_SATA_AVDDPP1V05_S0_MCP_SATA_AVDD GND
6
6 7
35 44 45 59 60 62 63 64 73
6 7
35 44 45 59 60 62 63 64 73
6 7
35 44 45 59 60 62 63 64 73
6 7
35 44 45 59 60 62 63 64 73
6 7
35 44 45 59 60 62 63 64 73
6 7
35 44 45 59 60 62 63 64 73
6 7
35 44 45 59 60 62 63 64 73
6 7
35 44 45 59 60 62 63 64 73
6 7
35 44 45 59 60 62 63 64 73
7
45 61 65
7
45 61 65
7
45 61 65
6 7
20 21 24 38 40 41 42 43 45
48 59 60 67
6 7
20 21 24 38 40 41 42 43 45
48 59 60 67 6 7
20 21 24 38 40 41 42 43 45
48 59 60 67 6 7
20 21 24 38 40 41 42 43 45
48 59 60 67 6 7
20 21 24 38 40 41 42 43 45
48 59 60 67 6 7
20 21 24 38 40 41 42 43 45
48 59 60 67 6 7
20 21 24 38 40 41 42 43 45
48 59 60 67 6 7
20 21 24 38 40 41 42 43 45
48 59 60 67 6 7
20 21 24 38 40 41 42 43 45
48 59 60 67 6 7
20 21 24 38 40 41 42 43 45
48 59 60 67 6 7
20 21 24 38 40 41 42 43 45
48 59 60 67 6 7
20 21 24 38 40 41 42 43 45
48 59 60 67 6 7
20 21 24 38 40 41 42 43 45
48 59 60 67 6 7
20 21 24 38 40 41 42 43 45
48 59 60 67
7
59 60
7
59 60
7
35 36
7
35 36
7
35 36
6 7 8
29 37 38 39 41 49 51 53
62 63 68
6 7 8
29 37 38 39 41 49 51 53
62 63 68 6 7 8
29 37 38 39 41 49 51 53
62 63 68 6 7 8
29 37 38 39 41 49 51 53
62 63 68 6 7 8
29 37 38 39 41 49 51 53
62 63 68 6 7 8
29 37 38 39 41 49 51 53
62 63 68 6 7 8
29 37 38 39 41 49 51 53
62 63 68 6 7 8
29 37 38 39 41 49 51 53
62 63 68 6 7 8
29 37 38 39 41 49 51 53
62 63 68 6 7 8
29 37 38 39 41 49 51 53
62 63 68 6 7 8
29 37 38 39 41 49 51 53
62 63 68 6 7 8
29 37 38 39 41 49 51 53
62 63 68 6 7 8
29 37 38 39 41 49 51 53
62 63 68 6 7 8
29 37 38 39 41 49 51 53
62 63 68 6 7 8
29 37 38 39 41 49 51 53
62 63 68 6 7 8
29 37 38 39 41 49 51 53
62 63 68 6 7 8
29 37 38 39 41 49 51 53
62 63 68 6 7 8
29 37 38 39 41 49 51 53
62 63 68
6 7
37 42 47 49 61 64 65 67 68
70 72
6 7
37 42 47 49 61 64 65 67 68
70 72 6 7
37 42 47 49 61 64 65 67 68
70 72 6 7
37 42 47 49 61 64 65 67 68
70 72 6 7
37 42 47 49 61 64 65 67 68
70 72 6 7
37 42 47 49 61 64 65 67 68
70 72 6 7
37 42 47 49 61 64 65 67 68
70 72 6 7
37 42 47 49 61 64 65 67 68
70 72 6 7
37 42 47 49 61 64 65 67 68
70 72 6 7
37 42 47 49 61 64 65 67 68
70 72 6 7
37 42 47 49 61 64 65 67 68
70 72
6 7 9
10 11 12 13 16 17 19 21
22 23 35 61 65 66 67
7
16 22
6 7 9
10 11 12 13 16 17 19 21
22 23 35 61 65 66 67
7
19 22
68 69 71 82
PP3V3_S5
6 7
17 19 21 22
24 28 32 35 36 42 52 62 66 67
PP3V3_S3
6 7
20 25 29 30 43 48 50 68
PP3V3_ENET
6 7
17 22 31 32
57 58 61 66 67 68 69 71 72 82
PP3V3_S0
6 7
12 17 18 20 21 22 23 26
27 35 37 41 43 45 46 47 49 53
PP3V3_FW
7
34 35 36
PP1V8_S0
6 7
17 23 53 66
500 mA max supply
PP1V5_S3
6 7
26 27 28 63 68
5
3.3V Rails
1.8V Rail
190 mA
1.5V S3 Rail
PP3V3_S5
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE
PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5
PP3V3_S3
MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V MAKE_BASE=TRUE
PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3
PP3V3_ENET
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE
PP3V3_ENET PP3V3_ENET
PP3V3_S0
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE
PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0
PP3V3_FW
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE
PP3V3_FW PP3V3_FW
PP1V8_S0
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V MAKE_BASE=TRUE
PP1V8_S0 PP1V8_S0
PP1V5_S3
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.5V MAKE_BASE=TRUE
PP1V5_S3 PP1V5_S3 PP1V5_S3 PP1V5_S3 PP1V5_S3
4
68 69 71 82 6 7
17 19 21 22
24 28 32 35 36 42 52 62 66 67
6 7
17 19 21 22 24 28 32 35 36
42 52 62 66 67 68 69 71 82 6 7
17 19 21 22 24 28 32 35 36
42 52 62 66 67 68 69 71 82 6 7
17 19 21 22 24 28 32 35 36
42 52 62 66 67 68 69 71 82 6 7
17 19 21 22 24 28 32 35 36
42 52 62 66 67 68 69 71 82 6 7
17 19 21 22 24 28 32 35 36
42 52 62 66 67 68 69 71 82 6 7
17 19 21 22 24 28 32 35 36
42 52 62 66 67 68 69 71 82 6 7
17 19 21 22 24 28 32 35 36
42 52 62 66 67 68 69 71 82 6 7
17 19 21 22 24 28 32 35 36
42 52 62 66 67 68 69 71 82 6 7
17 19 21 22 24 28 32 35 36
42 52 62 66 67 68 69 71 82 6 7
17 19 21 22 24 28 32 35 36
42 52 62 66 67 68 69 71 82 6 7
17 19 21 22 24 28 32 35 36
42 52 62 66 67 68 69 71 82 6 7
17 19 21 22 24 28 32 35 36
42 52 62 66 67 68 69 71 82 6 7
17 19 21 22 24 28 32 35 36
42 52 62 66 67 68 69 71 82 6 7
17 19 21 22 24 28 32 35 36
42 52 62 66 67 68 69 71 82 6 7
17 19 21 22 24 28 32 35 36
42 52 62 66 67 68 69 71 82 6 7
17 19 21 22 24 28 32 35 36
42 52 62 66 67 68 69 71 82 6 7
17 19 21 22 24 28 32 35 36
42 52 62 66 67 68 69 71 82
6 7
20 25 29 30 43 48 50 68
6 7
20 25 29 30 43 48 50 68
6 7
20 25 29 30 43 48 50 68
6 7
20 25 29 30 43 48 50 68
6 7
20 25 29 30 43 48 50 68
6 7
20 25 29 30 43 48 50 68
6 7
20 25 29 30 43 48 50 68
6 7
20 25 29 30 43 48 50 68
6 7
20 25 29 30 43 48 50
68 6 7
20 25 29 30 43 48 50 68
6 7
17 22 31 32
6 7
17 22 31 32
6 7
17 22 31 32
58 61 66 67 68 69 71 72 82 6 7
12 17 18 20 21 22 23 26 27
35 37 41 43 45 46 47 49 53 57
58 61 66 67 68 69 71 72 82 6 7
12 17 18 20 21 22 23 26 27
35 37 41 43 45 46 47 49 53 57
58 61 66 67 68 69 71 72 82 6 7
12 17 18 20 21 22 23 26 27
35 37 41 43 45 46 47 49 53 57 6 7
12 17 18 20 21 22 23 26 27 35 37 41 43 45 46 47 49 53 57 58 61 66 67 68 69 71 72 82
6 7
12 17 18 20 21 22 23 26 27
37 41 43 45 46 47 49 53 57 58 61 66 67 68 69 71 72 82
58 61 66 67 68 69 71 72 82 6 7
12 17 18 20 21 22 23 26 27 35 37 41 43 45 46 47 49 53 57
6 7
12 17 18 20 21 22 23 26 27 35 37 41 43 45 46 47 49 53 57 58 61 66 67 68 69 71 72 82
58 61 66 67 68 69 71 72 82 6 7
12 17 18 20 21 22 23 26 27 35 37 41 43 45 46 47 49 53 57
6 7
12 17 18 20 21 22 23 26 27 35 37 41 43 45 46 47 49 53 57 58 61 66 67 68 69 71 72 82
6
41
7
12 17 18 20 21 22 23 26 27 12
37 41 43 45 46 47 49 53 57
6
58 61 66 67 68 69 71 72 82 7 17 18 20 21 22 23 26 27 35 37 43 45 46 47 49 53 57 58 61 66 67 68 69 71 72 82
6 7
12 17 18 20 21 22 23 26 27 35 37 41 43 45 46 47 49 53 57 67 68 69 71 72 82
6
41
7
12 17 18 20 21 22 23 26 27 12
45 46 47 49 53 57 58 61 66
6
67 68 69 71 72 82 7 17 18 20 21 22 23 26 27 35 37 43 45 46 47 49 53 57 58 61 69 71 72 82
58 61 66 67 68 69 71 72 82 6 7
12 17 18 20 21 22 23 26 27
35 37 41 43 45 46 47 49 53 57 6 7
12 17 18 20 21 22 23 26 27 35 37 41 43 45 46 47 49 53 57 58 61 66 67 68 69 71 72 82
6
41
7
12 17 18 20 21 22 23 26 27 12
37 41 43 45 46 47 49 53 57
6
58 61 66 67 68 69 71 72 82 7 17 18 20 21 22 23 26 27 35 37 43 45 46 47 49 53 57 58 61 66 67 68 69 71 72 82
6 7
12 17 18 20 21 22 23 26 27 35 37 41 43 45 46 47 49 53 57 67 68 69 71 72 82
6
41
7
12 17 18 20 21 22 23 26 27 12
45 46 47 49 53 57 58 61 66
6
67 68 69 71 72 82 7 17 18 20 21 22 23 26 27 35 37 43 45 46 47 49 53 57 58 61 69 71 72 82
6 7
12 17 18 20 21 22 23 26 27 35 37 41 43 45 46 47 49 53 57 71 72 82
6
41
12 17 18 20 21 22 23 26 27
7
12
49 53 57 58 61 66 67 68 69
6
71 72 82 7 17 18 20 21 22 23 26 27 35 37 43 45 46 47 49 53 57 58 61 82
7
34 35 36
7
34 35 36
7
34 35 36
6 7
17 23 53 66
6 7
17 23 53 66
6 7
17 23 53 66
6 7
26 27 28 63 68
6 7
26 27 28 63 68
6 7
26 27 28 63 68
6 7
26 27 28 63 68
6 7
26 27 28 63 68
6 7
26 27 28 63 68
35 37 41 43
35 37 41 43
58 61 66 67 68 69
35 37 41 43 45 46 47
66 67 68 69 71 72
8
7 6
5
4
3
2
1
8 7
Board Mounting Holes
ZT0965
HOLE-VIA-P5RP25
ZT0950
D
TH
3R2P5
1
1
SL-3.1X2.7-6CIR-NSP
ZT0990
(ORIGIN)
NOTE: VIAs represent non-plated holes with ground rings. Place VIAs in corresponding hole’s ground ring.
Left Speaker Standoffs
(Not to scale)
ZT0960
3R2P5
ZT0915
3R2P5
1
ZT0934
ZT0935
1
1
1
1
STDOFF-4.0OD3.0H-TH
(UPPER)
STDOFF-4.0OD3.0H-TH
(LOWER)
ZT0942
3R2P5
HOLE-VIA-P5RP25
C
I/O Row Pogos
(FW800)
(Audio)
SH0914
SM
SH0913
SM
SH0912
SM
SH0911
SM
SH0910
SM
SH0915
SM
SH0916
SM
1
1
1
1
1
1
1
1.4DIA-SHORT-EMI-MLB-M97-M98
(Ethernet)
1.4DIA-SHORT-EMI-MLB-M97-M98
1.4DIA-SHORT-EMI-MLB-M97-M98
(Mini-DP)
1.4DIA-SHORT-EMI-MLB-M97-M98
B
(Upper USB)
1.4DIA-SHORT-EMI-MLB-M97-M98
(Lower USB)
1.4DIA-SHORT-EMI-MLB-M97-M98
(SD Card)
1.4DIA-SHORT-EMI-MLB-M97-M98
ZT0940
3R2P5
1
1
ZT0945
1
2.0DIA-TALL-EMI-MLB-M97-M98
2.0DIA-TALL-EMI-MLB-M97-M98
(Near BIL Connector)
GND_CHASSIS_AUDIO_JACK
6
CPU Thermal Module Holes
STDOFF-4.5OD.98H-1.1-3.48-TH
STDOFF-4.5OD.98H-1.1-3.48-TH
ZT0986
1
MCP Thermal Module Holes
STDOFF-4.5OD.98H-1.1-3.48-TH
ZT0930
1
STDOFF-4.5OD.98H-1.1-3.48-TH
Fan Screw Hole
STDOFF-4.5OD.98H-1.1-3.48-TH
ZT0988
1
CPU Pogo
2.0DIA-TALL-EMI-MLB-M97-M98
SH0903
SM
1
SO-DIMM Pogos
SH0900
SM
1
(LEFT)
Other Board Pogos
SH0905
SM
1
57
Bosses
ZT0985
1
1
ZT0984
2.0DIA-TALL-EMI-MLB-M97-M98
2.0DIA-TALL-EMI-MLB-M97-M98
(Near IPD Connector)
STDOFF-4.5OD.98H-1.1-3.48-TH
STDOFF-4.5OD.98H-1.1-3.48-TH
ZT0981
1
ZT0982
1
SH0902
SM
1
(RIGHT)
SH0906
SM
1
5
4
3
CPU Signals
TP_IMVP6_CLKEN_L
8
61
IN
CPU_VID<0..6>
10 75
IN
MAKE_BASE=TRUE
CPU_BSEL<0..2>
9
75
IN
MAKE_BASE=TRUE
TP_CPU_PECI_MCP
8
13
BI
NC_PEG_CLK100MP
8
16 77
IN
NC_PEG_CLK100MN
8
16 77
IN
=PEG_R2D_C_P<0..15>
IN
=PEG_R2D_C_N<0..15>
IN
NC_PEG_D2RP<0..15>
16
MAKE_BASE=TRUE
NC_PEG_D2RN<0..15>
16
MAKE_BASE=TRUE
TP_PEG_PRSNT_L
8
16
MAKE_BASE=TRUE
PEG Signals
NO_TEST=TRUE
NO_TEST=TRUE
TP_IMVP6_CLKEN_L
MAKE_BASE=TRUE
IMVP6_VID<0..6> =MCP_BSEL<0..2>
TP_CPU_PECI_MCP
MAKE_BASE=TRUE
NC_PEG_CLK100MP
MAKE_BASE=TRUE
NC_PEG_CLK100MN
MAKE_BASE=TRUE
NC_PEG_R2DCP<0..15>
MAKE_BASE=TRUE
NC_PEG_R2DCN<0..15>
MAKE_BASE=TRUE
=PEG_D2R_P<0..15> =PEG_D2R_N<0..15>
TP_PEG_PRSNT_L
(Internal pull-up)
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
8
8
8
8
16
16
OUT
OUT
OUT
OUT
OUT
61
13
16 77
16 77
61 75
13
8
16
NC_USB_EXTCP
8
19 78
BI
NC_USB_EXTCN
8
19 78
BI
NC_USB_EXTDP
8
19 78
BI
NC_USB_EXTDN
8
19 78
BI
NC_USB_MINIP
8
19 78
BI
NC_USB_MININ
8
19 78
BI
NC_USB_EXCARDP
8
19 78
BI
NC_USB_EXCARDN
8
19 78
BI
AUD_IPHS_SWITCH_EN
18 58
IN
PCIe Signals
NC_PCIE_CLK100M_EXCARDP
MAKE_BASE=TRUE
NC_PCIE_CLK100M_EXCARDN
MAKE_BASE=TRUE
TP_EXCARD_CLKREQ_L
(Internal pull-up)
NC_PCIE_EXCARD_R2DCP
MAKE_BASE=TRUE
NC_PCIE_EXCARD_R2DCN
MAKE_BASE=TRUE
NC_PCIE_EXCARD_D2RP
TP_PCIE_EXCARD_PRSNT_L
(Internal pull-up)
PCIE_FW_PRSNT_L
NOSTUFF
1
R0925
0
5% 1/16W MF-LF 402
2
LVDS_CONN_A_CLK_P
MAKE_BASE=TRUE
LVDS_CONN_A_CLK_N
MAKE_BASE=TRUE
LVDS_CONN_A_DATA_P<0..2>
MAKE_BASE=TRUE
LVDS_CONN_A_DATA_N<0..2>
MAKE_BASE=TRUE
NC_LVDS_IG_A_DATAP<3>
MAKE_BASE=TRUE
NC_LVDS_IG_A_DATAN<3>NC_LVDS_IG_A_DATAN<3>
MAKE_BASE=TRUE
LVDS_CONN_B_CLK_P
MAKE_BASE=TRUE
LVDS_CONN_B_CLK_N
MAKE_BASE=TRUE
LVDS_CONN_B_DATA_P<0..2>
MAKE_BASE=TRUE
LVDS_CONN_B_DATA_N<0..2>
MAKE_BASE=TRUE
NC_LVDS_IG_B_DATAP<3>
MAKE_BASE=TRUE
NC_LVDS_IG_B_DATAN<3>
MAKE_BASE=TRUE
LVDS_BKL_ON
MAKE_BASE=TRUE
LCD_BKLT_PWM
MAKE_BASE=TRUE
LCD_PWR_EN
MAKE_BASE=TRUE
LVDS_DDC_CLK
MAKE_BASE=TRUE
LVDS_DDC_DATA
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
8
8
8
8
8
8
8
8
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
16 77
16 77
16 77
16 77
17 77
17 77
17 77
17 77
BI
8
16
8
16 77
8
16 77
8
16
16 35
8
17 69 77
8
17 69 77
6
69
6
69
8
17 69 77
8
17 69 77
6
69
6
69
8
17 73
8
17 72 73 74
8
17 69
6 8
17 69
6 8
17 69
40 62 67
PP5V_S3
6 7
29 37 38 39 41 49 51 53
62 63 68
PM_SLP_RMGT_L
8
20 32
IN
MAKE_BASE=TRUE
NC_RTL8211_REGOUT
8
31
IN
RTL8211_VDDREG
8
31
GND
IN
MCP_MII_PD
8
17
MAKE_BASE=TRUE
1
R0930
47K
5% 1/16W MF-LF 402
2
RTL8211_CLK125
8
31
IN
SMC_PM_G2_EN
6 8
IN
MAKE_BASE=TRUE
TP_GMUX_JTAG_TCK_L
8
16
IN
TP_GMUX_JTAG_TDI
8
18
IN
TP_GMUX_JTAG_TMS
8
18
IN
TP_GMUX_JTAG_TDO
8
16
MAKE_BASE=TRUE
MCP_HPLUG_DET2
8
17
MAKE_BASE=TRUE
1
R0920
20K
5% 1/16W MF-LF 402
2
17 69
17 69
NC_PCIE_CLK100M_EXCARDP
8
16 77
IN
NC_PCIE_CLK100M_EXCARDN
8
16 77
IN
TP_EXCARD_CLKREQ_L
8
16
MAKE_BASE=TRUE
NC_PCIE_EXCARD_R2DCP
8
16 77
IN
NC_PCIE_EXCARD_R2DCN
8
16 77
IN
NC_PCIE_EXCARD_D2RP
8
16 77
MAKE_BASE=TRUE
NC_PCIE_EXCARD_D2RN NC_PCIE_EXCARD_D2RN
8
16 77
MAKE_BASE=TRUE
TP_PCIE_EXCARD_PRSNT_L
8
16
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
LVDS Signals
LVDS_CONN_A_CLK_P
8
17 69 77
IN
LVDS_CONN_A_CLK_N
8
17 69 77
IN
LVDS_IG_A_DATA_P<0..2>
17 77
IN
LVDS_IG_A_DATA_N<0..2>
17 77
IN
NC_LVDS_IG_A_DATAP<3>
8
17 77
IN
8
17 77
IN
LVDS_CONN_B_CLK_P
8
17 69 77
IN
LVDS_CONN_B_CLK_N
8
17 69 77
IN
LVDS_IG_B_DATA_P<0..2>
17 77
IN
LVDS_IG_B_DATA_N<0..2>
17 77
IN
NC_LVDS_IG_B_DATAP<3>
8
17 77
IN
NC_LVDS_IG_B_DATAN<3>
8
17 77
IN
LVDS_BKL_ON
8
17 73
IN
LCD_BKLT_PWM
8
17 72 73 74
IN
LCD_PWR_EN
8
17 69
IN
LVDS_DDC_CLK
6 8
IN
LVDS_DDC_DATA
6 8
BI
DisplayPort Signals
(Aliases on page70.csa)
USB Signals
Audio Signals
Ethernet Signals
Power Signals
GMUX Signals
NC_USB_EXTCP
MAKE_BASE=TRUE
NC_USB_EXTCN
MAKE_BASE=TRUE
NC_USB_EXTDP
MAKE_BASE=TRUE
NC_USB_EXTDN
MAKE_BASE=TRUE
NC_USB_MINIP
MAKE_BASE=TRUE
NC_USB_MININ
MAKE_BASE=TRUE
NC_USB_EXCARDP
MAKE_BASE=TRUE
NC_USB_EXCARDN
MAKE_BASE=TRUE
1
R0902
10K
5% 1/16W MF-LF 402
2
XW0901
SM
12
PP5V_S3_AUDIO_AMP
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V
PM_SLP_RMGT_L PM_SLP_RMGT_L
NC_RTL8211_REGOUT
MAKE_BASE=TRUE
RTL8211_VDDREG
MAKE_BASE=TRUE
MCP_MII_PD MCP_MII_PD MCP_MII_PD
RTL8211_CLK125
MAKE_BASE=TRUE
SMC_PM_G2_EN
TP_GMUX_JTAG_TCK_L
MAKE_BASE=TRUE
TP_GMUX_JTAG_TDI
MAKE_BASE=TRUE
TP_GMUX_JTAG_TMS
MAKE_BASE=TRUE
TP_GMUX_JTAG_TDO MCP_HPLUG_DET2
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
1
R0931
22
5% 1/16W MF-LF 402
2
8
19 78
8
19 78
8
19 78
8
19 78
8
19 78
8
19 78
8
19 78
8
19 78
56
8
OUT
8
OUT
8
31
8
31
8
OUT
8
OUT
8
OUT
20 32
20 32
17
17
17
D
C
B
6 8
40 62 67
OUT
8
16
8
18
8
18
8
16
OUT
8
17
OUT
Digital Ground
GND_BATT_CHGND
A
GND
MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM VOLTAGE=0V
8
6
59
7 6
ZT0951
4.0OD1.85H-M1.6X0.35
1
(Keyboard Protector)
ZT0952
4.0OD1.85H-M1.6X0.35
1
(IPD Protector)
FW643_WAKE_L
8
34 35
IN
FW_PLUG_DET_L
8
18 35
IN
MAKE_BASE=TRUE
MEM_VTT_EN MEM_VTT_EN
8
24 63 68
IN
MAKE_BASE=TRUE
NC_MEM_A_A<15>
8
26
MAKE_BASE=TRUE
NC_MEM_B_A<15>
8
27
MAKE_BASE=TRUE
5
FireWire Signals
FW643_WAKE_L
MAKE_BASE=TRUE
FW_PLUG_DET_L
Memory Signals
NO_TEST=TRUE
NO_TEST=TRUE
NC_MEM_A_A<15> NC_MEM_B_A<15>
4
8
OUT
OUT
OUT
OUT
34 35
8
18 35
8
24 63 68
8
26
8
27
Signal Aliases
SYNC_MASTER=WFERRY_K19I
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
D
APPLE INC.
3
2
SCALE
NONE
SYNC_DATE=01/13/2009
051-7903
SHT
OF
8
1
A
REV.
A
83
8 7
6
5
4
3
OMIT
AA4 AB2
AA3
D22
J4 L5
L4
K5 M3
N2
J1 N3
P5 P2
L2
P4 P1
R1
M1
K3
H2 K2
J3
L1
Y2
U5
R3 W6
U4
Y5 U1
R4 T5
T3
W2 W5
Y4
U2 V4
W3
V1
A6 A5
C4
D5
C6
B4 A3
M4
N5
T2 V3
B2
F6 D2
D3
A3* A4* A5* A6* A7* A8* A9* A10* A11* A12* A13* A14* A15* A16* ADSTB0*
REQ0* REQ1* REQ2* REQ3* REQ4*
A17* A18* A19* A20* A21* A22* A23* A24* A25* A26* A27* A28* A29* A30* A31* A32* A33* A34* A35* ADSTB1*
A20M* FERR* IGNNE*
STPCLK* LINT0 LINT1 SMI*
RSVD0 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8
U1000
PENRYN
FCBGA
1 OF 4
ADDR GROUP0
ADDR GROUP1
THERMAL
THERMTRIP*
ICH
RESERVED
CONTROL
XDP/ITP SIGNALS
PROCHOT*
H CLK
FSB_A_L<3>
6
13 75
BI
FSB_A_L<4>
6
13 75
BI
FSB_A_L<5>
6
13 75
BI
FSB_A_L<6>
6
13 75
BI
FSB_A_L<7>
6
13 75
BI
FSB_A_L<8>
6
13 75
BI
FSB_A_L<9>
6
13 75
BI
FSB_A_L<10>
6
13 75
BI
FSB_A_L<11>
6
13 75
BI
FSB_A_L<12>
6
13 75
BI
FSB_A_L<13>
6
13 75
D
C
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
13 75
13 75
13 75
13 75
6
13 75
13 75
13 75
13 75
13 75
13 75
13 75
13 75
BI
FSB_A_L<14>
BI
FSB_A_L<15>
BI
FSB_A_L<16>
BI
FSB_ADSTB_L<0>
BI
FSB_REQ_L<0>
BI
FSB_REQ_L<1>
BI
FSB_REQ_L<2>
BI
FSB_REQ_L<3>
BI
FSB_REQ_L<4>
BI
FSB_A_L<17>
BI
FSB_A_L<18>
BI
FSB_A_L<19>
BI
FSB_A_L<20>
BI
FSB_A_L<21>
BI
FSB_A_L<22>
BI
FSB_A_L<23>
BI
FSB_A_L<24>
BI
FSB_A_L<25>
BI
FSB_A_L<26>
BI
FSB_A_L<27>
BI
FSB_A_L<28>
BI
FSB_A_L<29>
BI
FSB_A_L<30>
BI
FSB_A_L<31>
BI
FSB_A_L<32>
BI
FSB_A_L<33>
BI
FSB_A_L<34>
BI
FSB_A_L<35>
BI
FSB_ADSTB_L<1>
BI
CPU_A20M_L
IN
CPU_FERR_L
OUT
CPU_IGNNE_L
IN
CPU_STPCLK_L
IN
CPU_INTR
IN
CPU_NMI
IN
CPU_SMI_L
IN
TP_CPU_RSVD_M4 TP_CPU_RSVD_N5 TP_CPU_RSVD_T2 TP_CPU_RSVD_V3 TP_CPU_RSVD_B2 TP_CPU_RSVD_F6 TP_CPU_RSVD_D2 TP_CPU_RSVD_D22 TP_CPU_RSVD_D3
B
PLACEMENT_NOTE=Place R1092 near ITP connector (if present)
ADS* BNR*
BPRI*
DEFER*
DRDY* DBSY*
BR0*
IERR* INIT*
LOCK*
RESET*
RS0* RS1* RS2*
TRDY*
HIT*
HITM*
BPM0* BPM1* BPM2* BPM3* PRDY* PREQ*
TRST*
DBR*
THERMDA THERMDC
BCLK0 BCLK1
TCK TDI TDO TMS
H1 E2
G5
H5
F21
E1
F1
D20
B3
H4
C1 F3
F4 G3
G2
G6 E4
AD4 AD3
AD1
AC4 AC2
AC1 AC5
AA6
AB3 AB5
AB6
C20
D21 A24
B25
C7
A22 A21
FSB_ADS_L FSB_BNR_L FSB_BPRI_L
FSB_DEFER_L FSB_DRDY_L FSB_DBSY_L
FSB_BREQ0_L
CPU_IERR_L
75
CPU_INIT_L
FSB_LOCK_L
FSB_CPURST_L FSB_RS_L<0> FSB_RS_L<1> FSB_RS_L<2> FSB_TRDY_L
FSB_HIT_L FSB_HITM_L
XDP_BPM_L<0> XDP_BPM_L<1> XDP_BPM_L<2> XDP_BPM_L<3> XDP_BPM_L<4> XDP_BPM_L<5> XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST_L XDP_DBRESET_L
CPU_PROCHOT_L CPU_THERMD_P CPU_THERMD_N
PM_THRMTRIP_L
FSB_CLK_CPU_P FSB_CLK_CPU_N
12 75
12 75
12 75
12 75
12 75
BI BI BI
BI BI BI
BI
IN
BI
IN IN IN IN IN
BI BI
BI BI BI BI BI
IN IN
OUT
IN IN
OUT
OUT OUT
OUT
IN IN
CPU JTAG Support
XDP_TMS
9
XDP_TDI
9
XDP_TDO
1 9
XDP_TCK
9
XDP_TRST_L
9
6
13 75
13 75
13 75
13 75
13 75
13 75
13 75
13 75
6
13 75
12 13 75
13 75
13 75
13 75
13 75
6
13 75
6
13 75
12 75
12 75
12 75
12 75
12 75
9
12 75
9
12 75
1 9
12 75
9
12 75
9
12 75
12 24
46 82
46 82
13 41 75
13 75
13 75
R1091
1 2
R1094
1 2
54.9
1/16W MF-LF
402
649
1/16W MF-LF
402
R1000
54.9
1/16W MF-LF
PP1V05_S0
1
1%
402
2
6 7
10 11 12 13 16 17 19 21 22
23 35 61 65 66 67
D
OMIT
AD26
AF26
E22
F24
E26 G22
F23
G25 E25
E23 K24
G24
J24 J23
H22
F26 K22
H23
J26 H26
H25
N22
K25
P26 R23
L23
M24 L22
M23 P25
P23
P22 T24
R24
L25 T25
N25
L26 M26
N24
C23 D25
C24
AF1
A26
B22
B23 C21
C3
D0* D1* D2* D3* D4* D5* D6* D7* D8* D9* D10* D11* D12* D13* D14* D15* DSTBN0* DSTBP0* DINV0*
D16* D17* D18* D19* D20* D21* D22* D23* D24* D25* D26* D27* D28* D29* D30* D31* DSTBN1* DSTBP1* DINV1*
GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 BSEL0 BSEL1 BSEL2
U1000
PENRYN
FCBGA
2 OF 4
DATA GRP 0DATA GRP 1
MISC
DATA GRP 3 DATA GRP 2
FSB_D_L<0>
6
13 75
BI
FSB_D_L<1>
6
13 75
1
R1001
54.9
1% 1/16W MF-LF
402
2
1
R1002
68
5% 1/16W MF-LF
402
2
R1090
54.9
1 2
1% 1/16W MF-LF
402
1%
1%
R1092
54.9
1 2
1% 1/16W MF-LF
402
R1093
54.9
1 2
1% 1/16W MF-LF
402
1
R1005
1K
1% 1/16W MF-LF 402
2
1
R1006
2.0K
1% 1/16W MF-LF 402
2
BI
13 41 61 75
OUT
NO STUFF
R1011
1/16W MF-LF
12 75
NO STUFF
1
C1014
NO STUFF
1
R1012
1K
5% 1/16W MF-LF 402
2
0.1uF
10% 16V
2
X5R 402
PLACEMENT_NOTE=Place C1014 within 12.7mm of CPU. PLACEMENT_NOTE=Place R1005 within 12.7mm of CPU. PLACEMENT_NOTE=Place R1006 within 12.7mm of CPU.
NO STUFF
R1010
0
1 2
5%
1/16W
1
MF-LF
402
1K
5%
402
2
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
6
13 75
8
75
8
75
8
75
BI
FSB_D_L<2>
BI
FSB_D_L<3>
BI
FSB_D_L<4>
BI
FSB_D_L<5>
BI
FSB_D_L<6>
BI
FSB_D_L<7>
BI
FSB_D_L<8>
BI
FSB_D_L<9>
BI
FSB_D_L<10>
BI
FSB_D_L<11>
BI
FSB_D_L<12>
BI
FSB_D_L<13>
BI
FSB_D_L<14>
BI
FSB_D_L<15>
BI
FSB_DSTB_L_N<0>
BI
FSB_DSTB_L_P<0>
BI
FSB_DINV_L<0>
BI
FSB_D_L<16>
BI
FSB_D_L<17>
BI
FSB_D_L<18>
BI
FSB_D_L<19>
BI
FSB_D_L<20>
BI
FSB_D_L<21>
BI
FSB_D_L<22>
BI
FSB_D_L<23>
BI
FSB_D_L<24>
BI
FSB_D_L<25>
BI
FSB_D_L<26>
BI
FSB_D_L<27>
BI
FSB_D_L<28>
BI
FSB_D_L<29>
BI
FSB_D_L<30>
BI
FSB_D_L<31>
BI
FSB_DSTB_L_N<1>
BI
FSB_DSTB_L_P<1>
BI
FSB_DINV_L<1>
BI
CPU_GTLREF
25 75
CPU_TEST1
CPU_TEST2 TP_CPU_TEST3 CPU_TEST4 TP_CPU_TEST5 TP_CPU_TEST6
TP_CPU_TEST7
CPU_BSEL<0>
OUT
CPU_BSEL<1>
OUT
CPU_BSEL<2>
OUT
D32* D33* D34* D35* D36* D37* D38* D39* D40* D41* D42* D43* D44* D45* D46*
D47* DSTBN2* DSTBP2*
DINV2*
D48*
D49*
D50*
D51*
D52*
D53*
D54*
D55*
D56*
D57*
D58*
D59*
D60*
D61*
D62*
D63* DSTBN3* DSTBP3*
DINV3*
COMP0 COMP1 COMP2 COMP3
DPRSTP*
DPSLP*
DPWR*
PWRGOOD
SLP*
PSI*
Y22
AB24 V24
V26
V23 T22
U25 U23
Y25
W22 Y23
W24
W25 AA23
AA24
AB25 Y26
AA26 U22
AE24
AD24
AA21 AB22
AB21
AC26 AD20
AE22 AF23
AC25
AE21 AD21
AC22
AD23 AF22
AC23
AE25
AF24 AC20
R26
U26
AA1 Y1
E5 B5
D24
D6 D7
AE6
75
75
75
75
FSB_D_L<32> FSB_D_L<33> FSB_D_L<34> FSB_D_L<35> FSB_D_L<36> FSB_D_L<37> FSB_D_L<38> FSB_D_L<39> FSB_D_L<40> FSB_D_L<41> FSB_D_L<42> FSB_D_L<43> FSB_D_L<44> FSB_D_L<45> FSB_D_L<46> FSB_D_L<47> FSB_DSTB_L_N<2> FSB_DSTB_L_P<2> FSB_DINV_L<2>
FSB_D_L<48> FSB_D_L<49> FSB_D_L<50> FSB_D_L<51> FSB_D_L<52> FSB_D_L<53> FSB_D_L<54> FSB_D_L<55> FSB_D_L<56> FSB_D_L<57> FSB_D_L<58> FSB_D_L<59> FSB_D_L<60> FSB_D_L<61> FSB_D_L<62> FSB_D_L<63> FSB_DSTB_L_N<3> FSB_DSTB_L_P<3> FSB_DINV_L<3>
CPU_COMP<0> CPU_COMP<1> CPU_COMP<2> CPU_COMP<3>
CPU_DPRSTP_L CPU_DPSLP_L FSB_DPWR_L CPU_PWRGD FSB_CPUSLP_L CPU_PSI_L
6
13 75
BI
6
13 75
BI
6
13 75
BI
6
13 75
BI
6
13 75
BI
6
13 75
BI
6
13 75
BI
6
13 75
BI
6
13 75
BI
6
13 75
BI
6
13 75
BI
6
13 75
BI
6
13 75
BI
6
13 75
BI
6
13 75
BI
6
13 75
BI
6
13 75
BI
6
13 75
BI
6
13 75
BI
6
13 75
BI
6
13 75
BI
6
13 75
BI
6
13 75
BI
6
13 75
BI
6
13 75
BI
6
13 75
BI
6
13 75
BI
6
13 75
BI
6
13 75
BI
6
13 75
BI
6
13 75
BI
6
13 75
BI
6
13 75
BI
6
13 75
BI
6
13 75
BI
6
13 75
BI
6
13 75
BI
6
13 75
BI
13 61 75
IN
13 75
IN
13 75
IN
12 13 75
IN
13 75
IN
61
OUT
PLACEMENT_NOTE (all 4 resistors):
Place within 12.7mm of CPU
Place within 12.7mm of CPU
Place within 12.7mm of CPU
Place within 12.7mm of CPU
R1023
54.9
1/16W MF-LF
C
B
1
1%
402
2
1
2
R1021
R1022
27.4
1% 1/16W MF-LF 402
54.9
1/16W MF-LF
1
1%
402
2
1
R1020
27.4
1% 1/16W MF-LF 402
2
CPU FSB
SHT
9
SYNC_DATE=02/05/2009
OF
83
1
A
REV.
A
A
SYNC FROM T18 CHANGE CPU FROM SOCKET TO BGA SYMBOL
8
7 6
5
4
3
SYNC_MASTER=K24_MLB
APPLE INC.
2
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
D
SCALE
051-7903
NONE
8 7
6
5
4
3
D
C
B
A
SYNC FROM T18 CHANGE CPU FROM SOCKET TO BGA SYMBOL
Current numbers from Merom for Santa Rosa EMTS, doc #20905.
8
AB10
AB12 AB14
AB15
AB17 AB18
AA10
AA12
AA13 AA15
AA17
AA18 AA20
AC10
A7
A9
A10 A12
A13
A15 A17
A18 A20
B7
B9 B10
B12
B14 B15
B17
B18 B20
C9 C10
C12
C13 C15
C17
C18
D9
D10
D12 D14
D15
VCC
D17
D18
E7
E9
E10
E12 E13
E15
E17 E18
E20
F7
F9
F10 F12
F14
F15 F17
F18
F20 AA7
AA9
AB9
(BR1#)
OMIT
U1000
PENRYN
FCBGA
3 OF 4
VCCSENSE
VSSSENSE
VCC
VCCP
VCCA
VID0 VID1 VID2 VID3 VID4 VID5 VID6
AB20
AB7
AC7 AC9
AC12
AC13 AC15
AC17 AC18
AD7
AD9 AD10
AD12
AD14 AD15
AD17
AD18 AE9
AE10 AE12
AE13
AE15 AE17
AE18
AE20 AF9 AF10
AF12
AF14 AF15
AF17
AF18 AF20
G21 V6
J6 K6
M6
J21 K21
M21
N21 N6
R21
R6
T21 T6
V21
W21
B26 C26
AD6 AF5
AE5
AF4 AE3
AF3
AE2
AF7
AE7
7 6
(CPU CORE POWER) PPVCORE_S0_CPU
6 7
30.4 A (SV LFM)
(CPU IO POWER 1.05V)
PP1V05_S0
6 7 9 23 35 61 65 66 67
4500 mA (before VCC stable) 2500 mA (after VCC stable)
(CPU INTERNAL PLL POWER 1.5V) PP1V5_S0
6 7
130 mA
CPU_VID<0> CPU_VID<1> CPU_VID<2> CPU_VID<3> CPU_VID<4> CPU_VID<5> CPU_VID<6>
8
75
OUT
8
75
OUT
8
75
OUT
8
75
OUT
8
75
OUT
8
75
OUT
8
75
OUT
CPU_VCCSENSE_P
CPU_VCCSENSE_N
10 11 44 61
44 A (SV Design Target) 41 A (SV HFM)
23 A (LV Design Target)
11 12 13 16 17 19 21 22
11 15 22 37 66 67 68 82
PPVCORE_S0_CPU
1
R1100
100
1% 1/16W MF-LF 402
2
OUT
PLACEMENT_NOTE=Place R1100 within 25.4mm of CPU, no stubs. PLACEMENT_NOTE=Place R1101 within 25.4mm of CPU, no stubs.
OUT
1
R1101
100
1% 1/16W MF-LF 402
2
61 75
61 75
6 7
5
10 11 44 61
A4 A8
A11 A14
A16
A19 A23
AF2
B6 B8
B11
B13 B16
B19 B21
B24
C5 C8
C11
C14 C16
C19
C2 C22
C25
D1
D4
D8 D11
D13
D16 D19
D23
D26
E3
E6
E8
E11 E14
VSS VSS
E16 E19
E21 E24
F5
F8 F11
F13 F16
F19
F2 F22
F25
G4
G1
G23
G26
H3
H6 H21
H24
J2
J5
J22
J25
K1
K4
K23 K26
L3
L6
L21
L24
M2
M5
M22 M25
N1
N4 N23
N26
P3
B1
(Socket-P KEY)
OMIT
U1000
PENRYN
FCBGA
4 OF 4
T26
U3 U6
U21 U24
V2
V5
V22 V25
W1
W4 W23
W26 Y3
Y6 Y21
Y24
AA2 AA5
AA8
AA11 AA14
AA16
AA19 AA22
AA25 AB1
AB4
AB8 AB11
AB13
AB16 AB19
AB23
AB26 AC3
AC6
AC8
AC11 AC14
AC16 AC19
AC21
AC24 AD2 AD5 AD8
AD11 AD13
AD16
AD19 AD22
AD25
AE1
AE4 AE8
AE11
AE14 AE16
AE19
AE23 AE26
A2 AF6
AF8
AF11 AF13
AF16
AF19 AF21
A25
AF25
P6
P21 P24
R2
R5 R22
R25 T1
T4
T23
D
C
B
CPU Power & Ground
SHT
SYNC_DATE=02/05/2009
OF
8310
1
A
REV.
A
SYNC_MASTER=K24_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
APPLE INC.
4
3
2
SCALE
D
051-7903
NONE
8 7
6
5
4
3
CPU VCore HF and Bulk Decoupling
4X 330UF. 20X 22UF 0805
PPVCORE_S0_CPU
6 7
10 44 61
D
PLACEMENT_NOTE (C1200-C1219):
Place inside socket cavity on secondary side.
Place inside socket cavity on secondary side.
Place inside socket cavity on secondary side.
Place inside socket cavity on secondary side.
Place inside socket cavity on secondary side.
Place inside socket cavity on secondary side.
Place inside socket cavity on secondary side.
Place inside socket cavity on secondary side.
Place inside socket cavity on secondary side.
Place inside socket cavity on secondary side.
Place inside socket cavity on secondary side.
Place inside socket cavity on secondary side.
Place inside socket cavity on secondary side.
Place inside socket cavity on secondary side.
Place inside socket cavity on secondary side.
Place inside socket cavity on secondary side.
Place inside socket cavity on secondary side.
Place inside socket cavity on secondary side.
Place inside socket cavity on secondary side.
Place inside socket cavity on secondary side.
CRITICAL
1
C1200
22UF
20%
6.3V
2
CERM-X5R 805
CRITICAL
1
C1201
22UF
20%
6.3V
2
CERM-X5R 805
CRITICAL
1
C1202
22UF
20%
6.3V
2
CERM-X5R 805
CRITICAL
1
C1203
22UF
20%
6.3V
2
CERM-X5R
805
CRITICAL
1
C1204
22UF
20%
6.3V
2
CERM-X5R 805
CRITICAL
1
C1205
22UF
20%
6.3V
2
CERM-X5R 805
CRITICAL
1
C1206
22UF
20%
6.3V
2
CERM-X5R 805
CRITICAL
1
C1207
22UF
20%
6.3V
2
CERM-X5R 805
CRITICAL
1
C1208
22UF
20%
6.3V
2
CERM-X5R 805
CRITICAL
1
C1209
22UF
20%
6.3V
2
CERM-X5R 805
D
CRITICAL
1
C1210
22UF
20%
6.3V
2
CERM-X5R 805
CRITICAL
1
C1211
22UF
20%
6.3V
2
CERM-X5R 805
CRITICAL
1
C1212
22UF
20%
6.3V
2
CERM-X5R 805
CRITICAL
1
C1213
22UF
20%
6.3V
2
CERM-X5R 805
CRITICAL
1
C1214
22UF
20%
6.3V
2
CERM-X5R 805
CRITICAL
1
C1215
22UF
20%
6.3V
2
CERM-X5R 805
C
CRITICAL
1
C1216
22UF
20%
6.3V
2
CERM-X5R 805
CRITICAL
1
C1217
22UF
20%
6.3V
2
CERM-X5R 805
CRITICAL
1
C1218
22UF
20%
6.3V
2
CERM-X5R 805
CRITICAL
1
C1219
22UF
20%
6.3V
2
CERM-X5R 805
C
PLACEMENT_NOTE (C1240-C1243):
Place on secondary side.
NOSTUFF
CRITICAL
1
C1240
470UF-4MOHM
20%
2.0V
23
POLY-TANT D2T-SM
Place on secondary side.
CRITICAL
1
C1241
470UF-4MOHM
20%
2.0V
23
POLY-TANT D2T-SM
Place on secondary side.
CRITICAL
1
C1242
470UF-4MOHM
20%
2.0V
23
POLY-TANT D2T-SM
Place on secondary side.
CRITICAL
1
C1243
470UF-4MOHM
20%
2.0V
23
POLY-TANT D2T-SM
VCCA (CPU AVdd) DECOUPLING
10 15 22 37 66 67 68 82
PP1V5_S0
6 7
1x 10uF, 1x 0.01uF
1
C1250
10uF
20%
6.3V 2
X5R 603
PLACEMENT_NOTE=Place C1281 near CPU pin B26.
1
C1251
0.01UF
10% 16V
2
CERM 402
B
B
VCCP (CPU I/O) DECOUPLING
PP1V05_S0
6 7 9
10 12 13 16 17 19 21 22
23 35 61 65 66 67
CRITICAL
A
SYNC FROM T18 REMOVE NO STUFF CAPS C1220 TO C1231 REMOVE C1244 & C1245 CHANGE C1240-C1243 AND C1260 FROM 128S0241(9 MILLI-OHM) TO 128S0231(6 MILLI-OHM)
8
7 6
1x 330uF, 6x 0.1uF 0402
PLACEMENT_NOTE=Place C1260 between CPU & NB.
1
C1260
330UF
POLY-TANT
D2T-SM2
1
C1261
0.1UF
2 3
20% 10V
2
CERM 402
20%
2.0V
1
2
C1262
0.1UF
20% 10V CERM 402
1
C1263
2
5
0.1UF
20% 10V CERM 402
1
C1264
0.1UF
2
20% 10V CERM 402
1
C1265
2
0.1UF
20% 10V CERM 402
1
C1266
0.1UF
20% 10V
2
CERM 402
CPU Decoupling
SHT
SYNC_DATE=02/05/2009
OF
8311
1
A
REV.
A
SYNC_MASTER=K24_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
APPLE INC.
4
3
2
SCALE
D
051-7903
NONE
8 7
6
5
4
3
Mini-XDP Connector
NOTE: This is not the standard XDP pinout.
D
Use with 920-0620 adapter board to support CPU, MCP debugging.
D
MCP79-specific pinout
58 61 66 67 68 69 71 72 82
PP3V3_S0
6 7
17 18 20 21 22 23 26 27
35 37 41 43 45 46 47 49 53 57
PP1V05_S0
6 7 9
10 11 13 16 17 19 21 22
23 35 61 65 66 67
XDP
1
R1315
54.9
1% 1/16W MF-LF
402
2
9
75
BI
XDP_BPM_L<4>
9
75
BI
XDP_BPM_L<3>
9
75
BI
XDP_BPM_L<2>
9
75
IN
XDP_BPM_L<1>
9
75
IN
XDP_BPM_L<0>
9
75
IN
C
XDP
R1399
1K
CPU_PWRGD
9
13 75
IN
1 2
5% 1/16W MF-LF
402
18
IN
20
OUT
20 26 43 78
BI
20 26 27 43 78
BI
9
75
OUT
TP_XDP_OBSFN_B0 TP_XDP_OBSFN_B1
TP_XDP_OBSDATA_B0 TP_XDP_OBSDATA_B1
TP_XDP_OBSDATA_B2 TP_XDP_OBSDATA_B3
XDP_PWRGD
PM_LATRIGGER_L JTAG_MCP_TCK
SMBUS_MCP_0_DATA SMBUS_MCP_0_CLK
XDP_TCK
XDP_OBS20
OBSFN_A0 OBSFN_A1
OBSDATA_A0 OBSDATA_A1
OBSDATA_A2 OBSDATA_A3
OBSFN_B0 OBSFN_B1
OBSDATA_B0 OBSDATA_B1 OBSDATA_D1
OBSDATA_B2 OBSDATA_B3
PWRGD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2 HOOK3
SDA
SCL TCK1 TCK0
XDP
1
C1300
0.1uF
10% 16V
2
X5R 402
B
CRITICAL XDP_CONN
NC
J1300
F-ST-SM 2 4 6
10
20
30
40
50
60
1 3 5 78
9 1112 1314 1516 1718 19 2122 2324 2526 2728 29 3132 3334 3536 3738 39 4142 4344 4546 4748 49 5152 5354 5556 5758 59
LTH-030-01-G-D-NOPEGS
998-1571
OBSFN_C0 OBSFN_C1
OBSDATA_C0 OBSDATA_C1
OBSDATA_C2 OBSDATA_C3
OBSFN_D0 OBSFN_D1
OBSDATA_D0
OBSDATA_D2 OBSDATA_D3
ITPCLK/HOOK4 ITPCLK#/HOOK5 VCC_OBS_CD RESET#/HOOK6 DBR#/HOOK7 NOTE: XDP_DBRESET_L must be pulled-up to 3.3V. TDO TRSTn TDI TMS XDP_PRESENT#
XDP
1
C1301
0.1uF
10% 16V
2
X5R 402
JTAG_MCP_TDOXDP_BPM_L<5> JTAG_MCP_TRST_L
MCP_DEBUG<0> MCP_DEBUG<1>
MCP_DEBUG<2> MCP_DEBUG<3>
JTAG_MCP_TDI JTAG_MCP_TMS
MCP_DEBUG<4> MCP_DEBUG<5>
MCP_DEBUG<6> MCP_DEBUG<7>
FSB_CLK_ITP_P FSB_CLK_ITP_N
XDP_CPURST_L
75
XDP_DBRESET_L
XDP_TDO XDP_TRST_L XDP_TDI XDP_TMS
1
20
IN
20
OUT
18 78
BI
18 78
BI
18 78
BI
18 78
BI
20
OUT
20
OUT
18 78
BI
18 78
BI
18 78
BI
18 78
BI
13 75
IN
13 75
IN
9
24
OUT
1 9
75
IN
9
75
OUT
9
75
OUT
9
75
OUT
XDP
R1303
1K
1 2
1/16W MF-LF
FSB_CPURST_L
5%
PLACEMENT_NOTE=Place close to CPU to minimize stub.
402
9
13 75
IN
C
B
Direction of XDP module
Please avoid any obstructions on even-numbered side of J1300
eXtended Debug Port(MiniXDP)
SHT
12
SYNC_DATE=02/05/2009
OF
83
1
A
REV.
A
A
8
7 6
5
4
3
SYNC_MASTER=K19_MLB
APPLE INC.
2
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
D
SCALE
051-7903
NONE
8 7
6
D
C
PP1V05_S0
6 7 9
10 11 12 13 16 17 19 21
22 23 35 61 65 66 67
R1415
1/16W MF-LF
R1421
1/16W MF-LF
1
1
R1416
62
62
5%
5% 1/16W MF-LF
402
402
2
2
NO STUFF
1
1
R1422
1K
1K
5%
5%
1/16W MF-LF 402
402
2
2
1
R1430
49.9
1/16W MF-LF
1
R1435
49.9
1%
1% 1/16W MF-LF
402
402
2
2
1
R1410
54.9
1% 1/16W MF-LF
402
2
B
9
41 75
9
75
8
8
8
PM_THRMTRIP_L
IN
CPU_FERR_L
IN
=MCP_BSEL<2>
IN
=MCP_BSEL<1>
IN
=MCP_BSEL<0>
IN
NO STUFF
R1420
1/16W MF-LF
1K
5%
402
NO STUFF
1
2
A
1
1
R1431
49.9
1/16W MF-LF
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
8
7 6
R1436
49.9
1%
1%
1/16W MF-LF 402
402
2
2
5
4
3
OMIT
U1400
MCP79-TOPO-B
BGA
FSB_DSTB_L_P<0>
6 9
75
BI
FSB_DSTB_L_N<0>
6 9
75
BI
FSB_DINV_L<0>
6 9
75
BI
FSB_DSTB_L_P<1>
6 9
75
BI
FSB_DSTB_L_N<1>
6 9
75
BI
FSB_DINV_L<1>
6 9
75
BI
FSB_DSTB_L_P<2>
6 9
75
BI
FSB_DSTB_L_N<2>
6 9
75
BI
FSB_DINV_L<2>
6 9
75
BI
FSB_DSTB_L_P<3>
6 9
75
BI
FSB_DSTB_L_N<3>
6 9
75
BI
FSB_DINV_L<3>
6 9
75
BI
FSB_A_L<3>
6 9
75
BI
FSB_A_L<4>
6 9
75
BI
FSB_A_L<5>
6 9
75
BI
FSB_A_L<6>
6 9
75
BI
FSB_A_L<7>
6 9
75
BI
FSB_A_L<8>
6 9
75
BI
FSB_A_L<9>
6 9
75
BI
FSB_A_L<10>
6 9
75
BI
FSB_A_L<11>
6 9
75
BI
FSB_A_L<12>
6 9
75
BI
FSB_A_L<13>
6 9
75
BI
FSB_A_L<14>
6 9
75
BI
FSB_A_L<15>
6 9
75
BI
FSB_A_L<16>
6 9
75
BI
FSB_A_L<17>
6 9
75
BI
FSB_A_L<18>
6 9
75
BI
FSB_A_L<19>
6 9
75
BI
FSB_A_L<20>
6 9
75
BI
FSB_A_L<21>
6 9
75
BI
FSB_A_L<22>
6 9
75
BI
FSB_A_L<23>
6 9
75
BI
FSB_A_L<24>
6 9
75
BI
FSB_A_L<25>
6 9
75
BI
FSB_A_L<26>
6 9
75
BI
FSB_A_L<27>
6 9
75
BI
FSB_A_L<28>
6 9
75
BI
FSB_A_L<29>
6 9
75
BI
FSB_A_L<30>
6 9
75
BI
FSB_A_L<31>
6 9
75
BI
FSB_A_L<32>
9
75
BI
FSB_A_L<33>
9
75
BI
FSB_A_L<34>
9
75
BI
FSB_A_L<35>
9
75
BI
FSB_ADSTB_L<0>
6 9
75
BI
FSB_ADSTB_L<1>
6 9
75
BI
FSB_REQ_L<0>
6 9
75
BI
FSB_REQ_L<1>
6 9
75
BI
FSB_REQ_L<2>
6 9
75
BI
FSB_REQ_L<3>
6 9
75
BI
FSB_REQ_L<4>
6 9
75
BI
FSB_ADS_L
6 9
75
BI
FSB_BNR_L
9
75
BI
FSB_BREQ0_L
9
75
BI
FSB_BREQ1_L
75
FSB_DBSY_L
9
75
BI
FSB_DRDY_L
9
75
BI
FSB_HIT_L
6 9
75
BI
FSB_HITM_L
6 9
75
BI
FSB_LOCK_L
6 9
75
IN
FSB_TRDY_L
9
75
OUT
TP_CPU_PECI_MCP
8
OUT
CPU_PROCHOT_L
9
41 61 75
OUT
(MCP_BSEL<2>) (MCP_BSEL<1>) (MCP_BSEL<0>)
FSB_RS_L<0>
9
75
OUT
FSB_RS_L<1>
9
75
OUT
FSB_RS_L<2>
9
75
OUT
PP1V05_S0_MCP_PLL_FSB
22
MCP_BCLK_VML_COMP_VDD
75
MCP_BCLK_VML_COMP_GND
75
MCP_CPU_COMP_VCC
75
MCP_CPU_COMP_GND
75
206 mA270 mA (A01)
20 mA 29 mA 15 mA
T40
CPU_DSTBP0#
U40
CPU_DSTBN0#
V41
CPU_DBI0#
W39
CPU_DSTBP1#
W37
CPU_DSTBN1#
V35
CPU_DBI1#
N37
CPU_DSTBP2#
L36
CPU_DSTBN2#
N35
CPU_DBI2#
M39
CPU_DSTBP3#
M41
CPU_DSTBN3#
J41
CPU_DBI3#
AC34
CPU_A3#
AE38
CPU_A4#
AE34
CPU_A5#
AC37
CPU_A6#
AE37
CPU_A7#
AE35
CPU_A8#
AB35
CPU_A9#
AF35
CPU_A10#
AG35
CPU_A11#
AG39
CPU_A12#
AE33
CPU_A13#
AG37
CPU_A14#
AG38
CPU_A15#
AG34
CPU_A16#
AN38
CPU_A17#
AL39
CPU_A18#
AG33
CPU_A19#
AL33
CPU_A20#
AJ33
CPU_A21#
AN36
CPU_A22#
AJ35
CPU_A23#
AJ37
CPU_A24#
AJ36
CPU_A25#
AJ38
CPU_A26#
AL37
CPU_A27#
AL34
CPU_A28#
AN37
CPU_A29#
AJ34
CPU_A30#
AL38
CPU_A31#
AL35
CPU_A32#
AN34
CPU_A33#
AR39
CPU_A34#
AN35
CPU_A35#
AE36
CPU_ADSTB0#
AK35
CPU_ADSTB1#
AC38
CPU_REQ0#
AA33
CPU_REQ1#
AC39
CPU_REQ2#
AC33
CPU_REQ3#
AC35
CPU_REQ4#
AD42
CPU_ADS#
AD43
CPU_BNR#
AE40
CPU_BR0#
AL32
CPU_BR1#
AD39
CPU_DBSY#
AD41
CPU_DRDY#
AB42
CPU_HIT#
AD40
CPU_HITM#
AC43
CPU_LOCK#
AE41
CPU_TRDY#
E41
CPU_PECI
AJ41
CPU_PROCHOT#
AG43
CPU_THERMTRIP#
AH40
CPU_FERR#
F42
CPU_BSEL2
D42
CPU_BSEL1
F41
CPU_BSEL0
AC41
CPU_RS0#
AB41
CPU_RS1#
AC42
CPU_RS2#
AG27
+V_DLL_DLCELL_AVDD
AH27
+V_PLL_MCLK
AG28
+V_PLL_FSB
AH28
+V_PLL_CPU
AM39
BCLK_VML_COMP_VDD
AM40
BCLK_VML_COMP_GND
AM43
CPU_COMP_VCC
AM42
CPU_COMP_GND
(1 OF 11)
FSB
CPU_BPRI#
CPU_DEFER#
BCLK_OUT_CPU_P BCLK_OUT_CPU_N
BCLK_OUT_ITP_P BCLK_OUT_ITP_N
BCLK_OUT_NB_P BCLK_OUT_NB_N
BCLK_IN_N BCLK_IN_P
CPU_A20M#
CPU_IGNNE#
CPU_INIT#
CPU_PWRGD
CPU_RESET#
CPU_DPSLP#
CPU_DPWR# CPU_STPCLK# CPU_DPRSTP#
5
CPU_D0# CPU_D1# CPU_D2# CPU_D3# CPU_D4# CPU_D5# CPU_D6# CPU_D7# CPU_D8#
CPU_D9# CPU_D10# CPU_D11# CPU_D12# CPU_D13# CPU_D14# CPU_D15# CPU_D16# CPU_D17# CPU_D18# CPU_D19# CPU_D20# CPU_D21# CPU_D22# CPU_D23# CPU_D24# CPU_D25# CPU_D26# CPU_D27# CPU_D28# CPU_D29# CPU_D30# CPU_D31# CPU_D32# CPU_D33# CPU_D34# CPU_D35# CPU_D36# CPU_D37# CPU_D38# CPU_D39# CPU_D40# CPU_D41# CPU_D42# CPU_D43# CPU_D44# CPU_D45# CPU_D46# CPU_D47# CPU_D48# CPU_D49# CPU_D50# CPU_D51# CPU_D52# CPU_D53# CPU_D54# CPU_D55# CPU_D56# CPU_D57# CPU_D58# CPU_D59# CPU_D60# CPU_D61# CPU_D62# CPU_D63#
CPU_INTR
CPU_NMI CPU_SMI#
CPU_SLP#
4
Y43 W42 Y40 W41 Y39 V42 Y41 Y42 P42 U41 R42 T39 T42 T41 R41 T43 W35 AA37 W33 W34 AA36 AA34 AA38 AA35 U38 U36 U35 U33 U34 W38 R33 U37 N34 N33 R34 R35 P35 R39 R37 R38 L37 L39 L38 N36 N38 J39 J38 J37 L42 M42 P41 N41 N40 M40 H40 K42 H41 L41 H43 H42 K41 J40 H39 M43
AA41 AA40
G42 G41
AL43 AL42
AL41 AK42
AK41 AJ40
AF41 AH39 AH42 AF42 AG41 AH41
AH43 H38
AM33 AN33 AM32 AG42 AN32
FSB_D_L<0> FSB_D_L<1> FSB_D_L<2> FSB_D_L<3> FSB_D_L<4> FSB_D_L<5> FSB_D_L<6> FSB_D_L<7> FSB_D_L<8> FSB_D_L<9> FSB_D_L<10> FSB_D_L<11> FSB_D_L<12> FSB_D_L<13> FSB_D_L<14> FSB_D_L<15> FSB_D_L<16> FSB_D_L<17> FSB_D_L<18> FSB_D_L<19> FSB_D_L<20> FSB_D_L<21> FSB_D_L<22> FSB_D_L<23> FSB_D_L<24> FSB_D_L<25> FSB_D_L<26> FSB_D_L<27> FSB_D_L<28> FSB_D_L<29> FSB_D_L<30> FSB_D_L<31> FSB_D_L<32> FSB_D_L<33> FSB_D_L<34> FSB_D_L<35> FSB_D_L<36> FSB_D_L<37> FSB_D_L<38> FSB_D_L<39> FSB_D_L<40> FSB_D_L<41> FSB_D_L<42> FSB_D_L<43> FSB_D_L<44> FSB_D_L<45> FSB_D_L<46> FSB_D_L<47> FSB_D_L<48> FSB_D_L<49> FSB_D_L<50> FSB_D_L<51> FSB_D_L<52> FSB_D_L<53> FSB_D_L<54> FSB_D_L<55> FSB_D_L<56> FSB_D_L<57> FSB_D_L<58> FSB_D_L<59> FSB_D_L<60> FSB_D_L<61> FSB_D_L<62> FSB_D_L<63>
FSB_BPRI_L FSB_DEFER_L
FSB_CLK_CPU_P FSB_CLK_CPU_N
FSB_CLK_ITP_P FSB_CLK_ITP_N
FSB_CLK_MCP_P
75
75
FSB_CLK_MCP_N
CPU_A20M_L CPU_IGNNE_L CPU_INIT_L CPU_INTR CPU_NMI CPU_SMI_L
CPU_PWRGD FSB_CPURST_L
FSB_CPUSLP_L CPU_DPSLP_L FSB_DPWR_L CPU_STPCLK_L CPU_DPRSTP_L
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
6 9
75
BI
9
75
OUT
9
75
OUT
9
75
OUT
9
75
OUT
12 75
OUT
12 75
OUT
Loop-back clock for delay matching.
9
75
OUT
9
75
OUT
9
75
OUT
9
75
OUT
9
75
OUT
9
75
OUT
9
12 75
OUT
9
75
OUT
9
75
OUT
9
75
OUT
9
75
OUT
9
61 75
OUT
PP1V05_S0
NO STUFF
1
R1440
150
5% 1/16W MF-LF 402
2
9
OUT
12 75
3
6 7 9
10 11 12 13 16 17 19 21
22 23 35 61 65 66 67
SYNC_MASTER=T18_MLB
APPLE INC.
2
MCP CPU Interface
SYNC_DATE=02/05/2009
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
D
SCALE
NONE
051-7903
SHT
1
D
C
B
A
REV.
A
OF
8313
8 7
6
5
4
3
OMIT
U1400
MCP79-TOPO-B
BGA
MDQ0_63 MDQ0_62 MDQ0_61 MDQ0_60 MDQ0_59 MDQ0_58 MDQ0_57 MDQ0_56 MDQ0_55 MDQ0_54 MDQ0_53 MDQ0_52 MDQ0_51 MDQ0_50 MDQ0_49 MDQ0_48 MDQ0_47 MDQ0_46 MDQ0_45 MDQ0_44 MDQ0_43 MDQ0_42 MDQ0_41 MDQ0_40 MDQ0_39 MDQ0_38 MDQ0_37 MDQ0_36 MDQ0_35 MDQ0_34 MDQ0_33 MDQ0_32 MDQ0_31 MDQ0_30 MDQ0_29 MDQ0_28 MDQ0_27 MDQ0_26 MDQ0_25 MDQ0_24 MDQ0_23 MDQ0_22 MDQ0_21 MDQ0_20 MDQ0_19 MDQ0_18 MDQ0_17 MDQ0_16 MDQ0_15 MDQ0_14 MDQ0_13 MDQ0_12 MDQ0_11 MDQ0_10 MDQ0_9 MDQ0_8 MDQ0_7 MDQ0_6 MDQ0_5 MDQ0_4 MDQ0_3 MDQ0_2 MDQ0_1 MDQ0_0
MDQM0_7 MDQM0_6 MDQM0_5 MDQM0_4 MDQM0_3 MDQM0_2 MDQM0_1 MDQM0_0
(2 OF 11)
MDQS0_7_P MDQS0_7_N MDQS0_6_P MDQS0_6_N MDQS0_5_P MDQS0_5_N MDQS0_4_P MDQS0_4_N MDQS0_3_P MDQS0_3_N MDQS0_2_P MDQS0_2_N MDQS0_1_P MDQS0_1_N MDQS0_0_P MDQS0_0_N
MEMORY PARTITION 0
MEMORY
CONTROL
MCLK0A_2_P MCLK0A_2_N
MCLK0A_1_P MCLK0A_1_N
MCLK0A_0_P MCLK0A_0_N
MEM_A_DQ<63>
26 76
BI
MEM_A_DQ<62>
26 76
BI
MEM_A_DQ<61>
26 76
BI
MEM_A_DQ<60>
26 76
BI
MEM_A_DQ<59>
26 76
D
C
B
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
OUT
26 76
OUT
26 76
OUT
26 76
OUT
26 76
OUT
26 76
OUT
26 76
OUT
26 76
OUT
MEM_A_DQ<58> MEM_A_DQ<57> MEM_A_DQ<56> MEM_A_DQ<55> MEM_A_DQ<54> MEM_A_DQ<53> MEM_A_DQ<52> MEM_A_DQ<51> MEM_A_DQ<50> MEM_A_DQ<49> MEM_A_DQ<48> MEM_A_DQ<47> MEM_A_DQ<46> MEM_A_DQ<45> MEM_A_DQ<44> MEM_A_DQ<43> MEM_A_DQ<42> MEM_A_DQ<41> MEM_A_DQ<40> MEM_A_DQ<39> MEM_A_DQ<38> MEM_A_DQ<37> MEM_A_DQ<36> MEM_A_DQ<35> MEM_A_DQ<34> MEM_A_DQ<33> MEM_A_DQ<32> MEM_A_DQ<31> MEM_A_DQ<30> MEM_A_DQ<29> MEM_A_DQ<28> MEM_A_DQ<27> MEM_A_DQ<26> MEM_A_DQ<25> MEM_A_DQ<24> MEM_A_DQ<23> MEM_A_DQ<22> MEM_A_DQ<21> MEM_A_DQ<20> MEM_A_DQ<19> MEM_A_DQ<18> MEM_A_DQ<17> MEM_A_DQ<16> MEM_A_DQ<15> MEM_A_DQ<14> MEM_A_DQ<13> MEM_A_DQ<12> MEM_A_DQ<11> MEM_A_DQ<10> MEM_A_DQ<9> MEM_A_DQ<8> MEM_A_DQ<7> MEM_A_DQ<6> MEM_A_DQ<5> MEM_A_DQ<4> MEM_A_DQ<3> MEM_A_DQ<2> MEM_A_DQ<1> MEM_A_DQ<0>
MEM_A_DM<7> MEM_A_DM<6> MEM_A_DM<5> MEM_A_DM<4> MEM_A_DM<3> MEM_A_DM<2> MEM_A_DM<1> MEM_A_DM<0>
AL8 AL9 AP9 AN9 AL6 AL7 AN6 AN7 AR6 AR7 AV6 AW5
AN10
AR5 AU6 AV5 AU7 AU8 AW9
AP11
AW6 AY5 AU9
AV9 AU11 AV11 AV13 AW13 AR11 AT11 AR14 AU13 AR26 AU25 AT27 AU27 AP25 AR25 AP27 AR27 AP29 AR29 AP31 AR31 AV27 AN29 AV29 AN31 AU31 AR33 AV37 AW37 AT31 AV31 AT37 AU37 AW39 AV39 AR37 AR38 AV38 AW38 AR35 AP35
AN5
AU5 AR10 AN13 AN27 AW29 AV35 AR34
MRAS0# MCAS0#
MWE0#
MBA0_2 MBA0_1 MBA0_0
MA0_14 MA0_13 MA0_12 MA0_11 MA0_10
MA0_9 MA0_8 MA0_7 MA0_6 MA0_5 MA0_4 MA0_3 MA0_2 MA0_1 MA0_0
0A
MCS0A_1# MCS0A_0#
MODT0A_1 MODT0A_0
MCKE0A_1 MCKE0A_0
AL10 AL11 AR8 AR9 AW7 AW8 AP13 AR13 AV25 AW25 AU30 AU29 AT35 AU35 AU39 AT39
AV17 AP17 AR17
AP23 AP19 AW17
AR23 AU15 AN23 AW21 AN19 AV21 AR22 AU21 AP21 AR21 AN21 AV19 AU19 AT19 AR19
AW33 AV33
BA24 AY24
BB20 BC20
AT15 AR18
AP15 AV15
AU23 AT23
MEM_A_DQS_P<7> MEM_A_DQS_N<7> MEM_A_DQS_P<6> MEM_A_DQS_N<6> MEM_A_DQS_P<5> MEM_A_DQS_N<5> MEM_A_DQS_P<4> MEM_A_DQS_N<4> MEM_A_DQS_P<3> MEM_A_DQS_N<3> MEM_A_DQS_P<2> MEM_A_DQS_N<2> MEM_A_DQS_P<1> MEM_A_DQS_N<1> MEM_A_DQS_P<0> MEM_A_DQS_N<0>
MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L
MEM_A_BA<2> MEM_A_BA<1> MEM_A_BA<0>
MEM_A_A<14> MEM_A_A<13> MEM_A_A<12> MEM_A_A<11> MEM_A_A<10> MEM_A_A<9> MEM_A_A<8> MEM_A_A<7> MEM_A_A<6> MEM_A_A<5> MEM_A_A<4> MEM_A_A<3> MEM_A_A<2> MEM_A_A<1> MEM_A_A<0>
TP_MEM_A_CLK2P NC_MEM_A_CLK2N
MEM_A_CLK_P<1> MEM_A_CLK_N<1>
MEM_A_CLK_P<0> MEM_A_CLK_N<0>
MEM_A_CS_L<1> MEM_A_CS_L<0>
MEM_A_ODT<1> MEM_A_ODT<0>
MEM_A_CKE<1> MEM_A_CKE<0>
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
BI
26 76
OUT
26 76
OUT
26 76
OUT
26 76
OUT
26 76
OUT
26 76
OUT
26 76
OUT
26 76
OUT
26 76
OUT
26 76
OUT
26 76
OUT
26 76
OUT
26 76
OUT
26 76
OUT
26 76
OUT
26 76
OUT
26 76
OUT
26 76
OUT
26 76
OUT
26 76
OUT
26 76
OUT
6
26 76
OUT
26 76
OUT
26 76
OUT
26 76
OUT
26 76
OUT
26 76
OUT
26 76
OUT
26 76
OUT
26 76
OUT
26 76
OUT
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
OUT
27 76
OUT
27 76
OUT
27 76
OUT
27 76
OUT
27 76
OUT
27 76
OUT
27 76
OUT
MEM_B_DQ<63> MEM_B_DQ<62> MEM_B_DQ<61> MEM_B_DQ<60> MEM_B_DQ<59> MEM_B_DQ<58> MEM_B_DQ<57> MEM_B_DQ<56> MEM_B_DQ<55> MEM_B_DQ<54> MEM_B_DQ<53> MEM_B_DQ<52> MEM_B_DQ<51> MEM_B_DQ<50> MEM_B_DQ<49> MEM_B_DQ<48> MEM_B_DQ<47> MEM_B_DQ<46> MEM_B_DQ<45> MEM_B_DQ<44> MEM_B_DQ<43> MEM_B_DQ<42> MEM_B_DQ<41> MEM_B_DQ<40> MEM_B_DQ<39> MEM_B_DQ<38> MEM_B_DQ<37> MEM_B_DQ<36> MEM_B_DQ<35> MEM_B_DQ<34> MEM_B_DQ<33> MEM_B_DQ<32> MEM_B_DQ<31> MEM_B_DQ<30> MEM_B_DQ<29> MEM_B_DQ<28> MEM_B_DQ<27> MEM_B_DQ<26> MEM_B_DQ<25> MEM_B_DQ<24> MEM_B_DQ<23> MEM_B_DQ<22> MEM_B_DQ<21> MEM_B_DQ<20> MEM_B_DQ<19> MEM_B_DQ<18> MEM_B_DQ<17> MEM_B_DQ<16> MEM_B_DQ<15> MEM_B_DQ<14> MEM_B_DQ<13> MEM_B_DQ<12> MEM_B_DQ<11> MEM_B_DQ<10> MEM_B_DQ<9> MEM_B_DQ<8> MEM_B_DQ<7> MEM_B_DQ<6> MEM_B_DQ<5> MEM_B_DQ<4> MEM_B_DQ<3> MEM_B_DQ<2> MEM_B_DQ<1> MEM_B_DQ<0>
MEM_B_DM<7> MEM_B_DM<6> MEM_B_DM<5> MEM_B_DM<4> MEM_B_DM<3> MEM_B_DM<2> MEM_B_DM<1> MEM_B_DM<0>
AT4 AT3 AV2 AV3 AR4 AR3 AU2 AU3 AY4 AY3 BB3 BC3 AW4 AW3 BA3 BB2 BB5 BA5 BA8 BC8 BB4 BC4 BA7 AY8
BA9 BB10 BB12 AW12
BB8
BB9 AY12 BA12 BC32 AW32 BA35 AY36 BA32 BB32 BA34 AY35 BC36 AW36 BA39 AY40 BA36 BB36 BA38 AY39 BB40 AW40 AV42 AV41 BA40 BC40 AW42 AW41 AT40 AT41 AP41 AN40 AU40 AU41 AR41 AP42
AT5
BA2
AY7 BA11 BB34 BB38 AY43 AR42
OMIT
U1400
MCP79-TOPO-B
BGA
(3 OF 11)
MDQ1_63 MDQ1_62 MDQ1_61 MDQ1_60 MDQ1_59 MDQ1_58 MDQ1_57 MDQ1_56 MDQ1_55 MDQ1_54 MDQ1_53 MDQ1_52 MDQ1_51 MDQ1_50 MDQ1_49 MDQ1_48 MDQ1_47 MDQ1_46 MDQ1_45 MDQ1_44 MDQ1_43 MDQ1_42 MDQ1_41 MDQ1_40 MDQ1_39 MDQ1_38 MDQ1_37 MDQ1_36 MDQ1_35 MDQ1_34 MDQ1_33 MDQ1_32 MDQ1_31 MDQ1_30 MDQ1_29 MDQ1_28 MDQ1_27 MDQ1_26 MDQ1_25 MDQ1_24 MDQ1_23 MDQ1_22 MDQ1_21 MDQ1_20 MDQ1_19 MDQ1_18 MDQ1_17 MDQ1_16 MDQ1_15 MDQ1_14 MDQ1_13 MDQ1_12 MDQ1_11 MDQ1_10 MDQ1_9 MDQ1_8 MDQ1_7 MDQ1_6 MDQ1_5 MDQ1_4 MDQ1_3 MDQ1_2 MDQ1_1 MDQ1_0
MDQM1_7 MDQM1_6 MDQM1_5 MDQM1_4 MDQM1_3 MDQM1_2 MDQM1_1 MDQM1_0
CONTROL
MRAS1# MCAS1#
MWE1#
MBA1_2 MBA1_1 MBA1_0
MA1_14 MA1_13 MA1_12 MA1_11 MA1_10
MA1_9 MA1_8 MA1_7 MA1_6 MA1_5 MA1_4 MA1_3 MA1_2 MA1_1 MA1_0
AT2 AT1 AY2 AY1 BB6 BA6 BA10 AY11 BB33 BA33 BB37 BA37 BA43 AY42 AT42 AT43
AW16 BA15 BA16
BB29 BB18 BB17
BA29 BA14 AW28 BC28 BA17 BB28 AY28 BA28 AY27 BA27 BA26 BB26 BA25 BB25 BA18
MDQS1_7_P MDQS1_7_N MDQS1_6_P MDQS1_6_N MDQS1_5_P MDQS1_5_N MDQS1_4_P MDQS1_4_N MDQS1_3_P MDQS1_3_N MDQS1_2_P MDQS1_2_N MDQS1_1_P MDQS1_1_N MDQS1_0_P MDQS1_0_N
MEMORY PARTITION 1
MEM_B_DQS_P<7> MEM_B_DQS_N<7> MEM_B_DQS_P<6> MEM_B_DQS_N<6> MEM_B_DQS_P<5> MEM_B_DQS_N<5> MEM_B_DQS_P<4> MEM_B_DQS_N<4> MEM_B_DQS_P<3> MEM_B_DQS_N<3> MEM_B_DQS_P<2> MEM_B_DQS_N<2> MEM_B_DQS_P<1> MEM_B_DQS_N<1> MEM_B_DQS_P<0> MEM_B_DQS_N<0>
MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L
MEM_B_BA<2> MEM_B_BA<1> MEM_B_BA<0>
MEM_B_A<14> MEM_B_A<13> MEM_B_A<12> MEM_B_A<11> MEM_B_A<10> MEM_B_A<9> MEM_B_A<8> MEM_B_A<7> MEM_B_A<6> MEM_B_A<5> MEM_B_A<4> MEM_B_A<3> MEM_B_A<2> MEM_B_A<1> MEM_B_A<0>
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
BI
27 76
OUT
27 76
OUT
27 76
OUT
27 76
OUT
27 76
OUT
27 76
OUT
27 76
OUT
27 76
OUT
27 76
OUT
27 76
OUT
27 76
OUT
27 76
OUT
27 76
OUT
27 76
OUT
27 76
OUT
27 76
OUT
27 76
OUT
27 76
OUT
27 76
OUT
27 76
OUT
27 76
OUT
MEMORY
1A
MCLK1A_2_P MCLK1A_2_N
MCLK1A_1_P MCLK1A_1_N
MCLK1A_0_P MCLK1A_0_N
MCS1A_1# MCS1A_0#
MODT1A_1 MODT1A_0
MCKE1A_1 MCKE1A_0
BA42 BB42
BB22 BA22
BA19 AY19
BB14 BB16
BB13 AY15
AY31 BB30
TP_MEM_B_CLK2P TP_MEM_B_CLK2N
MEM_B_CLK_P<1> MEM_B_CLK_N<1>
MEM_B_CLK_P<0> MEM_B_CLK_N<0>
MEM_B_CS_L<1> MEM_B_CS_L<0>
MEM_B_ODT<1> MEM_B_ODT<0>
MEM_B_CKE<1> MEM_B_CKE<0>
27 76
OUT
27 76
OUT
27 76
OUT
27 76
OUT
27 76
OUT
27 76
OUT
27 76
OUT
27 76
OUT
27 76
OUT
27 76
OUT
D
C
B
MCP Memory Interface
A
SYNC_MASTER=T18_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
D
APPLE INC.
8
7 6
5
4
3
2
SCALE
NONE
SYNC_DATE=02/05/2009
051-7903
SHT
OF
14
1
A
REV.
A
83
8 7
6
D
PP1V5_S0
10 11 15 22 37 66 67 68
6 7 82
R1611
C
R1610
40.2
1/16W MF-LF
1
40.2
1% 1/16W MF-LF
402
2
1
1%
402
2
B
A
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
8
7 6
TP_MEM_A_CLK5P TP_MEM_A_CLK5N
NC_MEM_A_CLK4P
6
TP_MEM_A_CLK4N NC_MEM_A_CLK3P
6
NC_MEM_A_CLK3N
6
TP_MEM_A_CS_L<2> NC_MEM_A_CS_L<3>
6
NC_MEM_A_ODT<2>
6
NC_MEM_A_ODT<3>
6
NC_MEM_A_CKE<2>
6
NC_MEM_A_CKE<3>
6
PP1V05_S0_MCP_PLL_CORE
22
87 mA (A01)
MCP_MEM_COMP_VDD
76
MCP_MEM_COMP_GND
76
17 mA 12 mA 19 mA 39 mA
5
4
3
OMIT
U1400
MCP79-TOPO-B
BGA
AU33
MCLK0B_2_P
AU34
MCLK0B_2_N
BB24
MCLK0B_1_P
BC24
MCLK0B_1_N
BA21
MCLK0B_0_P
BB21
MCLK0B_0_N
AU17
MCS0B_0#
AR15
MCS0B_1#
AN17
MODT0B_0
AN15
MODT0B_1
AV23
MCKE0B_0
AN25
MCKE0B_1
T27
+V_PLL_XREF_XS
U28
+V_PLL_DP
U27
+V_PLL_CORE
T28
+V_VPLL
AN41
MEM_COMP_VDD
AM41
MEM_COMP_GND
AA22
GND1
AP12
GND2
G30
GND3
P10
GND4
T10
GND5
T6
GND6
V10
GND7
V34
GND8
W5
GND9
AA39
GND10
AB22
GND11
AB7
GND12
AD22
GND13
AE20
GND14
AF24
GND15
AG24
GND16
AH35
GND17
AK7
GND18
AM28
GND19
AT25
GND20
AP30
GND21
AR36
GND22
AU10
GND23
F28
GND24
BC21
GND25
AY9
GND26
BC9
GND27
D34
GND28
F24
GND29
G32
GND30
H31
GND31
K7
GND32
M38
GND33
M5
GND34
M6
GND35
M7
GND36
M9
GND37
N39
GND38
N8
GND39
P33
GND40
P34
GND41
P37
GND42
P4
GND43
P40
GND44
P7
GND45
R36
GND46
R40
GND47
R43
GND48
R5
GND49
T18
GND50
T20
GND51
AK11
GND52
T24
GND53
T26
GND54
5
(4 OF 11)
MCLK1B_2_P MCLK1B_2_N
MCLK1B_1_P MCLK1B_1_N
MCLK1B_0_P MCLK1B_0_N
MEMORY CONTROL 0B
MEMORY CONTROL 1B
+VDD_MEM1 +VDD_MEM2 +VDD_MEM3 +VDD_MEM4 +VDD_MEM5 +VDD_MEM6 +VDD_MEM7 +VDD_MEM8
+VDD_MEM9 +VDD_MEM10 +VDD_MEM11 +VDD_MEM12 +VDD_MEM13 +VDD_MEM14 +VDD_MEM15 +VDD_MEM16 +VDD_MEM17 +VDD_MEM18 +VDD_MEM19 +VDD_MEM20 +VDD_MEM21 +VDD_MEM22 +VDD_MEM23 +VDD_MEM24 +VDD_MEM25 +VDD_MEM26 +VDD_MEM27 +VDD_MEM28 +VDD_MEM29 +VDD_MEM30 +VDD_MEM31 +VDD_MEM32 +VDD_MEM33 +VDD_MEM34 +VDD_MEM35 +VDD_MEM36 +VDD_MEM37 +VDD_MEM38 +VDD_MEM39 +VDD_MEM40 +VDD_MEM41 +VDD_MEM42 +VDD_MEM43 +VDD_MEM44 +VDD_MEM45
MCS1B_0# MCS1B_1#
MODT1B_0 MODT1B_1
MCKE1B_0 MCKE1B_1
MRESET0#
GND55 GND56 GND57 GND58 GND59 GND60 GND61 GND62 GND63 GND64
BA41 BB41
AY23 BA23
BA20 AY20
BC16 BA13
AY16 BC13
BA30 BA31
AY32
AM17 AM19 AM21 AM23 AM25 AM27 AM29 AN16 BC29 AN20 AN24 AT17 AP16 AN22 AP20 AP24 AV16 AR16 AR20 AR24 AW15 AP22 AP18 AU16 AN18 AU24 AT21 AY29 AV24 AU20 AU22 AW27 BC17 AV20 AY17 AY18 AM15 AU18 AY25 AY26 AW19 AW24 BC25 AL30 AM31
T33 T34 T35 T37 T38 T7 T9 U18 U20 U22
TP or NC for DDR2.
PP1V5_S0
4
TP_MEM_B_CLK5P NC_MEM_B_CLK5N
NC_MEM_B_CLK4P NC_MEM_B_CLK4N
NC_MEM_B_CLK3P TP_MEM_B_CLK3N
TP_MEM_B_CS_L<2> TP_MEM_B_CS_L<3>
NC_MEM_B_ODT<2> TP_MEM_B_ODT<3>
NC_MEM_B_CKE<2> TP_MEM_B_CKE<3>
MCP_MEM_RESET_L
4771 mA (A01, DDR3)
6
6
6
6
6
6
28
OUT
6 7
10 11 15 22 37 66 67 68 82
D
C
B
MCP Memory Misc
SYNC_MASTER=T18_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
D
APPLE INC.
3
2
SCALE
NONE
SYNC_DATE=02/05/2009
051-7903
SHT
OF
15 83
1
A
REV.
A
8 7
6
D
C
29
29
35
35
58
30
29
29 77
29 77
34 77
B
34 77
77
77
A
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
8
7 6
NC_PEG_D2RP<0>
8
IN
NC_PEG_D2RN<0>
8
IN
NC_PEG_D2RP<1>
8
IN
NC_PEG_D2RN<1>
8
IN
NC_PEG_D2RP<2>
8
IN
NC_PEG_D2RN<2>
8
IN
NC_PEG_D2RP<3>
8
IN
NC_PEG_D2RN<3>
8
IN
NC_PEG_D2RP<4>
8
IN
NC_PEG_D2RN<4>
8
IN
NC_PEG_D2RP<5>
8
IN
NC_PEG_D2RN<5>
8
IN
NC_PEG_D2RP<6>
8
IN
NC_PEG_D2RN<6>
8
IN
NC_PEG_D2RP<7>
8
IN
NC_PEG_D2RN<7>
8
IN
NC_PEG_D2RP<8>
8
IN
NC_PEG_D2RN<8>
8
IN
NC_PEG_D2RP<9>
8
IN
NC_PEG_D2RN<9>
8
IN
NC_PEG_D2RP<10>
8
IN
NC_PEG_D2RN<10>
8
IN
NC_PEG_D2RP<11>
8
IN
NC_PEG_D2RN<11>
8
IN
NC_PEG_D2RP<12>
8
IN
NC_PEG_D2RN<12>
8
IN
NC_PEG_D2RP<13>
8
IN
NC_PEG_D2RN<13>
8
IN
NC_PEG_D2RP<14>
8
IN
NC_PEG_D2RN<14>
8
IN
NC_PEG_D2RP<15>
8
IN
NC_PEG_D2RN<15>
8
IN
TP_PEG_PRSNT_L
8
IN
MINI_CLKREQ_L
IN
PCIE_MINI_PRSNT_L
IN
FW_CLKREQ_L
IN
PCIE_FW_PRSNT_L
8
IN
TP_EXCARD_CLKREQ_L
8
IN
TP_PCIE_EXCARD_PRSNT_L
8
IN
TP_PE4_CLKREQ_L NC_PE4_PRSNT_L
6
AUD_IP_PERIPHERAL_DET
IN
TP_GMUX_JTAG_TCK_L
8
OUT
CARDREADER_RESET
OUT
TP_GMUX_JTAG_TDO
8
IN
PCIE_WAKE_L
6
IN
PCIE_MINI_D2R_P
6
IN
PCIE_MINI_D2R_N
6
IN
PCIE_FW_D2R_P
IN
PCIE_FW_D2R_N
IN
NC_PCIE_EXCARD_D2RP
8
IN
NC_PCIE_EXCARD_D2RN
8
IN
TP_PCIE_PE4_D2RP NC_PCIE_PE4_D2RN
6
GND
57 mA (A01, DVDD0 & 1)
PP1V05_S0
6 7 9
10 11 12 13 17 19 21 22
23 35 61 65 66 67
PP1V05_S0_MCP_PLL_PEX
22
84 mA (A01)
MCP_PEX_CLK_COMP
77
NO STUFF
1
R1710
2.37K
1% 1/16W MF-LF 402
2
PLACEMENT_NOTE=Place within 12.7mm of U1400
5
4
OMIT
U1400
MCP79-TOPO-B
BGA
F7
PE0_RX0_P
E7
PE0_RX0_N
D7
PE0_RX1_P
C7
PE0_RX1_N
E6
PE0_RX2_P
F6
PE0_RX2_N
E5
PE0_RX3_P
F5
PE0_RX3_N
E4
PE0_RX4_P
E3
PE0_RX4_N
C3
PE0_RX5_P
D3
PE0_RX5_N
G5
PE0_RX6_P
H5
PE0_RX6_N
J7
PE0_RX7_P
J6
PE0_RX7_N
J5
PE0_RX8_P
J4
PE0_RX8_N
L11
PE0_RX9_P
L10
PE0_RX9_N
L9
PE0_RX10_P
L8
PE0_RX10_N
L7
PE0_RX11_P
L6
PE0_RX11_N
N11
PE0_RX12_P
N10
PE0_RX12_N
N9
PE0_RX13_P
P9
PE0_RX13_N
N7
PE0_RX14_P
N6
PE0_RX14_N
N5
PE0_RX15_P
N4
PE0_RX15_N
Int PU
C9 D11
PE0_PRSNT_16#
Int PU
D5
PEB_CLKREQ#/GPIO_49
D9
PEB_PRSNT#
Int PU
E8
PEC_CLKREQ#/GPIO_50
C10
PEC_PRSNT#
Int PU
M15
PED_CLKREQ#/GPIO_51
B10
PED_PRSNT#
Int PU
L16
PEE_CLKREQ#/GPIO_16
L18
PEE_PRSNT#/GPIO_46
Int PU
M16
PEF_CLKREQ#/GPIO_17
M18
PEF_PRSNT#/GPIO_47
Int PU
M17
PEG_CLKREQ#/GPIO_18
M19
PEG_PRSNT#/GPIO_48
F17
PE_WAKE#
K9
PE1_RX0_P
J9
PE1_RX0_N
H9
PE1_RX1_P
G9
PE1_RX1_N
F9
PE1_RX2_P
E9
PE1_RX2_N
H7
PE1_RX3_P
G7
PE1_RX3_N
T17
+DVDD0_PEX1
W19
+DVDD0_PEX2
U17
+DVDD0_PEX3
V19
+DVDD0_PEX4
W16
+DVDD0_PEX5
W17
+DVDD0_PEX6
W18
+DVDD0_PEX7
U16
+DVDD0_PEX8
T19
+DVDD1_PEX1
U19
+DVDD1_PEX2
T16
+V_PLL_PEX
A11
PEX_CLK_COMP
If PE0 interface is not used, ground DVDD0_PEX and AVDD0_PEX. If PE1 interface is not used, ground DVDD1_PEX and AVDD1_PEX.
5
(5 OF 11)
Int PU
Int PU
Int PU
Int PU
Int PU
Int PU
Int PU (S5)
PE0_TX0_P
PE0_TX0_N
PE0_TX1_P
PE0_TX1_N
PE0_TX2_P
PE0_TX2_N
PE0_TX3_P
PE0_TX3_N
PE0_TX4_P
PE0_TX4_N
PE0_TX5_P
PE0_TX5_N
PE0_TX6_P
PE0_TX6_N
PE0_TX7_P
PE0_TX7_N
PE0_TX8_P
PE0_TX8_N
PE0_TX9_P
PE0_TX9_N PE0_TX10_P PE0_TX10_N PE0_TX11_P PE0_TX11_N PE0_TX12_P PE0_TX12_N PE0_TX13_P PE0_TX13_N PE0_TX14_P PE0_TX14_N PE0_TX15_P PE0_TX15_N
PCI EXPRESS
PE0_REFCLK_P PE0_REFCLK_N
PE1_REFCLK_P PE1_REFCLK_N
PE2_REFCLK_P PE2_REFCLK_N
PE3_REFCLK_P PE3_REFCLK_N
PE4_REFCLK_P PE4_REFCLK_N
PE5_REFCLK_P PE5_REFCLK_N
PE6_REFCLK_P PE6_REFCLK_N
PEX_RST0#
PE1_TX0_P
PE1_TX0_N
PE1_TX1_P
PE1_TX1_N
PE1_TX2_P
PE1_TX2_N
PE1_TX3_P
PE1_TX3_N
+AVDD0_PEX1 +AVDD0_PEX2 +AVDD0_PEX3 +AVDD0_PEX4 +AVDD0_PEX5 +AVDD0_PEX6 +AVDD0_PEX7 +AVDD0_PEX8
+AVDD0_PEX9 +AVDD0_PEX10 +AVDD0_PEX11 +AVDD0_PEX12 +AVDD0_PEX13
+AVDD1_PEX1
+AVDD1_PEX2
+AVDD1_PEX3
C5 D4 C4 B4 A4 A3 B3 B2 C1 D1 D2 E1 E2 F2 F3 F4 G3 H4 H3 H2 H1 J1 J2 J3 K2 K3 L4 L3 M4 M3 M2 M1
E11
G11 F11
J11 J10
G13 F13
J13 H13
L14 K14
N14 M14
K11
D8 C8
B8 A8
A7 B7
B6 C6
Y12 AA12 AB12 M12 P12 R12 N12 T12 U12 AC12 AD12 V12 W12
M13 N13 P13
NC_PEG_R2DCP<0> NC_PEG_R2DCN<0> NC_PEG_R2DCP<1> NC_PEG_R2DCN<1> NC_PEG_R2DCP<2> NC_PEG_R2DCN<2> NC_PEG_R2DCP<3> NC_PEG_R2DCN<3> NC_PEG_R2DCP<4> NC_PEG_R2DCN<4> NC_PEG_R2DCP<5> NC_PEG_R2DCN<5> NC_PEG_R2DCP<6> NC_PEG_R2DCN<6> NC_PEG_R2DCP<7> NC_PEG_R2DCN<7> NC_PEG_R2DCP<8> NC_PEG_R2DCN<8> NC_PEG_R2DCP<9> NC_PEG_R2DCN<9> NC_PEG_R2DCP<10> NC_PEG_R2DCN<10> NC_PEG_R2DCP<11> NC_PEG_R2DCN<11> NC_PEG_R2DCP<12> NC_PEG_R2DCN<12> NC_PEG_R2DCP<13> NC_PEG_R2DCN<13> NC_PEG_R2DCP<14> NC_PEG_R2DCN<14> NC_PEG_R2DCP<15> NC_PEG_R2DCN<15>
NC_PEG_CLK100MP NC_PEG_CLK100MN
PCIE_CLK100M_MINI_P PCIE_CLK100M_MINI_N
PCIE_CLK100M_FW_P PCIE_CLK100M_FW_N
NC_PCIE_CLK100M_EXCARDP NC_PCIE_CLK100M_EXCARDN
NC_PCIE_CLK100M_PE4P NC_PCIE_CLK100M_PE4N
NC_PCIE_CLK100M_PE5P NC_PCIE_CLK100M_PE5N
NC_PCIE_CLK100M_PE6P TP_PCIE_CLK100M_PE6N
PCIE_RESET_L
PCIE_MINI_R2D_C_P PCIE_MINI_R2D_C_N
PCIE_FW_R2D_C_P PCIE_FW_R2D_C_N
NC_PCIE_EXCARD_R2DCP NC_PCIE_EXCARD_R2DCN
TP_PCIE_PE4_R2D_CP NC_PCIE_PE4_R2D_CN
GND
206 mA (A01, AVDD0 & 1)
Minimum 1.025V for Gen2 supportMinimum 1.025V for Gen2 support
PP1V05_S0_MCP_PEX_AVDD
4
3
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
77
8
OUT
8
77
OUT
29 77
OUT
29 77
OUT
34 77
OUT
34 77
OUT
8
77
OUT
8
77
OUT
6
6
6
6
6
24 35
OUT
29 77
OUT
29 77
OUT
34 77
OUT
34 77
OUT
8
77
OUT
8
77
OUT
6
7
22
D
C
B
MCP PCIe Interfaces
SYNC_MASTER=T18_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
D
APPLE INC.
3
2
SCALE
NONE
SYNC_DATE=02/05/2009
051-7903
SHT
OF
16 83
1
A
REV.
A
8 7
6
D
31 79
IN
31 79
IN
31 79
IN
31 79
IN
31 79
IN
31 79
IN
8
17
IN
8
17
6 7
17 22 31 32
PP3V3_ENET
R1810
49.9
1/16W MF-LF
R1811
49.9
1/16W MF-LF
1
1%
402
2
1
1%
402
2
IN
8
17
IN
6
22
79
79
23
23
C
23 77
OUT
23 77
OUT
PP3V3_S5
6 7
19 21 22 24 28 32 35 36
42 52 62 66 67 68 69 71 82
R1820
47K
1/16W MF-LF
42
BI
1
5%
402
2
Interface Mode MCP Signal =MCP_HDMI_TXC_P/N
=MCP_HDMI_TXD_P/N<0> =MCP_HDMI_TXD_P/N<1> =MCP_HDMI_TXD_P/N<2> =MCP_HDMI_DDC_CLK =MCP_HDMI_DDC_DATA
B
=MCP_HDMI_HPD DP_IG_AUX_CH_P/N
NOTE: 1M pull-down required on DP_IG_CA_DET if DP not used. NOTE: 20K pull-down required on DP_HPD_DET. NOTE: 1K pull-down required on DP_IG_AUX_CH_N if DP is used.
NOTE: HDMI port requires level-shifting. IFP interface can be used to provide HDMI or dual-channel TMDS without level-shifters.
TMDS/HDMI TMDS_IG_TXC_P/N
TMDS_IG_TXD_P/N<0> TMDS_IG_TXD_P/N<1> TMDS_IG_TXD_P/N<2> TMDS_IG_DDC_CLK TMDS_IG_DDC_DATA TMDS_IG_HPD TP_DP_IG_AUX_CHP/N
LVDS: Power +VDD_IFPx at 1.8V Dual-channel TMDS: Power +VDD_IFPx at 3.3V
DisplayPort DP_IG_ML_P/N<3>
DP_IG_ML_P/N<2> DP_IG_ML_P/N<1> DP_IG_ML_P/N<0> DP_IG_DDC_CLK DP_IG_DDC_DATA DP_IG_HPD DP_IG_AUX_CH_P/N
A
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
8
7 6
23
IN
23
OUT
70
IN
8
72 73 74
OUT
8
73
OUT
8
69
OUT
70
OUT
70
OUT
70
OUT
70
OUT
70
OUT
70
OUT
70 71 82
OUT
70 71 82
OUT
70 77
OUT
70 77
OUT
8
IN
70 71
IN
6 7
23 53 66
23
6 7 9
10 11 12 13 16 19 21 22
23 35 61 65 66 67
23 77
OUT
23 77
OUT
GPIOs 57-59 (if LCD panel is used): In MCP79 these pins have undocumented internal
pull-ups (~10K to 3.3V S0). To ensure pins are low by default, pull-downs (1K or stronger) must be used.
=DVI_HPD_GMUX_INT: Alias to DVI_HPD for systems using IFP for DVI.
Alias to GMUX_INT for systems with GMUX. Alias to HPLUG_DET2 for other systems. Pull-down (20k) required in all cases.
ENET_RXD<0> ENET_RXD<1> ENET_RXD<2> ENET_RXD<3>
ENET_CLK125M_RXCLK ENET_RX_CTRL
MCP_MII_PD MCP_MII_PD MCP_MII_PD
NC_ENET_INTR_L PP1V05_ENET_MCP_PLL_MAC
5 mA (A01)
MCP_MII_COMP_VDD MCP_MII_COMP_GND
NC_MCP_RGB_DAC_RSET NC_MCP_RGB_DAC_VREF
NC_MCP_TV_DAC_RSET NC_MCP_TV_DAC_VREF
NC_MCP_CLK27M_XTALIN NC_MCP_CLK27M_XTALOUT
LPCPLUS_GPIO DP_IG_CA_DET
LCD_BKLT_PWM LVDS_BKL_ON LCD_PWR_EN
=MCP_HDMI_TXC_P =MCP_HDMI_TXC_N
=MCP_HDMI_TXD_P<0> =MCP_HDMI_TXD_N<0> =MCP_HDMI_TXD_P<1> =MCP_HDMI_TXD_N<1> DP_ML_P<0> DP_ML_N<0>
DP_IG_AUX_CH_P DP_IG_AUX_CH_N
MCP_HPLUG_DET2 DP_HPD
PP1V8_S0
190 mA (A01, 1.8V)
PP3V3_S0_MCP_VPLL
16 mA (A01)
PP1V05_S0
95 mA (A01)
MCP_HDMI_RSET MCP_HDMI_VPROBE
(See below)
(See below)
8 mA 8 mA
5
C23
RGMII_RXD0
B23
RGMII_RXD1
E24
RGMII_RXD2
A24
RGMII_RXD3
A23
RGMII_RXC/MII_RXCLK
C22
RGMII_RXCTL/MII_RXDV
F23
MII_RXER/GPIO_36
B26
MII_COL/GPIO_20/MSMB_DATA
B22
MII_CRS/GPIO_21/MSMB_CLK
J22
RGMII_INTR/GPIO_35
T23
+V_DUAL_MACPLL
C27
MII_COMP_VDD
B27
MII_COMP_GND
C39
RGB_DAC_RSET
B38
RGB_DAC_VREF
E36
TV_DAC_RSET
A35
TV_DAC_VREF
C38
XTALIN_TV
D38
XTALOUT_TV
E16
GPIO_6/FERR*/IGPU_GPIO_6
B15
GPIO_7/NFERR*/IGPU_GPIO_7
G39
LCD_BKL_CTL/GPIO_57
E37
LCD_BKL_ON/GPIO_59
F40
LCD_PANEL_PWR/GPIO_58
D35
HDMI_TXC_P/ML0_LANE3_P
E35
HDMI_TXC_N/ML0_LANE3_N
G35
HDMI_TXD0_P/ML0_LANE2_P
F35
HDMI_TXD0_N/ML0_LANE2_N
F33
HDMI_TXD1_P/ML0_LANE1_P
G33
HDMI_TXD1_N/ML0_LANE1_N
J33
HDMI_TXD2_P/ML0_LANE0_P
H33
HDMI_TXD2_N/ML0_LANE0_N
D43
DP_AUX_CH0_P
C43
DP_AUX_CH0_N
C31
HPLUG_DET2/GPIO_22
F31
HPLUG_DET3
M27
+VDD_IFPA
M26
+VDD_IFPB
M28
+V_PLL_IFPAB
M29
+V_PLL_HDMI
T25
+VDD_HDMI
J31
HDMI_RSET
J30
HDMI_VPROBE
5
OMIT
U1400
MCP79-TOPO-B
BGA
(6 OF 11)
LAN
DACS
TV / Component C / Pr Y / Y Comp / Pb
4
MII_VREF
DDC_CLK0
DDC_CLK3
J24 K24
U23 V23
E28
B24 C24 C25 D25
D24 C26
D21 C21
G23
E23
J23
J32 K32
B31 A31
B39 A39 B40
A40 A41
A36 B36 C36
D36 C37
B35 C35
B32 A32 D32 C32 D33 C33 B34 C34
L31 K31
J29 H29 L29 K29 L30 K30 N30 M30
C30 B30
D31 E31
E32 G31
+3.3V_DUAL_RMGT1 +3.3V_DUAL_RMGT2
+V_DUAL_RMGT1 +V_DUAL_RMGT2
RGMII_TXD0 RGMII_TXD1 RGMII_TXD2 RGMII_TXD3
RGMII_TXC/MII_TXCLK
RGMII_TXCTL/MII_TXEN
RGMII_MDC
RGMII_MDIO
RGMII_PWRDWN/GPIO_37
BUF_25MHZ
MII_RESET#
+V_RGB_DAC
+V_TV_DAC
DDC_DATA0
RGB_DAC_RED
RGB_DAC_GREEN
RGB_DAC_BLUE
RGB_DAC_HSYNC RGB_DAC_VSYNC
RGB ONLY
TV_DAC_RED
TV_DAC_GREEN
TV_DAC_BLUE
TV_DAC_HSYNC/GPIO_44 TV_DAC_VSYNC/GPIO_45
IFPA_TXC_P IFPA_TXC_N
IFPA_TXD0_P IFPA_TXD0_N IFPA_TXD1_P IFPA_TXD1_N IFPA_TXD2_P IFPA_TXD2_N IFPA_TXD3_P IFPA_TXD3_N
IFPB_TXC_P IFPB_TXC_N
IFPB_TXD4_P IFPB_TXD4_N IFPB_TXD5_P IFPB_TXD5_N IFPB_TXD6_P IFPB_TXD6_N IFPB_TXD7_P
FLAT PANEL
IFPB_TXD7_N
DDC_CLK2/GPIO_23
DDC_DATA2/GPIO_24
DDC_DATA3
IFPAB_RSET
IFPAB_VPROBE
4
PP3V3_ENET
PP1V05_ENET
MCP_MII_VREF ENET_TXD<0>
ENET_TXD<1> ENET_TXD<2> ENET_TXD<3>
ENET_CLK125M_TXCLK ENET_TX_CTRL
ENET_MDC ENET_MDIO
NC_ENET_PWRDWN_L
MCP_CLK25M_BUF0_R
ENET_RESET_L
PP3V3_S0_MCP_DAC 103 mA 103 mA
MCP_DDC_CLK0 MCP_DDC_DATA0
NC_MCP_RGB_RED NC_MCP_RGB_GREEN NC_MCP_RGB_BLUE
NC_MCP_RGB_HSYNC NC_MCP_RGB_VSYNC
NC_CRT_IG_R_C_PR NC_CRT_IG_G_Y_Y NC_CRT_IG_B_COMP_PB
NC_CRT_IG_HSYNC NC_CRT_IG_VSYNC
LVDS_CONN_A_CLK_P LVDS_CONN_A_CLK_N
LVDS_IG_A_DATA_P<0> LVDS_IG_A_DATA_N<0> LVDS_IG_A_DATA_P<1> LVDS_IG_A_DATA_N<1> LVDS_IG_A_DATA_P<2> LVDS_IG_A_DATA_N<2> NC_LVDS_IG_A_DATAP<3> NC_LVDS_IG_A_DATAN<3>
LVDS_CONN_B_CLK_P LVDS_CONN_B_CLK_N
LVDS_IG_B_DATA_P<0> LVDS_IG_B_DATA_N<0> LVDS_IG_B_DATA_P<1> LVDS_IG_B_DATA_N<1> LVDS_IG_B_DATA_P<2> LVDS_IG_B_DATA_N<2> NC_LVDS_IG_B_DATAP<3> NC_LVDS_IG_B_DATAN<3>
LVDS_DDC_CLK LVDS_DDC_DATA
DP_IG_DDC_CLK DP_IG_DDC_DATA
MCP_IFPAB_RSET MCP_IFPAB_VPROBE
1
R1850
10K
5% 1/16W MF-LF 402
2
206 mA (A01)
3
6 7
17 22 31 32
83 mA (A01)
6 7
131 mA (A01)
22 31 32
22
IN
31 79
OUT
31 79
OUT
31 79
OUT
31 79
OUT
31 79
OUT
31 79
OUT
31 79
OUT
BI
6
32 79
OUT
31 79
OUT
23
23
23
23
23
23
23 77
OUT
23 77
OUT
23 77
OUT
23 77
OUT
23 77
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
6 8
OUT
BI
70
OUT
BI
23 77
OUT
23 77
OUT
3
Network Interface Select
Interface
RGMII
NOTE: All Apple products set strap to MII, RGMII products will enable
31 79
1
R1860
100K
5% 1/16W MF-LF
402
2
69 77
69 77
77
77
77
77
77
77
77
77
WF: IFP is capable of LVDS (1.8V) or TMDS (3.3V), need aliases
69 77
69 77
77
77
77
77
77
77
77
77
69
6 8
69
70
feature via software. This avoids a leakage issue since MCP79 requires a S5 pull-up.
PP3V3_S0
1
R1861
100K
5% 1/16W MF-LF 402
2
RGB DAC Disable: Okay to float all RGB_DAC signals.
DDC_CLK0/DDC_DATA0 pull-ups still required.
TV DAC Disable: Okay to float all TV_DAC signals.
Okay to float XTALIN_TV and XTALOUT_TV. DDC_CLK0/DDC_DATA0 pull-ups still required.
MCP Ethernet & Graphics
SYNC_MASTER=T18_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
APPLE INC.
2
MII
61 66 67 68 69 71 72 82 6 7
12 18 20 21 22 23 26 27 35
37 41 43 45 46 47 49 53 57 58
DRAWING NUMBER
SIZE
D
SCALE
NONE
ENET_TXD<0>
1 0
SYNC_DATE=02/05/2009
051-7903
SHT
OF
17 83
1
D
C
B
A
REV.
A
8 7
6
5
4
3
OMIT
U1400
MCP79-TOPO-B
BGA
Int PU
(7 OF 11)
PCI_GNT2#/GPIO_41/RS232_DTR# PCI_GNT3#/GPIO_39/RS232_RTS#
PCI_GNT4#/GPIO_53/RS232_SOUT#
PCI_PERR#/GPIO_43/RS232_DCD#
LPC_PWRDWN#/GPIO_54/EXT_NMI#
LPC PCIGND
PCI_GNT0#
PCI_GNT1#/FANCTL2
PCI_CBE0# PCI_CBE1# PCI_CBE2# PCI_CBE3#
PCI_DEVSEL#
PCI_FRAME#
PCI_IRDY#
PCI_PAR
PCI_SERR# PCI_STOP#
PCI_PME#/GPIO_30
Int PU (S5)
PCI_RESET0# PCI_RESET1#
PCI_CLK0 PCI_CLK1 PCI_CLK2
PCI_CLKIN
LPC_FRAME#
LPC_RESET0#
LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3
LPC_CLK0
GND98
GND99 GND100 GND101 GND102 GND103 GND104 GND105 GND106 GND107 GND108 GND109 GND110 GND111 GND112 GND113 GND114 GND115 GND116 GND117 GND118 GND119 GND120 GND121 GND122 GND123 GND124 GND125 GND126 GND127 GND128 GND129 GND130
R3 U10 R4 U11 P3
AA3 AA6 AA11 W10
AA9 Y4 AA10 Y1 AB9 AA7 Y2
T1
R10 R11
R6 R7 R8
R9
AD4 AE12
AE5
AD3 AD2 AD1 AD5
AE9
Y26 Y27 AB18 H34 AB20 AB21 AB23 AB24 AB25 AB26 AB27 AB28 AB34 AB37 AB4 AB40 AC22 AC36 AC40 AB33 AC5 AD16 AD17 AD18 AD19 AD20 AD24 AD25 AD26 AD27 AD28 AD33 AD34
NC_PCI_GNT0_L NC_PCI_GNT1_L TP_GMUX_JTAG_TMS TP_GMUX_JTAG_TDI MCP_RS232_SOUT_L
NC_PCI_C_BE_L<0> NC_PCI_C_BE_L<1> NC_PCI_C_BE_L<2> NC_PCI_C_BE_L<3>
NC_PCI_DEVSEL_L NC_PCI_FRAME_L NC_PCI_IRDY_L TP_PCI_PAR NC_PCI_PERR_L NC_PCI_SERR_L NC_PCI_STOP_L
PM_LATRIGGER_L
MEM_VTT_EN_R NC_PCI_RESET1_L
NC_PCI_CLK0 NC_PCI_CLK1 PCI_CLK33M_MCP_R
78
PCI_CLK33M_MCP
78
LPC_FRAME_R_L LPC_PWRDWN_L
6
6
8
OUT
8
OUT
18
OUT
6
6
6
6
6
6
6
6 6
6
6
12
OUT
24
OUT
6
6
6
1
R1910
22
5% 1/16W MF-LF 402
2
PLACEMENT_NOTE=Place close to pin R8
R1960
22
1 2
LPC_RESET_L
LPC_AD_R<0> LPC_AD_R<1> LPC_AD_R<2> LPC_AD_R<3>
R1950 R1951 R1952 R1953
22 22
1 2 1 2 1 2 1 2
LPC_CLK33M_SMC_R
1
R1961
10K
5% 1/16W MF-LF 402
2
Strap for Boot ROM Selection (See HDA_SDOUT)
1/16W MF-LF
5%
5%
1/16W MF-LF22402
5%
1/16W MF-LF22402
5%
1/16W MF-LF
5%
LPC_FRAME_L
402
LPC_AD<0> LPC_AD<1> LPC_AD<2>
402
LPC_AD<3>
402
MF-LF1/16W
40 42 78
OUT
40 42
OUT
24 78
OUT
40 42 78
BI
40 42 78
BI
40 42 78
BI
40 42 78
BI
OUT
PCI_REQ0_L
18 78
PCI_REQ1_L
18 78
FW_PWR_EN
18 35
OUT
AUD_IPHS_SWITCH_EN
8
58
OUT
MCP_RS232_SIN_L
18
IN
D
C
MCP_DEBUG<0>
12 78
BI
MCP_DEBUG<1>
12 78
BI
MCP_DEBUG<2>
12 78
BI
MCP_DEBUG<3>
12 78
BI
MCP_DEBUG<4>
12 78
BI
MCP_DEBUG<5>
12 78
BI
MCP_DEBUG<6>
12 78
BI
MCP_DEBUG<7>
12 78
BI
NC_PCI_AD<8>
6
NC_PCI_AD<9> NC_PCI_AD<10>
6
NC_PCI_AD<11>
6
NC_PCI_AD<12>
6
NC_PCI_AD<13>
6
NC_PCI_AD<14>
6
NC_PCI_AD<15>
6
NC_PCI_AD<16>
6
NC_PCI_AD<17>
6
NC_PCI_AD<18>
6
NC_PCI_AD<19>
6
NC_PCI_AD<20>
6
NC_PCI_AD<21>
6
NC_PCI_AD<22>
6
NC_PCI_AD<23>
6
NC_PCI_AD<24>
6
NC_PCI_AD<25>
6
NC_PCI_AD<26>
6
NC_PCI_AD<27>
6
NC_PCI_AD<28>
6
NC_PCI_AD<29>
6
NC_PCI_AD<30>
6
NC_PCI_AD<31>
6
NC_PCI_INTW_L
6
NC_PCI_INTX_L
6
TP_PCI_INTY_L NC_PCI_INTZ_L
6
NC_PCI_TRDY_L
6
PM_CLKRUN_L
40 42
IN
FW_PLUG_DET_L
8
35
IN
NC_LPC_DRQ0_L
6
LPC_SERIRQ
40 42 24 78
BI
B
A
T2
PCI_REQ0#
V9
PCI_REQ1#/FANRPM2
T3
PCI_REQ2#/GPIO_40/RS232_DSR#
U9
PCI_REQ3#/GPIO_38/RS232_CTS#
T4
PCI_REQ4#/GPIO_52/RS232_SIN#
AC3
PCI_AD0
AE10
PCI_AD1
AC4
PCI_AD2
AE11
PCI_AD3
AB3
PCI_AD4
AC6
PCI_AD5
AB2
PCI_AD6
AC7
PCI_AD7
AC8
PCI_AD8
AA2
PCI_AD9
AC9
PCI_AD10
AC10
PCI_AD11
AC11
PCI_AD12
AA1
PCI_AD13
AA5
PCI_AD14
Y5
PCI_AD15
W3
PCI_AD16
W6
PCI_AD17
W4
PCI_AD18
W7
PCI_AD19
V3
PCI_AD20
W8
PCI_AD21
V2
PCI_AD22
W9
PCI_AD23
U3
PCI_AD24
W11
PCI_AD25
U2
PCI_AD26
U5
PCI_AD27
U1
PCI_AD28
U6
PCI_AD29
T5
PCI_AD30
U7
PCI_AD31
P2
PCI_INTW#
N3
PCI_INTX#
N2
PCI_INTY#
N1
PCI_INTZ#
Y3
PCI_TRDY#
AD11
PCI_CLKRUN#/GPIO_42
AE2
LPC_DRQ1#/GPIO_19
AE1 AE6
U24 U26 U39
V16 V17 V18 V20 V22 V24 V26 V27 V28 V33 V37
V40
W20 W22 W24 W36 W40 W43 Y16 Y17 Y18 Y19 Y20 Y22 Y24 Y25
U4 U8
V4
V7
LPC_DRQ0# LPC_SERIRQ
GND65 GND66 GND67 GND68 GND69 GND70 GND71 GND72 GND73 GND74 GND75 GND76 GND77 GND78 GND79 GND80 GND81 GND82 GND83 GND84 GND85 GND86 GND87 GND88 GND89 GND90 GND91 GND92 GND93 GND94 GND95 GND96 GND97
Int PU Int PU
MCP_RS232_SOUT_L
18
PCI_REQ0_L
18 78
PCI_REQ1_L
18 78
FW_PWR_EN
18 35
MCP_RS232_SIN_L
18
R1989 R1990
R1991 R1992 R1994
MCP PCI & LPC
SYNC_MASTER=T18_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
APPLE INC.
8.2K
8.2K
8.2K
8.2K
8.2K
SIZE
D
SCALE
58 61 66 67 68 69 71 72 82
PP3V3_S0
6 7
12 17 20 21 22 23 26 27
35 37 41 43 45 46 47 49 53 57
1 2
1 2 1 2 1 2 1 2
DRAWING NUMBER
NONE
5%
5% 5% 5% 5%
MF-LF1/16W
MF-LF1/16W MF-LF1/16W
1/16W MF-LF
MF-LF1/16W
SYNC_DATE=02/05/2009
051-7903
SHT
OF
402
402 402 402 402
D
C
B
A
REV.
A
8318
8
7 6
5
4
3
2
1
8 7
6
37 77
OUT
37 77
OUT
37 77
IN
37 77
IN
D
37 77
OUT
37 77
OUT
37 77
IN
37 77
IN
6
6
6
6
6
C
22
84 mA (A01)
6 7 9
10 11 12 13 16 17 21 22
23 35 61 65 66 67
43 mA (A01, DVDD0 & 1)
Minimum 1.025V for Gen2 support
B
7
22
127 mA (A01, AVDD0 & 1)
Minimum 1.025V for Gen2 support
77
1
2
A
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
8
7 6
SATA_HDD_R2D_C_P SATA_HDD_R2D_C_N
SATA_HDD_D2R_N SATA_HDD_D2R_P
SATA_ODD_R2D_C_P SATA_ODD_R2D_C_N
SATA_ODD_D2R_N SATA_ODD_D2R_P
NC_SATA_C_R2D_CP NC_SATA_C_R2D_CN
TP_SATA_C_D2RN NC_SATA_C_D2RP
TP_SATA_D_R2D_CP TP_SATA_D_R2D_CN
NC_SATA_D_D2RN NC_SATA_D_D2RP
TP_SATA_E_R2D_CP TP_SATA_E_R2D_CN
TP_SATA_E_D2RN TP_SATA_E_D2RP
TP_SATA_F_R2D_CP TP_SATA_F_R2D_CN
TP_SATA_F_D2RN TP_SATA_F_D2RP
TP_MCP_SATALED_L
PP1V05_S0_MCP_PLL_SATA
PP1V05_S0
GND
PP1V05_S0_MCP_SATA_AVDD
GND
MCP_SATA_TERMP
R2010
2.49K
1% 1/16W MF-LF 402
If all SATA_Ax & Bx pins are not used, ground DVDD0_SATA and AVDD0_SATA. If all SATA_Cx pins are not used, ground DVDD1_SATA and AVDD1_SATA.
AJ11 AJ10
AE16
AF19 AG16 AG17 AG19
AH17 AH19
AJ12 AN11 AK12 AK13 AL12 AM11 AM12 AN12 AL13
AN14 AL14 AM13 AM14
AJ7 AJ6
AJ5 AJ4
AJ9 AK9
AK2 AJ3
AJ2 AJ1
AM4 AL3
AL4 AK3
AN1 AM1
AM2 AM3
AP3 AP2
AN3 AN2
E12
AE3
5
SATA_A0_TX_P SATA_A0_TX_N
SATA_A0_RX_N SATA_A0_RX_P
SATA_A1_TX_P SATA_A1_TX_N
SATA_A1_RX_N SATA_A1_RX_P
SATA_B0_TX_P SATA_B0_TX_N
SATA_B0_RX_N SATA_B0_RX_P
SATA_B1_TX_P SATA_B1_TX_N
SATA_B1_RX_N SATA_B1_RX_P
SATA_C0_TX_P SATA_C0_TX_N
SATA_C0_RX_N SATA_C0_RX_P
SATA_C1_TX_P SATA_C1_TX_N
SATA_C1_RX_N SATA_C1_RX_P
SATA_LED#
+V_PLL_SATA
+DVDD0_SATA1 +DVDD0_SATA2 +DVDD0_SATA3 +DVDD0_SATA4
+DVDD1_SATA1 +DVDD1_SATA2
+AVDD0_SATA1 +AVDD0_SATA2 +AVDD0_SATA3 +AVDD0_SATA4 +AVDD0_SATA5 +AVDD0_SATA6 +AVDD0_SATA7 +AVDD0_SATA8 +AVDD0_SATA9
+AVDD1_SATA1 +AVDD1_SATA2 +AVDD1_SATA3 +AVDD1_SATA4
SATA_TERMP
5
OMIT
U1400
MCP79-TOPO-B
BGA
(8 OF 11)
SATA
USB_OC2#/GPIO_27/MGPIO USB_OC3#/GPIO_28/MGPIO
USB
USB_OC0#/GPIO_25 USB_OC1#/GPIO_26
USB_RBIAS_GND
4
USB0_P USB0_N
USB1_P USB1_N
USB2_P USB2_N
USB3_P USB3_N
USB4_P USB4_N
USB5_P USB5_N
USB6_P USB6_N
USB7_P USB7_N
USB8_P USB8_N
USB9_P USB9_N
USB10_P USB10_N
USB11_P USB11_N
+V_PLL_USB
GND131 GND132 GND133 GND134 GND135 GND136 GND137 GND138 GND139 GND140 GND141 GND142 GND143 GND144 GND145 GND146 GND147 GND148 GND149 GND150 GND151 GND152 GND153 GND154 GND155 GND156 GND157 GND158 GND159 GND160
4
External A
C29 D29
C28 D28
A28 B28
F29 G29
K27 L27
J26 J27
F27 G27
D27 E27
K25 L25
H25 J25
F25 G25
K23 L23
L21 K21 J21 H21
L28
A27
AD35 AD37 AD38 AE22 AE24 AE39 AE4 AD6 AF16 AF17 AF18 AF20 AF22 AF26 AF27 AF28 AF33 AF34 AF37 AF40 AG18 AG20 AG22 AG26 AG36 AG40 AH18 AH20 AH22 AH24
USB_EXTA_P USB_EXTA_N
AirPort (PCIe Mini-Card)
NC_USB_MINIP NC_USB_MININ
External D
NC_USB_EXTDP NC_USB_EXTDN
Camera
USB_CAMERA_P USB_CAMERA_N
IR
USB_IR_P USB_IR_N
Geyser Trackpad/Keyboard
USB_TPAD_P USB_TPAD_N
Bluetooth
USB_BT_P USB_BT_N
External B
USB_EXTB_P USB_EXTB_N
ExpressCard
NC_USB_EXCARDP NC_USB_EXCARDN
External C
NC_USB_EXTCP NC_USB_EXTCN
NC_USB_10P NC_USB_10N
SD Card Reader
USB_CARDREADER_P USB_CARDREADER_N
PP3V3_S0_MCP_PLL_USB
MCP_USB_RBIAS_GND
78
19 mA (A01)
R2060
1/16W MF-LF
806
402
3
38 78
BI
38 78
BI
8
78
BI
8
78
BI
8
78
BI
8
78
BI
6
29 78
BI
6
29 78
BI
39 78
BI
39 78
BI
48 78
BI
48 78
BI
6
29 78
BI
6
29 78
BI
38 78
BI
38 78
BI
8
78
BI
8
78
BI
8
78
BI
8
78
BI
6
6
30 78
BI
30 78
BI
22
1
1%
2
R2050
8.2K
1/16W MF-LF
1
R2051
8.2K
5% 1/16W MF-LF 402
2
1
R2052
8.2K
5%
402
2
1/16W MF-LF
5%
402
1
R2053
8.2K
5% 1/16W MF-LF 402
2
1
2
PP3V3_S5
USB_EXTA_OC_L USB_EXTB_OC_L USB_EXTC_OC_L EXCARD_OC_L
38
38
6 7 52 62 66 67 68 69 71 82
D
17 21 22 24 28 32 35 36 42
C
B
MCP SATA & USB
SYNC_MASTER=T18_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
D
APPLE INC.
3
2
SCALE
NONE
SYNC_DATE=02/05/2009
051-7903
SHT
OF
1
A
REV.
A
8319
8 7
6
5
4
3
OMIT
U1400
MCP79-TOPO-B
BGA
(9 OF 11)
D
53 57 58 61 66 67 68 69 71
PP3V3_S0
6 7
12 17 18 20 21 22 23 26
27 35 37 41 43 45 46 47 49 72 82
PP3V42_G3H
6 7
21 24 38 40 41 42 43 45
48 59 60 67
R2120
C
49.9K
1/16W MF-LF
1
R2110
49.9
1% 1/16W MF-LF 402
2
1
1
R2121
49.9K
1%
1%
1/16W MF-LF 402
402
2
2
HDA_SDIN0
53 78
IN
NC_MLB_RAM_SIZE
6
TP_MLB_RAM_VENDOR
(MXM_OK for MXM systems)
78
MCP_HDA_PULLDN_COMP
PP1V05_S0_MCP_PLL_NV
22
37 mA (A01)
SPIROM_USE_MLB
42
OUT
SMC_ADAPTER_EN
32 35 40 41
IN
NC_SB_A20GATE
6
TP_MCP_KBDRSTIN_L SMC_WAKE_SCI_L
40
IN
SMC_RUNTIME_SCI_L
40
IN
20 mA 17 mA
SM_INTRUDER_L
TP_MCP_LID_L PM_BATLOW_L
40
IN
PM_DPRSLPVR
61 75
IN
PM_PWRBTN_L
40
IN
PM_SYSRST_DEBOUNCE_L
24
IN
RTC_RST_L
PM_RSMRST_L
40
IN
MCP_PS_PWRGD
24
IN
MCP_CPU_VLD
24 24
IN
JTAG_MCP_TDI
12
IN
JTAG_MCP_TDO
1
12
OUT
JTAG_MCP_TMS
12
IN
JTAG_MCP_TRST_L
12
IN
JTAG_MCP_TCK
12
B
IN
MCP_CLK25M_XTALIN
24
IN
MCP_CLK25M_XTALOUT
24
OUT
RTC_CLK32K_XTALIN
24
IN
RTC_CLK32K_XTALOUT
24
OUT
R2150
10K
1/16W MF-LF
1
5%
402
2
G15
HDA_SDATA_IN0
Int PD
J14
HDA_SDATA_IN1_GPIO_2/PS2_KB_CLK
Int PD
J15
HDA_SDATA_IN2_GPIO_3/PS2_KB_DATA
Int PD
A15
HDA_PULLDN_COMP
AE18
+V_PLL_NV_H
AE17
+V_PLL_SP_SPREF
L24
GPIO_1/PWRDN_OK/SPI_CS1
L26
GPIO_12_SUS_STAT_ACCLMTR_EXT_TRIG_L
K13
A20GATE
L13
KBRDRSTIN*
C19
SIO_PME*
C18
EXT_SMI/GPIO_32*
B20
INTRUDER*
M25
LID*
M24
LLB*
M22
CPU_DPRSLPVR
C16
PWRBTN*
D16
RSTBTN*
C20
RTC_RST*
D20
PWRGD_SB
E20
PS_PWRGD
C17 D17
CPU_VLD
E19
JTAG_TDI
F19
JTAG_TDO
J19
JTAG_TMS
J18
JTAG_TRST*
G19
JTAG_TCK
A16
XTALIN
B16
XTALOUT
A19
XTALIN_RTC
B19
XTALOUT_RTC
1
R2151
100K
5% 1/16W MF-LF 402
2
Int PU Int PU Int PU (S5)
Int PU (S5) Int PU (S5)
Int PU (S5) Int PU
Int PU
Int PU
Int PU (S5)
HDA
HDA_DOCK_EN*_GPIO_4/PS2_MS_CLK
HDA_DOCK_RST*_GPIO_5/PS2_MS_DATA
(MGPIO2)
MISC
(MGPIO3)
+V_DUAL_HDA1 +V_DUAL_HDA2
HDA_SDATA_OUT
HDA_BITCLK
HDA_RESET*
SLP_RMGT*
THERM_DIODE_P THERM_DIODE_N
MCP_VID0/GPIO_13 MCP_VID1/GPIO_14 MCP_VID2/GPIO_15
SMB_DATA0
SMB_CLK1/MSMB_CLK
SMB_DATA1/MSMB_DATA
SMB_ALERT*/GPIO_64
FANRPM0/GPIO_60 FANCTL0/GPIO_61 FANRPM1/GPIO_63 FANCTL1/GPIO_62
CPUVDD_EN
SPI_CS0/GPIO_10 SPI_CLK/GPIO_11
SPI_DI/GPIO_8 SPI_DO/GPIO_9
SUS_CLK/GPIO_34
BUF_SIO_CLK
TEST_MODE_EN
HDA_SYNC
SLP_S3*
SLP_S5*
SPKR
SMB_CLK0
PKG_TEST
J16 K16
F15
E15
K15
L15
K17 L17
G17 J17 H17
B11 C11
L20 M20 M21
C13
L19 K19 G21 F21 M23
B12 A12 D12 C12
C14 D13 C15 B14
B18 AE7
K22 L22
PP3V3_S0
1
R2160
8.2K
5% 1/16W MF-LF 402
2
HDA_SDOUT_R
20 78
HDA_BIT_CLK_R
20 78
HDA_RST_R_L
20 78
20 78
HDA_SYNC_R
MCP_GPIO_4 AUD_I2C_INT_L
PM_SLP_S3_L PM_SLP_RMGT_L PM_SLP_S4_L
MCP_THMDIODE_P MCP_THMDIODE_N
MCP_VID<0> MCP_VID<1> MCP_VID<2>
MCP_SPKR
SMBUS_MCP_0_CLK SMBUS_MCP_0_DATA SMBUS_MCP_1_CLK SMBUS_MCP_1_DATA AP_PWR_EN
MEM_EVENT_L ODD_PWR_EN_L SMC_IG_THROTTLE_L ARB_DETECT
MCP_CPUVDD_EN
SPI_CS0_R_L SPI_CLK_R SPI_MISO SPI_MOSI_R
PM_CLK32K_SUSCLK_R TP_MCP_BUF_SIO_CLK
MCP_TEST_MODE_EN
1
R2163
10K
5% 1/16W MF-LF 402
2
82 45 46 47 49 53 57 58 61 66 67 6 7
12 17 18 20 21 22 23 26 27 35 37 41 43 68 69 71 72
7 mA (A01)
R2170
1 2
R2171
22
1 2
5% 1/16W MF-LF
R2172
402
1 2
R2173
22
1 2
5% 1/16W MF-LF
402
20
IN
OUT OUT OUT
OUT OUT
OUT OUT OUT
OUT
BI
OUT
BI
OUT
IN
OUT
IN
20
OUT
OUT OUT
IN
OUT
OUT
1
R2190
1K
1% 1/16W MF-LF 402
2
22
5% 1/16W MF-LF
402
22
5% 1/16W MF-LF
402
20 58
6
32 35 40 67 71
8
32
6
38 40 41 67
46 82
46 82
20 64
20 64
20 64
12 26 27 43 78
12 26 43 78
43 58 72 78
43 58 72 78
20 29 32
20 26 27 40
37
20 40 41
42 78
42 78
42 78
42 78
24 78
HDA_SDOUT
HDA_BIT_CLK
HDA_RST_L
HDA_SYNC
BOOT_MODE_SAFE
1
R2180
10K
2
53 78
OUT
53 78
OUT
53 78
OUT
53 78
OUT
PP3V3_S0
5% 1/16W MF-LF 402
41
OUT
BOOT_MODE_USER
1
R2181
10K
USER mode: Normal
5% 1/16W
SAFE mode: For ROMSIP
MF-LF 402
2
recovery Connects to SMC for
automatic recovery.
53 57 58 61 66 67 68 69 71 6 7
12 17 18 20 21 22 23 26 27 35 37 41 43 45 46 47 49 72 82
BIOS Boot Select
I/F HDA_SDOUT LPC
PCI SPI0 SPI1
SPI0 = SPI_CS0_L, SPI1 = SPI_CS1_L R1961 and R2160 selects SPI0 ROM by
default, LPC+ debug card pulls LPC_FRAME# high for SPI1 ROM override.
NOTE: MCP79 does not support FWH, only LPC ROMs. So Apple designs will not use LPC for BootROM override.
NOTE: MCP79 rev A01 does not support SPI1 option. Rev B01 will.
0 0 1 1
LPC_FRAME#
0 1 0 1
BUF_SIO_CLK Frequency
Frequency
24 MHz
14.31818 MHz
HDA_SYNC
1 0
SPI Frequency Select
0 0 1 1
SPI_CLK
0 1 0 1
Frequency
SPI_DO 31 MHz 42 MHz 25 MHz
1 MHz
NOTE: Straps not provided on this page.
D
C
B
HDA Output Caps
For EMI Reduction on HDA interface
HDA_SDOUT_R HDA_BIT_CLK_R
HDA_RST_R_L HDA_SYNC_R
1
C2170
A
10PF
CERM
5%
50V 402
C2172
2
1
C2171
2
10PF
5% 50V CERM 402
10PF
CERM
1
5%
50V
2
402
1
C2173
10PF
5% 50V
2
CERM 402
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
8
20 78
20 78
20 78
20 78
7 6
1
R2140
10K
5% 1/16W MF-LF 402
2
1
R2141
10K
5% 1/16W MF-LF 402
2
1
R2142
10K
5% 1/16W MF-LF 402
2
PP3V3_S0
1
R2143
10K
5% 1/16W MF-LF 402
2
MCP_GPIO_4 AUD_I2C_INT_L MEM_EVENT_L SMC_IG_THROTTLE_L
ARB_DETECT
1
R2147
100K
5% 1/16W MF-LF 402
2
5
58 61 66 67 68 69 71 72 82 6 7
12 17 18 20 21 22 23 26 27
35 37 41 43 45 46 47 49 53 57
20
20 58
20 26 27 40
20 40 41
20
4
1
R2155
22K
5% 1/16W MF-LF 402
2
1
R2156
22K
5% 1/16W MF-LF 402
2
PP3V3_S3
2
R2154
100K
5% 1/16W MF-LF 402
1
AP_PWR_EN
MCP_VID<0> MCP_VID<1> MCP_VID<2>
1
R2157
22K
5% 1/16W MF-LF 402
2
6 7
25 29 30 43 48 50 68
20 29 32
20 64
20 64
20 64
SYNC_MASTER=T18_MLB
APPLE INC.
3
2
MCP HDA & MISC
SYNC_DATE=02/05/2009
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
D
SCALE
NONE
051-7903
SHT
20 83
1
A
REV.
A
OF
8 7
6
5
4
3
OMIT
U1400
MCP79-TOPO-B
BGA
AH26 AH33 AH34 AH37 AH38 AJ39
D
C
B
A
AK10 AK33 AK34 AK37
AK40 AL36 AL40
AM10 AM16 AM18 AM20 AM22 AM24 AM26 AM30 AM34 AM35 AM37 AM38
AP26 AN28 AN30 AN39
AP10 AU26 AP14 AU14 AP28 AP32 AP34 AP36 AP37
AP40
AW23 AR28 AR32 AR40 AT10 AR12 AT13 AT29 AT33
AY21 AY22
AU12 AU28 AP33 AU32 AR30 AU36 AU38
AV28 AV32 AV36
AW11
AR43 AW43 AY10 AV12 AY30 AY33 AY34 AY37 AY38 AY41
(11 OF 11)
GND161 GND162 GND163 GND164 GND165 GND166
AJ8
GND167 GND168 GND169 GND170 GND171
AK4
GND172 GND173 GND174 GND175
AL5
GND176 GND177 GND178 GND179 GND180 GND181 GND182 GND183 GND184 GND185 GND186 GND187 GND188
AM5
GND189
AM6
GND190
AM7
GND191
AM9
GND192 GND193 GND194 GND195 GND196
AN4
GND197
Y7
GND198 GND199 GND200 GND201 GND202 GND203 GND204 GND205 GND206 GND207
AP4
GND208 GND209
AP7
GND210 GND211 GND212 GND213 GND214 GND215 GND216 GND217 GND218 GND219
AT6
GND220
AT7
GND221
AT9
GND222 GND223 GND224
L12
GND225 GND226 GND227 GND228 GND229 GND230 GND231 GND232
AU4
GND233
G28
GND234
F20
GND235 GND236 GND237 GND238
AV4
GND239
AV7
GND240 GND241
G20
GND242 GND243 GND244 GND245 GND246 GND247 GND248 GND249 GND250 GND342 GND251 GND252
GND253 GND254 GND255 GND256 GND257 GND258 GND259 GND260 GND261 GND262 GND263 GND264 GND265 GND266 GND267 GND268 GND269 GND270 GND271 GND272 GND273 GND274 GND275 GND276 GND277 GND278 GND279 GND280 GND281 GND282 GND283 GND284 GND285 GND286 GND287 GND288 GND289 GND290 GND291 GND292 GND293 GND294 GND295 GND296 GND297 GND298 GND299 GND300 GND301
GND
GND302 GND303 GND304 GND305 GND306 GND307 GND308 GND309 GND310 GND311 GND312 GND313 GND314 GND315 GND316 GND317 GND318 GND319 GND320 GND321 GND322 GND323 GND324 GND325 GND326 GND327 GND328 GND329 GND330 GND331 GND332 GND333 GND334 GND335 GND336 GND337 GND338 GND339 GND340 GND341
GND343
AV40 BA1 BA4 AW31 AY6 L35 BC33 BC37 BC41 AY14 BC5 C2 D10 D14 D15 D18 D19 D22 D23 D26 D30 D37 D6 E13 E17 E21 E25 E29 E33 F12 F16 F32 F8 G10 G12 G14 G16 BC12 G22 G24 AW20 G34 G4 G43 G6 G8 H11 H15 AW35 H23 AN8 G40 J12 J8 K10 K12 K18 K26 K37 K4 K40 K8 AU1 L40 L43 L5 M10 M34 M35 M37 Y28 Y33 Y34 Y35 Y37 Y38 AB17 AB16 AN26 AD7 M11 AA4 AB19 AY13 P11 Y6 T11 V11 Y11 AH16 T22
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
8
7 6
PPVCORE_S0_MCP
6 7
22 44 64
23065 mA (A01, 1.2V) 16996 mA (A01, 1.0V)
PP3V42_G3H
6 7
20 24 38 40 41 42 43 45
48 59 60 67
10 uA (G3) 80 uA (S0)
OMIT
U1400
MCP79-TOPO-B
BGA
AA25 AC23
U25 AH12 AG10
AG5
Y21
Y23 AA16 AA26 AA27 AA28 AC16 AC17 AC18 AC19 AC20 AC21 AA17 AC24 AC25 AC26 AC27 AC28 AD21 AD23
W27
V25 AA18 AE19 AE21 AE23 AE25 AE26 AE27 AE28 AF10 AF11 AA19
AF2 AF21 AF23 AF25
AF3
AF4
AF7 AH23
AF9 AA20 AG11 AG12 AG21 AG23 AG25
AG3
AG4 AA21
AG6
AG7
AG8
AG9
AH1 AH10 AH11
W26
AH2 AA23
W28 AH25 AH21
AH3
AH4
AH5
AH6
AH7
AH9 AA24
W21
W23
W25 AF12
A20
+VDD_CORE1 +VDD_CORE2 +VDD_CORE3 +VDD_CORE4 +VDD_CORE5 +VDD_CORE6 +VDD_CORE7 +VDD_CORE8 +VDD_CORE9 +VDD_CORE10 +VDD_CORE11 +VDD_CORE12 +VDD_CORE13 +VDD_CORE14 +VDD_CORE15 +VDD_CORE16 +VDD_CORE17 +VDD_CORE18 +VDD_CORE19 +VDD_CORE20 +VDD_CORE21 +VDD_CORE22 +VDD_CORE23 +VDD_CORE24 +VDD_CORE25 +VDD_CORE26 +VDD_CORE27 +VDD_CORE28 +VDD_CORE29 +VDD_CORE30 +VDD_CORE31 +VDD_CORE32 +VDD_CORE33 +VDD_CORE34 +VDD_CORE35 +VDD_CORE36 +VDD_CORE37 +VDD_CORE38 +VDD_CORE39 +VDD_CORE40 +VDD_CORE41 +VDD_CORE42 +VDD_CORE43 +VDD_CORE44 +VDD_CORE45 +VDD_CORE46 +VDD_CORE47 +VDD_CORE48 +VDD_CORE49 +VDD_CORE50 +VDD_CORE51 +VDD_CORE52 +VDD_CORE53 +VDD_CORE54 +VDD_CORE55 +VDD_CORE56 +VDD_CORE57 +VDD_CORE58 +VDD_CORE59 +VDD_CORE60 +VDD_CORE61 +VDD_CORE62 +VDD_CORE63 +VDD_CORE64 +VDD_CORE65 +VDD_CORE66 +VDD_CORE67 +VDD_CORE68 +VDD_CORE69 +VDD_CORE70 +VDD_CORE71 +VDD_CORE72 +VDD_CORE73 +VDD_CORE74 +VDD_CORE75 +VDD_CORE76 +VDD_CORE77 +VDD_CORE78 +VDD_CORE79 +VDD_CORE80 +VDD_CORE81
+VBAT
(10 OF 11)
+3.3V_DUAL_USB1 +3.3V_DUAL_USB2 +3.3V_DUAL_USB3 +3.3V_DUAL_USB4
+VTT_CPU1 +VTT_CPU2 +VTT_CPU3 +VTT_CPU4 +VTT_CPU5 +VTT_CPU6 +VTT_CPU7 +VTT_CPU8
+VTT_CPU9 +VTT_CPU10 +VTT_CPU11 +VTT_CPU12 +VTT_CPU13 +VTT_CPU14 +VTT_CPU15 +VTT_CPU16 +VTT_CPU17 +VTT_CPU18 +VTT_CPU19 +VTT_CPU20 +VTT_CPU21 +VTT_CPU22 +VTT_CPU23 +VTT_CPU24 +VTT_CPU25 +VTT_CPU26 +VTT_CPU27 +VTT_CPU28 +VTT_CPU29 +VTT_CPU30 +VTT_CPU31 +VTT_CPU32 +VTT_CPU33 +VTT_CPU34 +VTT_CPU35 +VTT_CPU36 +VTT_CPU37
POWER
+VTT_CPU38 +VTT_CPU39 +VTT_CPU40 +VTT_CPU41 +VTT_CPU42 +VTT_CPU43 +VTT_CPU44 +VTT_CPU45 +VTT_CPU46 +VTT_CPU47 +VTT_CPU48 +VTT_CPU49 +VTT_CPU50 +VTT_CPU51 +VTT_CPU52
+VTT_CPUCLK
+3.3V_1 +3.3V_2 +3.3V_3 +3.3V_4 +3.3V_5 +3.3V_6 +3.3V_7 +3.3V_8
+3.3V_DUAL1 +3.3V_DUAL2 +3.3V_DUAL3 +3.3V_DUAL4
+VDD_AUXC1 +VDD_AUXC2 +VDD_AUXC3
5
R32 AC32 E40 J36 N32 T32 U32 V32 W32 P31 AF32 AE32 AH32 AJ32 AK31 AK32 AD32 AL31 AB32 B41 B42 C40 C41 C42 D39 D40 D41 E38 E39 F37 F38 F39 G36 G37 G38 H35 H37 J34 J35 K33 K34 K35 L32 L33 L34 M31 M32 M33 N31 P32 Y32 AA32
AG32
AD10 AE8 AB10 AD9 Y10 AB11 AA8 Y9
G18 H19 J20 K20
G26 H27 J28 K28
T21 U21 V21
4
PP1V05_S0 1139 mA
43 mA
PP3V3_S0
PP3V3_S5 16 mA
250 mA
PP1V05_S5
66 67 6 7 9 23 35 61 65
1182 mA (A01)
46 47 49 53 57 58 61 66 67 68 6 7
12 17 18 20 22 23 26 27 35 37 41 43 45 69 71 72 82
450 mA (A01)
68 69 71 82 6 7
17 19 22 24 28 32 35 36 42 52 62 66 67
266 mA (A01)
6 7
105 mA (A01)
22 32 66
10 11 12 13 16 17 19 22
3
MCP Power & Ground
SYNC_MASTER=T18_MLB
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
APPLE INC.
2
SYNC_DATE=02/05/2009
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SIZE
D
SCALE
NONE
051-7903
SHT
1
D
C
B
A
REV.
A
OF
8321
8 7
6
5
4
3
MCP Core Power
PPVCORE_S0_MCP
6 7
21 44 64
23065 mA (A01, 1.2V) 16996 mA (A01, 1.0V)
(No IG vs. EG data)
D
MCP PCIE (DVDD) Power
35 61 65 66 67 6 7 9
10 11 12 13
16 17 19 21 22 23
57 mA (A01) 43 mA (A01)
C2500
C2515
MCP 1.05V AUX Power
PP1V05_S5
6 7
21 32 66
MCP FSB (VTT) Power
35 61 65 66 67
PP1V05_S0
6 7 9
10 11 12 13
16 17 19 21 22 23
1182 mA (A01)
C
NV: 1x 10uF 0805, 2x 4.7uF 0402, 3x 1uF 0402, 9x 0.1uF 0402 (23.3 uF) Apple: 4x 4.7uF 0402, 4x 1uF 0402, 6x 0.1uF 0402 (23.4 uF)
4.7UF
20% X5R
402
1
4V
2
C2501
4.7UF
20% X5R
402
1
C2502
4V
2
4.7UF
20% X5R
402
1
C2503
4.7UF
4V
2
20% X5R
402
1
1
C2504
1UF
4V
10% 10V
2
2
X5R 402-1
MCP SATA (DVDD) Power
PP1V05_S0PP1V05_S0
6 7 9
10 11 12 13 16 17 19 21
22 23 35 61 65 66 67
4.7UF
20% X5R
402
1
1
C2516
1UF
10%
4V
10V
2
2
X5R 402-1
1
C2517
1UF
10% 10V
2
X5R 402-1
1
C2518
0.1uF
20% 10V
2
CERM 402
1
C2519
0.1uF
20% 10V
2
CERM 402
MCP 1.05V RMGT Power
PP1V05_ENET
6 7
17 22 31 32
131 mA (A01)105 mA (A01)
1
C2525
0.1uF
20% 10V
2
CERM 402
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF) Apple: 7x 2.2uF 0402 (15.4 uF)
1
C2530
2.2UF
20%
6.3V
2
CERM 402-LF
1
C2526
0.1uF
20% 10V
2
CERM 402
1
C2531
2.2UF
20%
6.3V
2
CERM 402-LF
1
C2532
2.2UF
20%
6.3V
2
CERM 402-LF
1
C2533
2.2UF
20%
6.3V
2
CERM 402-LF
1
C2534
2.2UF
20%
6.3V
2
CERM 402-LF
1
C2505
1UF
10% 10V
2
X5R 402-1
1
C2535
2.2UF
20%
6.3V
2
CERM 402-LF
1
C2506
1UF
10% 10V
2
X5R 402-1
C2520
4.7UF
20% X5R
402
C2528
4.7uF
20% X5R
402
1
C2536
2.2UF
20%
6.3V
2
CERM 402-LF
1
C2507
1UF
10% 10V
2
X5R 402-1
1
4V
2
1
4V
2
1
C2521
0.1uF
20% 10V
2
CERM 402
1
C2529
0.1uF
20% 10V
2
CERM 402
1
C2508
0.1UF
20% 10V
2
CERM 402
1
C2509
0.1UF
20% 10V
2
CERM 402
1
C2510
0.1UF
20% 10V
2
CERM 402
1
C2511
0.1UF
20% 10V
2
CERM 402
1
C2512
0.1UF
20% 10V
2
CERM 402
PP1V05_S0
6 7 9
10 11 12 13 16 17 19 21
22 23 35 61 65 66 67
333 mA (A01)
PP1V05_S0_MCP_PLL_UF
7
66
562 mA (A01)
1
C2513
0.1UF
20% 10V
2
CERM 402
L2570
30-OHM-5A
1 2
0603
L2575
30-OHM-5A
1 2
0603
L2580
30-OHM-1.7A
1 2
0402
C2580
4.7UF
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 1uF 0402, 2x 0.1uF 0402 (16.9 uF) Apple: 5x 2.2uF 0402 (11 uF)
1
C2570
2.2UF
20%
6.3V
2
CERM 402-LF
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF) Apple: 2x 2.2uF 0402 (4.4 uF)
1
C2575
2.2UF
20%
6.3V
2
CERM 402-LF
1
1
20%
4V
2
X5R 402
2
1
C2571
2.2UF
20%
6.3V
2
CERM 402-LF
PP1V05_S0_MCP_SATA_AVDD
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V
1
C2576
2.2UF
20%
6.3V
2
CERM 402-LF
PP1V05_S0_MCP_PLL_FSB
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V
C2581
0.1UF
20% 10V CERM 402
1
C2572
2.2UF
20%
6.3V
2
CERM 402-LF
13
270 mA (A01)
1
C2573
2.2UF
20%
6.3V
2
CERM 402-LF
7
127 mA (A01)
PP1V05_S0_MCP_PEX_AVDD
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V
1
C2574
2.2UF
20%
6.3V
2
CERM 402-LF
19
7
206 mA (A01)
16
D
C
MCP Memory Power
PP1V5_S0
6 7
10 11 15 37 66
67 68 82
4771 mA (A01, DDR3)
1
C2553
2.2UF
20%
6.3V
2
CERM 402-LF
1
C2544
0.1UF
20% 10V
2
CERM 402
53 57 58 61 66 67 68 69 71 72 6 7
12 17 18 20 21 22 23 26
27 35 37 41 43 45 46 47 49 82
MCP 3.3V Power
72 82 41 43 45 46 47 49 53 57 58
PP3V3_S0
6 7
12 17 18 20 21
22 23 26 27 35 37 61 66 67 68 69 71
450 mA (A01)
C2540
4.7UF
1
C2551
2.2UF
20%
6.3V
2
CERM 402-LF
1
C2542
0.1UF
20% 10V
2
CERM 402
1
1
C2541
0.1UF
20% X5R
402
4V
20% 10V
2
2
CERM 402
NV: 1x 4.7uF 0603, 4x 0.1uF 0402 (5.1 uF) Apple: 4x 2.2uF 0402 (8.8 uF)
1
C2550
2.2UF
20%
6.3V
2
CERM 402-LF
1
C2552
2.2UF
20%
6.3V
2
CERM 402-LF
1
C2543
0.1UF
20% 10V
2
CERM 402
B
MCP 3.3V AUX/USB Power
66 67 68 69 71 82
PP3V3_S5
6 7
17 19 21 24 28
32 35 36 42 52 62
266 mA (A01)
MCP 3.3V/1.5V HDA Power
72 82 41 43 45 46 47 49 53 57 58
PP3V3_S0
6 7
12 17 18 20 21
22 23 26 27 35 37 61 66 67 68 69 71
7 mA (A01)
A
PP1V05_ENET
6 7
17 22 31 32
5 mA (A01)
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
8
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) Apple: 1x 2.2uF 0402 (2.2 uF)
1
C2560
2.2UF
20%
6.3V
2
CERM 402-LF
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) Apple: 1x 2.2uF 0402 (2.2 uF)
1
C2562
2.2UF
20%
6.3V
2
CERM 402-LF
L2595
30-OHM-1.7A
1 2
0402
C2595
4.7UF
20% X5R
402
4V
PP1V05_ENET_MCP_PLL_MAC
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V
1
1
C2596
0.1UF
20% 10V
2
2
CERM 402
7 6
17
5 mA (A01)
1
C2545
0.1UF
20% 10V
2
CERM 402
PP3V3_S0
19 mA (A01)
1
C2546
0.1UF
20% 10V
2
CERM 402
1
C2547
0.1UF
20% 10V
2
CERM 402
MCP 3.3V Ethernet Power
PP3V3_ENET
6 7
17 22 31 32
83 mA (A01)
MCP79 Ethernet VRef
PP3V3_ENET
6 7
17 22 31 32
1
C2548
0.1UF
20% 10V
2
CERM 402
L2555
30-OHM-1.7A
1 2
0402
R2591
1.47K
1/16W MF-LF
R2590
1.47K
1/16W MF-LF
5
1
C2549
0.1UF
20% 10V
2
CERM 402
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) Apple: 1x 2.2uF 0402 (2.2 uF)
PP3V3_S0_MCP_PLL_USB
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V
1
C2555
2.2UF
20%
6.3V
2
CERM 402-LF
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) Apple: 1x 2.2uF 0402 (2.2 uF)
1
C2564
2.2UF
20%
6.3V
2
CERM 402-LF
1
1%
402
2
402
1
1%
2
MCP_MII_VREF
1
C2591
0.1UF
20% 10V
2
CERM 402
OUT
19
19 mA (A01)
17
L2582
30-OHM-1.7A
1 2
0402
C2582
4.7UF
L2584
30-OHM-1.7A
1 2
0402
C2584
4.7UF
20% X5R
402
20% X5R
402
4V
4V
PP1V05_S0_MCP_PLL_PEX
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V
1
1
C2583
0.1UF
20% 10V
2
2
CERM 402
PP1V05_S0_MCP_PLL_SATA
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V
1
1
C2585
0.1UF
20% 10V
2
2
CERM 402
16
84 mA (A01)
19
84 mA (A01)
B
L2586
30-OHM-1.7A
1 2
0402
C2586
4.7UF
20%
4V X5R 402
L2588
30-OHM-1.7A
1 2
0402
C2588
4.7UF
20%
4V X5R 402
4
3
PP1V05_S0_MCP_PLL_CORE
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V
1
1
C2587
0.1UF
20% 10V
2
2
CERM 402
1
1
C2589
0.1UF
20% 10V
2
2
CERM 402
87 mA (A01)
PP1V05_S0_MCP_PLL_NV
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V
1
C2590
0.1UF
20% 10V
2
CERM 402
SYNC_MASTER=T18_MLB
APPLE INC.
2
15
20
37 mA (A01)
MCP Standard Decoupling
SYNC_DATE=02/05/2009
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
D
SCALE
NONE
051-7903
SHT
22
OF
83
1
A
REV.
A
8 7
WF: Checklist says 0-ohm resistor placeholder for ferrite bead.
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
PP1V8_S0
6 7
17 53 66
190 mA (A01, 1.8V)
D
PP1V05_S0
6 7 9
10 11 12 13 16 17 19 21
22 35 61 65 66 67
95 mA (A01)
C2615
Apple: 1x 2.2uF 0402 (2.2 uF)
1
C2610
2.2UF
20%
6.3V
2
CERM 402-LF
1
4.7UF
20% X5R
402
1
4V
2
2
C2616
2.2UF
20%
6.3V CERM 402-LF
6
5
4
3
NV: 1x 4.7uF 0603, 2x 0.1uF 0402 (4.9 uF)
Apple: 2x 2.2uF 0402 (4.4 uF)
PP3V3_S0_MCP_DAC
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V
1
R2651
0
5% 1/16W MF-LF 402
2
17
206 mA (A01)
D
17 23
17 23
17 23
17 23
MCP_HDMI_RSET
17 77
MCP_HDMI_VPROBE
17 77
C
58 61 66 67 68 69 71 72 82
PP3V3_S0
6 7
12 17 18 20 21 22 26 27
35 37 41 43 45 46 47 49 53 57
16 mA (A01)
NO STUFF
C2620
0.1UF
20% 10V
CERM
402
1
R2620
1
1K
1% 1/16W MF-LF
2
402
2
WF: Checklist says 0-ohm resistor placeholder for ferrite bead.
L2640
30-OHM-1.7A
1 2
0402
C2640
4.7UF
20%
6.3V CERM
603
1
2
MCP_IFPAB_RSET
17 77
MCP_IFPAB_VPROBE
17 77
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) Apple: ???
PP3V3_S0_MCP_VPLL
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V
1
C2641
0.1uF
20% 10V
2
CERM 402
NO STUFF
C2630
0.1UF
20% 10V
CERM
402
1
2
16 mA (A01)
NO STUFF
1
R2630
1K
1% 1/16W MF-LF 402
2
17
17 23
17 23 77
17 23 77
17 23 77
NC_MCP_RGB_DAC_RSET
17 23
NC_MCP_RGB_DAC_VREF
17 23
NC_MCP_TV_DAC_RSET
17 23 77
NC_MCP_TV_DAC_VREF
17 23 77 17 23 77
NC_MCP_CLK27M_XTALIN
17 23
NC_MCP_CLK27M_XTALOUT
17 23
NC_MCP_RGB_RED NC_MCP_RGB_GREEN NC_MCP_RGB_BLUE NC_MCP_RGB_HSYNC NC_MCP_RGB_VSYNC
NC_CRT_IG_R_C_PR
NC_CRT_IG_B_COMP_PB
NC_CRT_IG_HSYNC
B
NC_MCP_RGB_RED
MAKE_BASE=TRUE
NC_MCP_RGB_GREEN
MAKE_BASE=TRUE
NC_MCP_RGB_BLUE
MAKE_BASE=TRUE
NC_MCP_RGB_HSYNC
MAKE_BASE=TRUE
NC_MCP_RGB_VSYNC
MAKE_BASE=TRUE
NC_CRT_IG_R_C_PR
MAKE_BASE=TRUE
NC_CRT_IG_G_Y_YNC_CRT_IG_G_Y_Y
MAKE_BASE=TRUE
NC_CRT_IG_B_COMP_PB
MAKE_BASE=TRUE
NC_CRT_IG_HSYNC
MAKE_BASE=TRUE
NC_CRT_IG_VSYNCNC_CRT_IG_VSYNC
MAKE_BASE=TRUE
NC_MCP_RGB_DAC_RSET
MAKE_BASE=TRUE
NC_MCP_RGB_DAC_VREF
MAKE_BASE=TRUE
NC_MCP_TV_DAC_RSET
MAKE_BASE=TRUE
NC_MCP_TV_DAC_VREF
MAKE_BASE=TRUE
NC_MCP_CLK27M_XTALIN
MAKE_BASE=TRUE
NC_MCP_CLK27M_XTALOUT
MAKE_BASE=TRUE
NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE
NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE
NO_TEST=TRUE NO_TEST=TRUE
NO_TEST=TRUE NO_TEST=TRUE
NO_TEST=TRUE NO_TEST=TRUE
NO_TEST=TRUE NO_TEST=TRUE
17 23
17 23
17 23
17 23
17 23
17 23 77
17 23 77 17 23 77
17 23 77
17 23 77
17 23 77 17 23 77
17 23
17 23
17 23 77
17 23
17 23
C
B
A
Current numbers from email Xiaowei Lin provided 11/12/2007 3:22pm (no official document number).
8
7 6
MCP Graphics Support
SYNC_MASTER=K19_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
APPLE INC.
5
4
3
2
SCALE
D
051-7903
NONE
SHT
SYNC_DATE=02/05/2009
OF
8323
1
A
REV.
A
8 7
6
5
4
3
Platform Reset Connections
RTC Power Source
1
2
PP3V42_G3H
1
C2802
0.1UF
10% 16V
2
X5R 402
PP3V42_G3H
6 7
20 21 24 38 40 41 42 43
45 48 59 60 67
D
C2800
4.7UF
6.3V
1
C2801
4.7UF
20%
2
X5R 402
6.3V
20% X5R
402
6 7
20 21 24 38 40 41 42 43 45
48 59 60 67
18 78
IN
LPC_RESET_L
LPC Reset (Unbuffered)
R2881
PLACEMENT_NOTE=Place close to U1400
PLACEMENT_NOTE=Place close to U1400
33
1 2
5% 1/16W MF-LF
402
PCIE Reset (Unbuffered)
R2883
33
1 2
5% 1/16W MF-LF
402
DEBUG_RESET_L
SMC_LRESET_L
42
OUT
D
40
OUT
RTC Crystal
R2810
0
RTC_CLK32K_XTALOUT
20
IN
NO STUFF
R2811
10M
5% 1/16W MF-LF
RTC_CLK32K_XTALIN
20
OUT
C
MCP_CLK25M_XTALOUT
20
IN
402
MCP 25MHz Crystal
NO STUFF
R2816
1M
5% 1/16W MF-LF
MCP_CLK25M_XTALIN
20
OUT
402
1 2
1/16W MF-LF
1
2
R2815
1 2
1/16W MF-LF
402
1
2
RTC_CLK32K_XTALOUT_R
5%
402
0
MCP_CLK25M_XTALOUT_R
5%
CRITICAL
Y2810
32.768K
7X1.5X1.4-SM
CRITICAL
Y2815
25.0000M
SM-3.2X2.5MM
1 4
1 3
MCP S0 PWRGD & CPU_VLD
PP3V3_S5
6 7
17 19 21 22 28 32 35 36
B
40 62 64 65 66 67
IN
61
IN
42 52 62 66 67 68 69 71 82
ALL_SYS_PWRGD
VR_PWRGOOD_DELAY
2
A
U2850
1
B
1
C2850
0.1UF
20% 10V
2
CERM 402
TC7SZ08AFEAPE
5
SOT665
4
3
MCP_PS_PWRGD
C2810
12pF
1 2
5%
50V
CERM
402
C2811
12pF
1 2
5%
50V
CERM
402
C2815
12pF
1 2
5%
50V
CERM
402
NC
2 4
NC
C2816
12pF
1 2
5%
50V
CERM
402
PCIE_RESET_L
16 24 35
IN
MAKE_BASE=TRUE
MEM_VTT_EN_R
18
IN
LPC_CLK33M_SMC_R
18 78
IN
PLACEMENT_NOTE=Place close to U1400
R2893
0
1 2
5% 1/16W MF-LF
402
R2895
0
1 2
5% 1/16W MF-LF
402
R2825
33
1 2
5% 1/16W MF-LF
402
R2891
1 2
1/16W MF-LF
R2894
1 2
1/16W MF-LF
R2870
1 2
1/16W MF-LF
R2826
1 2
1/16W MF-LF
PCIE_RESET_L
0
PCA9557D_RESET_L
5%
402
BKLT_PLT_RST_L
0
MINI_RESET_L
5%
402
CARDREADER_PLT_RST_L
33
MEM_VTT_EN
5%
402
LPC_CLK33M_SMC
33
LPC_CLK33M_LPCPLUS
5%
PLACEMENT_NOTE=Place close to U1400
402
16 24 35
OUT
25
OUT
73
OUT
29
OUT
C
30
OUT
8
63 68
OUT
40 78
OUT
42 78
OUT
B
R2829
22
PM_CLK32K_SUSCLK_R
20 78
IN
20
OUTY
PLACEMENT_NOTE=Place close to U1400
1 2
5% 1/16W MF-LF
402
PM_CLK32K_SUSCLK
40 78
OUT
MCP_CPUVDD_EN
20
IN
PLACEMENT_NOTE=Place close to U1400
1 2
5% 1/16W MF-LF
402
MCP_CPU_VLD
20
OUT
R2850
0
System Reset Circuit
PM_SYSRST_L
40
IN
A
XDP_DBRESET_L
9
12 20
IN
PLACEMENT_NOTE=Place R2897 on BOTTOM
XDP
R2896
0
1 2
5% 1/16W MF-LF
R2897
402
SILK_PART=SYS RST
OMIT
1/16W MF-LF
402
R2899
1 2
1/16W
1
MF-LF
0
5%
2
10K pull-up to 3.3V S0 inside MCP
33
5%
402
PM_SYSRST_DEBOUNCE_L
NO STUFF
1
C2899
1UF
10% 10V
2
X5R 402
OUT
SYNC_MASTER=WFERRY_K19I
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
APPLE INC.
8
7 6
5
4
3
2
SB Misc
DRAWING NUMBER
SIZE
D
SCALE
NONE
SYNC_DATE=01/06/2009
051-7903
SHT
OF
24
1
A
REV.
A
83
8 7
Page Notes
Power aliases required by this page:
- =PP3V3_S3_VREFMRGN
- =PP3V3_S5_VREFMRGN
- =PPVTT_S3_DDR_BUF
Signal aliases required by this page:
- =I2C_VREFDACS_SCL
- =I2C_VREFDACS_SDA
- =I2C_PCA9557D_SCL
- =I2C_PCA9557D_SDA
BOM options provided by this page:
D
VREFMRGN NO_VREFMRGN
C
B
6
MEM A VREF CAMEM A VREF DQ
DAC channel A B A B C Min DAC code 0x00 0x00 0x00 0x00 0x00 Max DAC code 0x87 0x87 0x87 0x87 0x55 Max sink I -3.75 mA -3.75 mA -3.75 mA -3.75 mA -0.91 mA Max source I 5 mA 5 mA 5 mA 5 mA 0.52 mA Nominal Vref 0.75 V 0.75 V 0.75 V 0.75 V 0.70 V Min Vref 0.375 V 0.375 V 0.375 V 0.375 V 0.091 V Max Vref 1.250 V 1.250 V 1.250 V 1.250 V 1.044 V Vref Stepping 6.5 mV 6.5 mV 6.5 mV 6.5 mV 11.2 mV (per DAC LSB)
PP3V3_S3
6 7
20 29 30 43 48 50 68
VREFMRGN
C2900
2.2UF
20%
6.3V CERM 402-LF
25 37 40 43 81
25 37 40 43 81
SMBUS_SMC_MGMT_SCL
IN
SMBUS_SMC_MGMT_SDA
BI
ADDR=0x98(WR)/0x99(RD)
VREFMRGN
1
C2901
0.1UF
20% 10V
2
CERM 402
VREFMRGN
U2900
8
VDD
6
SCL
MSOP
7
SDA
9
A0
10
A1
GND
3
VOUTA
VOUTB
VOUTC
VOUTD
DAC5574
1
VREFMRGN_DQ_SODIMM
2
VREFMRGN_CA_SODIMM
4
VREFMRGN_CPUFSB
5
NC
MEM B VREF DQ
5
MEM B VREF CA
CPU FSB VREF
1
2
1
2
1
2
VREFMRGN
C2903
0.1UF
20% 10V CERM 402
VREFMRGN
C2904
0.1UF
20% 10V CERM 402
VREFMRGN
C2905
0.1UF
20% 10V CERM 402
4
SO-DIMM A and SO-DIMM B Vref settings should be margined separately
(i.e. not simultaneously) due to current limitation of TPS51116 regulator.
PPVTTDDR_S3
7
63
B1
V+
VREFMRGN
V-
B4
B1
V+
VREFMRGN
V-
B4
B1
V+
VREFMRGN
V-
B4
B1
V+
VREFMRGN
V-
B4
B1
V+
VREFMRGN
V-
B4
U2902
MAX4253
UCSP
A1
A4
U2902
MAX4253
UCSP
C1
C4
U2903
MAX4253
UCSP
A1
A4
U2903
MAX4253
UCSP
C1
C4
U2904
MAX4253
UCSP
A1
A4
VREFMRGN_DQ_SODIMMA_BUF
25
VREFMRGN_DQ_SODIMMA_EN
VREFMRGN_DQ_SODIMMB_BUF
25
VREFMRGN_DQ_SODIMMB_EN
VREFMRGN_CA_SODIMMA_BUF
25
VREFMRGN_CA_SODIMMA_EN
VREFMRGN_CA_SODIMMB_BUF
25
VREFMRGN_CA_SODIMMB_EN
NC
A2
A3
C2
C3
A2
A3
C2
C3
A2
A3
3
10mA max load
R2901
100K
5% 1/16W MF-LF
402
R2902
100K
5% 1/16W MF-LF
402
R2907
100K
5% 1/16W MF-LF
402
R2908
100K
5% 1/16W MF-LF
402
VREFMRGN
1 2
VREFMRGN
1 2
VREFMRGN
1 2
VREFMRGN
1 2
R2903
200
1 2
1% 1/16W MF-LF
402
R2904
100
1 2
1% 1/16W MF-LF
402
R2905
200
1 2
1% 1/16W MF-LF
402
R2906
100
1 2
1% 1/16W MF-LF
402
R2909
200
1 2
1% 1/16W MF-LF
402
R2910
100
1 2
1% 1/16W MF-LF
402
R2911
200
1 2
1% 1/16W MF-LF
402
R2912
100
1 2
1% 1/16W MF-LF
402
VREFMRGN
VREFMRGN
VREFMRGN
VREFMRGN
VREFMRGN
VREFMRGN
VREFMRGN
VREFMRGN
PP0V75_S3_MEM_VREFDQ_A
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm
Place close to J3100.1
PP0V75_S3_MEM_VREFDQ_B
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm
Place close to J3200.1
PP0V75_S3_MEM_VREFCA_A
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm
Place close to J3100.126
PP0V75_S3_MEM_VREFCA_B
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm
Place close to J3200.126
D
26
27
26
27
C
B
ADDR=0x30(WR)/0x31(RD)
SMBUS_SMC_MGMT_SCL
25 37 40 43 81
IN
SMBUS_SMC_MGMT_SDA
25 37 40 43 81
BI
A
Required zero ohm resistors when no VREF margining circuit stuffed
PART NUMBER
116S0004 1 116S0004
116S0004
8
QTY
1 CRITICAL
1 CRITICAL
DESCRIPTION
RES,MTL FILM,0,5%,0402,SM,LF
RES,MTL FILM,0,5%,0402,SM,LF
RES,MTL FILM,0,5%,0402,SM,LF
RES,MTL FILM,0,5%,0402,SM,LF
7 6
VREFMRGN
1
C2902
0.1UF
20% 10V
2
CERM 402
REFERENCE DES
R2903 CRITICAL R2905 R2909116S0004 R2911
PCA9557
3
A0
4
A1
5
A2
1
SCL
2
SDA
THRM
PAD
17
CRITICAL
CRITICAL1
16
VCC
U2901
QFN
GND
8
VREFMRGN
P0 P1 P2 P3 P4 P5 P6 P7
RESET*
6
NC
7 9 10 11 12 13
NC
14
NC
15
BOM OPTION NO_VREFMRGN NO_VREFMRGN NO_VREFMRGN NO_VREFMRGN
VREFMRGN_CPUFSB_EN VREFMRGN_CA_SODIMMA_EN VREFMRGN_DQ_SODIMMA_EN VREFMRGN_CA_SODIMMB_EN VREFMRGN_DQ_SODIMMB_EN
PCA9557D_RESET_L
B1
V+
VREFMRGN
V-
B4
U2904
MAX4253
UCSP
C1
C4
VREFMRGN_CPUFSB_BUF
25
VREFMRGN_CPUFSB_EN
R2913
100K
1/16W MF-LF
100
1/16W MF-LF
402
VREFMRGN
1%
Place close to U1000.AD26
CPU_GTLREF
9
75
OUT
R2914
1 2
VREFMRGN
5%
1 2
402
C2
C3
25
25
25
25
25
24
IN
FSB/DDR3 Vref Margining
SYNC_MASTER=K24_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
D
APPLE INC.
5
4
3
2
SCALE
NONE
SYNC_DATE=02/05/2009
051-7903
SHT
OF
1
A
REV.
A
8325
8 7
6
5
4
3
Power aliases required by this page:
- =PP1V5_S0_MEM_A
- =PP1V5_S3_MEM_A
- =PP0V75_S0_MEM_VTT_A
- =PPSPD_S0_MEM_A (2.5 - 3.3V)
Signal aliases required by this page:
- =I2C_SODIMMA_SCL
- =I2C_SODIMMA_SDA
BOM options provided by this page:
D
(NONE)
C
B
A
Page Notes
72 82 45 46 47 49 53
PP3V3_S0
6 7
12 17 18 20
21 22 23 27 35 37 41 43 57 58 61 66 67 68 69 71
1
C3140
2.2UF
20%
6.3V
2
CERM 402-LF
14 76
IN
14 76
IN
14 76
IN
14 76
IN
14 76
IN
14 76
IN
14 76
IN
14 76
IN
14 76
IN
14 76
IN
14 76
IN
14 76
IN
14 76
IN
14 76
IN
14 76
IN
14 76
IN
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
IN
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
IN
14 76
BI
14 76
BI
1
R3140
10K
5% 1/16W MF-LF 402
2
GND
PP1V5_S3
6 7
27 28 63 68
MEM_A_CKE<0>
MEM_A_BA<2>
MEM_A_A<12> MEM_A_A<9>
MEM_A_A<8> MEM_A_A<5>
MEM_A_A<3> MEM_A_A<1>
MEM_A_CLK_P<0> MEM_A_CLK_N<0>
MEM_A_A<10> MEM_A_BA<0>
MEM_A_WE_L MEM_A_CAS_L
MEM_A_A<13> MEM_A_CS_L<1>
MEM_A_DQ<33> MEM_A_DQ<32>
MEM_A_DQS_N<4> MEM_A_DQS_P<4>
MEM_A_DQ<34> MEM_A_DQ<35>
MEM_A_DQ<44> MEM_A_DQ<41>
MEM_A_DM<5>
MEM_A_DQ<45> MEM_A_DQ<42>
MEM_A_DQ<52> MEM_A_DQ<51>
MEM_A_DQS_N<6> MEM_A_DQS_P<6>
MEM_A_DQ<55> MEM_A_DQ<54>
MEM_A_DQ<61> MEM_A_DQ<60>
MEM_A_DM<7>
MEM_A_DQ<58> MEM_A_DQ<59>
MEM_A_SA<0>
MEM_A_SA<1>
1
R3141
10K
5% 1/16W MF-LF 402
2
1
C3100
10UF
20%
6.3V
2
X5R 603
CKE0
VDD NC
BA2
VDD A12/BC* A9
VDD A8 A5
VDD A3 A1
VDD CK0 CK0*
VDD A10/AP BA0
VDD WE* CAS*
VDD A13 S1*
VDD TEST
VSS DQ32 DQ33
VSS DQS4* DQS4
VSS DQ34 DQ35
VSS DQ40 DQ41
VSS DM5
VSS DQ42 DQ43
VSS DQ48 DQ49
VSS DQS6* DQS6
VSS DQ50 DQ51
VSS DQ56 DQ57
VSS DM7
VSS DQ58 DQ59
VSS SA0 VDDSPD SA1
VTT
KEY
J3100
F-RT-THB
516-0196
73 74 75 76 77 79 81 82
85 87 88 89
93 94
99 100 101 103 105 106 107 109 111 112 113 115 117 118 119 121 123 124 125 127 128 129 131 133 134 135 137 139 141 143 145 147 149 151 153 155 156 157 159 161 162 163 165 167 168 169 171 173 175 177 179 181 183 185 187 189 190 191 193 195 196 197 199 201 202 203 204
SPD ADDR=0xA0(WR)/0xA1(RD)
1
C3101
10UF
20%
6.3V
2
X5R 603
CKE1
VDD
78
A15
80
A14
VDD
8483
A11
86
A7
VDD
90
A6
9291
A4
VDD
(SYMBOL 2 OF 2)
DDR3-SODIMM-DUAL-M97-3
VREFCA
EVENT*
VDD
CK1*
VDD
RAS*
VDD
ODT0
VDD
ODT1
VDD
VSS DQ36 DQ37
VSS
VSS DQ38 DQ39
VSS DQ44 DQ45
VSS
DQS5*
DQS5
VSS DQ46 DQ47
VSS DQ52 DQ53
VSS
VSS DQ54 DQ55
VSS DQ60 DQ61
VSS
DQS7*
DQS7
VSS DQ62 DQ63
VSS
VTT
CK1
BA1
S0*
DM4
DM6
SDA SCL
9695
A2
9897
A0
102 104
108 110
114 116
120 122
NC
126
130 132
136 138 140 142 144 146 148 150 152 154
158 160
164 166
170 172 174 176 178 180 182 184 186 188
192 194
198 200
DDR3 PLANE STITCHING CAPS (SPACE EVENLY ACROSS PLANE SPLIT)
1
C3110
0.1UF
20% 10V
2
CERM 402
MEM_A_CKE<1>
NC_MEM_A_A<15> MEM_A_A<14>
MEM_A_A<11> MEM_A_A<7>
MEM_A_A<6> MEM_A_A<4>
MEM_A_A<2> MEM_A_A<0>
MEM_A_CLK_P<1> MEM_A_CLK_N<1>
MEM_A_BA<1> MEM_A_RAS_L
MEM_A_CS_L<0> MEM_A_ODT<0>
MEM_A_ODT<1>
MEM_A_DQ<36> MEM_A_DQ<37>
MEM_A_DM<4>
MEM_A_DQ<38> MEM_A_DQ<39>
MEM_A_DQ<47> MEM_A_DQ<40>
MEM_A_DQS_N<5> MEM_A_DQS_P<5>
MEM_A_DQ<46> MEM_A_DQ<43>
MEM_A_DQ<48> MEM_A_DQ<53>
MEM_A_DM<6>
MEM_A_DQ<50> MEM_A_DQ<49>
MEM_A_DQ<57> MEM_A_DQ<56>
MEM_A_DQS_N<7> MEM_A_DQS_P<7>
MEM_A_DQ<62> MEM_A_DQ<63>
MEM_EVENT_L SMBUS_MCP_0_DATA SMBUS_MCP_0_CLK
1
C3111
0.1UF
20% 10V
2
CERM 402
PP0V75_S3_MEM_VREFDQ_A
25
14 76
IN
8
IN
14 76
IN
14 76
IN
14 76
IN
14 76
IN
14 76
IN
14 76
IN
14 76
IN
14 76
IN
14 76
IN
14 76
IN
14 76
IN
14 76
IN
14 76
IN
14 76
IN
14 76
BI
14 76
BI
14 76
IN
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
IN
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
20 27 40
OUT
12 20 43 78
BI
12 20 27 43 78
IN
1
C3112
0.1UF
20% 10V
2
CERM 402
1
C3113
0.1UF
20% 10V
2
CERM 402
1
C3130
2.2UF
20%
6.3V
2
CERM 402-LF
14 76
14 76
BI
14 76
IN
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
IN
14 76
BI
14 76
BI
1
C3135
2.2UF
20%
6.3V
2
CERM 402-LF
PP0V75_S0_DDRVTT
1
C3114
0.1UF
20% 10V
2
CERM 402
1
C3131
0.1UF
20% 10V
2
CERM 402
MEM_A_DQ<0> MEM_A_DQ<1>
MEM_A_DM<0>
MEM_A_DQ<3> MEM_A_DQ<2>
MEM_A_DQ<9> MEM_A_DQ<13>
MEM_A_DQS_N<1> MEM_A_DQS_P<1>
MEM_A_DQ<11> MEM_A_DQ<14>
MEM_A_DQ<16> MEM_A_DQ<18>
MEM_A_DQS_N<2> MEM_A_DQS_P<2>
MEM_A_DQ<23> MEM_A_DQ<19>
MEM_A_DQ<24> MEM_A_DQ<30>
MEM_A_DM<3>
MEM_A_DQ<27> MEM_A_DQ<25>
PP0V75_S3_MEM_VREFCA_A
1
C3136
0.1UF
20% 10V
2
CERM 402
1
C3115
0.1UF
20% 10V
2
CERM 402
6 7
1
C3116
0.1UF
20% 10V
2
CERM 402
1 2
VREFDQ
3
VSS
5
DQ0 DQ1
VSS
DM0
VSS DQ2 DQ3
VSS DQ8 DQ9
VSS DQS1* DQS1
VSS DQ10 DQ11
VSS DQ16 DQ17
VSS DQS2* DQS2
VSS DQ18 DQ19
VSS DQ24 DQ25
VSS DM3
VSS DQ26 DQ27
VSS
CRITICAL
J3100
F-RT-THB
516-0196
7
9 11 13 14 15 17 19 20 21 23 25 26 27 29 31 32 33 35 37 38 39 41 43 44 45 47 49 51 53 55 57 59 61 63 65 66 67 69 71 72
27 63 68
1
C3117
0.1UF
20% 10V
2
CERM 402
DQS0*
(SYMBOL 1 OF 2)
RESET*
DDR3-SODIMM-DUAL-M97-3
DQS3*
KEY
25
DQS0
VSS
VSS DQ12 DQ13
VSS
VSS DQ14 DQ15
VSS DQ20 DQ21
VSS
VSS DQ22 DQ23
VSS DQ28 DQ29
VSS
DQS3
VSS DQ30 DQ31
VSS
DQ4 DQ5
DQ6 DQ7
DM1
DM2
VSS
VSS
1
2
4 6 8 10 12
16 18
22 24
28 30
34 36
40 42
46 48 50 52 54 56 58 60 62 64
68 70
C3118
0.1UF
20% 10V CERM 402
1
C3119
0.1UF
20% 10V
2
CERM 402
MEM_A_DQ<4> MEM_A_DQ<5>
MEM_A_DQS_N<0> MEM_A_DQS_P<0>
MEM_A_DQ<6> MEM_A_DQ<7>
MEM_A_DQ<8> MEM_A_DQ<12>
MEM_A_DM<1> MEM_RESET_L
MEM_A_DQ<15> MEM_A_DQ<10>
MEM_A_DQ<21> MEM_A_DQ<20>
MEM_A_DM<2>
MEM_A_DQ<17> MEM_A_DQ<22>
MEM_A_DQ<29> MEM_A_DQ<28>
MEM_A_DQS_N<3> MEM_A_DQS_P<3>
MEM_A_DQ<26> MEM_A_DQ<31>
1
C3120
0.1UF
20% 10V
2
CERM 402
1
C3121
0.1UF
20% 10V
2
CERM 402
1
C3122
0.1UF
20% 10V
2
CERM 402
1
C3123
0.1UF
20% 10V
2
CERM 402
D
14 76
BI
14 76
BIBI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
IN
27 28
IN
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
IN
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
C
B
"Factory" (top) slot
DDR3 SO-DIMM Connector A
SYNC_MASTER=K19_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
APPLE INC.
SCALE
D
NONE
DRAWING NUMBER
051-7903
SHT
OF
SYNC_DATE=02/05/2009
REV.
A
8326
A
8
7 6
5
4
3
2
1
8 7
6
5
4
3
D
C
B
A
Page Notes
Power aliases required by this page:
- =PP1V5_S0_MEM_B
- =PP1V5_S3_MEM_B
- =PP0V75_S0_MEM_VTT_B
- =PPSPD_S0_MEM_B (2.5 - 3.3V)
Signal aliases required by this page:
- =I2C_SODIMMB_SCL
- =I2C_SODIMMB_SDA
BOM options provided by this page:
(NONE)
47 49 53 57 58 61
PP3V3_S0
6 7
12 17 18 20 21
22 23 26 35 37 41 43 45 46 66 67 68 69 71 72 82
1
R3240
10K
5% 1/16W MF-LF 402
2
1
C3240
2.2UF
20%
6.3V
2
CERM 402-LF
14 76
IN
14 76
IN
14 76
IN
14 76
IN
14 76
IN
14 76
IN
14 76
IN
14 76
IN
14 76
IN
14 76
IN
14 76
IN
14 76
IN
14 76
IN
14 76
IN
14 76
IN
14 76
IN
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
IN
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
IN
14 76
BI
14 76
BI
6 7
26 28 63 68
MEM_B_CKE<0>
MEM_B_BA<2>
MEM_B_A<12> MEM_B_A<9>
MEM_B_A<8> MEM_B_A<5>
MEM_B_A<3> MEM_B_A<1>
MEM_B_CLK_P<0> MEM_B_CLK_N<0>
MEM_B_A<10> MEM_B_BA<0>
MEM_B_WE_L MEM_B_CAS_L
MEM_B_A<13> MEM_B_CS_L<1>
MEM_B_DQ<32> MEM_B_DQ<37>
MEM_B_DQS_N<4> MEM_B_DQS_P<4>
MEM_B_DQ<34> MEM_B_DQ<35>
MEM_B_DQ<41> MEM_B_DQ<40>
MEM_B_DM<5>
MEM_B_DQ<43> MEM_B_DQ<42>
MEM_B_DQ<55> MEM_B_DQ<49>
MEM_B_DQS_N<6> MEM_B_DQS_P<6>
MEM_B_DQ<52> MEM_B_DQ<51>
MEM_B_DQ<56> MEM_B_DQ<57>
MEM_B_DM<7>
MEM_B_DQ<63> MEM_B_DQ<59>
MEM_B_SA<0>
MEM_B_SA<1>
1
R3241
10K
5% 1/16W MF-LF 402
2
GND
PP1V5_S3
1
C3200
10UF
20%
6.3V
2
X5R 603
73 74 75 76 77 79 81 82
85 87 88 89
93 94
99 100 101 103 105 106 107 109 111 112 113 115 117 118 119 121 123 124 125 127 128 129 131 133 134 135 137 139 141 143 145 147 149 151 153 155 156 157 159 161 162 163 165 167 168 169 171 173 175 177 179 181 183 185 187 189 190 191 193 195 196 197 199 201 202 203 204
205 206 207 208 209 210 211 212
SPD ADDR=0xA2(WR)/0xA3(RD)
KEY
CKE0
VDD NC
BA2
J3200
F-RT-BGA3
VDD A12/BC* A9
VDD A8 A5
VDD A3 A1
VDD CK0 CK0*
VDD A10/AP BA0
VDD WE* CAS*
VDD A13 S1*
VDD TEST
VSS DQ32 DQ33
VSS DQS4* DQS4
VSS DQ34 DQ35
VSS DQ40 DQ41
VSS DM5
VSS DQ42 DQ43
VSS DQ48 DQ49
VSS DQS6* DQS6
VSS DQ50 DQ51
VSS DQ56 DQ57
VSS DM7
VSS DQ58 DQ59
VSS SA0 VDDSPD SA1
VTT
MTG PINS
MTG PIN
MTG PIN
MTG PIN MTG PIN
MTG PIN
516s0704
1
C3201
10UF
20%
6.3V
2
X5R 603
CKE1
VDD
A15 A14
VDD
A11
A7
VDD
(2 OF 2)
A6 A4
VDD
A2
DDR3-SODIMM
A0
VDD
CK1
CK1*
VDD
BA1
RAS*
VDD
S0*
ODT0
VDD
ODT1
NC
VDD
VREFCA
VSS DQ36 DQ37
VSS
DM4
VSS DQ38 DQ39
VSS DQ44 DQ45
VSS
DQS5*
DQS5
VSS DQ46 DQ47
VSS DQ52 DQ53
VSS
DM6
VSS DQ54 DQ55
VSS DQ60 DQ61
VSS
DQS7*
DQS7
VSS DQ62 DQ63
VSS
EVENT*
SDA SCL
VTT
MTG PIN
MTG PIN
MTG PIN
78 80
8483 86
90 9291
9695 9897
102 104
108 110
114 116
120 122
126
130 132
136 138 140 142 144 146 148 150 152 154
158 160
164 166
170 172 174 176 178 180 182 184 186 188
192 194
198 200
DDR3 PLANE STITCHING CAPS (SPACE EVENLY ACROSS PLANE SPLIT)
1
C3210
0.1UF
20% 10V
2
CERM 402
MEM_B_CKE<1>
NC_MEM_B_A<15> MEM_B_A<14>
MEM_B_A<11> MEM_B_A<7>
MEM_B_A<6> MEM_B_A<4>
MEM_B_A<2> MEM_B_A<0>
MEM_B_CLK_P<1> MEM_B_CLK_N<1>
MEM_B_BA<1> MEM_B_RAS_L
MEM_B_CS_L<0> MEM_B_ODT<0>
MEM_B_ODT<1>
MEM_B_DQ<33> MEM_B_DQ<36>
MEM_B_DM<4>
MEM_B_DQ<38> MEM_B_DQ<39>
MEM_B_DQ<44> MEM_B_DQ<45>
MEM_B_DQS_N<5> MEM_B_DQS_P<5>
MEM_B_DQ<47> MEM_B_DQ<46>
MEM_B_DQ<48> MEM_B_DQ<54>
MEM_B_DM<6>
MEM_B_DQ<53> MEM_B_DQ<50>
MEM_B_DQ<60> MEM_B_DQ<61>
MEM_B_DQS_N<7> MEM_B_DQS_P<7>
MEM_B_DQ<58> MEM_B_DQ<62>
MEM_EVENT_L =I2C_SODIMMB_SDA SMBUS_MCP_0_CLK
1
C3211
0.1UF
20% 10V
2
CERM 402
PP0V75_S3_MEM_VREFDQ_B
25
14 76
IN
8
IN
14 76
IN
14 76
IN
14 76
IN
14 76
IN
14 76
IN
14 76
IN
14 76
IN
14 76
IN
14 76
IN
14 76
IN
14 76
IN
14 76
IN
14 76
IN
14 76
IN
14 76
BI
14 76
BI
14 76
IN
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
IN
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
20 26 40
OUT
43
BI
12 20 26 43 78
IN
1
2
C3212
0.1UF
20% 10V CERM 402
1
C3213
0.1UF
20% 10V
2
CERM 402
1
C3230
2.2UF
20%
6.3V
2
CERM 402-LF
14 76
BI
14 76
BI
14 76
IN
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
IN
14 76
BI
14 76
BI
1
C3235
2.2UF
20%
6.3V
2
CERM 402-LF
PP0V75_S0_DDRVTT
1
C3214
0.1UF
20% 10V
2
CERM 402
1
C3231
0.1UF
20% 10V
2
CERM 402
MEM_B_DQ<0> MEM_B_DQ<1>
MEM_B_DM<0>
MEM_B_DQ<2> MEM_B_DQ<3>
MEM_B_DQ<28> MEM_B_DQ<24>
MEM_B_DQS_N<3> MEM_B_DQS_P<3>
MEM_B_DQ<31> MEM_B_DQ<30>
MEM_B_DQ<9> MEM_B_DQ<8>
MEM_B_DQS_N<1> MEM_B_DQS_P<1>
MEM_B_DQ<15> MEM_B_DQ<10>
MEM_B_DQ<21> MEM_B_DQ<17>
MEM_B_DM<2>
MEM_B_DQ<18> MEM_B_DQ<22>
PP0V75_S3_MEM_VREFCA_B
1
C3236
0.1UF
20% 10V
2
CERM 402
1
C3215
0.1UF
20% 10V
2
CERM 402
6 7
1
C3216
0.1UF
20% 10V
2
CERM 402
1 2
VREFDQ
3
VSS
5
DQ0 DQ1
VSS
DM0
VSS DQ2 DQ3
VSS DQ8 DQ9
VSS DQS1* DQS1
VSS DQ10 DQ11
VSS DQ16 DQ17
VSS DQS2* DQS2
VSS DQ18 DQ19
VSS DQ24 DQ25
VSS DM3
VSS DQ26 DQ27
VSS
CRITICAL
J3200
F-RT-BGA3
516s0704
7
9 11 13 14 15 17 19 20 21 23 25 26 27 29 31 32 33 35 37 38 39 41 43 44 45 47 49 51 53 55 57 59 61 63 65 66 67 69 71 72
26 63 68
1
C3217
0.1UF
20% 10V
2
CERM 402
DQS0*
(1 OF 2)
DDR3-SODIMM
RESET*
DQS3*
KEY
25
DQS0
VSS
VSS DQ12 DQ13
VSS
VSS DQ14 DQ15
VSS DQ20 DQ21
VSS
VSS DQ22 DQ23
VSS DQ28 DQ29
VSS
DQS3
VSS DQ30 DQ31
VSS
VSS DQ4 DQ5 VSS
DQ6 DQ7
DM1
DM2
1
2
4 6 8 10 12
16 18
22 24
28 30
34 36
40 42
46 48 50 52 54 56 58 60 62 64
68 70
C3218
0.1UF
20% 10V CERM 402
1
C3219
0.1UF
20% 10V
2
CERM 402
MEM_B_DQ<4> MEM_B_DQ<5>
MEM_B_DQS_N<0> MEM_B_DQS_P<0>
MEM_B_DQ<6> MEM_B_DQ<7>
MEM_B_DQ<29> MEM_B_DQ<25>
MEM_B_DM<3> MEM_RESET_L
MEM_B_DQ<26> MEM_B_DQ<27>
MEM_B_DQ<13> MEM_B_DQ<12>
MEM_B_DM<1>
MEM_B_DQ<14> MEM_B_DQ<11>
MEM_B_DQ<20> MEM_B_DQ<16>
MEM_B_DQS_N<2> MEM_B_DQS_P<2>
MEM_B_DQ<19> MEM_B_DQ<23>
1
C3220
0.1UF
20% 10V
2
CERM 402
1
C3221
0.1UF
20% 10V
2
CERM 402
1
C3222
0.1UF
20% 10V
2
CERM 402
1
C3223
0.1UF
20% 10V
2
CERM 402
D
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
IN
26 28
IN
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
IN
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
14 76
BI
C
B
"Expansion" (bottom) slot
DDR3 SO-DIMM Connector B
SYNC_MASTER=K19_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
APPLE INC.
SCALE
D
NONE
DRAWING NUMBER
051-7903
SHT
27 83
OF
SYNC_DATE=02/05/2009
REV.
A
A
8
7 6
5
4
3
2
1
8 7
6
5
4
3
D
D
DDR3 RESET Support
Required becaues MCP79 does not meet DDR3 spec power-up reset timing requirement.
R3309
0
MCP_MEM_RESET_L
15
IN
PP1V5_S3
6 7
26 27 63 68
C
1
R3300
10K
5% 1/16W MF-LF
402
2
1
R3301
1/16W MF-LF
20K
1
5%
2
402
2
2 1
5% 1/16W MF-LF
402
R3310
1/16W MF-LF
402
MEM_RESET_RC_L
C3300
0.1UF
20% 10V CERM 402
1K
5%
1
2
MEM_RESET_L
Q3305
DMB53D0UDW
SOT-363
D
64
B
5
E
26 27
OUT
PP3V3_S5
1
Q1
SG
2 1
Q2
C
3
R3305
MEM_RESET
3.3V S5 is used because MEM_RESET
100K
must be high before 1.5V starts to
5%
1/16W
rise to avoid glitch on MEM_RESET_L.
MF-LF
402
2
6 7
17 19 21 22 24 32 35 36 42
52 62 66 67 68 69 71 82
C
B
B
DDR3 Support
A
SYNC_MASTER=T18_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
D
APPLE INC.
8
7 6
5
4
3
2
SCALE
NONE
SYNC_DATE=02/05/2009
051-7903
SHT
OF
1
A
REV.
A
8328
D
C
B
CRITICAL
J3401
20347-325E-12
F-RT-SM
31
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
26 27 28 29 30
32
518S0610
8 7
PCIE_MINI_PRSNT_L
16
OUT
MINI_CLKREQ_L
16
OUT
PCIE_MINI_D2R_P PCIE_MINI_D2R_N
82
PCIE_MINI_R2D_P
6
77 82
PCIE_MINI_R2D_N
6
77
PCIE_CLK100M_MINI_CONN_P
6
82
PCIE_CLK100M_MINI_CONN_N
6
82
MINI_CLKREQ_Q_L
6
PCIE_WAKE_L MINI_RESET_CONN_L
6
6
PP5V_WLAN
NC
PP5V_S3_BTCAMERA_F
6
SMBUS_SMC_A_S3_SDA SMBUS_SMC_A_S3_SCL
USB_CAMERA_CONN_P USB_CAMERA_CONN_N
CONN_USB2_BT_P CONN_USB2_BT_N
1
C3422
0.1uF
20% 10V
2
CERM 402
6
5
4
3
5V S3 WLAN FET
3
D
Q3401
SSM6N15FEAPE
SOT563
5
S G
4
6
D
Q3401
SSM6N15FEAPE
SOT563
2
S G
1
C3430
0.1uF
1 2
10% 16V X5R
6
16 77
OUT
6
16 77
OUT
6
16
OUT
6
40 43 49 81
BI
6
40 43 49 81
IN
402
CRITICAL
L3401
90-OHM-100MA
1 2
PLACEMENT_NOTE=Place close to J3401.
CRITICAL
L3402
1 2
PLACEMENT_NOTE=Place close to J3401.
AP_PWR_EN
20 32
IN
AIRPORT
C3431
0.1uF
PLACEMENT_NOTE=Place close to J3401.
1 2
PCIE_MINI_R2D_C_P
10% 16V X5R 402
PLACEMENT_NOTE=Place close to J3401.
DLP11S
SYM_VER-1
PCIE_MINI_R2D_C_N
34
PCIE_CLK100M_MINI_P
PCIE_CLK100M_MINI_N
MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=5V
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V
ALS
90-OHM DLP0NS
SYM_VER-1
CAMERA
34
USB_CAMERA_P
USB_CAMERA_N
5 6 7 8
C3450
0.1UF
1 2
10% 16V X5R 402
51 82
51 82
R3455
1
1 2
5% 1/16W MF-LF
402
CRITICAL
Q3450
TPCP8102
23V1K-SM
D
WLAN_SMIT_DISCHRG
PLACEMENT_NOTE=Place close to J3401.
1000 mA peak 750 mA nominal max
L3404
FERR-120-OHM-1.5A
0402-LF
C3421
0.1uF
CERM
12
20% 10V
402
51
MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=5V
1
1
2
2
C3420
10UF
20% 10V X5R 805
XW3451
SM
XW3450
SM
1 2
1 2
PP5V_WLAN_RPP5V_WLAN_F
MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=5V
XW3452
SM
1 2
PLACEMENT_NOTEs: Place close to Q3450.
Place close to Q3450. (C3420 & C3421)
ISNS_AIRPORT_P ISNS_AIRPORT_N
16 77
IN
4
Y
U3401
5
3
PP3V3_S3
2
A
1
B
WLAN_SMIT_BUF
16 77
IN
TC7SZ08AFEAPE
SOT665
16 77
IN
16 77
IN
MINI_RESET_L
6 7
20 25 29 30 43 48 50 68
U3402
74LVC1G17DRL
SOT-553
4
IN
R3453
5
2
NC
3 1
NC
24
WLAN_SMIT_RC
1
C3453
1UF
10%
6.3V
2
CERM 402
1/16W MF-LF
R3454
33K
402
5%
62K
1/16W MF-LF
OUT OUT
1
2
1
5%
402
2
L3406
PP3V3_S3_BT_F
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm
12
VOLTAGE=3.3V
PP5V_S3
6 7 8
29 37 38 39 41 49 51 53
62 63 68
C3462
0.1uF
CERM
20% 10V
402
275 mA peak 206 mA nominal max
6
19 78
BI
6
19 78
BI
PLACEMENT_NOTE=Place close to J3401.
L3405
FERR-120-OHM-1.5A
0402-LF
1
C3452
0.1uF
20% 10V
2
CERM 402
FERR-120-OHM-1.5A
1
2
12
0402-LF
S
1 2 3
G
C3451
4
0.033UF
P5VWLAN_SS
Type Rds(on) Loading
10% 16V X5R 402
PP3V3_S3
CRITICAL
L3403
90-OHM DLP0NS
SYM_VER-1
1 2
PLACEMENT_NOTE=Place close to J3401.
BLUETOOTH
34
USB_BT_P
USB_BT_N
6
19 78
BI
6
19 78
BI
1
2
R3450
100K
1 2
1/16W MF-LF
TPCP8102Part P-Channel 14 mOhm @4.5V
0.8 A (EDP)
PP5V_S3
1
R3451
10K
5% 1/16W MF-LF 402
2
D
PM_WLAN_EN_L
Q3455
SSM3K15FV
SOD-VESM-HF
1
GS
5%
402
3
2
20 25 29 30 43 48 50 68
6 7
6 7 8
29 37 38 39 41 49 51 53
62 63 68
32
IN
D
C
B
Right Clutch Connector
A
SYNC_MASTER=K19_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
D
APPLE INC.
8
7 6
5
4
3
2
SCALE
NONE
SYNC_DATE=03/04/2009
051-7903
SHT
OF
1
A
REV.
A
8329
8 7
6
5
4
3
R3511
0
20 25 29 43 48 50 68
PP3V3_S3
6 7
MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V
1 2
5% 1/16W MF-LF
402
D
PLACEMENT_NOTE=PLACE 402 NEAR EACH PIN
PP3V3_S3_CARDREADER_AVDD
1
C3514
10UF
20%
6.3V
2
X5R 603
BI BI
USB_CARDREADER_N USB_CARDREADER_P
NO STUFF
R3503
1M
1 2
5% 1/16W MF-LF
402
CRITICAL
Y3500
12.000M-100PPM
1 2
8X4.5X1.4-SM
C3511
33PF
1 2
5%
50V
CERM
402
C3512
33PF
1 2
5%
50V
CERM
402
CARDREADER_XTAL1 CARDREADER_XTAL2
1
2
19 78
C
19 78
B
PLACEMENT_NOTE=PLACE 402 NEAR EACH PIN
PP3V3_S3_CARDREADER_DVDD
30
1
C3500
10UF
20%
6.3V
2
X5R 603
1
C3504
0.1UF
20% 10V
2
CERM 402
CARDREADER_RREF
1
R3506
715
1% 1/16W MF-LF 402
R3502
0
5% 1/16W MF-LF 402
2
1
2
1
C3501
0.1UF
20% 10V
2
CERM 402
MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V
1
C3508
0.1UF
20% 10V
2
CERM 402
PP1V8_S3_CARDREADER
1
2
CARDREADER_GPIO1
30
CARDREADER_GPIO2
30
C3502
0.1UF
20% 10V CERM 402
C3506
0.1UF
20% 10V CERM 402
CARDREADER_TEST_MOD
CARDREADER_RESET_L
1
C3503
0.1UF
20% 10V
2
CERM 402
L3500
0.22UH
1 2
0805-1
MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM
VOLTAGE=1.8V
NC NC
NC NC NC
NO STUFF
1
C3513
0.1UF
20% 10V
2
CERM 402
MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V
4
VDD18O
7
DM
8
DP
48
GPIO1
47
GPIO2
46
GPIO3
19
SK
20
CS
21
DO
22
DI
/IPD
13
X1
14
X2
10
RREF
17
TEST_MOD
18
EXTRSTZ*
6
11
AVDD
U3500
SD_CLK/MS_SCLK/SM_ALE
/IPD /IPU
AGND
5
9
152635
GL137
LQFP
IPD/ IPD/
IPD/
12
25
DVDD
VDD5V
SD_WP/SM_WPDZ SD_CMD/SM_REZ
IPU/ IPU/
IPU/
IPD/ IPD/ IPD/
IPU/
MS_BS/SM_CLE
DGND
34
16
27
36
PMOSO
SM_CDZ SD_CDZ
XD_CDZ
SM_CE SM_WEZ SM_RBZ SM_WPZ
MS_INS
40
D0
43
D1
37
D2
29
D3
28
D4
30
D5
32
D6
38
D7
39 3 41 2 23
1 31 42 44 45
24 33
SD_CLK_R
CARDREADER_PDMOD
NC NC NC NC NC
NC NC
PLACEMENT_NOTE=KEEP THIS NET AS SHORT AS POSSIBLE
1
C3507
2.2UF
20%
6.3V
2
CERM1 603
1
C3505
0.1UF
20% 10V
2
CERM 402
R3504
0
1 2
5% 1/16W MF-LF
402
PDMOD: POWER DOWN MODES NC = DISABLE (DEFAULT) 10K LOW = POWER SAVING MODE ENABLE 10K HIGH = REMOTE WAKE UP ENABLE
PP3V3_S3_CARDREADER_DVDD
30
1
R3505
39K
5% 1/16W MF-LF 402
2
PART NUMBER
516-0225
NO STUFF
1
C3515
10PF
5% 50V
2
CERM 402-1
QTY
1
DESCRIPTION
CONN,SD CARD, OPTN B
MAX CURRENT = 250MA
PP3V3_SW_SD_PWR
MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V
82
82
82
82
82
82
82
82
82
82
SD_CLK
6
6
SD_CMD SD_D<0>
6
SD_D<1>
6
SD_D<2>
6
SD_D<3>
6
SD_D<4>
6
SD_D<5>
6
6
SD_D<6> SD_D<7>
6
SD_CD_L
6
SD_WP
6
REFERENCE DES
J3500
OMIT
J3500
SD-CARD-K19
F-RT-TH
3
VSS
6
VSS
5
CLK
2
CMD
7
DAT0
8
DAT1
9
DAT2
1
CD/DAT3
10
DAT4
11
DAT5
12
DAT6
13
DAT7
14
CARD_DETECT_SW
15
CARD_DETECT_GND
16
WRITE_PROTECT_SW
4
VDD
17
SHLD_PIN
18
SHLD_PIN
19
SHLD_PIN
20
SHLD_PIN
CRITICAL
CRITICAL
BOM OPTION
D
C
B
3
Q3500
SSM6N15FEAPE
CARDREADER_RESET
16
IN
SSM6N15FEAPE
CARDREADER_PLT_RST_L
24
IN
PP3V3_S3_CARDREADER_DVDD
30
1
R3507
10K
5% 1/16W MF-LF 402
A
8
CARDREADER_GPIO1
30
7 6
2
NO STUFF
1
R3509
10K
5% 1/16W MF-LF 402
2
NO STUFF
1
R3508
10K
5% 1/16W MF-LF 402
2
1
R3510
10K
5% 1/16W MF-LF 402
2
CARDREADER_GPIO2
SOT563
Q3500
SOT563
D
5
SG
4
CARDREADER_PLT_RST
6
D
2
SG
1
30
5
4
(PDMOD)
1
R3512
10K
5% 1/16W MF-LF 402
2
NO STUFF
1
R3513
10K
5% 1/16W MF-LF 402
2
SECUREDIGITAL CARD READER
SHT
30 83
1
SYNC_DATE=03/23/2009
REV.
A
OF
A
SYNC_MASTER=K19_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
APPLE INC.
3
2
SCALE
D
051-7903
NONE
8 7
6
5
4
3
PP1V05_ENET
(221mA typ - 1000base-T)
D
PP3V3_ENET
6 7
(43mA typ - 1000base-T)
WF: Marvell numbers, update for Realtek
(19mA typ - Energy Detect)
C
ENET_CLK125M_TXCLK
17 79
IN
B
17 22 32
1
CRITICAL
L3705
FERR-120-OHM-1.5A
0402-LF
2
PP3V3_ENET_PHYAVDD
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V
Alias to =PP3V3_ENET_PHY for internal switcher. Alias to GND for external 1.05V supply.
R3796
1 2
PLACEMENT_NOTE=Place R3796 close to U1400,pin D24
22
R3730
2.49K
1/16W MF-LF
402
5%
1/16W
1
1%
2
GND
IN
ENET_CLK125M_TXCLK_R
402
MF-LF
ENET_TXD<0>
17 79
IN
ENET_TXD<1>
17 79
IN
ENET_TXD<2>
17 79
IN
ENET_TXD<3>
17 79
IN
ENET_TX_CTRL
17 79
IN
ENET_MDC
17 79
IN
ENET_MDIO
17 79
BI
ENET_RESET_L
17 79
IN
RTL8211_RSET
RTL8211_CLK125
8
RTL8211_CLK25M_CKXTAL1
32 79
IN
TP_RTL8211_CKXTAL2
1
C3700
0.1UF
10% 16V
2
X5R 402
1
C3705
0.1UF
10% 16V
2
X5R 402
R3720
10K
1/16W MF-LF
402
1
C3701
0.1UF
10% 16V
2
X5R 402
1
C3706
0.1UF
10% 16V
2
X5R 402
1
5%
2
39
22
23 24 25 26
27
30 31
29
46
32
42 43
1
C3702
0.1UF
10% 16V
2
X5R 402
ENSWREG
TXC
TXD[0] TXD[1] TXD[2] TXD[3]
TXCTL
MDC MDIO
PHYRSTB*
RSET
CLK125
CKXTAL1 CKXTAL2
6
41
AVDD33
152137
DVDD33
MANAGEMENT
REFERENCE
C3714
0.1UF
10% 16V X5R 402
44
45
VDDREG
U3700
RTL8211CLGR
TQFP
OMIT
CRITICAL
RGMII/MII
RESET
CLOCK
GND
7
203347
1
2
28
3
FB12
MEDIA DEPENDENT
LED
10
40
36
DVDD12
AVDD12
REGOUT
RXC
RXD[0]
RXD[1]/TXDLY
RXD[2]/AN0 RXD[3]/AN1
RXCTL
MDI+[0] MDI-[0]
MDI+[1] MDI-[1]
MDI+[2] MDI-[2]
MDI+[3] MDI-[3]
LED0/PHYAD0 LED1/PHYAD1
LED2/RXDLY
Reserved for EMI per RealTek request.
C3710
0.1UF
C3715
0.1UF
R3750
48
19
14 16 17 18
13
1 2
4 5
8 9
11 12
34 35 38
1
10% 16V
2
X5R 402
1
10% 16V
2
X5R 402
4.7K
5% 1/16W MF-LF
402
NO STUFF
C3790
1
2
10PF
1
C3711
0.1UF
10% 16V
2
X5R 402
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V
1
C3716
0.1UF
10% 16V
2
X5R 402
1
R3751
4.7K
5% 1/16W MF-LF 402
2
ENET_CLK125M_RXCLK_R
79
ENET_RXD_R<0>
79
ENET_RXD_R<1>
79
ENET_RXD_R<2>
79
ENET_RXD_R<3>
79
ENET_RXCTL_R
ENET_MDI_P<0> ENET_MDI_N<0>
ENET_MDI_P<1> ENET_MDI_N<1>
ENET_MDI_P<2> ENET_MDI_N<2>
ENET_MDI_P<3> ENET_MDI_N<3>
RTL8211_PHYAD0 RTL8211_PHYAD1 RTL8211_RXDLY
1
5%
50V
2
CERM
402
CRITICAL
FERR-120-OHM-1.5A
L3715
0402-LF
PP1V05_ENET_PHYAVDD
R3752
BI BI
BI BI
BI BI
BI BI
1
R3755
4.7K
1/16W MF-LF
402
R3756
5%
2
( 7mA typ - Energy Detect)
1
WF: Marvell numbers, update for Realtek
2
RTL8211_VDDREG
If internal switcher is used, must place 1x 22uF & 1x 0.1uF caps within 5mm of U3700 pins 44 & 45.
NOTE: VDDREG rise time must be >1ms to avoid damage to switcher.
1
4.7K
1/16W MF-LF
402
NC_RTL8211_REGOUT
5%
If internal switcher is used, must place inductor within 5mm of U3700, and 1x 22uF & 1x 0.1uF caps within 5mm of inductor.
2
If internal switcher is not used, VDDREG and REGOUT can float.
R3790 R3791
R3792 R3793 R3794
R3795
33 79
33 79
33 79
33 79
33 79
33 79
33 79
33 79
1
1
402
R3757
4.7K
5%
5% 1/16W MF-LF 402
2
2
4.7K
1/16W MF-LF
22
22 22 22 22
22
6 7
1 2
1 2 1 2 1 2 1 2
1 2
17 22 32
D
8
8
C
1/16W
MF-LF
MF-LF1/16W MF-LF1/16W MF-LF1/16W MF-LF1/16W
MF-LF1/16W
5%
5% 5% 5% 5%
5%
ENET_CLK125M_RXCLK
402
ENET_RXD<0>
402
ENET_RXD<1>
402
ENET_RXD<2>
402
ENET_RXD<3>
402
ENET_RX_CTRL
402
17 79
OUT
17 79
OUT
17 79
OUT
17 79
OUT
17 79
OUT
17 79
OUT
B
A
Configuration Settings:
PHYAD = 01 (PHY Address 00001) AN[1:0] = 11 (Full auto-negotiation) RXDLY = 0 (RXCLK transitions with data) TXDLY = 0 (No TXCLK Delay)
8
7 6
Ethernet PHY (RTL8211CL)
SYNC_MASTER=(K19I_MLB)
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
D
APPLE INC.
5
4
3
2
SCALE
NONE
SYNC_DATE=02/05/2009
051-7903
SHT
OF
31
1
A
REV.
A
83
8 7
6
5
4
3
3.3V ENET FET
@ 2.5V Vgs: Rds(on) = 90mOhm max I(max) = 1.7A (85C)
PP3V3_S5
6 7
17 19 21 22 24 28 32 35
36 42 52 62 66 67 68 69 71 82
D
Q3801
SSM6N15FEAPE
PM_SLP_RMGT_L
8
20 32
IN
MOBILE:
Recommend aliasing PM_SLP_RMGT_L and =P3V3ENET_EN. Nets separated on ARB for alternate power options.
SOT563
R3800
10K
1/16W MF-LF
5
402
1
5%
2
3
D
SG
4
P3V3ENET_EN_L
R3810
100K
1 2
1/16W MF-LF
402
1
C3811
0.033UF
10% 16V
2
X5R 402
5%
P3V3ENET_SS
CRITICAL
Q3810
NTR4101P
SOT-23-HF
2
G
1
C3810
DS
0.01UF
10% 16V
CERM
402
3
12
PP3V3_ENET
6 7
17 22 31
D
WLAN Enable Generation
"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))
NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.
PM_WLAN_EN_L
C
Q3805
20 29
IN
20 35 40 41
IN
6
20 35 40 67 71
IN
SSM6N15FEAPE
AP_PWR_EN
SSM6N15FEAPE
SMC_ADAPTER_EN
PM_SLP_S3_L
SOT563
2
Q3805
SOT563
5
Pull-up is with power FET.
6
D
SG
1
AC_OR_S0_L
3
D
SG
4
6
1
OUT
D
S G
29
Q3801
SSM6N15FEAPE
SOT563
2
17 19 21 22 24 28 32 35
PP3V3_S5
6 7 36 42 52 62 66 67 68 69 71 82
R3842
Q3841
SSM6N15FEAPE
SOT563
69.8K
1/16W MF-LF
1
1%
402
2
P1V05ENET_EN_L
3
D
21 22 66
PP1V05_S5
6 7
1.05V ENET FET
C3840
0.1UF
20% 10V
CERM
R3840
100K
1 2
5% 1/16W MF-LF
402
P1V05ENET_SS
SSM6N15FEAPE
R3841
10K
1 2
1% 1/16W MF-LF
402
402
Q3841
SOT563
2
P1V05ENET_EN_L_RC
C
1
2
1
6
D
SG
1
1.8V Vgs
3
CRITICAL
D
Q3840
G
SI2312BDS
SOT23
S
2
PP1V05_ENET
1
C3841
0.01UF
10% 16V
2
CERM 402
6 7
17 22 31
5
SG
PM_SLP_RMGT_L
8
20 32
B
IN
Non-ARB:
Recommend aliasing PM_SLP_RMGT_L and =P1V05ENET_EN. Nets separated on ARB for alternate power options.
RTL8211 25MHz Clock
NOTE: MCP79 can provide 25MHz clock, but clock runs whenever RMGT rails are powered.
A
Designs must ensure PHY is powered whenever RMGT rails are, or use separate crystal.
R3895
MCP_CLK25M_BUF0_R
17 79
IN
PLACEMENT_NOTE=Place close to U1400
1 2
1/16W MF-LF
4
22
RTL8211_CLK25M_CKXTAL1
5%
402
B
Ethernet & AirPort Support
SHT
32 83
SYNC_DATE=02/05/2009
REV.
A
OF
A
SYNC_MASTER=K19_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
31 79
OUT
APPLE INC.
AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
D
SCALE
051-7903
NONE
8
7 6
5
4
3
2
1
8 7
Page Notes
Power aliases required by this page: (NONE)
Signal aliases required by this page: (NONE)
BOM options provided by this page: (NONE)
6
5
4
3
D
Place one of 0.1uf cap close to each centertap pin of transformer
D
ENETCONN_CTAP
1
C3900
0.1UF
10% 16V
2
X5R 402
1
C3902
0.1UF
10% 16V
2
X5R 402
1
C3904
0.1UF
10% 16V
2
X5R 402
1
C3906
0.1UF
10% 16V
2
X5R 402
CRITICAL
T3900
ENET_MDI_P<0>
31 79
BI
ENET_MDI_N<0>
31 79
BI
C
ENET_MDI_N<1>
31 79
BI
ENET_MDI_P<1>
31 79
BI
ENET_MDI_N<2>
31 79
BI
ENET_MDI_P<2>
31 79
BI
ENET_MDI_N<3>
31 79
BI
ENET_MDI_P<3>
31 79
BI
Transformers should be mirrored on opposite
B
CRITICAL
1
C3910
10PF
5% 50V
2
CERM 402-1
1
2
CRITICAL
1
C3911
10PF
5% 50V
2
CERM 402-1
CRITICAL
C3920
10PF
5% 50V CERM 402-1
CRITICAL
1
2
C3921
10PF
5% 50V CERM 402-1
CRITICAL
1
C3930
10PF
5% 50V
2
CERM 402-1
CRITICAL
1
2
C3931
10PF
5% 50V CERM 402-1
1
2
sides of the board
CRITICAL
C3940
10PF
5% 50V CERM 402-1
CRITICAL
1
C3941
10PF
5% 50V
2
CERM 402-1
1
2
3
4
5
6 7
1
2
3
4
5
6 7
SM
TX
TLA-6T213HF
RX
CRITICAL
T3901
SM
TX
TLA-6T213HF
RX
12
82
ENETCONN_P<0>
11
82
ENETCONN_N<0>
10
ENET_CTAP0
9
ENET_CTAP1
8
82
ENETCONN_N<1> ENETCONN_P<1>
82
12
ENETCONN_N<2>
82
11
ENETCONN_P<2>
82
10
ENET_CTAP2
9
ENET_CTAP3
8
ENETCONN_N<3>
82
ENETCONN_P<3>
82
R3900
75
5% 1/16W MF-LF
402
1
R3901
1/16W MF-LF
2
75
402
CRITICAL
J3900
RJ45-M97-3
F-RT-TH
9
10
1 2 3 4 5 6 7 8
11 12
C
514-0636
1
1
R3902
75
5%
5% 1/16W MF-LF 402
2
2
1
R3903
75
5% 1/16W MF-LF 402
2
ENET_BOB_SMITH_CAP
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm
CRITICAL
C3908
1000PF
1 2
10%
2KV CERM 1206
B
PLACEMENT_NOTE=Place on MDI lines so there are no stubs all 8 caps.
PLACEMENT_NOTE=Place on MDI lines so there are no stubs all 8 caps.
PLACEMENT_NOTE=Place on MDI lines so there are no stubs all 8 caps.
PLACEMENT_NOTE=Place on MDI lines so there are no stubs all 8 caps.
PLACEMENT_NOTE=Place on MDI lines so there are no stubs all 8 caps.
PLACEMENT_NOTE=Place on MDI lines so there are no stubs all 8 caps.
PLACEMENT_NOTE=Place on MDI lines so there are no stubs all 8 caps.
PLACEMENT_NOTE=Place on MDI lines so there are no stubs all 8 caps.
Ethernet Connector
A
SYNC_MASTER=K19_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
D
APPLE INC.
8
7 6
5
4
3
2
SCALE
NONE
SYNC_DATE=03/13/2009
051-7903
SHT
OF
33
1
A
REV.
A
83
8 7
6
5
4
3
7 mA I/O
1
C4120
1UF
10%
6.3V 2
CERM
402
D
PART NUMBER
114S0556
QTY
1
DESCRIPTION
RES,549mOHM,1%,1/16W,0402
REFERENCE DES
R4100
CRITICAL
CRITICAL
BOM OPTION
OMIT
PP1V05_FW
7
35
135 mA
R4100
0.2
1 2
1% 1/16W MF-LF
402
PP1V0_FW_R
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.0V
L4110
120-OHM-0.3A-EMI
1 2
0402-LF
PP1V0_FW_FWPHY_AVDD
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.0V
25 mA PCIe SerDes
1
C4110
1UF
10%
6.3V
2
CERM 402
1
C4111
1UF
10%
6.3V
2
CERM 402
110 mA Digital Core
1
C4100
1UF
10%
6.3V
2
CERM 402
1
C4101
1UF
10%
6.3V
2
CERM 402
1
C4102
1UF
10%
6.3V
2
CERM 402
1
C4103
1UF
10%
6.3V
2
CERM 402
1
C4104
1UF
10%
6.3V
2
CERM 402
1
C4105
1UF
10%
6.3V
2
CERM 402
1
C4106
1UF
10%
6.3V
2
CERM 402
C4121
1UF
6.3V CERM
C4130
1UF
6.3V CERM
1
C4122
10%
402
1UF
10%
6.3V
2
CERM
402
114 mA FireWire PHY
1
C4131
10%
402
1UF
10%
6.3V
2
CERM
402
17 mA PCIe SerDes
C4135
1UF
10%
6.3V CERM
402
1
C4123
1UF
10%
6.3V
2
CERM
402
1
C4132
1UF
10%
6.3V
2
CERM
402
1
C4136
1UF
10%
6.3V
2
CERM
402
0 mA VReg PWR
1
C4141
0.1UF
20% 10V
2
CERM
402
1
C4124
2
PP3V3_FW_FWPHY_VDDA
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V
1
2
PP3V3_FW_FWPHY_VP25
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V
1
2
1
2
1UF
10%
6.3V CERM
402
C4140
1UF
10%
6.3V CERM 402
1
2
L4130
120-OHM-0.3A-EMI
1 2
0402-LF
L4135
120-OHM-0.3A-EMI
1 2
0402-LF
C
A1
B1
B12
C13E2E10H2H12K2L1
B13
ATBUSB
NC
A13
ATBUSH
NC
A11
ATBUSN
NC
FWPHY_DS0
36
IN
FWPHY_DS1
36
IN
FWPHY_DS2
36
IN
NC_FW0_TPAN
36 80
BI
NC_FW0_TPAP
36 80
BI
FW_PORT1_TPA_N
36 80
BI
FW_PORT1_TPA_P
36 80
BI
NC_FW2_TPAN
36
BI
NC_FW2_TPAP
36
BI
NC_FW0_TPBN
36 80
BI
NC_FW0_TPBP
36 80
BI
FW_PORT1_TPB_N
36 80
BI
FW_PORT1_TPB_P
36 80
BI
NC_FW2_TPBN
36
PPVP_FW_CPS
36
1
R4160
B
C4150
22PF
1 2
5%
50V
CERM
402
C4151
22PF
1 2
5%
50V
CERM
402
1 3
2 4
NC NC
FW_CLK24P576M_XO
CRITICAL
Y4150
24.576MHZ
SM-3.2X2.5MM
R4150
412
1 2
1% 1/16W MF-LF
402
200K
1% 1/16W MF-LF
402
2
R4161
2.94K
1/16W MF-LF
402
R4162
470K
1/16W MF-LF
402
1
1
R4170
191
1%
1%
1/16W MF-LF 402
2
2
1
1
C4162
0.33UF
5%
10%
6.3V
2
CERM-X5R 402
2
BI
NC_FW2_TPBP
36
BI
NC_FW0_TPBIAS
36
BI
FW_P1_TPBIAS
35 36
BI
NC_FW2_TPBIAS
36
BI
FW643_R0 FW643_TPCPS
TP_FW643_NAND_TREE FW643_REXT FW_CLK24P576M_XO_R FW_CLK24P576M_XI
TP_FW643_SE TP_FW643_SM TP_FW643_MODE_A TP_FW643_CE TP_FW643_FW620_L TP_FW643_JASI_EN TP_FW643_AVREG TP_FW643_VBUF FW643_PU_RST_L
TP_FW643_OCR10_CTL
F12
DS0
(IPD) NT-2
E12
(IPD) NT-3
DS1
E13
DS2
(IPD) NT-4
B8
TPA0N
A8
TPA0P
B5
TPA1N
A5
TPA1P
B3
TPA2N
A3
TPA2P
B9
TPB0N
A9
TPB0P
B6
TPB1N
A6
TPB1P
B4
TPB2N
A4
TPB2P
B7
TPBIAS0
C3
TPBIAS1
A2
TPBIAS2
B11
R0
B10
TPCPS
K1
NAND_TREE
L8
REXT
F13
XO
G13
XI
NT-9
M13
(IPD)
SE
N13
(IPD)
SM
J2
MODE_A
L13
CE
(IPD)
D12
FW620*
D1
JASI_EN
A10
AVREG
H13
VBUF
K13
FW_RESET*
J12
OCR_CTL_V10
J13
OCR_CTL_V12
NC
B2
VDD10
NT-OUT
NOTE: NT-xx notes show NAND tree order.
(IPD) NT-1
(IPU)
(IPD) NT-11
(IPU) NT-8
(Reserved)
D4
E4E5E9F4F6
D10
M12N3N11
MISCELLANEOUS
F7
F8
F10
C1
C12F1G12J1L3
1394 PHY
G4G6G7
VDD33
OMIT
CRITICAL
U4100
FW643E
BGA
VSS
G8
H4
G10
H6D7H7
L11M2A12D5D6D8L5
VDDH
PCI EXPRESS PHY
TEST CONTROLLER
FIXME!!! - TYPO IN SYMBOL REGCTL
POWER MANAGEMENT
SCIF
L10L6L9
VP
NT-12 (IPD)
NT-13
VP25
NT-10 (IPD)
NT-16 (IPD) NT-14 (IPD)
NT-15 (IPD)
SERIAL EEPROM CONTROLLER
CHIP RESET
H8
J4J5J9
H10
K4K5K7D9K8K9L7
J10
K12
VREG_PWR
PCIE_RXD0N PCIE_RXD0P PCIE_TXD0N PCIE_TXD0P
NT-21 (IPU) NT-20 (IPU)
(IPU)
NT-18 (IPU)
NT-19 (IPU)
(OD)
VAUX_DETECT
VAUX_DISABLE
(OD)
NT-17
NT-7 NT-6
NT-5
VREG_VSS
K6
K10
REFCLKN REFCLKP
TRST*
WAKE*
REGCLT
CLKREQN
SCIFCLK SCIFDAIN SCIFDOUT
SCIFMC
PERST*
L12
TCK TDI TDO TMS
SCL SDA
N8 N7 N5 N6
N9 N10
M4 N2 M1 M3
N1
C2 D13 E1 D2 L2
G2 G1 H1 F2
N12 M11
N4
77
PCIE_FW_R2D_N PCIE_FW_R2D_P
77
77
PCIE_FW_D2R_C_N
77
PCIE_FW_D2R_C_P
PCIE_CLK100M_FW_N PCIE_CLK100M_FW_P
TP_FW643_TCK TP_FW643_TDI TP_FW643_TDO TP_FW643_TMS
FW643_TRST_L
FW643_WAKE_L FW643_REGCTL FW643_VAUX_DETECT TP_FW643_VAUX_ENABLE FW_CLKREQ_PHY_L
TP_FW643_SCIFCLK TP_FW643_SCIFDAIN TP_FW643_SCIFDOUT TP_FW643_SCIFMC
FW643_SCL TP_FW643_SDA
FW_RESET_L
1
R4163
10K
5% 1/16W MF-LF 402
2
16 77
IN
16 77
IN
8
OUT
35
OUT
35
IN
A
PP3V3_FW
PLACEMENT_NOTE=Place C4170 close to U1400 PLACEMENT_NOTE=Place C4171 close to U1400
C4170 C4171
C4175 C4176
1 2
0.1UF
1 2
0.1UF
1 2
0.1UF
1 2
0.1UF
PLACEMENT_NOTE=Place C4175 close to U4100 PLACEMENT_NOTE=Place C4176 close to U4100
FW643_LDO
R4165
35
1
R4164
10K
5% 1/16W MF-LF 402
2
FireWire LLC/PHY (FW643E)
SYNC_MASTER=T18_MLB
APPLE INC.
7
138 mA
1/16W MF-LF
34 35 36
PCIE_FW_R2D_C_N
16V X5R 40210%
PCIE_FW_R2D_C_P
16V X5R 402
10%
PCIE_FW_D2R_N
16V X5R 402
10%
PCIE_FW_D2R_P
16V X5R 40210%
PP3V3_FW
1
1
10K
R4166
10K
5%
5% 1/16W
402
MF-LF 402
2
2
NOTE: FW_PME_L and FW_CLKREQ_L are isolated for systems that use 1394B physical plug detect.
WITH PLUG DETECT:
- Gate CLKREQ# based on PHY power
- TP (or NC) PME# WITHOUT PLUG DETECT:
- Alias both signals to drop = prefix
16 77
IN
16 77
IN
16 77
OUT
16 77
OUT
7
34 35 36
SYNC_DATE=02/05/2009
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
D
SCALE
NONE
051-7903
SHT
D
C
B
A
REV.
A
OF
8334
8
7 6
5
4
3
2
1
8 7
Page Notes
Power aliases required by this page:
- =PPBUS_S5_FWPWRSW (system supply for bus power)
- =PP3V3_FW_LATEVG_ACTIVE
- =PPVP_FW_SUMNODE (power passthru summation node)
Signal aliases required by this page: (NONE)
BOM options provided by this page:
D
PP3V3_FW
7 34 35 36
R4277
10K
5% 1/16W MF-LF
402
FW643_WAKE_L
8 34
C
1
2
CRITICAL
G
2
1
R4276
100K
5% 1/16W MF-LF 402
2
FW_WAKE
6 D
Q4276
DMB53D0UV
SOT-563
S 1
NOSTUFF
1
C4276
0.1UF
10% 16V
2
X5R 402
5
66 67 68 69 71 82
PP3V3_S5
28 32 35 36 42 52 62
FW_PLUG_DET_L
3
CRITICAL
Q4276
DMB53D0UV
SOT-563
4
R4295
Q4293
SSM6N15FEAPE
SOT563
10K
1/16W MF-LF
5%
402
8 18 35
PP3V3_FW
7 34 35 36
1
2
P1V05_FW_EN_L
3
D
18 35
FW_PWR_EN
IN
57 58 61 66 67 68 69 71 72
PP3V3_S0
6 7 12 17 18 20 21 22 23 26 27 35 37 41 43 45 46 47 49 53 82
R4296
1 2
6
SSM6N15FEAPE
SSM6N15FEAPE
100K
5% 1/16W MF-LF
402
R4290
1/16W MF-LF
Q4290
SOT563
5
PP1V05_S0
6 7 9 10 11 12 13 16 17 19 21 22 23 35 61 65 66 67
R4297
220K
1 2
5% 1/16W MF-LF
402
Q4293
D
SOT563
2
SG
P1V05_FW_EN_L_RC
10K
402
5%
D
SG
3.3V FW FET
1
2
P3V3FW_EN_L
3
4
@ 2.5V Vgs:
1.05V FW FET
1
C4296
0.1UF
20% 10V
2
CERM
402
P1V05FW_SS
6
1
1
NOSTUFF
1
C4295
0.068UF
10% 10V
2
CERM 402
5
Rds(on) = 90mOhm max I(max) = 1.7A (85C)
R4291
100K
1 2
5% 1/16W MF-LF
402
3
CRITICAL
D
Q4295
G
SI2312BDS
SOT23
S
2
PP1V05_FW
1
C4290
0.033UF
10% 16V
2
X5R 402
P3V3FW_SS
7 34 35
CRITICAL
Q4291
NTR4101P
SOT-23-HF
2
G
1
C4291
0.01UF
SSM6N15FEAPE
FW_PWR_EN
18 35 6 7 17 19 21 22 24
FW_CLKREQ_PHY_L
34 35
IN
DS
10% 16V
CERM
402
3
12
Q4264
SOT563
4
PP3V3_FW
D
5
SG
3
4
SSM6N15FEAPE
35 34
FW_CLKREQ_PHY_L
MAKE_BASE=TRUE
7 34 35 36
PCIE_FW_PRSNT_L
MAKE_BASE=TRUE
6
SOT563
D
2
SG
Q4264
8 16
OUT
FW_CLKREQ_L
1
3
PP1V05_FW
7 34 35
C4281
16
OUT
FireWire Port Power Switch
1UF
6.3V CERM
57 58 61 66 67 68 69 71 72
10%
402
PP3V3_S0
6 7 12 17 18 20 21 22 23 26 27 35 37 41 43 45 46 47 49 53 82
P1V0_FW_RC
1
2
CRITICAL
2
2 1
1
R4281
100K
R4280
10K
1 2
1% 1/16W MF-LF
402
P1V0_RESET_GATE
G
6 D
S 1
Q4299
DMB53D0UV
SOT-563
5% 1/16W MF-LF 402
2
CRITICAL
3
Q4299
5
DMB53D0UV
SOT-563
4
PP1V05_FW PGOOD/FW_RESET_L
R4283
10K
1 2
5% 1/16W MF-LF
402
FW_RESET_L
PCIE_RESET_L
OUT
D
16 24
IN
34
C
5
SG
4
2
V+
V-
5
R4210
200K
1 2
1% 1/16W MF-LF
402
4
U4210
LMC7211
SM-HF
1
C4210
0.1UF
20% 10V
2
CERM 402
1
LATEVG_EVENT
FWLATEVG Hysteresis:
3.08V when port power is on
2.91V when late Vg event and port power is off
E
5
BD
6 4
CRITICAL
Q4262
DMB54D0UV
SOT-563
Q2
CRITICAL
Q4260
NDS9407
SOI-HF
3 2
1
R4260
470K
5% 1/16W MF-LF 402
2
3
C
21
GS
Q1
Q4261
SMC_ADAPTER_EN
20 32 40
IN
41
PM_SLP_S3_L
6 20 32 40 67 71
IN
Enables port power when machine is running or on AC.
SSM6N15FEAPE
SOT563
2
FWPWR_EN_L_DIV
1
R4261
330K
5% 1/16W MF-LF 402
2
FWPWR_EN_L
6
D
SSM6N15FEAPE
SG
1
C4260
Q4261
SOT563
0.1UF
5
18 35
34 36
10% 25V X5R 402
D
SG
IN
IN
1
1
2
PP1V05_S0
6 7 9 10 11 12 13 16 17 19 21 22 23 35 61 65 66 67
3
4
FW_PWR_EN
FW_P1_TPBIAS
FW_PWR_EN_L
4
CRITICAL
G
2
8
PPBUS_FW_FWPWRSW_F
MIN_LINE_WIDTH=0.5 mm
7
MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V
6 5
1
R4275
1K
5% 1/16W MF-LF 402
2
FW_P1_TPBIAS_R
6
D
Q4275
DMB53D0UV
SOT-563
S
1
CRITICAL
Q4270
BC847CDXV6TXG
SOT563
1
R4270
330K
5% 1/16W MF-LF 402
2
3
4
1
R4272
1K
5% 1/16W MF-LF 402
2
CRITICAL
F4260
1.1A-24V
1 2
MINISMDC110H24
FW_DET_MIRROR
5
FW_DET_EMIT
PPBUS_FW_FWPWRSW_D
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V
1
R4271
56K
5% 1/16W MF-LF 402
2
FW_PLUG_DET
CRITICAL
6
Q4270
2
BC847CDXV6TXG SOT563
1
1
R4273
12K
5% 1/16W MF-LF 402
2
CRITICAL
D4260
SM
1 2
CRS08-1.5A-30V
PPVP_FW
PP3V3_S0
5
1
C4270
0.1UF
10% 16V
2
X5R 402
FireWire Port Power
SYNC_MASTER=K19_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
APPLE INC.
1
R4274
100K
5%
1/16W
MF-LF 402
2
FW_PLUG_DET_L
CRITICAL
3
Q4275
DMB53D0UV
SOT-563
4
DRAWING NUMBER
SIZE
D
SCALE
051-7903
NONE
7 36
OUT
SHT OF
53 57 58 61 66 67 68 69 71 72 6 7 12 17 18 20 21 22 23 26 27 35 37 41 43 45 46 47 49 82
8 18 35
SYNC_DATE=03/18/2009
REV.
A
8335
B
A
FW_PWR_EN
18 35
PPBUS_G3H
6 7 44 45 59 60 62 63 64 73
Late-VG Event Detection
B
NOSTUFF
R4263
100
10K
50V 402
402
5%
1
5%
2
1
2
1 2
1% 1/16W MF-LF
402
1
R4212
10K
1% 1/16W MF-LF 402
2
FWLATEGV_3V_REF
P2V4_FWLATEVG_RC
1
R4213
80.6K
1% 1/16W MF-LF 402
2
LATEVG_RETRY_RC
NOSTUFF
1
C4263
1UF
10% 10V
2
X5R
402-1
69 71 82 35 36 42 52
PP3V3_S5
6 7 17 19 21 22 24 28 32 62 66 67 68
PP2V4_FW_LATEVG
R4211
1/16W MF-LF
A
C4211
100pF
CERM
R4265
10K
5% 1/16W MF-LF
402
12
LATEVG_FAULT_EVENT_PNP
LATEVG_FAULT_EVENT
3
8
7 6
5
4
3
2
1
8 7
Page Notes
Power aliases required by this page:
- =PPVP_FW_PORT1
- =PP3V3_FW_LATEVG
- =GND_CHASSIS_FW_PORT1
- =GND_CHASSIS_FW_EMI_R
Signal aliases required by this page: (NONE)
D
NOTE: This page is expected to contain the necessary aliases to map the FireWire TPA/TPB pairs to their appropriate connectors and/or to properly terminate unused signals.
BOM options provided by this page: (NONE)
NOTE: FireWire TPA/TPB pairs are NOT constrained on this page. It is assumed that FireWire PHY page will provide the appropriate constraints to apply to entire TPA/TPB XNets.
1394b implementation based on Apple FireWire Design Guide (FWDG 0.6, 5/14/03)
FW_P1_TPBIAS
34 35
C
FW_PORT1_TPA_P
34 36 80
FW_PORT1_TPA_N
34 36 80
FW_PORT1_TPB_P
34 36 80
FW_PORT1_TPB_N
34 36 80
B
Termination
Place close to FireWire PHY
TI PHYs require 1uF even though FW spec calls out 0.33uF
1
C4360
0.33UF
10%
6.3V
2
CERM-X5R 402
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
1
R4360
56.2
1% 1/16W MF-LF 402
2
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
1
R4362
56.2
1% 1/16W MF-LF 402
2
FW_PORT1_TPB_C
1
C4364
220pF
5% 25V
2
CERM 402
R4361
56.2
1/16W MF-LF
402
R4363
56.2
1/16W MF-LF
402
R4364
4.99K
1/16W MF-LF
402
1
1%
2
1
1%
2
1
1%
2
Configures PHY for:
- 1-port Portable Power Class (0)
- Port "1" Bilingual (1394B)
FW_PORT1_TPA_P
MAKE_BASE=TRUE
FW_PORT1_TPA_N
MAKE_BASE=TRUE
FW_PORT1_TPB_P
MAKE_BASE=TRUE
FW_PORT1_TPB_N
MAKE_BASE=TRUE
6
FireWire PHY Config Straps
SOT-363
BSS8402DW
Q4300
(SYM-VER2)
PPVP_FW
7
34 36 80
34 36 80
34 36 80
34 36 80
35 36
1
R4311
470K
5% 1/16W MF-LF
402
2
CPS_EN_L_DIV
1
R4312
330K
5% 1/16W MF-LF
402
2
CPS_EN_L
PP3V3_FW
7
34 35 36 34 36 80
SGD
5
6
D
S
(SYM-VER1)
1
3
Q4300
BSS8402DW
SOT-363
4
G
2
5
PP3V3_FW
7
34 35 36
PPVP_FW_CPS
34 36
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=12.6V
R4382
MAKE_BASE=TRUE
10K
1/16W MF-LF
1%
402
1
2
R4381
PPVP_FW_CPS
1
R4380
10K
1% 1/16W MF-LF
402
2
34 36
34 36
FWPHY_DS1
34 36
MAKE_BASE=TRUE
1
10K
1% 1/16W MF-LF
402
2
NC_FW0_TPBIAS
34 36
NC_FW2_TPBIAS
34 36
NC_FW0_TPAN
34 36 80
NC_FW0_TPAP
34 36 80
NC_FW2_TPAN
34 36
NC_FW2_TPAP
34 36
NC_FW0_TPBN
34 36 80
NC_FW0_TPBP
34 36 80
NC_FW2_TPBN
34 36
NC_FW2_TPBP NC_FW2_TPBP
34 36 34 36
"Snapback" & "Late VG" Protection
PP2V4_FW_LATEVG
35 36
BAV99DW-X-G
1
C4310
0.01uF
10% 50V
2
X7R 402
FW_PORT1_TPB_N
FW_PORT1_TPB_P
34 36 80
FW_PORT1_TPA_N
34 36 80
FW_PORT1_TPA_P
34 36 80
BAV99DW-X-G
1
C4312
0.01uF
10% 50V
2
X7R 402
4
FWPHY_DS0
MAKE_BASE=TRUE
FWPHY_DS2
MAKE_BASE=TRUE
34 36
C4311
0.01uF
CRITICAL
DP4310
SOT-363
2
1
CRITICAL
DP4311
SOT-363
2
1
C4313
0.01uF
NC_FW0_TPBN NC_FW0_TPBP NC_FW2_TPBN
1
10% 50V
2
X7R 402
6
6
1
10% 50V
2
X7R 402
3
FWPHY_DS0
FWPHY_DS2
FWPHY_DS1
NC_FW0_TPBIAS NC_FW2_TPBIAS NC_FW0_TPAN NC_FW0_TPAP NC_FW2_TPAN NC_FW2_TPAP
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
CRITICAL
DP4310
BAV99DW-X-G
SOT-363
5
4
CRITICAL
DP4311
BAV99DW-X-G
SOT-363
5
4
PLACEMENT_NOTE=Place C4319 close to connector pin 5.
Cable Power
PPVP_FW
7
35 36
3
3
34 36
34 36
34 36
MAKE_BASE=TRUE
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
C4319
1
R4319
1M
5% 1/16W MF-LF 402
2
0.1uF
603-1
34 36
34 36
34 36 80
34 36 80
34 36
34 36
34 36 80
34 36 80
34 36
CRITICAL
L4310
FERR-250-OHM
1 2
SM
1
C4314
0.01UF
10% 50V
2
X7R 402
1
10% 50V
2
X7R
AREF needs to be isolated from all local grounds per 1394b spec
When a bilingual device is connected to a beta-only device, there is no DC path between them (to avoid ground offset issue)
BREF should be hard-connected to logic ground for speed signaling and connection
Note: Trace PPVP_FW_PORT1 must handle up to 5A
PPVP_FW_PORT1_F
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=33V
PORT 1
BILINGUAL
CRITICAL
J4310
1394B-M97
F-RT-TH
TPB-
1
(FW_PORT1_BREF)
(GND_FW_PORT1_VG)
FW_PORT1_AREF
9 2 8 7
NC
6
TPA-
3 5
TPA+
4
10 11 12 13
TPB­TPB<R>
TPB+ VP
NC
VG TPA-
TPA<R>
TPA+
CHASSIS
GND
TPB(R)
SC/NC
TPA(R)
VPTPB+
VG
514S0605
D
C
OUTPUT
B
INPUT
Late-VG Protection Power
PP3V3_S5
6 7
A
PP2V4_FWLATEVG needs to be biased to at least 2.1V for FW signal integrity and should be biased to 2.4V for margin R4390 should be 390 Ohms max for a 3.3V rail
8
17 19 21 22 24 28 32 35
42 52 62 66 67 68 69 71 82
7 6
R4390
332
1 2
1% 1/16W MF-LF
402
PP2V4_FW_LATEVG
MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=2.4V
CRITICAL
3
D4390
MMBZ5227BLT1H
SOT23
1
35 36
ESD and late-VG rail for snap-back diodes (Common to all ports)
5
4
3
SYNC_MASTER=K19_MLB
APPLE INC.
2
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
FireWire Ports
SYNC_DATE=02/05/2009
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SIZE
D
SCALE
NONE
051-7903
SHT
36 83
1
A
REV.
A
OF
8 7
6
5
4
3
ODD Power Control
CRITICAL
Q4590
TPCP8102
PP5V_S3
6 7 8
29 37 38 39 41 49 51 53
62 63 68
D
NOTE: 3.3V must be S0 if 5V is S3 or S5 to ensure the drive is unpowered in S3/S5.
20
IN
57 58 61 66 67 68 69 71 72
PP3V3_S0
6 7
12 17 18 20 21 22 23 26
27 35 37 41 43 45 46 47 49 53 82
SSM6N15FEAPE
ODD_PWR_EN_L
R4597
Q4596
SOT563
5
100K
1/16W MF-LF
5%
402
1
2
ODD_PWR_EN
3
D
SG
4
Q4596
SSM6N15FEAPE
SOT563
R4596
100K
1/16W MF-LF
2
1
5%
402
2
ODD_PWR_EN_LS5V_L
6
D
SG
1
R4595
100K
1 2
5% 1/16W MF-LF
402
1
C4595
0.068UF
10% 10V
2
CERM 402
ODD_PWR_SS
23V1K-SM
S
G
4
C4596
0.01UF
D
1 2
10% 16V
CERM
402
1 2 3
PP5V_SW_ODD_R
MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.4mm VOLTAGE=5V
5 6 7 8
PP5V_SW_ODD
6
51
MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.4mm VOLTAGE=5V
XW4503
SM
1 2
XW4504
SM
1 2
XW4505
SM
1 2
ISNS_ODD_P
ISNS_ODD_N
D
51 82
OUT
51 82
OUT
C
C
SATA ODD Port
FL4520
90-OHM-100MA
DLP11S
SYM_VER-1
CRITICAL
57 58 61 66 67 68 69 71 72
PP3V3_S0
6 7
12 17 18 20 21 22 23 26
27 35 37 41 43 45 46 47 49 53 82
SMC_ODD_DETECT
6
40
OUT
Indicates disc presence
R4590
33K
1/16W MF-LF
402
3 4
J4500
CRITICAL
1
5%
2
54722-0164
F-ST-SM 1 3 4 5 6 7 8 9
11 12 13 14 15 16
516S0616
2
10
SATA_ODD_R2D_P
6
77
SATA_ODD_R2D_N
6
77
SATA_ODD_D2R_C_N SATA_ODD_D2R_C_P
PLACEMENT_NOTE=Place FL4520 close to J4500
PLACEMENT_NOTE=PLACE C4526 CLOSE TO J4500 PLACEMENT_NOTE=PLACE C4525 NEXT TO C4526
C4526
1 2
0.01UF
C4525
1 2
0.01UF
SATA_ODD_R2D_UF_P
82
12
SATA_ODD_R2D_UF_N
82
SATA_ODD_D2R_UF_N
6
82
CERM
10% 16V
SATA_ODD_D2R_UF_P
6
82
CERM
402
40210% 16V
B
1
C4501
OUT
C4531
0.001UF
10% 50V CERM 402
6
2
39
402
0.1UF
20% 10V CERM 402
R4531
4.7
5%
MF-LF
CRITICAL
L4500
FERR-70-OHM-4A
1 2
0603
CRITICAL
FL4501
90-OHM-100MA
3 4
PLACEMENT_NOTE=Place FL4501 close to J4501
C4515
0.01UF
C4516
0.01UF
PLACEMENT_NOTE=Place C4515 next to C4516 PLACEMENT_NOTE=Place C4516 close to J4501
12
SYS_LED_ANODE
1/16W
L4502
FERR-220-OHM
PP1V5_S0
6 7
10 11 15 22 66 67 68
82
A
29 37 38 39 41 49 51 53
1 2
1
C4503
1UF
10%
6.3V
2
CERM 402
PLACEMENT_NOTE=PLACE C4503 CLOSE TO J4501
PP5V_S3
6 7 8 62 63 68
0402
402
25 40 43 81
IN
25 40 43 81
BI
R4532
10
5%
MF-LF
12
1/16W
PP1V5_S0_HDD_FLT
VOLTAGE=1.5V MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.3mm
SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA
21 22 19 17 18 15 16 13 14 11 12
9 7 8 5 6
PP5V_S3_IR_R
6 6
1
C4532
0.1UF
10%
2
16V X7R-CERM 402
516S0687
3 4 1
F-ST-SM
54722-0224
J4501
20
10
2
MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.4mm VOLTAGE=5V
PP5V_S0_HDD_FLT
6
PLACEMENT_NOTE=PLACE L4500 CLOSE TO J4501
6
77
SATA_HDD_R2D_P SATA_HDD_R2D_N
6
77
SATA_HDD_D2R_C_N
6
77
SATA_HDD_D2R_C_P
6
77
IR_RX_OUT SYS_LED_ANODE_R
1
2
DLP11S
SYM_VER-1
1 2
1 2
1
C4502
0.1UF
20% 10V
2
CERM 402
12
41
PLACEMENT_NOTE=PLACE C4501 CLOSE TO J4501 PLACEMENT_NOTE=PLACE C4502 CLOSE TO J4501
PP5V_S0_HDD_R
MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.4mm VOLTAGE=5V
SATA_HDD_R2D_UF_P
82
SATA_HDD_R2D_UF_N
82
SATA_HDD_D2R_UF_N
82
CERM
40210% 16V
SATA_HDD_D2R_UF_P
82
CERM
40210% 16V
PLACEMENT_NOTE=PLACE C4520 CLOSE TO MCP79 PLACEMENT_NOTE=PLACE C4521 NEXT TO C4520
0.01UF
0.01UF
C4521
1 2
1 2
CERM
C4520
CERM
FL4525
90-OHM-100MA
DLP11S
SYM_VER-1
1 2
PLACEMENT_NOTE=Place FL4525 close to J4500
40210% 16V
40210% 16V
CRITICAL
34
SATA_ODD_R2D_C_P
SATA_ODD_R2D_C_N
SATA_ODD_D2R_N
SATA_ODD_D2R_P
SATA HDD Port
PLACEMENT_NOTE=Place C4510 close to MCP79 PLACEMENT_NOTE=Place C4511 next to C4510
C4510
1 2
0.01UF
C4511
1 2
DLP11S
SYM_VER-1
CRITICAL
0.01UF
34
FL4502
90-OHM-100MA
1 2
PLACEMENT_NOTE=PLACE FL4502 CLOSE TO J4501
SATA_HDD_R2D_C_P
40210% 16V
CERM
SATA_HDD_R2D_C_N
40210% 16V
CERM
SATA_HDD_D2R_N
SATA_HDD_D2R_P
19 77
IN
19 77
IN
19 77
OUT
19 77
OUT
B
XW4500
SM
XW4501
SM
19 77
IN
19 77
IN
19
OUT
77
19 77
OUT
1 2
SM
1 2
1 2
SYNC_MASTER=K19_MLB
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
APPLE INC.
XW4502
ISNS_HDD_P ISNS_HDD_N
SATA Connectors
NOTICE OF PROPRIETARY PROPERTY
SIZE
D
SCALE
PP5V_S0
DRAWING NUMBER
051-7903
NONE
6 7
42 47 49 61 64 65 67 68
70 72
51 82
OUT
51 82
OUT
SYNC_DATE=03/23/2009
SHT
OF
8337
A
REV.
A
8
7 6
5
4
3
2
1
8 7
6
5
4
3
D
Port Power Switch
CRITICAL
Q4690
TPS2064DGN
PP5V_S3
6 7 8
C
PM_SLP_S4_L
6
20 40 41 67
29 37 39 41 49 51 53 62
C4692
0.47UF
10% 10V X5R 402
63 68
1
2
1
2
R4690
5.1K
5% 1/16W MF-LF 402
USB_PWR_EN
19
OUT
19
OUT
USB_EXTA_OC_L
USB_EXTB_OC_L
C4690
10UF
6.3V
20% X5R
603
1
1
C4691
0.1UF
20% 10V
2
2
CERM 402
2
IN
8
OC1*
3
EN1
5
OC2*
4
EN2
GND
1
MSOP
TPAD
9
OUT1
OUT2
7
6
C4695
10UF
6.3V
20% X5R
603
PP5V_S3_RTUSB_A_ILIM
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.375 mm VOLTAGE=5V
PP5V_S3_RTUSB_B_ILIM
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.375 mm VOLTAGE=5V
CRITICAL
1
1
C4696
100UF
20%
6.3V
2
2
POLY-TANT CASE-B2-SM
C4617
10UF
6.3V X5R 603
20%
1
2
CRITICAL
1
C4616
100UF
20%
6.3V
2
POLY-TANT CASE-B2-SM
C4605
82
USB2_EXTA_MUXED_N
82
USB2_EXTA_MUXED_P
0.01uF
CERM
20% 16V
402
1
2
Left USB Port A
CRITICAL
L4605
FERR-220-OHM-2.5A
1 2
0603
CRITICAL
L4600
90-OHM-100MA
DLP11S
SYM_VER-1
1 2
PP5V_S3_RTUSB_A_F
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.375 mm VOLTAGE=5V
34
USB2_LT1_N
82
USB2_LT1_P
82
CRITICAL
J4600
USB
F-RT-TH-M97-4
5 6
1 2 3 4
5 42 3
IOIONC
NC
6
VBUS
1
GND
7 8
D
C
514-0606
D4600
RCLAMP0502N
SLP1210N6
34
USB_LT2_N
82
CRITICAL
USB_LT2_P
6
VBUS
1
GND
RCLAMP0502N
Place L4600 and L4605 at connector pin
CRITICAL
J4610
F-RT-TH-M97-4
5 42 3
IOIONC
NC
D4610
SLP1210N6
CRITICAL
5 6
1 2 3 4
7 8
USB
External USB Connectors
SYNC_MASTER=K19_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
APPLE INC.
SCALE
D
NONE
DRAWING NUMBER
051-7903
SHT
38 83
SYNC_DATE=02/05/2009
REV.
A
OF
B
A
CRITICAL
L4615
FERR-220-OHM-2.5A
1 2
C4615
0.01uF
20% 16V CERM 402
0603
B
1
2
We can add protection to 5V if we want, but leaving NC for now
PP5V_S3_RTUSB_B_F
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.375 mm VOLTAGE=5V
USB/SMC Debug Mux
60 67
PP3V42_G3H
6 7
20 21 24 40
41 42 43 45 48 59
SMC_DEBUG_YES
C4650
0.1UF
20% 10V
CERM
40 41 42
40 41 42
19 78
19 78
IN OUT
BI BI
SMC_RX_L SMC_TX_L
USB_EXTA_P USB_EXTA_N
402
A
SMC_DEBUG_YES
1
2
5 4
7 6
8
SMC_DEBUG_NO
R4651
0
1 2
5% 1/16W MF-LF
402
SIGNAL_MODEL=USB_MUX
9
VCC
M+ M-
U4650
PI3USB102ZLE
TQFN
D+
CRITICAL
D-
GND
3
SMC_DEBUG_NO
R4652
1 2
1/16W MF-LF
402
1
R4650
10K
5% 1/16W MF-LF 402
1
Y+
2
Y-
10
SELOE*
2
USB_DEBUGPRT_EN_L
SEL=0 Choose SMC SEL=1 Choose USB
40
IN
19 78
BI
19 78
BI
USB_EXTB_N
USB_EXTB_P
Left USB Port B
0
5%
CRITICAL
L4610
90-OHM-100MA
DLP11S
SYM_VER-1
82
1 2
8
7 6
5
4
3
2
1
8 7
6
5
4
3
IR SUPPORT
D
19 78
BI
19 78
BI
C
PP5V_S3
6 7 8
29 37 38 41 49 51 53 62
63 68
DIFFERENTIAL_PAIR=USB2_IR DIFFERENTIAL_PAIR=USB2_IR
1
C4801
0.1UF
10% 16V
2
X7R-CERM 402
USB_IR_P USB_IR_N
IR_VREF_FILTER
1
C4803
1UF
10% 10V
2
X5R 402-1
CY7C63803-LQXC
12
P1.0/D+
13
P1.1/D-
15
P1.2/VREG
16
P1.3/SSEL
17
P1.4/SCLK
18
P1.5/SMOSI
19
P1.6/SMISO
8 9
10
P/N 338S0633
20
NC
21 22 23 24
THRML
14
VCC
U4800
QFN
CRITICAL
OMIT
25
P0.0
P0.1 INT0/P0.2 INT1/P0.3 INT2/P0.4 TIO0/P0.5 TIO1/P0.6
VSSPAD
11
7 6 5 4 3 2 1
IR_RX_OUT_RC
1
C4804
0.001UF
10% 50V
2
CERM 402
R4800
100
1 2
5% 1/16W MF-LF
402
IR_RX_OUT
6
37
IN
D
C
B
B
Front Flex Support
A
8
7 6
5
4
3
SYNC_MASTER=K19_MLB
APPLE INC.
2
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
D
SCALE
051-7903
NONE
SHT
39 83
1
SYNC_DATE=02/05/2009
REV.
A
OF
A
8 7
NOTE: Unused pins have "SMC_Pxx" names. Unused pins designed as outputs can be left floating, those designated as inputs require pull-ups.
D
TP_SMC_EXCARD_PWR_EN
41
OUT
TP_SMC_RSTGATE_L
41
OUT
ALL_SYS_PWRGD
24 62 64 65 66 67
IN
RSMRST_PWRGD
67
IN
PM_RSMRST_L
20
OUT
IMVP_VR_ON
61
OUT
PM_PWRBTN_L
20
OUT
TP_ESTARLDO_EN
41
OUT
TP_SMC_P24
41
SMC_BMON_MUX_SEL
41 45
LPC_AD<0>
18 42 78
BI
LPC_AD<1>
18 42 78
BI
LPC_AD<2>
18 42 78
BI
LPC_AD<3>
18 42 78
C
BI
LPC_FRAME_L
18 42 78
IN
SMC_LRESET_L
24
IN
LPC_CLK33M_SMC
24 78
IN
LPC_SERIRQ
18 42
BI
TP_SMC_P41
41
SMBUS_SMC_MGMT_SDA
25 37 43 81
BI
SMS_PWRDN
50
OUT
SMC_IG_THROTTLE_L
20 41
OUT
SMC_SYS_KBDLED
49
OUT
SMC_TX_L
38 40 41 42
OUT
SMC_RX_L
38 40 41 42
IN
SMBUS_SMC_0_S0_SCL
43 46 51 81
BI
(OC)
(OC)
6
B12
P10
A13
P11
A12
P12
B13
P13
D11
NC
NC NC NC
NC
NC
NC
NC NC
P14
C13
P15
C12
P16 P66
D10
P17
D13
P20
E11
P21
D12
P22
F11
P23
E13
P24
E12
P25
F13
P26
E10
P27
A9
P30
D9
P31
C8
P32
B7
P33
A8
P34
D8
P35
D7
P36
D6
P37
D4
P40
A5
P41
B4
P42
A1
P43
C2
P44
B2
P45
C1
P46
C3
P47
G2
P50
F3
P51
E4
P52
U4900
H8S2117
LGA-HF
(1 OF 3)
OMIT
P60 P61 P62 P63 P64 P65
P67
P70 P71 P72 P73 P74 P75 P76 P77
P80 P81 P82 P83 P84 P85 P86
P90 P91 P92 P93 P94 P95 P96 P97
L13 K12 K11 J12 K13 J10 J11 H12
N10 M11 L10 N11 N12 M13 N13 L12
A7 B6 C7 D5 A6 B5 C6
J4 G3 H2 G1 H4 G4 F4 F1
SMC_PM_G2_EN
NC NC NC
SMC_ADAPTER_EN
NC
SMC_PROCHOT_3_3_L SMC_BIL_BUTTON_L
SMC_CPU_ISENSE SMC_CPU_VSENSE TP_SMC_GPU_ISENSE TP_SMC_GPU_VSENSE SMC_DCIN_ISENSE SMC_PBUS_VSENSE SMC_BATT_ISENSE TP_SMC_CPU_HI_ISENSE
SMC_WAKE_SCI_L
NC
PM_CLKRUN_L LPC_PWRDWN_L SMC_TX_L SMC_RX_L SMBUS_SMC_MGMT_SCL
(OC)
SMC_ONOFF_L SMC_BC_ACOK SMC_BS_ALRT_L PM_SLP_S3_L PM_SLP_S4_L PM_SLP_S4_L PM_CLK32K_SUSCLK SMBUS_SMC_0_S0_SDA
(OC)
5
6
41
6 7
20 21 24 38 41 42 43 45
48 59 60 67
6 8
62 67
OUT
20 32 35 41
OUT
41
IN
6
41 59
IN
45
IN IN IN IN IN IN IN IN
OUT
OUT
IN
OUT
IN
BI
IN IN IN IN IN IN IN
BI
44
41
41
45
44
45
41
20
18 42
18 42
38 40 41 42
38 40 41 42
25 37 43 81
41 48
41 59 60
41
6
20 32 35 67 71
6
20 38 40 41 67
6
20 38 40 41 67
24 78
43 46 51 81
PLACEMENT_NOTE=Place R4999 close to U4900 pins N14,N15 PLACEMENT_NOTE=Place C4920 close to U4900 pins N14,N15
NOTE: P94 and P95 are shorted, P95 could be spare.
4
PP3V3_S5_AVREF_SMC PP3V42_G3H
1
C4902
22UF
20%
6.3V
2
CERM
805
1
C4903
0.1UF
20% 10V
2
CERM 402
R4999
4.7
1 2
5% 1/16W MF-LF
402
1
C4904
0.1UF
20% 10V
2
CERM 402
PP3V3_S5_SMC_AVCC
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V
41 42
IN
41
41
3
1
C4905
0.1UF
20% 10V
2
CERM 402
C4920
0.1UF
SMC_RESET_L SMC_XTAL
SMC_EXTAL
20% 10V
CERM
402
1
C4906
0.1UF
20% 10V
2
CERM 402
1
2
M12
B1M1H10
AVCC
U4900
H8S2117
LGA-HF
(3 OF 3)
D3
RES*
A3
XTAL
A2
EXTAL
VSS
D2
L3
F10
B11
OMIT
C5
L11
E1
VCLVCC
AVREF
ETRST
XW4900
SM
PLACEMENT_NOTE=Place C4907 close to U4900 pin F1
SMC_VCL
1
C4907
0.47UF
10%
6.3V 2
CERM-X5R
AVSS
MD1 MD2
NMI
402
E5
NC
NC
D1
SMC_KBC_MDE
H1
E3
H3
L9
1
R4902
10K
5% 1/16W MF-LF 402
12
2
GND_SMC_AVSS
R4909
10K
1/16W MF-LF
1
R4998
10K
5% 1/16W MF-LF 402
2
41 44 45
402
5%
1
2
1
R4901
10K
5% 1/16W MF-LF 402
2
SMC_MD1
SMC_NMI
SMC_TRST_L
NO STUFF
1
R4903
0
5% 1/16W MF-LF 402
2
D
42
IN
42
IN
42
IN
C
(DEBUG_SW_1) (DEBUG_SW_2)
B
A
SMC_PA0
41
SMC_PA1
41
PM_SYSRST_L
24
OUT
USB_DEBUGPRT_EN_L
38
OUT
MEM_EVENT_L
20 26 27
BI
SMC_PA5
41
SYS_ONEWIRE
59
BI
PM_BATLOW_L
20
OUT
SMC_RUNTIME_SCI_L
20
OUT
SMC_ODD_DETECT
6
37
IN
TP_SMC_PB3
41
SMC_EXCARD_CP
41
IN
SMC_EXCARD_OC_L
41
IN
SMC_GFX_OVERTEMP_L
41
IN
SMC_FAN_0_CTL
47
OUT
TP_SMC_FAN_1_CTL
41
OUT
NC_SMC_FAN_2_CTL
41
OUT
NC_SMC_FAN_3_CTL
41
OUT
SMC_FAN_0_TACH
47
IN
TP_SMC_FAN_1_TACH
41
IN
NC_SMC_FAN_2_TACH
41
IN
NC_SMC_FAN_3_TACH
41
IN
SMS_X_AXIS
50
IN
SMS_Y_AXIS
50
IN
SMS_Z_AXIS
50
IN
TP_SMC_GPU_1V8_ISENSE
41
IN
SMC_MCP_CORE_ISENSE
41 45
IN
SMC_MCP_DDR_ISENSE
41 45
IN
SMC_MCP_VSENSE
41 44
IN
SMC_CPU_FSB_ISENSE
41 45
IN
(See below)
(OC) (OC) (OC) (OC) (OC) (OC)
NC
NC
SMC_PB3: SMC_IG_THROTTLE_L for MG systems.
Otherwise, TP/NC okay (was ISENSE_CAL_EN)
A10 C10 B10 C11 A11
G11 G13 F12 H13 G10 G12 H11 J13
M10
K10
N3
PA0
N1
PA1
M3
PA2
M2
PA3
N2
PA4
L1
PA5
K3
PA6
L2
PA7
B8
PB0
C9
PB1
B9
PB2 PB3 PB4 PB5 PB6 PB7
PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7
PD0
N9
PD1 PD2
L8
PD3
M9
PD4
N8
PD5
K9
PD6
L7
PD7
U4900
H8S2117
LGA-HF
(2 OF 3)
OMIT
PE0 PE1 PE2 PE3 PE4 PF0
PF1 PF2 PF3 PF4 PF5 PF6 PF7
PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7
PH0 PH1 PH2 PH3 PH4 PH5
K1 J3 K2 J1 K4 K5
N5 M6 L5 M5 N4 L4 M4
M8 N7 K8 K7 K6 N6 M7 L6
E2 F2 J2 A4 B3 C4
SMC_CASE_OPEN SMC_TCK SMC_TDI SMC_TDO SMC_TMS
NC
SMC_SYS_LED SMC_LID
NC NC
SMC_MCP_SAFE_MODE
NC NC
NC
SMS_INT_L SMBUS_SMC_BSA_SDA
(OC)
SMBUS_SMC_BSA_SCL
(OC)
SMBUS_SMC_A_S3_SDA
(OC)
SMBUS_SMC_A_S3_SCL
(OC)
SMBUS_SMC_B_S0_SDA
(OC)
SMBUS_SMC_B_S0_SCL
(OC)
SMC_PROCHOT SMC_THRMTRIP SMC_PH2 TP_ALS_GAIN
NC NC
41
IN
41 42
IN
41 42
IN
41 42
OUT
41 42
IN
41
OUT
41 48 59
IN
41
OUT
41
IN
6
43 59 60 81
BI
6
43 59 60 81
BI
6
29 43 49 81
BI
6
29 43 49 81
BI
43 46 81
BI
43 46 81
BI
41
OUT
41
OUT
41
41
OUT
NOTE: SMS Interrupt can be active high or low, rename net accordingly. If SMS interrupt is not used, pull up to SMC rail.
B
SMC
SYNC_MASTER=T18_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
APPLE INC.
SCALE
DRAWING NUMBER
D
NONE
SYNC_DATE=02/05/2009
051-7903
SHT
OF
A
REV.
A
8340
8
7 6
5
4
3
2
1
8 7
6
5
4
3
SMC Reset "Button" / Brownout Detect
PP3V42_G3H
6 7
20 21 24 38 40 41 42 43
45 48 59 60 67
CRITICAL
U5000
NCP303LSN
SOT23-5-HF
D
SMC_MANUAL_RST_L
OMIT
1
R5001
0
5% 1/10W MF-LF 603
2
SILK_PART=SMC_RST
C5001
0.01UF
CERM
10% 16V
402
5
CD
4
NC
NC
1
2
GND
3
OUT
IN
PLACEMENT_NOTE=Place R5001 on BOTTOM side
PP3V42_G3H
6 7
20 21 24 38 40 41 42 43
48
IN
40 41 48
IN
45 48 59 60 67
SMC_TPAD_RST_L
SMC_ONOFF_L
U5001
5
SN74LVC1G02
1
2
SOT553-5
4
02
PLACEMENT_NOTE=Place next to U5000 (shares C5000)
3
1
R5000
1K
5% 1/16W MF-LF 402
2 1 2
1
C5000
0.1uF
20% 10V
2
CERM 402
SSM6N15FEAPE
SMC_TPAD_RST
SMC_RESET_L
Q5032
SOT563
5
40 42
OUT
3
D
SG
4
SMC_BC_ACOK
40 41 59 60 40 41 59 60
IN
SMC_MCP_VSENSE
40 41 44
MAKE_BASE=TRUE
SMC_CPU_FSB_ISENSE
40 41 45
MAKE_BASE=TRUE
SMC_MCP_CORE_ISENSE
40 41 45
MAKE_BASE=TRUE
SMC_MCP_DDR_ISENSE
40 41 45
MAKE_BASE=TRUE
TP_SMC_CPU_HI_ISENSE
40 41
MAKE_BASE=TRUE
TP_SMC_GPU_1V8_ISENSE
40 41
MAKE_BASE=TRUE
TP_SMC_GPU_ISENSE
40 41
MAKE_BASE=TRUE
TP_SMC_GPU_VSENSE
40 41
MAKE_BASE=TRUE
SMC_IG_THROTTLE_L
20 40 41 20 40 41
IN
SMC_BMON_MUX_SEL
40 41 45 40 41 45
IN
SMS_INT_L
40 41
MAKE_BASE=TRUE
SMC_MCP_SAFE_MODE
40 20
IN
SMC Aliases
SMC_BC_ACOK
MAKE_BASE=TRUE
SMC_MCP_VSENSE SMC_CPU_FSB_ISENSE SMC_MCP_CORE_ISENSE SMC_MCP_DDR_ISENSE TP_SMC_CPU_HI_ISENSE TP_SMC_GPU_1V8_ISENSE TP_SMC_GPU_ISENSE TP_SMC_GPU_VSENSE
SMC_IG_THROTTLE_L
MAKE_BASE=TRUE
SMC_BMON_MUX_SEL
MAKE_BASE=TRUE
SMS_INT_L
R5096
0
1 2
1/16W MF-LF
402
MCP_SPKR
5%
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
40 41
OUT
40 41 44
40 41 45
40 41 45
40 41 45
40 41
40 41
40 41
40 41
13 61 75
9
13 75
TO CPU
9
CPU_PROCHOT_L
BI
PM_THRMTRIP_L
OUT
Unused Pins
TP_SMC_FAN_1_CTL TP_SMC_FAN_1_CTL
40 41
IN
TP_SMC_FAN_1_TACH
SMC AVREF Supply
CRITICAL
VR5020
PP3V42_G3H
6 7
PART NUMBER
353S1381
20 21 24 38 40 41 42
43 45 48 59 60 67
ALTERNATE FOR PART NUMBER
353S1912
BOM OPTION
REF DES
ALL
C
REF3333
SOT23-3
1 2
IN
GND
3
1
C5020
0.47UF
10%
6.3V
2
CERM-X5R 402
C5025
COMMENTS:
Intersil ISL60002-33
OUT
10uF
20%
6.3V X5R 603
PP3V3_S5_AVREF_SMC
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
1
C5026
0.01UF
10% 16V
2
CERM 402
1
2
GND_SMC_AVSS
TABLE_ALT_HEAD
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V
TABLE_ALT_ITEM
40 44 45
6
40
40 41
MAKE_BASE=TRUE
NC_SMC_FAN_2_CTL NC_SMC_FAN_2_CTL
40 41
IN
NC_SMC_FAN_2_TACH
40 41
MAKE_BASE=TRUE
NC_SMC_FAN_3_CTL
40 41
IN
NC_SMC_FAN_3_TACH
40 41
MAKE_BASE=TRUE
TP_ALS_GAIN TP_ALS_GAIN
40 41
IN
TP_ESTARLDO_EN
40 41
IN
TP_SMC_EXCARD_PWR_EN
40 41
IN
TP_SMC_RSTGATE_L
40 41
IN
TP_SMC_P24
40 41
IN
TP_SMC_P41
40 41
IN
TP_SMC_PB3
40 41
IN
NO_TEST=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
TP_SMC_FAN_1_TACH
MAKE_BASE=TRUE
NC_SMC_FAN_2_TACH
NC_SMC_FAN_3_CTL
MAKE_BASE=TRUE
NC_SMC_FAN_3_TACH
MAKE_BASE=TRUE
TP_ESTARLDO_EN
MAKE_BASE=TRUE
TP_SMC_EXCARD_PWR_EN
MAKE_BASE=TRUE
TP_SMC_RSTGATE_L
MAKE_BASE=TRUE
TP_SMC_P24
MAKE_BASE=TRUE
TP_SMC_P41
MAKE_BASE=TRUE
TP_SMC_PB3
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
40 41
OUT
40 41
OUT
40 41
OUT
40 41
40 41
40 41
40 41
40 41
40 41
40 41
40 41
40 41
40 41
Debug Power "Buttons"
SMC_ONOFF_L
603
OMIT
1
1
R5015
0
0
5%
5%
1/10W MF-LF 603
2
2
SILK_PART=PWR_BTN PLACEMENT_NOTEs:
Place R5014 on TOP side Place R5015 on BOTTOM side
OMIT
R5014
1/10W MF-LF
B
SILK_PART=PWR_BTN
System (Sleep) LED Circuit
PP5V_S3
6 7 8
29 37 38 39 49
51 53 62 63 68
1
523
402
1%
2
1
R5030
20
1% 1/16W MF-LF 402
2
SYS_LED_ILIM
R5031
1/16W MF-LF
40 41 48
OUT
SMC Crystal Circuit
1
2
C5010
15pF
1 2
5%
50V
CERM
402
C5011
15pF
1 2
5%
50V
CERM
402
SMC_XTAL
40
SMC_EXTAL
40
R5010
0
1 2
5% 1/16W MF-LF
402
SMC_XTAL_R
CRITICAL
Y5010
20.00MHZ
5X3.2-SM
SMC FSB to 3.3V Level Shifting
12 17 18 20 21 22 23 26
57 58 61 66 67 68 69 71 72 82
PP3V3_S0
6 7 27 35 37 41 43 45 46 47 49 53
1
R5061
100K
5% 1/16W MF-LF 402
2
CPU_PROCHOT_BUF
3
Q5060
5
DMB53D0UV
SOT-563
4
6
1
3
4
R5062
1 2
D
S G
D
S G
3.3K CPU_PROCHOT_L_R
5% 1/16W MF-LF
402
Q5059
SSM6N15FEAPE
SOT563
2
SMC_PROCHOT
Q5059
SSM6N15FEAPE
SOT563
5
SMC_THRMTRIP
SMC Pull-ups
SMC_PA0
40
SMC_PA1
40
SMC_PH2
40
SMC_ONOFF_L
40 41 48
SMC_LID
40 48 59
SMC_TX_L
38 40 42
SMC_RX_L
38 40 42
SMC_TMS
40 42
SMC_TDO
40 42
SMC_TDI
40 42
SMC_TCK
40 42
SMC_BIL_BUTTON_L
6
40 59
SMC_BC_ACOK
40 41 59 60
SMS_INT_L
40 41
SMC_GFX_OVERTEMP_L
40
SMC_EXCARD_OC_L
40
SMC_PA5
40
R5091 R5092 R5072
R5070 R5071 R5073 R5074
R5077 R5078 R5079 R5080 R5081 R5087 R5093 R5094 R5095
R5089
SMC Pull-downs
SMC_BS_ALRT_L
40
SMC_ADAPTER_EN
20 32 35 40
SMC_CASE_OPEN
40
SMC_EXCARD_CP
40
PM_SLP_S4_L
6
20 38 40 41 67
PM_SLP_S4_L
6
20 38 40 41 67
R5076 R5085 R5086
R5088 R5090
2
100K 100K
10K
10K
100K
10K
100K
10K 10K 10K 10K 10K
470K
10K 10K 10K
10K
100K
10K 10K
10K
100K
G
1 2 1 2 1 2
1 2 1 2 1 2 1 2
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
12 17 18 20 21 22 23 26
1 2
1 2 1 2 1 2
1 2
1 2
1
R5060
10K
5% 1/16W MF-LF 402
2
SMC_PROCHOT_3_3_L
6 D
Q5060
DMB53D0UV
SOT-563
S 1
6 7
20 21 24 38 40 41 42 43
45 48 59 60 67
5% 402 5% 402
5% 402 5% 402 5% 402 5% 402 5% 402 5% 402
5% 402
57 58 61 66 67 68 69 71 72 82
PP3V3_S0
6 7 27 35 37 41 43 45 46 47 49 53
5% 402
5%
5%
TO SMC
PP3V42_G3H
MF-LF
1/16W
MF-LF
1/16W 1/16W5%MF-LF
1/16W
MF-LF
1/16W
MF-LF MF-LF
1/16W
MF-LF
1/16W
1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF 1/16W MF-LF 1/16W
MF-LF
MF-LF
1/16W
1/16W
MF-LF
MF-LF
1/16W
MF-LF1/16W
MF-LF
1/16W
MF-LF
1/16W
1/16W
MF-LF
4025% 4025% 402
4025% 4025%
4025%
4025%
402 4025% 4025%
4025%
402
40
OUT
D
40
IN
40
IN
C
B
SYS_LED_L_VDIV
1
R5032
1.47K
1% 1/16W MF-LF
402
A
2
SYS_LED_L
SMC_SYS_LED
40
IN
5
6 4
BD
Q1
GS 21
E
Q5030
DMB54D0UV
SOT-563
Q2
C 3
SYS_LED_ANODE
SMC Support
SYNC_MASTER=(K19_MLB)
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
37
OUT
APPLE INC.
D
SCALE
SYNC_DATE=(11/25/2008)
DRAWING NUMBER
051-7903
SHT
NONE
A
REV.
A
OF
8341
8
7 6
5
4
3
2
1
8 7
6
5
4
3
LPC+SPI Connector
CRITICAL
LPCPLUS
J5100
55909-0374
M-ST-SM
31
PP3V42_G3H
6 7
20 21 24 38 40 41 42 43
45 48 59 60 67
PP5V_S0
6 7
37 47 49 61 64 65 67 68
D
70 72
18 40 78
BI
18 40 78
BI
42
IN
42
OUT
18 40 78
IN
18 40
OUT
40 41
OUT
24
IN
40 41
OUT
40
IN
40
OUT
IN
LPC_AD<0> LPC_AD<1>
SPI_ALT_MOSI SPI_ALT_MISO LPC_FRAME_L PM_CLKRUN_L SMC_TMS DEBUG_RESET_L SMC_TDO SMC_TRST_L SMC_MD1
SMC_TX_L
Alternate SPI ROM Support
PP3V42_G3H
6 7
20 21 24 38 40 41 42 43
10K
1/16W MF-LF
402
1
5%
2
45 48 59 60 67
LPCPLUS
10
LPCPLUS
10
LPCPLUS_NOT
R5146
0
1 2
5% 1/16W MF-LF
402
9
1 2
VCC
Y+ Y-
U5110
PI3USB102ZLE
TQFN
CRITICAL
SEL OE*
GND
3
9
1 2
VCC
Y+ Y-
U5120
PI3USB102ZLE
TQFN
CRITICAL
SEL OE*
GND
3
PLACEMENT_NOTE=PLACE NEXT TO U1400
PP3V3_S5
6 7
17 19 21 22 24 28 32 35
36 42 52 62 66 67 68 69 71 82
R5190
SPI_CLK_R
20 42 78
IN
C
1
R5191
10K
5% 1/16W MF-LF
402
2
SEL HIGH OUTPUTS TO D (ON BOARD ROM) SEL LOW OUTPUTS TO M (FRANKCARD ROM)
59 60 67
PP3V42_G3H
6 7
20 21 24 38
40 41 42 43 45 48
1
R5140
100K
5% 1/16W MF-LF
402
2
20 42
BI
SPIROM_USE_MLB
20 42 78
IN
20 42 78
OUT
20 78
IN
SPI_MOSI_R
SPI_MISO SPI_CS0_R_L
42
SPIROM_USE_MLB
20
MAKE_BASE=TRUE
B
LPCPLUS
1
C5114
0.1UF
20% 10V
2
CERM 402
5
M+
4
M-
7
D+
6
D-
8
SPI_ALT_CLK SPI_ALT_MOSI
SPI_CLK_MUX SPI_MOSI_MUX
42
OUT
42
OUT
42 52
OUT
42 52
OUT
516S0573
LPCPLUS
1
C5124
0.1UF
20% 10V
2
CERM 402
5
M+
4
M-
7
D+
6
D-
8
SPI_ALT_MISO
SPI_ALT_CS_L
SPI_MISO_MUX
SPI_MLB_CS_L
1
R5144
20K
5% 1/16W MF-LF
402
2
42
IN
Pull-up on debug card
42
OUT
42 52
IN
52
OUT
PP3V3_S5
6 7
17 19 21 22 24 28 32 35 36
42 52 62 66 67 68 69 71 82
32
2
1
4
3
6
5
8
7
10
9
12
11
14
13
16
15
18
17
20
19
22
21
24
23
26
25
28
27
30
29
33
34
LPC_CLK33M_LPCPLUS LPC_AD<2> LPC_AD<3>
SPIROM_USE_MLB SPI_ALT_CLK
SPI_ALT_CS_L LPC_SERIRQ LPC_PWRDWN_L SMC_TDI SMC_TCK SMC_RESET_L SMC_NMI SMC_RX_L LPCPLUS_GPIO
24 78
IN
18 40 78
BI
18 40 78
BI
20 42
OUT
42
IN
42
IN
18 40
BI
18 40
IN
40 41
OUT
40 41
OUT
40 41
OUT
40
OUT
38 40 41
OUT
17
OUT
D
C
B
SPI MUX BYPASS
LPCPLUS_NOT
R5156
0
SPI_CLK_MUX
42 52
OUT
SPI_MOSI_MUX
42 52
OUT
SPI_MISO_MUX
42 52
IN
A
8
7 6
1 2
5% 1/16W MF-LF
402
LPCPLUS_NOT
R5158
0
1 2
5% 1/16W MF-LF
402
LPCPLUS_NOT
R5157
0
1 2
5% 1/16W MF-LF
402
SPI_CLK_R
SPI_MOSI_R
SPI_MISO
20 42 78
IN
20 42 78
IN
20 42 78
OUT
APPLE INC.
5
4
3
2
LPC+SPI Debug Connector
SYNC_MASTER=K19_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
D
SCALE
NONE
051-7903
SHT
42 83
SYNC_DATE=02/05/2009
OF
1
A
REV.
A
8 7
6
5
4
3
MCP79 SMBUS "0" CONNECTIONS
57 58 61 66 67 68 69 71 72
PP3V3_S0
6 7
12 17 18 20 21 22 23 26
27 35 37 41 43 45 46 47 49 53 82
1
402
1
R5201
1K
1K
5%
5% 1/16W MF-LF 402
2
2
SO-DIMM "A"
(Write: 0xA0 Read: 0xA1)
J3100
SMBUS_MCP_0_CLK SMBUS_MCP_0_DATA
SO-DIMM "B"
(Write: 0xA2 Read: 0xA3)
J3200
SMBUS_MCP_0_CLK
NBC
=I2C_SODIMMB_SDA
12 20 26 27 43 78
12 20 26 43 78
12 20 26 27 43 78
27
MCP79
U1400
(MASTER)
SMBUS_MCP_0_CLK
12 20 26 27 43 78
D
MAKE_BASE=TRUE
SMBUS_MCP_0_DATA
12 20 26 43 78
MAKE_BASE=TRUE
R5200
1/16W MF-LF
MCP79 SMBUS "1" CONNECTIONS
57 58 61 66 67 68 69 71 72
PP3V3_S0
6 7
12 17 18 20 21 22 23 26
27 35 37 41 43 45 46 47 49 53 82
1
1
402
R5231
2.0K
5%
5%
1/16W MF-LF 402
2
2
Mikey
(WRITE: 0X72 READ: 0X73)
U6860
SMBUS_MCP_1_CLK SMBUS_MCP_1_DATA
20 43 58 72 78
20 43 58 72 78
MCP79
U1400
(MASTER/SLAVE)
C
SMBUS_MCP_1_CLK
20 43 58 72 78
MAKE_BASE=TRUE
SMBUS_MCP_1_DATA
20 43 58 72 78
MAKE_BASE=TRUE
R5230
2.0K
1/16W MF-LF
SMC "0" SMBus Connections
57 58 61 66 67 68 69 71 72
PP3V3_S0
6 7
12 17 18 20 21 22 23 26
27 35 37 41 43 45 46 47 49 53 82
1
1
402
402
R5251
4.7K
5%
5%
1/16W MF-LF 402
2
2
MCP Temp
EMC1403-5: U5535
(Write: 0x98 Read: 0x99)
SMBUS_SMC_0_S0_SCLSMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA
Sensor ADCs
(Write: 0x10 Read: 0x11)
U5930
SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA
1
1
R5281
2.61K
1%
1% 1/16W MF-LF 402
2
2
BATTERY & BIL
J6950 & J6955
(See Table)
SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA
SMC
U4900
(MASTER)
SMBUS_SMC_0_S0_SCL
40 43 46 51 81
SMBUS_SMC_0_S0_SDA
40 43 46 51 81
81 51 43 46 40
MAKE_BASE=TRUE
51 81
43 46 40
SMBUS_SMC_0_S0_SDA
MAKE_BASE=TRUE
R5250
4.7K
1/16W MF-LF
SMC "Battery A" SMBus Connections
PP3V42_G3H
6 7
20 21 24 38 40 41 42 45
48 59 60 67
SMC
U4900
(MASTER)
SMBUS_SMC_BSA_SCL
6
40 43 59
60 81
SMBUS_SMC_BSA_SDA
6
40 43 59
60 81
SMBUS_SMC_BSA_SCL
MAKE_BASE=TRUE
SMBUS_SMC_BSA_SDA
MAKE_BASE=TRUE
R5280
2.61K
1/16W MF-LF
40 43 46 51 81
40 43 46 51 81
40 43 46 51 81
40 43 46 51 81
6
40 43
59 60 81
6
40 43
59 60 81
SMC "A" SMBus Connections
NOTE: SMC RMT bus remains powered and may be active in S3 state
SMC
U4900
(MASTER)
SMBUS_SMC_A_S3_SCL
6
29 40 43
49 81
SMBUS_SMC_A_S3_SDA
6
29 40 43
49 81
20 25 29 30 43 48 50 68
PP3V3_S3
6 7
R5270
SMBUS_SMC_A_S3_SCL
MAKE_BASE=TRUE
SMBUS_SMC_A_S3_SDA
MAKE_BASE=TRUE
1/16W MF-LF
402
1
1
R5271
1K
1K
5%
5%
1/16W MF-LF 402
2
2
(Write: 0x90 Read: 0x91)
SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA
(Write: 0x52 Read: 0x53)
SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA
SMC "B" SMBus Connections
57 58 61 66 67 68 69 71 72
PP3V3_S0
6 7
12 17 18 20 21 22 23 26
27 35 37 41 43 45 46 47 49 53 82
1
1
402
R5261
4.7K
5%
5%
1/16W MF-LF 402
2
2
(Write: 0x98 Read: 0x99)
SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA
SMC
U4900
(MASTER)
SMBUS_SMC_B_S0_SCL
40 43 46 81
SMBUS_SMC_B_S0_SDA
40 43 46 81
81 43 46 40
SMBUS_SMC_B_S0_SCL
MAKE_BASE=TRUE
81
43 46 40
SMBUS_SMC_B_S0_SDA
MAKE_BASE=TRUE
R5260
4.7K
1/16W MF-LF
TRACKPAD
J5800
ALS
J3401
CPU Temp
EMC1403-5: U5515
6
29 40
43 49 81
6
29 40
43 49 81
6
29 40
43 49 81
6
29 40
43 49 81
40 43 46 81
40 43 46 81
D
C
LP8543 (Bklt)
U9700 (DEFAULT)
(Write: 0x58 Read: 0x59)
SMBUS_MCP_1_CLK SMBUS_MCP_1_DATA
20 43 58 72 78
20 43 58 72 78
Battery
Battery Manager - (Write: 0x16 Read: 0x17) Battery LED Driver - (Write: 0x36 Read: 0x37) Battery Temp - (Write: 0x90 Read: 0x91)
Battery Charger
ISL6258A - U7000
(Write: 0x12 Read: 0x13)
SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA
6
40 43
59 60 81
6
40 43
59 60 81
SMC "Management" SMBus Connections
PP3V3_S3
6 7
20 25 29 30 43 48 50 68
SMC
U4900
(MASTER)
B
SMBUS_SMC_MGMT_SCL
25 37 40 43 81
SMBUS_SMC_MGMT_SDA
25 37 40 43 81
81 43 37 40 25
SMBUS_SMC_MGMT_SCL
MAKE_BASE=TRUE
43 81
37 40
SMBUS_SMC_MGMT_SDA
25
MAKE_BASE=TRUE
R5290
A
The bus formerly known as "Battery B"
1
1
4.7K
1/16W MF-LF
402
R5291
4.7K
5%
5% 1/16W MF-LF 402
2
2
Vref DACs
(Write: 0x98 Read: 0x99)
SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA
Margin Control
(Write: 0x30 Read: 0x31)
SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA
HDD Margin Ctrl.
(Write: 0xXX Read: 0xXX)
SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA
U2900
U2901
J4501
25 37 40 43 81
25 37 40 43 81
25 37 40 43 81
25 37 40 43 81
25 37 40 43 81
25 37 40 43 81
K19i SMBus Connections
SYNC_MASTER=WFERRY_K19I
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
APPLE INC.
SCALE
DRAWING NUMBER
D
NONE
SYNC_DATE=12/12/2008
051-7903
SHT
B
A
REV.
A
OF
8343
8
7 6
5
4
3
2
1
8 7
6
5
4
3
CPU Voltage Sense / Filter
6 7
10 11 61
PPVCORE_S0_CPU
PLACEMENT_NOTE=Place near U1000 center
XW5309
SM
1 2
CPUVSENSE_IN
D
R5309
4.53K
1 2
1% 1/16W MF-LF
402
Place RC close to SMC
SMC_CPU_VSENSE
1
C5309
0.22UF
20%
6.3V
2
X5R 402
GND_SMC_AVSS
40 41 44 45
40
OUT
D
MCP Voltage Sense / Filter
6 7
21 22 64
PPVCORE_S0_MCP
PLACEMENT_NOTE=Place near U1400 center
XW5359
1 2
SM
MCPVSENSE_IN
R5359
4.53K
1 2
1% 1/16W MF-LF
402
Place RC close to SMC
SMC_MCP_VSENSE
1
C5359
0.22UF
20%
6.3V
2
X5R 402
GND_SMC_AVSS
40 41 44 45
40 41
OUT
C
C
PBUS VOLTAGE SENSE ENABLE & FILTER
Q5315
NTUD3127CXXG
SOT-963
N-CHANNEL
G
PM_SLP_S3_L_BUF
67 68
IN
Enables PBUS VSense divider when high.
PPBUS_G3H
6 7
35 45 59 60 62 63 64 73
B
R5315
100K
1/16W MF-LF
1
1%
402
2
PBUSVSENS_EN_L_DIV
2
1
5
4
G
P-CHANNEL
6
D
S
D
S
PBUSVSENS_EN_L
3
R5316
100K
1/16W MF-LF
1
1%
402
2
MIN_LINE_WIDTH=0.20 mm MIN_NECK_WIDTH=0.20 mm VOLTAGE=18.5V
PPBUS_G3HRS5_VSENSE
1
R5385
27.4K
1% 1/16W MF-LF
402
2
1
R5386
5.49K
1% 1/16W MF-LF
402
2
Place RC close to SMC
RTHEVENIN = 4573 OHMS
SMC_PBUS_VSENSE
1
C5385
0.22UF
20%
6.3V
2
X5R 402
GND_SMC_AVSS
40 41 44 45
40
OUT
B
VOLTAGE SENSING
A
8
7 6
5
4
3
SYNC_MASTER=K24_MLB
APPLE INC.
2
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
D
SCALE
051-7903
NONE
SHT
44 83
1
SYNC_DATE=02/05/2009
REV.
A
OF
A
8 7
6
5
4
3
MCP MEM VDD Current Sense / Filter
57 58 61 66 67 68 69 71 72 82
PP3V3_S0
6 7
12 17 18 20 21 22 23 26
27 35 37 41 43 45 46 47 49 53
1
C5400
0.1uF
20%
R5410
R5412
5
IN-
4
CERM
0
5% 1/16W MF-LF
402
118
1% 1/16W MF-LF
402
U5402
INA213
SC70
GND
10V 402
2
1
2
2
3
1
2
3
V+
OUT
2
5
2
U5400
OPA348 SC70-5
1
3
P1V5_S0_SENSE_E
Q5401
2SA2154MFV-YAE
SOD
1
P1V5_S0_SENSE_B
P1V5_S0_SENSE_C
1
C5417
0.1uF
20% 10V
2
CERM 402
6
CPUVTT_IOUT
1
REFIN+
4
P1V5_S0_SENSE_AMP
1
C5434
0.1UF
10% 16V
2
X5R 402
R5417
4.53K
1 2
1% 1/16W MF-LF
PLACEMENT_NOTEs: Place close to SMC
Place close to SMC (For R and C)
PLACEMENT_NOTEs: Place close to SMC
Place close to SMC (For R and C)
402
R5418
4.53K
1 2
1% 1/16W MF-LF
402
2
R5411
0
5% 1/16W MF-LF
402
1
SMC_MCP_DDR_ISENSE
1
C5435
0.22UF
20%
6.3V
2
X5R 402
GND_SMC_AVSS
SMC_CPU_FSB_ISENSE
1
C5436
0.22UF
20%
6.3V
2
X5R 402
GND_SMC_AVSS
40 41 44 45
40 41 44 45
40 41
OUT
CPU VCore Load Side Current Sense / Filter
40 41
OUT
D
P1V5_S0_KELVIN
68
IN
P1V5_S0_SENSE
68
IN
C
MCP/CPU 1.05V AND CPU VCore High-Side Current Sense / Filter
57 58 61 66 67 68 69 71 72 82
PP3V3_S0
6 7
12 17 18 20 21 22 23 26
27 35 37 41 43 45 46 47 49 53
PPBUS_G3H
6 7
35 44 59 60 62 63 64 73
PPBUS_CPU_IMVP_ISNS
7
61 65
CRITICAL
R5492
0612-1
0.01
0.5%
12
34
1W
MF
ISNS_CPUVTT_N
82
ISNS_CPUVTT_P
82
B
MCP VCore Current Sense Filter
R5416
4.53K
61
MCPCORES0_IMON
64
IN
IMVP6_IMON
IN
PLACEMENT_NOTEs: Place close to SMC
Place close to SMC
Place close to SMC (For R’s and C)
1 2
1% 1/16W MF-LF
PLACEMENT_NOTEs: Place close to SMC
Place close to SMC (For R and C)
R5471
6.19K
1 2
1% 1/16W MF-LF
402
402
R5480
17.4K
1/16W MF-LF
402
SMC_MCP_CORE_ISENSE
1
C5472
0.22UF
20%
6.3V
2
X5R 402
GND_SMC_AVSS
SMC_CPU_ISENSE
1
1
C5470
0.22UF
1%
20%
6.3V
2
X5R 402
2
GND_SMC_AVSS
40 41 44 45
40 41 44 45
40 41
OUT
D
C
40
OUT
B
PP3V42_G3H
6 7
20 21 24 38 40 41 42 43
48 59 60 67
PLACEMENT_NOTE=Place near sense resistor
Charger/Load side
60 82
IN
CHGR_CSO_R_N
60 82
IN
Battery side
NOTE: Monitoring current from battery to PBUS (battery discharge) across R7008
CHGR_BMON
60
A
IN
From charger
8
Battery (BMON) Current Sense, MUX & Filter
BMON_ENG
1
3
V+
U5403
INA213
5
SC70
IN-
BMON_ENG
4
(50V/V)
For engineering, stuff BMON_ENG For production, stuff BMON_PROD
GND
OUT
REFIN+
2
C5418
0.1uF
20% 10V
2
CERM 402
6
BMON_INA_OUTCHGR_CSO_R_P
1
BMON_ENG
C5459
0.1uF
CERM
20% 10V
402
1
2
BMON_ENG
U5413
NC7SB3157P6XG
SC70
B1
1
1
2
GND
0
B0
VER 1
SEL
6
5
VCC
43
A
BMON_PROD
R5431
0
2 1
5% 1/16W MF-LF
402
PLACEMENT_NOTE=Place R5431 next to U5413
7 6
SMC_BMON_MUX_SEL
BMON_AMUX_OUT
BMON_ENG
1
R5423
100K
5% 1/16W MF-LF 402
2
PLACEMENT_NOTEs: Place close to SMC
Place close to SMC (For R and C)
5
40 41
IN
R5401
4.53K
1 2
1% 1/16W MF-LF
402
SMC_BATT_ISENSE
1
C5490
0.22UF
20%
6.3V
2
X5R 402
GND_SMC_AVSS
40 41 44 45
DC-IN (AMON) Current Sense Filter
R5481
4.53K
CHGR_AMON
IN
PLACEMENT_NOTEs: Place close to SMC
Place close to SMC (For R and C)
40
OUT
1 2
1% 1/16W MF-LF
402
SMC_DCIN_ISENSE
1
C5487
0.22UF
20%
6.3V
2
X5R 402
GND_SMC_AVSS
40 41 44 45
40 60
OUT
Current Sensing
SYNC_MASTER=WFERRY_K19I
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
D
APPLE INC.
4
3
2
SCALE
NONE
SYNC_DATE=12/16/2008
051-7903
SHT
OF
45
1
A
REV.
A
83
8 7
6
5
4
3
CPU T-Diode Thermal Sensor
57 58 61 66 67 68 69 71 72 82
PP3V3_S0
6 7
12 17 18 20 21 22 23 26
27 35 37 41 43 45 46 47 49 53
D
9
82
BI
DETECT CPU DIE TEMPERATURE
9
82
BI
3
DETECT FIN-STACK TEMPERATURE
Q5501
BC846BMXXH
SOT732-3
1
2
R5515
1 2
CPU_THERMD_P
CPU_THERMD_N
CPUTHMSNS_D2_P
82
CPUTHMSNS_D2_N
82
47
MIN_LINE_WIDTH=0.25 mm
5%
MIN_NECK_WIDTH=0.25 mm
1/16W
VOLTAGE=3.3V
MF-LF
402
SIGNAL_MODOL=EMPTY
C5521
0.0022uF
SIGNAL_MODOL=EMPTY
C5520
0.0022uF
PP3V3_S0_CPUTHMSNS_R
1
10% 50V
2
CERM
402
1
10% 50V
2
CERM
402
2
4
5
INTERNAL DIODE IN U5515 DETECTS CPU PROXIMITY TEMPERATURE
DP1
CRITICAL
DN1
DP2/DN3
DN2/DP3
GND
6
1
VDD
U5515
EMC1413
DFN
THERM*/ADDR
THRM_PAD
ALERT*
SMDATA
SMCLK
11
1
C5515
0.1uF
20% 10V
2
CERM 402
7
CPUTHMSNS_THERM_L
83
CPUTHMSNS_ALERT_L
9
SMBUS_SMC_B_S0_SDA
10
SMBUS_SMC_B_S0_SCL
PLACEMENT NOTE: PLACE U5515 NEAR CPU
R5516
1/16W MF-LF
10K
1
1
R5517
10K
5%
1%
1/16W MF-LF 402
402
2
2
40 43 81
BI
40 43 81
BI
D
C
C
MCP T-Diode Thermal Sensor
57 58 61 66 67 68 69 71 72 82
PP3V3_S0
6 7
12 17 18 20 21 22 23 26
27 35 37 41 43 45 46 47 49 53
20 82
BI
DETECT MCP DIE TEMPERATURE
B
CRITICAL
J5590
78171-0002
M-RT-SM
3
1 2
4
NOSTUFF
DETECT HEAT-PIPE TEMPERATURE
20 82
BI
82
R5535
1 2
MCP_THMDIODE_P
MCP_THMDIODE_N
MCPTHMSNS_D2_P
82
SIGNAL_MODOL=EMPTY
MCPTHMSNS_D2_N
47
MIN_LINE_WIDTH=0.25 mm
5%
MIN_NECK_WIDTH=0.25 mm
1/16W
VOLTAGE=3.3V
MF-LF
402
SIGNAL_MODOL=EMPTY
C5522
0.0022uF
C5540
0.0022uF
NOSTUFF
PP3V3_S0_MCPTHMSNS_R
1
10% 50V
2
CERM
402
1
10% 50V
2
CERM
402
INTERNAL DIODE IN U5535 DETECTS MCP PROXIMITY TEMPERATURE
1
C5535
0.1uF
20% 10V
2
CERM 402
7
MCPTHMSNS_THERM_L
83
MCPTHMSNS_ALERT_L
9
SMBUS_SMC_0_S0_SDA
10
SMBUS_SMC_0_S0_SCL
2
4
5
DP1
DN1
DP2/DN3
DN2/DP3
GND
6
1 VDD
U5535
EMC1413
DFN
THERM*/ADDR
CRITICAL
ALERT*
SMDATA
SMCLK
THRM_PAD
11
PLACEMENT NOTE: PLACE U5535 NEAR MCP
R5536
10K
1/16W MF-LF
1
1
R5537
10K
5%
1%
1/16W MF-LF 402
402
2
2
40 43 51 81
BI
BI
40 43 51 81
B
REPLACED 518S0521 WITH 518S0519
Thermal Sensors
A
8
7 6
5
4
3
SYNC_MASTER=K24_MLB
APPLE INC.
2
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
D
SCALE
051-7903
NONE
SHT
SYNC_DATE=02/05/2009
OF
8346
1
A
REV.
A
8 7
6
5
4
3
D
PP5V_S0
6 7
37 42 49 61 64 65 67 68
70 72
58 61 66 67 68 69 71 72 82
PP3V3_S0
6 7
12 17 18 20 21 22 23 26
27 35 37 41 43 45 46 49 53 57
47K
1/16W MF-LF
402
1
5%
2
C
R5660
R5665
47K
SMC_FAN_0_TACH
40
R5661
100K
1/16W MF-LF
SMC_FAN_0_CTL
40
402
1 2
1/16W MF-LF
1
5%
1
GS
2
2
5%
402
FAN_RT_TACH
6
Q5660
SSM3K15FV
SOD-VESM-HF
D
FAN_RT_PWM
6
3
CRITICAL
J5601
78171-0004
M-RT-SM
5
NC
1
5V DC
2
TACH
3
MOTOR CONTROL
4
GND
6
NC
518S0521
D
C
B
B
Fan
A
SYNC_MASTER=K24_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
APPLE INC.
8
7 6
5
4
3
2
SCALE
SYNC_DATE=02/05/2009
DRAWING NUMBER
051-7903
SHT
NONE
A
REV.
A
OF
8347
1
8 7
6
5
4
3
IC
PSOC USB CONTROLLER
USB INTERFACES TO MLB
SPI HOST TO Z2
D
PICKB_L
6
49
BUTTON_DISABLE
48
Z2_HOST_INTN
6
49
WS_LEFT_SHIFT_KEY
48
WS_LEFT_OPTION_KEY
48
WS_CONTROL_KEY
48
Z2_KEY_ACT_L
6
49
TP_P4_5 Z2_DEBUG3
6
49
Z2_RESET
6
49
PSOC_MISO
6
49
PSOC_F_CS_L
6
49
PSOC_MOSI
6
49
PSOC_SCLK
6
49
Z2_MISO
6
49
Z2_CS_L
6
49
Z2_MOSI
6
49
Z2_SCLK
6
49
C
6
USB_TPAD_P
19 78
B
TO MLB CONNECTOR
19 78
USB_TPAD_N
1
P2_3
2
P2_1
3
NC
P4_7
4
P4_5
5
P4_3
6
P4_1
7
P3_7
8
P3_5
9
P3_3 P3_1 P5_7 P5_5 P5_3 P5_1
TP_PSOC_SCL
NC_PSOC_SDA
6
NC_PSOC_P1_3
6
NC_ISSP_SCLK_P1_1
ISSP SCLK/I2C SCL
DIFFERENTIAL_PAIR=USB2_TPAD
R5701
1 2
1/16W MF-LF
R5702
1 2
1/16W MF-LF
P2_5
P1_7
15
24
5%
402
24
5%
402
DIFFERENTIAL_PAIR=USB2_TPAD
TRACKPAD PICK BUTTONS KEYBOARD SCANNER
55
P2_7
P0_3
P0_5
P0_1
CRITICAL
U5701
CY8C24794
(SYM-VER2) APN 337S2983
P1_1
P1_3
P1_5
VSS
19
USB_TPAD_R_P
USB_TPAD_R_N
51
P0_7
OMIT
D+
20
50
VSS
MLF
D-
21
PP3V3_S3_PSOC
48
48 6 48 6 48
6
6
WS_KBD22
WS_KBD23
WS_KBD21
VDD
P0_4
P0_2
P0_6
P7_7
P7_0
P1_0
VDD
25182617271628
24
235722 49
PP3V3_S3_PSOC
48
48
48
6
6
WS_KBD19
WS_KBD18
WS_KBD20
45544653475248
435644
P2_4
P2_6
P0_0
P2_2 P2_0 P4_6 P4_4 P4_2 P4_0 P3_6 P3_4 P3_2 P3_0 P5_6 P5_4 P5_2 P5_0
THRML
PAD
P1_2
P1_4
P1_6
NC_ISSP_SDATA_P1_0
ISSP SDATA/I2C SDA
42 41 40 39 38 37 36 35 34 3310 3211 3112 3013 2914
WS_KBD4 WS_KBD5 WS_KBD6
Z2_CLKIN
NC_P7_7
48
WS_KBD17 WS_KBD16N WS_KBD15_C WS_KBD14 WS_KBD13 WS_KBD12 WS_KBD11 WS_KBD10 WS_KBD9 WS_KBD8 WS_KBD7 WS_KBD1 WS_KBD2 WS_KBD3
6
6
6
6
6
49
6
6
48
48
48
6
48
6
48
6
48
6
48
6
48
6
48
6
48
6
48
6
48
6
48
6
48
48
48
48
TMP102
3V3 LDO
PSOC
18V BOOSTER
PIN NAME
PP3V3_S3
6 7
20 25 29 30 43 48 50 68
WS_LEFT_SHIFT_KBD
6
48
PP3V3_S3
6 7
20 25 29 30 43 48 50 68
WS_LEFT_OPTION_KBD
6
48
6 7
20 25 29 30 43 48 50 68
6
48
U5701 CHIP DECOUPLING
PLACE C5701, C5702 & C5703
PP3V3_S3_PSOC
48
1
C5701
4.7UF
20%
6.3V
2
X5R 603
VDD PIN 22
1
C5702
100PF
5% 50V
2
CERM 402
MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM
1
C5703
0.1UF
10% 16V
2
X7R-CERM 402
PLACE C5704, C5705 & C5706 CLOSE TO U5701CLOSE TO U5701
1
C5704
100PF
5% 50V
2
CERM 402
VDD PIN 49
1
C5705
0.1UF
10% 16V
2
X7R-CERM 402
1
C5706
4.7UF
20%
6.3V
2
X5R 603
R5704
1.5
1 2
5% 1/16W MF-LF
402
PP3V3_S3
6 7
20 25 29 30 43 48 50 68
V+
VDD VOUT
CURRENT
10UA 80UA 60MA MAX 60MA MAX
VDD
8MA (TYP)
14MA (MAX)
VIN
4MA (MAX)
R_SNS
2.55 KOHM
10 OHM
0.2 OHM
1.5 OHM
4.7 OHM
V_SNS POWER
0.0255 V
0.204 V
0.6 V
0.012 V
0.012 V
0.021 V
0.0188 V
ISOLATION CIRCUIT
6 7
20 21 24 38 40 41 42 43
45 48 59 60 67
6 7
20 21 24 38 40 41 42 43
45 48 59 60 67
6 7
20 21 24 38 40 41 42 43 45
48 59 60 67
PP3V3_S3
WS_CONTROL_KBD
PP3V42_G3H
2
A
U5725
1
B
PP3V42_G3H
2
A
U5726
1
B
PP3V42_G3H
2
A
1
B
TC7SZ08AFEAPE
5
3
5
3
U5727
CRITICAL
SOT665
4
Y
CRITICAL
TC7SZ08AFEAPE
SOT665
4
Y
CRITICAL
TC7SZ08AFEAPE
5
SOT665
Y
3
4
TPAD BUTTONS DISABLE
BUTTON_DISABLE
48
Q5701
SSM3K15FV
SOD-VESM-HF
PLACE THESE COMPONENTS CLOSE TO J5800
THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB
3
D
C5725
0.1UF
20% 10V
CERM
402
C5726
0.1UF
0.255E-6 W
16.32E-6 W
0.72E-3 W
75.2E-6 W
12
20% 10V
CERM
402
C5727
0.1UF
20% 10V
CERM
402
36E-3 W
96E-6 W
294E-6 W
WS_LEFT_SHIFT_KEY
12
WS_LEFT_OPTION_KEY
12
WS_CONTROL_KEY
R5714
470
1 2
1% 1/16W MF-LF
402
R5715
10K
1 2
1% 1/16W MF-LF
402
1
C5710
0.1UF
20% 10V
2
CERM
PLACEMENT_NOTE=NEAR J5713
402
40 41
OUT
WS_KBD15_C
48
WS_KBD16N
48
SMC_ONOFF_L
SMC_MANUAL_RESET LOGIC
48
WS_LEFT_SHIFT_KBD
6
48
48
48
WS_LEFT_OPTION_KBD
6
48
WS_CONTROL_KBD
6
48
1
R5769
33K
5%
1/16W MF-LF 402
2
Alternate Parts
PART NUMBER
311S0406 311S0447
A
1
SMC_LID
40 41 59
IN
G S
THE TPAD BUTTONS WILL BE DISABLE
2
WHEN THE LID IS CLOSED LID OPEN => SMC_LID_LC ~ 3.42V
LID CLOSE => SMC_LID_LC < 0.50V
KEYBOARD CONNECTOR
PP3V3_S3
IN
WS_KBD1
6
48
WS_KBD2
6
48
WS_KBD3
6
48
WS_KBD4
6
48
WS_KBD5
6
48
WS_KBD6
6
48
WS_KBD7
6
48
WS_KBD8
6
48
WS_KBD9
6
48
WS_KBD10
6
48
WS_KBD11
6
48
WS_KBD12
6
48
WS_KBD13
6
48
WS_KBD14
6
48
WS_KBD15_CAP
6
WS_KBD16_NUM
6
WS_KBD17
6
48
WS_KBD18
6
48
WS_KBD19
6
48
WS_KBD20
6
48
WS_KBD21
6
48
WS_KBD22
6
R5710
1K
1 2
5% 1/16W MF-LF
402
6 7
20 21 24 38 40 41 42 43
45 48 59 60 67
PP3V42_G3H
1
R5770
33K
5%
1/16W MF-LF 402
2
ALTERNATE FOR PART NUMBER
48
WS_KBD23
6
48
WS_KBD_ONOFF_L
6
67
PP3V42_G3H
6 7
20 21 24 38 40 41 42
43 45 48 59 60
WS_LEFT_SHIFT_KBD
6
48
WS_LEFT_OPTION_KBD
6
48
WS_CONTROL_KBD
6
48
1
R5771
33K
5% 1/16W MF-LF 402
2
BOM OPTION
CRITICAL
J5713
APN 518S0637
NC
32
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
NC
31
F-RT-SM
FF14-30A-R11B-B-3H
1
2
APN 311S0406
CRITICAL
5
SN74LVC1G10
1 3 6
REF DES
SC70
A B C
ALL NXP PART AS ALTERNATE
U5703
2
4
Y
COMMENTS:
WELLSPRING 1
SYNC_MASTER=K24_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
APPLE INC.
SCALE
C5758
0.1UF
10% 16V X7R-CERM 402
SMC_TPAD_RST_L
TABLE_ALT_HEAD
TABLE_ALT_ITEM
DRAWING NUMBER
D
NONE
41
SYNC_DATE=02/05/2009
051-7903
SHT
48 83
D
C
B
A
REV.
A
OF
8
7 6
5
4
3
2
1
8 7
6
5
4
3
BOOSTER +18.5VDC FOR SENSORS
BOOSTER DESIGN CONSIDERATION:
- POWER CONSUMPTION
- DROOP LINE REGULATION
- RIPPLE TO MEET ERS
- 100-300 KHZ CLEAN SPECTRUM
- STARTUP TIME LESS THAN 2MS
D
PP5V_S3
6 7 8
29 37 38 39 41 49 51 53
62 63 68
0
5%
R5805
1 2
MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM
1/16W
MF-LF
402
INPUT_SW
0.50MM
0.20MM
PP5V_S3_BOOSTER
APN 152S0504
CRITICAL
L5801
3.3UH-870MA
VLF3010AT-SM-HF
APN 353S1401
2
BOOST_SW
VIN
1
C5800
0.1UF
20% 10V
2
CERM
PLACEMENT_NOTE=NEAR J5800
402
1
2
C5816
0.1UF
10% 16V X7R-CERM 402
1
2
C5817
2.2UF
10% 16V X5R 603
L
DO
THRML
PAD
U5805
TPS61045
QFN
CRITICAL
9
PGND
CTRL
GND 617
4
FB
53
8
SW
- R5812,R5813,C5818 MODIFIED
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM SWITCH_NODE=TRUE
BOOST_FB
Z2_BOOST_EN
1
R5811
100K
1% 1/16W MF-LF 402
2
6
49
CRITICAL
D5802
SOD-323
B0520WSXG
APN 371S0313
MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM
1
C5818
39PF
5% 50V
2
CERM 402
1
R5812
1M
1% 1/16W MF-LF 402
2
1
R5813
71.5K
1%
1/16W MF-LF
402
2
PP18V5_S3_SW
1
2
C5819
1UF
10% 25V X5R 603-1
R5806
0
1 2
5% 1/16W MF-LF
402
PP18V5_S3
D
6
49
Z2_CS_L
6
48
Z2_DEBUG3
6
48
Z2_MOSI
6
48
Z2_MISO
6
48
Z2_SCLK
6
48
Z2_BOOST_EN
6
49
Z2_HOST_INTN
6
48
Z2_CLKIN
6
48
PP3V3_S3_LDO
6
49
IPD FLEX CONNECTOR
APN 516S0689
CRITICAL
J5800
55560-0228
0.50MM
M-ST-SM
0.50MM
0.20MM
0.20MM
NC
1
2
34 56 78
10
9 1112 1314 1516 1718 19
20
2122
Z2_KEY_ACT_L
PSOC_F_CS_L
PSOC_MISO
PSOC_SCLK
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_A_S3_SCL
0.50MM
0.20MM
Z2_RESET
PICKB_L
PSOC_MOSI
PP18V5_S3
6
6
6
6
6
6
6
48
48
48
48
48
48
6
48
6
6
49
29 40 43 81
29 40 43 81
C
C
3V3 LDO FOR IPD
R5873
PP5V_S3
6 7 8
29 37 38 39 41 49 51 53
62 63 68
B
10
1 2
1% 1/16W MF-LF
402
1
C5853
2.2UF
10%
16V
2
X5R 603
PP5V_S3_VR
1
CE
CRITICAL
2
APN 353S1364
VDD
VR5802
MM3243DRRE
MLF
GND
4
VOUT
PP3V3_S3_LDO_R
3
PP3V3_S3_LDO
6
49
2
1%
1/6W
0.2
R5836
1
MF
402-HF
1
C5838
0.1UF
10%
16V
2
X7R-CERM 402
1
C5854
4.7UF
20%
6.3V
2
X5R 603
B
KEYBOARD BACKLIGHT DRIVNG AND DETECTION
10UH-0.58A-0.35OHM
1 2
1
VIN
KB_BL
DFN
THRML
PAD
7
KB_BL
CRITICAL
L5850
1098AS-SM
SW
LED
CAP
3
5
4
KBDLED_SW
MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.25 MM SWITCH_NODE=TRUE
KB_BL
1
R5855
10
1%
1/16W
MF-LF
402
2
KBDLED_CAP
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM
1
2
KB_BL C5855
1UF
10% 35V X5R 603
KBDLED_ANODE
6
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM
APN 518S0691
KB_BL
CRITICAL
J5815
FF18-4A-R11AD-B-3H
SMC_KDBLED_PRESENT_L
6
49
F-RT-SM
1 2 3 4
KBD BACKLIGHT CONNECTOR
J5815 pin 1 is grounded
on keyboard backlight flex
WELLSPRING 2
SYNC_MASTER=K24_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
APPLE INC.
SCALE
D
NONE
DRAWING NUMBER
051-7903
SYNC_DATE=02/25/2009
SHT
OF
49 83
A
REV.
A
PP3V3_S0
58 61 66 67 68 69 71 72 82
6 7
12 17 18 20 21 22 23 26
27 35 37 41 43 45 46 47 53 57
1
To detect Keyboard backlight, SMC will
tristate SMC_SYS_KBDLED:
LOW = keyboard backlight present
HIGH= keyboard backlight not present
BOM OPTION: KBDLED_YES
A
TURNED ON FOR BEST MLB CONFIG
R5853 ALWAYS PRESENT
SMC_SYS_KBDLED
IN
40
SMC_KDBLED_PRESENT_L
6
49
R5853
470K
1/16W MF-LF
KB_BL
R5854
5%
402
2
1
4.7K
5% 1/16W MF-LF
402
2
PP5V_S0
6 7
37 42 47 61 64 65 67 68
70 72
KB_BL
1
C5850
1UF
10% 10V
2
X5R
NO STUFF
R5852
1/16W MF-LF
402-1
10K
5%
402
6
CTRL
CRITICAL
GND
2
U5850
LT3491
1
2
8
7 6
5
4
3
2
1
8 7
6
5
4
3
D
C
D
C
Analog SMS
R5921 PULLS UP SMS_PWRDN TO TURN OFF SMS WHEN PIN IS NOT BEING DRIVEN BY SMC
PP3V3_S3
6 7
20 25 29 30 43 48 68
1 5 2
4
3 6 9
U5920
AP344ALH
FS PD
CRITICAL
ST
RES RES
NC NC NC
VDD
LGA
GND
14
12
NC NC NC
SMS_X_AXIS
10
SMS_Y_AXIS
8
SMS_Z_AXIS
11
NC
13
NC
16
NC
VOUTX
VOUTY
VOUTZ
7
B
40 50
IN
SMS_PWRDN
40 50
MAKE_BASE=TRUE
SMS_PWRDN
R5921
10K
1/16W MF-LF
402
1
5%
2
SMS_SELFTEST
R5922
10K
5% 1/16W MF-LF 402
NC
NC NC NC
1
2
15
1
C5922
0.1UF
10% 16V
2
X5R 402
1
C5923
0.01UF
10% 16V
2
CERM 402
1
2
1
C5924
0.01UF
10% 16V
2
CERM 402
C5926
10UF
20% 4V X5R 603
1
C5925
0.01UF
10% 16V
2
CERM 402
40
OUT
40
OUT
40
OUT
A
Desired orientation when placed on board top-side:
+Y
Front of system
+Z (up)
Circle indicates pin 1 location when placed in correct orientation
+X
Sudden Motion Sensor (SMS)
SYNC_MASTER=K19_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
APPLE INC.
SCALE
D
NONE
DRAWING NUMBER
051-7903
SHT
SYNC_DATE=02/05/2009
REV.
A
OF
8350
B
A
8
7 6
5
4
3
2
1
DEBUG_ADC
1
C6003
10UF
20%
6.3V
2
X5R 603
PLACEMENT_NOTE=PLACE CLOSE TO U4900
0
DEBUG_ADC
R6002
0
1 2
5% 1/16W MF-LF
402
DEBUG_ADC
1
C6005
10UF
20%
6.3V
2
X5R 603
DEBUG_ADC
R6054
226K
1 2
1% 1/16W MF-LF
402
DEBUG_ADC
R6064
226K
1 2
1% 1/16W MF-LF
402
DEBUG SENSORS AND ADC
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
SIZE
D
SCALE
14 15
17
ADC_SDA
16
ADC_SCL
7
8
ISNS_ODD_IOUT
GAIN: 561X
ISNS_HDD_IOUT
GAIN: 845X
DEBUG_ADC
1
C6002
0.1UF
20% 10V
2
CERM 402
DEBUG_ADC
R6001
1 2
5% 1/16W MF-LF
402
ADC_VREF
ADC_REFCOMP DEBUG_ADC
1
C6004
0.1UF
20% 10V
2
CERM 402
DEBUG_ADC
1
C6040
0.1UF
20% 10V
2
CERM 402
PLACEMENT_NOTE=PLACE RC NEAR U6000
PLACEMENT_NOTE=PLACE RC NEAR U6000
SYNC_MASTER=K19_MLB
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
APPLE INC.
SMBUS_SMC_0_S0_SDA
PLACEMENT_NOTE=PLACE CLOSE TO U4900
SMBUS_SMC_0_S0_SCL
DEBUG_ADC
1
C6006
2.2UF
20%
6.3V
2
CERM 402-LF
ADC_CH4
DEBUG_ADC
1
C6054
2.2UF
10%
6.3V
2
X5R 402
ADC_CH5
DEBUG_ADC
1
C6064
2.2UF
10%
6.3V
2
X5R 402
SYNC_DATE=03/25/2009
DRAWING NUMBER
051-7903
SHT
NONE
D
40 43 46
BI
81
40 43 46 81
IN
51
51
C
B
A
REV.
A
OF
8351
CERM
CERM
10% 50V
402
10% 50V
402
3
1
2
DEBUG_ADC
1
2
DEBUG_ADC
1
2
DEBUG_ADC
R6082
226K
1 2
1% 1/16W MF-LF
402
DEBUG_ADC
C6001
10UF
20%
6.3V X5R 603
22 23 24
1 2 3 4 5
6
1
R6052
280K
1% 1/16W MF-LF 402
2
1
R6062
348K
1% 1/16W MF-LF 402
2
CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7
COM
9
12
13
U6000
LTC2309
QFN
DEBUG_ADC
GND
1011181920
3
2
DEBUG_ADC
R6053
280K
1 2
1% 1/16W MF-LF
402
5
6
DEBUG_ADC
R6063
348K
1 2
1% 1/16W MF-LF
402
ADC_CH7
DEBUG_ADC
1
C6082
2.2UF
10%
6.3V
2
X5R 402
29 37 38 39 41 49 51 53
21
DVDDAVDD
REFCOMP
THRM
PAD
25
V+ V-
THRM
9
DEBUG_ADC
C6053
470PF
1 2
10% 50V
CERM
402
V+ V-
THRM
9
DEBUG_ADC
C6063
470PF
1 2
10% 50V
CERM
402
51
PP5V_S3PP5V_S3
6 7 8 62 63 68
AD0 AD1
SDA SCL
VREF
DEBUG_ADC
U6040
OPA2330
8
DFN
1
4
U6040
OPA2330
8
DFN
7
4
8 7
PLACEMENT_NOTE=PLACE NEAR Q3450
XW6010
SM
PP5V_WLAN_F
29
1 2
D
PP5V_WLAN_F_XW
DEBUG_ADC
1
R6010
1M
1% 1/16W MF-LF 402
2
PP5V_WLAN_F_DIV
DEBUG_ADC
1
R6011
681K
1% 1/16W MF-LF 402
2
37
PLACEMENT_NOTE=PLACE RC NEAR U6000
DEBUG_ADC
R6012
226K
1 2
1% 1/16W MF-LF
402
DIVIDER: ~ 2/5
PP5V_S3
6 7 8
29 37 38 39 41 49 51 53
62 63 68
DEBUG_ADC
R6030
243
29 82
ISNS_AIRPORT_P
IN
C
1 2
1% 1/16W MF-LF
402
ISNS_AIRPORT_R_P
82
DEBUG_ADC
R6031
243
29 82
ISNS_AIRPORT_N
IN
1 2
1% 1/16W MF-LF
402
ISNS_AIRPORT_R_N
82
DEBUG_ADC
C6032
470PF
10% 50V
CERM
402
1
2
DEBUG_ADC
1
R6032
301K
1% 1/16W MF-LF 402
2
DEBUG_ADC
DEBUG_ADC
R6040
3.65K
IN
ISNS_1V5_S3_P
63 82
1 2
1/16W MF-LF
402
82
1%
ISNS_1V5_S3_R_P
DEBUG_ADC
R6041
3.65K
PP5V_S3
1 2
1/16W MF-LF
402
B
63 82
72 82
72 82
ISNS_1V5_S3_N
IN
ISNS_LCDBKLT_N
IN
ISNS_LCDBKLT_P
IN
6 7 8
29 37 38 39 41 49 51 53
62 63 68
A
82
1%
ISNS_1V5_S3_R_N
DEBUG_ADC
C6042
470PF
10% 50V
CERM
402
1
2
DEBUG_ADC
1
R6042
1M
1% 1/16W MF-LF 402
2
5
IN-
DEBUG_ADC
4
3
V+
U6050
INA210
SC70
GND
2
DEBUG_ADC
PLACEMENT_NOTE=PLACE NEAR Q4590
PP5V_SW_ODD
6
ADC_CH0
DEBUG_ADC
1
C6012
2.2UF
10%
6.3V
2
X5R 402
3
2
THRM
R6033
301K
1 2
1% 1/16W MF-LF
C6033
402
5
6
THRM
R6043
1M
1 2
1% 1/16W MF-LF
C6043
402
6
OUT
1
REFIN+
6
XW6020
SM
1 2
51 51
PP5V_SW_ODD_XW
DEBUG_ADC
1
R6020
1M
1% 1/16W MF-LF 402
2
PP5V_SW_ODD_DIV DEBUG_ADC
1
R6021
681K
1% 1/16W MF-LF 402
2
PLACEMENT_NOTE=PLACE RC NEAR U6000
5
DEBUG_ADC
R6022
226K
1 2
1% 1/16W MF-LF
402
1
2
DIVIDER: ~ 2/5
DEBUG_ADC
1
C6030
0.1UF
20% 10V
2
CERM 402
PLACEMENT_NOTE=PLACE RC NEAR U6000
GAIN: 1239X
DEBUG_ADC
R6034
226K
1 2
1% 1/16W MF-LF
402
ADC_CH2
DEBUG_ADC
1
C6034
2.2UF
10%
6.3V
2
X5R 402
51
V+ V-
9
DEBUG_ADC
U6030
OPA2330
8
DFN
1
4
ISNS_AIRPORT_IOUT
DEBUG_ADC
470PF
1 2
10% 50V
CERM
402
PLACEMENT_NOTE=PLACE RC NEAR U6000
GAIN: 273X
DEBUG_ADC
R6044
226K
1 2
1% 1/16W MF-LF
402
ADC_CH3
DEBUG_ADC
1
C6044
2.2UF
10%
6.3V
2
X5R 402
51
9
8
V+ V-
4
U6030
OPA2330
DFN
7
ISNS_1V5_S3_IOUT
DEBUG_ADC
470PF
1 2
10% 50V
CERM
402
DEBUG_ADC
1
C6050
0.1UF
20% 10V
2
CERM 402
PLACEMENT_NOTE=PLACE RC NEAR U6000
ISNS_LCDBKLT_IOUT
GAIN: 200X
DEBUG_ADC
R6074
226K
1 2
1% 1/16W MF-LF
402
ADC_CH6
DEBUG_ADC
1
C6074
2.2UF
10%
6.3V
2
X5R 402
69 72 74
51
ADC_CH1
DEBUG_ADC
C6022
2.2UF
10%
6.3V X5R 402
37 82
IN
37 82
IN
37 82
IN
37 82
IN
PLACEMENT_NOTE=PLACE NEAR D9701
PPVOUT_S0_LCDBKLT
6
ISNS_ODD_P
ISNS_ODD_N
ISNS_HDD_P
ISNS_HDD_N
4
XW6080
SM
1 2
29 37 38 39 41 49 51 53
51
51
51
51
51
51
51
51
I2C ADDRESS: 0X10 / 0X11 ADC RANGE: 0V TO 4.096V LSB: 0.001V
DEBUG_ADC
R6050
499
1 2
1% 1/16W MF-LF
402
ISNS_ODD_R_P
82
DEBUG_ADC
R6051
499
1 2
1% 1/16W MF-LF
402
ISNS_ODD_R_N
82
DEBUG_ADC
DEBUG_ADC
R6060
412
1 2
1% 1/16W MF-LF
402
ISNS_HDD_R_P
82
DEBUG_ADC
R6061
412
1 2
1% 1/16W MF-LF
402
ISNS_HDD_R_N
82
DEBUG_ADC
PPVOUT_S0_LCDBKLT_XW
DEBUG_ADC
1
R6080
1M
1% 1/16W MF-LF 402
2
PPVOUT_S0_LCDBKLT_DIV
DEBUG_ADC
1
R6081
47.0K
1% 1/16W MF-LF 402
2
6 7 8 62 63 68
DEBUG_ADC
1
C6000
0.1UF
20% 10V
2
CERM 402
ADC_CH0 ADC_CH1 ADC_CH2 ADC_CH3 ADC_CH4 ADC_CH5 ADC_CH6 ADC_CH7
C6052
470PF
C6062
470PF
PLACEMENT_NOTE=PLACE RC NEAR U6000
DIVIDER: ~ 1/22
8
7 6
5
4
3
2
1
8 7
6
5
4
3
D
PP3V3_S5
6 7
17 19 21 22 24 28 32 35
36 42 62 66 67 68 69 71 82
NO STUFF
1
R6190
10K
5% 1/16W MF-LF
402
C
SPI_CLK_MUX
PLACEMENT_NOTE=PLACE CLOSE TO U6100
SPI_MLB_CS_L
42
IN
R6150
0
1 2
5% 1/16W MF-LF
402
2
R6100
3.3K
1/16W MF-LF
402
5%
1
2
1
R6101
3.3K
5% 1/16W MF-LF 402
2
SPI_CLK
78
SPI_WP_L SPI_HOLD_L
C6100
0.1UF
20% 10V
CERM
402
CRITICAL
1
2
6
SCLK
1
CE*
3
WP*/ACC
7
HOLD*
8
VCC
U6100
32MBIT
SOP
OMIT
GND
4
SI/SIO0
SO/SIO1
MX25L3205DM2I-12G
5
2
SPI_MOSI
78
SPI_MISO_R
78
NO STUFF
1
R6191
10K
5% 1/16W MF-LF 402
2
R6105
0
1 2
5%
1/16W
PLACEMENT_NOTE=PLACE CLOSE TO U6100
MF-LF
402
R6152
0
1 2
SPI_MOSI_MUX
5%
PLACEMENT_NOTE=PLACE CLOSE TO U6100
1/16W MF-LF
402
SPI_MISO_MUX
42 42
ININ
42
OUT
D
C
MCP79 SPI Frequency Select
Frequency
B
25MHz is selected with R5190 and R5191 Any of the 4 frequencies can be selected with R6190, R6191, R5190 and R5191
31 MHz
42 MHz
25 MHz
1 MHz
SPI_MOSI
0
0
1
1
SPI_CLK
0
1
0
1
B
SPI ROM
A
SYNC_MASTER=K19_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
APPLE INC.
SCALE
D
NONE
DRAWING NUMBER
051-7903
SHT
52 83
SYNC_DATE=02/05/2009
REV.
A
OF
A
8
7 6
5
4
3
2
1
6 7 8
29 37 38 39 41 49 51 53
62 63 68
58 61 66 67 68 69 71 72 82 6 7
12 17 18 20 21 22 23 26 27
35 37 41 43 45 46 47 49 53 57
6
53
IN
53 55 57
53 54 58
55
OUT
55
OUT
57
IN
NC
6
NC
6
56
OUT
56
OUT
56
OUT
56
OUT
56
OUT
56
OUT
58
OUT
54
IN
54
IN
54
IN
58
IN
58
IN
58
IN
58
IN
NC
D
C
B
0.1UF
10% 16V X5R 402
1
2
3
CRITICAL
1
C6213
10UF
20%
6.3V
2
X5R 603
1
R6213
100K
5% 1/16W MF-LF 402
2
PP5V_S3
PP3V3_S0
PP4V5_AUDIO_ANALOG
VOLTAGE=4.5V MIN_LINE_WIDTH=0.15MM MIN_NECK_WIDTH=0.10MM
GND_AUDIO_HP_AMP
GND_AUDIO_CODEC
AUD_HP_PORT_L
AUD_HP_PORT_R AUD_HP_PORT_REF NC_AUD_LO1_P_L
NC_AUD_LO1_N_L
AUD_LO1_P_R AUD_LO1_N_R
AUD_LO2_P_L AUD_LO2_N_L AUD_LO2_P_R AUD_LO2_N_R
AUD_CODEC_MICBIAS
AUD_LI_P_L AUD_LI_REF AUD_LI_P_R
AUD_MIC_INP_L
AUD_MIC_INN_L
AUD_MIC_INP_R
AUD_MIC_INN_R
TP_AUD_DMIC_CLK
1
C6211
0.1UF
10% 16V
2
X5R 402
CRITICAL
C6221
10UF
20%
6.3V X5R 603-1
6
PP1V8_S0_AUDIO_DIG
VOLTAGE=1.8V MIN_LINE_WIDTH=0.10MM MIN_NECK_WIDTH=0.10MM
CRITICAL
1
1
C6220
2
2
CRITICAL
C6222
2.2UF
20%
6.3V CERM 402-LF
AUD_SPDIF_OUT_CHIP
CRITICAL
C6219
10UF
20% 16V
TANT-POLY
2012-LLP
10UF
20%
6.3V X5R
603-1
CS4206_FP CS4206_FN
CS4206_FLYP CS4206_FLYC
CRITICAL
1
1
C6223
2.2UF
20%
2
6.3V
2
CERM
402-LF
CS4206_FLYN
MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0V
1
2
VBIAS_DAC
5
AUDIO CODEC
APPLE P/N 353S2355
24
9
VA_REF
29
VBIAS_DAC
44
VHP_FILT+
41
VHP_FILT-
2
GPIO0/DMIC_SDA1
12
GPIO1/DMIC_SDA2
14
GPIO2
15
GPIO3
13
SENSE_A
45
FLYP
43
FLYC
42
FLYN
3
VL_HD
1
VL_IF
6
BITCLK
10
SYNC
8
SDI
5
SDO
11
RESET*
47
SPDIF_IN
48
SPDIF_OUT
DGND
VD
/SPDIF_OUT2
7
VA_HP
U6201
CS4206ACNZC
QFN
CRITICAL
THRM_PAD
AGND
49
C6218
25
46
VA
HPOUT_L HPOUT_R
HPREF
LINEOUT_L1+ LINEOUT_L1­LINEOUT_R1+ LINEOUT_R1-
LINEOUT_L2+ LINEOUT_L2­LINEOUT_R2+ LINEOUT_R2-
MICBIAS
VCOM
LINEIN_L+ LINEIN_C­LINEIN_R+
MICIN_L+ MICIN_L­MICIN_R+ MICIN_R-
VREF+_ADC
DMIC_SCL
26
0.1UF
10% 16V X5R 402
CRITICAL
C6224
38 40
39
35 34 36 37
31 30 32 33
16
28
21 22 23
18 17 19 20
27
4
8 7
CRITICAL
L6201
FERR-220-OHM
PP1V8_S0
6 7
17 23 66
IN
D
C
GND_AUDIO_HP_AMP
53 55 57
PP4V5_AUDIO_ANALOG
6
53
IN
57 58 61 66 67 68 69
PP3V3_S0
6 7
12 17 18 20 21 22 23 26
27 35 37 41 43 45 46 47 49 53 71 72 82
TP_AUD_GPIO_0
NC
TP_AUD_GPIO_2
NC
AUD_GPIO_3
56
OUT
AUD_SENSE_A
58
IN
20 78
IN
20 78
IN
20 78
OUT
20 78
IN
20 78
IN
57
IN
57
OUT
53 54 58
HDA_BIT_CLK HDA_SYNC
HDA_SDIN0
HDA_SDOUT HDA_RST_L
AUD_SPDIF_IN
AUD_SPDIF_OUT
GND_AUDIO_CODEC
1 2
0402
K19
1
R6218
10K
5% 1/16W MF-LF 402
2
K19I
1
R6219
10K
5% 1/16W MF-LF 402
2
R6211
39
1 2
5% 1/16W MF-LF
402
CRITICAL
C6210
4.7UF
20% 4V X5R 402
1
R6210
2.67K
1% 1/16W MF-LF 402
2
AUD_GPIO_1
AUD_SDI_R
R6212
39
1 2
5% 1/16W MF-LF
402
1
2
4
CRITICAL
C6216
1UF
C6217
10UF
20% 16V TANT-POLY 2012-LLP
10% 10V X5R 402-1
CRITICAL
1
1
2
2
MIN_LINE_WIDTH=0.30MM MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM
CS4206_VCOM
CS4206_VREF_ADC
CRITICAL
1
C6225
10UF
20% 16V
2
POLY-TANT CASE-B2-SM
1UF
TANT
0603-SM
20% 16V
1
2
1
C6215
0.1UF
2
MIN_NECK_WIDTH=0.20MM
10% 16V X5R 402
1
2
NC
C6214
B
4.5V POWER SUPPLY FOR CODEC
APPLE P/N 353S2234
CRITICAL
L6200
FERR-220-OHM
PP5V_S3
6 7 8
29 37 38 39 41 49 51 53
IN
62 63 68
53 57 58 61 66 67 68 69 71
PP3V3_S0
6 7
12 17 18 20 21 22 23 26
IN
27 35 37 41 43 45 46 47 49 72 82
1 2
0402
R6200
2.21K
1 2
1% 1/16W MF-LF
402
A
8
7 6
MIN_LINE_WIDTH=0.15MM MIN_NECK_WIDTH=0.10MM
VOLTAGE=5V
4V5_REG_IN
4V5_REG_EN
1
C6200
1UF
10% 10V
2
X5R 402-1
XW6200
SM
1 2
NOSTUFF
R6201
0
1 2
5% 1/16W MF-LF
402
XW6201
SM
1 2
MAX8840-4.5V
1
IN OUT
3
SHDN*
CRITICAL
1
C6201
1UF
10% 10V
2
X5R 402-1
CRITICAL
U6200
UDFN
BP
NC
GND
2
VOLTAGE=0V
MIN_LINE_WIDTH=0.15MM MIN_NECK_WIDTH=0.10MM
6
4
4V5_NR
5
MIN_LINE_WIDTH=0.15MM MIN_NECK_WIDTH=0.10MM VOLTAGE=4.5V
C6202
0.1UF
1 2
X7R-CERM
VOLTAGE=0V
PP4V5_AUDIO_ANALOG
CRITICAL
1
C6203
1UF
10% 10V
2
10% 16V
402
X5R 402-1
GND_AUDIO_CODEC
GND_AUDIO_HP_AMP
5
NOTES ON CODEC I/O
6
53
OUT
53 54 58
DIFF FSINPUT= 2.45VRMS SE FSINPUT= 1.22VRMS DAC1 FSOUTPUT= 1.34VRMS DAC2/3 FSOUTPUTDIFF= 2.67VRMS DAC2/3 FSOUTPUTSE= 1.34VRMS
AUDIO: CODEC/REGULATOR
A
A
53 55 57
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
APPLE INC.
4
3
2
SCALE
D
NONE
051-7903
SHT
53 83
1
REV.
OF
8 7
6
5
4
3
D
D
LINE INPUT VOLTAGE DIVIDER
CODEC RIN = 20K OHMS NET RIN = 20K OHMS FC = 8 HZ VIN = 2VRMS, CODEC VIN = 1.21 VRMS
CRITICAL
R6301
6.04K
57
IN
AUD_LI_L
MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM
1 2
1% 1/16W MF-LF
402
AUD_LI_L_DIV
MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM
C
1
R6302
16.5K
1% 1/16W MF-LF 402
2
AUD_LI_GND
57
IN
1
R6300
10
1% 1/16W MF-LF 402
2
GND_AUDIO_CODEC
53 58
IN
B
R6311
6.04K
AUD_LI_R
57
IN
MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM
1 2
1% 1/16W MF-LF
402
MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM
AUD_LI_R_DIV
MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM
1
R6312
16.5K
1% 1/16W MF-LF 402
2
C6301
3.3UF
1 2
10% 10V
CERM-X5R
805-1
CRITICAL
C6302
3.3UF
1 2
10% 10V
CERM-X5R
805-1
CRITICAL
C6312
3.3UF
1 2
10% 10V
CERM-X5R
805-1
CRITICAL
C6311
3.3UF
1 2
10% 10V
CERM-X5R
805-1
MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM
CRITICAL NOSTUFF
1
C6303
15PF
5% 50V
2
CERM 402
MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM
CRITICAL NOSTUFF
1
C6313
15PF
5% 50V
2
CERM 402
MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM
AUD_LI_P_L
AUD_LI_REF
AUD_LI_P_R
53
OUT
C
53
OUT
B
53
OUT
AUDIO: LINE INPUT FILTER
A
APPLE INC.
8
7 6
5
4
3
2
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
D
SCALE
NONE
051-7903
SHT
1
REV.
OF
8354
A
A
8 7
6
5
4
3
D
D
ZOBEL NETWORK & 1ST ORDER DAC FILTER PLACEHOLDER
R6501
0
1/16W MF-LF
402
10% 16V
402
1 2
5% 1/10W MF-LF
1
603
2
1
2
R6511
1 2
1/10W MF-LF
NO STUFF CRITICAL
C6501
0.0022UF
NO STUFF CRITICAL
C6511
0.0022UF
0
5%
603
10% 50V
CERM
402
10% 50V
CERM
402
1
2
1
2
10% 16V
402
39
5%
402
1
39
5%
2
1
2
AUD_HP_PORT_L
53
C
IN
AUD_HP_ZOBEL_L
NC
CRITICAL
C6500
0.1UF
X7R-CERM
R6500
GND_AUDIO_HP_AMP
53 57
IN
R6510
1/16W MF-LF
AUD_HP_ZOBEL_R
NC
53
AUD_HP_PORT_R
IN
CRITICAL
C6510
0.1UF
X7R-CERM
B
AUD_HP_L
1
R6502
2.21K
1% 1/16W MF-LF 402
2
1
R6512
2.21K
1% 1/16W MF-LF 402
2
AUD_HP_R
57
OUT
57
OUT
C
B
AUDIO: HEADPHONE FILTER
A
8
7 6
5
4
3
SYNC_MASTER=K19_MLB
APPLE INC.
2
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
D
SCALE
051-7903
NONE
SHT
SYNC_DATE=02/05/2009
OF
8355
1
A
REV.
A
8 7
6
5
4
3
3X MONO SPEAKER AMPLIFIERS (SSM2315)
APN: 353S2500
GAIN = 6DB 1ST ORDER FC (L&R) = 120 HZ +/- 30% 1ST ORDER FC (SUB) = 58HZ +/- 30%
D
PP5V_S3_AUDIO_AMP
8
56
53
AUD_LO2_P_L
IN
53
AUD_LO2_N_L
IN
AUD_GPIO_3
53
IN
AUD_SPKRAMP_SHUTDOWN_L
56
L6611
FERR-1000-OHM
1 2
L6601
FERR-1000-OHM
1 2
0402
L6610
FERR-1000-OHM
1 2
0402
0402
CRITICAL
CRITICAL
AUD_SPKRAMP_INP_L
CRITICAL
AUD_SPKRAMP_INN_L
1
R6601
100K
5% 1/16W MF-LF
402
2
CRITICAL
C6611
0.033UF
1 2
10% 16V X5R 402
CRITICAL
C6610
0.033UF
1 2
10% 16V X5R 402
CRITICAL
C6612
TANT-POLY
CASE-A4
SSM2315L_P SSM2315L_N
47UF
20%
6.3V
1
2
C1 A1
C2
PLACE C6610 CLOSE TO VDD PIN
B1
VDD
U6610
SSM2315
WLCSP
IN­IN+
CRITICAL
SD*
GND
B3
A2
PVDD
B2
OUT+ OUT_
CRITICAL
1
C6613
0.1UF
10% 16V
2
X5R 402
MIN_LINE_WIDTH=0.30 mm
C3 A3
SPKRAMP_L_OUT_P SPKRAMP_L_OUT_N
56 82
56 82
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_L_OUT_P
56 82
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM
SPKRAMP_L_OUT_N
56 82
SPEAKER CHECKPOINTS
R6610
1/16W MF-LF
402
R6611
1/16W MF-LF
402
MIN_LINE_WIDTH=0.30 mm
0
12
5%
0
12
5%
MIN_NECK_WIDTH=0.20 MM
SPKRCONN_L_OUT_P
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM
SPKRCONN_L_OUT_N
6
57 82
OUT
6
57 82
OUT
D
C
PP5V_S3_AUDIO_AMP
8
56
53
53
AUD_LO2_P_R
IN
AUD_LO2_N_R
IN
AUD_SPKRAMP_SHUTDOWN_L
56
L6620
FERR-1000-OHM
1 2
L6621
FERR-1000-OHM
1 2
0402
CRITICAL
0402
AUD_SPKRAMP_INP_R
CRITICAL AUD_SPKRAMP_INN_R
CRITICAL
C6621
0.033UF
1 2
10% 16V X5R 402
CRITICAL
C6620
0.033UF
1 2
10% 16V X5R 402
CRITICAL
C6622
TANT-POLY
SSM2315R_P
SSM2315R_N
47UF
6.3V
CASE-A4
20%
1
2
C1 A1
C2
PLACE C6620 CLOSE TO VDD PIN
B1
VDD
U6620
SSM2315
WLCSP
IN­IN+
CRITICAL
SD*
GND
B3
A2
PVDD
B2
OUT+ OUT_
CRITICAL
1
C6623
0.1UF
10% 16V
2
X5R 402
C3 A3
SPKRAMP_R_OUT_P SPKRAMP_R_OUT_N
56 82
56 82
B
PP5V_S3_AUDIO_AMP
8
56
CRITICAL
1 2
10% 10V
CERM
402
CRITICAL
C6630
0.068UF
1 2
10% 10V
CERM
402
SSM2315S_P
SSM2315S_N
L6630
FERR-1000-OHM
53
53
A
AUD_LO1_P_R
IN
AUD_LO1_N_R
IN
AUD_SPKRAMP_SHUTDOWN_L
56
1 2
L6631
FERR-1000-OHM
1 2
0402
0402
CRITICAL AUD_SPKRAMP_INP_SUB
CRITICAL
AUD_SPKRAMP_INN_SUB
CRITICAL
C6631
0.068UF
C6632
100UF
20%
6.3V TANT
CASE-AL1
1
2
C1 A1
C2
PLACE C6630 CLOSE TO VDD PIN
B1
VDD
U6630
SSM2315
WLCSP
IN­IN+
CRITICAL
SD*
GND
A2
B3
PVDD
B2
OUT+ OUT_
CRITICAL
1
C6633
0.1UF
10% 16V
2
X5R 402
C3 A3
SPKRAMP_S_OUT_P SPKRAMP_S_OUT_N
56 82
56 82
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM
SPKRAMP_R_OUT_P
56 82
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM
SPKRAMP_R_OUT_N
56 82
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM
SPKRAMP_S_OUT_P
56 82
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM
SPKRAMP_S_OUT_N
56 82
R6620
0
5% 1/16W MF-LF
402
R6621
0
5% 1/16W MF-LF
402
R6630
0
5% 1/16W MF-LF
402
R6631
0
5% 1/16W MF-LF
402
12
12
12
12
APPLE INC.
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM
SPKRCONN_R_OUT_P
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM
SPKRCONN_R_OUT_N
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM
SPKRCONN_S_OUT_P
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM
SPKRCONN_S_OUT_N
OUT
OUT
OUT
OUT
AUDIO:SPEAKER AMP
SYNC_MASTER=K19_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
D
SCALE
NONE
6
57 82
6
57 82
6
57 82
6
57 82
051-7903
SHT
56 83
SYNC_DATE=02/05/2009
REV.
OF
C
B
A
A
8
7 6
5
4
3
2
1
8 7
6
5
AUDIO JACK 1 LO/HP JACK, SPDIF TX
4
3
D
72 82 53 57 58 61 27 35 37 41
PP3V3_S0
6 7
12 17 18
20 21 22 23 26 43 45 46 47 49 66 67 68 69 71
APN: 514-0671
J6700
SPDIF-TXRX-K24
F-RT-TH
6
MIC
5
DETECT
2
SWITCH
1
LEFT
3
RIGHT
4
GND
AUDIO
PINS
SWITCH
LEFT
RIGHT
GROUND
7 8 9
10 11 12 13
5 2 1 3 4
A - VIN B - VCC
C
OPERATING VOLTAGE 3.3
C - GND
POF
SHELL
SHIELD
71 72 82 43 45 46 47 49
PP3V3_S0
6 7
12 17 18 20
21 22 23 26 27 35 37 41 53 57 58 61 66 67 68 69
B
APN: 514-0635
J6750
AUDIO-RCVR-M97
F-RT-TH5
DETECT FOR PLUG TYPE
AUDIO
6
A - VDD
7
B - GND
SHELL
SHIELD
PINS
8
9 10 11 12
C - VOUT
OPERATING VOLTAGE 3.3
POF
A
AUD_CONNJ1_SLEEVE2 AUD_CONNJ1_SLEEVEDET AUD_CONNJ1_TIPDET AUD_CONNJ1_TIP AUD_CONNJ1_RING
AUD_CONNJ1_SLEEVE
1
C6700
0.1UF
10% 16V
2
X5R 402
AUD_J2_OPT_OUT
1
C6750
1UF
10% 10V
2
X5R 402-1
1
C6701
2.2UF
20%
6.3V
2
CERM 402-LF
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.10 MM VOLTAGE=0V
GND_CHASSIS_AUDIO_JACK
8
57
R6749
4.7
1 2
1/16W MF-LF
402
AUD_CONNJ2_SLEEVE
AUD_CONNJ2_TIPDET
AUD_CONNJ2_RING
AUD_CONNJ2_TIP
AUD_CONNJ2_SLEEVEDET
CRITICAL
DZ6703
6.8V-100PF
2
402
1
6.8V-100PF
CRITICAL
2
DZ6706
6.8V-100PF
402
1
CRITICAL
DZ6704
GND PATCH
5%
CRITICAL
DZ6754
6.8V-100PF CRITICAL
2
DZ6756
6.8V-100PF
402
1
402
402
XW6701
SM
1 2
XW6702
SM
1 2
R6701
0
1 2
5% 1/16W MF-LF
402
2
1
2
1
2
2
1
6.8V-100PF
CRITICAL
DZ6701
6.8V-100PF
402
1
CRITICAL
DZ6758
6.8V-100PF
CRITICAL
DZ6751
6.8V-100PF
402
CRITICAL
DZ6700
402
402
L6703
FERR-1000-OHM
1 2
0402
L6702
FERR-1000-OHM
1 2
0402
CRITICAL
L6701
FERR-220-OHM-2.5A
1 2
0603
2
1
1
C6705
100PF
5% 50V
2
CERM 402
FERR-220-OHM
FERR-1000-OHM
FERR-1000-OHM
FERR-220-OHM
2
1
FERR-1000-OHM
1
C6756
100PF
5% 50V
2
CERM 402
CRITICAL
CRITICAL
L6707
FERR-220-OHM
1 2
0402
CRITICAL
L6704
FERR-220-OHM
1 2
0402
CRITICAL
L6706
FERR-220-OHM
1 2
0402
R6700
10K
1 2
5% 1/16W MF-LF
402
L6705
FERR-1000-OHM
1 2
0402
GND_CHASSIS_AUDIO_JACK
L6751
1 2
0402
CRITICAL
L6754
1 2
0402
CRITICAL
L6756
1 2
0402
CRITICAL
L6758
1 2
0402
CRITICAL
L6752
1 2
0402
CRITICAL
GND_CHASSIS_AUDIO_JACK
CRITICAL
CRITICAL
AUD_SPDIF_OUT
HS_MIC_HI
HS_MIC_LO
AUD_HP_PORT_REF
GND_AUDIO_HP_AMP
AUD_HP_R
AUD_HP_L
AUD_J1_SLEEVEDET_R
AUD_J1_TIPDET_R
AUD_SPDIF_IN
AUD_LI_R
AUD_LI_L
AUD_LI_GND
AUD_J2_TIPDET_R
8
57
8
AUDIO JACK 2 LINE IN JACK, SPDIF RX
53
IN
MIC CONNECTOR
D
CRITICAL
58
OUT
BI_MIC_LO
6
58
OUT
53
BI
53 55
OUT
55
BI
55
BI
58
OUT
58
OUT
58
OUT
6
58
OUT
6
58
OUT
BI_MIC_SHIELD BI_MIC_HI
APN: 518S0520
SPEAKER CONNECTOR
APN: 518S0519
SPKRCONN_L_OUT_P
6
56 82
IN
SPKRCONN_L_OUT_N
6
57
56 82
IN
J6780
78171-0003
M-RT-SM
4
1 2 3
5
CRITICAL
78171-0002
J6781
M-RT-SM 3
1 2
4
C
CRITICAL
J6782
78171-0004
APN: 518S0521
SPKRCONN_S_OUT_P
6
56 82
IN
SPKRCONN_S_OUT_N
6
56 82
IN
SPKRCONN_R_OUT_P
6
56 82
IN
SPKRCONN_R_OUT_N
6
56 82
53
OUT
54
BI
54
BI
54
58
OUT
IN
NOSTUFF CRITICAL
C6781
33PF
CERM
50V 402
1
5%
2
NOSTUFF
CRITICAL
C6783
33PF
5%
NOSTUFF
CRITICAL
1
C6782
33PF
5% 50V
2
CERM 402
SYNC_MASTER=CASEYHARDY_K19
50V
CERM
402
NOSTUFF CRITICAL
1
1
C6784
33PF
5% 50V
2
2
CERM 402
AUDIO: JACKS
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
D
APPLE INC.
SCALE
NONE
M-RT-SM
5
1 2 3 4
6
051-7903
SHT
SYNC_DATE=03/20/2009
REV.
A
OF
8357
B
A
8
7 6
5
4
3
2
1
8 7
6
5
4
3
CODEC OUTPUT SIGNAL PATHS
FUNCTION HP/LINE OUT SATELLITES SUB SPDIF OUT
VOLUME 0X02 (2) 0X04 (4) 0X03 (3) N/A
CONVERTER 0X02 (2) 0X04 (4) 0X03 (03) 0X08 (8)
PIN COMPLEX 0X09 (9,A) 0X0B (11) 0X0A (10) 0X10 (16)
CODEC INPUT SIGNAL PATHS
D
FUNCTION LINE IN SPDIF IN BUILT-IN MIC HEADSET MIC
AUD_SENSE_A
53 58
OUT
PP3V3_S0_AUDIO_F
58
AUD_J1_TIPDET_R
57 58
IN
1
R6801
220K
5% 1/16W MF-LF 402
2
R6802
47K
1 2
5% 1/16W MF-LF
402
C
GND_AUDIO_CODEC
53 54 58
PP3V3_S0_AUDIO_F
58
AUD_J1_SLEEVEDET_R
57 58
IN
GND_AUDIO_CODEC
53 54 58
PP3V3_S0_AUDIO_F
B
58
EXTRACT_BUFF
AUD_J1_TIPDET_R
57 58
GND_AUDIO_CODEC
53 54 58
MIN_LINE_WIDTH=0.1MM MIN_NECK_WIDTH=0.1MM PP3V3_S0_AUDIO_F
58
VOLTAGE=3.3V
53 57 58 61 66 67 68 69 71
6 7
12 17 18 20 21 22 23 26
IN
27 35 37 41 43 45 46 47 49 72 82
PP3V3_S0
AUD_J1_TIPDET_R
57 58
FERR-1000-OHM
A
GND_AUDIO_CODEC
53 54 58
PLACE L6800/C6800 CLOSE TO U6800
1
R6804
220K
5% 1/16W MF-LF 402
2
EXTRACT_BUFF
R6864
220K
1 2
5% 1/16W MF-LF
402
SSM6N15FEAPE
R6860
15K
1 2
TIPDET_FILT
5% 1/16W MF-LF
402
CRITICAL
L6862
1 2
0402
C6861
0.1UF
10V
CERM
402
1
C6860
0.1UF
20%
2
CERM
EXTRACT_BUFF
20%
CONVERTER 0X05 (5) 0X07 (7) 0X06 (6) 0X06 (6)
APN:376S0613
Q6800
SSM6N15FEAPE
AUD_J1_DET_RC
1
2
R6803
220K
1 2
5% 1/16W MF-LF
402
SSM6N15FEAPE
1
C6802
0.01UF
10% 16V
2
CERM 402
AUD_J1_TIPDET_INV
EXTRACT_BUFF
Q6803
SOT563
2
10V 402
EXTRACTION NOTIFICATION
APN:353S2401
SOT563
5
C6801
0.1UF
10V
20% CERM
402
AUD_J1_SLEEVEDET_INV
Q6800
SOT563
2
EXTRACT_BUFF
R6865
100K
1 2
5% 1/16W MF-LF
402
EXTRACT_BUFF
6
D
SSM6N15FEAPE
SG
1
EXTRACT_DEBOUNCE
TPS3801E18DCK
4
VDD
U6860
5 3
1
2
MR*
SC-70-1
GND
1 2
AUD_PERPH_DET_R
RST*
PIN COMPLEX 0X0C (12,C) 0X0F (15) 0X0D (13,B,RIGHT) 0X0D (13,V22,B,LEFT)
AUD_OUTJACK_INSERT_L
3
D
SG
4
6
D
SG
1
3
Q6803
SOT563
D
5
SG
4
R6861
1 2
100
5% 1/16W MF-LF
402
MUTE CONTROL
N/A GPIO_3 GPIO_3 N/A
VREF
N/A N/A MIC_BIAS (80%) MIKEY
PORT A DETECT (HEADPHONES)
1
R6806
39.2K
1% 1/16W MF-LF 402
2
AUD_PORTA_DET_L
3
Q6801
SSM6N15FEAPE
SOT563
AUD_IP_PERIPHERAL_DET
D
5
SG
4
AUD_J1_SLEEVEDET_R
57 58
OUT
DET ASSIGNMENT 0X09 (A) N/A N/A 0X0C (B)
DET ASSIGNMENT 0X0C (12,C) N/A N/A MIKEY
Q6801
SSM6N15FEAPE
SOT563
16
PORT B DETECT(SPDIF DELEGATE)
1
R6805
20.0K
1% 1/16W MF-LF 402
2
NC
2
AUD_PORTB_DET_L
6
D
SG
1
53 58
57
OUT
IN
53 54 58
NC
AUD_SENSE_A
PP3V3_S0_AUDIO_F
58
AUD_J2_TIPDET_R
GND_AUDIO_CODEC
1
R6811
270K
5% 1/16W MF-LF 402
2
R6812
47K
1 2
5% 1/16W MF-LF
402
57 58 61 66 67 68 69 71 72 82
PP3V3_S0
6 7
12 17 18 20 21 22 23 26
27 35 37 41 43 45 46 47 49 53
20 43 72 78
IN
20 43 72 78
BI
20
OUT
8
18
IN
53
OUT
53
OUT
53 54 58
AUD_CODEC_MICBIAS
53
IN
GND_AUDIO_CODEC
53 54 58
AUD_MIC_INP_R
53
OUT
AUD_MIC_INN_R
53
OUT
GND_AUDIO_CODEC
53 54 58
XW6851
SM
1 2
PORT C DETECT (LINE-IN)
1
R6813
10K
1% 1/16W MF-LF
402
2
Q6802
SSM3K15FV
SOD-VESM-HF
AUD_J2_DET_RC
1
C6811
0.1UF
10V
20%
2
CERM
402
AUD_INJACK_INSERT_L
D
1
G S
PULLUPS ON MCP PAGE
SMBUS_MCP_1_CLK SMBUS_MCP_1_DATA AUD_I2C_INT_L AUD_IPHS_SWITCH_EN
AUD_MIC_INP_L
AUD_MIC_INN_L
GND_AUDIO_CODEC
R6850
100
1 2
1% 1/16W MF-LF
402
CRITICAL
C6850
0.1UF
C6851
0.1UF
1 2
10% 25V X5R 402
1 2
10% 25V X5R 402
R6853
2.4K
1 2
1%
1/16W
MF
402-1
CRITICAL
3
APN:376S0612
2
PORT B LEFT(HEADSET MIC)
CRITICAL
FERR-1000-OHM
1 2
MIKEY
CRITICAL
C6886
0.1UF
1 2
HP=80HZ, LP=8.82KHZ
MIKEY
L6880
0402
CRITICAL
MIKEY
C6880
10UF
6.3V
20%
603 X5R
MIKEY
1
R6880
100K
5% 1/16W MF-LF
402
2
MIKEY
CRITICAL
C6883
0.1UF
1 2
10% 25V X5R 402
10% 25V X5R
XW6880
402
SM
1 2
MIN_LINE_WIDTH=0.1MM MIN_NECK_WIDTH=0.1MM VOLTAGE=3.3V
PP3V3_S0_HS_RX
1
2
6
SCL
5
SDA
7
INT*
8
ENABLE
HS_MIC_HI_RC
MIKEY
1
R6883
100K
5% 1/16W MF-LF 402
2
PORT B RIGHT(BUILT-IN MIC)
R6851
2.4K
MIC_BIAS_FILT
CRITICAL
1
C6852
2.2UF
20%
6.3V
2
TANT 402
1 2
1%
1/16W
MF
402-1
BI_MIC_HI_F
1
R6852
100K
2
5% 1/16W MF-LF 402
BI_MIC_LO_F
CRITICAL
C6853
0.001UF
50V
CERM
402
10%
1
2
HP=80HZ
NC
3
AVDD
U6880
CD3275
DRC
MICBIAS
DETECT
BYPASS
GND THM
9
4
CRITICAL
1
C6854
27PF
5%
2
CERM
DRC MIKEY
APN:353S2256
MIKEY
1
HS_MIC_BIAS
2
HS_SW_DET
10
11
MIKEY
C6881
0.01UF
16V
10%
402
CERM
R6884
MIKEY
1
C6884
0.0082UF
25V
10%
2
402X7R
CRITICAL
FERR-1000-OHM
50V 402
FERR-1000-OHM
HS_RX_BP
1
MIKEY
2
R6881
1K
1% 1/16W MF-LF
402
MIKEY
2.2K
1 2
5% 1/16W MF-LF
402
L6850
1 2
0402
L6851
1 2
0402
SYNC_MASTER=K19_MLB
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
APPLE INC.
MIKEY
CRITICAL
1
C6882
2.2UF
20%
6.3V
2
TANT 402
GND_AUDIO_CODEC
MIKEY
1
1
R6882
2.2K
5% 1/16W MF-LF 402
2
2
MIKEY
1
C6885
27PF
5%
2
CERM
CRITICAL
BI_MIC_HI
BI_MIC_LO
BI_MIC_SHIELD
HS_MIC_HI
50V 402
HS_MIC_LO
IN
IN
IN
57
IN
57
IN
6
57
6
57
6
57
AUDIO: JACK TRANSLATORS
SYNC_DATE=03/17/2009
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
DRAWING NUMBER
SIZE
D
SCALE
NONE
051-7903
SHT
58 83
D
53 54 58
C
B
A
REV.
A
OF
8
7 6
5
4
3
2
1
8 7
MagSafe DC Power Jack
6
5
4
3
CRITICAL
J6900
D
78048-0573
M-RT-SM
1
PWR
2
PWR
3
GND
4
GND
5
SIG
PP18V5_DCIN_FUSE
6
MIN_LINE_WIDTH=1mm MIN_NECK_WIDTH=0.20mm VOLTAGE=18.5V
3
1
2
CRITICAL
SC-75
RCLAMP2402B
D6900
1
C6905
2
40
NO STUFF
1-Wire OverVoltage Protection
ADAPTER_SENSE
6
The chassis ground will otherwise float and can send transients onto ADAPTER_SENSE when AC is
C
connected.
CRITICAL
F6905
6AMP-24V
1 2
0.01UF
20% 50V CERM 603
BI
1206-2
PLACEMENT_NOTE=Place near L6900
SYS_ONEWIRE
1
R6929
2.0K
5% 1/16W MF-LF 402
2
4
CRITICAL
1
VCC
U6900
MAX9940
SC70-5
GND
2
SMC_BC_ACOK_VCC
5
EXTINT
NC
3
NC
PPDCIN_S5
PP3V42_G3H
1
C6908
0.1UF
20%
PLACEMENT_NOTE=PLACE NEAR U6900 and U6901
10V
2
R6961
100
5%
MF-LF
12
1/16W
C6955
0.001UF
CERM 402
10% 50V
CERM
402
1
2
TC7SZ08AFEAPE SOT665
5
2
Y
U6901
3
SMC_LID
A
1
B
402
4
40 41 48
OUT
20 21 24 38 40 41 42 43
60 81 40 43
59
81 40 43 59 60
6 7
20 21 24 38 40 41 42 43 45
48 59 60 67
PP3V42_G3H
6 7 45 48 59 60 67
SMC_LID_R
6
SMBUS_SMC_BSA_SDA
6
BI
SMBUS_SMC_BSA_SCL
6
BI
C6953
SMC_BC_ACOK
1
C6951
0.1UF
10% 25V
2
X5R 402
1
C6952
47PF
5%
50V
2
CERM
402
40 41 60
IN
BIL CONNECTOR
516S0523
CRITICAL
J6955
CPB6312-0101F
F-ST-SM
2
NC
10
1
47PF
5%
50V
2
CERM
402
1314
1 34
NC
56 78 9 1112
1516
SMC_BIL_BUTTON_L
C6954
0.001UF
CERM
TO SMC
6
40 41
OUT
1
10% 50V
2
402
59 60
7
D
C
3.425V "G3Hot" Supply
Supply needs to guarantee 3.31V delivered to SMC VRef generator
PPVIN_G3H_P3V42G3H
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.3 mm
NC
VOLTAGE=18.5V
C6990
10UF
10% 25V X5R 805
1
2
6
VIN
U6990
LT3470A
DFN
8 4
SHDN*
CRITICAL
7
NC
NC
GND
5
3
BOOST
THRM
BIAS
PAD
9
P3V42G3H_BOOST
0.22UF
6.3V
DIDT=TRUE
20% X5R
402
1
2
CRITICAL
L6995
33UH
1 2
CDPH4D19FHF-SM
C6995
22pF
5%
50V
CERM
402
PP3V42_G3H
Vout = 3.425
<Ra>
1
R6995
1
348K
1% 1/16W
2
MF-LF 402
2
<Rb>
1
R6996
200K
1% 1/16W MF-LF 402
2
250mA max output
(Switcher limit)
1
C6999
22UF
20%
6.3V
2
X5R-CERM 603
6 7
20 21 24 38 40 41 42 43 45
48 59 60 67
B
C6994
SW
FB
P3V42G3H_SW
MIN_LINE_WIDTH=0.5 mm
2
MIN_NECK_WIDTH=0.25 mm
SWITCH_NODE=TRUE
1
P3V42G3H_FB
Vout = 1.25V * (1 + Ra / Rb)
7
59 60
PPDCIN_S5
R6905
47
1 2
5%
1/8W
MF-LF
805
35 44 45 60 62 63 64 73
PPDCIN_S5_P3V42G3H
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.3 mm VOLTAGE=18.5V
PPBUS_G3H
6 7
D6905
HN2D01JEAPE
SOT665
1
3
5
4
2
NC
518-0358
B
SHLD_PIN SHLD_PIN SHLD_PIN SHLD_PIN
CRITICAL
J6950
BAT-K19
M-RT-TH
P1 P2 P3 P4 P5 P6 P7 P8 P9
BATTERY CONNECTOR
1 2 3 4 5 6 7 8 9
10 11 12 13
SMBUS_SMC_BSA_SCL SYS_DETECT_L
6
SMBUS_SMC_BSA_SDA
GND_BATT_CHGND
6 8
CRITICAL
D6950
RCLAMP2402B
SC-75
1
2
3
PPVBAT_G3H_CONN
40 43 59 60 81
6
6 40 43 59 60 81
1
R6950
10K
5% 1/16W MF-LF
402
2
C6950
0.1UF
6
60
1
10% 25V
2
X5R 402
DC-In & Battery Connectors
A
8
7 6
5
4
3
SYNC_MASTER=K19_MLB
APPLE INC.
2
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
D
SCALE
051-7903
NONE
SHT
59 83
1
SYNC_DATE=03/18/2009
REV.
A
OF
A
8 7
6
5
4
3
FROM ADAPTER
PPDCIN_S5
7
59
2
D7005
1SS418
SOD-723-HF
1
D
C
ACIN pin threshold is 3.2V, +/- 50mV
Divider sets ACIN threshold at 13.07V
Input impedance of ~40K meets sparkitecture requirements
1
R7010
30.1K
1% 1/16W MF-LF
402
2
1
R7011
9.31K
1% 1/16W MF-LF
402
B
1
R7015
2
56.2K
1% 1/16W MF-LF 402
2
CHGR_VCOMP_R
C7015
0.001UF
CHGR_VNEG_R
1
C7016
470PF
10% 50V
2
CERM 402
20 21 24 38 40 41 42 43
10% 50V
CERM
402
R7016
3.01K
1/16W MF-LF
402
PP3V42_G3H
6 7 45 48 59 60 67
6
40 43 59 81
IN
6
40 43 59 81
BI
VREF = 3.2V, < 300uA
1
2
1
1%
2
1
C7002
1UF
10% 10V
2
X5R
402-1
SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA
CHGR_ACIN
CHGR_ICOMP CHGR_VCOMP CHGR_VNEG
81
CHGR_CSO_P CHGR_CSO_N
81
1
C7050
0.1uF
10% 16V
2
X5R 402
PP5V1_CHGR_VDD
60
MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5.1V
30mA max load
Inrush Limiter
1
R7060
470K
5% 1/16W MF-LF 402
2
CHGR_AGATE_DIV
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.3 mm
1
R7061
330K
5% 1/16W MF-LF 402
2
NC
C7060
0.1UF
R7001
4.7
1 2
1/16W MF-LF
402
19
VDD
CRITICAL
12
VHST
U7000
11
SCL
10
SDA
4
VREF
3
ACIN
5
ICOMP
7
VCOMP
OMIT
8
VNEG
18
CSOP
17
CSON
THRM_PAD
29
XW7000
1 2
10% 25V X5R 402
5%
VDDP
QFN
ISL6258A
(OD) 20V/V 32V/V
(OD)
AGND
6
26
SM
1
2
20
AGATE
BGATE
UGATE PHASE
LGATE
TRKL*
PGND
22
CSIP CSIN
DCIN
BOOT
AMON BMON ACOK
1 2 3
S
4
G
D
5 6 7 8
(CHGR_AGATE)
(CHGR_DCIN)
PP5V1_CHGR_VDDP
MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5.1V
C7001
1
CHGR_AGATE
28
CHGR_CSI_P
81
27
CHGR_CSI_N
81
16
CHGR_BGATE
2
CHGR_DCIN
25
CHGR_BOOT
24
CHGR_UGATE
23
CHGR_PHASE
21
CHGR_LGATE
13
TP_CHGR_TRKL
9
CHGR_AMON
15
CHGR_BMON
14
SMC_BC_ACOK
(CHGR_CSO_P) (CHGR_CSO_N)
(PPVBAT_G3H_CHGR_R)
CRITICAL
Q7060
HAT1128R01
SOI
1UF
402-1
10% 10V X5R
HAT1128R01
PPDCIN_S5_INRUSH
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=18.5V
1
2
CRITICAL
Q7065
45 60
OUT
45
OUT
40 41 59
OUT
SOI
1
C7020
0.047UF
10% 10V
2
CERM 402
C7022
0.1UF
Max Current = 8.5A (L7030 limit) f = 400 kHz
Reverse-Current Protection
PPDCIN_S5_CHGR_R
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=18.5V
1 2 3
10% 25V X5R 402
S
D
CHGR_SGATE_DIV
G
4
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.3 mm
5 6 7 8
R7021
1 2
1/16W MF-LF
R7022
1 2
1/16W MF-LF
1
1
C7021
0.1UF
10% 25V
2
2
X5R 402
1
C7035
0.1UF
10% 25V
2
X5R 402
DIDT=TRUE
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE DIDT=TRUE
DIDT=TRUE
R7051
10
1 2
1/16W MF-LF
402
10
5%
402
10
5%
402
4
4
5%
1
R7065
100K
5% 1/16W MF-LF
402
2
1
R7066
62K
5% 1/16W MF-LF
402
2
82
CHGR_CSI_R_P
CHGR_CSI_R_N
82
PPDCIN_S5_FET_CHGR
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=18.5V
5
1 2 3
5
CRITICAL
Q7035
RJK0305DPB
LFPAK-HF
1 2 3
R7052
10
1 2
5% 1/16W MF-LF
402
CHGR_SGATE
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.25 mm
152S0542
CRITICAL
Q7030
RJK0305DPB
LFPAK-HF
CRITICAL
L7030
3
4.7UH-10.2A
FDA1254F-SM
1
45 82
CHGR_CSO_R_P
82 45
CHGR_CSO_R_N
1
2
2
U7070
TL331
SOT23-5
4
CRITICAL
123
R7020
0.02
0.5% 1W MF 0612-1
4
CRITICAL
1
C7030
22UF
20% 25V
2
POLY-TANT CASE-D2-SM
C7032
1UF
10% 25V X5R 603-1
CRITICAL
R7050
1
2
PPVBAT_G3H_CHGR_REG
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=12.6V
0.01
0.5% 1W MF
0612-1
12 34
5
1
VCC
GND
3
2
NOSTUFF
D7040
1 2
1SS418
SOD-723-HF
CRITICAL
1
C7031
22UF
20% 25V
2
POLY-TANT CASE-D2-SM
C7033
1UF
10% 25V X5R 603-1
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=12.6V
1
C7034
0.001UF
10% 50V
2
X7R 402
CRITICAL
C7040
POLY-TANT
CASE-D2-SM
PPVBAT_G3H_CHGR_R
1
C7055
1UF
10% 25V
2
X5R
603-1
1
C7070
0.1uF
10% 16V
2
X5R 402
SGATE_P0V1_VREF
CRITICAL
1
F7040
8AMP-24V
1206-2
2
1
22UF
20% 25V
2
C7057
0.01uF
10% 16V
CERM
402
1
C7056
0.1UF
10% 16V
2
X5R 402
1
2
1
C7041
0.001UF
10% 50V
2
X7R 402
R7070
57.6K
1/16W MF-LF
R7071
1.82K
1/16W MF-LF
1 2 3
1
1%
402
2
1
1%
402
2
CRITICAL
Q7055
SI7137DP
SO-8
S
G
4
3
4
D
S G
D
Q7074
SSM6N15FEAPE
SOT563
5
5
AMON_CLAMP
TO SYSTEM
PPBUS_G3H
PPVBAT_G3H_CONN
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=12.6V
PP3V42_G3H
1
R7074
1M
5% 1/16W MF-LF 402
2
CHGR_AMON
R7075 clamps CHGR_AMON when charger is not powered to counter TL331 bias current.
6
D
Q7074
SSM6N15FEAPE
SOT563
2
S G
1
PP5V1_CHGR_VDD
6
59
45 60
6 7
35 44 45 59 62 63 64 73
6 7
20 21 24 38 40 41 42 43 45
48 59 60 67
60
D
C
B
A
PART NUMBER
353S1811
1
2
8
C7042
0.033UF
10% 16V X5R 402
QTY
1
IC,ISL6258,BAT CHARGER,28P,4X4,QFN,L
1
IC,ISL6258A,BAT CHARGER,4X4MM,QFN28
DESCRIPTION
1
2
U7000 U7000
1
C7011
0.01UF
10% 16V
2
CERM 402
CRITICAL
CRITICAL CRITICAL ISL6258A353S1832
C7005
BOM OPTION
ISL6258
C7000
1UF
10% 10V X5R
402-1
REFERENCE DES
7 6
0.1UF
1
10% 25V
2
X5R 402
GND_CHGR_AGND
MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V
2S Battery Default
3S Battery Default
1
C7026
0.001UF
10% 50V
2
CERM 402
5
PBus Supply & Battery Charger
SHT
60 83
1
SYNC_DATE=03/18/2009
REV.
A
OF
A
SYNC_MASTER=K19_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
APPLE INC.
4
3
2
SCALE
D
051-7903
NONE
10% 50V X7R 402
CRITICAL
L7100
1 2
MPCG1040-SM
XW7103
SM
1 2
10K
1% 1/16W MF-LF
402
CRITICAL
L7101
1 2
MPCG1040-SM
XW7101
SM
1 2
10K
1% 1/16W MF-LF
402
SYNC_MASTER=K19_MLB
1
2
C7103
0.22UF
1 2
CERM
C7104
0.22UF
1 2
CERM
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
C7152
0.001UF
0.36UH-26A-1.05MOHM
IMVP6_VSUM1
61
R7100
1 2
1
R7101
3.65K
1% 1/10W MF-LF 603
2
0.36UH-26A-1.05MOHM
IMVP6_VSUM2
61
R7105
1 2
1
R7106
3.65K
1% 1/10W MF-LF 603
2
APPLE INC.
CRITICAL
1
C7153
68UF
20% 16V
2
POLY-TANT CASE-D2E-SM
10% 10V
402
10% 10V
402
IMVP6 CPU VCore Regulator
NOTICE OF PROPRIETARY PROPERTY
PPVCORE_S0_CPU
44A MAX CURRENT
XW7104
SM
12
IMVP6_VO1
61
1
R7104
1
5% 1/16W MF-LF 402
2
XW7102
SM
12
IMVP6_VO2
61
1
R7107
1
5% 1/16W MF-LF 402
2
SIZE
D
SCALE
NONE
1
C7154
1UF
10% 25V
2
X5R 603-1
DRAWING NUMBER
051-7903
SHT
61 83
6 7
C7156
0.001UF
C7157
0.001UF
1
10% 50V
2
X7R 402
1
10% 50V
2
X7R 402
SYNC_DATE=02/05/2009
REV.
OF
10 11 44
D
C
B
A
A
1
C7109
1UF
10% 25V
2
X5R 603-1
1 2 6 7
D
S
3 4
1 2 6 7
D
S
3 4
3
CRITICAL
Q7100
IRF6710
G
3
CRITICAL
Q7101
IRF6795
DIRECTFET-MX
CRITICAL
Q7102
IRF6710
G
3
CRITICAL
Q7103
IRF6795
DIRECTFET-MX
CRITICAL
1
C7155
68UF
20% 16V
2
POLY-TANT CASE-D2E-SM
S1
1
D
2 5 64
S
(IMVP6_PHASE1)
(IMVP6_ISEN1)
S1
1
D
2 5 64
S
(IMVP6_PHASE2)
(IMVP6_ISEN2)
(IMVP6_VSUM)
(IMVP6_VO)
I848I849
8 7
PPBUS_CPU_IMVP_ISNS
7
45 65
R7120
10
1 2
1% 1/16W MF-LF
402
PP5V_S0
6 7
37 42 47 49
64 65 67 68 70 72
D
68 69 71 72 82 37 41 43 45 46 47
PP3V3_S0
6 7
12 17 18 20
21 22 23 26 27 35 49 53 57 58 66 67
35 65 66 67
PP1V05_S0
6 7 9
10 11 12 13
16 17 19 21 22 23
R7119
PM_DPRSLPVR
20 75
IN
CPU_PROCHOT_L
9
13 41 75
OUT
LAYOUT NOTE: Place R7126 in hot spot of reg circuit.
CRITICAL
R7126
C
470K
402
1
2
1 2
(IMVP6_NTC)
499
1% 1/16W MF-LF
402
C7110
0.01uF
R7112
1 2
1/16W MF-LF
R7121
1 2
1/16W MF-LF
R7198
1 2
1/16W MF-LF
10% 16V
CERM
402
10
1%
402
10
1%
402
0
5%
402
1
2
IMVP6_NTC_R
1
R7127
4.02K
1% 1/16W MF-LF
C7105
0.015UF
10% 16V X7R 402
1
2
1
2
1
C7106
0.001UF
10% 50V
2
CERM 402
R7108
147K
1% 1/16W MF-LF 402
402
2
R7113
IMVP6_VDIFF_RC
1
1
1%
402
1
2
2
C7114
470PF
10% 50V CERM 402
R7109
1K
1% 1/16W MF-LF 402
2
(IMVP6_FB)
R7111
255
1/16W MF-LF
B
IMVP6_COMP_RC
R7160
0
IMVP_VR_ON
40
IMVP6_OCSET
A
61
IMVP6_VO
61
IMVP6_DROOP
61
IMVP6_DFB
61
IMVP6_SOFT
61
IMVP6_RBIAS
61
IMVP6_VDIFF
61
IMVP6_FB2
61
IMVP6_FB
61
IMVP6_COMP
61
IMVP6_VW
61
1 2
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM
5% 1/16W MF-LF
402
IMVP_VR_ON_R
PPVIN_S5_IMVP6_VIN
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=12.6V
PP5V_S0_IMVP6_VDD
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V
PP3V3_S0_IMVP6_3V3
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V
1
R7199
68
5% 1/16W MF-LF 402
2
1
1K
1% 1/16W MF-LF
402
2
C7113
220PF
10% 50V
X7R-CERM
402
1
R7114
97.6K
1% 1/16W MF-LF
402
2
1
2
61
8
75
IN
8
75
IN
8
75
IN
8
75
IN
8
75
IN
8
75
IN
8
75
IN
9
13 75
IN
9
IN
45
OUT
8
OUT
61
IN
24
OUT
(IMVP6_VW)
(IMVP6_COMP)
75
61
61
61
61
61
61
61
C7196
0.1UF
C7126
1UF
402-1
C7130
0.1uF
10% 16V X5R 402
IMVP6_VID<6> IMVP6_VID<5> IMVP6_VID<4> IMVP6_VID<3> IMVP6_VID<2> IMVP6_VID<1> IMVP6_VID<0>
CPU_DPRSTP_L IMVP_DPRSLPVR CPU_PSI_L IMVP6_IMON
TP_IMVP6_CLKEN_L IMVP_VR_ON_R VR_PWRGOOD_DELAY IMVP6_VR_TT_L IMVP6_NTC
(GND_IMVP6_SGND)
IMVP6_SOFT IMVP6_RBIAS
(GND_IMVP6_SGND)
IMVP6_VDIFF
IMVP6_FB2 IMVP6_FB IMVP6_COMP IMVP6_VW
1
CERM
10% 50V
402
1
2
2
C7107
0.001UF
10% 16V X5R 402
1
10% 10V
2
X5R
1
2
R7110
6.81K
1% 1/16W MF-LF 402
1
2
61
61
61
61
61
61
61
61 75
6
1
R7197
10K
5% 1/16W MF-LF 402
2
43 42 41 40 39 38 37
46 45
2 3
48 47 44
1 5 6
7
4
13
12 11 10
9
25
GND_IMVP6_SGND
MIN_LINE_WIDTH=0.50 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=0V
IMVP6_PHASE1 IMVP6_BOOT1 IMVP6_UGATE1 IMVP6_LGATE1 IMVP6_ISEN1 IMVP6_VSUM1 IMVP6_VO1 IMVP6_VSEN_P
5
DPRSLPVR
0 1 0 1-Phase 1
1
C7135
4.7UF
20%
6.3V
2
X5R-CERM 402
20
VIN VDD
VID6 VID5 VID4 VID3 VID2 VID1 VID0
DPRSTP* DPRSLPVR PSI* IMON
(PGD_IN) (ISL9504A)
3V3 CLK_EN* VR_ON PGOOD VR_TT* NTC
SOFT
RBIAS
VDIFF
FB2 FB COMP VW
NC
XW7100
MIN_LINE_WIDTH=1.5 MM MIN_NECK_WIDTH=0.2 MM MIN_LINE_WIDTH=0.25 MM MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM MIN_LINE_WIDTH=0.25 MM MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM
MIN_LINE_WIDTH=0.25 MM
22
U7100
QFN
GND
SM
1 2
21
31
PVCC
36
BOOT1
26
BOOT2
35
UGATE1
34
PHASE1
32
LGATE1
33
PGND1
24
ISEN1
ISL9504BCRZ
27
UGATE2
28
PHASE2
30
LGATE2
29
PGND2
23
ISEN2
19
VSUM
8
OCSET
18
VO
16
DROOP
17
DFB
14
VSEN
15
RTN
TPAD
49
C7121
0.22UF
IMVP6_BOOT1
61
IMVP6_BOOT2
61
IMVP6_UGATE1
61
IMVP6_PHASE1
61
IMVP6_LGATE1
61
(GND)
61
IMVP6_ISEN1
IMVP6_UGATE2
61
IMVP6_PHASE2
61
IMVP6_LGATE2
61
(GND)
IMVP6_ISEN2
61
IMVP6_VSUM IMVP6_OCSET
61
IMVP6_VO IMVP6_DROOP
IMVP6_DFB
61
C7131
0.01UF
1
C7133
0.01uF
20%
6.3V
2
X5R 402
MIN_NECK_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.25 MMMIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM
10% 16V
CERM
402
10% 16V
CERM
402
DPRSTP*
1
2
1
2
1 0 0
C7127
0.22UF
R7117
4.12K
1 2
1/16W MF-LF
1
R7118
1K
1% 1/16W MF-LF 402
2
1
2
IMVP6_VSEN_P
61 75
IMVP6_VSEN_N
61 75
NO STUFF
1
C7132
0.01uF
10% 16V
2
CERM 402
PSI*
Operation
1
2-Phase 0 1 0
20% 25V X5R 603
1%
402
C7134
0.068UF
10% 10V CERM 402
C7128
0.22UF
CERM-X5R
Place R7131 Between L7100,L7101 and CPU
1
2
6.3V
10%
402
1
2
61
61
61
61
61
61
61
61 75
1-Phase1
1
C7115
0.22UF
20% 25V
2
X5R 603
OUT OUT
C7129
180pF
5% 50V CERM 402
1
R7115
11K
1% 1/16W MF-LF 402
2
1
2
R7122
0
1 2
5% 1/16W MF-LF
402
IMVP6_PHASE2 IMVP6_BOOT2 IMVP6_UGATE2 IMVP6_LGATE2 IMVP6_ISEN2 IMVP6_VSUM2 IMVP6_VO2 IMVP6_VSEN_N
61
61
IMVP6_VO_R
1
2
4
These caps are for Q7100 These caps are for Q7102
1
C7108
0.001UF
10% 50V
2
X7R 402
Mode
CCM CCM DCM1-Phase DCM
NO STUFF
0.001uF
1
R7116
13.3K
1% 1/16W MF-LF 402
2
(IMVP6_VO)
C7116
CERM
R7130
2.61K
1/16W MF-LF
10% 50V
402
402
1
2
1
1%
2
CRITICAL
R7131
10KOHM-5%
0603-LF
CPU_VCCSENSE_P
R7123
0
1 2
1/16W MF-LF
CPU_VCCSENSE_N
5%
402
MIN_LINE_WIDTH=1.5 MM MIN_NECK_WIDTH=0.2 MM MIN_LINE_WIDTH=0.25 MM MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM MIN_LINE_WIDTH=0.25 MM MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM MIN_LINE_WIDTH=0.25 MM
CRITICAL
1
C7117
68UF
20% 16V
2
POLY-TANT CASE-D2E-SM
DIDT=TRUE
DIDT=TRUE
DIDT=TRUE
DIDT=TRUE
DIDT=TRUE
IN
IN
MIN_NECK_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM
G
5
DIDT=TRUE
G
5
10 75
10 75
8
7 6
5
4
3
2
1
8 7
6
5
4
3
D
PPBUS_G3H
6 7
35 44 45 59 60 63 64 73
29 37 38 39 41 49 51 53
C
Vout = 5.0V 13A max output
(Q7220 limit) f=365KHz
CRITICAL NO STUFF
C7252
150UF
POLY-TANT
CASE-B2-SM
CRITICAL
1
C7253
150UF
20%
6.3V
2
POLY-TANT CASE-B2-SM
PLACEMENT_NOTE=Place XW7220 next to L7220.
B
PP5V_S3
6 7 8 63 68
20%
6.3V
D
CRITICAL
1
C7240
68UF
20% 16V
2
POLY-TANT CASE-D2E-SM
4.7UH-13A-15MOHM
1
2
10UF
1
C7251
0.001UF
10% 50V
2
CERM 402
XW7220
20% 10V X5R 805
2
2
SM
1
1
C7250
P5VS5_REG_XW
1
C7241
2
CRITICAL
L7220
1 2
PCMB104E4R7-SM
NO STUFF
R7222
1/16W MF-LF
1UF
10% 25V X5R 603-1
STL11NH3LL
1
10
5%
402
2
1
C7243
0.001UF
10% 50V
2
CERM 402
CRITICAL
Q7220
PWRFLAT-SM
CRITICAL
Q7225
STL15N3LLH5
P5VS5_RC
NO STUFF
C7222
100PF
CERM
1
R7220
15K
5% 1/16W MF-LF 402
2
1
R7221
10K
1% 1/16W MF-LF 402
2
50V 402
P5VP3V3_VREG5
P5VP3V3_VREG3
1
2
DIDT=TRUE
DIDT=TRUE
DIDT=TRUE
NO STUFF
C7208
220PF
25V
CERM
402
1
C7205
10UF
20%
6.3V
2
X5R 603
P3V3S5_VBST_R
2
R7264
0
5% 1/16W MF-LF 402
1
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm
1
R7206
1
75K
1%
5%
1/16W MF-LF
2
402
2
1
C7264
0.1UF
10% 50V
2
X7R 603-1
1
8
C7203
10UF
R7273
100K
1/16W MF-LF
20%
6.3V X5R 603
2
5%
402
1
P5VP3V3_VREF
0.22UF
VREG3
VREG5
VBST2
DRVH2
LL2
DRVL2
VO2
VFB2
VCLK
PGOOD
EN0
Q7210
10% 10V
CERM
402
8
17
18
23
13
SOT563
1
2
P3V3S5_VBST P3V3S5_DRVH
GATE_NODE=TRUE
P3V3S5_LL
SWITCH_NODE=TRUE
P3V3S5_DRVL
GATE_NODE=TRUE
(P3V3S5_V02) P3V3S5_VFB P3V3S5_ENTRIP
P5V3V3_EN0
3
D
16
3
VREF
QFN
ENTRIP2
THRM_PAD
15
25
XW7200
1 2
SSM6N15FEAPE
C7201
SM
5
D
S
1
5%
2
C7224
0.1UF
G
4
123
5
D
G
S
PWRFLAT-SM
123
P5VS5_VBST_R
1
10% 50V
2
X7R
603-1
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm GATE_NODE=TRUE MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm GATE_NODE=TRUE MIN_NECK_WIDTH=0.2 mm
4
24 40 64 65 66 67
2
R7224
0
5% 1/16W MF-LF
402
1
1
R7200
86.6K
1% 1/16W MF-LF
402
2
One master PGOOD for both 5V and 3V3
ALL_SYS_PWRGD
OUT
C7200
1UF
10% 25V X5R
603-1
P5VS5_VBST P5VS5_DRVH P5VS5_LL
SWITCH_NODE=TRUE
P5VS5_DRVL
(P5VS5_VO1) P5VS5_VFB P5VS5_ENTRIP
GND_P5VP3V3_SGND
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V
Q7210
SSM6N15FEAPE
SOT563
1
2
DIDT=TRUE
DIDT=TRUE
DIDT=TRUE
VIN
14
SKIPSEL
4
TONSEL
U7201
22 9
VBST1
TPS51125
21 10
DRVH1
20 11
LL1
19 12
DRVL1
24 7
VO1
2 5
VFB1
1 6
ENTRIP1
GND
PLACEMENT_NOTE=Place XW7200 next to U7200 pin 15.
6
D
CRITICAL
1
C7280
68UF
20% 16V
2
POLY-TANT CASE-D2E-SM
2349
CRITICAL
Q7260
FDMS9600S
Q1
Q2
MLP
10
SW
7
56
1
2
NO STUFF
R7262
P3V3S5_RC NO STUFF
C7262
100PF
5% 50V CERM 402
R7260
R7261
1
C7281
1UF
10% 25V
2
X5R 603-1
10
5% 1/16W MF-LF
402
6.49K
1/16W MF-LF
402
10K
1/16W MF-LF
402
1
2
P3V3S5_REG_XW
1
1%
2
1
1%
2
1
C7282
0.001UF
10% 50V
2
CERM 402
CRITICAL
L7260
4.7UH-5.5A
1 2
IHLP2525CZ
PP3V3_S5
Vout = 3.3V
6 7
17 19 21 22 24 28 32 35 36
42 52 66 67 68 69 71 82
5.5A max output (L7260 limit) f=460KHz
1
C7290
10UF
20%
6.3V
2
X5R 603
C7291
0.001UF
10% 50V
CERM
402
2
XW7260
SM
1
PLACEMENT_NOTE=Place XW7260 next to L7260.
CRITICAL
1
C7292
150UF-.025-OHM
20%
6.3V
2
TANT CASE-B2-SM
1
2
C
B
6 8
IN
5
SG
4
SMC_PM_G2_EN
5V / 3.3V Power Supply
1
SYNC_DATE=01/13/2009
REV.
OF
8362
A
A
SYNC_MASTER=WFERRY_K19I
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
APPLE INC.
4
3
2
SCALE
D
NONE
051-7903
SHT
2
SG
1
PM_G2_P3V3S5_EN_L
40 67
PART NUMBER
ALTERNATE FOR PART NUMBER
152S0778 152S0693
BOM OPTION
REF DES
ALL
COMMENTS:
Cyntec alternate to MagLayers
PM_SLP_S3_L_INVERT
67 67
IN IN
TABLE_ALT_HEAD
TABLE_ALT_ITEM
A
8
7 6
5
8 7
6
5
4
3
D
PP1V5_S3
6 7
26 27 28 63 68
64 73
PPBUS_G3H
6 7
1
C7355
10UF
20%
6.3V
2
X5R 603
6.3V CERM
20%
603
R7305
1 2
1
C7305
2
C7350
0.033UF
4.7
5% 1/16W MF-LF
402
10% 16V X5R 402
1UF
402-1
10% 10V X5R
1
2
NC NC
1
2
PP5V_S3_DDRREG_V5FILT
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=5V
15
V5IN
6
COMP
10
S3
VTT Enable
11
S5
VDDQ/VTTREF Enable
13
PGOOD
VDDQ PGOOD
5
VTTREF
24
VTT
2
VTTSNS
7
NC0
12
NC1
VTTGND
THRM_PAD
1
25
14
CRITICAL
U7300
TPS51116
QFN
SYM (2 OF 2)
GND
3
XW7300
23
VLDOINV5FILT
8
VDDQSNS
4
MODE
22
VBST
21
DRVH
20
LL
19
DRVL
16
CS
9
VDDQSET CS_GND
PGND
17
18
2
SM
1
PP5V_S3
6 7 8
29 37 38 39 41 49 51 53
62 68
C7300
4.7UF
C
MEM_VTT_EN
8
24 68
IN
DDRREG_EN
67
IN
TP_DDRREG_PGOOD
67
OUT
PPVTTDDR_S3
7
25
PP0V75_S0_DDRVTT
6 7
26 27 68
MIN_LINE_WIDTH=2 mm
MIN_NECK_WIDTH=0.17 mm
PLACEMENT_NOTE=Place next to C7360
CRITICAL
C7360
X5R-CERM
22UF
20%
6.3V 603
1
2
XW7360
SM
1 2
CRITICAL
1
C7361
22UF
20%
6.3V
2
X5R-CERM 603
10mA max load Vout = VDDQSNS/2
Vout = VTTREF
DDRREG_VTTSNS
B
GND_DDRREG_SGND
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=0V
35 44
45 59 60 62
DDRREG_VDDQSNS
R7310
DDRREG_VBST
DDRREG_DRVH
GATE_NODE=TRUE
DDRREG_LL
SWITCH_NODE=TRUE
DDRREG_DRVL
GATE_NODE=TRUE
DDRREG_CS
DDRREG_FB
DDRREG_CSGND
10K
1/16W MF-LF
CRITICAL
1
1%
402
2
C7330
POLY-TANT
CASE-D2-SM
CRITICAL
1
22UF
20% 25V
2
POLY-TANT
CASE-D2-SM
(DDRREG_DRVH)
DIDT=TRUE
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm
(DDRREG_VBST)
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm
(DDRREG_LL)
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm
(DDRREG_DRVL)
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm
DIDT=TRUE
PLACEMENT_NOTE=Place next to Q7335
(DDRREG_CSGND)
MIN_LINE_WIDTH=0.1 mm MIN_NECK_WIDTH=0.1 mm
(DDRREG_VDDQSNS)
MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.17 mm
(DDRREG_FB)
C7331
22UF
20% 25V
1
1
C7332
1UF
10% 25V
2
2
X5R 603-1
C7325
0.1UF
1 2
10% 50V X7R
603-1
DIDT=TRUE
1
C7333
0.001UF
10% 50V
2
X7R 402
XW7335
SM
1 2
CRITICAL
D
Q7330
G
G
SI7110DN
PWRPK-1212-8-HF
S
CRITICAL
L7330
1.0UH-13A-5.6MOHM
1 2
PCMB065T-SM
CRITICAL
D
Q7335
SI7108DN
PWRPK-1212-8-HF
S
CRITICAL
1
C7340
270UF
20% 2V
2
TANT CASE-B4-SM
CRITICAL
C7341
CASE-B4-SM
Vout = 0.75V * (1 + Ra / Rb)
VOLTAGE=1.5V MIN_NECK_WIDTH=0.1 MM MIN_LINE_WIDTH=0.8 MM
PPDDR_S3_REG_R
1
270UF
20%
2V
2
TANT
NO STUFF
C7320
1
C7345
10UF
20%
6.3V
2
X5R 603
100PF
CERM
50V 402
ISNS_1V5_S3_P
ISNS_1V5_S3_N
XW7331
SM
1 2
XW7330
1 2
1
C7346
0.001UF
10% 50V
2
X7R 402
1
R7320
1
15.0K
5%
1% 1/16W MF-LF
2
402
2
<Ra>
1
R7321
15.0K
1% 1/16W MF-LF 402
2
<Rb>
2
XW7345
SM
PLACEMENT_NOTE=Place next to C7345
1
XW7332
SM
1 2
SM
PP1V5_S3
Vout = 1.5V 15A max output (Q7335 limit) f = 400 kHz
OUT
OUT
51 82
51 82
6 7
26 27 28 63 68
D
C
B
1.5V DDR3 Supply
A
SYNC_MASTER=K19_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
D
APPLE INC.
8
7 6
5
4
3
2
SCALE
NONE
SYNC_DATE=02/04/2009
051-7903
SHT
OF
1
A
REV.
A
8363
8 7
D
R7593
0
MCPCORES0_IMON
45
MCP_VID<0>
20
IN
MCP_VID<1>
20
IN
MCP_VID<2>
20
IN
C
21 22 44 64
XW7562
SM
PPVCORE_S0_MCP
6 7
21 22 44 64
PLACE XW NEAR THE MCP, CONNECT SENSE LINES TO CLOSEST MCPCORE AND GND BALL OF MCP
1 2
OMIT
XW7563
SM
1 2
OMIT
1 2
5% 1/16W MF-LF
402
R7590
0
1 2
5% 1/16W MF-LF
402
R7592
0
1 2
5% 1/16W MF-LF
402
PPVCORE_S0_MCP
6 7
MCPCORES0_RSEN_P
82
MCPCORES0_RSEN_N
82
R7591
0
1 2
5% 1/16W MF-LF
402
R7566
1 2
1/16W MF-LF
R7568
1 2
1/16W MF-LF
20
1%
402
20
1%
402
NOSTUFF
1
R7580
20.0K
1% 1/16W MF-LF 402
2
1
R7582
20.0K
1% 1/16W MF-LF 402
2
B
VOLTAGE=5V MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 MM
NOSTUFF
1
R7581
20.0K
1% 1/16W MF-LF 402
2
1
R7583
20.0K
1% 1/16W MF-LF 402
2
1
R7563
100
1% 1/16W MF-LF 402
2
(MCPCORES0_VSEN)
1
C7570
0.001UF
10% 50V
2
X7R 402
(MCPCORES0_RTN)
1
R7571
100
1% 1/16W MF-LF 402
2
6
5V_S0_MCPREG_VIN
1
R7561
1K
5% 1/16W MF-LF 402
2
67 66 62 24 40 65
67
MCPCORES0_RBIAS MCPCORES0_SOFT
MCPCORES0_IMON_R
ALL_SYS_PWRGD
OUT
MCP_VID0_R MCP_VID1_R
MCP_VID2_R MCPCORES0_OS0 MCPCORES0_OS1
MCPCORES0_EN
IN
MCPCORES0_FDE
MCPCORES0_VSEN MCPCORES0_RTN
MCPCORES0_VW
MCPCORES0_COMP
MCPCORES0_FB
MCPCORES0_VDIFF
C7576
0.1UF
10% 16V
X7R-CERM
402
C7550
1
2
1
1UF
10% 16V
2
X5R 402
1
R7572
150K
1% 1/16W MF-LF 402
2
GND_MCPCORES0_AGND
VOLTAGE=0V MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 MM
5
R7560
2.2
1 2
5% 1/10W MF-LF
603
16
VDD
U7500
1
RBIAS
2
SOFT
28
IMON
31 19
PGOOD
25
VID0
26
VID1
27
VID2
23
OFFSET0
24
OFFSET1
29
VR_ON
30
AF_EN
32
FDE
8
VSEN
9
RTN
4
VW
5
COMP
6
FB
7
VDIFF
VSS
PGND
20
PVCC
QFN
ISL6263D
THRM_PAD
15
PP5V_S0
22
VIN
UGATE
BOOT
PHASE
LGATE
VO
OCSET
ISP ISN
ICOMP
33
XW7561
1 2
SM
PPBUS_G3H
6 7
35 44 45 59 60 62 63 73
1
C7562
1UF
10% 16V
2
X5R 402
14
18
MCPCORES0_UGATE
17
MCPCORES0_BOOT
MCPCORES0_PHASE
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM
SWITCH_NODE=TRUE
DIDT=TRUE
21
MCPCORES0_LGATE
12
MCPCORES0_VO
3
MCPCORES0_OCSET
6
13
MCPCORES0_ISP
11
MCPCORES0_ISN
10
MCPCORES0_ICOMP
6 7 70 72
(MCPCORES0_UGATE) MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM
GATE_NODE=TRUE
DIDT=TRUE
R7565
0
1 2
5% 1/10W MF-LF
0.2 MM 603
0.25 MM
(MCPCORES0_LGATE)
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM
GATE_NODE=TRUE
(MCPCORES0_ISN)
(MCPCORES0_ICOMP)
4
37 42 47 49 61 65 67 68
MCPCORES0_BOOT_R
0.25 MM
0.2 MM
(MCPCORES0_PHASE)
R7569
11.3K
1 2
1% 1/16W MF-LF
402
4
DIDT=TRUE
1
2
C7564
0.22UF
CERM-X7R
G
CRITICAL
C7540
68UF
20% 16V POLY-TANT CASE-D2E-SM
4
1 2
10V 603
5%
SWITCHNODE
5
D
Q7565
FDMC8678S
MICROFET3X3
S
1 2 3
1
2
1
2
5
D
G
S
1 2 3
CRITICAL
0.001UF
R7573
10K
C7573
1% 1/16W MF-LF 402
R7575
47.0K
1% 1/16W MF-LF 402
C7563
0.001UF
CRITICAL
Q7560
FDMC8676
POWER33-SM
NO STUFF
C7589
10% 50V X7R 402
47PF
5%
50V
CERM
402
1
10% 50V
2
X7R 402
NO STUFF
1
R7589
1
5% 1/10W MF-LF 603
2
MCPCORE_SNUBBER
1
2
1
2
3
CRITICAL
1
C7560
68UF
20% 16V
2
POLY-TANT CASE-D2E-SM
1.0UH-17A-5M-OHM
1
C7575
47PF
5% 50V
2
CERM 402
1
2
CRITICAL
L7560
1 2
HAHF651R0AP-SM
(MCPCORES0_VO)
R7500
100
1 2
1% 1/16W MF-LF
402
C7561
1UF
10% 25V X5R 603-1
PPMCPCORE_S0_R
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1V
MCPCORES0_ISP_R
CRITICAL
R7525
0.001
1% 1W MF
0612
1 2 3 4
C7566
10UF
1
C7567
10UF
20% 4V
2
X5R 603
20% X5R
603
MAX CURRENT: 15.5A (Q7560 Limit)
PPVCORE_S0_MCP
1
4V
2
f = 300 kHz
CRITICAL
1
C7565
270UF
20% 2V
2
TANT CASE-B4-SM
1
C7569
0.001UF
10% 50V
2
X7R 402
6 7
CRITICAL
1
C7568
270UF
20% 2V
2
TANT CASE-B4-SM
D
21 22 44 64
C
B
(MCPCORES0_VW)
1
C7579
C7580
68PF
1 2
5%
50V
CERM
R7577
402-1
133K
1 2
1% 1/16W MF-LF
402
R7578
100
1 2
1/16W MF-LF
MCPCORES0_COMP_C
1%
402
A
8
7 6
0.001UF
10% 50V X7R 402
C7581
560PF
1 2
10% 50V
CERM
402
MCPCORES0_VDIF_C
R7579
2.21K
1 2
(MCPCORES0_VDIFF)
1% 1/16W MF-LF
402
2
1
R7576
6.98K
1% 1/16W MF-LF 402
2
(MCPCORES0_COMP)
(MCPCORES0_FB)
C7582
560PF
1 2
10% 50V
CERM
402
VID<2:0> VOLTAGE
000 1.05V 001 1.00V 010 0.95V 011 0.90V 100 0.85V
SYNC_MASTER=K19_MLB
101 0.80V 110 0.75V 111 0.70V
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
APPLE INC.
5
4
3
2
MCP CORE REGULATOR
SYNC_DATE=02/03/2009
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
DRAWING NUMBER
SIZE
D
SCALE
NONE
051-7903
SHT
64 83
1
A
REV.
A
OF
8 7
6
5
4
3
D
PPBUS_CPU_IMVP_ISNS
7
45 61
CRITICAL
C7690
22UF
20% 25V
POLY-TANT
CASE-D2-SM
PP5V_S0
6 7
37 42 47 49 61 64 67 68
70 72
R7601
200
1 2
C
B
PP5V_S0_CPUVTTS0_V5FILT
MIN_LINE_WIDTH=0.6 mm
1%
MIN_NECK_WIDTH=0.2 mm
1/16W
VOLTAGE=5V
MF-LF
402
67
IN
24 40 62 64 66 67
OUT
CPUVTTS0_EN ALL_SYS_PWRGD
(=PPCPUVTT_S0_REG)
CPUVTTS0_VFB CPUVTTS0_TRIP
1
R7685
8.87K
1% 1/16W MF-LF 402
2
C7601
2.2UF
10% 16V X5R 603
1
2
TPS51117RGY_QFN14
1
EN_PSV
6
PGOOD
3
VOUT
5
VFB
11
TRIP
GND
4
V5FILT
CRITICAL
U7600
SYM (2 OF 2)
THRM_PAD
7
XW7600
QFN
15
SM
1 2
V5DRV
10
PGND
8
TON
VBST
DRVH
DRVL
1
2
2
14
13
12
LL
9
C7600
1UF
10% 10V X5R 402-1
CPUVTTS0_TON CPUVTTS0_VBST CPUVTTS0_DRVH
GATE_NODE=TRUE
CPUVTTS0_LL
SWITCH_NODE=TRUE
CPUVTTS0_DRVL
GATE_NODE=TRUE
(GND)
GND_CPUVTTS0_SGND
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V
(CPUVTTS0_VFB)
(=PPCPUVTT_S0_REG)
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM
1
2
C7680
1
2
R7679
0.1UF
603-1
DIDT=TRUE
DIDT=TRUE
DIDT=TRUE
C7695
1UF
10% 25V X5R 603-1
226K
1% 1/16W MF-LF
402
1
10% 50V
2
X7R
FDMS9600S
1
2
CRITICAL
Q7660
MLP
1
8
2349
Q1
10
SW
Q2
7
56
CPUVTTS0_VSNS
1
R7670
8.06K
1% 1/16W MF-LF 402
2
<Ra>
1
R7671
20.0K
1% 1/16W MF-LF 402
2
<Rb>
Vout = 0.75V * (1 + Ra / Rb)
CRITICAL
L7660
2.2UH-8.0A
1 2
PCMB065T-SM
XW7665
PLACEMENT_NOTE=Place XW7665 next to L7660
PP1V05_S0
20%
1
2
Vout = 1.052V 8A max output (Q7660 limit?) f = 360 kHz
1
C7665
10UF
20%
6.3V
2
X5R 603
CRITICAL
C7660
2
SM
1
330UF
2.0V
POLY-TANT
B2-SM
6 7 9
10 11 12 13 16 17 19 21
22 23 35 61 66 67
D
C
B
CPU VTT Power Supply
051-7903
SHT
SYNC_DATE=(12/05/2008)
REV.
OF
8365
1
A
A
A
M99 differences from last sync on 12/03/07 to T18 MLB:
1. Tied THERMAL_PAD to PGND. GND and THERMAL_PAD disconnected.
SYNC_MASTER=(K19_MLB)
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
D
APPLE INC.
8
7 6
5
4
3
2
SCALE
NONE
8 7
6
5
4
3
1.8V S0 SWITCHER
D
57 58 61 66 67 68 69 71 72 82
PP3V3_S0
6 7
12 17 18 20 21 22 23 26
27 35 37 41 43 45 46 47 49 53
CRITICAL
C7760
10uF
6.3V
1
1
20%
2
X5R 603
P1V8S0_EN
TPS62202
4
FB
3
EN
VI
U7760
SOT23-5
GND
2
SW
5
P1V8S0_SW
DIDT=TRUE
CRITICAL
L7760
10UH-0.55A-330MOHM
PCAA031B-SM
1 2
MAX CURRENT = 200MA
1
C7762
10uF
20%
6.3V
2
X5R 603
PP1V8_S0
6 7
17 23 53 67
1.05V S0 PLL LDO
D
C
MCP 1.05V S5 (AUXC) SUPPLY
CRITICAL
1
C7750
LX
VFB
RSI
22UF
20%
6.3V
2
CERM 805
8
1V05S5_SW
DIDT=TRUE
6
1V05S5_FB
54
CRITICAL
L7770
2.2UH-3.25A
IHLP1616BZ-SM
1 2
C7776
47PF
5%
50V
CERM
402
1
2
PP3V3_S5
6 7
17 19 21 22 24 28 32 35
36 42 52 62 67 68 69 71 82
B
1
VIN
U7750
ISL8009B
DFN
2
67
P1V05_S5_PGOOD
67
PM_G2_P1V05S5_EN
IN
EN
3
POR
SKIP
CRITICAL
GND
THRM_PAD
7
9
12 17 18 20 21 22 23 26
1
2
1
2
PP3V3_S0
57 58 61 66 67 68 69 71 72 82 6 7 27 35 37 41 43 45 46 47 49 53
<Ra>
R7780
255K
1% 1/16W MF-LF 402
<Rb>
R7781
806K
1% 1/16W MF-LF 402
10 11 15 22 37 67 68 82
PP1V5_S0
6 7
LDO_YES
CRITICAL
1
C7771
22UF
20%
6.3V
2
CERM 805
C7741
1UF
6.3V CERM
PP1V05_S5
10% 402
1
2
LDO_YES
R7743
100
1 2
PP3V3_S0_MCP_PLL_VLDO_BIAS
5% 1/16W MF-LF
402
1
1UF
6.3V CERM
10% 402
LDO_YES
2
C7740
P1V05S0_LDO_SS
1
C7743
0.0022UF
10% 50V
2
CERM
402
LDO_YES
6 7
21 22 32
Vout = 1.05V MAX CURRENT = 0.8A FREQ = 1.6MHZ
LDO_YES
4
CRITICAL
BIAS
1
IN0
2
IN1
TPS74701
5 8
EN FB
SS
SON
U7740
THRML_PAD
GND
6
11
OUT0 OUT1
PG
PP1V05_S0
6 7 9
10 11 12 13 16 17 19
21 22 23 35 61 65 67
VOUT = 0.8V * (1 + RA / RB)
9 10
MIN_NECK_WIDTH=0.2 mm
37
PP1V05S0_PGOOD
MIN_LINE_WIDTH=0.6 mm VOLTAGE=1.05V
DIDT=TRUE
P1V05S0_LDO_FB
PP1V05_S0_MCP_PLL_UF_LDO
<Ra>
1
R7746
1.37K
1% 1/16W MF-LF 402
2
LDO_YES
<Rb>
1
R7747
4.42K
1% 1/16W MF-LF 402
2
LDO_YES
R7748
0
1 2
5% 1/16W MF-LF
402
LDO_YES
1
C7742
4.7UF
20% 4V
2
X5R 402
LDO_YES
ALL_SYS_PWRGD
LDO_NO
R7745
0
1 2
5% 1/16W MF-LF
402
R7744
0
1 2
5% 1/16W MF-LF
402
LDO_YES
24 40 62 64 65 67
PP1V05_S0_MCP_PLL_UF
Vout = 1.05V MAX CURRENT = 0.5A
7
22
C
B
VOUT = 0.8V * (1 + RA / RB)
MISC POWER SUPPLIES
A
SYNC_MASTER=K24_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
APPLE INC.
8
7 6
5
4
3
2
SCALE
NONE
SYNC_DATE=02/25/2009
DRAWING NUMBER
051-7903
SHT
OF
66 83
1
A
REV.
A
8 7
6
5
4
3
3.3V 1.05V S5 ENABLE
R7802
100K
PP3V42_G3H
6 7
20 21 24 38 40 41 42 43
45 48 59 60 67
D
40 62
SMC_PM_G2_EN
6 8
IN
R7800
100K
5% 1/16W MF-LF
402
12
5% 1/16W MF-LF
402
Q7800
SSM3K15FV
SOD-VESM-HF
1
1
G S
3
D
2
2
1
2
NO STUFF
C7802
0.068UF
10% 10V CERM 402
62 67
PM_G2_P3V3S5_EN_L
MAKE_BASE=TRUE
R7801
5.1K
5% 1/16W MF-LF
402
12
PM_G2_P1V05S5_EN
MAKE_BASE=TRUE
1
2
C7801
0.47UF
10%
6.3V CERM-X5R 402
PM_G2_P3V3S5_EN_L
PM_G2_P1V05S5_EN
62 67
OUT
State
Run (S0)
Sleep (S3)
Soft-Off (S5)
Battery Off (G3Hot)
66 67
OUT
S3 ENABLE
R7813
PP3V42_G3H
6 7
20 21 24 38 40 41 42 43
45 48 59 60 67
PM_SLP_S4_L
6
20 38 40 41
IN
C
MAKE_BASE=TRUE
R7810
100K
1/16W MF-LF
1
5%
402
2
68K
1/16W MF-LF
402
(PM_S4_STATE_L)
R7811
5.1K
1 2
5% 1/16W MF-LF 402
R7812
1 2
5% 1/16W MF-LF 402
12
5%
1
0
G S
3
D
2
67 63
DDRREG_EN
MAKE_BASE=TRUE
Q7813
SSM3K15FV
SOD-VESM-HF
C7810
0.47UF
1 2
10%
6.3V
CERM-X5R
402
NO STUFF
C7812
0.47UF
1 2
10%
6.3V
CERM-X5R
402
P3V3S3_EN
67 68
MAKE_BASE=TRUE
62 67
PM_SLP_S3_L_INVERT
MAKE_BASE=TRUE
NO STUFF
1
C7813
0.068UF
10% 10V
2
CERM 402
P3V3S3_EN
DDRREG_EN DDRREG_EN
OUT
PM_SLP_S3_L_INVERT
OUT OUT
67 68
63 67
63 67
62 67
OUT
B
R7870
R7871
20.0K
PP5V_S0
1
10K
1% 1/16W MF-LF
402
2
1
1% 1/16W MF-LF
402
2
3.3V 1.05V AND 1.5V S0 RAILS MONITOR CIRCUIT
PP3V3_VMON_VDD
353S2310
2
7
VDD
U7870
ISL88042IRTEZ
58 61 66 67 68 69 71 72 82
PP3V3_S0
6 7
12 17 18 20 21 22 23 26 27
35 37 41 43 45 46 47 49 53 57
PP1V5_S0
6 7
10 11 15 22 37 66 68 82
PP1V05_S0
6 7 9
10 11 12 13 16 17 19 21
22 23 35 61 65 66
TDFN
3
V2MON
5
V3MON
6
GND
THRM_PAD
4
1
MR*
NC
8
RST*V4MON
9
C7870
0.1uF
1
20% 10V
2
CERM
402
ALL_SYS_PWRGD
24 40 62 64 65 66 67
A
V2MON THRESHOLD IS 2.866V
V3MON THRESHOLD IS 0.6V V4MON THRESHOLD IS 0.6V
Power Control Signals
SMC_PM_G2_ENABLE
1
1
1 0
0 0
PM_SLP_S3_L
6
20 32 35 40 71
IN
6 7
37 42 47 49 61 64 65 68 70
72
OTHER S0 RAILS PGOOD
49 53 57 58 61 66 67 68
PP3V3_S0
6 7
12 17 18 20 21 22 23
26 27 35 37 41 43 45 46 47 69 71 72 82
24 40 62 64 65 66 67
24 40 62 64 65 66 67
24 40 62 64 65 66 67
24 40 62 64 65 66 67
ALL_SYS_PWRGD
IN
ALL_SYS_PWRGD
IN
ALL_SYS_PWRGD
IN
ALL_SYS_PWRGD
IN
(S0PGOOD_PWROK)
(PM_SLP_S3_L)
R7820
PM_SLP_S4_L
1
1
R7859
1
10K
5% 1/16W MF-LF
402
2
100
5%
1/16W MF-LF
402
ALL_SYS_PWRGD
12
R7879
MAKE_BASE=TRUE
PM_SLP_S3_L
100K
5% 1/16W MF-LF
402
3.3V_S0, 1.8V_S0 ENABLE MCPDDR, CPUVTT,MCPCORES0 ENABLE
1
0
1.5V S0 AND 1.05V S0 ENABLE
D
0
0
44 67 68
PM_SLP_S3_L_BUF
MAKE_BASE=TRUE
PM_SLP_S3_L_BUF
1
2
2
1
MCPCORES0_EN
64 67
MAKE_BASE=TRUE
1
2
R7880
5% 1/16W MF-LF
402
22K
C7880
0.47UF
10%
6.3V CERM-X5R 402
2
1
65 67
CPUVTTS0_EN
MAKE_BASE=TRUE
1
2
R7881
5%
1/16W MF-LF
402
33K
C7881
0.47UF
10%
6.3V CERM-X5R 402
2
1
67 68
MCPDDR_EN
MAKE_BASE=TRUE
1
2
R7882
5%
1/16W MF-LF 402
0
NO STUFF
C7882
0.47UF
10%
6.3V CERM-X5R 402
2
1
66 67
P1V8S0_EN
MAKE_BASE=TRUE
1
2
R7883
5%
1/16W MF-LF
402
10K
C7883
0.47UF
10%
6.3V CERM-X5R 402
R7884
5% 1/16W MF-LF
402
5.1K
1 2
68 67
MAKE_BASE=TRUE
1
C7884
0.47UF
10%
6.3V
2
CERM-X5R 402
PM_SLP_S3_L_BUF
P3V3S0_ENP3V3S0_EN
P1V8S0_EN
MCPDDR_EN
CPUVTTS0_EN
MCPCORES0_EN
44 67 68
OUT
44 67 68
OUT
67 68
OUT
66 67
OUT
67 68
OUT
65 67
OUT
64 67
OUT
C
VOLTAGE MONITOR
PP3V42_G3H
6 7
20 21 24 38 40 41 42 43
45 48 59 60 67
PP3V3_S5
6 7
17 19 21 22 24 28 32 35
24 40 62 64 65 66 67
OUT
TP_DDRREG_PGOOD
63 67
MAKE_BASE=TRUE
36 42 52 62 66 68 69 71 82
CT
1
C7841
0.001UF
20% 50V
2
CERM
402
Unused PGOOD signal
TP_DDRREG_PGOOD
SENSE
TPS3808G33DBVRG4
4
CT
6
VDD
U7840
SOT23-6
GND
2
RESET*
C7840
0.1uF
20% 10V
CERM
402
15
3
MR*
TPS3808 MR* HAS INTERNAL PULLUP
SYNC_MASTER=K24_MLB
63 67
APPLE INC.
1
1
R7840
100K
2
5% 1/16W MF-LF 402
2
RSMRST_PWRGD
P1V05_S5_PGOOD
40
66
POWER SEQUENCING
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
D
SCALE
NONE
051-7903
SHT
SYNC_DATE=02/05/2009
REV.
OF
67
83
B
A
A
8
7 6
5
4
3
2
1
8 7
3.3V S3 FET
6
5
4
3
1.5V S0 FET
(1.5V S0 FET FOR DDR3 MEM, MCP79 AND CPU)
CRITICAL
Q7910
FDC638P_G
36 42 52 62 66
PP3V3_S5
6 7
17 19 21
22 24 28 32 35
D
67 68 69 71 82
1
R7912
10K
5% 1/16W MF-LF
402
2
P3V3S3_EN_L
Q7903
SSM3K15FV
SOD-VESM-HF
P3V3S3_EN
67
IN
1
G S
3
D
2
R7910
47K
1 2
5% 1/16W MF-LF
402
C7911
0.033UF
1
10% 16V
2
X5R 402
P3V3S3_SS
SM
4
3
C7910
0.01UF
1 2
10% 16V
CERM
402
PP3V3_S3
6
5
2
1
6 7
20 25 29 30 43 48 50
3.3V S0 FET
CRITICAL
Q7930
4
FDC606P_G
SOT-6
SGD
3
C7930
0.01UF
1 2
10% 16V
CERM
402
PP3V3_S0
1 2 5 6
58 61 66 67 69 71 72 82 6 7
12 17 18 20 21 22 23 26 27
35 37 41 43 45 46 47 49 53 57
C
36 42 52 62 66
PP3V3_S5
6 7
17 19 21
22 24 28 32 35 67 68 69 71 82
R7932
Q7905
SSM3K15FV
SOD-VESM-HF
100K
1
5% 1/16W MF-LF
402
2
P3V3S0_EN_L
3
D
R7930
47K
1 2
5% 1/16W MF-LF
402
0.033UF
C7931
1
10% 16V
2
X5R 402
P3V3S0_SS
MOSFET
CHANNEL
RDS(ON)
LOADING
MOSFET
CHANNEL
RDS(ON)
LOADING
3.3V S3 FET
FDC638P
P-TYPE
48 mOhm @4.5V
0.182 A (EDP)
3.3V S0 FET
FDC606P
P-TYPE
26 MOHM @4.5V
1.431 A (EDP)
PP5V_S3
6 7 8
29 37 38 39 41 49 51 53
62 63 68
1
R7903
100K
5% 1/16W MF-LF
402
2
3
SOT563
D
5
SG
4
Q7971
SSM6N15FEAPE
MCPDDR_EN
67
IN
6 7
26 27 28 63
R7901
10K
1 2
5% 1/16W MF-LF
402
MCPDDR_EN_L
PP1V5_S3
MCPDDR_SS
R7971
47K
1 2
5% 1/16W MF-LF
402
C7902
0.1UF
Q7971
SSM6N15FEAPE
SOT563
MCPDDR_EN_L_RC
9
CRITICAL
Q7901
D
ROME
1
20% 10V
CERM
402
2
4
2
6
D
SG
1
DFN
8
S
1 2 37
1
C7903
0.068UF
10% 10V
2
CERM 402
KELVIN
NC
6
GND
5
PP1V5_S0
P1V5_S0_KELVIN
P1V5_S0_SENSE
MOSFET
CHANNEL
RDS(ON)
LOADING
OUT
45 45
OUT
6 7
10 11 15 22 37 66 67 82
1.5V S0 FET
Rome SenseFET
N-TYPE
6.3 mOHM @4.5V VGS
5A (EDP)
G
SENSE
D
C
MCP79 DDRVTT FET
1
G S
R7942
47K
1
G S
2
5.0V S0 FET
CRITICAL
Q7940
TPCP8102
23V1K-SM
S
1
5% 1/16W MF-LF
402
2
D
P5V0S0_EN_L
3
2
R7940
47K
1 2
5% 1/16W MF-LF
402
C7941
0.033UF
1
10% 16V
2
X5R 402
1 2 3
P5V0S0_SS
4
G
D
C7940
0.01UF
1 2
10% 16V
CERM
402
376S0778
5 6 7 8
PP5V_S0
49 61 64 65 67 70 72 6 7
37
42 47
5.0V S0 FET
Part TPCP8102 Type Rds(on) Loading
P-Channel 14 mOhm @4.5V
1.7 A (EDP)
6 7
26 27 63
6 7 8
29 37 38 39 41 49 51 53
62 63 68
8
24 63
IN
MCP79 DDR PAD LEAKAGE IS HIGH ENOUGH THAT NVIDIA RECOMMENDS UNPOWERING DURING SLEEP. IN ORDER TO SUPPORT UNPOWERING RAIL, HARDWARE MUST GUARANTEE MEM_CKE SIGNALS ARE LOW BEFORE RAIL IS TURNED OFF, AND REMAINS LOW UNTIL AFTER RAIL TURNS BACK ON OR DIMMS WILL EXIT SELF-REFRESH PREMATURELY. MEM_VTT_EN OUTPUT FROM MCP79 USED TO ENABLE CLAMP ON VTT RAIL, WHICH PULLS ALL CKE SIGNALS LOW THROUGH VTT TERMINATION RESISTORS.
R7975
5%
402
1
2
VTTCLAMP_EN
3
D
SG
4
10
5% 1/10W MF-LF
603
PP0V75_S0_DDRVTT
PP5V_S3
SSM6N15FEAPE
MEM_VTT_EN
R7976
Q7975
SOT563
5
100K
1/16W MF-LF
12
VTTCLAMP_L
Q7975
SSM6N15FEAPE
NO STUFF
C7976
0.001UF
20% 50V
CERM
402
SOT563
B
90mA max load @ 0.9V
81mW max power
CKT FROM T18
6
D
2
SG
1
1
2
SYNC_MASTER=K24_MLB
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
APPLE INC.
POWER FETS
SYNC_DATE=03/12/2009
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SIZE
D
SCALE
NONE
051-7903
SHT
A
REV.
A
OF
8368
P3V3S0_EN
67
IN
B
PP5V_S3
6 7 8
29 37 38
39 41 49 51 53 62 63 68
Q7945
SSM3K15FV
SOD-VESM-HF
PM_SLP_S3_L_BUF
44 67
IN
A
8
7 6
5
4
3
2
.
.
1
8 7
6
5
4
3
D
C
B
17
8
IN
17 19 21 22 24 28 32 35
LCD_PWR_EN
PP3V3_S5
6 7 36 42 52 62 66 67 68 71 82
R9094
10K
1/16W MF-LF
402
1
5%
2
CRITICAL
U9000
FPF1009
MFET-2X2
ON
1
C9009
0.1UF
10% 16V
2
X5R 402
2
3
VIN_1
VIN_2
GND
617
VOUT_1
VOUT_2
THRM
PAD
4
5
LCD (LVDS) INTERFACE
100K pull-ups are for no-panel case (development).
Panel has 2K pull-ups
LVDS_CONN_A_CLK_N
8
17 77
LVDS_CONN_A_CLK_P
8
17 77
LVDS_CONN_B_CLK_N
8
17 77
LVDS_CONN_B_CLK_P
8
17 77
1
C9011
0.1UF
10% 16V
2
X5R 402
Place close to the connector
Place close to the connector
1
C9012
10UF
20%
6.3V
2
X5R 603
57 58 61 66 67 68 71 72 82
PP3V3_S0
12 17 18 20 21 22 23 26
6 7 27 35 37 41 43 45 46 47 49 53
LVDS_DDC_CLK
6 8
17
LVDS_DDC_DATA
6 8
17
CRITICAL
L9010
90-OHM-100MA
DLP11S
SYM_VER-1
1 2
CRITICAL
L9011
90-OHM-100MA
DLP11S
SYM_VER-1
1 2
CRITICAL
L9000
FERR-250-OHM
10% 16V X5R 402
1
2
1
2
1 2
SM
C9002
0.001UF
LED_RETURN_6
6
72 74
LED_RETURN_5
6
72 74
LED_RETURN_4
6
72 74
LED_RETURN_3
6
72 74
LED_RETURN_2
6
72 74
LED_RETURN_1
6
72 74
PPVOUT_S0_LCDBKLT
6
51 72 74
1
10% 50V
2
X7R 402
PP3V3_SW_LCD
6
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V
LVDS_CONN_A_DATA_N<0>
6 8
LVDS_CONN_A_DATA_P<0>
6 8
LVDS_CONN_A_DATA_N<1>
6 8
LVDS_CONN_A_DATA_P<1>
6 8
LVDS_CONN_A_DATA_N<2>
6 8
LVDS_CONN_A_DATA_P<2>
6 8
LVDS_CONN_A_CLK_F_N
6
82
LVDS_CONN_A_CLK_F_P
6
82
LVDS_CONN_B_DATA_N<0>
6 8
LVDS_CONN_B_DATA_P<0>
6 8
LVDS_CONN_B_DATA_N<1>
6 8
LVDS_CONN_B_DATA_P<1>
6 8
LVDS_CONN_B_DATA_N<2>
6 8
LVDS_CONN_B_DATA_P<2>
6 8
LVDS_CONN_B_CLK_F_N
6
82
LVDS_CONN_B_CLK_F_P
6
82
CRITICAL
J9000
20474-040E-11
F-RT-SM
41 42
1 2 3 4 5
NC
6 7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
NC
37 38 39 40
43 44
518S0651
PP3V3_SW_LCD_UF
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V
C9001
0.1UF
1
1
402
R9011
100K
5%
5%
1/16W MF-LF 402
2
2
C9010
0.001UF
10% 50V X7R 402
R9010
100K
1/16W MF-LF
34
34
D
C
B
LVDS Display Connector
A
8
7 6
5
4
3
SYNC_MASTER=K19_MLB
APPLE INC.
2
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
D
SCALE
NONE
051-7903
SHT
SYNC_DATE=02/05/2009
OF
69 83
1
A
REV.
A
8 7
6
5
4
3
=MCP_HDMI_TXC_P
17
=MCP_HDMI_TXC_N
17
=MCP_HDMI_TXD_P<0>
17
=MCP_HDMI_TXD_N<0>
17
=MCP_HDMI_TXD_P<1>
17
=MCP_HDMI_TXD_N<1>
17
DP_ML_P<0>
17 70 71 82
DP_ML_N<0> DP_ML_N<0>
17 70 71 82 17 70 71 82
DP_HPD
17 70 71 17 70 71
DP_IG_DDC_CLK
D
DP_AUX_CH_C_N
R9300
DP_IG_DDC_DATA
17 70
BI
Display Port Interoperability spec says that sources
or sinks which do both DP and DVI must depend on the external adapter for pull ups on DDC lines (since DP AUX CH has 100K pull up/down on the MLB)..
DP_IG_DDC_CLK
17 70
BI
C
33
1 2
5% 1/16W MF-LF
402
R9301
33
1 2
5% 1/16W MF-LF
402
C9301
0.1UF
1 2
10% 16V X5R 402
DP_AUX_CH_SW_P
82
SIGNAL_MODEL=DP_AUXCH_FET
3
D
S G
4
C9300
0.1UF
1 2
Q9300
SSM6N15FEAPE
SOT563
5
DP_AUX_CH_SW_N
82
10% 16V X5R 402
SIGNAL_MODEL=DP_AUXCH_FET
Q9300
SSM6N15FEAPE
SOT563
DP_AUX_CH_C_P
6
D
2
SG
1
71 82
BI
71 82
BI
17 70
DP_IG_DDC_DATA
17 70
DP_ML_P<3> DP_ML_N<3> DP_ML_P<2> DP_ML_N<2> DP_ML_P<1> DP_ML_N<1> DP_ML_P<0>
DP_HPD
DP_IG_DDC_CLK DP_IG_DDC_DATA
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE MAKE_BASE=TRUE
MAKE_BASE=TRUE MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
71 82
71 82
71 82
71 82
71 82
71 82
17 70 71 82
17 70
17 70
D
C
DP_IG_AUX_CH_P
17 77
BI
DP_IG_AUX_CH_N
17 77
BI
PP5V_S0
6 7
37 42 47 49 61 64
65 67 68 72
1
R9302
100K
1
R9306
1K
5% 1/16W MF-LF
402
2
B
DP_CA_DET
71
IN
5% 1/16W MF-LF 402
2
DDC_CA_DET_LS5V_L
Q9301
SSM3K15FV
3
D
SOD-VESM-HF
1
GS
2
DP_IG_CA_DET
B
17
OUT
DISPLAYPORT SUPPORT
A
SYNC_MASTER=K24_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
D
APPLE INC.
SCALE
NONE
SYNC_DATE=12/19/2008
051-7903
SHT
OF
70 83
A
REV.
A
8
7 6
5
4
3
2
1
8 7
Port Power Switch
CRITICAL
U9480
TPS2051B
D
17 19 21 22 24 28 32
20 32 35 40 67
82 6 7 35 36 42 52 62 66 67 68 69
6
IN
PP3V3_S5
PM_SLP_S3_L
C9480
10UF
6.3V
20% X5R
603
1
1
C9481
0.1UF
20% 10V
2
2
CERM 402
HDMI_CEC
C
70
12 17 18 20 21 22 23 26
OUT
1
R9425
1M
5% 1/16W MF-LF 402
2
49 53 57 58 61 66 67 68
PP3V3_S0
6 7 27 35 37 41 43 45 46 47 69 71 72 82
DP_CA_DET
DP_ML_P<3>
70 82
IN
DP_ML_N<3> DP_ML_CONN_N<3>
70 82
IN
DP_AUX_CH_C_P
70 82
BI
DP_AUX_CH_C_N
70 82
BI
C9414
0.1uF
C9415
0.1uF
R9443
100K
1/16W MF-LF
Q9440
2N7002DW-X-G
SOT-363
B
Q9440 must have Drain to Gate leakage of <500nA and Gate to Source resistance of >5MOhm
SOT23
5
IN
4
EN
GND
2
1 2
DP_ML_C_P<3>
1 2
DP_ML_C_N<3>
82 82
1
5%
402
2
6
D
2
G
S
1
2N7002DW-X-G
1
OUT
3
OC*
C9485
0.1UF
20% 10V
CERM
402
R9403 R9413
X5R 40210% 16V
X5R 40210% 16V
1
R9442
100K
5% 1/16W MF-LF
402
2
DP_CA_DET_L_Q
3
Q9440
SOT-363
4
1
2
D
G
S
TP_DPPWR_OC_L
CRITICAL
1
C9486
22UF
20%
6.3V
2
X5R-CERM 603
NO STUFF
0
1 2
NO STUFF
0
1 2
FL9403
12-OHM-100MA
TCM1210-4SM
SYM_VER-2
4
5
6
PP3V3_S0_DPILIM
MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V
R9420
100K
1/16W MF-LF
MF-LF
1/16W
MF-LF
1/16W
1
23
R9421
100K
5% 1/16W MF-LF
402
DP_CA_DET_Q
R9422
402
1
2
5%
4025%
4025%
1
2
1/16W MF-LF
402
1
1M
5%
2
82
DP_ML_CONN_P<3>
DP_ESD
CRITICAL
D9411
RCLAMP0524P
SLP2510P8
2 1
IO
9 10
NC NC
GND
3
DP to DVI/HDMI Cable Adapter (CA) has 100k pull-up to DP_PWR.
5
IO
L9400
FERR-120-OHM-3A
1 2
0603
1
C9400
0.01UF
20% 50V
2
CERM 603
PP3V3_S0_DPPWR
MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V
CRITICAL
J9400
DSPLYPRT-M97-1
F-RT-THSM
BOT ROW TOP ROW
TH PINS SM PINS
2
HOT_PLUG_DETECT
4
CONFIG1
6
CONFIG2 GND
10
ML_LANE3P
12
ML_LANE3N GND
16
AUX_CHP
18
AUX_CHN
20
DP_PWR
DP_ESD
CRITICAL
D9400
RCLAMP0504F
SC70-6-1
1
2 5
3
ML_LANE0P ML_LANE0N
ML_LANE1P ML_LANE1N
ML_LANE2P ML_LANE2N
SHIELD PINS
6
4
RETURN
2122
GND
GND
GND
MF-LF
1/16W
1/16W
4
82
82
82
82
4025%
4025%
4025%
MF-LF
4025%
DP_ML_C_P<0>
6
82
DP_ML_C_N<0>
82
DP_ML_C_P<1>
6
DP_ML_C_N<1>
DP_ML_C_P<2>
6
DP_ML_C_N<2>
C9410
0.1uF
C9411
0.1uF
C9412
0.1uF
C9413
0.1uF
C9416
0.1uF
C9417
0.1uF
1 2
1 2
1 2
1 2
1 2
1 2
DP_ML_P<0>
X5R 40210% 16V
DP_ML_N<0>
X5R 40210% 16V
DP_ML_P<1>
X5R 40210% 16V
DP_ML_N<1>
X5R 40210% 16V
DP_ML_P<2>
X5R 40210% 16V
DP_ML_N<2>
X5R 40210% 16V
D
17 70 82
IN
17 70 82
IN
70 82
IN
70 82
IN
70 82
IN
70 82
IN
C
B
IO
1 2
1 2
FL9401
SYM_VER-2
R9402 R9432
IO
3
4
R9400 R9430
MF-LF
1/16W
MF-LF
1/16W
FL9402
12-OHM-100MA
TCM1210-4SM
1
2 3
NO STUFF
0
1 2
NO STUFF
0
1 2
SYM_VER-2
0
0
4025%
4025%
4
DP_ESD
CRITICAL
D9410
RCLAMP0524P
SLP2510P8
2 1
IO NC NC
GND
3
NO STUFF
1 2
NO STUFF
1 2
FL9400
TCM1210-4SM
SYM_VER-2
MF-LF
MF-LF
IO
9 10
12-OHM-100MA
1
2 3
1/16W
1/16W
4
DP_ESD
CRITICAL
D9410
RCLAMP0524P
SLP2510P8
5 4
IO
6 7
NC NC
GND
3
NO STUFF
R9401 R9431
82
1 3 5
82
78 9 11
82
1314 15 17 19
82
DP_ML_CONN_P<1>
DP_ML_CONN_N<1>
82
82
0
NO STUFF
0
DP_ML_CONN_P<0> DP_ML_CONN_N<0>
12-OHM-100MA
TCM1210-4SM
1
2 3
DP_ML_CONN_P<2>
DP_ML_CONN_N<2>
DP_ESD
CRITICAL
D9411
RCLAMP0524P
SLP2510P8
5 4
IO
6 7
NC NC
GND
3
47 49 53 57 58 61 66
PP3V3_S0
6 7
12 17 18 20 21 22 23 26
27 35 37 41 43 45 46 67 68 69 71 72 82
DP_HPD
17 70
OUT
2N7002DW-X-G
A
8
R9445
1/16W MF-LF
Q9441
SOT-363
10K
402
5%
1
2
6
D
G
S
1
2N7002DW-X-G
2
DP_HPD_L_Q
R9444
10K
1/16W MF-LF
Q9441
SOT-363
402
1
5%
2
3
D
5
G
S
4
DP_HPD_Q
7 6
R9423
100K
1/16W MF-LF
402
1
5%
2
DP Source must pull
down HPD input with greater than or equal
to 100K (DPv1.1a).
DisplayPort Connector
SHT
71 83
1
SYNC_DATE=02/05/2009
REV.
A
OF
A
SYNC_MASTER=K19_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
APPLE INC.
5
4
3
2
SCALE
D
051-7903
NONE
8 7
6
5
*L9701, D9701, C9796, C9797, C9799, C9712 AND C9713 SHOULD ALL BE PLACED NEAR EACHOTHER.
4
*PPVOUT_S0_LCDBKLT_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.
* LVDS_IG_BKL_PWM SHOULD BE AWAY FROM BOOST CIRCUIT
3
BKL_VLDO_EN_L
CRITICAL
Q9701
NTZD3155C
3
SOT-563-HF
P-CHN
6
BKL_VLDO
6
1
2
NC
D
S
D
S
N-CHN
C9711
0.1UF
10%
VDDIO VLDO
16V X5R 402
6
ALSO
5
ALSI
20
ADR
3
IF_SEL
10
11
SDA
2
PWM
7
FAULT
4
EN
BKL_SGND
G
G
82322
U9701
OMIT
GND_SW
GND_S
9
1
5
4
2
1
1
R9702
0
5% 1/16W MF-LF 402
2
PPVIN_BKL
74
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.375 MM VOLTAGE=6V
NO STUFF
1
2
PPVIN_BKL_R
CRITICAL
VIN
LLP
SW
FB
OUT1
LP8543SQX
OUT2
OUT3SCLK
OUT4
OUT5
OUT6
OUT7
THRM
PAD
GND_L
15
25
XW9710
1 2
R9735
100K
1 2
1% 1/16W MF-LF
402
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM
BKLT_EN_R
CRITICAL
22UH-2.5A
1 2
R9703
0
5% 1/16W MF-LF 402
24
21
12
6
13
6
14
6
16
6
17
6
18
6
19
NC
SM
IHLP2525CZ-SM
BKL_ISEN1 BKL_ISEN2 BKL_ISEN3 BKL_ISEN4 BKL_ISEN5 BKL_ISEN6
L9701
R9701
0
1 2
5% 1/16W MF-LF
402
PPBUS_S0_LCDBKLT_PWR_SW
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.375 MM VOLTAGE=50V
SWITCH_NODE=TRUE
PP5V_S0
BKLT_EN
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
6 7
37 42 47 49 61 64 65 67 68
70
72
CRITICAL
D9701
SOD-123
1 2
RB160M-60G
R9717
10.2
1 2
0.1%
1/16W
TF
402
R9718
10.2
1 2
0.1%
1/16W
TF
402
R9719
10.2
1 2
0.1%
1/16W
TF
402
R9720
10.2
1 2
0.1%
1/16W
TF
402
R9721
10.2
1 2
0.1%
1/16W
TF
402
R9722
10.2
1 2
0.1%
1/16W
TF
402
1
C9796
220PF
10% 50V
2
X7R-CERM 402
1
C9799
2.2UF
10% 100V
2
X7R 1210
LED_RETURN_1
LED_RETURN_2
LED_RETURN_3
LED_RETURN_4
LED_RETURN_5
LED_RETURN_6
PPVOUT_S0_LCDBKLT
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.375 MM
C9797
2.2UF
10% 100V X7R 1210
VOLTAGE=50V
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
1
2
6
51 69 74
6
69 74
OUT
6
69 74
OUT
6
69 74
OUT
6
69 74
OUT
6
69 74
OUT
6
69 74
OUT
D
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V
XW9720
SM
PPBUS_S0_LCDBKLT_PWR
72 73
C
51 82
51 82
SMBUS_MCP_1_CLK
20 43 58 78
SMBUS_MCP_1_DATA
B
20 43 58 78
PPBUS_S0_LCDBKLT_PWR
72 73
ISNS_LCDBKLT_P
OUT
ISNS_LCDBKLT_N
OUT
R9753
R9757
17 73 74
8
IN
XW9721
57 58 61 66 67 68 69 71 82
12 17 18 20 21 22 23 26
0
1 2
0
1 2
R9731
1 2
301K
1% 1/16W MF-LF
402
LCD_BKLT_PWM
R9704 SHOULD BE 47K IF RC FILTER IS USED
1 2
SM
1 2
PP3V3_S0
6 7 27 35 37 41 43 45 46 47 49 53
IF_SEL=1 FOR SMBUS
1/16W
5%
5%
1/16W
NO STUFF
1
C9723
0.1UF
10% 25V
2
X5R 402
MF-LF
MF-LF
SM
XW9722
1 2
402
402
R9715
100K
1% 1/16W MF-LF
402
1 2
R9704
1 2
1/16W MF-LF
R9716
100K
1/16W MF-LF
NO STUFF
R9714
100K
1/16W MF-LF
0
5%
402
CRITICAL
1
2
1
5%
402
2
1
5%
402
2
NO STUFF
C9712
10UF
10% 25V X5R 805
1
C9704
33PF
5% 50V
2
CERM 402
1
C9713
0.1UF
10% 25V
2
X5R 402
1
C9714
0.01UF
10% 16V
2
CERM 402
1
C9710
1UF
10% 25V
2
X5R 603-1
BKL_IF_SEL BKL_SCL BKL_SDA
LVDS_BKL_PWM_RC
TP_BKL_FAULT
BKLT_EN
72
PLACE XW9700 CLOSE TO C9712 AND C9713
D
C
B
LCD BACKLIGHT DRIVER
SHT
72
1
SYNC_DATE=02/10/2009
REV.
A
OF
83
A
A
PART NUMBER
353S2670
QTY
1
8
DESCRIPTION
IC,LP8543,WHT LED BKLT,PROD
REFERENCE DES
U9701
7 6
CRITICAL
CRITICAL
BOM OPTION
5
4
3
SYNC_MASTER=K19_MLB
APPLE INC.
2
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
D
SCALE
051-7903
NONE
8 7
F9800
2AMP-32V
PPBUS_G3H
6 7
35 44 45 59 60 62 63 64
IN
MIN_LINE_WIDTH=0.4 mm
D
MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V
1 2
0402-HF
6
PPBUS_S0_LCDBKLT_FUSED
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V
Q9807
SSM6N15FEAPE
SOT563
1
R9808
301K
1% 1/16W MF-LF 402
2
PPBUS_S0_LCDBKLT_EN_L
3
D
1
C9802
0.1UF
10% 16V
2
X5R 402
PPBUS_S0_LCDBKLT_EN_DIV
1
R9809
147K
1% 1/16W MF-LF 402
2
5
CRITICAL
Q9806
FDC638APZ_SBMS001
SSOT6-HF
4
3
PPBUS S0 LCDBkLT FET
MOSFET
CHANNEL
1 2 5 6
RDS(ON)
LOADING 0.4 A (EDP)
4
FDC638APZ
P-TYPE
43 mOhm @4.5V
3
D
5
SG
LVDS_BKL_ON
8
17 73
IN
C
BKLT_PLT_RST_L
24
IN
4
Q9807
SSM6N15FEAPE
SOT563
BKLT_EN_L
2
6
D
SG
1
PPBUS_S0_LCDBKLT_PWR
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V
B
72
OUT
C
B
1
R9840
1K
5% 1/16W MF-LF 402
2
1
R9841
1K
5% 1/16W MF-LF 402
2
LVDS_BKL_ON LCD_BKLT_PWM
8
17 73
8
17 72 74
MCP HAS INTERNAL 10K PULL-UP FOR THESE SIGNALS
LCD Backlight Support
SHT
1
SYNC_DATE=03/16/2009
REV.
A
OF
8373
A
A
8
7 6
5
4
3
SYNC_MASTER=K24_MLB
APPLE INC.
2
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
D
SCALE
.
051-7903
NONE
8 7
6
5
4
3
D
BKLT_FS
BKLT_FS
1
R9930
10
5% 1/16W MF-LF 402
2
LCDBKLT_VIN
MIN_LINE_WIDTH=0.3 MM
1
MIN_NECK_WIDTH=0.2 MM
VIN
U9900
LLP
PGNDA
5
2
CRITICAL
L9910
10UH-2.1A
1 2
IHLP2020BZ11-SM
SWA SWB
VOUT
OVP
CH1
CH2
CH3
CH4
CH5
CH6
FAIL
THRM
PAD
PGNDB
25
GND_LCDBKLT
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V
PPVOUT_S0_LCDBKLT_SW
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.38 MM VOLTAGE=50V SWITCH_NODE=TRUE
f = 600kHz
(PGND)
4 3
24
OVP = Vovp * (1 + Ra/Rb) Vovp = 6.5V +/- 0.35V
22
LCDBKLT_OVP
7
BKL_MC_CH1
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
8
BKL_MC_CH2
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
9
BKL_MC_CH3
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
10
BKL_MC_CH4
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
11
BKL_MC_CH5
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
12
BKL_MC_CH6
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
14
LCDBKLT_FAIL
NO STUFF
R9902
NO STUFF
R9901
0
PPVIN_BKL
1 2
5%
1/8W
MF-LF
805
PLACEMENT_NOTEs:
Place near L9910 & pin1 of U9900
BKLT_FS
1
C9911
0.1UF
10% 25V
2
X5R 402
C
LCDBKLT_COMP_RC
BKLT_FS
1
C9905
0.0022UF
10% 50V
2
CERM 402
B
BKLT_FS
C9900
2.2UF
X5R-CERM
BKLT_FS
R9905
6.8K
1/16W MF-LF
BKLT_FS
C9906
(C9910-C9911)
1
20% 10V
2
402
8
17 72 73
IN
MIN_LINE_WIDTH=0.2 MM
1
5%
402
2
1
56PF
5%
50V
2
CERM
402
PP2V5_S0_LCDBKLT
MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=2.5V
PP5V5_S0_LCDBKLT
MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5.5V
1
C9901
2.2UF
2
(SGND)
ISET = 153mA / <Riset>
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.38 MM VOLTAGE=9V
PPVIN_BKL_U9900
CRITICAL
BKLT_FS
C9910
10UF
BKLT_FS
20% 10V X5R-CERM 402
LCD_BKLT_PWM
LCDBKLT_COMP LCDBKLT_ISET
MIN_LINE_WIDTH=0.2 MM
OMIT
1
R9910
NOSTUFF
NONE NONE NONE 402
2
<Riset>
1
10% 25V
2
X5R 805
20
VDC1
23
VDC2
NO STUFF CRITICAL
MC34845
16
PWM
18
WAKE
6
EN
17
COMP
15
ISET
GND
131921
PLACEMENT_NOTE=Place near L9910
NO STUFF CRITICAL
D9910
SOD-123 1 2
RB160M-60G
BKLT_FS
1
R9915
1M
1% 1/16W MF-LF
402
2
<Ra>
OMIT
1
R9916
NOSTUFF
NONE NONE NONE
<Rb>
402
2
1/16W MF-LF
1
0
5%
402
2
BKLT_FS
1
C9915
2.2UF
10% 100V
2
X7R 1210
BKLT_FS
1
C9916
2.2UF
10% 100V
2
X7R 1210
BKLT_FS
1
C9917
200PF
5% 100V
2
CERM 1206
WF: C9911 and C9917 not in ref schematic.
NO STUFF
1
C9921
100PF
5% 50V
2
CERM 402
NO STUFF
C9922
100PF
XW9900
SM
1 2
CERM
NO STUFF
1
C9923
100PF
5% 50V
2
CERM 402
NO STUFF
1
C9924
5%
50V 402
100PF
2
CERM
NO STUFF
1
C9925
100PF
5% 50V
2
CERM 402
NO STUFF
1
C9926
5%
50V 402
100PF
2
CERM
PLACEMENT_NOTEs: Place near U9900
Place near U9900
Place near U9900
Place near U9900
Place near U9900
Place near U9900 (C9921-C9926)
1
5%
50V
2
R9917
402
1 2
R9920
1 2
PPVOUT_S0_LCDBKLT
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.375 MM VOLTAGE=50V
10.2
R9918
0.1%
1/16W
10.2
1 2
TF
402
0.1%
1/16W
10.2
R9921
0.1%
1/16W
10.2
1 2
TF
402
0.1%
1/16W
TF
402
6
51 69 72 72
LED_RETURN_1
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
LED_RETURN_2
10.2
0.1%
1/16W
TF
402
10.2
0.1%
1/16W
TF
402
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
LED_RETURN_3
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
LED_RETURN_4
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
LED_RETURN_5
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
LED_RETURN_6
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
R9919
1 2
TF
402
R9922
1 2
6
69 72
IN
6
69 72
IN
6
69 72
IN
6
69 72
IN
6
69 72
IN
6
69 72
IN
D
C
B
13.3 Inch Panel (9 LEDs per string)
PART NUMBER
QTY
114S0298 ?
1114S0445
Target: ISET = 23mA, OVP = 35V Actual: ISET = 23mA, OVP = 35.2V
DESCRIPTION
RES,MTL FILM,1/16W,6.65K,1,0402,SMD,LF
RES,MTL FILM,1/16W,226K,1,0402,SMD,LF
REFERENCE DES
R99101
CRITICAL
?R9916
BOM OPTION
LCD_13INCH LCD_13INCH
WF: Need 6.65K 0.1% resistor?
15.4 Inch Panel (10/11 LEDs per string)
PART NUMBER
QTY
1114S0298
114S0438
Target: ISET = 23mA, OVP = 40V Actual: ISET = 23mA, OVP = 40.5V
A
17 Inch Panel (14 LEDs per string)
PART NUMBER
114S0299
QTY
1 ?R9910
114S0428
Target: ISET = 22.5mA, OVP = 50V Actual: ISET = 22.47mA, OVP = 49.8V
8
7 6
DESCRIPTION
RES,MTL FILM,1/16W,6.65K,1,0402,SMD,LF
RES,MTL FILM,1/16W,191K,1,0402,SMD,LF
DESCRIPTION
RES,MTL FILM,1/16W,6.81K,1,0402,SMD,LF
RES,MTL FILM,1/16W,150K,1,0402,SMD,LF
REFERENCE DES
R9910
REFERENCE DES
R99161 ?
5
CRITICAL
? ?1 R9916
CRITICAL
BOM OPTION
LCD_15INCH LCD_15INCH
BOM OPTION
LCD_17INCH LCD_17INCH
WF: Need 6.65K 0.1% resistor?
WF: Need 6.80K 0.1% resistor?
4
LCD Backlight Driver (MC34845)
SYNC_MASTER=VEMURI_K19I
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
APPLE INC.
3
2
SCALE
SYNC_DATE=02/09/2009
DRAWING NUMBER
051-7903
SHT
NONE
OF
74 83
1
A
REV.
A
8 7
FSB (Front-Side Bus) Constraints
LAYER
FSB_50S
FSB_DSTB_50S
LAYER
D
SPACING_RULE_SET
FSB_DATA FSB_DSTB FSB_ADDR
FSB_ADSTB
FSB_1X
ALLOW ROUTE ON LAYER?
* =STANDARD
=50_OHM_SE
=50_OHM_SE
*
LINE-TO-LINE SPACING
*
=2x_DIELECTRIC
*
=3x_DIELECTRIC * *
=2x_DIELECTRIC *
=STANDARD
=STANDARD
MINIMUM LINE WIDTH
=50_OHM_SE
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
=50_OHM_SE =50_OHM_SE
=50_OHM_SE=50_OHM_SE=50_OHM_SE
SPACING_RULE_SET
FSB_DATA FSB_DSTB FSB_ADDR
FSB_ADSTB
FSB_1X
LAYER
TOP,BOTTOM TOP,BOTTOM TOP,BOTTOM?=3x_DIELECTRIC TOP,BOTTOM TOP,BOTTOM?=3x_DIELECTRIC
DIFFPAIR PRIMARY GAP
LINE-TO-LINE SPACING
=4x_DIELECTRIC =5x_DIELECTRIC
=4x_DIELECTRIC
6
=STANDARD
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
WEIGHT
? ?
?
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
=1:1_DIFFPAIR=1:1_DIFFPAIR
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
All 4x/2x/1x FSB signals with impedance requirements are 50-ohm single-ended. FSB 4X signals / groups shown in signal table on right.
Signals within each 4x group should be matched within 5 ps of strobe. DSTB# complementary pairs should be matched within 1 ps of each other, all DSTB#s matched to +/- 300 ps. Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s. DSTB# complementary pairs are spaced normally and are NOT routed as differential pairs.
FSB 2X signals / groups shown in signal table on right. Signals within each 2x group should be matched within 20 ps. ADTSB#s should be matched +/- 300 ps. Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB#.
FSB 1X signals shown in signal table on right. Signals within each 1x group should be matched to CPU clock, +0/-1000 mils.
Design Guide recommends each strobe/signal group is routed on the same layer. Intel Design Guide recommends FSB signals be routed only on internal layers.
NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened. SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2
SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3
CPU Signal Constraints
C
CPU_50S
LAYER
CPU_27P4S
ALLOW ROUTE ON LAYER?
* =STANDARD =STANDARD
=27P4_OHM_SE*
MINIMUM LINE WIDTH
=27P4_OHM_SE
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
=50_OHM_SE =50_OHM_SE=50_OHM_SE =50_OHM_SE
=27P4_OHM_SE =27P4_OHM_SE
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
7 MIL7 MIL
NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.
TABLE_SPACING_RULE_HEAD
WEIGHT
SPACING_RULE_SET
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
CPU_AGTL
SR DG recommends at least 25 mils, >50 mils preferred
* * * * * *
LINE-TO-LINE SPACING
=STANDARD
8 MIL 25 MIL 25 MIL
=2:1_SPACING
25 MIL
SPACING_RULE_SET
LAYER
CPU_AGTL CPU_8MIL CPU_COMP
CPU_GTLREF
CPU_ITP
CPU_VCCSENSE
Most CPU signals with impedance requirements are 55-ohm single-ended. Some signals require 27.4-ohm single-ended impedance.
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2 SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4
MCP FSB COMP Signal Constraints
B
MCP_50S
SPACING_RULE_SET
MCP_FSB_COMP
LAYER
LAYER
ALLOW ROUTE ON LAYER?
=50_OHM_SE =50_OHM_SE=50_OHM_SE
* =STANDARD =STANDARD
LINE-TO-LINE SPACING
*
8 MIL
MINIMUM LINE WIDTH
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
MINIMUM NECK WIDTH
=50_OHM_SE
LAYER
TOP,BOTTOM
MAXIMUM NECK LENGTH
LINE-TO-LINE SPACING
=2x_DIELECTRIC
DIFFPAIR PRIMARY GAP
WEIGHT
?
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.4
FSB Clock Constraints
CLK_FSB_100D
SPACING_RULE_SET
CLK_FSB
LAYER
LAYER
*
*
ALLOW ROUTE ON LAYER?
=100_OHM_DIFF
LINE-TO-LINE SPACING
=3x_DIELECTRIC
MINIMUM LINE WIDTH
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
MINIMUM NECK WIDTH
SPACING_RULE_SET
MAXIMUM NECK LENGTH
=100_OHM_DIFF=100_OHM_DIFF =100_OHM_DIFF
LAYER
TOP,BOTTOM
DIFFPAIR PRIMARY GAP
=100_OHM_DIFF
LINE-TO-LINE SPACING
=4x_DIELECTRICCLK_FSB
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
=100_OHM_DIFF
TABLE_SPACING_RULE_HEAD
WEIGHT
TABLE_SPACING_RULE_ITEM
?
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.5
A
5
CPU / FSB Net Properties
ELECTRICAL_CONSTRAINT_SET
FSB_DATA_GROUP0 FSB_DATA_GROUP0 FSB_DSTB0 FSB_DSTB0
FSB_DATA_GROUP1 FSB_DATA_GROUP1 FSB_DSTB1 FSB_DSTB1
FSB_DATA_GROUP2 FSB_DATA_GROUP2 FSB_DSTB2 FSB_DSTB2
FSB 4X Signal Groups
FSB 2X
Signals
FSB 1X Signals
FSB_DATA_GROUP3 FSB_DATA_GROUP3 FSB_DSTB3 FSB_DSTB3
FSB_ADDR_GROUP0 FSB_ADDR_GROUP0 FSB_ADSTB0
FSB_ADDR_GROUP1 FSB_ADSTB1
FSB_BREQ0_L FSB_BREQ1_L
FSB_1X FSB_1X FSB_1X FSB_1X
FSB_CPURST_L FSB_1X FSB_1X
CPU_ASYNC CPU_BSEL CPU_FERR_L CPU_ASYNC CPU_INIT_L CPU_ASYNC_R CPU_ASYNC_R CPU_PROCHOT_L CPU_PWRGD CPU_ASYNC CPU_ASYNC PM_THRMTRIP_L FSB_CPUSLP_L CPU_FROM_SB CPU_DPRSTP_L CPU_ASYNC MCP_CPU_COMP MCP_FSB_COMP MCP_CPU_COMP MCP_FSB_COMP MCP_CPU_COMP MCP_FSB_COMP MCP_CPU_COMP MCP_FSB_COMP
FSB_CLK_CPU FSB_CLK_CPU FSB_CLK_ITP FSB_CLK_ITP FSB_CLK_MCP FSB_CLK_MCP
CPU_IERR_L
PM_DPRSLPVR
(See above)
CPU_GTLREF CPU_COMP CPU_COMP CPU_COMP
XDP_TRST_L XDP_BPM_L XDP_BPM_L5
(FSB_CPURST_L)
CPU_VCCSENSE CPU_VCCSENSE
(CPU_VCCSENSE) (CPU_VCCSENSE)
4
PHYSICAL
FSB_50S FSB_50S
FSB_DSTB_50S
FSB_50S FSB_50S FSB_DSTB_50S
FSB_50S FSB_50S FSB_DSTB_50S
FSB_50S FSB_50S FSB_DSTB_50S
FSB_50S FSB_50S FSB_50S
FSB_50S FSB_50S
FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S
CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S MCP_50S MCP_50S MCP_50S MCP_50S
CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D
CPU_50S
CPU_50S CPU_50S
CPU_50S CPU_50S CPU_27P4S CPU_50S CPU_27P4S
CPU_50S
CPU_50S CPU_ITP
CPU_50S CPU_50S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S
NET_TYPE
SPACING
FSB_DATA FSB_DATA FSB_DSTBFSB_DSTB_50S FSB_DSTB
FSB_DATA FSB_DATA FSB_DSTB FSB_DSTBFSB_DSTB_50S
FSB_DATA FSB_DATA FSB_DSTB FSB_DSTBFSB_DSTB_50S
FSB_DATA FSB_DATA FSB_DSTB FSB_DSTBFSB_DSTB_50S
FSB_ADDR FSB_ADDR FSB_ADSTB
FSB_ADDR FSB_ADSTB
FSB_1XFSB_1X FSB_1X FSB_1X FSB_1XFSB_1X FSB_1XFSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1XFSB_1X FSB_1XFSB_1X FSB_1X FSB_1X FSB_1X
CPU_AGTL CPU_AGTL CPU_8MIL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_8MIL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL
CLK_FSB CLK_FSB CLK_FSB CLK_FSB CLK_FSB CLK_FSB
CPU_AGTL CPU_AGTL
CPU_GTLREF CPU_COMP CPU_COMP CPU_COMP CPU_COMPCPU_COMP
CPU_ITPCPU_50SXDP_TDI CPU_ITPCPU_50SXDP_TDO CPU_ITPCPU_50SXDP_TMS CPU_ITPCPU_50SXDP_TCK CPU_ITPCPU_50S CPU_ITP CPU_ITPCPU_50S
CPU_8MIL CPU_8MIL CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE
FSB_D_L<15..0> FSB_DINV_L<0> FSB_DSTB_L_P<0> FSB_DSTB_L_N<0>
FSB_D_L<31..16> FSB_DINV_L<1> FSB_DSTB_L_P<1> FSB_DSTB_L_N<1>
FSB_D_L<47..32> FSB_DINV_L<2> FSB_DSTB_L_P<2> FSB_DSTB_L_N<2>
FSB_D_L<63..48> FSB_DINV_L<3> FSB_DSTB_L_P<3> FSB_DSTB_L_N<3>
FSB_A_L<16..3> FSB_REQ_L<4..0> FSB_ADSTB_L<0>
FSB_A_L<35..17> FSB_ADSTB_L<1>
FSB_ADS_L FSB_BREQ0_L FSB_BREQ1_L FSB_BNR_L FSB_BPRI_L FSB_DBSY_L FSB_DEFER_L FSB_DRDY_L FSB_HIT_L FSB_HITM_L FSB_LOCK_L FSB_CPURST_L FSB_RS_L<2..0> FSB_TRDY_L
CPU_A20M_L CPU_BSEL<2..0> CPU_FERR_L CPU_IGNNE_L CPU_INIT_L CPU_INTR CPU_NMI CPU_PROCHOT_L CPU_PWRGD CPU_SMI_L CPU_STPCLK_L PM_THRMTRIP_L FSB_CPUSLP_L CPU_DPSLP_L CPU_DPRSTP_L
FSB_DPWR_L MCP_BCLK_VML_COMP_VDD MCP_BCLK_VML_COMP_GND MCP_CPU_COMP_VCC MCP_CPU_COMP_GND
FSB_CLK_CPU_P
FSB_CLK_CPU_N
FSB_CLK_ITP_P
FSB_CLK_ITP_N
FSB_CLK_MCP_P
FSB_CLK_MCP_N
CPU_IERR_L
PM_DPRSLPVR
IMVP_DPRSLPVR
CPU_GTLREF
CPU_COMP<3>
CPU_COMP<2>
CPU_COMP<1>
CPU_COMP<0>
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TCK
XDP_TRST_L
XDP_BPM_L<4..0>
XDP_BPM_L<5>
XDP_CPURST_L
CPU_VID<6..0>
IMVP6_VID<6..0>
CPU_VCCSENSE_P
CPU_VCCSENSE_N
IMVP6_VSEN_P
IMVP6_VSEN_N
3
6 9
13
6 9
13
6 9
13
6 9
13
6 9
13
6 9
13
6 9
13
6 9
13
6 9
13
6 9
13
6 9
13
6 9
13
6 9
13
6 9
13
6 9
13
6 9
13
6 9
13
6 9
13
6 9
13
6 9
13
6 9
13
6 9
13
9
13
13
9
13
9
13
9
13
9
13
9
13
6 9
13
6 9
13
6 9
13
9
12 13
9
13
9
13
9
13
8 9
9
13
9
13
9
13
9
13
9
13
9
13 41 61
9
12 13
9
13
9
13
9
13 41
9
13
9
13
9
13 61
9
13
13
13
13
13
9
13
9
13
12 13
12 13
13
13
9
20 61
61
9
25
9
9
9
9
12
9
1 9
12
9
12
9
12
9
12
9
12
9
12
12
8
10
8
61
10 61
10 61
61
61
CPU/FSB Constraints
SYNC_MASTER=T18_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
APPLE INC.
SCALE
DRAWING NUMBER
D
NONE
SYNC_DATE=02/05/2009
051-7903
SHT
75 83
D
C
B
A
REV.
A
OF
8
7 6
5
4
3
2
1
8 7
6
Memory Bus Constraints
LAYER
ALLOW ROUTE ON LAYER?
MEM_40S
=40_OHM_SE
=70_OHM_DIFF
=70_OHM_DIFF
* =70_OHM_DIFF =70_OHM_DIFF
* * * * * * * *
LINE-TO-LINE SPACING
=4:1_SPACING
=2:1_SPACING =2.5:1_SPACING =1.5:1_SPACING
=3:1_SPACING =1.5:1_SPACING
=3:1_SPACINGMEM_DATA2MEM
=3:1_SPACING
LAYER
*
D
MEM_40S_VDD
MEM_70D
MEM_70D_VDD
SPACING_RULE_SET
MEM_CLK2MEM
MEM_CTRL2CTRL
MEM_CTRL2MEM
MEM_CMD2CMD MEM_CMD2MEM
MEM_DATA2DATA
MEM_DQS2MEM
MEM_2OTHER
Memory Bus Spacing Group Assignments
NET_SPACING_TYPE1 NET_SPACING_TYPE2
MEM_CLKMEM_CLK MEM_CLK MEM_CLK MEM_CLK MEM_CLK
NET_SPACING_TYPE1 NET_SPACING_TYPE2
C
MEM_CTRL MEM_CTRL MEM_CTRL MEM_CTRL MEM_CTRL
NET_SPACING_TYPE1 NET_SPACING_TYPE2
MEM_DQS MEM_DQS MEM_DQS MEM_CMD MEM_DQS MEM_DQS MEM_DQS
DDR2:
DQ signals should be matched within 20 ps of associated DQS pair. DQS intra-pair matching should be within 1 ps, no inter-pair matching requirement. All DQS pairs should be matched within 100 ps of clocks. CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 140 ps. A/BA/cmd signals should be matched within 75 ps, no CLK matching requirement. All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate).
B
DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.
DDR3:
DQ signals should be matched within 5 ps of associated DQS pair. DQS intra-pair matching should be within 1 ps, inter-pair matching shoulw be within 180 ps No DQS to clock matching requirement. CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 2 ps. A/BA/cmd signals should be matched within 5 ps of CLK pairs. All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate). DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3 SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2
MEM_CTRL
MEM_CMD
MEM_DATA
MEM_DQS
MEM_CLK
MEM_CTRL
MEM_CMD
MEM_DATA
MEM_DQS
MEM_CLK
MEM_CTRL
MEM_DATA
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
=40_OHM_SE =40_OHM_SE =40_OHM_SE
=70_OHM_DIFF
25 MIL
AREA_TYPE
* * * * *
AREA_TYPE
* * * * *
AREA_TYPE
* * * * *
=70_OHM_DIFF
WEIGHT
SPACING_RULE_SET
MEM_CLK2MEM MEM_CLK2MEM MEM_CLK2MEM MEM_CLK2MEM MEM_CLK2MEM
SPACING_RULE_SET
MEM_CTRL2MEM
MEM_CTRL2CTRL
MEM_CTRL2MEM MEM_CTRL2MEM MEM_CTRL2MEM
SPACING_RULE_SET
MEM_DQS2MEM MEM_DQS2MEM MEM_DQS2MEM MEM_DQS2MEM MEM_DQS2MEM
=70_OHM_DIFF =70_OHM_DIFF
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CMD MEM_CMD
MEM_CMD MEM_CMD
NET_SPACING_TYPE1 NET_SPACING_TYPE2
MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA
NET_SPACING_TYPE1 NET_SPACING_TYPE2
MEM_CLK
MEM_CTRL
MEM_CMD
MEM_DATA
MEM_DQS
Need to support MEM_*-style wildcards!
MAXIMUM NECK LENGTH
=40_OHM_SE=40_OHM_SE=40_OHM_SE=40_OHM_SE
=70_OHM_DIFF=70_OHM_DIFF
MEM_CLK
MEM_CTRL
MEM_CMDMEM_CMD
MEM_DATA
MEM_DQS
MEM_CLK
MEM_CTRL
MEM_CMD
MEM_DATA
MEM_DQS
* *
* *
* *
DIFFPAIR PRIMARY GAP
=STANDARD* =STANDARD
AREA_TYPE
SPACING_RULE_SET
* * * * *
AREA_TYPE
SPACING_RULE_SET
* * * *
MEM_DATA2DATA
*
AREA_TYPE
SPACING_RULE_SET
**
**
MCP MEM COMP Signal Constraints
LAYER
ALLOW ROUTE ON LAYER?
MCP_MEM_COMP
SPACING_RULE_SET
MCP_MEM_COMP
LAYER
LINE-TO-LINE SPACING
*
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3.4
Y
8 MIL
MINIMUM LINE WIDTH
7 MIL 7 MIL
TABLE_SPACING_RULE_HEAD
WEIGHT
TABLE_SPACING_RULE_ITEM
?
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
=STANDARD
DIFFPAIR PRIMARY GAP
A
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
=STANDARD* =STANDARD
=70_OHM_DIFF=70_OHM_DIFF*
MEM_CMD2MEM MEM_CMD2MEM MEM_CMD2CMD MEM_CMD2MEM MEM_CMD2MEM
MEM_DATA2MEM MEM_DATA2MEM MEM_DATA2MEM
MEM_DATA2MEM
MEM_2OTHER MEM_2OTHER MEM_2OTHER MEM_2OTHER MEM_2OTHER
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
=STANDARD=STANDARD*
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
5
Memory Net Properties
ELECTRICAL_CONSTRAINT_SET
MEM_A_CLK MEM_A_CLK
MEM_A_CNTL MEM_A_CNTL MEM_A_CNTL
MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_CMD
MEM_A_DQ_BYTE0 MEM_A_DQ_BYTE1 MEM_A_DQ_BYTE2 MEM_A_DQ_BYTE3 MEM_40S MEM_A_DQ_BYTE4 MEM_40S MEM_A_DQ_BYTE5 MEM_40S MEM_A_DQ_BYTE6 MEM_A_DQ_BYTE7
MEM_A_DQ_BYTE0 MEM_40S MEM_A_DQ_BYTE1 MEM_40S MEM_A_DQ_BYTE2 MEM_40S MEM_A_DQ_BYTE3 MEM_40S MEM_A_DQ_BYTE4 MEM_40S MEM_A_DQ_BYTE5 MEM_40S MEM_A_DQ_BYTE6 MEM_40S MEM_A_DQ_BYTE7 MEM_40S
MEM_A_DQS0 MEM_A_DQS0 MEM_A_DQS1 MEM_A_DQS1 MEM_A_DQS2 MEM_A_DQS2 MEM_A_DQS3 MEM_A_DQS3 MEM_A_DQS4 MEM_A_DQS4 MEM_A_DQS5 MEM_A_DQS5 MEM_A_DQS6 MEM_A_DQS6 MEM_A_DQS7 MEM_A_DQS7
MEM_B_CLK MEM_B_CLK
MEM_B_CNTL MEM_B_CNTL MEM_B_CNTL
MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_B_CMD
MEM_B_DQ_BYTE0 MEM_B_DQ_BYTE1 MEM_B_DQ_BYTE2 MEM_B_DQ_BYTE3 MEM_B_DQ_BYTE4 MEM_40S MEM_B_DQ_BYTE5 MEM_B_DQ_BYTE6 MEM_B_DQ_BYTE7
MEM_B_DQ_BYTE0 MEM_B_DQ_BYTE1 MEM_B_DQ_BYTE2 MEM_B_DQ_BYTE3 MEM_B_DQ_BYTE4 MEM_B_DQ_BYTE5 MEM_B_DQ_BYTE6 MEM_B_DQ_BYTE7
MEM_B_DQS0 MEM_B_DQS0 MEM_B_DQS1 MEM_B_DQS1 MEM_B_DQS2 MEM_B_DQS2 MEM_B_DQS3 MEM_B_DQS3 MEM_B_DQS4 MEM_B_DQS4 MEM_B_DQS5 MEM_B_DQS5 MEM_B_DQS6 MEM_B_DQS6 MEM_B_DQS7 MEM_B_DQS7
MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP
4
PHYSICAL
MEM_70D_VDD MEM_70D_VDD
MEM_40S_VDD MEM_40S_VDD MEM_40S_VDD
MEM_40S_VDD MEM_40S_VDD MEM_40S_VDD MEM_40S_VDD MEM_40S_VDD
MEM_40S MEM_40S MEM_40S
MEM_40S MEM_40S
MEM_70D
MEM_70D
MEM_70D
MEM_70D MEM_70D
MEM_70D
MEM_70D_VDD MEM_70D_VDD
MEM_40S_VDD MEM_40S_VDD MEM_40S_VDD
MEM_40S_VDD MEM_40S_VDD MEM_40S_VDD MEM_40S_VDD MEM_40S_VDD
MEM_40S MEM_40S MEM_40S MEM_40S
MEM_40S MEM_40S MEM_40S
MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S
MEM_70D MEM_DQS MEM_70D MEM_DQS MEM_70D MEM_DQS MEM_70D MEM_DQS MEM_70D MEM_DQS MEM_70D MEM_DQS MEM_70D MEM_DQS MEM_70D MEM_DQS MEM_70D MEM_DQS MEM_70D MEM_70D MEM_DQS MEM_70D MEM_DQS MEM_70D MEM_DQS MEM_70D MEM_DQS MEM_70D MEM_DQS MEM_70D MEM_DQS
NET_TYPE
SPACING
MEM_CLK MEM_CLK
MEM_CTRL MEM_CTRL MEM_CTRL
MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_CMD
MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA
MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA
MEM_DQSMEM_70D MEM_DQSMEM_70D MEM_DQS MEM_DQSMEM_70D MEM_DQSMEM_70D MEM_DQS MEM_DQSMEM_70D MEM_DQSMEM_70D MEM_DQSMEM_70D MEM_DQS MEM_DQSMEM_70D MEM_DQSMEM_70D MEM_DQS MEM_DQS MEM_DQSMEM_70D MEM_DQS
MEM_CLK MEM_CLK
MEM_CTRL MEM_CTRL MEM_CTRL
MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_CMD
MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA
MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA
MEM_DQS
MEM_A_CLK_P<5..0> MEM_A_CLK_N<5..0>
MEM_A_CKE<3..0> MEM_A_CS_L<3..0> MEM_A_ODT<3..0>
MEM_A_A<14..0> MEM_A_BA<2..0> MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L
MEM_A_DQ<7..0> MEM_A_DQ<15..8> MEM_A_DQ<23..16> MEM_A_DQ<31..24> MEM_A_DQ<39..32> MEM_A_DQ<47..40> MEM_A_DQ<55..48> MEM_A_DQ<63..56>
MEM_A_DM<0> MEM_A_DM<1> MEM_A_DM<2> MEM_A_DM<3> MEM_A_DM<4> MEM_A_DM<5> MEM_A_DM<6> MEM_A_DM<7>
MEM_A_DQS_P<0> MEM_A_DQS_N<0> MEM_A_DQS_P<1> MEM_A_DQS_N<1> MEM_A_DQS_P<2> MEM_A_DQS_N<2> MEM_A_DQS_P<3> MEM_A_DQS_N<3> MEM_A_DQS_P<4> MEM_A_DQS_N<4> MEM_A_DQS_P<5> MEM_A_DQS_N<5> MEM_A_DQS_P<6> MEM_A_DQS_N<6> MEM_A_DQS_P<7> MEM_A_DQS_N<7>
MEM_B_CLK_P<5..0> MEM_B_CLK_N<5..0>
MEM_B_CKE<3..0> MEM_B_CS_L<3..0> MEM_B_ODT<3..0>
MEM_B_A<14..0> MEM_B_BA<2..0> MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L
MEM_B_DQ<7..0> MEM_B_DQ<15..8> MEM_B_DQ<23..16> MEM_B_DQ<31..24> MEM_B_DQ<39..32> MEM_B_DQ<47..40> MEM_B_DQ<55..48> MEM_B_DQ<63..56>
MEM_B_DM<0> MEM_B_DM<1> MEM_B_DM<2> MEM_B_DM<3> MEM_B_DM<4> MEM_B_DM<5> MEM_B_DM<6> MEM_B_DM<7>
MEM_B_DQS_P<0> MEM_B_DQS_N<0> MEM_B_DQS_P<1> MEM_B_DQS_N<1> MEM_B_DQS_P<2> MEM_B_DQS_N<2> MEM_B_DQS_P<3> MEM_B_DQS_N<3> MEM_B_DQS_P<4> MEM_B_DQS_N<4> MEM_B_DQS_P<5> MEM_B_DQS_N<5> MEM_B_DQS_P<6> MEM_B_DQS_N<6> MEM_B_DQS_P<7> MEM_B_DQS_N<7>
MCP_MEM_COMP_VDD MCP_MEM_COMP_GND
3
14 26
14 26
14 26
14 26
14 26
14 26
14 26
14 26
14 26
14 26
14 26
14 26
14 26
14 26
14 26
14 26
14 26
14 26
14 26
14 26
14 26
14 26
14 26
14 26
14 26
14 26
14 26
14 26
14 26
14 26
14 26
14 26
14 26
14 26
14 26
14 26
14 26
14 26
14 26
14 26
14 26
14 26
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
15
15
Memory Constraints
SYNC_MASTER=T18_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
APPLE INC.
SCALE
DRAWING NUMBER
D
NONE
SYNC_DATE=02/05/2009
051-7903
SHT
D
C
B
A
REV.
A
OF
8376
8
7 6
5
4
3
2
1
8 7
PCI-Express
LAYER
PCIE_90D
SPACING_RULE_SET
LAYER
PCIE
CLK_PCIE
MCP_PEX_COMP
D
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.4
Analog Video Signal Constraints
LAYER
CRT_50S
SPACING_RULE_SET
LAYER
CRT CRT_2CRT CRT_2CLK
CRT_2SWITCHER
CRT_SYNC
MCP_DAC_COMP
CRT signal single-ended impedence varies by location:
- 37.5-ohm from MCP to first termination resistor.
- 50-ohm from first to second termination resistor.
- 75-ohm from output of three-pole filter to connector (if possible). R/G/B signals should be matched as close as possible and < 10 inches. SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.1 & 2.5.2.
Digital Video Signal Constraints
C
LAYER
DP_100D
LVDS_100D
MCP_DV_COMP
SPACING_RULE_SET
LAYER
DISPLAYPORT
LVDS
LVDS intra-pair matching should be 5 mils. Pairs should be within 100 mils of clock length. DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps. DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals. Max length of LVDS/DisplayPort/TMDS traces: 12 inches. SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4.
SATA Interface Constraints
LAYER
SATA_100D
SPACING_RULE_SET
B
SATA
SATA_TERMP 8 MIL
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1.
LAYER
ALLOW ROUTE ON LAYER?
=90_OHM_DIFF
* =90_OHM_DIFF=90_OHM_DIFF *
=100_OHM_DIFF
LINE-TO-LINE SPACING
*
=3X_DIELECTRIC * *
ALLOW ROUTE ON LAYER?
LINE-TO-LINE SPACING
*
=4:1_SPACING * * * * *
* *
=2:1_SPACING
ALLOW ROUTE ON LAYER?
=100_OHM_DIFF
=100_OHM_DIFF
*
LINE-TO-LINE SPACING
=3x_DIELECTRIC
* *
=3x_DIELECTRIC
ALLOW ROUTE ON LAYER?
=100_OHM_DIFF
LINE-TO-LINE SPACING
=4x_DIELECTRIC
* *
20 MIL
8 MIL
=STANDARD
50 MIL
250 MIL
16 MIL
Y
MINIMUM LINE WIDTH
=90_OHM_DIFF
=100_OHM_DIFF
TABLE_SPACING_RULE_HEAD
WEIGHT
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
MINIMUM LINE WIDTH
=50_OHM_SE
TABLE_SPACING_RULE_HEAD
WEIGHT
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
MINIMUM LINE WIDTH
=100_OHM_DIFF
20 MIL 20 MIL
TABLE_SPACING_RULE_HEAD
WEIGHT
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
MINIMUM LINE WIDTH
=100_OHM_DIFF
TABLE_SPACING_RULE_HEAD
WEIGHT
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
=90_OHM_DIFF=90_OHM_DIFF
=100_OHM_DIFF
SPACING_RULE_SET
PCIE
MINIMUM NECK WIDTH
=100_OHM_DIFFCLK_PCIE_100D
LAYER
TOP,BOTTOM
MAXIMUM NECK LENGTH
=50_OHM_SE=50_OHM_SE =50_OHM_SE
NET_SPACING_TYPE1 NET_SPACING_TYPE2
CRTCRT
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
=100_OHM_DIFF=100_OHM_DIFF
=100_OHM_DIFF=100_OHM_DIFF
=100_OHM_DIFF
=STANDARD
SPACING_RULE_SET
DISPLAYPORT
LVDS
MINIMUM NECK WIDTH
=100_OHM_DIFF
SPACING_RULE_SET
SATA
LAYER
TOP,BOTTOM TOP,BOTTOM
MAXIMUM NECK LENGTH
=100_OHM_DIFF
LAYER
TOP,BOTTOM
DIFFPAIR PRIMARY GAP
LINE-TO-LINE SPACING
=4X_DIELECTRIC
DIFFPAIR PRIMARY GAP
AREA_TYPE
*
DIFFPAIR PRIMARY GAP
=100_OHM_DIFF =100_OHM_DIFF
=STANDARD =STANDARD
LINE-TO-LINE SPACING
=4x_DIELECTRIC =4x_DIELECTRIC
DIFFPAIR PRIMARY GAP
=100_OHM_DIFF*=100_OHM_DIFF
LINE-TO-LINE SPACING
=3x_DIELECTRIC
A
6
WEIGHT
SPACING_RULE_SET
CRT_2CRT
WEIGHT
WEIGHT
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
=100_OHM_DIFF=100_OHM_DIFF
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
=STANDARD* =STANDARD
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
=100_OHM_DIFF =100_OHM_DIFF
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
5
ELECTRICAL_CONSTRAINT_SET
PEG_R2D
PEG_D2R
PCIE_MINI_R2D
PCIE_MINI_D2R
PCIE_FW_R2D
PCIE_FW_D2R
PCIE_EXCARD_R2D
PCIE_EXCARD_D2R
MCP_PE0_REFCLK
MCP_PE1_REFCLK
MCP_PE2_REFCLK
MCP_PE3_REFCLK
MCP_PEX_CLK_COMP
CRT_RED CRT_GREEN CRT_BLUE CRT_SYNC CRT_SYNC MCP_DAC_RSET MCP_DAC_COMP MCP_DAC_VREF MCP_DAC_COMP
TMDS_IG_TXC TMDS_IG_TXC DISPLAYPORT TMDS_IG_TXD TMDS_IG_TXD
DP_ML DP_ML DP_AUX_CH DP_AUX_CH
MCP_HDMI_RSET MCP_HDMI_VPROBE
LVDS_IG_A_CLK LVDS_IG_A_CLK LVDS_IG_A_DATA LVDS_IG_A_DATA LVDS_IG_A_DATA3 LVDS_IG_A_DATA3 LVDS_IG_B_CLK LVDS_IG_B_CLK LVDS_IG_B_DATA LVDS_IG_B_DATA LVDS_IG_B_DATA3 LVDS_IG_B_DATA3
MCP_IFPAB_RSET MCP_IFPAB_VPROBE
SATA_HDD_R2D
SATA_HDD_D2R
SATA_ODD_R2D
SATA_ODD_D2R
MCP_SATA_TERMP
4
PCIE_90D
PCIE_90D PCIE_90D PCIE_90D
PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE_90D PCIE_90D
CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D
CRT_50S CRT_50S CRT_50S CRT_50S CRT_50S
DP_100D DP_100D DP_100D DP_100D
DP_100D DP_100D DP_100D DP_100D
MCP_DV_COMP MCP_DV_COMP
LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D
MCP_DV_COMP
SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D
PHYSICAL
NET_TYPE
SPACING
PCIEPCIE_90D PCIEPCIE_90D PCIE PCIEPCIE_90D PCIEPCIE_90D PCIEPCIE_90D PCIEPCIE_90D PCIEPCIE_90D
PCIEPCIE_90D PCIEPCIE_90D PCIE PCIE PCIE PCIEPCIE_90D
PCIEPCIE_90D PCIEPCIE_90D PCIEPCIE_90D PCIEPCIE_90D PCIEPCIE_90D PCIEPCIE_90D PCIEPCIE_90D PCIEPCIE_90D
PCIEPCIE_90D
PCIE PCIE PCIE
CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE MCP_PEX_COMP
CRT CRT CRT CRT_SYNC CRT_SYNC
DISPLAYPORT
DISPLAYPORT DISPLAYPORT
DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT
LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS
SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA
SATA_TERMP
PEG_R2D_P<15..0> PEG_R2D_N<15..0> PEG_R2D_C_P<15..0> PEG_R2D_C_N<15..0> PEG_D2R_P<15..0> PEG_D2R_N<15..0> PEG_D2R_C_P<15..0> PEG_D2R_C_N<15..0>
PCIE_MINI_R2D_P PCIE_MINI_R2D_N PCIE_MINI_R2D_C_P PCIE_MINI_R2D_C_N PCIE_MINI_D2R_P PCIE_MINI_D2R_N
PCIE_FW_R2D_P PCIE_FW_R2D_N PCIE_FW_R2D_C_P PCIE_FW_R2D_C_N PCIE_FW_D2R_P PCIE_FW_D2R_N PCIE_FW_D2R_C_P PCIE_FW_D2R_C_N
PCIE_EXCARD_R2D_P PCIE_EXCARD_R2D_N NC_PCIE_EXCARD_R2DCP NC_PCIE_EXCARD_R2DCN NC_PCIE_EXCARD_D2RP NC_PCIE_EXCARD_D2RN
NC_PEG_CLK100MP NC_PEG_CLK100MN PCIE_CLK100M_MINI_P PCIE_CLK100M_MINI_N PCIE_CLK100M_FW_P PCIE_CLK100M_FW_N NC_PCIE_CLK100M_EXCARDP NC_PCIE_CLK100M_EXCARDN MCP_PEX_CLK_COMP
NC_CRT_IG_R_C_PR NC_CRT_IG_G_Y_Y NC_CRT_IG_B_COMP_PB NC_CRT_IG_HSYNC NC_CRT_IG_VSYNC NC_MCP_TV_DAC_RSET NC_MCP_TV_DAC_VREF
TMDS_IG_TXC_P TMDS_IG_TXC_N TMDS_IG_TXD_P<2..0> TMDS_IG_TXD_N<2..0>
DP_IG_ML_P<3..0> DP_IG_ML_N<3..0> DP_IG_AUX_CH_P DP_IG_AUX_CH_N
MCP_HDMI_RSET MCP_HDMI_VPROBE
LVDS_CONN_A_CLK_P LVDS_CONN_A_CLK_N LVDS_IG_A_DATA_P<2..0> LVDS_IG_A_DATA_N<2..0> NC_LVDS_IG_A_DATAP<3> NC_LVDS_IG_A_DATAN<3> LVDS_CONN_B_CLK_P LVDS_CONN_B_CLK_N LVDS_IG_B_DATA_P<2..0> LVDS_IG_B_DATA_N<2..0> NC_LVDS_IG_B_DATAP<3> NC_LVDS_IG_B_DATAN<3>
MCP_IFPAB_RSET MCP_IFPAB_VPROBE
SATA_HDD_R2D_C_P SATA_HDD_R2D_C_N SATA_HDD_R2D_P SATA_HDD_R2D_N SATA_HDD_D2R_P SATA_HDD_D2R_N SATA_HDD_D2R_C_P SATA_HDD_D2R_C_N SATA_ODD_R2D_C_P SATA_ODD_R2D_C_N SATA_ODD_R2D_P SATA_ODD_R2D_N SATA_ODD_D2R_P SATA_ODD_D2R_N SATA_ODD_D2R_C_P SATA_ODD_D2R_C_N
MCP_SATA_TERMP
3
6
29 82
6
29 82
16 29
16 29
6
16 29
6
16 29
34
34
16 34
16 34
16 34
16 34
34
34
8
16
8
16
8
16
8
16
8
16
8
16
16 29
16 29
16 34
16 34
8
16
8
16
16
17 23
17 23
17 23
17 23
17 23
17 23
17 23
17 70
17 70
17 23
17 23
8
17 69
8
17 69
8
17
8
17
8
17
8
17
8
17 69
8
17 69
8
17
8
17
8
17
8
17
17 23
17 23
19 37
19 37
6
37
6
37
19 37
19 37
6
37
6
37
19 37
19 37
6
37
6
37
19 37
19 37
6
37
6
37
19
MCP Constraints 1
SYNC_MASTER=T18_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
APPLE INC.
SCALE
DRAWING NUMBER
D
NONE
SYNC_DATE=02/05/2009
051-7903
SHT
D
C
B
A
REV.
A
OF
8377
8
7 6
5
4
3
2
1
8 7
PCI Bus Constraints
LAYER
PCI_55S
CLK_PCI_55S
SPACING_RULE_SET
LAYER
PCI
CLK_PCI
D
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.8.
LPC Bus Constraints
LAYER
LPC_55S
CLK_LPC_55S
SPACING_RULE_SET
LAYER
LPC
CLK_LPC
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.9.1.
USB 2.0 Interface Constraints
LAYER
MCP_USB_RBIAS
USB_90D
SPACING_RULE_SET
LAYER
USB
C
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.10.1.
SMBus Interface Constraints
LAYER
SMB_55S
SPACING_RULE_SET
LAYER
SMB
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.11.1.
HD Audio Interface Constraints
LAYER
HDA_55S
SPACING_RULE_SET
LAYER
HDA
MCP_HDA_COMP
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.12.1.
SIO Signal Constraints
B
LAYER
CLK_SLOW_55S
SPACING_RULE_SET
LAYER
CLK_SLOW
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.13.
SPI Interface Constraints
LAYER
SPI_55S
SPACING_RULE_SET
SPI
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.14.
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
=55_OHM_SE
8 MIL
=55_OHM_SE
WEIGHT
MINIMUM LINE WIDTH
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
*
=55_OHM_SE =55_OHM_SE =55_OHM_SE
LINE-TO-LINE SPACING
*
=STANDARD
*
ALLOW ROUTE ON LAYER?
* =STANDARD *
LINE-TO-LINE SPACING
* *
* =STANDARD=STANDARD
6 MIL 8 MIL
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
=STANDARD =STANDARD
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
* =90_OHM_DIFF =90_OHM_DIFF=90_OHM_DIFF
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
*
LINE-TO-LINE SPACING
=2x_DIELECTRIC
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
=55_OHM_SE
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
*
LINE-TO-LINE SPACING
=2x_DIELECTRIC
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
=55_OHM_SE =55_OHM_SE=55_OHM_SE=55_OHM_SE
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
* *
LINE-TO-LINE SPACING
=2x_DIELECTRIC
8 MIL
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
*
LINE-TO-LINE SPACING
*
* =STANDARD =STANDARD
*
8 MIL
ALLOW ROUTE ON LAYER?
LINE-TO-LINE SPACING
MINIMUM LINE WIDTH
8 MIL
=55_OHM_SE
WEIGHT
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
A
MINIMUM NECK WIDTH
MINIMUM NECK WIDTH
=55_OHM_SE=55_OHM_SE=55_OHM_SE
MINIMUM NECK WIDTH
8 MIL8 MIL
=90_OHM_DIFF
SPACING_RULE_SET
USB
MINIMUM NECK WIDTH
MINIMUM NECK WIDTH
MINIMUM NECK WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
=55_OHM_SE=55_OHM_SE=55_OHM_SE
MAXIMUM NECK LENGTH
=55_OHM_SE =55_OHM_SE=55_OHM_SE=55_OHM_SE=55_OHM_SE
MAXIMUM NECK LENGTH
=90_OHM_DIFF=90_OHM_DIFF
LAYER
TOP,BOTTOM
MAXIMUM NECK LENGTH
=55_OHM_SE=55_OHM_SE=55_OHM_SE
MAXIMUM NECK LENGTH
MAXIMUM NECK LENGTH
=55_OHM_SE=55_OHM_SE=55_OHM_SE=55_OHM_SE
MAXIMUM NECK LENGTH
=55_OHM_SE=55_OHM_SE=55_OHM_SE
6
DIFFPAIR PRIMARY GAP
=STANDARD* =STANDARD =STANDARD
DIFFPAIR PRIMARY GAP
DIFFPAIR PRIMARY GAP
LINE-TO-LINE SPACING
=4x_DIELECTRIC
DIFFPAIR PRIMARY GAP
DIFFPAIR PRIMARY GAP
=STANDARD =STANDARD*
DIFFPAIR PRIMARY GAP
DIFFPAIR PRIMARY GAP
WEIGHT
?
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
=STANDARD
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
=STANDARD =STANDARD=STANDARD
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
=STANDARD=STANDARD*
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
=STANDARD=STANDARD
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
5
ELECTRICAL_CONSTRAINT_SET
MCP_DEBUG PCI_AD PCI_AD24 PCI_AD PCI_AD PCI_C_BE_L PCI_CNTL PCI_CNTL PCI_CNTL PCI_CNTL PCI_CNTL PCI_CNTL PCI_CNTL PCI_REQ0_L PCI_GNT0_L PCI_REQ1_L PCI_GNT1_L PCI_INTW_L PCI_INTX_L PCI_INTY_L PCI_INTZ_L
MCP_PCI_CLK2
LPC_AD LPC_FRAME_L LPC_RESET_L
MCP_LPC_CLK0
USB_EXTA
USB_MINI
USB_EXTD
USB_CAMERA
USB_BT
USB_TPAD
USB_IR
USB_EXTB
USB_EXCARD
USB_EXTC
USB_CARDREADER
SMBUS_MCP_0_CLK SMBUS_MCP_0_DATA SMBUS_MCP_1_CLK SMBUS_MCP_1_DATA
HDA_BIT_CLK
HDA_SYNC
HDA_RST_L
HDA_SDIN0
HDA_SDOUT
MCP_HDA_PULLDN_COMP
MCP_SUS_CLK
SPI_CLK SPI_55S
SPI_MOSI
SPI_MISO
4
PHYSICAL
PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S
CLK_PCI_55S CLK_PCI_55S
LPC_55S LPC_55S LPC_55S
CLK_LPC_55S CLK_LPC_55S CLK_LPC_55S
USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D
MCP_USB_RBIASMCP_USB_RBIAS
SMB_55S SMB_55S SMB_55S SMB_55S
HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S
CLK_SLOW_55S CLK_SLOW
SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55SSPI_CS0 SPI_55S
NET_TYPE
SPACING
PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI
CLK_PCI CLK_PCI
LPC LPC LPC
CLK_LPC CLK_LPC CLK_LPC
USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB
SMB SMB SMB SMB
HDA HDA HDA HDA HDA HDA HDA HDA HDA HDA
MCP_HDA_COMP
CLK_SLOWCLK_SLOW_55S
SPI SPI SPI SPI SPI SPI SPI SPI
MCP_DEBUG<7..0> PCI_AD<23..8> PCI_AD<24> PCI_AD<31..25> PCI_PAR PCI_C_BE_L<3..0> PCI_IRDY_L PCI_DEVSEL_L PCI_PERR_L PCI_SERR_L PCI_STOP_L PCI_TRDY_L PCI_FRAME_L PCI_REQ0_L PCI_GNT0_L PCI_REQ1_L PCI_GNT1_L PCI_INTW_L PCI_INTX_L PCI_INTY_L PCI_INTZ_L
PCI_CLK33M_MCP_R PCI_CLK33M_MCP
LPC_AD<3..0> LPC_FRAME_L LPC_RESET_L
LPC_CLK33M_SMC_R LPC_CLK33M_SMC LPC_CLK33M_LPCPLUS
USB_EXTA_P USB_EXTA_N USB_EXTA_MUXED_P USB_EXTA_MUXED_N NC_USB_MINIP NC_USB_MININ NC_USB_EXTDP NC_USB_EXTDN USB_CAMERA_P USB_CAMERA_N USB_BT_P USB_BT_N USB_TPAD_P USB_TPAD_N USB_IR_P USB_IR_N USB_EXTB_P USB_EXTB_N NC_USB_EXCARDP NC_USB_EXCARDN NC_USB_EXTCP NC_USB_EXTCN USB_CARDREADER_P USB_CARDREADER_N
MCP_USB_RBIAS_GND SMBUS_MCP_0_CLK
SMBUS_MCP_0_DATA SMBUS_MCP_1_CLK SMBUS_MCP_1_DATA
HDA_BIT_CLK HDA_BIT_CLK_R HDA_SYNC HDA_SYNC_R HDA_RST_R_L HDA_RST_L HDA_SDIN0 HDA_SDIN_CODEC HDA_SDOUT HDA_SDOUT_R
MCP_HDA_PULLDN_COMP PM_CLK32K_SUSCLK_R
PM_CLK32K_SUSCLK SPI_CLK_R
SPI_CLK SPI_MOSI_R SPI_MOSI SPI_MISO SPI_MISO_R SPI_CS0_R_L SPI_CS0_L
3
12 18
18
18
18
18
18 40 42
18 40 42
18 24
18 24
24 40
24 42
19 38
19 38
8
19
8
19
8
19
8
19
6
19 29
6
19 29
6
19 29
6
19 29
19 48
19 48
19 39
19 39
19 38
19 38
8
19
8
19
8
19
8
19
19 30
19 30
19
12 20 26 27 43
12 20 26 43
20 43 58 72
20 43 58 72
20 53
20
20 53
20
20
20 53
20 53
20 53
20
20
20 24
24 40
20 42
52
20 42
52
20 42
52
20 42
D
C
B
MCP Constraints 2
SYNC_MASTER=T18_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
APPLE INC.
SCALE
DRAWING NUMBER
D
NONE
SYNC_DATE=02/05/2009
051-7903
SHT
OF
78 83
A
REV.
A
8
7 6
5
4
3
2
1
8 7
MCP RGMII (Ethernet) Constraints
LAYER
MCP_MII_COMP ENET_MII_55S
SPACING_RULE_SET
MCP_BUF0_CLK
ENET_MII
D
SOURCE: MCP73 Interface DG (DG-02974-001_v01), Sections 2.7.2 & 2.7.4
LAYER
88E1116R (Ethernet PHY) Constraints
LAYER
ENET_MDI_100D
SPACING_RULE_SET
ENET_MDI
SOURCE: MCP73 Interface DG (DG-02974-001_v01), Section 2.7.4
LAYER
* *
*
*
ALLOW ROUTE ON LAYER?
=STANDARD*
=55_OHM_SE
LINE-TO-LINE SPACING
=3:1_SPACING
12 MIL
ALLOW ROUTE ON LAYER?
=100_OHM_DIFF
LINE-TO-LINE SPACING
25 MIL
MINIMUM LINE WIDTH
7.5 MIL
WEIGHT
MINIMUM LINE WIDTH
=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
MINIMUM NECK WIDTH
7.5 MIL
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
=STANDARD
=55_OHM_SE=55_OHM_SE=55_OHM_SE
MAXIMUM NECK LENGTH
6
DIFFPAIR PRIMARY GAP
=STANDARD =STANDARD =STANDARD =STANDARD*
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
=100_OHM_DIFF=100_OHM_DIFF
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
5
ELECTRICAL_CONSTRAINT_SET
MCP_MII_COMP MCP_MII_COMP
MCP_CLK25M_BUF0
ENET_INTR_L ENET_MDIO ENET_MDC ENET_MIIENET_MII_55S ENET_PWRDWN_L
ENET_RXCLK
ENET_RXD ENET_RXD_STRAP ENET_RXD
ENET_TXCLK ENET_TXD0
ENET_TXD
ENET_MDI
4
PHYSICAL
MCP_MII_COMP MCP_MII_COMP
ENET_MII_55S ENET_MII_55S
ENET_MII_55S ENET_MII
ENET_MII_55S ENET_MII ENET_MII_55S ENET_MII ENET_MII_55S ENET_MII ENET_MII_55S ENET_MII ENET_MII_55S ENET_MII
ENET_MII_55S ENET_MII ENET_MII_55S ENET_MII
ENET_MII_55S ENET_MII
ENET_MDI_100D ENET_MDI_100D
NET_TYPE
SPACING
MCP_BUF0_CLKENET_MII_55S MCP_BUF0_CLKENET_MII_55S
ENET_MII ENET_MII
ENET_MIIENET_MII_55S
ENET_MIIENET_MII_55SENET_TXD
ENET_MIIENET_MII_55S
ENET_MDI ENET_MDI
MCP_MII_COMP_VDD MCP_MII_COMP_GND
MCP_CLK25M_BUF0_R RTL8211_CLK25M_CKXTAL1
ENET_INTR_L ENET_MDIO ENET_MDC ENET_PWRDWN_L
ENET_CLK125M_RXCLK_R ENET_CLK125M_RXCLK ENET_RXD_R<3..0> ENET_RXD<0> ENET_RXD<3..1> ENET_RX_CTRL
ENET_CLK125M_TXCLK ENET_TXD<0> ENET_TXD<3..1> ENET_TX_CTRL
ENET_RESET_L ENET_MDI_P<3..0>
ENET_MDI_N<3..0>
3
17
17
17 32
31 32
17 31
17 31
31
17 31
31
17 31
17 31
17 31
17 31
17 31
17 31
17 31
17 31
31 33
31 33
D
C
B
C
B
Ethernet Constraints
A
SYNC_MASTER=T18_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
D
APPLE INC.
8
7 6
5
4
3
2
SCALE
NONE
SYNC_DATE=02/05/2009
051-7903
SHT
OF
79 83
1
A
REV.
A
8 7
FireWire Interface Constraints
LAYER
FW_110D
SPACING_RULE_SET
FW_TP
LAYER
*
*
ALLOW ROUTE ON LAYER?
=110_OHM_DIFF
LINE-TO-LINE SPACING
=3:1_SPACING
MINIMUM LINE WIDTH
WEIGHT
?
D
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
MINIMUM NECK WIDTH
=110_OHM_DIFF=110_OHM_DIFF
MAXIMUM NECK LENGTH
=110_OHM_DIFF
6
DIFFPAIR PRIMARY GAP
5
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
=110_OHM_DIFF=110_OHM_DIFF
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
FireWire Net Properties
ELECTRICAL_CONSTRAINT_SET
FW_P0_TPA FW_P0_TPA FW_P0_TPB FW_P0_TPB FW_P1_TPA FW_P1_TPA FW_P1_TPB FW_P1_TPB
4
NET_TYPE
PHYSICAL
FW_110D FW_110D FW_110D FW_110D FW_110D FW_110D FW_110D FW_110D
SPACING
FW_TP FW_TP FW_TP FW_TP FW_TP FW_TP FW_TP FW_TP
NC_FW0_TPAP NC_FW0_TPAN NC_FW0_TPBP NC_FW0_TPBN FW_PORT1_TPA_P FW_PORT1_TPA_N FW_PORT1_TPB_P FW_PORT1_TPB_N
3
34 36
34 36
34 36
34 36
34 36
34 36
34 36
34 36
D
Port 2 Not Used
C
B
C
B
FireWire Constraints
A
SYNC_MASTER=T18_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
D
APPLE INC.
8
7 6
5
4
3
2
SCALE
NONE
SYNC_DATE=02/05/2009
051-7903
SHT
OF
1
A
REV.
A
8380
D
1TO1_DIFFPAIR
8 7
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
=STANDARD=STANDARD
MINIMUM NECK WIDTH
=STANDARD =STANDARD
MAXIMUM NECK LENGTH
6
DIFFPAIR PRIMARY GAP
0.1 MM 0.1 MM*
5
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
SMC SMBus Net Properties
ELECTRICAL_CONSTRAINT_SET
SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA
4
NET_TYPE
PHYSICAL
SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S
SPACING
SMB SMB SMB SMB SMB SMB SMB SMB SMB SMB
SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA
3
6
29 40 43 49
6
29 40 43 49
40 43 46
40 43 46
40 43 46 51
40 43 46 51
6
40 43 59 60
6
40 43 59 60
25 37 40 43
25 37 40 43
D
SMBus Charger Net Properties
ELECTRICAL_CONSTRAINT_SET
CHGR_CSI
CHGR_CSO
1TO1_DIFFPAIR 1TO1_DIFFPAIR
1TO1_DIFFPAIR 1TO1_DIFFPAIR
C
PHYSICAL
NET_TYPE
SPACING
CHGR_CSI_P CHGR_CSI_N
CHGR_CSO_P CHGR_CSO_N
60
60
60
60
C
B
B
SMC Constraints
A
SYNC_MASTER=T18_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
D
APPLE INC.
8
7 6
5
4
3
2
SCALE
NONE
SYNC_DATE=02/05/2009
051-7903
SHT
OF
1
A
REV.
A
8381
8 7
6
5
4
3
SENSE_1TO1_55S
THERM_1TO1_55S
DIFFPAIR
SPACING_RULE_SET
D
C
SENSE
THERM
AUDIO
SPACING_RULE_SET
ENETCONN
SPACING_RULE_SET
SPACING_RULE_SET
GND_P2MM
PWR_P2MM
NET_SPACING_TYPE1 NET_SPACING_TYPE2
MEM_CLK
MEM_CMD
MEM_CTRL
MEM_DATA
MEM_DQS
NET_SPACING_TYPE1 NET_SPACING_TYPE2
CLK_PCIE
PCIE
SATA
CLK_PCIE SB_POWER
SATA
USB
NET_SPACING_TYPE1 NET_SPACING_TYPE2
LVDS
LAYER
LAYER
LAYER
LAYER
LAYER
ALLOW ROUTE ON LAYER?
*
=1:1_DIFFPAIR
=1:1_DIFFPAIR
*
*
=1:1_DIFFPAIR =1:1_DIFFPAIR
LINE-TO-LINE SPACING
* ?
*
*
LINE-TO-LINE SPACING
* ?
LINE-TO-LINE SPACING
* ?
LINE-TO-LINE SPACING
*
*
GND
GND
GND
GND
GND
GND
GND
GND
GNDUSB
SB_POWER
SB_POWER
GND
=2:1_SPACING
=2:1_SPACING
=2:1_SPACING
25 MILS
=STANDARDGND
=STANDARDPP1V8_MEM
0.20 MM
0.20 MM
AREA_TYPE
*
*
*
*
*
AREA_TYPE
*
*
*
*
*
*
*
AREA_TYPE
*
MINIMUM LINE WIDTH
=55_OHM_SE
=55_OHM_SE =55_OHM_SE
TABLE_SPACING_RULE_HEAD
WEIGHT
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_HEAD
WEIGHT
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_HEAD
WEIGHT
TABLE_SPACING_RULE_ITEM
?*
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_HEAD
WEIGHT
TABLE_SPACING_RULE_ITEM
1000
TABLE_SPACING_RULE_ITEM
1000
GND_P2MM
GND_P2MM
GND_P2MM
GND_P2MM
GND_P2MM
GND_P2MM
GND_P2MM
GND_P2MM
GND_P2MM
PWR_P2MM
PWR_P2MM
PWR_P2MM
GND_P2MM
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
SPACING_RULE_SET
SPACING_RULE_SET
SPACING_RULE_SET
Memory Constraint Relaxations
Allow 0.127 mm necks for >0.127 mm lines for GMCH fanout.
LAYER
B
MEM_70D
BOTTOM
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
=55_OHM_SE
NET_SPACING_TYPE1 NET_SPACING_TYPE2
CPU_GTLREF
CPU_VCCSENSE
NET_SPACING_TYPE1 NET_SPACING_TYPE2
MINIMUM NECK WIDTH
0.127 MM
MAXIMUM NECK LENGTH
=55_OHM_SE
=55_OHM_SE
CLK_FSB
CPU_COMP
FSB_DSTB
MAXIMUM NECK LENGTH
6.35 MM
GND
GND
GND
GND
GND
DIFFPAIR PRIMARY GAP
=1:1_DIFFPAIR
=1:1_DIFFPAIR =1:1_DIFFPAIR
=1:1_DIFFPAIR
AREA_TYPE
*
*
*
*
*
AREA_TYPE
*
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
=1:1_DIFFPAIR
=1:1_DIFFPAIR
SPACING_RULE_SET
GND_P2MM
GND_P2MM
GND_P2MM
GND_P2MM
GND_P2MMFSB_DSTB
SPACING_RULE_SET
GND_P2MMENET_MDI
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
K19i Specific Net Properties
ELECTRICAL_CONSTRAINT_SET
ENET_MDI_100D ENET_MDI_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D
CPUTHMSNS_D2
CPU_THERMD
MCPTHMSNS_D2
MCP_THMDIODE
SENSE_DIFFPAIR SENSE_1TO1_55S
SENSE_DIFFPAIR SENSE_1TO1_55S
SENSE_DIFFPAIR SENSE_1TO1_55S
SENSE_DIFFPAIR SENSE_1TO1_55S
SENSE_DIFFPAIR SENSE_1TO1_55S
SENSE_DIFFPAIR SENSE_1TO1_55S
SENSE_DIFFPAIR
THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S
SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S
SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S
SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S
SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S
SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S
SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S
SD Card Net Properties
ELECTRICAL_CONSTRAINT_SET
SD_DATA SD_DATA SD_DATA SD_DATA SD_DATA SD_DATA SD_DATA SD_DATA
SD_CLK SD_CMD
SD_55S SD_55S SD_55S SD_55S SD_55S SD_55S SD_55S SD_55S
SD_55S SD_55S
PHYSICAL
PHYSICAL
NET_TYPE
NET_TYPE
SD_INTERFACE SD_INTERFACE SD_INTERFACE SD_INTERFACE SD_INTERFACE SD_INTERFACE SD_INTERFACE SD_INTERFACE
SD_INTERFACE SD_INTERFACE
SPACING
ENETCONN ENETCONN SATA SATA SATA SATA SATA SATA SATA SATA
THERM THERM THERM THERM THERM THERM THERM THERM SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE
SB_POWER SB_POWER SB_POWER GND
SPACING
ENETCONN_P<3..0>
ENETCONN_N<3..0> SATA_ODD_R2D_UF_P SATA_ODD_R2D_UF_N SATA_ODD_D2R_UF_P SATA_ODD_D2R_UF_N SATA_HDD_D2R_UF_P SATA_HDD_D2R_UF_N SATA_HDD_R2D_UF_P
SATA_HDD_R2D_UF_N
CPUTHMSNS_D2_P
CPUTHMSNS_D2_N
CPU_THERMD_P
CPU_THERMD_N
MCPTHMSNS_D2_P
MCPTHMSNS_D2_N
MCP_THMDIODE_P
MCP_THMDIODE_N ISNS_1V5_S3_P ISNS_1V5_S3_N ISNS_1V5_S3_R_P ISNS_1V5_S3_R_N ISNS_AIRPORT_P ISNS_AIRPORT_N ISNS_AIRPORT_R_P ISNS_AIRPORT_R_N ISNS_HDD_P ISNS_HDD_N ISNS_HDD_R_P ISNS_HDD_R_N ISNS_LCDBKLT_P ISNS_LCDBKLT_N ISNS_LCDBKLT_R_P ISNS_LCDBKLT_R_N ISNS_ODD_P ISNS_ODD_N ISNS_ODD_R_P ISNS_ODD_R_N ISNS_CPUVTT_P ISNS_CPUVTT_N
MCPCORES0_RSEN_P
MCPCORES0_RSEN_N
PP3V3_S5
PP3V3_S0
PP1V5_S0 GND
SD_D<0>
SD_D<1>
SD_D<2>
SD_D<3>
SD_D<4>
SD_D<5>
SD_D<6>
SD_D<7>
SD_CLK
SD_CMD
33
33
37
37
6
37
6
37
37
37
37
37
46
46
9
46
9
46
46
46
20 46
20 46
51 63
51 63
51
51
29 51
29 51
51
51
37 51
37 51
51
51
51 72
51 72
37 51
37 51
51
51
45
45
64
64
68 69 71 6 7
17 19 21 22 24 28
32 35 36 42 52 62 66 67 6 7
12 17 18 20 21 22
23 26 27 35 37 41 43 45 6 7
10 11 15 22 37 66
67 68
6
30
6
30
6
30
6
30
6
30
6
30
6
30
6
30
6
30
6
30
K19i Specific Net Properties
ELECTRICAL_CONSTRAINT_SET
PCIE_90D (PCIE_MINI) (PCIE_MINI)
(USB_EXTA) (USB_EXTA) (USB_EXTA) (USB_EXTA) (USB_TPAD) (USB_TPAD) (USB_CAMERA) (USB_CAMERA)
SPK_OUT
SPK_OUT
SPK_OUT
PCIE_90D
CLK_PCIE_100D
CLK_PCIE_100D
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
DP_100D
DP_100D
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
K19i Specific Graphics Net Properties
ELECTRICAL_CONSTRAINT_SET
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
DP_ML
46 47
49 53
DP_ML
57 58 61 66 67
DP_ML
68 69 71 72
DP_AUX_CH DP_AUX_CH
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
PHYSICAL
PHYSICAL
NET_TYPE
NET_TYPE
DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT
SPACING
PCIE PCIE CLK_PCIE CLK_PCIE
USB USB USB USB USB USB USB USB USB USB USB USB DISPLAYPORT DISPLAYPORT AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO
SPACING
LVDS LVDS LVDS LVDS
PCIE_MINI_R2D_P
PCIE_MINI_R2D_N PCIE_CLK100M_MINI_CONN_P PCIE_CLK100M_MINI_CONN_N
CHGR_CSI_R_P
CHGR_CSI_R_N
CHGR_CSO_R_P
CHGR_CSO_R_N
USB2_EXTA_MUXED_P
USB2_EXTA_MUXED_N USB2_LT1_P USB2_LT1_N USB_TPAD_R_P USB_TPAD_R_N USB_CAMERA_CONN_P USB_CAMERA_CONN_N CONN_USB2_BT_P CONN_USB2_BT_N USB_LT2_P USB_LT2_N DP_AUX_CH_SW_P DP_AUX_CH_SW_N
SPKRCONN_L_OUT_P
SPKRCONN_L_OUT_N
SPKRCONN_S_OUT_P
SPKRCONN_S_OUT_N
SPKRCONN_R_OUT_P
SPKRCONN_R_OUT_N
SPKRAMP_L_OUT_P
SPKRAMP_L_OUT_N
SPKRAMP_R_OUT_P
SPKRAMP_R_OUT_N
SPKRAMP_S_OUT_P
SPKRAMP_S_OUT_N
LVDS_CONN_A_CLK_F_P
LVDS_CONN_A_CLK_F_N
LVDS_CONN_B_CLK_F_P
LVDS_CONN_B_CLK_F_N
DP_ML_C_P<3..0>
DP_ML_C_N<3..0>
DP_ML_P<3..0>DP_ML_P<3..0>
DP_ML_N<3..0>DP_ML_N<3..0>
DP_ML_CONN_P<3..0>
DP_ML_CONN_N<3..0>
DP_AUX_CH_C_P
DP_AUX_CH_C_N
6
29 77
6
29 77
6
29
6
29
60
60
45 60
45 60
38
38
38
38
48
48
6
29
6
29
6
29
6
29
38
38
70
70
6
56 57
6
56 57
6
56 57
6
56 57
6
56 57
6
56 57
56
56
56
56
56
56
6
69
6
69
6
69
6
69
6
71
71
17 70 71
17 70 71
71
71
70 71
70 71
D
C
B
MCP Fanout Constraint Relaxations
TOP
TOP
TOP
TOP
ALLOW ROUTE ON LAYER?
*
*
*
*
*
*
LAYER
MEM_40S
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
MEM_40S_VDD
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
MEM_70D
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
MEM_70D_VDD
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
PCIE_90D
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
USB_90D 0.09 MM
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
MCP_DV_COMP
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
MCP_MEM_COMP
A
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
MCP_MII_COMP
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
MCP_USB_RBIAS
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
MCP_DV_COMP
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
8
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
0.09 MM
0.09 MM
0.09 MM
0.09 MM 100 MIL
0.1 MM
0.1 MM
0.1 MM
0.1 MMTOP
0.25 MM
7 6
MAXIMUM NECK LENGTH
5.8 MM
5.8 MM
5.8 MM
100 MIL0.09 MM
500 MIL
500 MIL
500 MIL
500 MIL
500 MIL
250 MIL
DIFFPAIR PRIMARY GAP
SD Card Interface Constraints
*
*
ALLOW ROUTE ON LAYER?
LINE-TO-LINE SPACING
=3X_DIELECTRIC
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
SD_55S
SPACING_RULE_SET
SD_INTERFACE
LAYER
LAYER
5
MINIMUM LINE WIDTH
=55_OHM_SE=55_OHM_SE
WEIGHT
?
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
4
MINIMUM NECK WIDTH
=55_OHM_SE
MAXIMUM NECK LENGTH
=55_OHM_SE
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
=STANDARD =STANDARD
3
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
K19i Specific Constraints
SYNC_MASTER=WFERRY_K19I
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
D
APPLE INC.
SCALE
NONE
2
SYNC_DATE=01/08/2009
051-7903
SHT
OF
82 83
1
A
REV.
A
8 7
K19i Board-Specific Physical & Spacing Constraints
BOARD LAYERS
TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM
ALLOW ROUTE ON LAYER?
* *
Y Y
ALLOW ROUTE ON LAYER?
Y
*
Y
ALLOW ROUTE ON LAYER?
Y
*
Y
ALLOW ROUTE ON LAYER?
Y
*
Y
ALLOW ROUTE ON LAYER?
Y
*
*
Y
ALLOW ROUTE ON LAYER?
N Y Y
ALLOW ROUTE ON LAYER?
*
N Y Y
ALLOW ROUTE ON LAYER?
*
N Y Y
ALLOW ROUTE ON LAYER?
*
N Y Y
ALLOW ROUTE ON LAYER?
*
N Y Y
D
C
B
STANDARD
55_OHM_SE
50_OHM_SE
40_OHM_SE
27P4_OHM_SE 27P4_OHM_SE
70_OHM_DIFF 70_OHM_DIFF 70_OHM_DIFF
90_OHM_DIFF 90_OHM_DIFF 90_OHM_DIFF
100_OHM_DIFF 100_OHM_DIFF 100_OHM_DIFF
100_OHM_DIFF_HDD
100_OHM_DIFF_HDD
100_OHM_DIFF_HDD
110_OHM_DIFF 110_OHM_DIFF 110_OHM_DIFF
LAYER
LAYER
TOP,BOTTOM
LAYER
TOP,BOTTOM
LAYER
TOP,BOTTOM
LAYER
TOP,BOTTOM
LAYER
ISL3,ISL4,ISL9,ISL10
TOP,BOTTOM
LAYER
ISL3,ISL4,ISL9,ISL10
TOP,BOTTOM
LAYER
ISL3,ISL4,ISL9,ISL10
TOP,BOTTOM
LAYER
ISL3,ISL4,ISL9,ISL10
TOP,BOTTOM
LAYER
ISL3,ISL4,ISL9,ISL10
TOP,BOTTOM
MINIMUM LINE WIDTH
=50_OHM_SE
=DEFAULT
MINIMUM LINE WIDTH
0.090 MM
0.076 MM
MINIMUM LINE WIDTH
0.115 MM
0.076 MM
MINIMUM LINE WIDTH
0.165 MM
0.126 MM
MINIMUM LINE WIDTH
0.310 MM
0.222 MM
MINIMUM LINE WIDTH
=STANDARD
0.151 MM
0.185 MM
MINIMUM LINE WIDTH
=STANDARD
0.095 MM
0.112 MM
MINIMUM LINE WIDTH
=STANDARD
0.075 MM
0.091 MM
MINIMUM LINE WIDTH
=STANDARD
0.083 MM
0.095 MM
MINIMUM LINE WIDTH
=STANDARD
0.075 MM
0.077 MM
MINIMUM NECK WIDTH
0.080 MM =DEFAULT
MINIMUM NECK WIDTH
0.090 MM
0.076 MM
MINIMUM NECK WIDTH
0.115 MM
0.076 MM
MINIMUM NECK WIDTH
0.100 MM
0.100 MM
MINIMUM NECK WIDTH
0.310 MM
0.222 MM
MINIMUM NECK WIDTH
=STANDARD =STANDARD
0.151 MM
0.185 MM
MINIMUM NECK WIDTH
=STANDARD =STANDARD
0.095 MM
0.112 MM
MINIMUM NECK WIDTH
=STANDARD =STANDARD
0.075 MM
0.091 MM
MINIMUM NECK WIDTH
=STANDARD =STANDARD
0.083 MM
0.095 MM
MINIMUM NECK WIDTH
=STANDARD =STANDARD
0.075 MM
0.077 MM
BOARD AREAS
NO_TYPE,BGA
MAXIMUM NECK LENGTH
12.7 MMDEFAULT
12.7 MM
MAXIMUM NECK LENGTH
=STANDARD55_OHM_SE
MAXIMUM NECK LENGTH
=STANDARD50_OHM_SE
MAXIMUM NECK LENGTH
=STANDARD40_OHM_SE
MAXIMUM NECK LENGTH
=STANDARD
MAXIMUM NECK LENGTH
=STANDARD
MAXIMUM NECK LENGTH
MAXIMUM NECK LENGTH
MAXIMUM NECK LENGTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR PRIMARY GAP
DIFFPAIR PRIMARY GAP
DIFFPAIR PRIMARY GAP
DIFFPAIR PRIMARY GAP
DIFFPAIR PRIMARY GAP
DIFFPAIR PRIMARY GAP
DIFFPAIR PRIMARY GAP
DIFFPAIR PRIMARY GAP
DIFFPAIR PRIMARY GAP
6
BOARD UNITS (MIL or MM)
MM
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
=DEFAULT=DEFAULT
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
=STANDARD=STANDARD
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
=STANDARD=STANDARD
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
=STANDARD=STANDARD
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
=STANDARD=STANDARD
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
=STANDARD=STANDARD
0.224 MM0.224 MM
0.200 MM0.200 MM
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
=STANDARD=STANDARD
0.234 MM0.234 MM
0.220 MM0.220 MM
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
=STANDARD=STANDARD
0.244 MM0.244 MM
0.230 MM0.230 MM
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
=STANDARD=STANDARD
0.400 MM0.400 MM
0.400 MM0.400 MM
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
=STANDARD=STANDARD
0.330 MM0.330 MM
0.330 MM0.330 MM
5
TABLE_BOARD_INFO
ALLEGRO VERSION
15.2
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
0 MM0 MM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
SPACING_RULE_SET
DEFAULT STANDARD BGA_P1MM BGA_P2MM BGA_P3MM
SPACING_RULE_SET
1.5:1_SPACING 2:1_SPACING
2.5:1_SPACING 3:1_SPACING 4:1_SPACING
SPACING_RULE_SET
2X_DIELECTRIC 3X_DIELECTRIC 4X_DIELECTRIC 5X_DIELECTRIC 2X_DIELECTRIC 3X_DIELECTRIC 4X_DIELECTRIC
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
5X_DIELECTRIC
LAYER
* * * * *
LAYER
* * * * *
LAYER
TOP,BOTTOM TOP,BOTTOM TOP,BOTTOM TOP,BOTTOM
* * * *
4
LINE-TO-LINE SPACING
0.1 MM
=DEFAULT
0.1 MM
0.2 MM
0.3 MM
LINE-TO-LINE SPACING
0.15 MM
0.2 MM
0.25 MM
0.3 MM
0.4 MM
LINE-TO-LINE SPACING
0.140 MM
0.210 MM
0.280 MM
0.350 MM
0.126 MM
0.189 MM
0.252 MM
0.315 MM
WEIGHT
WEIGHT
WEIGHT
TABLE_SPACING_RULE_HEAD
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
MEM_CLK CLK_FSB CLK_LPC CLK_PCI
3
AREA_TYPE
*
* * * * * * *
FSB_DSTB
BGA BGA BGA BGA BGA BGA BGA BGA
SPACING_RULE_SET
BGA_P1MM BGA_P2MM BGA_P2MM BGA_P2MM BGA_P2MM BGA_P2MMCLK_PCIE BGA_P2MMCLK_SLOW BGA_P3MMFSB_DSTB
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
NET_PHYSICAL_TYPE
MEM_40S
MEM_40S_VDD
AREA_TYPE
BGA BGA
STANDARD STANDARD
TABLE_PHYSICAL_ASSIGNMENT_HEAD
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
PHYSICAL_RULE_SET
D
C
B
A
1:1_DIFFPAIR
LAYER
ALLOW ROUTE ON LAYER?
*
Y
MINIMUM LINE WIDTH
=STANDARD
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
=STANDARD =STANDARD
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
0.1 MM0.1 MM
K19i PCB Rule Definitions
SYNC_MASTER=WFERRY_K19I
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
D
APPLE INC.
8
7 6
5
4
3
2
SCALE
NONE
SYNC_DATE=12/12/2008
051-7903
SHT
OF
1
A
REV.
A
8383
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