Apple A1534 Schematics

ALIASES RESOLVED

PRODUCT SAFETY REQUIREMENTS:

Schematic / PCB #'s

PCB TO BE SILK-SCREENED WITH UL/CUL RECOGNITION MARK, MANUFACTURER'S UL FILE

PCB, UL RECOGNIZED, MIN. 130-C TEMP. RATING AND V-0 FLAME RATING PER UL 796 & UL 94. NUMBER, UL PCB MATERIAL DESIGNATION, 130-C TEMP. RATING AND V-0 FLAME RATING.

X260 MLB - CBB

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<PART_DESCRIPTION>

<SCH_NUM>

1 OF 130

PCBF,MLB,X260820-00244 1 PCB CRITICAL

Table of Contents [1]

CRITICALSCHEM,MLB,X2601 SCH051-00532

PROPRIETARY PROPERTY OF APPLE INC.

REVISION

ECNREV DESCRIPTION OF REVISION

DRAWING TITLE

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

CK APPD

2 1

1245678

B

D

6 5 4 3

C

A

PAGE

C

A

D

DATE

R

SHEET

D

SIZEDRAWING NUMBER

BRANCH

7

B

3

II NOT TO REPRODUCE OR COPY IT

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

8

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

NOTICE OF PROPRIETARY PROPERTY:

Apple Inc.

<CSA>

DATEPAGE

<CSA>

DATE

PAGE CONTENTS SYNC

SYNCCONTENTS

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

HYNIX

0 0

Programmable Parts

in a binary fashion (ID0 is the LSb). IDx is high if not set low in the BOM table.

Board ID should start all-high (first build), and each new build increment stuffing

Module Parts

VENDOR

1

Board IDs

Module Parts

CFG 2

DRAM Parts

0

SIZE

0

CFG 1

1

0

1

0

2GB

1

SAMSUNG

0

MICRON

18GB

CFG 0

ELPIDA

4GB DDP

SSD Configs

BOM Groups

4GB QDP

CFG 3

CPU DRAM CFG Chart

Alternate Parts

SSD Parts

CPU DRAM SPD Straps

2 OF 67

2 OF 130

<SCH_NUM>

BOM Configuration [2]

SYNC_DATE=06/09/2015SYNC_MASTER=X260_ERIC

UPCROM:BLANKCRITICAL

IC,SPI SERIAL FLASH,8MBIT,3.0V,CSP,8P

335S00084 1 U3090

UPCROM:PROG

IC,NVM (VXXX) CBB, X260

341S00466 U3090 CRITICAL1

SSD:512GB_SAND NAND:256GB_SAND,CAPACITY2,SANDISK_1Y

CRITICALU8600

1 S3X:B0

IC,S3-X,B0

337S00175

U9100,U9120 CRITICAL

335S1030

NAND,TOG DDR2,2CH,64GB,1YNM,3.3V,LGA60

NAND:64GB2

NAND,TOG DDR2,2CH,128GB,1YNM,3.3V,LGA60

U9100,U9120 CRITICAL

NAND:128GB335S00050 2

NEC alt to Kemet

128S00039 128S00038 ALL

ALL

Cyntec alt to Murata

152S00362 152S1129

ALL138S0831138S00049

Kyocera alt to Murata

ALL138S0831138S00032

Taiyo alt to Murata

ALL138S1086138S00087

TFT alt to Cyntec

ALL107S00056107S00086 ALL

Chilisin alt to Cyntec

152S00220152S00347

ALL

Taiyo alt to Murata

138S0943138S00090

Samsung alt to Murata

138S0739 ALL138S0706

ALL

Kyocera alt to Murata

138S0945 138S0706

Murata alt to TDK

155S00008 ALL155S00011

311S0612 ALL

Diodes alt to NXP

311S00057

ALL

Semtech alt to TI

353S4296353S00773

107S0284107S00021 ALL

TFT alt to Cyntec

107S0276

TFT alt to Cyntec

107S00020 ALL

338S00175 ALL338S1264

Broadcom alt packaging

333S00030

Hynix alt to Micron

ALL333S00016

311S00004 ALL

OnSemi alt to NXP

311S0370

ALL

Kyocera alt to TXC

197S00053 197S00050

197S00050

Murata alt to TXC

ALL197S00055

155S0706 155S0302 ALL

Taiyo alt to Murata

ALL

Murata alt to TDK

155S0361155S0741

155S00165

Taiyo alt to TDK

ALL155S0382

155S00166 155S0391

TDK alt to Murata

ALL

155S00155

TDK alt to Murata

ALL155S0441

ALL

Murata alt to Cyntec

152S00343 152S1682

138S00077 138S00035 ALL

Taiyo alt to Murata

337S00174 337S00175

S3X B0 alt to A0

ALLS3X:B0

ALL

ONSemi alt to TI

353S2208353S00714

353S00712 ALL353S2216

OnSemi alt to TI

152S00028

Murata alt to Taiyo Yuden

ALL152S1751

138S00073 138S00047 ALL

Murata alt to Taiyo

132S00012 132S0401

Multi alt to Taiyo

ALL

138S0772 ALL

Taiyo alt to Murata

138S00013

Rohm alt to Sanyo

128S00010 ALL128S00031

Kemet alt to Sanyo

ALL128S00010128S00011

NEC alt to Sanyo

ALL128S00026 128S00010

ALL128S00029 128S00015

Rohm alt to Sanyo

128S00015 ALL128S00009

Kemet alt to Sanyo

ALL128S00015128S00007

NEC alt to Sanyo

ALL138S0705

Samsung alt to Murata

138S0786

ALL

ROHM alt to NEC

128S00020128S00021

152S00224

Vishay alt to Cyntec

152S00098 ALL

152S2037

Cyntec new alt to Cyntec

ALL152S00311

376S1080 ALL376S0820

Diodes alt to OnSemi

128S0397 128S0325 ALL

Kemet alt to Sanyo

TDK alt to Murata

107S0085 ALL107S00070

376S00007 376S1179

AOS alt to Vishay

ALL

128S0487128S00012

ROHM alt to NEC

ALL

Polytronics alt to Wayon

740S0190 ALL740S00005

Sanyo alt to NEC

128S0487 ALL128S0296

Kemet alt to Sanyo

740S00004 ALL740S0134

ALL128S00041128S00044

Rubycon alt to Sanyo

107S0249

TFT alt to Cyntec

ALL107S0251

ALL376S0604

Diodes alt to Fairchild

376S1053

372S0186 372S0185 ALL

NXP alt to Diodes

Murata alt to Taiyo Yuden

138S0703 138S0648 ALL

NXP alt for Diodes single

ALL376S1089 376S1128

NXP alt for Diodes dual

376S1129 376S0855 ALL

376S00074

Toshiba alt for Diodes dual

ALL376S0855

DRAM_TYPE:ELPIDA_8GB

DRAM:ELP_8GB

RAMCFG0_L,RAMCFG1_L,DRAM_TYPE:HYNIX_8GB

DRAM:HYN_8GB

DRAM:SAM_8GB

RAMCFG0_L,DRAM_TYPE:SAMSUNG_8GB

SSD:256GB_SAND NAND:128GB_SAND,CAPACITY0,CAPACITY1,SANDISK_1Y

NAND:256GB,CAPACITY2SSD:512GB

MLB_DEBUG:ENG DEBUGLED

BOARDID1_LBUILD:CBB

SSDRAM:4GBIT

CRITICALU8600_POP_DRAM

333S00017 1

IC,LPDDR3-1600,128MX8,1.8V,25NM,276 POP

BUILD:PROTO1 BOARDID0_L

BOOTROM_MIC:BLANK

CRITICAL335S1029 U61001

64 MBIT SPI QUAD I/O FLASH,CSP,3.3V,QUAD IO

BOOTROM_WIN:BLANK

335S1009 CRITICALU6100

64 MBIT SPI QUAD I/O FLASH,CSP,3.3V,QUAD IO

1

BOOTROM_MAC:BLANK

CRITICAL335S1010 U61001

64 MBIT SPI QUAD I/O FLASH,CSP,3.3V,QUAD IO

NAND:64GB,CAPACITY1SSD:128GB

2

CRITICALU9100,U9120

NAND,TOG DDR2,2CH,256GB,1YNM,3.3V,LGA60

335S00122 NAND:256GB_SAND

IC,CD3215,USB PWR SWITCH,A1,6X6MM,BGA96

UPC:A1

U3100

CRITICAL1353S00660

IC,EFI ROM (VXXX) CBB,X260

341S00465 CRITICALU6100 BOOTROM:PROG1

NAND,TOG DDR2,2CH,128GB,1YNM,3.3V,LGA60

CRITICAL

2

U9100,U9120

335S00121 NAND:128GB_SAND

NAND,TOG DDR2,2CH,256GB,1YNM,3.3V,LGA60

U9100,U9120

NAND:256GB

CRITICAL

335S00051 2

CRITICAL

IC,CPU,SKY,SR2EH,PRQ,D1,2/2,1.3,5W,.85,B1515

337S00209 CPU:1.3GHZU05001

IC,CPU,SKY,SR2EM,PRQ,D1,2/2,1.2,5W,.85,B1515

337S00208 CPU:1.2GHZU0500 CRITICAL1

1 U0500

IC,CPU,SKY,SR2EN,PRQ,D1,2/2,1.1,5W,.85,B1515

337S00207 CPU:1.1GHZCRITICAL

IC,SDRAM,LPDDR-1866,32GBIT,253B FBGA

333S00054

CRITICAL

2

DRAM_TYPE:ELPIDA_8GB

U2300,U2500

CRITICALU2300,U2500

2333S00053

IC,SDRAM,LPDDR-1866,32GBIT,253B FBGA DRAM_TYPE:HYNIX_8GB

U2300,U2500

IC,SDRAM,LPDDR-1866,32GBIT,253B FBGA

2

CRITICAL

333S00052

DRAM_TYPE:SAMSUNG_8GB

CRITICAL

IC,SMC-B1,EXTERNAL (V2.33A2) PROTO 1,X260

341S00431 SMC:PROGU50001

NAND:128GB,CAPACITY0,CAPACITY1SSD:256GB

U7800

CRITICAL1338S00168 PMIC:A0D

IC,PMU,P650839A0D,7X7MM,BGA168

LABEL

LABEL,BARCODE,2D,1D,CONFIG,MLB,X260

825-00162 1

J11/J13 MLB DYMAX ADHESIVE 29993-SC 0.4G

GLUE CRITICAL1946-3892

IC,SMC12-B1,40MHZ/50DMIPS MCU,7X7,168BGA

U5000338S1231 CRITICAL SMC:BLANK1

CAM_FREQ:24M,CAM_XTAL:NO,SSDRAM:4GBIT,S3X:B0,UPC:A1,PCH24M:SUS,EQ:4CH,PMIC:A0D,BSSB_GPIO

MLB_MISC

MLB_COMMON ALTERNATE,COMMON,MLB_MISC,MLB_DEBUG:ENG,MLB_PROGPARTS,BUILD:CBB

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_HEAD

BOM GROUP BOM OPTIONS

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

TABLE_BOMGROUP_ITEM

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_HEAD

BOM GROUP BOM OPTIONS

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_HEAD

BOM GROUP BOM OPTIONS

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

PART NUMBER

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

PART NUMBER

TABLE_ALT_ITEM

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

TABLE_BOMGROUP_ITEM

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

TABLE_BOMGROUP_HEAD

BOM GROUP BOM OPTIONS

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

BOM Groups

Programmable Parts

Common BOM

Partial & development BOMs

Top level BOM Variants

3 OF 67

3 OF 130

<SCH_NUM>

939-01880

ALTERNATE,CMN,DRAM:SAM_8GB,SSD:512GB_SAND,WIFI:FCC

PCBA,MLB,NO CPU,SA 8GB,SAND 512G,WIFI FCC,X260

939-01879

ALTERNATE,CMN,DRAM:SAM_8GB,SSD:512GB,WIFI:FCC

PCBA,MLB,NO CPU,SA 8GB,TOSH 512G,WIFI FCC,X260

CRITICAL1 WIFI:FCC341S00346 U3780

WIFI ROM (PXXXX) PROTO0,WW1,X260

685-00073 CMN PTS,PCBA,MLB,X260

MLB_COMMON

MLB_PROGPARTS BOOTROM:PROG,BT:PROG,SMC:PROG,UPCROM:PROG

CRITICAL1 WIFI:APACU3780341S00348

WIFI ROM (PXXXX) PROTO0,WW3,X260

CRITICAL1 WIFI:INDU3780341S00349

WIFI ROM (PXXXX) PROTO0,IND,X260

CRITICAL1 WIFI:ETSIU3780341S00347

WIFI ROM (PXXXX) PROTO0,WW2,X260

CRITICAL1 CMNCMNPTS685-00073

CMN PTS,PCBA,MLB,X260

1 BT:PROGCRITICAL341S00345 U3770

BT ROM (VXX) PROTO0,X260

PCBA,MLB,1.3GHZ,EL 8GB,TOSH 256G,WIFI FCC,X260

ALTERNATE,CMN,CPU:1.3GHZ,DRAM:ELP_8GB,SSD:256GB,WIFI:FCC

639-6664

639-6670 PCBA,MLB,1.1GHZ,HY 8GB,TOSH 128G,WIFI FCC,X260

ALTERNATE,CMN,CPU:1.1GHZ,DRAM:HYN_8GB,SSD:128GB,WIFI:FCC

PCBA,MLB,1.2GHZ,SA 8GB,TOSH 512G,WIFI APAC,X260639-6672

ALTERNATE,CMN,CPU:1.3GHZ,DRAM:SAM_8GB,SSD:512GB,WIFI:APAC

PCBA,MLB,1.3GHZ,EL 8GB,TOSH 512G,WIFI FCC,X260

ALTERNATE,CMN,CPU:1.3GHZ,DRAM:ELP_8GB,SSD:512GB,WIFI:FCC

639-6665

PCBA,MLB,1.3GHZ,HY 8GB,TOSH 256G,WIFI FCC,X260639-6666

ALTERNATE,CMN,CPU:1.3GHZ,DRAM:HYN_8GB,SSD:256GB,WIFI:FCC

PCBA,MLB,1.2GHZ,EL 8GB,TOSH 256G,WIFI ETSI,X260639-6671

ALTERNATE,CMN,CPU:1.2GHZ,DRAM:ELP_8GB,SSD:256GB,WIFI:ETSI

PCBA,MLB,1.3GHZ,SA 8GB,TOSH 512G,WIFI FCC,X260639-6669

ALTERNATE,CMN,CPU:1.3GHZ,DRAM:SAM_8GB,SSD:512GB,WIFI:FCC

PCBA,MLB,1.3GHZ,SA 8GB,TOSH 256G,WIFI FCC,X260639-6668

ALTERNATE,CMN,CPU:1.3GHZ,DRAM:SAM_8GB,SSD:256GB,WIFI:FCC

PCBA,MLB,1.3GHZ,HY 8GB,TOSH 512G,WIFI FCC,X260639-6667

ALTERNATE,CMN,CPU:1.3GHZ,DRAM:HYN_8GB,SSD:512GB,WIFI:FCC

639-6678

ALTERNATE,CMN,CPU:1.3GHZ,DRAM:HYN_8GB,SSD:512GB_SAND,WIFI:FCC

PCBA,MLB,1.3GHZ,HY 8GB,SAND 512G,WIFI FCC,X260

639-6676

ALTERNATE,CMN,CPU:1.2GHZ,DRAM:ELP_8GB,SSD:256GB_SAND,WIFI:FCC

PCBA,MLB,1.2GHZ,EL 8GB,SAND 256G,WIFI FCC,X260

639-6677

ALTERNATE,CMN,CPU:1.3GHZ,DRAM:SAM_8GB,SSD:512GB_SAND,WIFI:FCC

PCBA,MLB,1.3GHZ,SA 8GB,SAND 512G,WIFI FCC,X260

639-6675

ALTERNATE,CMN,CPU:1.3GHZ,DRAM:SAM_8GB,SSD:512GB_SAND,WIFI:APAC

PCBA,MLB,1.3GHZ,SA 8GB,SAND 512G,WIFI APAC,X260

639-6674

ALTERNATE,CMN,CPU:1.3GHZ,DRAM:ELP_8GB,SSD:256GB_SAND,WIFI:FCC

PCBA,MLB,1.3GHZ,EL 8GB,SAND 256G,WIFI FCC,X260

639-6673

ALTERNATE,CMN,CPU:1.2GHZ,DRAM:ELP_8GB,SSD:256GB_SAND,WIFI:ETSI

PCBA,MLB,1.2GHZ,EL 8GB,SAND 256G,WIFI ETSI,X260

PCBA,MLB,1.1GHZ,HY 8GB,TOSH 512G,WIFI FCC,X260

ALTERNATE,CMN,CPU:1.1GHZ,DRAM:HYN_8GB,SSD:512GB,WIFI:FCC

639-6680

639-6682

ALTERNATE,CMN,CPU:1.2GHZ,DRAM:SAM_8GB,SSD:256GB_SAND,WIFI:FCC

PCBA,MLB,1.2GHZ,SA 8GB,SAND 256G,WIFI FCC,X260

ALTERNATE,CMN,CPU:1.2GHZ,DRAM:SAM_8GB,SSD:256GB_SAND,WIFI:IND

PCBA,MLB,1.2GHZ,SA 8GB,SAND 256G,WIFI IND,X260639-6685

ALTERNATE,CMN,CPU:1.1GHZ,DRAM:SAM_8GB,SSD:512GB_SAND,WIFI:ETSI

PCBA,MLB,1.1GHZ,SA 8GB,SAND 512G,WIFI ETSI,X260639-6684

PCBA,MLB,1.3GHZ,SA 8GB,SAND 256G,WIFI FCC,X260

ALTERNATE,CMN,CPU:1.3GHZ,DRAM:SAM_8GB,SSD:256GB_SAND,WIFI:FCC

639-6683

ALTERNATE,CMN,CPU:1.2GHZ,DRAM:HYN_8GB,SSD:512GB_SAND,WIFI:FCC

639-6679 PCBA,MLB,1.2GHZ,HY 8GB,SAND 512G,WIFI FCC,X260

PCBA,MLB,1.3GHZ,HY 8GB,TOSH 128G,WIFI FCC,X260639-6686

ALTERNATE,CMN,CPU:1.3GHZ,DRAM:HYN_8GB,SSD:128GB,WIFI:FCC

ALTERNATE,CMN,CPU:1.3GHZ,DRAM:SAM_8GB,SSD:128GB,WIFI:FCC

PCBA,MLB,1.3GHZ,SA 8GB,TOSH 128G,WIFI FCC,X260639-6694

PCBA,MLB,1.2GHZ,HY 8GB,TOSH 256G,WIFI FCC,X260

ALTERNATE,CMN,CPU:1.2GHZ,DRAM:HYN_8GB,SSD:256GB,WIFI:FCC

639-6681

ALTERNATE,CMN,CPU:1.1GHZ,DRAM:SAM_8GB,SSD:512GB_SAND,WIFI:FCC

PCBA,MLB,1.1GHZ,SA 8GB,SAND 512G,WIFI FCC,X260639-6690

ALTERNATE,CMN,CPU:1.2GHZ,DRAM:HYN_8GB,SSD:128GB,WIFI:FCC

PCBA,MLB,1.2GHZ,HY 8GB,TOSH 128G,WIFI FCC,X260639-6691

ALTERNATE,CMN,CPU:1.2GHZ,DRAM:SAM_8GB,SSD:128GB,WIFI:FCC

PCBA,MLB,1.2GHZ,SA 8GB,TOSH 128G,WIFI FCC,X260639-6692

ALTERNATE,CMN,CPU:1.2GHZ,DRAM:SAM_8GB,SSD:512GB,WIFI:FCC

PCBA,MLB,1.2GHZ,SA 8GB,TOSH 512G,WIFI FCC,X260639-6693

639-6689 PCBA,MLB,1.1GHZ,SA 8GB,SAND 256G,WIFI FCC,X260

ALTERNATE,CMN,CPU:1.1GHZ,DRAM:SAM_8GB,SSD:256GB_SAND,WIFI:FCC

639-6688 PCBA,MLB,1.1GHZ,HY 8GB,TOSH 256G,WIFI FCC,X260

ALTERNATE,CMN,CPU:1.1GHZ,DRAM:HYN_8GB,SSD:256GB,WIFI:FCC

639-6687 PCBA,MLB,1.1GHZ,SA 8GB,TOSH 128G,WIFI FCC,X260

ALTERNATE,CMN,CPU:1.1GHZ,DRAM:SAM_8GB,SSD:128GB,WIFI:FCC

X260 BOM Variants

SYNC_MASTER=J43_MLB SYNC_DATE=10/24/2012

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

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D

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PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

TABLE_BOMGROUP_ITEM

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_HEAD

BOM GROUP BOM OPTIONS

TABLE_BOMGROUP_HEAD

BOM NUMBER BOM NAME BOM OPTIONS

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_HEAD

BOM NUMBER BOM NAME BOM OPTIONS

SSD EMI CANs

DRAM EMI CAN

WIFI EMI CAN

860-00324

860-00329

USB-C BTB Connector BossCPU Heat Spreader Bosses

4 OF 67

4 OF 130

<SCH_NUM>

SH04001 CRITICAL

CAN,EMI,WIFI,X261

806-7064

SH04031 CRITICAL

FENCE,EMI,SSD,TOP,X261

806-00889

1 CRITICAL870-00998

MYLAR,SHIM,MLB,X261

MYLAR_SHIM

CRITICAL1 SH0402806-04848

CAN,EMI,DRAM,X260

SH04041 CRITICAL806-05622

FENCE,EMI,SSD,BTM,X260

CRITICAL1 SSD_TAPE_BTM870-01557 TAPE,CONDUCTIVE,SSD,REEL,X260

CRITICAL1870-00878 SSD_TAPE_TOPTAPE,CONDUCTIVE,SSD,REEL,X261

PD PARTS

SYNC_DATE=10/24/2012SYNC_MASTER=J43_MLB

Z0405

1

3.7OD1.85ID-1.5H-SM

1

Z0404

3.7OD1.85ID-1.5H-SM

1

Z0403

3.7OD1.85ID-1.5H-SM

1

Z0406

2.73OD1.15ID-0.814H-SM

1

SH0404

SM

OMIT_TABLE

SHLD-CAN-EMI-SSD-BTM-X261

1

SM

OMIT_TABLE

SH0403

SHLD-FENCE-SSD-TOP-X261

1

SM

OMIT_TABLE

SH0402

SHLD-CAN-EMI-DRAM-X261

SHLD-J92-EMI-CAN-WIFI

1

SH0400

SM

OMIT_TABLE

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

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D

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PAGE TITLE

C

A

D

2 1

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NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

DDI Port Assignments:

Internal panel

GPP_E20: JTAG_TBT_T_TMS

GPP_E18: JTAG_TBT_X_TMS'Ridge systems:

USBC Sink 0

USBC Sink 1

(IPD-PLTRST#)

eDP Port Assignment:

<SCH_NUM>

5 OF 67

5 OF 130

JTAG_ISP_TDO

NC_DP_DDI2_ML_CP<2> NC_DP_DDI2_ML_CN<3>

PP3V3_S0

TP_EDP_DISP_UTIL

DP_INT_AUXCH_C_P

NC_DP_DDI2_AUXCH_CN

DP_INT_ML_C_N<1>

DP_INT_ML_C_N<2>

DP_INT_AUXCH_C_N

DP_INT_ML_C_N<3> DP_INT_ML_C_P<3>

DP_INT_ML_C_P<2>

DP_XA_ML_C_N<1>

DP_XA_ML_C_P<0>

DP_INT_ML_C_N<0>

NC_DP_DDI2_ML_CN<1>

EDP_BKLT_EN

NC_DP_DDI2_ML_CP<3>

PCH_UPC_XA_SWD_DATA

DP_DDI2_HPD

NC_DP_DDI2_AUXCH_CP

DP_XA_AUXCH_C_P

DP_XA_AUXCH_C_N

DP_INT_ML_C_P<1>DP_XA_ML_C_P<1>

NC_DP_DDI2_ML_CN<0>

NC_DP_DDI2_ML_CP<1>

DP_XA_ML_C_N<0>

NC_DP_DDI2_ML_CN<2>

DP_XA_ML_C_P<3>

DP_XA_ML_C_N<3>

PCH_UPC_XA_SWD_CLK PCH_DDPB_CTRLDATA

NC_PCH_DDPC_CTRLDATA

EDP_BKLT_PWM EDP_PANEL_PWRMCP_EDP_RCOMP

PPVCCIO_S0

PLT_RST_L

EDP_BKLT_EN

DP_INT_HPD

DP_DDI1_HPD

NC_DP_DDI2_ML_CP<0>

TP_PCH_GPP_E15

SSD_RESET_L

PCH_UPC_XA_SWD_CLK

TBT_POC_RESET

PCH_UPC_XA_SWD_DATA

DP_DDI1_HPD DP_DDI2_HPD

EDP_PANEL_PWR

JTAG_ISP_TDO DP_INT_HPD

DP_XA_ML_C_N<2> DP_XA_ML_C_P<2>

TBT_POC_RESET

DP_INT_ML_C_P<0>

SYNC_DATE=05/11/2015SYNC_MASTER=DEVMLB

BOM_COST_GROUP=CPU & CHIPSET

CPU GFX

64

60 23

2

1

R0520

PLACE_NEAR=U0500.A50:15.24mm

24.9

1% MF

1/20W

201

21

R0584

1/32W 01005

100K

MF5%

21

R0580

1/32W 01005

100K

MF5%

21

R0581

1/32W 01005

100K

MF5%

21

R0515

1/32W 01005

100K

MF5%

21

R0583

1/32W 01005

10K

MF5%

64 5

65 30 26 19 15 14

2

1

R0514

1/32W 01005

100K

MF

5%

64 5

59

21

R0510

1/32W 01005

10K

MF5%

21

R0512

1/32W 01005

10K

MF5%

21

R0590

1/32W 01005

100K

MF5%

21

R0591

1/32W 01005

100K

MF5%

53 5

65 53

52 5

63

23 5

19

23 5

60 23

64

60 23

19 5

64 5

53 5

L4

M5

F4

H4

H6

L6

A7

F6

M7

L10

C11

D3

F43

G46

G44

F45

H43

J46

J44

H45

A50

A40

D4 B6

G42

J42

D43

D41

C44

C42

B43

B41

A44

A42

G40

J40

D47

D45

A48

C46

B47

B45

C48

A46

F41

H41

U0500

CRITICAL

OMIT_TABLE

SKL-Y

BGA

SKL-Y-ULX

53

64

67 61 53 51 50 46 39 35 34

33 31 27 26 23 19 17 16 15 14 6

52 5

61 47 11 8

23 5

64 5

23 5

19 5

64 5

53 5

64 5

53 5

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

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PAGE TITLE

C

A

D

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A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

OUT OUT OUT

OUT

OUT OUT OUT OUT OUT OUT OUT

OUT

IN

OUT

BI

OUT

BI

BI BI

BI

IN IN

IN

SYM 1 OF 20

DDI

DISPLAY SIDEBANDS

EDP

DISPLAY

EDP_TXP0 EDP_TXN1 EDP_TXP1 EDP_TXN2

EDP_AUXP

EDP_AUXN

DDI1_TXN0

GPP_E23

GPP_E22

EDP_VDDEN

EDP_BKLCTL

EDP_BKLEN

GPP_E17/EDP_HPD

GPP_E16/DDPE_HPD3

GPP_E15/DDPD_HPD2

GPP_E14/DDPC_HPD1

GPP_E13/DDPB_HPD0

DDI2_AUXP

DDI2_AUXN

DDI1_AUXP

DDI1_AUXN

EDP_DISP_UTIL

EDP_TXN3 EDP_TXP3

EDP_TXP2

DDI1_TXN1

DDI1_TXN3

EDP_RCOMP

GPP_E20/DDPC_CTRLCLK

DDI1_TXP1

DDI1_TXP3 DDI2_TXN0

DDI2_TXN2 DDI2_TXP2

DDI2_TXP0 DDI2_TXN1 DDI2_TXP1

DDI1_TXN2

DDI1_TXP0

DDI2_TXN3

EDP_TXN0

DDI2_TXP3

GPP_E18/DDPB_CTRLCLK GPP_E19/DDPB_CTRLDATA

GPP_E21/DDPC_CTRLDATA

DDI1_TXP2

BI

OUT

OUT OUT

(IPD)

(IPU)

.

(IPD)

6 OF 67

6 OF 130

<SCH_NUM>

TP_XDP_PCH_OBSFN_C1 TP_XDP_PCH_OBSDATA_A3 BT_PWRRST_L BT_TIMESTAMP

TP_MCP_RSVD_BJ17

TP_MCP_RSVD_BJ15

TP_MCP_RSVD_M27

TP_MCP_RSVD_L28

TP_MCP_RSVD_L24

TP_MCP_RSVD_M25

TP_MCP_RSVD_BE19 TP_MCP_RSVD_BA23

TP_MCP_RSVD_AY22

TP_MCP_RSVD_BN1

TP_MCP_RSVD_D49

TP_ITP_PMODE

CPU_CFG_RCOMP

TP_MCP_RSVD_BF18

TP_MCP_RSVD_AY18

TP_MCP_RSVD_BA17

NC_CPU_CFG0

NC_CPU_CFG10

NC_CPU_CFG1

TP_CPU_CFG3

NC_CPU_CFG2

CPU_CFG<4> NC_CPU_CFG5

NC_CPU_CFG8

NC_CPU_CFG6 NC_CPU_CFG7

NC_CPU_CFG9

NC_CPU_CFG13

NC_CPU_CFG12

NC_CPU_CFG11

NC_CPU_CFG14 NC_CPU_CFG15

NC_CPU_CFG17

NC_CPU_CFG16

NC_CPU_CFG18 NC_CPU_CFG19

TP_MCP_RSVD_BL64 TP_MCP_RSVD_BG47

PP3V3_S0

XDP_CPUPCH_TDO

XDP_CPUPCH_TCK

XDP_CPUPCH_TRST_L

XDP_CPUPCH_TDI

TP_XDP_PCH_TCK

XDP_CPUPCH_TRST_L

XDP_CPUPCH_TMS

XDP_CPUPCH_TDO

XDP_CPUPCH_TDI

XDP_CPUPCH_TCK

TP_XDP_BPM_L<1>

CPU_PROCHOT_R_L

TP_XDP_BPM_L<0>

TP_XDP_BPM_L<2> TP_XDP_BPM_L<3>

CPU_PROCHOT_L

PP1V_S0SW

CPU_OPI_RCOMP

CPU_PECI

PM_THRMTRIP_L

CPU_CATERR_L

PP1V_S3

XDP_CPUPCH_TMS

BT_TIMESTAMP

BT_PWRRST_L

PCH_OPI_COMP

SYNC_DATE=05/11/2015SYNC_MASTER=DEVMLB

CPU Misc/JTAG/CFG/RSVD

BOM_COST_GROUP=CPU & CHIPSET

2

1

1/32W 01005

MF

5%

1.00K

R0634

64 6

21

R0619

1/32W 01005

100K

MF5%

21

R0618

1/32W 01005

100K

MF5%

2

1

R0613

49.9

1% MF

1/20W

201

H47 B62

J48

F47

C52

H49

G50

F51

J50

H51

C59

G48

C54

D53

BN17

F49

A52

B51

C50

B53

B49

M9

E11

BC11

BD8

U0500

CRITICAL

BGA

OMIT_TABLE

SKL-Y-ULX

SKL-Y

BP16

63

2

1

R0680

49.9

1% MF

1/20W

201

63

64

63

2

1

R0621

49.9

PLACE_NEAR=U0500.BP16:2.54mm

1% MF

1/20W

201

2

1

R0620

49.9

PLACE_NEAR=U0500.BN17:2.54mm

1% MF

1/20W

201

2

1

R0612

1/32W 01005

1.00K

MF

5%

31 30

63 6

63

42 31 30

2

1

R0610

1/32W 01005

1.00K

MF

5%

2 1

R0611

499

1% MF

1/20W

201

31

65 30

63 6

OMIT_TABLE

CRITICAL

SKL-Y-ULX

U0500

G52

F53

J52 H53 H55 D55 C56

F55 D61 G58 D57

F61

J60

J58 H61 H59

J54 G54

G56

J56

A60

AH7

B3

B4

BA21 BB14

BC19

BE19

BF18

BN3 BP3

F1

F3

H12

K12

L16 L18

L22

L24 L28

M15

M17

M23

M25

M27

P13

R12

BA17

BG47

BL64

BA23 AY22

BGA

SKL-Y

AY18

A54

L26

M19

L20

M21

D49

BD18

BJ15 BJ17

AY20

BN1

L36 L38

BB18

BA19

67 61 53 51 50 46 39 35 34

33 31 27 26 23 19 17 16 15 14 5

63 61 50 12 8

61 50 42 31 15 12 8

64 6

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

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D

R

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PAGE TITLE

C

A

D

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PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

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8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

OUT

CPU MISC

JTAG

SYM 4 OF 20

PROC_TDI

PROC_TDO

GPP_B4/CPU_GP3

GPP_B3/CPU_GP2

GPP_E7/CPU_GP1

GPP_E3/CPU_GP0

BPM2*

BPM1*

SKTOCC*

PECI

PCH_OPIRCOMP

PROC_POPIRCOMP

BPM3*

CATERR*

PROCHOT* THERMTRIP*

BPM0*

PROC_TCK

PCH_TRST*

JTAGX

PCH_JTAG_TMS

PCH_JTAG_TDO

PCH_JTAG_TDI

PCH_JTAG_TCK

PROC_TRST*

PROC_TMS

BI

OUT

NC NC NC NC

NC NC

NC

OUT

BI BI

BI

OUT

NC

BI

IN

OUT

IN

BI

OUT

IN

SYM 12 OF 20

RESERVED SIGNALS

CFG0

CFG10

RSVD

CFG1

CFG3

CFG2

CFG4 CFG5

CFG8

CFG6 CFG7

CFG9

CFG13

CFG12

CFG11

CFG14 CFG15

CFG17

CFG16

CFG18

RSVD

CFG19

RSVD

ITP_PMODE

CFG_RCOMP

RSVD

TP1 TP2

RSVD

TP4

RSVD RSVD

RSVD

RSVD RSVD RSVD

RSVD

RSVD RSVD

RSVD

TP5 TP6

RSVD

RSVD_TP RSVD_TP

7 OF 67

7 OF 130

<SCH_NUM>

CPU_SM_RCOMP<0>

MEM_B_DQ<42>

MEM_B_DQ<41>

MEM_B_DQ<39>

MEM_B_DQ<38>

MEM_B_DQ<37>

CPU_SM_RCOMP<2>

MEM_B_DQ<44>

MEM_A_CAA<1> MEM_A_CAA<2>

MEM_A_CAB<0>

MEM_A_CAA<0>

MEM_A_CS_L<1>MEM_A_DQ<10>

MEM_B_DQS_N<7>

MEM_A_DQ<16>

MEM_A_DQ<8>

MEM_A_DQ<63>

MEM_A_DQ<62>

MEM_A_DQ<61>

MEM_A_DQ<60>

MEM_A_DQ<59>

MEM_A_DQ<58>

MEM_A_DQ<57>

MEM_A_DQ<56>

MEM_A_DQ<55>

MEM_A_DQ<54>

MEM_A_DQ<53>

MEM_A_DQ<52>

MEM_A_DQ<51>

MEM_A_DQ<50>

MEM_A_DQ<49>

MEM_A_DQ<48>

MEM_A_DQ<47>

MEM_A_DQ<46>

MEM_A_DQ<45>

MEM_A_DQ<44>

MEM_A_DQ<43>

MEM_A_DQ<42>

MEM_A_DQ<41>

MEM_A_DQ<40>

MEM_A_DQ<39>

MEM_A_DQ<38>

MEM_A_DQ<37>

MEM_A_DQ<36>

MEM_A_DQ<35>

MEM_A_DQ<34>

MEM_A_DQ<33>

MEM_A_DQ<32>

MEM_A_DQ<31>

MEM_A_DQ<30>

MEM_A_DQ<29>

MEM_A_DQ<28>

MEM_A_DQ<27>

MEM_A_DQ<26>

MEM_A_DQ<25>

MEM_A_DQ<24>

MEM_A_DQ<23>

MEM_A_DQ<22>

MEM_A_DQ<21>

MEM_A_DQ<20>

MEM_A_DQ<19>

MEM_A_DQ<18>

MEM_A_DQ<17>

MEM_A_DQ<15>

MEM_A_DQ<14>

MEM_A_DQ<13>

MEM_A_DQ<12>

MEM_A_DQ<11>

MEM_A_DQ<9>

MEM_A_DQ<7>

MEM_A_DQ<6>

MEM_A_DQ<5>

MEM_A_DQ<4>

MEM_A_DQ<3>

MEM_A_DQ<2>

MEM_A_DQ<1>

MEM_A_DQ<0>

MEM_A_CS_L<0>

MEM_A_CKE<3>

MEM_A_CKE<2>

MEM_A_CKE<1>

MEM_A_CKE<0>

MEM_A_CLK_P<1>

MEM_A_CLK_N<1>

MEM_A_CLK_P<0>

TP_CPU_MEMVTT_PWR_EN

CPU_DIMMA_VREFDQ CPU_DIMMB_VREFDQ

CPU_DIMM_VREFCA

MEM_A_DQS_P<7>

MEM_A_DQS_N<6> MEM_A_DQS_P<6> MEM_A_DQS_N<7>

MEM_A_DQS_N<5> MEM_A_DQS_P<5>

MEM_A_DQS_P<4>

MEM_A_DQS_N<4>

MEM_A_DQS_P<3>

MEM_A_DQS_N<2> MEM_A_DQS_P<2> MEM_A_DQS_N<3>

MEM_A_DQS_N<1> MEM_A_DQS_P<1>

MEM_A_DQS_N<0> MEM_A_DQS_P<0>

MEM_A_CAB<8> MEM_A_CAB<9>

MEM_A_CAB<7>

MEM_A_CAB<6>

MEM_A_CAB<5>

MEM_A_CAB<3> MEM_A_CAB<4>

MEM_A_CAB<2>

MEM_A_CAB<1>

MEM_A_CAA<7>

MEM_A_CAA<9>

MEM_A_CAA<8>

MEM_A_CAA<5> MEM_A_CAA<6>

MEM_A_CAA<4>

MEM_A_CAA<3>

MEM_A_ODT<0>

MEM_A_CLK_N<0>

MEM_B_DQ<63>

MEM_B_DQ<62>

MEM_B_DQ<61>

MEM_B_DQ<60>

MEM_B_DQ<59>

MEM_B_DQ<58>

MEM_B_DQ<57>

MEM_B_DQ<56>

MEM_B_DQ<55>

MEM_B_DQ<54>

MEM_B_DQ<53>

MEM_B_DQ<52>

MEM_B_DQ<51>

MEM_B_DQ<50>

MEM_B_DQ<49>

MEM_B_DQ<48>

MEM_B_DQ<47>

MEM_B_DQ<46>

MEM_B_DQ<45>

MEM_B_DQ<43>

MEM_B_DQ<40>

MEM_B_DQ<36>

MEM_B_DQ<35>

MEM_B_DQ<34>

MEM_B_DQ<33>

MEM_B_DQ<32>

MEM_B_DQ<31>

MEM_B_DQ<30>

MEM_B_DQ<29>

MEM_B_DQ<28>

MEM_B_DQ<27>

MEM_B_DQ<26>

MEM_B_DQ<25>

MEM_B_DQ<24>

MEM_B_DQ<23>

MEM_B_DQ<22>

MEM_B_DQ<21>

MEM_B_DQ<20>

MEM_B_DQ<19>

MEM_B_DQ<18>

MEM_B_DQ<17>

MEM_B_DQ<16>

MEM_B_DQ<15>

MEM_B_DQ<14>

MEM_B_DQ<13>

MEM_B_DQ<12>

MEM_B_DQ<11>

MEM_B_DQ<10>

MEM_B_DQ<9>

MEM_B_DQ<8>

MEM_B_DQ<7>

MEM_B_DQ<6>

MEM_B_DQ<5>

MEM_B_DQ<4>

MEM_B_DQ<3>

MEM_B_DQ<2>

MEM_B_DQ<1>

MEM_B_DQ<0>

MEM_B_DQS_P<7>

MEM_B_DQS_N<6> MEM_B_DQS_P<6>

MEM_B_DQS_N<5> MEM_B_DQS_P<5>

MEM_B_DQS_P<4>

MEM_B_DQS_N<4>

MEM_B_DQS_P<3>

MEM_B_DQS_N<3>

MEM_B_DQS_N<2> MEM_B_DQS_P<2>

MEM_B_DQS_N<1> MEM_B_DQS_P<1>

MEM_B_DQS_P<0>

MEM_B_DQS_N<0>

MEM_B_CAB<7> MEM_B_CAB<8> MEM_B_CAB<9>

MEM_B_CAB<5> MEM_B_CAB<6>

MEM_B_CAB<2> MEM_B_CAB<3> MEM_B_CAB<4>

MEM_B_CAB<0> MEM_B_CAB<1>

MEM_B_CAA<9>

MEM_B_CAA<8>

MEM_B_CAA<7>

MEM_B_CAA<5> MEM_B_CAA<6>

MEM_B_CAA<4>

MEM_B_CAA<3>

MEM_B_CAA<2>

MEM_B_CAA<0> MEM_B_CAA<1>

MEM_B_CS_L<1> MEM_B_ODT<0>

MEM_B_CS_L<0>

MEM_B_CKE<3>

MEM_B_CKE<1>

MEM_B_CKE<0>

MEM_B_CKE<2>

MEM_B_CLK_N<1> MEM_B_CLK_P<1>

MEM_B_CLK_P<0>

MEM_B_CLK_N<0>

CPU_SM_RCOMP<1>

SYNC_DATE=04/14/2015SYNC_MASTER=DEVMLB

CPU LPDDR3 Interface

BOM_COST_GROUP=CPU & CHIPSET

62 22

21

65 21

21

65 21

21

65 21

22

65 22

22

65 22

22

65 22

22

65 22

22

65 22

22

62 21

62 22

65 62 22

62 22

BF36

BC31

BG35

BD36

BF30

BC33

BF34

BC37

BE37

BG37

BN35

BM34

BJ35

BJ37

BN37

BG31

BL37

BM32

BN31

BK30

BP20

BJ33

BM30

BD34

BC64

BJ64

BF64

BD30

BC35

BK34

BJ31

BD22

BF26

BK22

BM26

BF22

BD26

BM22

BK26

BE21

BC21

BG23

BE23

BC23

BG21

BD24

BF24

BC25

BE25

BE27

BG27

BC27

BG25

BD28

BF28

BL21

BJ21

BN23

BL23

BJ23

BN21

BK24

BM24

BJ27

BJ25

BL27

BN25

BL25

BK28

BN27

BM28

BF32

BM36 BD32

BK36

BH30

BG33

BK32

BN33

BK40

BM44

BF44

BF40

BM40

BK44

BD44

BD40

BJ39

BL39

BL41

BK42

BN39

BJ41

BN41

BM42

BJ43

BJ45

BL45

BN43

BK46

BL43

BM46

BN45

BF46

BE45

BE43

BC45

BG45

BG43

BD46

BC43

BE41

BG39

BD42

BF42

BE39

BG41

BC39

BC41

U0500

BGA

SKL-Y

CRITICAL

OMIT_TABLE

SKL-Y-ULX

AV62

BN58

BM59

BL61

BB61

BN62

AV60

BJ61

BL62

BK59

BG61

BD61

BD59

BA56

AV58

AW57

AV56

BF62

AW55

AW59

BJ57

AW63

BG57

BN47

AR53

AW53

BM50

BK54

AJ55

AP58

BK50

BM54

AJ57

AP56

BM48

BK48

BN51

BN49

BJ49

BL49

BJ51

BL51

BK52

BM52

BN53

BN55

BL53

BJ53

BL55

BJ55

AG57

AG55

AK56

AK58

AH56

AH58

AL57

AL55

AM56

AM58

AT58

AR57

AN55

AN57

AR55

AT56

AN53

BM56

BN61

BL57

BB63

BD50

BF54

AP60

AJ63

BF50

BD54

AP62

AJ61

BD48

BF48

BG49

BG51

BE49

BC49

BE51

BC51

BF52

BD52

BG55

BC53

BE53

BG53

BC55

BE55

AT62

AR63

AN63

AN61

AR61

AT60

AM62

AM60

AL63

AL61

AG63

AH62

AK60

AK62

AH60

AG61

BA62

BC60 BA60

BC62

AW61

BE57

BC58

BB57

U0500

BGA

SKL-Y

OMIT_TABLE

SKL-Y-ULX

CRITICAL

63

2

1

R0750

PLACE_NEAR=U0500.BF64:12.7mm

1%

201

1/20W

MF

200

2

1

R0751

PLACE_NEAR=U0500.BJ64:12.7mm

MF

1%

201

1/20W

80.6

2

1

R0752

PLACE_NEAR=U0500.BC64:12.7mm

MF

1/20W

201

1%

162

20

62 21

65 62 21

62 21

65 62 21

62 21

62 22

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

BI

NC

OUT

OUT OUT

OUT

OUT OUT

OUT

OUT OUT OUT

OUT

OUT OUT

OUT

OUT OUT

OUT

NC

OUT

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

DDR CH - B

SYM 3 OF 20

DDR1_CAA2 DDR1_CAA3 DDR1_CAA4

DDR1_CAB0

DDR1_CAA9

DDR1_CAA8

DDR1_CAA1

DDR1_CAA0

DDR1_CAA6

DDR0_DQSN4/DDR1_DQSN0

DDR0_DQSP4/DDR1_DQSP0

DDR0_DQSN5/DDR1_DQSN1

DDR0_DQSP5/DDR1_DQSP1

DDR1_CS0* DDR1_CS1*

DDR1_ODT0

DDR1_CAB9

DDR1_CAB8

DDR1_CAB7

DDR1_CAB6

DDR1_CAB5

DDR1_CAB4

DDR1_CAB2

DDR1_CAB1

DDR1_CAA7

DDR1_CAA5

DDR0_DQ32/DDR1_DQ0

DDR0_DQSN7/DDR1_DQSN5

DDR0_DQSP7/DDR1_DQSP5

DDR0_DQSP6/DDR1_DQSP4

DDR0_DQSN6/DDR1_DQSN4

DDR1_DQSP5/DDR1_DQSP3

DDR1_DQSN5/DDR1_DQSN3

DDR1_DQSN4/DDR1_DQSN2

DDR1_DQSP4/DDR1_DQSP2

DDR1_MA3 DDR1_MA4

DDR1_DQSN7

DDR1_DQSN6 DDR1_DQSP6

DRAM_RESET*

DDR1_ALERT*

DDR_RCOMP2

DDR_RCOMP0 DDR_RCOMP1

DDR1_DQSP7

DDR1_PAR

DDR1_CKE3

DDR1_CKE1 DDR1_CKE2

DDR1_CKN1 DDR1_CKP1

DDR1_CKP0

DDR1_CKN0

DDR1_DQ63

DDR1_DQ62

DDR1_DQ61

DDR1_DQ60

DDR1_DQ59

DDR1_DQ58

DDR1_DQ57

DDR1_DQ55 DDR1_DQ56

DDR1_DQ52 DDR1_DQ53 DDR1_DQ54

DDR1_DQ51

DDR1_DQ50

DDR0_DQ63/DDR1_DQ47 DDR1_DQ48 DDR1_DQ49

DDR0_DQ62/DDR1_DQ46

DDR0_DQ61/DDR1_DQ45

DDR0_DQ58/DDR1_DQ42 DDR0_DQ59/DDR1_DQ43 DDR0_DQ60/DDR1_DQ44

DDR0_DQ57/DDR1_DQ41

DDR0_DQ56/DDR1_DQ40

DDR0_DQ55/DDR1_DQ39

DDR0_DQ54/DDR1_DQ38

DDR0_DQ53/DDR1_DQ37

DDR0_DQ52/DDR1_DQ36

DDR0_DQ51/DDR1_DQ35

DDR0_DQ50/DDR1_DQ34

DDR0_DQ49/DDR1_DQ33

DDR0_DQ48/DDR1_DQ32

DDR1_DQ45/DDR1_DQ29 DDR1_DQ46/DDR1_DQ30 DDR1_DQ47/DDR1_DQ31

DDR1_DQ44/DDR1_DQ28

DDR1_DQ43/DDR1_DQ27

DDR1_DQ40/DDR1_DQ24

DDR1_DQ42/DDR1_DQ26

DDR1_DQ39/DDR1_DQ23

DDR1_DQ38/DDR1_DQ22

DDR1_DQ37/DDR1_DQ21

DDR1_DQ36/DDR1_DQ20

DDR1_DQ35/DDR1_DQ19

DDR1_DQ34/DDR1_DQ18

DDR1_DQ33/DDR1_DQ17

DDR1_DQ32/DDR1_DQ16

DDR0_DQ46/DDR1_DQ14 DDR0_DQ47/DDR1_DQ15

DDR0_DQ43/DDR1_DQ11 DDR0_DQ44/DDR1_DQ12 DDR0_DQ45/DDR1_DQ13

DDR0_DQ42/DDR1_DQ10

DDR0_DQ41/DDR1_DQ9

DDR0_DQ38/DDR1_DQ6 DDR0_DQ39/DDR1_DQ7 DDR0_DQ40/DDR1_DQ8

DDR0_DQ36/DDR1_DQ4 DDR0_DQ37/DDR1_DQ5

DDR0_DQ33/DDR1_DQ1 DDR0_DQ34/DDR1_DQ2 DDR0_DQ35/DDR1_DQ3

DDR1_CKE0

DDR1_DQ41/DDR1_DQ25

DDR1_CAB3

DDR CH - A

SYM 2 OF 20

DDR0_CAB0

DDR0_CAA9

DDR0_CAA8

DDR0_CAB5

DDR0_CAA2 DDR0_CAA3 DDR0_CAA4 DDR0_CAA5 DDR0_CAA6 DDR0_CAA7

DDR0_CAB1 DDR0_CAB2 DDR0_CAB3 DDR0_CAB4

DDR0_CS1*

DDR0_ODT0

DDR0_DQ1

DDR1_DQ13/DDR0_DQ29

DDR0_DQ3

DDR0_DQ5

DDR0_CAB9

DDR0_CAB8

DDR0_CAB6 DDR0_CAB7

DDR0_CAA1

DDR0_CAA0

DDR0_DQ2

DDR0_DQ0

DDR0_DQ4

DDR0_DQ6 DDR0_DQ7 DDR0_DQ8

DDR0_DQ10

DDR0_DQ15

DDR0_CKE0 DDR0_CKE1 DDR0_CKE2

DDR0_CKN1

DDR0_DQ9

DDR0_DQ11 DDR0_DQ12 DDR0_DQ13 DDR0_DQ14

DDR1_DQ0/DDR0_DQ16 DDR1_DQ1/DDR0_DQ17 DDR1_DQ2/DDR0_DQ18

DDR1_DQ4/DDR0_DQ20

DDR1_DQ3/DDR0_DQ19

DDR1_DQ5/DDR0_DQ21

DDR1_DQ7/DDR0_DQ23

DDR1_DQ6/DDR0_DQ22

DDR1_DQ8/DDR0_DQ24 DDR1_DQ9/DDR0_DQ25 DDR1_DQ10/DDR0_DQ26

DDR1_DQ12/DDR0_DQ28

DDR1_DQ11/DDR0_DQ27

DDR1_DQ14/DDR0_DQ30

DDR0_DQ17/DDR0_DQ33

DDR0_DQ16/DDR0_DQ32

DDR0_DQ20/DDR0_DQ36

DDR0_DQ19/DDR0_DQ35

DDR0_DQ18/DDR0_DQ34

DDR0_DQ22/DDR0_DQ38

DDR0_DQ21/DDR0_DQ37

DDR0_DQ23/DDR0_DQ39

DDR0_DQ25/DDR0_DQ41

DDR0_DQ24/DDR0_DQ40

DDR0_DQ27/DDR0_DQ43

DDR0_DQ30/DDR0_DQ46

DDR0_DQ29/DDR0_DQ45

DDR0_DQ31/DDR0_DQ47 DDR1_DQ16/DDR0_DQ48 DDR1_DQ17/DDR0_DQ49

DDR1_DQ19/DDR0_DQ51

DDR1_DQ18/DDR0_DQ50

DDR1_DQ20/DDR0_DQ52 DDR1_DQ21/DDR0_DQ53 DDR1_DQ22/DDR0_DQ54

DDR1_DQ24/DDR0_DQ56

DDR1_DQ23/DDR0_DQ55

DDR1_DQ25/DDR0_DQ57 DDR1_DQ26/DDR0_DQ58 DDR1_DQ27/DDR0_DQ59

DDR1_DQ29/DDR0_DQ61

DDR1_DQ28/DDR0_DQ60

DDR1_DQ30/DDR0_DQ62 DDR1_DQ31/DDR0_DQ63

DDR1_DQ15/DDR0_DQ31

DDR0_DQ28/DDR0_DQ44

DDR0_DQ26/DDR0_DQ42

DDR0_CKN0 DDR0_CKP0

DDR0_CKP1

DDR0_CKE3

DDR0_CS0*

DDR0_PAR

DDR_VREF_CA

DDR1_VREF_DQ

DDR0_VREF_DQ

DDR_VTT_CNTL

DDR0_ALERT*

DDR0_MA3 DDR0_MA4

DDR0_DQSP0

DDR0_DQSN0

DDR0_DQSP1

DDR0_DQSN1

DDR1_DQSN1/DDR0_DQSN3

DDR1_DQSP0/DDR0_DQSP2

DDR1_DQSN0/DDR0_DQSN2

DDR1_DQSP1/DDR0_DQSP3

DDR0_DQSN2/DDR0_DQSN4

DDR0_DQSP2/DDR0_DQSP4

DDR0_DQSP3/DDR0_DQSP5

DDR0_DQSN3/DDR0_DQSN5

DDR1_DQSN3/DDR0_DQSN7

DDR1_DQSP2/DDR0_DQSP6

DDR1_DQSN2/DDR0_DQSN6

DDR1_DQSP3/DDR0_DQSP7

OUT

NC

NCNC

OUT

BI

BI BI

BI

BI BI

BI

BI BI

plane to BGA pads

R0802.2:

R0800.2:

R0811.1:

VCCIO breakdown per 4/20/15 email from Srini

SKL-ULX current estimates from Skylake Processor EDS vol 1, doc #544924, v0.94

320mA Max

3.78A Max

be isolated from local

VCCIO & VCCIO_DDR must

2A Max

24A Max

NOTE: Aliases not used on CPU supply outputs to avoid any extraneous connections.

1nH trace filter

VCCSA & VCCSA_DDR must be isolated from VR output to BGA pads

1.75A Max

1.185A Max

VDDQC must implement

8 OF 130

<SCH_NUM>

8 OF 67

VOLTAGE=1.5V

11

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.2000

VOLTAGE=1.2V

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.2000

VOLTAGE=1.5V

11

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.2000

PPVCCG1_S0_CPU

PP1V2_S0_CPU_VDDQC

TP_MCP_DC_B64

TP_MCP_DC_A64 TP_MCP_DC_BP64

TP_MCP_DC_BN64

PP1V_S0SW

CPU_VCCSASENSE_N

CPU_VCCGTSENSE_P CPU_VCCGTSENSE_N

PPVCORE_S0_CPU

CPU_VCCIOSENSE_N

CPU_VCCIOSENSE_P

PP1V_S3

PPVCORE_S0_GT PPVCORE_S0_GT

PPVCCSA_S0

PPVCCIO_S0

PP1V_S3

PP1V2_S3 PPVCCIO_S0

PP1V2_S0SW

PPVCCG0_S0_CPU

CPU_VIDSOUT_R

CPU_VIDALERT_R_L

PPVCORE_S0_CPU

PP1V_S3

CPU_VCCSENSE_N

CPU_VCCSENSE_P

CPU_VIDALERT_L

CPU_VIDSOUT

CPU_VIDSCLK_R CPU_VIDSCLK

PP1V_S0SW

PPVCCSA_DDR_S0

CPU_VCCSASENSE_P

SYNC_DATE=05/11/2015SYNC_MASTER=DEVMLB

BOM_COST_GROUP=CPU & CHIPSET

CPU Power

42

2

1

R0861

PLACE_NEAR=U0500.R30:50.8mm

1/32W 01005

100

MF

5%

2

1

R0860

PLACE_NEAR=U0500.N30:50.8mm

1/32W 01005

100

MF

5%

2

1

R0840

PLACE_NEAR=U0500.AT26:50.8mm

1/32W 01005

100

MF

5%

2

1

R0841

PLACE_NEAR=U0500.AN24:50.8mm

1/32W 01005

100

MF

5%

47

2

1

C0850

BYPASS=U0500.BA39::0.59mm

10%

0201

X5R-CERM

10V

0.1UF

21

XW0850

SM

2

1

R0831

PLACE_NEAR=U0500.P52:50.8mm

1/32W 01005

100

MF

5%

2

1

R0830

PLACE_NEAR=U0500.N52:50.8mm

1/32W 01005

100

MF

5%

42

21

R0812

0

0201

MF

1/20W

5%

21

R0810

220

1% MF

1/20W

201

21

R0811

0

0201

PLACE_NEAR=U0500.A56:12.7mm

MF

1/20W

5%

2

1

R0800

56

PLACE_NEAR=U0500.B58:12.7mm

1% MF

1/20W

201

2

1

R0802

PLACE_NEAR=U0500.A58:12.7mm

100

1% MF

1/20W 201

42

2

1

R0821

PLACE_NEAR=U0500.L32:50.8mm

1/32W 01005

100

MF

5%

2

1

R0820

PLACE_NEAR=U0500.L34:50.8mm

1/32W 01005

100

MF

5%

42

N28

Y30

Y29

V29

T30

T29

M29

R29

N30

M31

L30

AT30

AT29

AR29

AN30

AN29

AL29

AK30

AK29

AH29

AF30

AF29

AE29

AC30

AC29

AA29

AR38

AR35

AN38

AN35

AL38

AL35

AK38

AK35

AH38

AH35

AF38

AF35

Y38

Y35

V38

V35

T38

T35

R38

R35

AC38

AC35

AA38

AA35

U0500

SKL-Y-ULX

BGA

CRITICAL

OMIT_TABLE

SKL-Y

AR24

BA39

BP64

BP58

BP56

BP50

BP48

BP42

BP40

BP34

BP32

BP26

BP24

BN64

BA51

BA49

BA47

BA45

BA43

BA41

BA37

BA35

BA33

BA31

BA29

BA27

BA25

AV64

AT64

AK64

AH64

T26

R26

Y26

V26

T27

R27

AF27

AE27

AT24

AW51

AW49

AW47

AW45

AW43

AW41

AW39

AW37

AW35

AW33

AW31

AW29

AW27

AV50

AV48

AV46

AV44

AV42

AV40

AV38

AV36

AV34

AV32

AV30

AV28

AV26

AT26

AR26

AN26

AL26

AK26

AH26

AF26

AF24

AE26

AE24

AE23

AC24

AC23

U0500

OMIT_TABLE

CRITICAL

SKL-Y-ULX

SKL-Y

BGA

P52

Y64

Y62

Y60

Y58

Y56

Y54

Y51

Y50

Y49

Y47

Y46

Y44

Y43

W63

W61

W59

W57

W55

W53

V64

V62

V60

V58

V56

V54

U63

U61

U59

U57

U55

U53

T54

T51

T50

T49

T47

T46

T44

T43

N52

R53

R51

N50

N48

N46

N44

AT51

AT50

AT49

AT47

AT46

AT44

AT43

AN51

AN50

AN49

AN47

AN46

AN44

AN43

AK51

AK50

AK49

AK47

AK46

AK44

AK43

AJ53

AG53

AF51

AF50

AF49

AF47

AF46

AF44

AF43

AE63

AE61

AE59

AE57

AE55

AE53

AD64

AD62

AD60

AD58

AD56

AD54

AC63

AC61

AC59

AC57

AC55

AC53

AC51

AC50

AC49

AC47

AC46

AC44

AC43

AB64

AB62

AB60

AB58

AB56

AB54

AA53

U0500

OMIT_TABLE

SKL-Y-ULX

CRITICAL

SKL-Y

BGA

B58

L32

A58

A56

AC26

AA26

Y41

Y32

V41

V32

T41

T32

L34

R63

R61

R59

R57

R41

R32

P64

P62

P60

P58

P56

N63

N61

N59

N57

N55

N54

N42

N40

N38

N36

N34

N32

M64

M62

M60

M58

M56

M53

M51

M49

M47

M45

M43

M41

M39

M37

M35

M33

L63

L54

L52

L50

L48

L46

L44

L42

L40

J64

H63

F64

D64

B64

AT41

AT40

AT38

AT36

AT35

AT33

AT32

AR41

AR32

AN41

AN32

AL41

AL32

AK41

AK32

AH41

AH32

AF41

AF32

AE41

AE40

AE38

AE36

AE35

AE33

AE32

AC41

AC32

AA41

AA32

A64

U0500

SKL-Y-ULX

OMIT_TABLE

CRITICAL

SKL-Y

BGA

63

61 50 12 8 6

61 43 34 11 8

61 50 42 31 15 12 8 6

61 44

34 12 8 61 44 34 12 8

61 43 11

61 47 11 8 5

61 50 42 31

15 12 8 6

61 50 47 22 21 20 12 61 47 11 8 5

61 50 12

61 43 34 11 8

61 50 42 31 15 12 8 6

63 61

50 12 8 6

61 43 11

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

OUT

OUT OUT

OUT

BI

OUT

IN

OUT

CPU POWER 4 OF 4

SYM 16 OF 20

VCCG0

VCCG0 VCCG0 VCCG0

VCCG1

VCCG0 VCCG1

VCCG0

VCCG1

VCCG1 VCCG1

VCCG1

VCCSA_SENSE

VCCSA_DDR

VCCSA

VCCSA VCCSA

VSSSA_SENSE

VCCSA_DDR

VCCSA VCCSA

VCCSA

VCCSA VCCSA

VCCSA

VCCSA VCCSA

VCCSA VCCSA VCCSA

VCCSA

CPU POWER 3 OF 4

SYM 15 OF 20

VDDQ

VCCIO

VCCIO_DDR

VSSIO_SENSE

VCCIO_SENSE

VCCIO_DDR

VCCIO

VCCIO VCCIO VCCIO

VCCIO VCCIO

VDDQ

VCCPLL VCCPLL

VCCPLL_OC VCCPLL_OC

VCCSTG VCCSTG

VCCST

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VDDQ VDDQ VDDQ VDDQ VDDQ

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQC

VDDQ

SYM 14 OF 20

CPU POWER 2 OF 4

VSSGT_SENSE

VCCGT_SENSE

VCCGT VCCGT

VCCGT

VCCGT VCCGT

VCCGT

VCCGT VCCGT

VCCGT

VCCGT VCCGT VCCGT VCCGT

VCCGT

VCCGT VCCGT VCCGT

VCCGT

VCCGT VCCGT VCCGT

VCCGT

VCCGT VCCGT VCCGT

VCCGT

VCCGT VCCGT VCCGT VCCGT

VCCGT

VCCGT VCCGT VCCGT

VCCGT

VCCGT VCCGT VCCGT

VCCGT

VCCGT VCCGT VCCGT

VCCGT

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

VCCGT

VCCGT VCCGT VCCGT

VCCGT

VCCGT VCCGT VCCGT

VCCGT

VCCGT VCCGT VCCGT

CPU POWER 1 OF 4

SYM 13 OF 20

VCCSTG VCCSTG

VIDALERT*

VIDSCK

VIDSOUT

VCC

VCC VCC VCC VCC

VCC

VCC_SENSE

VCC

VCC VCC

VCC

VCC VCC

VCC

VSS_SENSE

VCC VCC

VCC

VCC VCC

VCC

VCC VCC

VCC

VCC VCC VCC

VCCVCC

VCC

VCC VCC VCC VCC

VCC

VCC VCC

VCC

VCC VCC

VCC

VCC VCC

VCC

VCC VCC VCC VCC VCC VCC VCC VCC

VCC

VCC VCC

VCC

VCC VCC

VCC

VCC VCC VCC VCC

VCC

24mA Max

33/161mA @ 3.3/1.8V Max

6/3mA @ 3.3/1.8V Max

4/2mA @ 3.3/1.8V Max

6/2mA @ 3.3/1.8V Max

8/3mA @ 3.3/1.8V Max

20/9mA @ 3.3/1.8V Max

Must not exceed

35mA Max

<1mA Max

6mA Max

1mA Max

29mA Max

33mA Max

10mA Max

41/56mA @ 3.3/1.8V Max

68/36/33mA @ 3.3/1.8/1.5V Max

Project specific (X260 TBD)

1.1A Max

370mA Max

See EDS Table 10-5

168mA Max

88mA Max

71mA Max

22mA Max

26mA Max

55mA Max

74mA Max

11/7mA @ 3.3/1.8V Max

0.565A Max

33mA Max

VCCAMPHYPLL_1P0 and VCCPRIM_1P0 / VCCPRIM_3P3 breakdowns from Srini email 4/13/15

SPT-LP current estimates from Sunrise Point-LP PCH EDS vol 1, doc #545659, v1.2. NOTE: Aliases not used on CPU supply outputs

to avoid any extraneous connections.

3.2V max

4mA Max

9 OF 67

9 OF 130

<SCH_NUM>

VOLTAGE=1.0V

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000

VOLTAGE=1.0V

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000

PP1V_SUS

PP1V_SUS_PCH_VCCCLK4

PP1V_SUS_PCH_VCCCLK5

PP1V_SUSSW_HSIO

PP1V_SUS

PP1V_S5_PCH_DCPDSW

PP1V8_SUS

PP3V3_SUS

PPVRTC_G3H

PP1V_SUSSW_HSIO

PP1V_SUS

PP3V3_SUS

PP1V_SUSSW_HSIO

PP3V3_SUS

PP3V3_S5

PP1V_SUS_PCH_VCCAPLL

PP3V3R1V8R1V5_S0_PCH_VCCHDA

PP1V_SUSSW_PCH_VCCAMPHYPLL

PP1V_SUS

PP1V_SUS_PCH_VCCCLK3

PP3V3_SUS

PP1V_SUS

TP_PCH_CORE_VID<1>

TP_PCH_CORE_VID<0>

PPVCORE_SUS_PCH

PP1V_SUS

PP3V3_SUS

PP1V8_SUS

PP3V3_SUS

PPVOUT_S0_PCH_DCPRTC

SYNC_DATE=05/11/2015SYNC_MASTER=DEVMLB

BOM_COST_GROUP=CPU & CHIPSET

PCH Power

2

1

C0901

BYPASS=U0500.AR19::2.10mm

X5R 0201-1

1.0UF

6.3V

20%

2

1

C0900

BYPASS=U0500.AT19::2.10mm

0.1UF

10V

10%

X5R-CERM

0201

2

1

C0910

BYPASS=U0500.AT18::1.08mm

0.1UF

10V

10% X5R-CERM

0201

V16

V15

R16

R15

AR23

AN23

AL23

AK23

AA23

AA21

AV15

AT15

AL19

AK19

AT19

AR19

AT16

AR16

AF19

AF18

AE19

AE18

AK21

AH21

AD1

AC2

AT21

AR21

AL18

AK18

AH19

AH18

AH15

AH13

AA16

AA15

AP13

AN15

AP1

AN2

AB1

AA2

AG2

AF1

AJ2

AH1

AW2

AV1

AU2

AT1

U2

T16

T15

T1

W2

V1

AV22

AT23

AM13

AL15

T19

R19

R23

R21

Y21

V21

Y23

V23

Y19

V19

Y18

V18

AE16

AE15

AA19

AA18

BB12

BA13

AV18

AT18

AM1

AL2

U0500

SKL-Y-ULX

CRITICAL

OMIT_TABLE

SKL-Y

BGA

2

1

C0920

BYPASS=U0500.AL2::5.32mm

X5R

0201-1

1.0UF

6.3V

20%

61 50 48 19 16 13 9

13

61 50 13 9

61 50 48 19

16 13 9

61 50 48 33 24 17 13 9

61 50 49 46 36 17 16 14 13 9

61 46 16 15

61 50 13 9

61 50 48 19 16 13 9

61 50 49 46 36 17 16 14 13 9

61 50 13 9

61 50 49 46 36 17 16 14 13 9

67 61

60 59 50 49 48 46 45 18 15 13

13

61 50 48 19 16 13 9

61

50 48 19

16 13 9

13

61 50 49 46 36 17 16 14 13 9

61 50 48 19 16 13 9

61 48

61 50 48 19 16 13 9

61 50 49 46 36 17 16 14 13 9

61 50 48 33 24 17 13 9

61 50 49 46 36 17 16 14 13 9

61 50 49 46 36 17 16 14

13 9

61 50 49 46 36 17 16 14 13 9

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

PCH POWER

SYM 17 OF 20

DCPRTC

VCCCLK1 VCCCLK1

VCCCLK2 VCCCLK2

VCCCLK3 VCCCLK3

GPP_B0/CORE_VID0 GPP_B1/CORE_VID1

VCCCLK4

VCCCLK5

VCCCLK6 VCCCLK6

VCCPGPPA

VCCPRIM_3P3 VCCPRIM_3P3

VCCPGPPA

VCCPGPPC

VCCPGPPB

VCCPGPPD

VCCPGPPG

VCCPGPPF

VCCPGPPE

VCCPGPPD

VCCPRIM_1P0

VCCRTCPRIM_3P3

VCCPRIM_1P0

VCCRTCPRIM_3P3

VCCRTC

VCCATS

VCCRTC DCPRTC

VCCAMPHYPLL_1P0

VCCMPHYGT_1P0

VCCMPHYAON_1P0 VCCMPHYGT_1P0

VCCMPHYGT_1P0

VCCAPLL_1P0 VCCAPLL_1P0

VCCPRIM_1P0

VCCPRIM_3P3 VCCPRIM_1P0

VCCPRIM_3P3

VCCSRAM_1P0

VCCSRAM_1P0 VCCSRAM_1P0

VCCSPI

VCCHDA

VCCDSW_3P3

VCCPRIM_1P0 VCCPRIM_1P0

VCCPRIM_1P0

VCCPRIM_CORE

VCCPRIM_CORE VCCPRIM_CORE VCCPRIM_CORE VCCPRIM_CORE

DCPDSW_1P0 DCPDSW_1P0

VCCMPHYAON_1P0

VCCMPHYGT_1P0

VCCAPLLEBB_1P0 VCCAPLLEBB_1P0

<SCH_NUM>

10 OF 130

10 OF 67

TP_MCP_DC_D1

TP_MCP_DC_A5

TP_MCP_DC_BP62

TP_MCP_DC_BP1

SYNC_DATE=04/14/2015SYNC_MASTER=DEVMLB

CPU & PCH Grounds

BOM_COST_GROUP=CPU & CHIPSET

Y27

Y13

Y11

Y5

Y3

V49

V47

V40

V36

V13

T58

T56

T24

T23

R47

R46

R36

R18

R8

R6

R4

R2

P54

N26

N18

N16

L59

L57

K51

K49

K41

K39

K31

K29

K21

K19

J62

J7

G14

F62

E52

E50

E42

E40

E32

E30

E22

E20

D62

D8

D1

C40

C14

BP62

BP52

BP46

BP30

BP28

BP1

BN29

BM38

BM14

BM11

BL33

BL31

BK38

BK20

BH59

BH56

BH48

BH46

BH38

BH36

BH26

BH24

BG63

BG17

BG15

BG6

BF38

BF20

BE31

BE29

BD38

BD20

BB59

BB54

BB46

BB44

BB36

BB34

BB26

BB24

BA64

BA11

AY48

AY40

AY38

AY28

AW23

AV52

AU61

AT54

AR51

AR44

AR33

AR15

AN59

AN24

AM64

AL50

AL43

AL27

AK33

AK15

AK7

AH54

AH46

AH36

AH33

AH23

AH16

AF60

AF58

AF36

AF33

AF15

AE49

AE4

AD13

AC21

AB13

AA55

AA46

AA33

A5

U0500

BGA

SKL-Y

OMIT_TABLE

SKL-Y-ULX

CRITICAL

Y40

Y36

Y24

Y16

Y7

Y1

V51

V46

V44

V33

V30

T64

T62

T40

T36

T21

T18

R55

R50

R44

R43

R33

R30

N24

N22

N14

M3

L14

K55

K47

K45

K37

K35

K27

K25

K17

K15

J5

J3

E59

E56

E48

E46

E38

E36

E28

E26

E18

E16

D6

BP60

BP44

BP38

BP22

BN6

BM20

BM18

BL47

BL29

BL8

BL1

BJ62

BJ47

BH54

BH52

BH44

BH42

BH34

BH32

BH22

BH20

BG12 BG4

BE47

BE12 BC47

BB52

BB42

BB32

BB22 BA58

BA3

BA1

AY50

AY46

AY36

AY30

AY26

AW25

AW21

AV54

AV24

AU63

AU59

AU53

AT27

AR59

AR50

AR46

AR43

AR36

AR30

AR18

AR12

AP54

AN40

AN21

AM54

AL49

AL40

AL24

AK54

AK13

AK3

AH51

AH44

AH30

AG59

AF56

AF23

AF13

AE47

AE46

AE30

AE21

AE8

AC40

AC36

AC19

AC18

AA63

AA61

AA51

AA50

AA44

AA43

AA30

AA27

U0500

BGA

SKL-Y

CRITICAL

SKL-Y-ULX

OMIT_TABLE

Y33

Y15

Y9

V50

V43

V27

V24

T60

T33

T13

R49

R40

R24

R10

N20

L61

K53

K43

K33

K23

J14

J9

E54

E44

E34

E24

E14

D10

BP54

BP36

BM16

BL35

BK56

BJ29

BH50

BH40

BH28

BG29

BG8

BG2

BF59

BF56

BE35

BE33

BD63

BD56

BC29

BC17

BB50

BB48

BB40

BB38

BB30

BB28

BB20

BA53

BA9

BA7

BA5

AY52

AY44

AY42

AY34

AY32

AY24

AY16

AW19

AW17

AV20

AV16

AU57

AU55

AR49

AR47

AR40

AR27

AR10

AR8

AR6

AR4

AR2

AP64

AN36

AN33

AN27

AN19

AN18

AN16

AL59

AL53

AL51

AL47

AL46

AL44

AL36

AL33

AL30

AL21

AL16

AK40

AK36

AK27

AK24

AK16

AK11

AK9

AK5

AK1

AJ59

AH50

AH49

AH47

AH43

AH40

AH27

AH24

AF64

AF62

AF54

AF40

AF21

AF16

AE51

AE50

AE44

AE43

AE10

AE2

AC33

AC27

AC16

AC15

AA59

AA57

AA49

AA47

AA40

AA36

AA24

A14

U0500

BGA

SKL-Y

CRITICAL

OMIT_TABLE

SKL-Y-ULX

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

GND 3 OF 3

SYM 20 OF 20

VSS

VSS VSS VSS VSS

VSS

VSS VSS

VSS VSS VSS

VSS

VSS VSS VSS VSS

VSS

VSS VSS VSS VSS

VSS

VSS VSS VSS

VSS

VSS VSS VSS VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS VSS

VSS VSS

VSS

VSS VSS VSS VSS

VSS

VSS VSS

VSS

SYM 19 OF 20

GND 2 OF 3

VSS

VSS VSS VSS

VSS

VSS VSS VSS VSS

VSS

VSS VSS VSS

VSS

VSS VSS VSS VSS VSS VSS

VSS VSS

VSS

VSS VSS VSS VSS VSS VSS VSS VSS

VSS

GND 1 OF 3

SYM 18 OF 20

VSS

VSS VSS VSS VSS

VSS

VSS VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS

VSS

VSS VSS

VSS

VSS VSS VSS

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

CPU VCORE G0 Decoupling

All Intel recommendations from Intel doc #543016 Skylake U and Y Platform Design Guide Rev 1.3 unless stated otherwise Intel's placeholders are no longer required per 4/20/15 email from Srini

CPU VCORE Decoupling

Intel recommendation (Table 52-2): 20x 0.1uF 0201 STUFF, 8x 10uF 0402, 6x 47uF 6.3V 0805 STUFF (2x NO STUFF) Apple implementation : 20x 0.1uF 0201 STUFF (6x NO STUFF), 16x 20uF 0402, 3x 270uF 2V B2

Intel recommendation (Table 52-2): 13X 0.1UF 0201 STUFF (10x NO STUFF), 1x 1uF 0402, 1x 22uF 0805

Apple implementation : 12x 0.1uF 0201

CPU VCCSA DDR Decoupling

CPU VCCSA Decoupling

Intel recommendation (Table 52-2): 12x 0.1uF 0201

Intel recommendation (Table 52-2): 1x 1uF 0201, 4x 22uF 0603 Apple implementation : 1x 1uF 0201, 5x 0.1uF NO STUFF, 5x 20uF 0402, 1x 270uF 2V B2

Intel recommendation (Table 52-2): 1x 0.1uF 0201 STUFF, 1x 22uF 0603 Apple implementation : 1x 0.1uF 0201 STUFF, 1x 20uF 0402

Apple implementation : 13x 0.1uF 0201 STUFF (10x NO STUFF), 1x 1uF 0201, 1x 20uF 0402

CPU VCCIO Decoupling

Intel recommendation (Table 52-2): 12x 0.1uF 0201

Apple implementation : 12x 0.1uF 0201

CPU VCORE G1 Decoupling

11 OF 67

11 OF 130

<SCH_NUM>

PPVCCSA_DDR_S0

PPVCCIO_S0

PPVCCG1_S0_CPU

PPVCCSA_S0

PPVCORE_S0_CPU

PPVCCG0_S0_CPU

SYNC_DATE=04/14/2015SYNC_MASTER=DEVMLB

CPU Decoupling 1

BOM_COST_GROUP=CPU & CHIPSET

CAP,AL,POLY,220UF,20%,2V

C1130,C11312 CRITICAL128S00041

12PF

5% 25V NP0-C0G 0201

1

2

C1132

NP0-C0G

25V

5%

0201

1

2

C1133

12PF

3 2

1

C1130

2.0V

220UF

POLY-TANT

20%

OMIT_TABLE

D15T-D1L-COMBO

3 2

1

D15T-D1L-COMBO

POLY-TANT

220UF

2.0V

20%

OMIT_TABLE

C1131

2

1

0402

CRITICAL

C118F

20% 4V X6S

10UF

20%

CRITICAL

X6S-CERM 0402

2.5V

1

2

20UF

C112C

20%

2.5V

20UF

CRITICAL

C112D

1

2

X6S-CERM 0402

20%

CRITICAL

2.5V X6S-CERM

20UF

C112E

1

2

0402

20%

2.5V X6S-CERM

20UF

C112F

1

2

0402

NO STUFF

20%

2

1

C1178

X6S-CERM

20UF

2.5V 0402

CRITICAL

2

1

C1197

0402

CRITICAL

20% 4V X6S

10UF

1

C118D

0402

CRITICAL

20%

10UF

2

4V X6S

2

1

0402

20% 4V X6S

10UF

NO STUFF

C118E

2

1

C118C

0402

20% 4V X6S

10UF

CRITICAL CRITICAL

20%

2.5V

C1190

TANT-POLY

120UF

CASE-B2-SM

2

1

2

1

0402

20% 4V X6S

10UF

C118B

NO STUFF

20%

2.5V X6S-CERM 0402

20UF

C1128

1

2

NO STUFF

20%

2.5V X6S-CERM 0402

20UF

C1129

1

2

NO STUFF

20%

CRITICAL

2.5V X6S-CERM 0402

20UF

C112A

1

2

20%

CRITICAL

2.5V X6S-CERM 0402

20UF

C112B

1

2

0201

6.3V

0.1UF

CERM-X5R

10%

NO STUFF

C1114

1

2

0201

6.3V CERM-X5R

0.1UF

NO STUFF

10%

C1115

1

2

20%

CRITICAL

2.5V X6S-CERM 0402

20UF

C1127

1

2

20%

CRITICAL

2.5V X6S-CERM 0402

20UF

C1126

1

2

20%

2.5V X6S-CERM 0402

20UF

C1125

1

2

NO STUFF

20%

CRITICAL

2.5V X6S-CERM 0402

20UF

C1124

1

2

20%

CRITICAL

X6S-CERM 0402

20UF

2.5V

1

2

C1123

20%

2.5V X6S-CERM 0402

20UF

1

2

C1122

CRITICAL

20%

CRITICAL

X6S-CERM 0402

20UF

2.5V

C1121

1

2

20%

CRITICAL

2.5V

20UF

0402

C1120

1

2

X6S-CERM

0201

6.3V CERM-X5R

10%

C1100

1

2

0.1UF

0201

6.3V CERM-X5R

10%

0.1UF

C1101

1

2

0201

6.3V CERM-X5R

10%

0.1UF

C1102

1

2

0201

6.3V

0.1UF

C1103

1

2

CERM-X5R

10%

0201

6.3V

10% CERM-X5R

0.1UF

C1104

1

2

0201

6.3V

0.1UF

10%

C1105

1

2

CERM-X5R

6.3V

10%

0.1UF

CERM-X5R

1

2

0201

C1106

0201

0.1UF

CERM-X5R

10%

C1107

1

2

6.3V

NO STUFF

0201

6.3V

0.1UF

CERM-X5R

10%

C1119

1

2

0201

6.3V

0.1UF

CERM-X5R

10%

NO STUFF

1

2

C1118

0201

6.3V CERM-X5R

NO STUFF

10%

0.1UF

C1117

1

2

0201

6.3V

10% CERM-X5R

0.1UF

NO STUFF

C1116

1

2

0201

6.3V

10% CERM-X5R

0.1UF

C110E

1

2

0201

6.3V

10% CERM-X5R

0.1UF

C110F

1

2

0201

6.3V

10% CERM-X5R

0.1UF

C1110

1

2

0201

6.3V

10%

0.1UF

CERM-X5R

C1111

1

2

0201

6.3V

0.1UF

CERM-X5R

10%

C1112

1

2

0201

6.3V CERM-X5R

0.1UF

10%

C1113

1

2

0201

0.1UF

C110D

1

2

10%

6.3V CERM-X5R

0201

6.3V

10% CERM-X5R

0.1UF

C110C

1

2

0201

6.3V

10% CERM-X5R

0.1UF

C110B

1

2

0201

6.3V

10% CERM-X5R

0.1UF

C110A

1

2

0201

6.3V

10%

0.1UF

CERM-X5R

C1109

2

1

6.3V

10%

0.1UF

C1108

1

0201

CERM-X5R

2

0201

6.3V

10%

0.1UF

CERM-X5R

C1195

1

2

20%

6.3V

1.0UF

0201-1

C118A

1

2

X5R

0201

6.3V

0.1UF

10% CERM-X5R

NO STUFF

C1180

1

2

0201

6.3V CERM-X5R

10%

0.1UF

NO STUFF

C1181

1

2

0201

6.3V

0.1UF

10%

NO STUFF

CERM-X5R

C1182

1

2

0201

6.3V

0.1UF

10% CERM-X5R

NO STUFF

C1183

1

2

0201

6.3V

NO STUFF

CERM-X5R

0.1UF

10%

C1184

1

2

20%

6.3V

1.0UF

0201-1

X5R

2

1

C1177

0201

6.3V

C116A

0.1UF

10% CERM-X5R

1

2

0201

6.3V CERM-X5R

10%

0.1UF

C116B

1

2

0201

6.3V CERM-X5R

10%

0.1UF

C116C

1

2

0201

6.3V

0.1UF

10% CERM-X5R

C1160

1

2

0201

6.3V CERM-X5R

0.1UF

10%

C1161

1

2

0201

6.3V

0.1UF

CERM-X5R

10%

C1162

1

2

0201

6.3V

10%

0.1UF

CERM-X5R

1

2

C1163

0201

6.3V

0.1UF

10% CERM-X5R

C1164

1

2

0201

6.3V

C1165

CERM-X5R

0.1UF

10%

1

2

0201

6.3V CERM-X5R

0.1UF

10%

C1166

1

2

0201

6.3V CERM-X5R

10%

1

2

C1167

0.1UF

0201

6.3V

0.1UF

10%

C1168

1

2

CERM-X5R

0201

6.3V

10%

1

2

C1169

0.1UF

CERM-X5R

0201

6.3V

10%

0.1UF

C1150

1

2

CERM-X5R

0201

6.3V

10%

0.1UF

CERM-X5R

C1151

1

2

0201

6.3V

10%

0.1UF

CERM-X5R

C1152

1

2

0201

6.3V CERM-X5R

10%

0.1UF

C1153

1

2

0201

6.3V CERM-X5R

10%

0.1UF

C1154

1

2

0201

0.1UF

10% CERM-X5R

C1155

1

2

6.3V 0201

6.3V

0.1UF

10% CERM-X5R

C1156

1

2

0201

6.3V

0.1UF

10% CERM-X5R

C1157

1

2

0201

6.3V

0.1UF

10% CERM-X5R

C1158

1

2

0201

6.3V CERM-X5R

0.1UF

10%

1

2

C1159

0201

6.3V

10%

0.1UF

CERM-X5R

C115A

1

2

0201

6.3V

10%

0.1UF

CERM-X5R

1

2

C115B

0201

6.3V

0.1UF

CERM-X5R

10%

C114A

1

2

0201

6.3V

10%

0.1UF

CERM-X5R

1

2

C114B

0201

6.3V CERM-X5R

C1140

1

2

0.1UF

10%

0201

6.3V

10%

0.1UF

C1141

1

2

CERM-X5R

0201

6.3V

10%

0.1UF

CERM-X5R

C1142

1

2

0201

6.3V

10%

0.1UF

CERM-X5R

C1143

1

2

0201

6.3V

10% CERM-X5R

0.1UF

C1144

1

2

0201

6.3V

0.1UF

10% CERM-X5R

C1145

1

2

0201

6.3V

0.1UF

10%

C1146

1

2

CERM-X5R

0201

6.3V

0.1UF

10% CERM-X5R

1

2

C1147

0201

6.3V

10%

1

2

CERM-X5R

0.1UF

C1148

0201

6.3V CERM-X5R

0.1UF

10%

C1149

1

2

61 43 8

61 47 8 5

8

61 43 8

61 43 34 8

8

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

Apple implementation : 12x 0.1uF 0201 STUFF (20x NO STUFF), 2x 1uF 0201, 16x 20uF 0402, 2x 270uF 2V B2

Intel recommendation (Table 52-2): 12x 0.1uF 0201 STUFF, 2x 1uF 0402, 2x 10uF 0402 NO STUFF, 9x 47uF 6.3V 0805

NOTE:

for power/ground via pair.

with worst case stackup and 500pH added

Bypass calcs based on 0.1mm trace width

CPU VCCPLL_OC BYPASS

Intel recommendation (Table 52-2): 18x 0.1uF 0201

CPU VDDQ DECOUPLING

CPU GT Decoupling

(CPU 1.0V SUSTAIN PWR)

CPU VCCST BYPASS

CPU VCCSTG BYPASS

(CPU 1.2V PLL PWR)

CPU VCCPLL BYPASS (CPU 1.0V DIGITAL PLL PWR)

(CPU 1.0V SUSTAIN GATED PWR)

Apple implementation : 18x 0.1uF 0201

All Intel recommendations from Intel doc #543016 Skylake U and Y Platform Design Guide Rev 1.3 unless stated otherwise Intel's placeholders are no longer required per 4/20/15 email from Srini

12 OF 130

<SCH_NUM>

12 OF 67

PPVCORE_S0_GT

PP1V_S3

PP1V_S0SW

PP1V_S3

PP1V2_S0SW

PP1V2_S3

SYNC_DATE=05/06/2015SYNC_MASTER=DEVMLB

CPU Decoupling 2

BOM_COST_GROUP=CPU & CHIPSET

NO STUFF

2

1

C1260

2.5V X6S-CERM 0402

20UF

20%

2

1

C1261

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C1262

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

NO STUFF

2

1

C1263

2.5V X6S-CERM 0402

20UF

20%

NO STUFF

2

1

C125F

2.5V X6S-CERM 0402

20UF

20%

2

1

C125E

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C125D

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C125C

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C125B

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C125A

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C1259

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C1258

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C1257

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C1256

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C1255

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

NO STUFF

2

1

C1254

2.5V X6S-CERM 0402

20UF

20%

2

1

C1220

CERM-X5R

NO STUFF

10%

0.1UF

6.3V 0201

2

1

C1221

NO STUFF

0.1UF

10% CERM-X5R

6.3V 0201

C1265

270UF

2V

CRITICAL

TANT CASE-B2-SM

2

1

20%

C1264

270UF

2V TANT

CRITICAL

CASE-B2-SM

2

1

20%

C1253

2

1

X5R 0201-1

1.0UF

6.3V

20%

1.0UF

2

1

C1252

X5R 0201-1

6.3V

20%

2

1

10%

0.1UF

CERM-X5R

C1222

NO STUFF

6.3V 0201

2

1

C1223

0.1UF

NO STUFF

CERM-X5R

10%

6.3V 0201

2

1

NO STUFF

10% CERM-X5R

0.1UF

C1224

6.3V 0201

2

1

C1225

10% CERM-X5R

NO STUFF

0.1UF

6.3V 0201

2

1

C1226

0.1UF

10% CERM-X5R

NO STUFF

6.3V 0201

2

1

C1227

10% CERM-X5R

0.1UF

NO STUFF

6.3V

0201

2

1

C1228

0.1UF

CERM-X5R

10%

NO STUFF

6.3V 0201

NO STUFF

2

1

C1229

0.1UF

CERM-X5R

10%

6.3V 0201

6.3V

2

1

C1230

10% CERM-X5R

NO STUFF

0.1UF

0201

NO STUFF

C1231

CERM-X5R

2

1

10%

0.1UF

6.3V 0201

2

1

C1219

CERM-X5R

10%

0.1UF

NO STUFF

6.3V 0201

2

1

C1218

0.1UF

10% CERM-X5R

NO STUFF

6.3V 0201

2

1

C1217

10% CERM-X5R

0.1UF

NO STUFF

6.3V 0201

2

1

C1216

NO STUFF

10% CERM-X5R

0.1UF

6.3V 0201

2

1

C1215

NO STUFF

10% CERM-X5R

0.1UF

6.3V 0201

2

1

C1214

NO STUFF

10% CERM-X5R

0.1UF

6.3V 0201

2

1

C1213

CERM-X5R

NO STUFF

10%

0.1UF

6.3V 0201

2

1

C1212

10% CERM-X5R

0.1UF

NO STUFF

6.3V 0201

2

1

C1211

10% CERM-X5R

0.1UF

6.3V 0201

2

1

C1210

10% CERM-X5R

0.1UF

6.3V 0201

2

1

C1209

10% CERM-X5R

0.1UF

6.3V 0201

2

1

C1208

10% CERM-X5R

0.1UF

6.3V 0201

2

1

C1207

0.1UF

CERM-X5R

10%

6.3V 0201

2

1

C1206

0.1UF

CERM-X5R

10%

6.3V 0201

2

1

C1205

0.1UF

CERM-X5R

10%

6.3V

0201

2

1

C1204

CERM-X5R

10%

0.1UF

6.3V 0201

2

1

C1203

0.1UF

CERM-X5R

10%

6.3V 0201

2

1

C1202

0.1UF

CERM-X5R

10%

6.3V 0201

2

1

C1201

0.1UF

10% CERM-X5R

6.3V 0201

2

1

C1200

CERM-X5R

10%

0.1UF

6.3V 0201

2

1

C1296

BYPASS=U0500.R27::1.99mm

10%

0.1UF

X6S

6.3V 0201

2

1

C1294

BYPASS=U0500.AE27::2.07mm

X6S

0.1UF

10%

6.3V 0201

2

1

C1292

BYPASS=U0500.R26::4.20mm

X6S

10%

0.1UF

6.3V 0201

2

1

C1290

BYPASS=U0500.V26::2.38mm

10% X6S

0.1UF

6.3V 0201

2

1

C1280

CERM-X5R

0.1UF

10%

6.3V 0201

2

1

C1281

0.1UF

CERM-X5R

10%

6.3V 0201

2

1

C1282

10% CERM-X5R

0.1UF

6.3V 0201

2

1

C1283

CERM-X5R

0.1UF

10%

6.3V 0201

2

1

C1284

CERM-X5R

0.1UF

10%

6.3V 0201

2

1

C1285

CERM-X5R

10%

0.1UF

6.3V

0201

2

1

C1286

CERM-X5R

0.1UF

10%

6.3V 0201

2

1

C1287

CERM-X5R

0.1UF

10%

6.3V 0201

2

1

C1277

10%

0.1UF

CERM-X5R

6.3V 0201

C1278

2

1

10%

0.1UF

CERM-X5R

6.3V 0201

2

1

C1279

10%

0.1UF

CERM-X5R

6.3V 0201

2

1

C1274

10%

0.1UF

CERM-X5R

6.3V 0201

2

1

C1275

10%

0.1UF

CERM-X5R

6.3V

0201

2

1

C1276

10%

0.1UF

CERM-X5R

6.3V 0201

2

1

C1273

10%

0.1UF

CERM-X5R

6.3V 0201

2

1

C1272

10%

0.1UF

CERM-X5R

6.3V 0201

2

1

C1271

10% CERM-X5R

0.1UF

6.3V 0201

2

1

C1270

0.1UF

10% CERM-X5R

6.3V 0201

61 44 34 8

61 50

42 31 15 12 8 6

63 61 50 8 6

61 50

42 31 15 12 8 6

61 50 8

61

50 47 22 21 20 8

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

(PCH 1.0V CLOCK 3 PWR)

PCH VCCCLK3 FILTER/BYPASS

PCH VCCRTCPRIM BYPASS

(PCH 3.3V DSW PWR) (PCH 1.8V THERMAL PWR)

PCH VCCATS BYPASS

(PCH 1.0V APLL EBB PWR)

PCH VCCAPLLEBB BYPASS

(PCH 1.0V USB PWR)

PCH VCCMPHYGT_1P0 BYPASS

PCH VCCPRIM_1P0 BYPASS

(PCH 1.0V MPHY GATED PWR)(PCH 1.0V MPHY ALWAYS ON PWR)

PCH VCCMPHYAON_1P0 BYPASS

PCH VCCDSW_3P3 BYPASS

(PCH 1.0V CLOCK 4 PWR)

(PCH 1.0V CLOCK 5 PWR)

PCH VCCCLK4 FILTER/BYPASS

PCH VCCAMPHYPLL_1P0 FILTER/BYPASS (PCH 1.0V USB3/PCIE/SATA/MIPI PLL PWR)

(PCH 3.3V/1.8V GPIO GROUP E PWR)

PCH VCCCLK5 FILTER/BYPASS

PCH VCCPGPPE BYPASS

(PCH 3.3V/1.8V/1.5V HDA PWR)

PCH VCCHDA FILTER/BYPASS

PCH VCCAPLL FILTER/BYPASS (PCH 1.0V APLL PWR)

(PCH 3.3V/1.8V SPI PWR)

PCH VCCSPI BYPASS

(PCH 3.3V SUSPEND RTC PWR)

<SCH_NUM>

13 OF 130

13 OF 67

VOLTAGE=1.5V

9

MIN_NECK_WIDTH=0.0700

MIN_LINE_WIDTH=0.0950

VOLTAGE=1.0V

9

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000

VOLTAGE=1.0V

9

MIN_NECK_WIDTH=0.1000

MIN_LINE_WIDTH=0.2000

VOLTAGE=1.0V

9

MIN_NECK_WIDTH=0.1000

MIN_LINE_WIDTH=0.2000

VOLTAGE=1.0V

9

MIN_NECK_WIDTH=0.0700

MIN_LINE_WIDTH=0.0950

VOLTAGE=1.0V

9

MIN_NECK_WIDTH=0.0700

MIN_LINE_WIDTH=0.0950

PP1V_SUS_PCH_VCCCLK3

PP1V_SUS_PCH_VCCAPLL

PP1V_SUS

PP1V_SUS_PCH_VCCCLK5

PP1V_SUS

PP1V_SUS_PCH_VCCCLK4

PP1V_SUS

PP1V_SUSSW_PCH_VCCAMPHYPLL

PP3V3R1V8R1V5_S0_PCH_VCCHDA

PP1V_SUSSW_HSIO

PP1V_SUS

PP1V5_S0

PP3V3_SUS

PP3V3_S5

PP1V_SUS

PP1V_SUSSW_HSIOPP1V_SUSSW_HSIO

PP1V8_SUS

PP3V3_SUS

SYNC_DATE=05/11/2015SYNC_MASTER=DEVMLB

PCH Decoupling

BOM_COST_GROUP=CPU & CHIPSET

BYPASS=U0500.AK19::1.68mm

2

1

C1306

X5R

0201-1

1.0UF

6.3V

20%

1 2

402

R1390

0

5% 1/16W MF-LF

1 2

402

R1385

1/16W MF-LF

5%

0

1 2

402

R1380

1/16W MF-LF

5%

0

BYPASS=U0500.AT23::1.23mm

X6S

10%

0.1UF

C1309

1

2

6.3V 0201

220-OHM-0.7A-0.28-OHM

L1395

0402-1

1 2

BYPASS=U0500.AA18::1.23mm

1

C1395

2

0.1UF

X6S

10%

6.3V 0201

220-OHM-0.7A-0.28-OHM

L1309

0402-1

1 2

2

1

C1390

20UF

0402

CERM-X5R

NOSTUFF

BYPASS=U0500.R21::10.17mm

6.3V

20%

BYPASS=U0500.R21::10.17mm

CERM-X5R

20UF

NOSTUFF

2

1

C1391

0402

6.3V

20%

BYPASS=U0500.R21::0.92mm

10%

2

1

C1392

0.1UF

X6S

6.3V 0201

2

1

C1385

BYPASS=U0500.V21::10.17mm

CERM-X5R

20UF

0402

NOSTUFF

6.3V

20%

BYPASS=U0500.V21::10.17mm

2

1

C1386

NOSTUFF

CERM-X5R

0402

20UF

6.3V

20%

2

1

C1380

BYPASS=U0500.V19::10.17mm

NOSTUFF

20UF

0402

CERM-X5R

6.3V

20%

2

1

C1381

NOSTUFF

20UF

CERM-X5R

0402

BYPASS=U0500.V19::10.17mm

6.3V

20%

1/16W

402

MF-LF

5%

0

R1370

1 2

2

1

C1372

NOSTUFF

0.1UF

10% X6S

BYPASS=U0500.V15::3.91mm

6.3V 0201

2

1

C1344

10% X6S

0.1UF

BYPASS=U0500.R15::1.54mm

6.3V 0201

2

1

C1348

20UF

0402

CERM-X5R

BYPASS=U0500.T15::4.18mm

6.3V

20%

2

1

C1347

BYPASS=U0500.T15::4.18mm

X5R 0201-1

1.0UF

6.3V

20%

2

1

C1346

0.1UF

X6S

10%

BYPASS=U0500.T15::3.07mm

6.3V 0201

2

1

C1336

10% X6S

0.1UF

BYPASS=U0500.AH13::1.39mm

6.3V 0201

0.1UF

2

1

C1340

X6S

10%

BYPASS=U0500.V1::1.68mm

6.3V 0201

2

1

C1330

BYPASS=U0500.AE15::1.76mm

X5R

0201-1

1.0UF

6.3V

20%

BYPASS=U0500.AA2::0.84mm

0.1UF

10%

2

1

C1318

X6S

6.3V 0201

2

1

C1307

X6S

0.1UF

10%

BYPASS=U0500.AK19::1.68mm

6.3V 0201

2

1

0.1UF

BYPASS=U0500.AT15::2.38mm

10% X6S

C1302

6.3V 0201

2

1

C1300

BYPASS=U0500.AL15::1.96mm

X6S

10%

0.1UF

6.3V 0201

NOSTUFF

0402

2

1

C1371

20UF

CERM-X5R

BYPASS=U0500.V15::12.82mm

6.3V

20%

NOSTUFF

C1370

2

1

20UF

0402

BYPASS=U0500.V15::12.82mm

CERM-X5R

6.3V

20%

61 50 48 19 16 13 9

61 50 48

19 16 13 9

61 50 48 19 16 13 9

61 50 13 9

61 50 48 19 16 13 9

61 49 46 39 18

61 50 49 46 36 17 16 14 13 9

67 61

60

59 50 49 48 46 45 18 15 9

61 50 48 19 16 13 9

61 50 13 9 61 50 13 9

61 50 48 33 24 17 9

61

50 49 46 36 17 16 14 13 9

61

50 49 46 36 17 16 14 13 9

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

BSSB strap sampled at RSMRST# rising (0 = USB-SS, 1=GPP_D11/D12)

(IPU-eSPI)

(x4)

(IPU-eSPI)

(IPU-RSMRST#)

(IPU/IPD)

(IPU-RSMRST#)

(IPU)

(IPD-PLTRST#)

(IPU)

(IPU-eSPI)

(IPU)

(IPD-RSMRST#)

(IPD-PLTRST#)

(IPD)

(IPD-RSMRST#)

(IPD-PLTRST#)

(IPU-RSMRST#)

LPC strap sampled at RSMRST# rising (0 = LPC, 1 = eSPI)

(IPU/IPD)

Requires connection to SMC via 1K series R

TLS strap sampled at RSMRST# rising (0 = disable)

14 OF 67

<SCH_NUM>

14 OF 130

NC_CLINK_DATA NC_CLINK_RESET_L

NC_CLINK_CLK

TP_SPI_CS2_L

TP_SPI_CS1_L

SPI_CS0_L

TP_SPKR_ID0

TP_PCH_GPP_A0 LPC_SERIRQ

TP_PCH_GPP_D0

MLB_RAMCFG4

TP_PCH_GPP_D3

TP_SPKR_ID1

TP_PCH_GPP_D1

SPI_CLK SPI_MISO SPI_MOSI SPI_IO<2> SPI_IO<3>

LPC_CLKRUN_L

TP_PCH_CLKOUT_LPC1

LPC_CLK24M_SMC_R

LPC_PWRDWN_L

SMBUS_PCH_CLK SMBUS_PCH_DATA PCH_STRP_TLSCONF

SML_PCH_0_CLK

PCH_STRP_ESPI

SML_PCH_0_DATA

SMBUS_SMC_1_S0_SDA

SMBUS_SMC_1_S0_SCL

PCH_STRP_BSSB_SEL_GPIO

LPC_AD_R<0>

LPC_AD_R<2>

LPC_AD_R<1>

LPC_FRAME_R_L

LPC_AD_R<3>

PLT_RST_L

HDA_RST_L

PCH_STRP_BSSB_SEL_GPIO

LPC_CLK24M_SMC

LPC_AD<3>

LPC_AD<2>

LPC_AD<1>

LPC_AD<0>

HDA_SYNC HDA_BIT_CLK HDA_SDOUT

PP3V3_SUS

TBT_T_USB_PWR_EN

TBT_T_CIO_PWR_EN

LPC_SERIRQ

TBT_X_USB_PWR_EN

TBT_X_CIO_PWR_EN

SSD_PWR_EN_L

CAMERA_PWR_EN

AP_DEV_WAKE

PP3V3_SUS

PCH_STRP_ESPI

PCH_STRP_TLSCONF

PP3V3_SUS

LPC_CLKRUN_L

PP3V3_S0

LPC_FRAME_L

HDA_SDOUT_R

HDA_BIT_CLK_R

HDA_SYNC_R

NC_HDA_SDIN1

HDA_SDIN0

TP_XDP_PCH_OBSDATA_D0 TP_PCH_I2S1_SFRM

HDA_RST_R_L

TP_PCH_I2S1_TXD NC_PCH_BT_I2S_SYNC

NC_PCH_BT_I2S_CLK NC_PCH_BT_I2S_R2D

TP_XDP_PCH_OBSDATA_C2

NC_PCH_BT_I2S_D2R

TP_XDP_PCH_OBSDATA_C3 TP_XDP_PCH_OBSDATA_C0

TP_XDP_PCH_OBSDATA_C1 PCH_STRP_TOPBLK_SWP_L

PCH_SD_RCOMP SSD_PWR_EN_L

CAMERA_PWR_EN

AP_DEV_WAKE

AP_RESET_L

TBT_T_PCI_RESET_L

TBT_T_USB_PWR_EN TBT_X_PCI_RESET_L

TBT_T_CIO_PWR_EN

TBT_X_USB_PWR_EN

TBT_X_CIO_PWR_EN

CAMERA_RESET_L

SYNC_DATE=05/11/2015SYNC_MASTER=DEVMLB

BOM_COST_GROUP=CPU & CHIPSET

PCH Audio/LPC/SPI/SMBus

010051/32W MF5%

21

R1463

TLS

1.00K

64 14

010051/32W MF5%

21

R1420

TBT

100K

010051/32W MF5%

21

R1421

TBT

100K

010051/32W MF5%

21

R1422

TBT

100K

010051/32W MF5%

21

R1423

TBT

100K

64

01005

1/32W MF

5%

2

1

R1424

TBT

100K

01005

1/32W MF

5%

2

1

R1425

TBT

100K

1% MF

1/20W

2

1

R1430

200

SD

201

010051/32W MF5%

21

R1466

ESPI

1.00K

64

63

59 14

010051/32W MF5%

21

R1431

100K

30

1% MF1/20W

21

R1476

22

201

63

17

65 25 14

010051/32W MF5%

21

R1450

10K

010051/32W MF5%

21

R1478

10K

010051/32W MF5%

21

R1469

BSSB_GPIO

1.00K

010051/32W MF5%

21

R1429

100K

65 27 14

65 27

01005

1/32W MF

5%

2

1

R1428

100K

010051/32W MF5%

21

R1427

100K

65 30 26 19 15 5

01005

1/32W MF

5%

2

1

R1426

100K

65 25

63

31

53 35 33 30

33

30

30 14

65 30 14

36

30

1%

33.2

010051/32W MF

21

R1474

1%

33.2

010051/32W MF

21

R1473

1%

33.2

010051/32W MF

21

R1472

1%

33.2

010051/32W MF

21

R1471

1%

33.2

010051/32W MF

R1470

1 2

39

33

010051/32W MF5%

21

R1402

PLACE_NEAR=U0500.BK16:1.27mm

33

010051/32W MF5%

21

R1401

PLACE_NEAR=U0500.BK18:1.27mm

33

010051/32W MF5%

21

R1400

PLACE_NEAR=U0500.BJ19:1.27mm

33

010051/32W MF5%

21

R1403

PLACE_NEAR=U0500.BL19:1.27mm

65 39

CRITICAL

SKL-Y-ULX

BGA

SKL-Y

OMIT_TABLE

U0500

F12

D12

BL10

BK11 BJ8 BG10 BP5 BP7

BN8

BH11

BJ10 BF5

BJ6

BB6

AC12 W6 W8

W4 AC10 AA6

AA4 W10

N6

P9 N8 P3

W12

V7

AU10

AV11 AV13

AU12

AT3

B12

AU4 AU6 AU8

BF1

BK14

BL12

BJ19

BK16

BL17

BL15

BL19

BK18

AE12

AG10

AG8

AF11

AF9

AG12

AH11

AH9

AJ8AT5

AP11

AT13 AT11

V5

V11

V3

U8

U12

AV3

BL4 BN4

U0500

SKL-Y

OMIT_TABLE

CRITICAL

BGA

SKL-Y-ULX

64

14

61 50 49 46 36 17 16 14 13 9

64 14

65 30 14

64 14

59 14

65 27 14

65 25 14

61 50 49 46 36 17 16 14 13 9

14

61 50 49 46 36 17 16 14 13 9

30 14

67 61 53 51 50 46 39 35 34

33 31 27 26 23 19 17 16 15 6 5

18

64

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

OUT OUT OUT OUT

OUT

IN

OUT OUT OUT

IN

OUT

IN

OUT

IN

OUT

IN

BI

OUT

BI

OUT

BI

OUT

BI

BI BI

OUT

BI

OUT

BI

OUT

IN

LPC SMBUS, SMLINK

SPI - FLASHC LINK

SYM 5 OF 20

CL_DATA CL_RST*

CL_CLK

SPI0_CS2*

SPI0_CS1*

SPI0_CS0*

GPP_D22

GPP_A0/RCIN* GPP_A6/SERIRQ

GPP_D0

GPP_D21

GPP_D3

GPP_D2

GPP_D1

SPI0_CLK SPI0_MISO SPI0_MOSI SPI0_IO2 SPI0_IO3

GPP_A8/CLKRUN*

GPP_A10/CLKOUT_LPC1

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A14/SUS_STAT*/ESPI_RESET*

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT*

GPP_C3/SML0CLK

GPP_C5/SML0ALERT*

GPP_C4/SML0DATA

GPP_C7/SML1DATA

GPP_C6/SML1CLK

GPP_B23/SML1ALERT*/PCHHOT*

GPP_A1/LAD0/ESPI_IO0

GPP_A3/LAD2/ESPI_IO2

GPP_A2/LAD1/ESPI_IO1

GPP_A5/LFRAME*/ESPI_CS*

GPP_A4/LAD3/ESPI_IO3

AUDIO

SDIO/SDXC

SYM 7 OF 20

GPP_A17/SD_PWR_EN*/ISH_GP7

GPP_G0/SD_CMD GPP_G1/SD_DATA0 GPP_G2/SD_DATA1

GPP_G4/SD_DATA3

GPP_G3/SD_DATA2

GPP_G5/SD_CD*

GPP_G6/SD_CLK

GPP_G7/SD_WP

GPP_A16/SD_1P8_SEL

GPP_F23

SD_RCOMP

GPP_B14/SPKR

GPP_D18/DMIC_DATA1

GPP_D17/DMIC_CLK1

GPP_D20/DMIC_DATA0

GPP_F3/I2S2_RXD GPP_D19/DMIC_CLK0

GPP_F2/I2S2_TXD

GPP_F0/I2S2_SCLK

GPP_F1/I2S2_SFRM

I2S1_TXD

HDA_RST*/I2S1_SCLK

I2S1_SFRM

GPP_D23/I2S_MCLK

HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD

HDA_SYNC/I2S0_SFRM HDA_BLK/I2S0_SCLK HDA_SDO/I2S0_TXD

(IPD-DeepSx)

(IPU)

(IPD-DeepSx)

(IPU)

(IPD-DeepSx)

15 OF 67

15 OF 130

<SCH_NUM>

SMC_WAKE_SCI_L

PP3V3_S0

PP3V3_S5 PP3V3_S4

PM_PWRBTN_L

BT_LOW_PWR_L

PM_DSW_PWRGD

PP1V_S3

PCIE_WAKE_L

PM_SLP_SUS_L

PM_SLP_S3_L PM_SLP_S4_L PM_SLP_S5_L

CPU_VCCST_PWRGD

PM_SLP_S0_L PM_SLP_S3_L

PM_BATLOW_L

PCH_HSIO_PWR_EN

PM_BATLOW_L

SSD_SR_EN_L

PM_SLP_S0_L

PMIC_SYS_PWROK

BT_LOW_PWR_L

PCH_INTRUDER_L

SSD_SR_EN_L

PM_PWRBTN_L

TP_PCH_SLP_LAN_L

NC_PCI_PME_L

PM_SLP_S5_L

PM_SLP_S4_L

TP_PCH_LANPHYPC

SMC_WAKE_SCI_L

PM_PCH_PWROK

PCIE_WAKE_L

SMC_PCH_SUSACK_L

PPVRTC_G3H

TP_PM_SLP_A_L

TP_PCH_SLP_WLAN_L

PM_SLP_SUS_L

TP_PCH_GPD7

SMC_PCH_SUSWARN_L

PM_RSMRST_L

PP3V3_S0

CPU_VCCST_PWRGD_R

TP_CPU_PWRGD

PM_SYSRST_L

PLT_RST_L

PCH Power Management

BOM_COST_GROUP=CPU & CHIPSET

SYNC_MASTER=X260_ERIC SYNC_DATE=06/04/2015

5% MF

100K

010051/32W

R1550

1 2

5% MF

100K

010051/32W

R1554

1 2

5% MF

100K

010051/32W

R1551

1 2

010055% MF

100K

1/32W

R1552

1 2

5% MF

100K

010051/32W

R1553

1 2

R1540

10K

5% MF 010051/32W

1 2

5% MF

1.00K

010051/32W

R1570

1 2

5% MF

10K

010051/32W

R1572

1 2

21

R1576

1/32W 01005MF5%

10K

5% MF

100K

01005

1/32W

R1530

1

2

5%

201

1/20W MF

2.2K

R1510

1

2

25 15

1/32W5% MF

100K

01005

R1571

1 2

50

5%

201

1/20W MF

1M

R1580

1

2

30 15

65 59 15

30 15

67 46 30 15

51 50 48 46 15

65 51 50 49 46 30 15

63 51 50 47 46 30 15

51 50 45 30 15

R1541

100K

5% MF 010051/32W

1 2

65 30 15

18 15

63 30

65 30

46

51 46 30

5% MF

1.00K

01005

1/32W

R1520

1

2

46

201

1/20W

MF

1%

PLACE_NEAR=U0500.B61:7.62mm

60.4

R1521

1 2

63 46 30

30

65 30 26 19 14 5

OMIT_TABLE

CRITICAL

BGA

SKL-Y-ULX

SKL-Y

U0500

BN15

BD16

BD14

BE15

BF14

AY14 BF16

BE17

BB16

BH16

BH14

BC15

BF7

BL6 BF9

BD6

BC7

BC9BB8

BP14

A62

J1

B61

BG19

BJ12

BP11

BN10

H2

BP9

65 30 15

67 61 53 51 50 46 39 35 34 33

31 27 26 23 19 17 16 15 14 6 5

67

61 60 59 50 49 48 46 45 18 13 9

61 59 50 46 31 29 26 25 24 18

30 15

25 15

61 50 42 31 12 8 6

18 15

51 50 48 46 15

65 51 50 49 46 30 15

63 51 50 47 46 30 15

51 50 45 30 15

30 15

65 59 15

67 46 30 15

64

61 46 16 9

67

61 53 51 50 46 39 35 34 33 31

27 26

23 19 17 16 15 14 6 5

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

OUT

IN

OUT

IN

OUT

OUT OUT OUT

IN

OUT

IN

OUT

SUSPWRDNACK

SYSTEM POWER MANAGEMENT

SYM 11 OF 20

GPD4/SLP_S3*

DSW_PWROK

WAKE*

SYS_RESET* RSMRST*

PROCPWRGD VCCST_PWRGD

PCH_PWROK

SYS_PWROK

GPP_A13/SUSWARN*/ GPP_A15/SUSACK*

GPD11/LANPHYPC GPD7/RSVD

GPP_B13/PLTRST*

GPD2/LAN_WAKE*

GPP_B11/EXT_PWR_GATE*

GPP_B2/VRALERT*

SLP_LAN*

GPP_A11/PME*

GPD0/BATLOW*

GPD3/PWRBTN*

GPD1/ACPRESENT

GPD6/SLP_A*

GPD9/SLP_WLAN*

INTRUDER*

SLP_SUS*

GPD10/SLP_S5*

GPD5/SLP_S4*

GPP_B12/SLP_S0*

SSD lane 3

SSD lane 0

Reserved: Thunderbolt B lane 1

Ext C (LS/FS/HS)

Ext B (LS/FS/HS)

Ext D (SS) USB Port Assignments:

Reserved: Thunderbolt B lane 0

Reserved: Thunderbolt A lane 1

(IPD-RSMRST#)

Unused

PCIe Port Assignments:

(IPD)

USB3 Port Assignments:

(IPU)

Ext B (SS)

Unused

Camera

Airport

(IPU)

SSD lane 1

Ext A (LS/FS/HS)

Grounded per SKL MOW 2015WW10

SSD lane 2

(IPU)

Ext D (LS/FS/HS)

Ext A (SS, DCI)

Ext C (SS)

Reserved: Thunderbolt A lane 0

16 OF 130

<SCH_NUM>

16 OF 67

USB_TEST_N

NC_USB_EXTCP

NC_USB_EXTCN

PCIE_CAMERA_D2R_P

PP3V3_SUS

NC_PCIE_SSD_R2D_CN<3> NC_PCIE_SSD_R2D_CP<3>

NC_PCIE_SSD_R2D_CN<2>

NC_PCIE_SSD_D2RP<2>

PCIE_SSD_D2R_N<1>

TP_USB_7N TP_USB_7P

NC_USB_EXTDP

USB_EXTA_N

NC_USB3_EXTD_R2D_CN

NC_USB3_EXTD_D2RP

NC_USB3_EXTD_D2RN

NC_USB3_EXTC_R2D_CP

NC_USB3_EXTC_R2D_CN

PCH_PCIE_RCOMP_N

PCIE_CAMERA_R2D_C_P

PCH_DIFFCLK_BIASREF

PCH_SRTCRST_L

NC_USB_EXTDN

PP3V3_S0

PPVRTC_G3H

PCH_RTCRST_L

TP_ITPXDP_CLK100MP

TP_ITPXDP_CLK100MN

USB_TEST_P

CAMERA_CLKREQ_L

AP_CLKREQ_L

SSD_CLKREQ_L

PCIE_CLK100M_SSD_P

PCIE_CLK100M_TEST_N

AP_CLKREQ_L PCIE_CLK100M_AP_N

TEST_CLKREQ_L

SSD_CLKREQ_L

TP_PCH_CLKREQ5_L

PCIE_CLK100M_AP_P

PCIE_CLK100M_CAMERA_P

TP_PCIE_CLK100M_TBT_BP

XDP_JTAG_ISP_TDI

XDP_JTAG_ISP_TCK

SMC_RUNTIME_SCI_L

CAMERA_CLKREQ_L

XDP_USB_EXTC_OC_L

PCIE_TEST_R2D_P

NC_PCIE_SSD_R2D_CP<2>

NC_PCIE_SSD_D2RP<3>

NC_PCIE_SSD_D2RN<3>

NC_PCIE_SSD_D2RN<2>

PCIE_SSD_R2D_C_P<1>

NC_USB_EXTBN NC_USB_EXTBP

USB_EXTA_P

PCIE_CLK100M_TEST_P

TP_PCIE_TBT_B_D2RP<1>

TP_PCIE_TBT_B_R2D_CP<0>

USB3_EXTA_D2R_P

NC_USB3_EXTB_R2D_CN

PCIE_SSD_D2R_N<0> PCIE_SSD_D2R_P<0>

PCIE_SSD_R2D_C_P<0>

PCIE_SSD_R2D_C_N<0>

PCIE_SSD_D2R_P<1>

PCIE_TEST_D2R_N PCIE_TEST_D2R_P PCIE_TEST_R2D_N

TP_PCIE_TBT_A_D2RN<1>

TP_PCIE_TBT_B_D2RN<0>

TP_PCIE_TBT_B_D2RN<1>

TP_PCIE_TBT_B_R2D_CN<1>

PCIE_AP_R2D_C_N

PCIE_SSD_R2D_C_N<1>

TP_PCIE_TBT_A_R2D_CP<1>

TP_PCIE_TBT_A_R2D_CN<1>

PCIE_CAMERA_D2R_N

PCIE_CLK100M_SSD_N

TP_PCIE_CLK100M_TBT_BN

PCH_PCIE_RCOMP_P TP_XDP_CPU_PRDY_L

TBT_X_CLKREQ_L

PCIE_AP_D2R_P

PCH_USB2_COMP

USB2_VBUSSENSE

TP_PCIE_TBT_A_D2RP<1>

PCIE_AP_R2D_C_P

XDP_USB_EXTA_OC_L

TP_XDP_CPU_PREQ_L

TP_PCIE_TBT_B_R2D_CN<0>

TP_PCIE_TBT_B_D2RP<0>

TP_PCIE_TBT_B_R2D_CP<1>

TP_XDP_PCH_OBSDATA_B0

TEST_CLKREQ_L

PP3V3_SUS

USB_EXTB_OC_L

SMC_RUNTIME_SCI_L XDP_USB_EXTA_OC_L

XDP_USB_EXTC_OC_L XDP_USB_EXTD_OC_L

XDP_JTAG_ISP_TCK

TBT_X_CLKREQ_L

XDP_JTAG_ISP_TDI

PCIE_CLK100M_CAMERA_N

USB3_EXTA_D2R_N

NC_USB3_EXTB_R2D_CP NC_USB3_EXTC_D2RN

NC_USB3_EXTC_D2RP

NC_USB3_EXTD_R2D_CP

NC_USB3_EXTB_D2RP

NC_USB3_EXTB_D2RN

USB3_EXTA_R2D_C_P

USB3_EXTA_R2D_C_N

TP_XDP_PCH_OBSDATA_D3

TP_XDP_PCH_OBSDATA_A2

XDP_USB_EXTD_OC_L

USB_EXTB_OC_L

TP_XDP_PCH_OBSDATA_D1 TP_XDP_PCH_OBSDATA_D2

PP1V_SUS

PM_CLK32K_SUSCLK_R SYSCLK_CLK24M_PCH

NC_PCH_CLK24M_XTALOUT

SYSCLK_CLK32K_PCH

PCIE_CAMERA_R2D_C_N

PCIE_AP_D2R_N

SYNC_DATE=05/11/2015SYNC_MASTER=DEVMLB

PCH PCIe/USB/CLK

BOM_COST_GROUP=CPU & CHIPSET

65

2

1

C1671

X5R 0201-1

1.0UF

6.3V

20%

010051/32W MF

21

R1633

100K

5%

010051/32W MF

21

R1632

100K

5%

010051/32W MF

21

R1631

100K

5%

010051/32W MF

21

R1630

100K

5%

010051/32W MF

21

R1650

47.0K

5%

010051/32W MF

21

R1651

47.0K

5%

010051/32W MF

21

R1653

47.0K

5%

63

65 25 16

59 16

63

010051/32W MF

21

R1641

100K

5%

010051/32W MF

21

R1640

100K

5%

64 16

30 16

010051/32W MF

21

R1611

100K

5%

63

01005

1/32W MF

2

1

R1620

1.00K

5%

010051/32W MF

21

R1652

47.0K

5%

010051/32W MF

21

R1655

47.0K

5%

65 60

60

65

65 23

65 63 18

1% MF

2

1

R1622

PLACE_NEAR=U0500.N2:2.54mm

113

1/20W 201

1% MF

2

1

R1671

20K

1/20W 201

1% MF

2

1

R1670

20K

1/20W

201

2

1

C1670

X5R

0201-1

1.0UF

6.3V

20%

65

65 63 24 23 16

64 63 16

64 16

1% MF

2

1

R1662

2.7K

PLACE_NEAR=U0500.P1:2.54mm

1/20W 201

31

65 18

65 63

54

65 63

54

63

54

J18

G18

A18

C18

H15

F15

D15

B15

B55

D51

H17

F17

D17

B17

J16

G16

A16

C16

AG4

AF3

AH3

AL4

AM5

AJ4

AG6

AF5

AH5

AL6

AM3

AJ6

AE6

AF7

N2

B10

A9

H27

F27

D27

B27

J28

G28

A28

C28

H25

F25

D25

B25

J26

G26

A26

C26

H23

F23

D23

B23

J24

G24

A24

C24

H21

F21

D21

B21

J22

G22

A22

C22

H19

F19

D19

B19

J20

G20

A20

C20

B8

F8

M11

N12

H8

L8

H10

F10

N10

J11

G11

BF3

U0500

BGA

SKL-Y

CRITICAL

OMIT_TABLE

SKL-Y-ULX

25

65 28

28

65 28

28

63

1% MF

2

1

R1610

PLACE_NEAR=U0500.B10:2.54mm

100

1/20W

201

65 63 54

BH18 BN12

L2

M1

P1

BP18

BN19

BC5

AV7

AV5

BD10

AV9

BB10

BA15

F39

F37

G38

G36

F35

H39

H37

J38

J36

H35

G34

J34

U0500

OMIT_TABLE

BGA

SKL-Y

SKL-Y-ULX

CRITICAL

25

65 27 16

28

65

61 50 49 46 36 17 16 14 13 9

67 61 53 51 50 46 39 35 34

33 31 27 26 23 19 17 15 14 6 5

61 46 15 9

65

65 27 16

65 25 16

59 16

65

65 16

65

16

65 16

61 50 49 46 36 17 16 14 13 9

64 63 16

30 16

65 63 24 23 16

64 16

16

64 16

61 50 48 19 13 9

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

BI

OUT

IN IN

OUT

IN

OUT

IN

OUT

IN

BI

OUT

IN

OUT

IN

IN OUT OUT

IN

IN OUT OUT

BI BI

IN

BI BI

IN

OUT

IN

NC

IN

OUT

IN

OUT

IN

IN OUT OUT

SYM 8 OF 20

SSIC / USB3

PCIE/USB3/SATA

USB2

USB3_2_RXP/SSIC_RXP

USB3_2_TXN/SSIC_TXN

USB3_2_TXP/SSIC_TXP

USB3_3_RXN

USB3_4_RXP

PROC_PREQ*

PROC_PRDY*

PCIE1_TXP/USB3_5_TXP

PCIE1_TXN/USB3_5_TXN

PCIE1_RXP/USB3_5_RXP

PCIE1_RXN/USB3_5_RXN

PCIE10_RXN PCIE10_RXP PCIE10_TXN PCIE10_TXP

PCIE2_RXP/USB3_6_RXP

PCIE2_RXN/USB3_6_RXN

PCIE2_TXN/USB3_6_TXN PCIE2_TXP/USB3_6_TXP

PCIE3_RXN

PCIE3_TXP

PCIE3_TXN

PCIE4_RXN PCIE4_RXP PCIE4_TXN PCIE4_TXP

PCIE5_RXN PCIE5_RXP PCIE5_TXN PCIE5_TXP

PCIE6_RXP

PCIE6_RXN

PCIE6_TXP

PCIE6_TXN

PCIE7_TXP/SATA0_TXP PCIE8_RXN/SATA1A_RXN

PCIE8_RXP/SATA1A_RXP

PCIE8_TXP/SATA1A_TXP

PCIE8_TXN/SATA1A_TXN

PCIE9_TXN

PCIE9_RXN PCIE9_RXP

PCIE9_TXP

PCIE_RCOMPP

PCIE_RCOMPN

GPP_A7/PIRQA*

PCIE3_RXP

PCIE7_TXN/SATA0_TXN

PCIE7_RXP/SATA0_RXP

PCIE7_RXN/SATA0_RXN

USB2P_2

USB2N_2

USB2N_9

USB2P_9

USB2P_3

USB2N_7

USB2P_7

USB2N_3

USB2P_5

USB2N_1

USB2P_1

USB2N_5

USB3_4_TXP

USB3_4_TXN

USB3_4_RXN

USB3_1_RXN

USB3_1_RXP USB3_1_TXN USB3_1_TXP

USB3_2_RXN/SSIC_RXN

USB3_3_RXP USB3_3_TXN USB3_3_TXP

GPP_E4/DEVSLP0 GPP_E5/DEVSLP1 GPP_E6/DEVSLP2

GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2

GPP_E8/SATALED*

GPP_E12/USB2_OC3*

GPP_E10/USB2_OC1* GPP_E11/USB2_OC2*

GPP_E9/USB2_OC0*

USB2_ID

USB2_VBUSSENSE

USB2_COMP

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT OUT

SYM 10 OF 20

CLOCK SIGNALS

GPD8/SUSCLK

CLKOUT_ITPXDP_P

CLKOUT_PCIE_N1 CLKOUT_PCIE_P1 GPP_B6/SRCCLKREQ1*

CLKOUT_PCIE_P2

CLKOUT_PCIE_N2

GPP_B7/SRCCLKREQ2*

GPP_B9/SRCCLKREQ4*

CLKOUT_PCIE_P4

CLKOUT_PCIE_P5

CLKOUT_PCIE_N5

GPP_B10/SRCCLKREQ5* GPP_B5/SRCCLKREQ0*

CLKOUT_PCIE_N4

GPP_B8/SRCCLKREQ3*

CLKOUT_PCIE_P3

CLKOUT_PCIE_N3

XCLK_BIASREF

CLKOUT_ITPXDP_N

XTAL24_IN

RTCX1

XTAL24_OUT

RTCX2

RTCRST*

SRTCRST*

OUT OUT IN

OUT OUT

(IPD-PLTRST#)

RAM Configuration StrapsBoard ID Straps

<SCH_NUM>

17 OF 67

17 OF 130

PCH_BT_UART_D2R

TPAD_SPI_INT_L

MLB_RAMCFG1

MLB_RAMCFG3

TPAD_SPI_CS_L

SOC_UART_RTS_L

TP_PCH_GPP_F20 TP_PCH_GPP_F21

TP_PCH_GPP_F22

PCH_EMMC_RCOMP

PCH_SWD_IO PCH_SWD_MUX_SEL SOC_WAKE_L

PCH_SWD_IO

TP_PCH_GPP_F16

PCH_SWD_CLK

SOC_UART_CTS_L

SOC_UART_D2R

MLB_DEV_L

TP_PCH_GPP_F19

TP_PCH_GPP_F17

PCH_CSI2_COMP TP_PCH_GPP_D4

MLB_RAMCFG0 MLB_RAMCFG1

SOC_WAKE_L

AUD_PWR_EN

PP3V3_S0

PP1V8_SUS

PP3V3_SUS

TPAD_SPI_IF_EN TPAD_SPI_INT_L

LCD_IRQ_L

SPIROM_USE_MLB

SOC_UART_R2D

PCH_SWD_CLK

PCH_SWD_MUX_SEL

PCH_BT_UART_R2D

PCH_BSSB_CLK

MLB_DEV_L

PCH_BSSB_DATA MLB_BOARD_ID0

AUD_PWR_EN

TP_TBT_T_DPMUX_SEL

LCD_IRQ_L

AP_S0IX_WAKE_SEL AP_S0IX_WAKE_L

TP_PCH_GPP_F18

TBT_T_PLUG_EVENT_L SSD_BOOT_L

AP_S0IX_WAKE_L TBT_X_PLUG_EVENT_L

AP_S0IX_WAKE_SEL

SSD_UART_CTS_L

LCD_PSR_EN

SSD_UART_D2R SSD_UART_R2D

PCH_BT_UART_CTS_L

PCH_BT_UART_RTS_L

PCH_BT_UART_R2D

PCH_BT_UART_D2R

TPAD_SPI_MISO TPAD_SPI_MOSI

TPAD_SPI_CLK

AUD_SPI_MOSI TPAD_SPI_CS_L

AUD_SPI_MISO

AUD_SPI_CLK

AUD_SPI_CS_L

PP3V3_S0 PP1V8_SUS

MLB_BOARD_ID0

MLB_BOARD_ID2

I2C_UPC_SCL

MLB_BOARD_ID3

TPAD_SPI_MISO

SSD_BOOT_L TP_PCH_GPP_F8

UPC_I2C_INT_L

LCD_PSR_EN

SSD_UART_R2D

SSD_UART_CTS_L

I2C_UPC_SDA

TP_PCH_GPP_F9

MLB_RAMCFG3

TPAD_SPI_IF_EN

TP_TBT_X_DPMUX_SEL

SPIROM_USE_MLB

SOC_UART_R2D

SOC_UART_CTS_L

SOC_UART_RTS_L

MLB_RAMCFG2

SOC_UART_D2R

MLB_BOARD_ID4

MLB_BOARD_ID2 MLB_BOARD_ID3

TP_PCH_GPP_F10

MLB_RAMCFG0

TP_PCH_GPP_F11

MLB_RAMCFG2

MLB_RAMCFG4

MLB_BOARD_ID1

MLB_BOARD_ID4

TBT_T_PLUG_EVENT_L

TBT_X_PLUG_EVENT_L

SSD_UART_D2R

PCH_BT_UART_CTS_L

PCH_BT_UART_RTS_L

TPAD_SPI_MOSI

TPAD_SPI_CLK MLB_BOARD_ID1

AUD_SPI_CLK

AUD_SPI_CS_L

AUD_SPI_MISO AUD_SPI_MOSI

SYNC_DATE=05/11/2015SYNC_MASTER=DEVMLB

PCH GPIO/LPSS

BOM_COST_GROUP=CPU & CHIPSET

2

1

R1795

200

EMMC

1% MF

1/20W 201

2

1

R1782

CSI2

100

1% MF

1/20W 201

64 17

21

R1784

1/32W 01005

100K

MF5%

21

R1785

1/32W 01005

100K

MF5%

21

R1786

1/32W 01005

100K

MF5%

64 17

21

R1794

1/32W 01005

100K

MF5%

21

R1750

MLB_DEV

1/32W 01005

1.00K

MF5%

21

R1778

1/32W 01005

100K

MF5%

21

R1779

1/32W 01005

100K

MF5%

65 29 17

21

R1775

1/32W 01005

100K

MF5%

65 53 17

21

R1770

MF1/32W 01005

47.0K

5%

21

R1771

MF1/32W 01005

47.0K

5%

21

R1772

MF1/32W 01005

47.0K

5%

21

R1773

MF1/32W 01005

47.0K

5%

21

R1722

1/32W 01005

100K

MF5%

64 17

33 24

65 18 17

21

R1717

1/32W 01005

100K

MF5%

2

1

R1755

BOARDID0_L

1/32W 01005

1.00K

MF

5%

2

1

R1756

BOARDID1_L

1/32W 01005

1.00K

MF

5%

2

1

R1757

BOARDID2_L

1/32W 01005

1.00K

MF

5%

2

1

R1758

BOARDID3_L

1/32W 01005

1.00K

MF

5%

2

1

R1759

BOARDID4_L

1/32W 01005

1.00K

MF

5%

2

1

R1769

RAMCFG4_L

1/32W 01005

1.00K

MF

5%

2

1

R1765

RAMCFG0_L

1/32W 01005

1.00K

MF

5%

2

1

R1766

RAMCFG1_L

1/32W 01005

1.00K

MF

5%

2

1

R1767

RAMCFG2_L

1/32W 01005

1.00K

MF

5%

2

1

R1768

RAMCFG3_L

1/32W 01005

1.00K

MF

5%

21

R1780

1/32W 01005

100K

MF5%

65 39 17

36 17

64 17

21

R1774

1/32W 01005

100K

MF5%

60

21

R1727

1/32W 01005

100K

MF5%

33 24

65 54 17

33 24

21

R1723

1/32W 01005

100K

MF5%

21

R1721

1/32W 01005

100K

MF5%

21

R1720

1/32W 01005

100K

MF5%

21

R1718

MF1/32W 01005

47.0K

5%

21

R1715

MF1/32W 01005

47.0K

5%

21

R1716

MF1/32W 01005

47.0K

5%

64 17

65 63 17

21

R1713

MF1/32W 01005

47.0K

5%

21

R1712

MF1/32W 01005

47.0K

5%

21

R1711

MF1/32W 01005

47.0K

5%

21

R1710

MF1/32W 01005

47.0K

5%

21

R1707

MF1/32W 01005

47.0K

5%

21

R1708

150K

MF1/20W 2015%

21

R1706

MF1/32W 01005

47.0K

5%

21

R1705

MF1/32W 01005

47.0K

5%

21

R1703

1/32W 01005

1.00K

MF5%

21

R1702

MF1/32W 01005

47.0K

5%

21

R1701

MF1/32W 01005

47.0K

5%

21

R1700

MF1/32W 01005

47.0K

5%

65 26 17

29 17

65 29 17

29 17

64 17

BJ4

AT9

AM7

AN6

AN4

AT7

AP5

AP7

AP3

V9

U6

U4

U10

T11

T5

T7

P11

T3

T9

P5

P7

AD9

AD3

AD7

AB11

AB9

AB3

AD11

AB5

AB7

AC4

AC6

AA12

AA10

AA8

AC8

AW8

AW4

AW12

BB2

BB4

AW6

AW10

BC3

BD4

BJ3

BL3

BJ1

BD2

BF11

U0500

SKL-Y

CRITICAL

OMIT_TABLE

SKL-Y-ULX

BGA

AD5

AL8

AL10

AN8

AJ12

AL12

AM9

AJ10

AN10

AP9

AN12

AM11

N4

BC1

A38

B37

A36

B35

B33

A30

A32

B29

G32

G30

H33

F29

C38

D37

C36

D35

D33

C30

C32

D29

J32

J30

F33

H29

A11

B39

A34

B31

F31

D39

C34

D31

H31

U0500

BGA

SKL-Y

SKL-Y-ULX

CRITICAL

OMIT_TABLE

17

64 17

17

65 39 17

67

61 53 51 50 46 39 35 34 33 31

27 26 23 19 17 16 15 14 6 5

61 50 48 33 24 17 13 9

61 50 49 46 36 16 14 13 9

65 29 17

65 53 17

36 17

64 17

17

64 17

65 54 17

65 18 17

64 17

65

18 17

17

64 17

65 63 17

65 26 17

29 17

64 17

65 29 17

64 17

67 61 53 51 50 46 39 35 34 33

31 27 26 23 19 17 16 15 14 6 5

61 50 48 33 24 17 13 9

17

14

17

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

OUT

NC

IN

OUT

IN

BI

IN

OUT

BI

IN

OUT OUT

IN

IN IN

IN

OUT

IN

OUT

IN

OUT

IN

OUT OUT

OUT

IN

OUT

SYM 6 OF 20

ISH

/BM_BUSY*/ISH_GP6

/SML0BALERT*

LPSS

GPP_F10/I2C5_SDA/ISH_I2C2_SDA

GPP_D13/ISH_UART0_RXD/SML0BDATA

GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D14/ISH_UART0_TXD/SML0BCLK

GPP_D16/ISH_UART0_CTS*

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_C14/UART1_RTS*/ISH_UART1_RTS* GPP_C15/UART1_CTS*/ISH_UART1_CTS*

SX_EXIT_HOLDOFF/GPP_A12

GPP_D9

GPP_D5/ISH_I2C0_SDA

GPP_D11

GPP_D10

GPP_D12

GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA

GPP_D8/ISH_I2C1_SCL

GPP_D15/ISH_UART0_RTS*

GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4

GPP_A18/ISH_GP0 GPP_A19/ISH_GP1

GPP_A23/ISH_GP5

GPP_B15/GSPI0_CS*

GPP_B18/GSPI0_MOSI

GPP_B17/GSPI0_MISO

GPP_B16/GSPI0_CLK

GPP_B19/GSPI1_CS* GPP_B20/GSPI1_CLK GPP_B21/GSPI1_MISO GPP_B22/GSPI1_MOSI

GPP_C8/UART0_RXD GPP_C9/UART0_TXD GPP_C10/UART0_RTS* GPP_C11/UART0_CTS*

GPP_C22/UART2_RTS*

GPP_C21/UART2_TXD

GPP_C20/UART2_RXD

GPP_C23/UART2_CTS* GPP_C16/I2C0_SDA

GPP_C17/I2C0_SCL GPP_C18/I2C1_SDA

GPP_C19/I2C1_SCL GPP_F4/I2C2_SDA

GPP_F5/I2C2_SCL GPP_F6/I2C3_SDA

GPP_F7/I2C3_SCL GPP_F8/I2C4_SDA

GPP_F9/I2C4_SCL

CSI-2

EMMC

SYM 9 OF 20

CSI2_CLKP1

CSI2_CLKP0

CSI2_DN8

CSI2_DP7

CSI2_DN7

CSI2_DP6

CSI2_DN6

CSI2_DP5

CSI2_DN4

CSI2_DN5

CSI2_DP4

CSI2_DN3 CSI2_DP3

CSI2_DN2 CSI2_DP2

CSI2_DP1

CSI2_DN1

CSI2_DP0

CSI2_DN0

CSI2_DP8 CSI2_DN9 CSI2_DP9 CSI2_DN10 CSI2_DP10 CSI2_DN11 CSI2_DP11

CSI2_CLKN0

CSI2_CLKN1

CSI2_CLKN2

CSI2_CLKP2

CSI2_CLKN3

CSI2_CLKP3

CSI2_COMP

GPP_D4/FLASHTRIG

GPP_F13/EMMC_DATA0 GPP_F14/EMMC_DATA1 GPP_F15/EMMC_DATA2 GPP_F16/EMMC_DATA3 GPP_F17/EMMC_DATA4 GPP_F18/EMMC_DATA5 GPP_F19/EMMC_DATA6 GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

GPP_F22/EMMC_CLK

GPP_F12/EMMC_CMD

EMMC_RCOMP

NOTE: 30 PPM or better required for SKL PCH

PCIe Wake Muxing

PCH IPD = 9-50k

L PCIE_WAKE_L (B0)

SEL OUTPUT

H AP_S0IX_WAKE_L (B1)

PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.

***** Circuit does not support HDA voltage >3.3V.

SMC controls strap enable to allow in-field control of strap setting.

If high, ME is disabled. This allows for full re-flashing of SPI ROM.

PCH ME Disable Strap

System 32kHz / 12MHz / 24MHz Clock Generator

18 OF 67

MIN_LINE_WIDTH=0.1000

VOLTAGE=2.9V

MIN_NECK_WIDTH=0.1000

19 OF 130

<SCH_NUM>

SYSCLK_CLK24M_X1

PP3V3_S4

SPI_DESCRIPTOR_OVERRIDE

HDA_SDOUT_R

SPI_DESCRIPTOR_OVERRIDE_L

PP1V5_S0

PP3V3_S5 AP_S0IX_WAKE_SEL

AP_PCIE_WAKE_L

AP_S0IX_WAKE_L

PCIE_WAKE_L

PP3V3_G3H

PP1V_SUSRS0SW_PCHCLK PP1V2_CAM_XTALPCIEVDD

SYSCLK_CLK32K_PCH

SYSCLK_CLK24M_CAMERA

SYSCLK_CLK24M_X2

SYSCLK_CLK12M_SMC

SYSCLK_CLK32K_CAMERA_BT_AP

SYSCLK_CLK24M_X2_R

SMC_CLK12M_EN

SYSCLK_CLK24M_SSD

SYSCLK_CLK24M_PCH

PP1V8_S0SW_SSD_COLD

PP2V9_SYSCLK

Chipset Support 1

BOM_COST_GROUP=CPU & CHIPSET

SYNC_MASTER=X260_ERIC SYNC_DATE=06/09/2015

5

PI5A3157B

CRITICAL

3 4

26

1

DFN

U1910

65 17

15

6.3V 0201

10%

0.1UF

1

2

CERM-X5R

C1910

100K

1

2

MF 201

1/20W

R1910

5%

65 25

6.3V 0201

10%

1

2

CERM-X5R

C1906

0.1UF

BYPASS=U1900.12:18:5MM

6.3V 0201

10%

0.1UF

2

CERM-X5R

BYPASS=U1900.02:18:5MM

C1905

1

6.3V 0201

10%

0.1UF

CERM-X5R

1

2

C1904

BYPASS=U1900.05:18:5MM

6.3V 0201

10%

CERM-X5R

C1903

2

1

0.1UF

BYPASS=U1900.15:18:5MM

3

DMP31D0UFB4

DFN1006H4-3

1

2

Q1930

61 49 46 39 13

20%

2.2UF

0201

X5R-CERM

6.3V

BYPASS=U1900.17:18:5MM

C1900

1

2

U1900

11

7

10

19

2 5

1

15

17

18

9

4

8

12

3 6

13

STQFN

SLG3AP3430

20

16

14

20%

0201-1

X5R

6.3V

1.0UF

C1901

1

2

BYPASS=U1900.11:18:5MM

30

201

1M

5%

2

1

MF

R1901

NO STUFF

1/20W

0201

1/20W

1

MF

0

5%

R1900

2

24MHZ-10PPM-8PF-40OHM

CRITICAL

Y1900

2.5X2.0MM-SM

31

2 4

12

C1907

0201

50V

CER-C0G

9.5PF

+/-0.1PF

C1908

21

0201

50V

CER-C0G

9.5PF

+/-0.1PF

30

14

201

R1930

1/20W

1

1K

5%

2

MF

61 59 50 46 31 29 26 25 24 15

67 61

60 59 50 49 48 46 45 15 13 9

61 41 40 36 33 31 30 29 23

19

27

65 16

65 27

65 30

65 25

65 54

65 63 16

61 59 58 57 55 54

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

SEL

0

VER 1

A

VCC

1

B1

GND

B0

IN

OUT

OUTIN

D

S

G

IN

32.768K_B

24M_C

24M_B

24M_A

32.768K_A

VIO_32K_B

OE_12M

GND

VOUT

12M

VRTC

VIOE_24M_C

VDD

VIOE_24M_B

VIOE_24M_A

X1

X2

IN

OUT

DP DDP Straps

Unbuffered

LPDDR3 Alias Support

HPD S0 Isolation

Platform Reset Connections

PCH 24MHz VIOE Options

19 OF 67

VOLTAGE=0.6V

22

VOLTAGE=0.6V

22

VOLTAGE=0.6V

VOLTAGE=1.0V MIN_NECK_WIDTH=0.1000

MIN_LINE_WIDTH=0.2000

VOLTAGE=1.0V MIN_NECK_WIDTH=0.1000

MIN_LINE_WIDTH=0.2000

20 OF 130

<SCH_NUM>

MAKE_BASE=TRUE

PP1V_SUSRS0SW_PCHCLK

PP1V_S0SW_PCHCLK

PP1V_SUSRS0SW_PCHCLK

PM_SLP_S0S3_L

PP1V_SUS

MAKE_BASE=TRUE

PPVREF_S3_MEM_VREFDQ_A

PPVREF_S3_MEM_VREFCA

PPVREF_S3_MEM_VREFDQ_B

PPVREF_S3_MEM_VREFDQ_A

PLT_RST_L

MAKE_BASE=TRUE

PLT_RST_L

PPVREF_S3_MEM_VREFCA

PPVREF_S3_MEM_VREFDQ_B

MAKE_BASE=TRUE

PCH_DDPB_CTRLDATA

PPVREF_S3_MEM_VREFCA

MAKE_BASE=TRUE

DP_XA_HPD

PP3V3_S0

DP_DDI1_HPD

PP3V3_S0

SYNC_DATE=06/09/2015SYNC_MASTER=X260_ERIC

Project Chipset Support

63 51 50 46

CRITICAL

Q2050

DMN32D2LFB4

DFN1006H4-3

3

2

1

21

01005

MF

1/32W

0.00

0%

R2051

PCH24M:S0SW

MF

1/32W

0.00

0%

R2050

PCH24M:SUS

01005

21

4

53

1 2

U2020

CRITICAL

74AUP1G08GX

SOT1226

2

1

R2021

201

5%

100K

1/20W MF

60 24 23

2

1

C2020

X5R-CERM

0201

10V

10%

0.1UF

BYPASS=U2020::5MM

5

2

1

R2000

2.2K

MF

1/20W

5%

201

65 30 26 19 15 14 5 65 30 26 19 15 14 5

19 18

61 50 48 16 13 9

21 20 19

22 21 20 19

22 20 19

21 20 19

22 21 20 19

20 19

5

21 20 19

67 61 53 51 50 46 39 35 34 33

31 27 26 23 19 17 16 15 14 6 5

67

61 53 51 50 46 39 35 34 33 31

27 26 23 19 17 16 15 14 6 5

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

IN

G S

SYM_VER_3

D

A

B

IN

OUT

OUTIN

CPU-Based Margining

VRef Dividers

<SCH_NUM>

22 OF 130

20 OF 67

MIN_NECK_WIDTH=0.2000

21

MIN_LINE_WIDTH=0.3000

MIN_NECK_WIDTH=0.2000

22

MIN_LINE_WIDTH=0.3000

MIN_NECK_WIDTH=0.2000

22

MIN_LINE_WIDTH=0.3000

PP1V2_S3

MEM_VREFDQ_A_RC

CPU_DIMMA_VREFDQ

MEM_VREFDQ_B_RC

CPU_DIMMB_VREFDQ

CPU_DIMM_VREFCA

MEM_VREFCA_A_RC

PPVREF_S3_MEM_VREFCA

PPVREF_S3_MEM_VREFDQ_B

PPVREF_S3_MEM_VREFDQ_A

SYNC_DATE=04/14/2015SYNC_MASTER=DEVMLB

LPDDR3 VREF MARGINING

2

1

C2220

6.3V

10%

0201

X5R-CERM

0.022UF

21

R2220

24.9

201

MF

1/20W

1%

2

1

R2222

PLACE_NEAR=R2221.2:1mm

1/20W

MF

201

1%

8.2K

21

R2223

201

1/20W

MF

10

1%

2

1

R2241

MF 201

8.2K

1% 1/20W

2

1

C2240

6.3V X5R-CERM 0201

0.022UF

10%

21

R2243

201

10

MF

1/20W

1%

21

R2240

201

MF

1/20W

1%

24.9

2

1

R2242

PLACE_NEAR=R2241.2:1mm

201

1%

8.2K

1/20W

MF

2

1

R2261

201

1%

8.2K

1/20W MF

2

1

C2260

10%

0.022UF

0201

X5R-CERM

6.3V

21

R2263

5.1

1/20W

0201

1% MF

21

R2260

201

MF

1/20W

1%

24.9

2

1

R2262

201

PLACE_NEAR=R2261.2:1mm

1%

8.2K

1/20W

MF

2

1

R2221

201

MF

1%

8.2K

1/20W

7

61 50 47 22 21 12 8

21 19

19

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

IN

21 OF 67

23 OF 130

<SCH_NUM>

PPVREF_S3_MEM_VREFDQ_A

PPVREF_S3_MEM_VREFCA

MEM_A_ZQ_B

PPVREF_S3_MEM_VREFCA

MEM_A_DQS_P<1>

MEM_A_DQS_P<6> MEM_A_DQS_N<6>

MEM_A_DQ<16>

MEM_A_CAB<7> MEM_A_CAA<7>

MEM_A_CAA<5>

MEM_A_CAA<1>

MEM_A_CAB<9>

MEM_A_CAB<6>

MEM_A_CAB<4>

MEM_A_CLK_N<1> MEM_A_CLK_N<0>

MEM_A_CAB<5>

MEM_A_ODT<0>

MEM_A_DQ<39> MEM_A_DQ<37> MEM_A_DQ<33> MEM_A_DQ<36> MEM_A_DQ<38> MEM_A_DQ<34>

MEM_A_DQ<42> MEM_A_DQ<41>

MEM_A_DQ<45> MEM_A_DQ<40>

MEM_A_DQ<52>

MEM_A_DQ<44>

MEM_A_DQ<51>

MEM_A_DQ<54>

MEM_A_DQ<55>

MEM_A_DQ<53> MEM_A_DQ<48> MEM_A_DQ<50> MEM_A_DQ<49> MEM_A_DQ<57> MEM_A_DQ<62>

MEM_A_DQ<63>

MEM_A_DQ<60>

MEM_A_DQ<59> MEM_A_DQ<56> MEM_A_DQ<61> MEM_A_DQ<58>

MEM_A_DQS_P<4> MEM_A_DQS_N<4>

MEM_A_DQS_P<5>

MEM_A_DQS_N<5>

MEM_A_DQS_P<7> MEM_A_DQS_N<7>

MEM_A_ZQ_A

MEM_A_ODT<0>

MEM_A_DQ<7>

MEM_A_DQ<6>

MEM_A_DQ<2>

MEM_A_DQ<1> MEM_A_DQ<4> MEM_A_DQ<5> MEM_A_DQ<0>

MEM_A_DQ<12>

MEM_A_DQ<8>

MEM_A_DQ<9> MEM_A_DQ<14> MEM_A_DQ<11>

MEM_A_DQ<13>

MEM_A_DQ<15>

MEM_A_DQ<20>

MEM_A_DQ<10>

MEM_A_DQ<19>

MEM_A_DQ<17> MEM_A_DQ<22> MEM_A_DQ<18> MEM_A_DQ<21> MEM_A_DQ<23> MEM_A_DQ<24> MEM_A_DQ<30> MEM_A_DQ<27> MEM_A_DQ<26> MEM_A_DQ<28> MEM_A_DQ<31> MEM_A_DQ<25> MEM_A_DQ<29>

MEM_A_DQS_N<0>

MEM_A_DQS_P<0>

MEM_A_DQS_N<1>

MEM_A_DQS_P<2> MEM_A_DQS_N<2>

MEM_A_DQS_P<3>

MEM_A_DQS_N<3>

PPVREF_S3_MEM_VREFDQ_A

MEM_A_DQ<3>

MEM_A_CAA<8>

MEM_A_CKE<2>

MEM_A_CS_L<0> MEM_A_CS_L<0> MEM_A_CS_L<1>

MEM_A_CKE<3>

MEM_A_CS_L<1>

MEM_A_CLK_P<1>

MEM_A_CAB<8>

MEM_A_CAB<3>

MEM_A_CAB<2>

MEM_A_CAB<1>

MEM_A_CAB<0>

MEM_A_CAA<2>

MEM_A_CAA<0>

MEM_A_CAA<3> MEM_A_CAA<4>

MEM_A_CAA<6>

MEM_A_CAA<9>

MEM_A_CLK_P<0>

MEM_A_DQ<43>

MEM_A_DQ<46>

MEM_A_DQ<47>

MEM_A_CKE<0> MEM_A_CKE<1>

PP1V8_S3

MEM_A_DQ<35>

MEM_A_DQ<32>

PP1V2_S3

SYNC_DATE=04/14/2015SYNC_MASTER=DEVMLB

LPDDR3 DRAM Channel A (0-63)

2

1

C2372

20%

6.3V

10UF

CERM-X5R

0402-2

BYPASS=U2300.E1::5mm

2

1

C2353

0402-2

6.3V CERM-X5R

10UF

20%

BYPASS=U2300.R15::5mm

21 7

65 21 7

7

65 7

2

1

C2390

BYPASS=U2300.U10::5mm

20%

6.3V

CERM-X5R

0402-2

10UF

2

1

C2380

BYPASS=U2300.A13::5mm

20%

6.3V

0402-2

10UF

CERM-X5R

2

1

C2385

BYPASS=U2300.K17::5mm

20%

6.3V

CERM-X5R

0402-2

10UF

2

1

C2350

20%

6.3V

0402-2

10UF

CERM-X5R

BYPASS=U2300.B17::5mm

2

1

C2351

20%

6.3V

CERM-X5R

10UF

0402-2

BYPASS=U2300.U2::5mm

2

1

C2352

6.3V

10UF

20%

0402-2

CERM-X5R

BYPASS=U2300.A11::5mm

2

1

C2370

20%

6.3V

BYPASS=U2300.A9::5mm

CERM-X5R

0402-2

10UF

2

1

C2371

10UF

0402-2

CERM-X5R

BYPASS=U2300.G2::5mm

6.3V

20%

65 7

E2B11

H17U8

J1A10

H13N8

U17U1

M9

J12

H4

E4

E3

D11

D8

C11

A17A1

D16T12 D15R12

M16T4 M15R4

G14P9 G13N9

J14P7 J13N7

B16R14

B15T14

B14P13

B13R13

C16T13

C15P12

C14N12

C13N11

L13N3

M14P3

M13R3

N16T3

N15N2

N14P2

P16R2

P15T2

D13R11

E16T11

E15N10

E14P10

E13R10

F16T10

F15R9

F14T9

J16P6

J15R6

K16T6

K15N5

K14P5

K13R5

L16T5

L15N4

D14P11

L14P4

F13P8

H14N6

J2B7

K4D6

J4D7

J3C7

H3B8 H2C8

F4D10

F3C10

F2B10

G4D9

G3C9

K3C6

K2B6

L4D5

L3C5

L2B5

U2300

CRITICAL

OMIT_TABLE

ELPIDA

BGA

32GB-LPDDR3X64

62 7

2

1

R2320

201

MF

1/20W

1%

243

2

1

C2330

X5R

6.3V

10%

0.047UF

201

2

1

C2331

X5R

6.3V

0.047UF

201

10%

65 62 7

62 7

2

1

C2310

X5R

6.3V

10%

0.047UF

201

2

1

C2311

X5R

6.3V 201

10%

0.047UF

2

1

R2300

201

MF

1/20W

1%

243

21 7

7

62 7

M11

E11

E10

U9

E9

R8

M8

E8

A8

T7

R7

E7

U6

M6

E6

T17

R17

N17

M17

J17

F17

D17

U16

R16

G16

U15

T15

H15

G15

P14

A14

U13

N13

U12

L12

H12

F12

E12

D12

A12

M5

L5

K5

J5

H5

G5

F5

E5

A5

U4

M4

D4

C4

B4

A4

D3

B3

A3

D2

C2

A2

P1

M1

G1

F1

D1

C1

B1

U11

U10

M10

U7

M7

P17

L17

K17

G17

E17

U14

A13

M12

K12

G12

C12

B12

U5

M3

M2

N1

B9

A9

G2

K1

E1

A6

A11

T8

A7

C17

B17

H16

R15

U3

C3

U2

L1

H1

T16

A16

A15

B2

T1

R1

U2300

ELPIDA

OMIT_TABLE

CRITICAL

BGA

32GB-LPDDR3X64

2

1

C2343

20%

10UF

0402-2

6.3V

BYPASS=U2300.T1::5mm

CERM-X5R

2

1

C2342

20%

10UF

0402-2

CERM-X5R

6.3V

BYPASS=U2300.A16::5mm

2

1

C2340

20%

6.3V

10UF

0402-2

CERM-X5R

BYPASS=U2300.A15::5mm

2

1

C2341

20%

6.3V

CERM-X5R

0402-2

10UF

BYPASS=U2300.R1::5mm

21 20 19

22 21 20 19 22 21 20 19

21 7

21 20 19

65 21 7

21 7

61 50 49 46 22

61 50 47

22 21 20 12 8

61 50 47 22 21 20 12 8

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

IN

DDR B

DDR A

SYM 1 OF 2

CA7_A CA7_B

CA6_B

CA5_B

CA4_B

CA3_B

CA2_B

CA1_B

CA0_B

CA9_A

CA6_A

CA4_A

CA2_A

CA8_A

CK_T_B

CA3_A

CA1_A

CK_C_A CK_C_B

CA5_A

CA0_A

CK_T_A

ODT_B

DM1_B

DM0_B

DM2_B DM3_B

DQ0_B DQ1_B DQ2_B DQ3_B DQ4_B DQ5_B DQ6_B DQ7_B

DQ9_B

DQ8_B

DQ10_B DQ11_B DQ12_B DQ13_B DQ14_B

DQ16_B

DQ15_B

DQ17_B

DQ19_B

DQ18_B

DQ20_B DQ21_B DQ22_B DQ23_B DQ24_B DQ25_B

DQ27_B

DQ26_B

DQ28_B DQ29_B DQ30_B DQ31_B

DQS0_T_B DQS0_C_B

DQS1_T_B DQS1_C_B

DQS2_T_B DQS2_C_B

DQS3_T_B DQS3_C_B

ZQ_B

VREFCA_B VREFDQ_B

NC NC NC NC NC NC

ODT_A

DM0_A DM1_A DM2_A DM3_A

DQ1_A

DQ0_A

DQ2_A

DQ4_A DQ5_A DQ6_A DQ7_A

DQ9_A

DQ8_A

DQ10_A DQ11_A DQ12_A

DQ14_A

DQ13_A

DQ16_A

DQ15_A

DQ17_A

DQ19_A

DQ18_A

DQ20_A DQ21_A DQ22_A DQ23_A DQ24_A DQ25_A DQ26_A DQ27_A DQ28_A DQ29_A DQ30_A DQ31_A

DQS0_C_A

DQS0_T_A

DQS1_C_A

DQS1_T_A

DQS2_T_A DQS2_C_A

DQS3_T_A DQS3_C_A

ZQ_A

VREFCA_A VREFDQ_A

NC NC NC NC NC NC

DQ3_A

CA8_B CA9_B

CKE0_A

CS0_A*

CKE0_B

CS0_B*

CS1_A*

CKE1_A

CS1_B*

CKE1_B

BI

IN

BI

IN

IN IN

NC

NC NC NC

NC

NC NC

IN IN

IN

IN IN

IN

BI

SYM 2 OF 2

VDD1_A/B VSS_A/B

VSS_A/B

VSS_A/B VSS_A/B

VSS_A/B VSS_A/B VSS_A/B VSS_A/B

VSS_A/B

VSS_A/B VSS_A/B VSS_A/B VSS_A/B VSS_A/B

VSS_A/B

VSS_A/B VSS_A/B

VSS_A/B

VSS_A/B VSS_A/B VSS_A/B

VSS_A/B

VSS_A/B VSS_A/B

VSS_A/B

VSS_A/B VSS_A/B VSS_A/B VSS_A/B VSS_A/B VSS_A/B

VSS_A/B

VSS_A/B VSS_A/B VSS_A/B VSS_A/B VSS_A/B

VSS_A/B

VSS_A/B VSS_A/B

VDD1_A/B VDD1_A/B VDD1_A/B

VSS_A/B

VDDQ_A/B

VDDQ_A/B VDDQ_A/B

VDDQ_A/B

VDDQ_A/B VDDQ_A/B VDDQ_A/B VDDQ_A/B VDDQ_A/B VDDQ_A/B VDDQ_A/B VDDQ_A/B VDDQ_A/B VDDQ_A/B VDDQ_A/B

VDD2_A/B

VDD2_A/B VDD2_A/B

VDD2_A/B

VDDCA_A/B

VDD1_A/B VDD1_A/B

VSS_A/B

VDD2_A/B

VDDCA_A/B

Apple A1534 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual