Apple MLB, A1466 Schematics

TABLE_TABLEOFCONTENTS_ITEM

DRAWING

TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_HEAD

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

PROPRIETARY PROPERTY OF APPLE INC.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

DESCRIPTION OF REVISION

CK APPD

21

1245678

B

D

6543

C

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

THE INFORMATION CONTAINED HEREIN IS THE

C

A

D

DATE

R

SHEET

Apple Inc.

THE POSESSOR AGREES TO THE FOLLOWING:

DRAWING TITLE

D

SIZE

REVISION

DRAWING NUMBER

BRANCH

REV ECN

7

B

3

II NOT TO REPRODUCE OR COPY IT

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

8

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

Schematic / PCB #’s

SCHEM,MLB,J13

2/23/12

1 OF 73

2012-02-23

1 OF 109

2.8.0

051-9277

Voltage & Load Side Current Sensing

12/02/2011

53

45

J11_MLB

SMBus Connections

10/04/2011

52

44

J11_MLB

LPC+SPI Debug Connector

09/08/2011

51

43

J11_MLB

SMC Support

11/10/2011

50

42

J13_MLB_NON_POR

SMC

10/17/2011

49

41

J13_MLB_NON_POR

Left I/O (LIO) Connector

11/10/2011

47

40

J13_MLB_NON_POR

External A USB3 Connector

09/30/2011

46

39

J11_MLB

SSD CONNECTOR

10/17/2011

45

38

J13_MLB_NON_POR

X21 WIRELESS CONNECTOR

10/11/2011

40

37

J11_MLB

TBT Power Support

11/10/2011

38

36

J13_MLB_NON_POR

Thunderbolt Host (2 of 2)

10/04/2011

37

35

J11_MLB

Thunderbolt Host (1 of 2)

09/30/2011

36

34

J11_MLB

SecureDigital Card Reader

11/10/2011

35

33

J13_MLB_NON_POR

DDR3 Bypassing/Termination

07/28/2011

34

32

K21_MLB

FSB/DDR3/FRAMEBUF Vref Margining

08/04/2011

33

31

J11_MLB

DDR3 DRAM CHANNEL B (32-63)

07/28/2011

32

30

K21_MLB

DDR3 DRAM CHANNEL B (0-31)

07/28/2011

31

29

K21_MLB

DDR3 DRAM CHANNEL A (32-63)

07/28/2011

30

28

K21_MLB

DDR3 DRAM CHANNEL A (0-31)

07/28/2011

29

27

K21_MLB

CPU Memory S3 Support

11/10/2011

28

26

J13_MLB_NON_POR

Clock (CK505) and Chipset Support

07/29/2011

27

25

K21_MLB

USB HUB & MUX

11/10/2011

26

24

J13_MLB_NON_POR

CPU & PCH XDP

10/17/2011

25

23

J13_MLB_NON_POR

PCH DECOUPLING

10/03/2011

24

22

J11_MLB

PCH GROUNDS

07/27/2011

23

21

J30_MLB

PCH POWER

09/30/2011

22

20

J11_MLB

PCH GPIO/MISC/NCTF

09/16/2011

21

19

J11_MLB

PCH PCI/USB/TP/RSVD

11/10/2011

20

18

J13_MLB_NON_POR

PCH DMI/FDI/PM/Graphics

07/27/2011

19

17

J30_MLB

PCH SATA/PCIe/CLK/LPC/SPI

07/27/2011

18

16

J30_MLB

CPU DECOUPLING-II

07/29/2011

17

15

K21_MLB

CPU DECOUPLING-I

10/03/2011

16

14

J11_MLB

CPU GROUNDS

07/27/2011

14

13

J30_MLB

CPU POWER

11/10/2011

13

12

J13_MLB_NON_POR

CPU DDR3 INTERFACES

07/27/2011

12

11

J30_MLB

CPU CLOCK/MISC/JTAG

07/27/2011

11

10

J30_MLB

CPU DMI/PEG/FDI/RSVD

10/17/2011

10

9

J13_MLB_NON_POR

Signal Aliases

11/10/2011

9

8

J13_MLB_NON_POR

Power Aliases

07/29/2011

8

7

K21_MLB

Functional Test / No Test

07/29/2011

7

6

K21_MLB

BOM Configuration

07/27/2011

5

J30_MLB

Revision History

07/27/2011

4

J30_MLB

Revision History

11/10/2011

3

J13_MLB_NON_POR

System Block Diagram

11/10/2011

2

J13_MLB_NON_POR

PCB Rule Definitions

01/11/2012

J13_CONSTRAINTS

109

73

Project Specific Constraints

01/11/2012

J13_CONSTRAINTS

108

72

SMC Constraints

01/11/2012

J13_CONSTRAINTS

106

71

Thunderbolt Constraints

01/11/2012

J13_CONSTRAINTS

105

70

PCH Constraints 2

01/11/2012

J13_CONSTRAINTS

103

69

PCH Constraints 1

01/11/2012

J13_CONSTRAINTS

102

68

Memory Constraints

01/11/2012

J13_CONSTRAINTS

101

67

CPU Constraints

01/11/2012

J13_CONSTRAINTS

100

66

LCD Backlight Driver

07/28/2011

K21_MLB

97

65

Thunderbolt Connector A

10/03/2011

J11_MLB

94

64

Internal DisplayPort Connector

07/28/2011

K21_MLB

90

63

Power Control 1/ENABLE

11/10/2011

J13_MLB_NON_POR

79

62

Power FETs

07/28/2011

K21_MLB

78

61

Misc Power Supplies

07/28/2011

K21_MLB

77

60

CPU VCCIO (1.05V) Power Supply

10/17/2011

J13_MLB_NON_POR

76

59

CPU IMVP7 & AXG VCore Output

10/17/2011

J13_MLB_NON_POR

75

58

CPU IMVP7 & AXG VCore Regulator

10/14/2011

J11_MLB

74

57

1.5V DDR3 Supply

12/02/2011

J11_MLB

73

56

5V / 3.3V Power Supply

10/17/2011

J13_MLB_NON_POR

72

55

System Agent Supply

10/17/2011

J13_MLB_NON_POR

71

54

PBus Supply & Battery Charger

11/10/2011

J13_MLB_NON_POR

70

53

DC-In & Battery Connectors

11/10/2011

J13_MLB_NON_POR

69

52

AUDI0: SPEAKER AMP

09/30/2011

J11_MLB

62

51

SPI ROM

07/28/2011

K21_MLB

61

50

IPD / KBD Backlight

11/10/2011

J13_MLB_NON_POR

57

49

Fan

07/28/2011

K21_MLB

56

48

Thermal Sensors

08/03/2011

J11_MLB

55

47

TITLE=MLB ABBREV=DRAWING

LAST_MODIFIED=Thu Feb 23 17:52:06 2012

CRITICAL

1 PCB

PCBF,MLB,J13

820-3209

Page

Date

(.csa)

Contents

Sync Page

(.csa)

Date

Sync

Contents

1 SCH

051-9277

SCHEM,MLB,J13

CRITICAL

SCHEM,MLB,J13

Table of Contents

07/27/2011

1

J30_MLB

High Side Current Sensing

10/17/2011

J13_MLB_NON_POR

54

46

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PCI-E

TMDS OUT

64-bit

MEMORY

DDR3-1600MHZ

DUAL Channel

A

x8

PG 27,28

MEMORY

B

PA_AUX

PA_DPSRC_1

x4

DPC

DP0, x1

EDP

PG 9

PCI-E

PG 9

PCIE1

RTC

PG 16

Xtal

25MHz

EEPROM

PA_LSTX/LSRX

SPI

PA_CIO0

PA_CIO1

PA_DPSRC_3

PCIe x4

U3690

U3600

PG 34

PG 34,35 37

PG 25

TBT Host

PG 11

CONN

LEFT SPEAKER

U6201

LID

I2C

LEFT L/O CONN

USB PORT B

J4610

CAMERA +ALS CONN

I2C

USB CAMERA

LEFT USB EXTB

PG 7

HALL

J4750

Re-DRIVER

U4700

PG 40

USB3

PG 24

U2660

EXTERNAL

(LEFT PORT)

THERMAL

EFFECT

SPK

U6210

SPEAKER

AMP

PG 51

J6903

PG 52

CONN

RIGHT SPEAKER

PG 7

MIC

LINE IN JACK

HEADPHONE/

PG 9

Filter

J4600

SD CARD

SERIAL PORT

Boot ROM

SPI

BUFFER

1

USB 3

6

47

0

1

4

3

8

9234

Conn

CLOCK

U2700

DPMLO

MUX

AUXIO

DISPLAY PORT

PG 64

U9420

DP OUT

DPB

/ TBT

PG 64

J9400

HDMI OUT

LVDS OUT

UP TO 8 LANES

61835

SPI

PG 38

HDD

SATA

J4501

EDP

CONN

J9000

5

7

Audio Codec

PG

J6700

2

J6701

SPEAKER

AMP

PG 10

U6620

PG 11

HDA

J4720

CONN

J6702

J4001

SNK1

SNK0

J4700

PG 11

U4650

CONN

U5700

USB

PM_SLP S3/S4

U4900

43

U3500

CONTROLLER

I2C

PG 7

PG

FILTER

LIO BOARD

CONN

LPC+SPI

J5100

U4730

1

MOJO SMC

DEBUG MUX

J3500

U5510

U5410

J5700

USB MUX

USB A

ADC

FAN0

SMB_3

SMB_5 SMB_1

PG 54-60

POWER CIRCUIT

PG 52,53

SMC

PG 41

2

SD CARD

USB

(UP TO 10 DEVICES)

U6100

U2600

USB HUB

PG 6

X21

CONN

PG 37

WIRELESS

PG 63

PWR

PG 17

PG 18

SMBUS

PCI

HDA

Misc

PG 18

2

LINE IN

CTRL

PG 17

PG 16

GPIOs

25MHz

SATA0

SATA

UP TO 6

PG 16

JTAG

DVI OUT

RGB OUT

PG 16

J2550

PG 23

XDP CONN

PCH

HEADPHONE

SYSTEM

SENSOR

PG 24

PG 35

PG 39

PG 40

PG 43

PG 49

SMB_2

LID

KBDLED

PG 48

FAN CONN

J5600

PG 45,46

PG 49

KBD CONN

J5715

PG 49

U5750

J4001

Bluetooth

PG 37

(ON AP)

PG 50

CPU TEMP SENSOR

PG 46,47

PG 38

U4510

MUX

LPC

1017P

U1800

PANTHER POINT - MPCH

PG 19

J6950,U7000

PG 47

TBT/MLBBOT/INLET TEMP SENSOR

VOLTAGE/CURRENT SENSOR

PG 16

PG 19

PG 23

PG 49

TRACKPAD

U1000

PG 17

DMI

CLK

32KHz

PCIE0

IVY BRIDGE 2C-35W

AXG=GT2, ULV, 1023P

INTEL CPU

PG 17

FDI

PG 11

DMI

PG 9PG 9

EDP

INTEL

PG 10

JTAG

FDI

MUX

XHCI/EHCI2

KBD DRIVER

CHARGER

J2500

CPU

XDP CONN

U3100-U3130 U3200-U3230

MEMORY

x8

PG 29,30

U3000-U3030

U2900-U2930

SYNC_MASTER=J13_MLB_NON_POR

SYNC_DATE=11/10/2011

System Block Diagram

051-9277

2.8.0

2 OF 109

2 OF 73

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

3.3V

(R/H)

TPS51980

A

AC

ADAPTER

A

R7050

PPVBAT_G3H_CHRG_RET

1

D7005

SMC_GFX_VSENSE

PPDCIN_G3H_OR_PBUS

PP5V5_CHAR_VDDP

1

SMC_DCIN_ISENSE

R7020

J6900

26

TBT_PWR_EN

PM_SLP_S3_L

RSMRST_OUT(P15)

1V05_S0_LDO_EN

U1800

PM_PCH_PWRGD

(PAGE 16~21)

(PAGE 41)

BATTERY CHARGER

CHGR_BGATE

F6901

U7000

ISL6259HRTZ

EN/UVLO

1

(PAGE 53)

LT3470A

VOUT

F7040

PPBUS_G3H

CPUIMVP_AXG_PGOOD

25-1

PPVCORE_S0_AXG_REG

(PAGE 36)

TPS22920

A

VOUT

R0954

VR_ON

(PAGE 57)

PGOOD

PGOODG

VLDOIN

PPVTT_S0_DDR_LDO

VOUT2

SMC_SYS_KBDLED

PP3V3_S0_SSD_R

PPVOUT_SW_LCDBKLT

16

PP1V05_S0_VMON

PP1V5_S3RS0_VMON

PP5V_S0_VMON

PP5V_S0_FET

PGOOD

LCD_BKLT_EN

SMC_BATT_ISENSE

PP5V5_CHRG_VDDP

VIN

SMC_RESET_L

U7090

(PAGE 53)

PBUS SUPPLY/

V

ENABLE

2

ENABLE

PP3V42_G3H_REG

(PAGE 52)

LT3470A

3.425V G3HOT

U6990

D6905

SMC_GFX_ISENSE

R7510

CPUVCCIOS0_PGOOD

CPUIMVP_PGOOD

PPDDR_S3_REG

Q7801

SMC

J6950

2S3P

(6 TO 8.4V)

U4900

Q7840

PP5V_SUS_FET

P3V3S3_EN

P5V_3V3_SUS_EN

TPS720105

(PAGE 60)

V

P3V3S5_EN

A

PPVBATT_G3H_CONN

Q7055

PPVBAT_G3H_CHGR_R

IN

DCIN(14.5V)

4

6A FUSE

Q5310

VOUT

ISL95870AH

0.75V

U7300

(PAGE 56)

TPS51916

24

1.5V

U7100

(PAGE 54)

PVCCSA_PGOOD

VCC

U7400

CPU VCORE

EN

VID1

Q5300

USB_PWR_EN

(PCH)

DDRREG_EN

PG62

DELAY

RC

R7962

PP1V05_SUS_LDO

U7960

ISL88042IRTEZ

VDD

MIC2292

OUT

PAGE49

PP3V3_S0_VMON

6

IMVP_VR_ON(P16)

R7978

PM_SLP_S3_L

CPU

U2760

8

PP5V_S0_KBDLED

Q7860

14

PP5V_S3_REG

V2MON

15

4

SMC_ONOFF_L

10-4

CPU_VCCSA_VID<0>

PGOOD

PVCCSA_PGOOD

PPVCCSA_S0_REG

R6906

23-1

PM_SLP_S5_L

DPWROK

SMC_DELAYED_PWRGD

ALL_SYS_PWRGD

DRAMPWROK

P1V5CPU_EN

A

U2750

VOUT1

PM_S0_PGOOD

CPUVCCIOS0_PGOOD

A

P3V3S5_PGOOD

P5VS3_PGOOD

P1V8S0_PGOOD

R7550

PLTRST#

16

R7350

DDRREG_PGOOD

RST*

COUGAR-POINT

SYS_RERST#

SLP_S3#(F4)

(PAGE 16~21)

SLP_S5_L(P95)

99ms DLY

P17(BTN_OUT)

(PAGE 9~13)

PWRBTN#

SMC

P5VS3_PGOOD

PP3V3_S5_REG

CPU_VCCSA_VID<1>

PP5V_S0_VCCSA

VOUT1

(L/H)

SMC_PBUS_VSENSE

P3V3S5_EN

CPUIMVP_VR_ON

PM_RSMRST_L

SLP_SUS#

U1800

SLP_S4#(H4)

CPUVCCIOS0_EN

21

14-1

PP3V3_S5

DDRVTT_EN

DDRREG_EN

VCC

VID0

PPVIN_S5_P5VP3V3

PPVCORE_S0_CPU_REG

V3MON

22

VIN

EN

PVCCSA_EN

MAX15120

CPUIMVP_VR_ON

25

PP1V05_TBTCIO_FET

SMC_CPU_ISENSE

EN

R7140

16-1

R7640

21

A

PGOOD

VIN

VOUT

VIN

SMC_CPU_FSB_ISENSE

(PAGE 59)

VIN

PP3V3_SUS_FET

A

VOUT

14-1

TBTBST_EN_UVLO

Q9706

BKLT_PLT_RST_L

13-2

P3V3S5_PGOOD

(PAGE 55)

VOUT2

3A 32V

F9700

PBUSVSENS_EN

(PAGE 65)

PM_SLP_S4_L

14

BKL_EN

15

Q7820

LP8550

U9701

SMC_PBUS_VSENSE

Q5300

PGOOD

A

P5V_3V3_SUS_EN

(PAGE 36)

P1V8_S0_EN

17

PP3V3_T29_FET

PP1V5S0_EN

10-2

A

R4599

R7831

T29_PWR_EN

Q7810

Q7830

P3V3S0_EN

14

PP3V3_S3_FET

EN

VIN

U7740

10-3

14-1

PP3V3_S0

R5430

P5VS3_EN

11

PM_SLP_S5_L

7

U7201

13

PP5V_S0_CPUVCCIOS0.

6-1

SYSRST(PA2)

PM_SYSRST_L

PM_PWRBTN_L

SMC_RESET_L

U4900

5

PPCPUVCCIO_S0_REG

29

PM_RSMRST_L

PM_PWRBTN_L

PM_SYSRST_L

PM_DSW_PWRGD

28

PM_MEM_PWRGD

10

P15

4

26

12

PROCPWRGD

RSMRST#

4

SMC_RESET_L

22

U5010

SN0903048

SMC POWER

(PAGE 42)

3

U7600

CPUVCCIOS0_EN

(PCH)

U1000

RSMRST_IN(P13)

PWR_BUTTON(P90)

PWRGD(P12)

SLP_S3_L(P93)

9

PM_SLP_S4_L

V4MON

(PAGE 62)

18

19

U7770

TPS72015

(PAGE 60)

TPS720105

U7780

(PAGE 60)

EN

P1V8S0_PGOOD

S5

S3

VOUT

PP1V8_S0_REG

U7720

ISL8014A

EN

(PAGE 60)

EN

9

R6905

5V

EN1

EN2

7

PG 17

PG62

VIN

EN

VOUT

PP15V_T29_REG

(PAGE 36)

VIN

LT3957

U3890

Q3880

&&

13

PG62

PG 17

T29_A_HV_EN

14-1

PBUSVSENS_EN

PG62

P5V_3V3_SUS_EN

P3V3S0_EN

P5VS3_EN

6

RC

DELAY

U7940

RC

SLP_S5#(E4)

SMC_PM_G2_EN

P60

PM_SLP_S3_R_L

21

22

17

19

1V05_S0_LDO_EN

PVCCSA_EN

RC

DELAY

RC

P1V8S0_EN

P1V5S0_EN

DELAY

RC

DELAY

P5VS0_EN

14-1

EN

(PAGE 41)

27

U3816/U3820

PM_DSW_PWRGD

ISL95870

1.05V

PPVIN_G3H_P3V42G3H

22-1

15

A

TPS22924

U3810

PP1V05_S0_LDO.

PP1V5_S0_REG

PLT_RERST_L

CPU_PWRGD

30

SM_DRAMPWROK

UNCOREPWRGOOD

RESET*

23

PP1V5_S3RS0_FET

13-1

PM_SLP_SUS_L

COUGAR-POINT

DELAY

P3V3S3_EN

PG61

10-1

J13 POWER SYSTEM ARCHITECTURE

P5VS0_EN

U5750

KBDLED_ANPDE

ALL_SYS_PWRGD

S5_PWRGD

25

SLP_S4_L(P94)

Revision History

SYNC_DATE=11/10/2011

3 OF 73

3 OF 109

2.8.0

051-9277

TABLE_BOMGROUP_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

BOM Variants

Bar Code Labels / EEEE #’s

Sub BOM

J13_CMNPTS,EEEE:F27Q,CPU:1.8GHZ,DDR3:SAMSUNG_8GB

PCBA,MLB,1.8GHZ,SA 8GB,J13

639-3791

J13_CMNPTS,EEEE:F27R,CPU:2.0GHZ,DDR3:SAMSUNG_8GB

PCBA,MLB,2.0GHZ,SA 8GB,J13

639-3792

J13_CMNPTS,EEEE:F27V,CPU:1.7GHZ,DDR3:SAMSUNG_8GB

PCBA,MLB,1.7GHZ,SA 8GB,J13

639-3790

PCBA,MLB,2.0GHZ,EL 8GB,J13

639-3767

J13_CMNPTS,EEEE:F25V,CPU:2.0GHZ,DDR3:ELPIDA_8GB

J13_CMNPTS,EEEE:F27W,CPU:1.7GHZ,DDR3:ELPIDA_4GB

PCBA,MLB,1.7GHZ,EL 4GB,J13

639-3793

PCBA,MLB,2.0GHZ,HY 4GB,J13

639-3766

J13_CMNPTS,EEEE:F25R,CPU:2.0GHZ,DDR3:HYNIX_4GB

639-3765

PCBA,MLB,2.0GHZ,HY 8GB,J13

J13_CMNPTS,EEEE:F25W,CPU:2.0GHZ,DDR3:HYNIX_8GB

639-3764

PCBA,MLB,2.0GHZ,SA 4GB,J13

J13_CMNPTS,EEEE:F25N,CPU:2.0GHZ,DDR3:SAMSUNG_4GB

639-3762

PCBA,MLB,1.8GHZ,HY 4GB,J13

J13_CMNPTS,EEEE:F25Y,CPU:1.8GHZ,DDR3:HYNIX_4GB

J13_CMNPTS,EEEE:F25T,CPU:1.8GHZ,DDR3:HYNIX_8GB

639-3761

PCBA,MLB,1.8GHZ,HY 8GB,J13

J13_CMNPTS,EEEE:F0TD,CPU:1.7GHZ,DDR3:ELPIDA_8GB

639-3644

PCBA,MLB,1.7GHZ,EL 8GB,J13

PCBA,MLB,1.7GHZ,HY 8GB,J13

639-3556

J13_CMNPTS,EEEE:DYRK,CPU:1.7GHZ,DDR3:HYNIX_8GB

085-3939

J13 MLB DEVELOPMENT BOM

J13_DEVEL:ENG

J13_CMNPTS,EEEE:F25Q,CPU:1.8GHZ,DDR3:SAMSUNG_4GB

PCBA,MLB,1.8GHZ,SA 4GB,J13

639-3760

639-3763

PCBA,MLB,1.8GHZ,EL 8GB,J13

J13_CMNPTS,EEEE:F25P,CPU:1.8GHZ,DDR3:ELPIDA_8GB

PCBA,MLB,1.5GHZ,EL 8GB,J13

639-3645

J13_CMNPTS,EEEE:F0TC,CPU:1.5GHZ,DDR3:ELPIDA_8GB

SYNC_DATE=07/27/2011

SYNC_MASTER=J30_MLB

Revision History

J13_CMNPTS,EEEE:F27Y,CPU:1.8GHZ,DDR3:ELPIDA_4GB

PCBA,MLB,1.8GHZ,EL 4GB,J13

639-3794

J13_CMNPTS,EEEE:DYRM,CPU:1.5GHZ,DDR3:SAMSUNG_4GB

639-3553

PCBA,MLB,1.5GHZ,SA 4GB,J13

CRITICAL

EEEE:F25Q

[EEEE_F25Q]

825-7670

LBL,P/N LABEL,PCB,28MM X 6 MM

1

[EEEE_F25R]

1

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

825-7670

EEEE:F25R

1

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

825-7670

[EEEE_F27V]

EEEE:F27V

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

1

825-7670

[EEEE_F27W]

EEEE:F27W

[EEEE_F25W]

1

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

825-7670

EEEE:F25W

LBL,P/N LABEL,PCB,28MM X 6 MM

825-7670 CRITICAL

1

[EEEE_DYRQ]

EEEE:DYRQ

EEEE:F25P

[EEEE_F25P]

825-7670

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

1

[EEEE_F25N]

EEEE:F25N

825-7670

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

1

[EEEE_F25V]

1

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

825-7670

EEEE:F25V

1

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

825-7670

[EEEE_F27R]

EEEE:F27R

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

1

825-7670

[EEEE_F27Y]

EEEE:F27Y

1

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

825-7670

[EEEE_F27Q]

EEEE:F27Q

[EEEE_F27T]

1

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

825-7670

EEEE:F27T

[EEEE_F25T]

1

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

825-7670

EEEE:F25T

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

1

825-7670

[EEEE_F25Y]

EEEE:F25Y

J13_CMNPTS

CMN PTS,PCBA,MLB,J13

607-9090

CMNPTS

CRITICAL

1

085-3939

DEVEL_BOM

DEVEL

1

CRITICAL

J13 MLB DEVELOPMENT

825-7670

EEEE:F0TD

[EEEE_F0TD]

1

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_DYRP]

EEEE:DYRP

825-7670

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

1

EEEE:DYRM

[EEEE_DYRM]

825-7670

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

1

LBL,P/N LABEL,PCB,28MM X 6 MM

EEEE:F0TC

[EEEE_F0TC]

825-7670 CRITICAL

1

EEEE:DYRL

[EEEE_DYRL]

825-7670

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

1

EEEE:DYRN

[EEEE_DYRN]

825-7670

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

1

[EEEE_DYRK]

EEEE:DYRK

825-7670

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

1

J13_CMNPTS,EEEE:DYRN,CPU:1.5GHZ,DDR3:HYNIX_4GB

639-3554

PCBA,MLB,1.5GHZ,HY 4GB,J13

J13_CMNPTS,EEEE:DYRL,CPU:1.5GHZ,DDR3:HYNIX_8GB

639-3555

PCBA,MLB,1.5GHZ,HY 8GB,J13

J13_CMNPTS,EEEE:DYRP,CPU:1.7GHZ,DDR3:HYNIX_4GB

639-3557

PCBA,MLB,1.7GHZ,HY 4GB,J13

J13_CMNPTS,EEEE:DYRQ,CPU:1.7GHZ,DDR3:SAMSUNG_4GB

639-3552

PCBA,MLB,1.7GHZ,SA 4GB,J13

CMN PTS,PCBA,MLB,J13

J13_COMMON

607-9090

J13_CMNPTS,EEEE:F27T,CPU:2.0GHZ,DDR3:ELPIDA_4GB

639-3795

PCBA,MLB,2.0GHZ,EL 4GB,J13

051-9277

2.8.0

4 OF 109

4 OF 73

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

Module Parts

DRAM CFG CHART

MICRON

Programmable Parts

Alternate Parts

1

0

B

A

DIE REV

CFG 3

00

CFG 1 CFG 0

VENDOR

HYNIX

1

0

CFG 2

1

0

1

ELPIDA

SIZE

4GB

SAMSUNG

8GB

PD Module Parts

J13 BOM GROUPS

371S0558371S0713

ALL

337S4196337S4236

ALL

337S4198

152S1462

353S1428

372S0185

152S1307

Murata alt to Taiyo Yuden

Coilcraft alt to Murata

CPUMEM_SLG:NO,HUB_3NONREM,TBT,MPM5:YES,PP5V5_DCIN:NO,TPAD_PCH:NO,SKIP_5V3V3:INAUDIBLE,BTPWR:S4,TBTHV:P15V,LVDDR3_HW:YES,AXG_ACOUSTIC:NO

BOOTROM_PROG,SMC_PROG,TBTROM:PROG

ALTERNATE,BKLT:ENG,XDP_CONN,XDP_CPU:BPM,XDP_PCH,LPCPLUS,DDRVREF_DAC,VREFDQ:M1_M3,VREFCA:LDO_DAC,S0PGOOD_ISL,S3_S0_LED,VCCIOISNS_ENG,AIRPORTISNS_ENG,HDDISNS_ENG,LCDBKLTISNS_ENG

LPCPLUS,XDP_CONN

DEVEL_BOM,MOJO:YES,XDP

BKLT:PROD,MOJO:YES,XDP,XDP_CPU:BPM,VREFDQ:LDO,VREFCA:LDO,LPCPLUS,VCCIOISNS_PROD,AIRPORTISNS_PROD,HDDISNS_PROD,LCDBKLTISNS_PROD

RAMCFG0:L,RAMCFG1:L,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:HYNIX_4GB

ALTERNATE,COMMON,J13_MISC,J13_DEBUG:ENG,J13_PROGPARTS,USBHUB2514B,EDP:YES,PCH_C1

IC,SDRAM,2GBIT,DDR3L-1600,REV D.78P FBGA

IC,SDRAM,2GBIT,DDR3L-1600,REV D,78P FBGA

DRAM_TYPE:ELPIDA_4GB

333S0628

U3200,U3210,U3220,U3230

CRITICAL

4

U3100,U3110,U3120,U3130

CRITICAL

4

CRITICAL

IC,SDRAM,4GBIT,DDR3L-1600,REV B,78P FBGA

DRAM_TYPE:ELPIDA_8GB

U2900,U2910,U2920,U2930

CRITICAL

IC,SDRAM,4GBIT,DDR3L-1600,REV B.78P FBGA

DRAM_TYPE:ELPIDA_8GB

CRITICAL

4

U3000,U3010,U3020,U3030

IC,SDRAM,4GBIT,DDR3L-1600,REV B,78P FGBA

DRAM_TYPE:ELPIDA_8GB

4

CRITICAL

U3100,U3110,U3120,U3130

IC,SDRAM,4GBIT,DDR3L-1600,REV B,78P FBGA

DRAM_TYPE:ELPIDA_8GB

CRITICAL

U3200,U3210,U3220,U3230

CRITICAL

1

806-3083

SHLD,USB,MLB,J11/J13

USBCAN

K78, mDP Spring

1

806-2377

CRITICAL

MDPSPRING

NOSTUFF

MDPCAN

1

CRITICAL

806-3216

CAN,MDP,J11/J13

CAN,TOPSIDE_2Piece_Fence,J11/J13

CRITICAL

1

806-3705

TBTTOPSIDE_2P_FENCE

1

CAN,TOPSIDE,J11/J13

806-3214

CRITICAL

TBTTOPSIDE_1P

CAN,TOPSIDE_2Piece_Cover,J11/J13

1

CRITICAL

806-3706

TBTTOPSIDE_2P_COVER

CRITICAL

1

806-3215

CAN,COVER,T29,J11/J13

TBTCOVER

1

U7000

IC,ISL6259,BATCHARGER,3%,4X4MM,QFN28

CRITICAL

353S2929

806-3142

CRITICAL

1

CAN,T29,J11/J13

TBTFENCE

GLUE

946-3115

1

MLB,DYMAX UV EB 0.22GRAM,K21

CRITICAL

RAMCFG0:H,RAMCFG1:H,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:ELPIDA_4GB

RAMCFG0:L,RAMCFG1:H,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:SAMSUNG_8GB

RAMCFG0:L,RAMCFG1:H,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:SAMSUNG_4GB

IC,SDRAM,2GBIT,256MX8,DDR3-1600,78P FBGA

4

DRAM_TYPE:HYNIX_4GB

333S0622

CRITICAL

U3100,U3110,U3120,U3130

4

CRITICAL

IC,SDRAM,4GBIT,512MXB,DDR3-1600,82 FGBA

IC,SDRAM,4GBIT,DDR3-1600,78P FBGA,C-DIE

U3200,U3210,U3220,U3230

CRITICAL

4

U3100,U3110,U3120,U3130

U3000,U3010,U3020,U3030

CRITICAL

IC,SDRAM,4GBIT,DDR3-1600,78P FBGA,C-DIE

DRAM_TYPE:SAMSUNG_8GB

4

IC,SDRAM,4GBIT,DDR3-1600,78P FBGA,C-DIE

333S0623

DRAM_TYPE:SAMSUNG_4GB

CRITICAL

4

IC,SDRAM,2GBIT,DDR3-1600,78P FBGA,D-DIE

CRITICAL

DRAM_TYPE:SAMSUNG_4GB

4

CRITICAL

333S0623

IC,SDRAM,2GBIT,DDR3-1600,78P FBGA,D-DIE

U3200,U3210,U3220,U3230

IC,SDRAM,4GBIT,512MXB,DDR3-1600,82 FBGA

CRITICAL

4

IC,SDRAM,4GBIT,512MXB,DDR3-1600,82 FPGA

DRAM_TYPE:HYNIX_8GB

CRITICAL

4

IC,SDRAM,4GBIT,512MXB,DDR3-1600,82 FBGA

U2900,U2910,U2920,U2930

DRAM_TYPE:HYNIX_8GB

4

U3200,U3210,U3220,U3230

CRITICAL

4

IC,SDRAM,2GBIT,256MX8,DDR3-1600,78P FBGA

333S0622

NXP alt to NXP

ALL

371S0652371S0709

376S0928376S0790

TI alt to Fairchild

138S0671

ALL

Taiyo alt to Murata

138S0673

TBTROM:BLANK

CRITICAL

1

IC,SERIAL SPI EEPROM,256KBIT,20MHZ,MLP8

335S0865

376S0604

Diodes alt to Fairchild

ALL

376S0855

ALL

376S0903

197S0432197S0431

ALL

Toko alt for NEC inductor

152S1295

ALL

152S1493 152S1300

ALL

353S3238

ALL

Intersil alt to OPA2333

U4900

SMC_BLANK

CRITICAL

1

IC,SMC12,40MHZ/50DMIPS MCU, 9X9,157BGA

338S1065

64 MBIT SPI SERIAL DUAL I/O FLASH,Macronix

CRITICAL

1

BOOTROM_BLANK

335S0809

U6100

376S0855

Diodes alt to Toshiba

376S0613

ALL

U3100,U3110,U3120,U3130

CRITICAL

333S0622

IC,SDRAM,2GBIT,256MX8,DDR3-1600,78P FGBA

4

IC,SDRAM,2GBIT,256MX8,DDR3-1600,78P FPGA

DRAM_TYPE:HYNIX_4GB

CRITICAL

4

333S0622

CPU:1.7GHZ

CRITICAL

1

U1000

CPU:1.5GHZU1000

1

CRITICAL

CPU:1.8GHZ

CRITICAL

U1000

1

U1000

CRITICAL

1

U1800

PCH_ES1

1

U3600

338S1047

TBT

IC,TBT,CR-4C,ES1,288 FCBGA,12X12MM

PCH_ES2

CRITICAL337S4180

CRITICAL

U1800

1

PCH_C0

IC,PCH,PPT-MB,QS77,C1,QS

337S4275

PCH_C1

1

U1800

CRITICAL

ALL

Toko alt for Cyntec

152S1085

ALL

Murata alt to Taiyo Yuden

138S0648

ALL

138S0684 138S0660

ALL

372S0186

64 MBIT SPI SERIAL DUAL I/O FLASH,Numonyx

CRITICAL

BOOTROM_BLANK

U6100

1

335S0803

ALL

376S0859

Diodes alt to Toshiba

376S0977

138S0676

ALL

138S0691

Murata alt to Samsung

ALL

Rohm alt to Toshiba

376S0972 376S0612

J13_DEBUG:PROD

J13_DEVEL:PVT

J13_DEVEL:ENG

J13_PROGPARTS

J13_MISC

J13_COMMON

J13_DEBUG:ENG

DDR3:SAMSUNG_8GB

DDR3:ELPIDA_4GB

BOM Configuration

SYNC_DATE=07/27/2011

SYNC_MASTER=J30_MLB

J13_DEBUG:PVT

DDR3:HYNIX_4GB

RAMCFG0:L,RAMCFG1:L,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:HYNIX_8GB

DDR3:HYNIX_8GB

DDR3:SAMSUNG_4GB

IC,EEPROM,CR,V24.1,J11/J13

341S3475

TBTROM:PROG

1

IC,EFI ROM,PROTO1B,J13 J11

341S3482 CRITICAL

BOOTROM_PROG

U6100

1

341S3433

U4900

CRITICAL

1

SMC_PROG

IC,SMC,V2.1A43,Proto1B,J13

IC,SMC12-A3,40MHZ/50DMIPS MCU,9X9,157BGA

SMC_BLANK

CRITICAL

1

338S1098

DDR3:ELPIDA_8GB

376S0796

376S1053

376S0613

NXP alt to Diodes

Diodes alt to Toshiba

Fairchild alt to Siliconix

Epson alt to NDK

TDP 1.5GHZ alt to Nominal

TDP 1.7GHZ alt to Nominal

Diodes alt to ST Micro

128S0333

ALL

Sanyo alt to Kemet

998-4435

128S0357

Sanyo alt to POS caps

998-4435

ALL

Kemet_Rect alt to POS caps

998-4435998-4715

ALL

Kemet_.0045 Flute alt to POS caps

998-4435998-4716

ALL

DRAM_TYPE:SAMSUNG_8GB

DRAM_TYPE:HYNIX_8GB

DRAM_TYPE:SAMSUNG_4GB

DRAM_TYPE:SAMSUNG_8GB

CRITICAL

4

333S0623

U2900,U2910,U2920,U2930

U3000,U3010,U3020,U3030

IC,SDRAM,2GBIT,DDR3L-1600,REV D,78P FGBA

IC,SDRAM,2GBIT,DDR3L-1600,REV D,78P FBGA

333S0623

333S0625

4

333S0629

333S0628

333S0642

4

IC,SDRAM,2GBIT,DDR3-1600,78P FGBA,D-DIE

IC,SDRAM,2GBIT,DDR3-1600,78P FBGA,D-DIE

IC,SDRAM,4GBIT,DDR3-1600,78P FGBA,C-DIE

333S0629

4

138S0703

CRITICAL

U3000,U3010,U3020,U3030

RAMCFG0:H,RAMCFG1:H,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:ELPIDA_8GB

DEVEL_BOM,BKLT:PROD,MOJO:YES,XDP,XDP_CPU:BPM,VREFDQ:LDO,VREFCA:LDO,VCCIOISNS_PROD,AIRPORTISNS_PROD,HDDISNS_PROD,LCDBKLTISNS_PROD

CRITICAL

ALL

337S4197

U3690

U4900

DRAM_TYPE:HYNIX_4GB

CRITICAL

U2900,U2910,U2920,U2930

U3200,U3210,U3220,U3230

U3100,U3110,U3120,U3130

U3000,U3010,U3020,U3030

U2900,U2910,U2920,U2930

U3000,U3010,U3020,U3030

U2900,U2910,U2920,U2930

DRAM_TYPE:HYNIX_4GB

DRAM_TYPE:HYNIX_8GB

DRAM_TYPE:SAMSUNG_4GB

IVB,QBP8,ES2,K0,1.5,17W,2+2,0.95,4M,ULVB

U1800

CRITICAL

CPU:1.7GHZTDP

CPU:1.5GHZTDP

CPU:2.0GHZ

CRITICAL

U1000

CRITICAL

IC,PCH,PPT-MB,SFF,ES2,B0

IC,PCH,PPT-MB,SFF,ES1

1

337S4235

337S4197

IC,PCH,PPT-MB,SFF,P-QS,C0

1

IVB,QBQF,ES2,K0,1.7,17W,2+2,1.0,4M,ULV,TDP

IVB,QBP8,ES2,K0,1.5,17W,2+2,0.95,4M,ULVB

IVB,QC55,QS,L0,1.7,17W,2+2,1.0,3M,ULVBGA

IVB,QC54,QS,L0,1.8,17W,2+2,1.1,3M,ULVBGA

IVB,QC52,QS,L0,2.0,17W,2+2,1.1,4M,ULVBGA

1

337S4165

337S4236

337S4198

337S4296

337S4298

337S4299

051-9277

2.8.0

5 OF 109

5 OF 73

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

FUNC_TEST

(Need to add 2 GND TPs)

POWER SIGNALS

NO_TEST

NO_TEST Nets

FUNC_TEST

J5600: Fan Connector

(Need to add 1 GND TP)

FUNC_TEST

(Need to add 5 GND TPs)

J5700: IPD Flex Connector

(Need to add 6 GND TPs)

FUNC_TEST

J5100: LPC+SPI Connector

(Need to add 8 GND TPs)

(Need 5 TPs)

Functional Test Points

FUNC_TEST

(Need 2 TPs)

(Need to add 2 GND TP)

J5715: KB BKLT CONNECTOR

FUNC_TEST

(Need to add 27 GND TPs)

(Need 5 TPs)

(Need to add 6 GND TPs)

J4501: SATA SSD Connector

FUNC_TEST

(Need 6 TPs)

(Need to add 5 GND TPs)

J6900: DC-In Connector

FUNC_TEST

(Need 4 TPs)

(Need to add 3 GND TPs)

J6903: Speaker Connector

FUNC_TEST

(Need 2 TPs)

(Need to add 5 GND TPs)

FUNC_TEST

J4001: AirPort / BT Connector

J4700: LIO Connector

(Need to add 4 GND TPs near

J6950: Battery Connector

J9000: Internal DP Connector

J6950 and 1 for shield)

FUNC_TEST

(Need 2 TPs)

Misc Voltages & Control Signals

(Need to add 5 GND TPs)

J4800: SD Card Connector

SYNC_DATE=07/29/2011

SYNC_MASTER=K21_MLB

Functional Test / No Test

TRUE

PPVBAT_G3H_CONN

TRUE

SPKRAMP_ROUT_N

TRUE

=SMBUS_BATT_SDA

TRUE

USB_BT_CONN_P

TRUE

NC_PCIE_CLK100M_PE7N

MAKE_BASE=TRUE

TRUE

PP1V5_S0

TP_PCI_CLK33M_OUT3

TP_PCI_PME_L

NC_PCIE_CLK100M_PE7P

TRUE MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE4N

TRUE MAKE_BASE=TRUE

AP_CLKREQ_Q_L

TRUE

PCIE_AP_D2R_N

TRUE

PCIE_AP_D2R_P

TRUE

PCIE_CLK100M_AP_P

TRUE

PCIE_CLK100M_AP_N

TRUE

PCIE_AP_R2D_P

AP_RESET_CONN_L

TRUE

DP_INT_ML_F_N<1>

TRUE

DP_INT_ML_F_P<1>

TRUE

DP_INT_ML_F_P<0>

TRUE

DP_INT_AUX_CH_C_P

TRUE

DP_INT_AUX_CH_C_N

TRUE

LED_RETURN_1

TRUE

LED_RETURN_2

TRUE

LED_RETURN_3

TRUE

LED_RETURN_5

TRUE

LED_RETURN_6

I2C_TCON_SCL_R

TRUE

I2C_TCON_SDA_R

PPVOUT_SW_LCDBKLT

TRUE

PP3V3_SW_LCD

TRUE

PP3V3_S4

PP5V_S0

PP5V_S3

PPDCIN_G3H_ISOL

PPBUS_S5_HS_OTHER_ISNS

PP1V05_TBTCIO

PP1V8_S0_CPU_VCCPLL_R

TRUE

PP1V5_S3_CPU_VCCDQ

TRUE

PP1V05_S0_CPU_VCCPQE

TRUE

PPVCORE_S0_AXG

TRUE

PPVCORE_S0_CPU

TRUE

PP1V05_S0_PCH_VCCADPLL

TRUE

PP1V05_TBTLC

PP3V3_TBTLC

TRUE

PP15V_TBT

TRUE

PPVCCSA_S0_CPU

TRUE

PP1V05_SUS

TRUE

PP0V75_S0_DDRVTT

TRUE

PPVTTDDR_S3

TRUE

PP1V05_S0

PP1V5_S3RS0

TRUE

PP1V5_S3

TRUE

PP3V3_S0

TRUE

PP1V8_S0

TRUE

PP3V3_SUS

TRUE

PP3V3_S3

TRUE

PP3V3_S5

TRUE

PP5V_SUS

TRUE

PP5V_S5

PPVRTC_G3H

TRUE

PP3V42_G3H

TRUE

PPDCIN_G3H

TRUE

PPVIN_SW_TBTBST

TRUE

PPBUS_S5_HS_COMPUTING_ISNS

PPBUS_G3H

TRUE

SYS_DETECT_L

TRUE

=SMBUS_BATT_SCL

TRUE

=PP5V_S3_LIO_CONN

=PP18V5_DCIN_CONN

TRUE

SSD_P3V3S0_EN

TRUE

SSD_RESET_L

TRUE

SATA_PCIE_SEL

TRUE

SATA_SSD_R2D_P

TRUE

SSD_CLKREQ_L

PCIE_SSD_D2R_N<1>

TRUE

SATA_SSD_R2D_N

SMC_OOB1_TX_L

TRUE

PCIE_CLK100M_SSD_P

SATA_SSD_D2R_N

TRUE

SMC_OOB1_RX_L

TRUE

SATA_SSD_D2R_P

TRUE

PP3V3_S0_SSD_FLT

TRUE

KBDLED_FB

TRUE

KBDLED_ANODE

USB3_EXTB_TX_C_P

TRUE

USB3_EXTB_TX_C_N

TRUE

USB_EXTB_P

USB_EXTB_N

TRUE

SPKRAMP_INR_P

SPKRAMP_INR_N

TRUE

AUD_GPIO_3

TRUE

AUD_I2C_INT_L

TRUE

AUD_IP_PERIPHERAL_DET

TRUE

AUD_IPHS_SWITCH_EN

TRUE

=I2C_MIKEY_SDA

TRUE

=I2C_MIKEY_SCL

TRUE

=I2C_LIO_SCL

TRUE

=I2C_LIO_SDA

TRUE

SMC_LID

TRUE

=USB_PWR_EN

SMC_BC_ACOK

TRUE

SYS_ONEWIRE

TRUE

=PP3V3R1V5_S0_AUDIO

TRUE

=PP3V3_S0_AUDIO

TRUE

=PP3V42_G3H_ONEWIRE

TRUE

HDA_SDOUT

TRUE

USB_CAMERA_P

TRUE

SMC_TDO

TRUE

TP_SMC_TRST_L

SD_CMD

TRUE

LPC_PWRDWN_L

PCIE_AP_R2D_N

TRUE

WIFI_EVENT_L

TRUE

PP3V3_WLAN_F

TRUE

NC_CPU_RSVD<8..27>

MAKE_BASE=TRUE

TP_CPU_RSVD<8..27>

TRUE

=I2C_TPAD_SCL

TP_PCIE_CLK100M_PEBN

PCIE_WAKE_L

TRUE

TP_CRT_IG_DDC_CLK

TP_CRT_IG_VSYNC

TP_LVDS_IG_CTRL_CLK

TP_PCH_LVDS_VBG

TP_HDA_SDIN1

TP_HDA_SDIN2

TP_CLINK_RESET_L

TP_PCIE_CLK100M_PEBP

TP_CLINK_DATA

TP_CLINK_CLK

TP_CRT_IG_HSYNC

TP_HDA_SDIN3

TP_LVDS_IG_CTRL_DATA

TP_SDVO_TVCLKINP

TP_SDVO_TVCLKINN

TP_SDVO_STALLN

TP_SDVO_INTP

TP_SDVO_INTN

TP_SDVO_STALLP

TP_XDP_PCH_OBSFN_D<0..1>

TP_XDPPCH_HOOK3

TP_XDP_PCH_OBSFN_B<0..1>

TP_XDPPCH_HOOK2

TP_XDP_PCH_OBSFN_A<0..1>

TP_XDP_PCH_HOOK4

TP_XDP_PCH_HOOK5

TP_PCH_GPIO64_CLKOUTFLEX0

TP_PCH_GPIO67_CLKOUTFLEX3

TP_PCH_GPIO66_CLKOUTFLEX2

TP_PCH_GPIO65_CLKOUTFLEX1

SMC_BS_ALRT_L

TP_LVDS_IG_BKL_PWM

TP_LVDS_IG_B_CLKP

TP_LVDS_IG_B_CLKN

TP_PCH_TP1

TP_PCH_TP2

TP_PCH_TP3

TP_PCH_TP4

TP_PCH_TP5

TP_PCH_TP6

TP_PCH_TP7

TP_PCH_TP8

TP_PCH_TP9

TP_PCH_TP10

TP_PCH_TP12

TP_PCH_TP13

TP_PCH_TP14

TP_PCH_TP15

TP_PCH_TP16

TP_PCH_TP18

TP_PCH_TP17

TP_SATA_E_D2RP

TP_SATA_E_D2RN

TP_SATA_F_R2D_CP

TP_SATA_D_D2RP

TP_SATA_D_D2RN

TP_SATA_D_R2D_CN

TP_SATA_D_R2D_CP

TP_SATA_B_R2D_CP

TP_SATA_B_D2RP

TP_SATA_B_D2RN

TP_PSOC_P1_3

TP_PCIE_CLK100M_PE7P

TP_SATA_B_R2D_CN

TP_PCIE_CLK100M_PE7N

TP_PCIE_CLK100M_PE5P

TP_PCIE_CLK100M_PE6P

TP_PCIE_CLK100M_PE6N

TP_CPU_THERMDC

TP_EDP_AUX_N

TP_EDP_TX_N<0..3>

TP_EDP_AUX_P

TP_EDP_TX_P<0..3>

TRUE

LPCPLUS_GPIO

TRUE

SMC_RX_L

TRUE

SMC_RESET_L

SMC_TDI

TRUE

SPI_ALT_CS_L

TRUE

SPI_ALT_CLK

TRUE

SPIROM_USE_MLB

TRUE

LPC_CLK33M_LPCPLUS

TRUE

SMC_TX_L

TRUE

LPCPLUS_RESET_L

TRUE

PM_CLKRUN_L

TRUE

SMC_TMS

TRUE

SPI_ALT_MISO

TRUE

LPC_FRAME_L

PP3V3_S3RS4_BT_F

TRUE

USB_BT_CONN_N

NC_PCIE_CLK100M_PE6N

MAKE_BASE=TRUE

TRUE

TRUE MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE6P

NC_SATA_B_R2D_CN

TRUE

MAKE_BASE=TRUE

NC_PSOC_P1_3

TRUE

MAKE_BASE=TRUE

TRUE

NC_SATA_B_D2RN

TRUE

MAKE_BASE=TRUE

NC_SATA_D_R2D_CP

TRUE

MAKE_BASE=TRUE

NC_SATA_F_R2D_CP

NC_SATA_F_R2D_CN

TRUE

MAKE_BASE=TRUE

NC_SATA_F_D2RN

MAKE_BASE=TRUE

TRUE

NC_SATA_E_R2D_CP

TRUE

MAKE_BASE=TRUE

NC_SATA_F_D2RP

TRUE

MAKE_BASE=TRUE

NC_SATA_E_D2RN

MAKE_BASE=TRUE

TRUE

NC_SATA_E_R2D_CN

TRUE

MAKE_BASE=TRUE

NC_SATA_E_D2RP

TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_PCH_TP17

TRUE

MAKE_BASE=TRUE

NC_PCH_TP18

TRUE

MAKE_BASE=TRUE

NC_PCH_TP16

TRUE

MAKE_BASE=TRUE

NC_PCH_TP15

TRUE

MAKE_BASE=TRUE

TRUE

NC_PCH_TP14

MAKE_BASE=TRUE

NC_PCH_TP13

TRUE

MAKE_BASE=TRUE

NC_PCH_TP12

TRUE

MAKE_BASE=TRUE

NC_PCH_TP10

TRUE

NC_PCH_TP9

TRUE

MAKE_BASE=TRUE

NC_PCH_TP8

TRUE

MAKE_BASE=TRUE

NC_PCH_TP7

MAKE_BASE=TRUE

TRUE

NC_PCH_TP6

MAKE_BASE=TRUE

TRUE

NC_PCH_TP5

TRUE

PCH_VSS_NCTF<15>

MAKE_BASE=TRUE

TRUE

NC_PCH_TP4

NC_PCH_TP3

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_PCH_TP2

NC_PCH_TP1

MAKE_BASE=TRUE

TRUE

PCH_VSS_NCTF<17>

TRUE

PCH_VSS_NCTF<19>

TRUE

PCH_VSS_NCTF<19>

TRUE

PCH_VSS_NCTF<25>

TRUE

PCH_VSS_NCTF<21>

TRUE

PCH_VSS_NCTF<27>

TRUE

PCH_VSS_NCTF<29>

TRUE

MAKE_BASE=TRUE

NC_LVDS_IG_B_CLKN

MAKE_BASE=TRUE

TRUE

NC_LVDS_IG_B_CLKP

MAKE_BASE=TRUE

TRUE

NC_LVDS_IG_BKL_PWM

MAKE_BASE=TRUE

TRUE

NC_SMC_BS_ALRT_L

PCH_VSS_NCTF<1>

TRUE

PCH_VSS_NCTF<5>

TRUE

PCH_VSS_NCTF<2>

TRUE

PCH_VSS_NCTF<9>

TRUE

PCH_VSS_NCTF<11>

TRUE

PCH_VSS_NCTF<12>

TRUE MAKE_BASE=TRUE

NC_PCH_GPIO67_CLKOUTFLEX3

TRUE MAKE_BASE=TRUE

NC_PCH_GPIO66_CLKOUTFLEX2

MAKE_BASE=TRUE

TRUE

NC_PCH_GPIO65_CLKOUTFLEX1

MAKE_BASE=TRUE

TRUE

NC_PCH_GPIO64_CLKOUTFLEX0

NC_TP_XDP_PCH_HOOK5

MAKE_BASE=TRUE

TRUE

NC_TP_XDP_PCH_HOOK4

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

NC_TP_XDP_PCH_OBSFN_A<0..1>

MAKE_BASE=TRUE

TRUE

NC_TP_XDPPCH_HOOK2

MAKE_BASE=TRUE

TRUE

NC_TP_XDP_PCH_OBSFN_B<0..1>

TRUE MAKE_BASE=TRUE

NC_TP_XDPPCH_HOOK3

TRUE MAKE_BASE=TRUE

NC_TP_XDP_PCH_OBSFN_D<0..1>

MAKE_BASE=TRUE

TRUE

NC_SDVO_STALLP

TRUE MAKE_BASE=TRUE

NC_SDVO_STALLN

MAKE_BASE=TRUE

TRUE

NC_SDVO_INTP

MAKE_BASE=TRUE

TRUE

NC_SDVO_TVCLKINP

TRUE MAKE_BASE=TRUE

NC_SDVO_TVCLKINN

TRUE MAKE_BASE=TRUE

NC_SDVO_INTN

XDP_AP_CLKREQ_L

TRUE

XDP_PCH_AUD_IPHS_SWITCH_EN

TRUE

XDP_FW_CLKREQ_L

TRUE

XDP_PCH_PWRBTN_L

TRUE

XDP_PCH_ISOLATE_CPU_MEM_L

TRUE

XDP_PCH_S5_PWRGD

TRUE

XDP_PCH_ENET_PWR_EN

TRUE

TRUE MAKE_BASE=TRUE

NC_CRT_IG_VSYNC

MAKE_BASE=TRUE

TRUE

NC_LVDS_IG_CTRL_CLK

MAKE_BASE=TRUE

TRUE

NC_HDA_SDIN1

TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE

TRUE

NC_HDA_SDIN3

TRUE MAKE_BASE=TRUE

NC_HDA_SDIN2

NC_CLINK_RESET_L

TRUE

MAKE_BASE=TRUE

TRUE

NC_CLINK_CLK

NC_CLINK_DATA

MAKE_BASE=TRUE

TRUE

TRUE MAKE_BASE=TRUE

NC_PCIE_CLK100M_PEBN

TRUE

MAKE_BASE=TRUE

NC_PCI_CLK33M_OUT3

TRUE

NC_CPU_RSVD<30..45>

NC_PCIE_CLK100M_PE5N

TRUE MAKE_BASE=TRUE

LPC_AD<3..0>

TRUE

=PP5V_S0_LPCPLUS

TRUE

SD_CD_L

TRUE

SD_WP

PP5V_TPAD_FILT

TRUE

USB_TPAD_CONN_P

TRUE

=I2C_TPAD_SDA

TRUE

SMC_TPAD_RST_L

TRUE

SMC_LID

SMC_PME_S4_WAKE_L

TRUE

PP3V3_TPAD_CONN

FAN_RT_TACH

TRUE

=PP5V_S0_FAN

TRUE

FAN_RT_PWM

SPI_ALT_MOSI

TRUE

=PP3V42_G3H_TPAD

TRUE

=PP3V3_S5_LPCPLUS

TRUE

NC_EDP_AUXP

TRUE

MAKE_BASE=TRUE

TP_PCIE_CLK100M_PE4N

TP_PCIE_CLK100M_PE4P

TP_PCIE_CLK100M_PE5N

TRUE

MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE

NC_PCI_PME_L

TRUE

NC_CPU_THERMDC

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE4P

TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE

TRUE

NC_PCIE_CLK100M_PE5P

MAKE_BASE=TRUE

TRUE

NC_SATA_B_D2RP

TRUE

MAKE_BASE=TRUE

NC_SATA_B_R2D_CP

MAKE_BASE=TRUE

TRUE

NC_SATA_D_D2RN

NC_SATA_D_D2RP

MAKE_BASE=TRUE

TRUE

NC_SATA_D_R2D_CN

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TP_CPU_THERMDA

TP_CPU_RSVD<30..45>

=PEG_D2R_N<15..2>

=PEG_D2R_P<15..2>

=PEG_R2D_C_N<15..2>

=PEG_R2D_C_P<15..2>

TRUE

NC_PEG_D2RP<15..2>

TRUE

MAKE_BASE=TRUE

NC_PEG_R2D_CP<15..2>

TRUE

MAKE_BASE=TRUE

TRUE

NC_PEG_D2RN<15..2>

MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE

NC_PCIE_CLK100M_PEBP

TP_CRT_IG_DDC_DATA

TRUE

LPC_SERIRQ

TRUE

SMC_TCK

TRUE

SMC_ROMBOOT

TRUE

XDP_PCH_SDCONN_DET_L

TRUE

USB_TPAD_CONN_N

TP_SATA_E_R2D_CN

TP_SATA_E_R2D_CP

TP_SATA_F_D2RN

TP_SATA_F_D2RP

TP_SATA_F_R2D_CN

NC_PCH_LVDS_VBG

MAKE_BASE=TRUE

TRUE

NC_LVDS_IG_CTRL_DATA

MAKE_BASE=TRUE

TRUE

TP_CRT_IG_GREEN

TP_CRT_IG_BLUE

TP_CRT_IG_RED

NC_CRT_IG_GREEN

MAKE_BASE=TRUE

TRUE

TRUE MAKE_BASE=TRUE

NC_CRT_IG_BLUE

NC_CRT_IG_DDC_DATA

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

TRUE MAKE_BASE=TRUE

NC_CRT_IG_RED

TRUE

XDP_PCH_SDCONN_STATE_RST_L

TRUE

XDP_PCH_USB_HUB_SOFT_RST_L

TRUE

VCCSAS0_SET1_R

VCCSAS0_SREF

TRUE

VCCSAS0_SET1

TRUE

XDP_PCH_AP_PWR_EN

TRUE

TP_SMC_MD1

SD_D<7..0>

TRUE

SD_CLK

TRUE

SPKRAMP_ROUT_P

TRUE

NC_CPU_THERMDA

MAKE_BASE=TRUE

PCIE_SSD_D2R_P<1>

TRUE

PCIE_CLK100M_SSD_N

TRUE

PCIE_SSD_R2D_N<1>

TRUE

PCIE_SSD_R2D_P<1>

TRUE

DP_INT_ML_F_N<0>

DP_INT_HPD_CONN

LED_RETURN_4

SMC_ONOFF_L

VCCSAS0_SET0

NC_EDP_AUXN

NC_EDP_TXN<0..3>

NC_EDP_TXP<0..3>

MAKE_BASE=TRUE

NC_PEG_R2D_CN<15..2>

NC_CRT_IG_HSYNC

NC_CRT_IG_DDC_CLK

HDA_SDIN0

HDA_BIT_CLK

USB_CAMERA_N

USB3_EXTB_RX_RC_P

USB3_EXTB_RX_RC_N

HDA_RST_L HDA_SYNC

PP3V3_SW_SD_PWR

USB_EXTB_OC_L

I499

I500

I501

I502

I503

I504

I505

I506

I566

I567

I568

I569

I570

I571

I592

I593

I594

I595

I596

I597

I598

I599

I600

I601

I602

I623

I624

I626

I627

I628

I629

I630

I631

I632

I633

I634

I635

I636

I637

I638

I639

I640

I641

I642

I643

I644

I645

I646

I647

I648

I649

I650

I651

I652

I653

I654

I655

I656

I657

I658

I659

I667

I668

I669

I670

I671

I672

I673

I674

I675

I676

I677

I678

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I686

I687

I688

I689

I690

051-9277

2.8.0

7 OF 109

6 OF 73

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44 52

37 68

7

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63

7

36

7

67

7

67

7

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7

72

7

36

7

52

44 52

7

52

7

52

38

25 38

38

38 68

16 38

8

38 66

38 68

38 41 42

16 38 66

38 68

38 41

38 68

38

49

40 68

40

40 68

24 68

24 40 68

40 51 72

40 51

18

18 40

25 40

40

40 44

40

40 44

6

40 42 49

39 40 62

40 41

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40

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40

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43

33

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37 42

44 49

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17 37

17

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16

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23

16

8

16

9

19 43

41 42 43

41 42 43 53

41 42 43

43

19 43 50

25 43 69

41 42 43

25 43 69

17 41 43

41 42 43

43

16 41 43 69

37

37 68

6

23

16 41 43 69

7

43

33

49

68

44 49

41 42 49

42 49

6

40 41 42 49

41 42 49

49

48

7

48

43

7

49

7

16

9

17

16 41 43

41 42 43

42 43

33

68

16

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43

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33

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

1.8V/1.5V/1.2V/1.05V Rails

"G3Hot" (Always-Present) Rails

3.3V Rails

TBT Rails (off when no cable)

Chipset "VCore" Rails

1V05 S0 LDO

? mA

2A max supply

5V Rails

=PP3V3_S4_TPAD

=PP3V3_S4_BT

=PP3V3_SUS_PCH_VCCSUS =PP3V3_SUS_GPIO

=PP3V3_S4_SMC

=PP3V3_S4_SD_HPD

=PP3V3_S5_PCH_GPIO

=PP3V3_S4_P3V3S4FET

=PP3V3_S5_PWRCTL =PP3V3_S4_TBTAPWRSW

=PP3V3_S5_SYSCLK =PP3V3_S5_VMON

=PP3V3_S5_SMCBATLOW

=PP3V3_S5_PCHPWRGD

=PP3V3_S5_PCH_VCCDSW

PP3V3_S5

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

VOLTAGE=3.3V MAKE_BASE=TRUE

=PP3V3_S5_PCH

VOLTAGE=3.3V MAKE_BASE=TRUE

PP3V3_S4

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

=PPBUS_S0_VSENSE

=PPVIN_S5_HS_COMPUTING_ISNS_R

PPBUS_S5_HS_OTHER_ISNS

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=8.4V

=PP3V3_SUS_SMC =PP3V3_SUS_PCH_VCC_SPI =PP3V3_SUS_PCH_GPIO

VOLTAGE=3.3V MAKE_BASE=TRUE

PP3V3_SW_TBTAPWR

MIN_LINE_WIDTH=0.38 MM

=PP3V3_S3_BT =PP3V3_S3_CARDREADER =PP3V3_S3_MEMRESET

PP3V3_SUS

MIN_LINE_WIDTH=0.50MM

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.20MM

=PP3V3_SUS_PCH_VCCSUS_USB

=PP3V3_SUS_PCH

VOLTAGE=8.4V

MIN_LINE_WIDTH=0.6 mm

PPBUS_S5_HS_COMPUTING_ISNS

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 mm

=PP3V3_S3_FET

=PP3V3_S4_TBT

=PP3V3_SUS_ROM

=PPVIN_S0_CPUAXG

=PPVCCSA_S0_CPU

=PP3V3_S5_XDP

=PPVIN_S0_CPUIMVP

=PP3V3_SUS_FET

=PPVIN_S0_VCCSAS0

=PPVIN_S0_CPUVCCIOS0

=PP3V3_SUS_PWRCTL

=PPVTT_S0_DDR_LDO

=PPVTT_S3_DDR_BUF

=PP3V3_S3_BMON_ISNS =PP3V3_S3_PCH_GPIO

=PP3V3_S3_WLAN

=PPBUS_S0_LCDBKLT

=PP1V5_S0_REG

=PPVCCSA_S0_REG

=PPVIN_S5_P5VP3V3

=PPVIN_S5_HS_COMPUTING_ISNS

=PPVCORE_S0_CPU_REG

=PP1V5_S3_MEM_B

=PPVIN_S0_DDRREG_LDO

=PP1V5_S3_P1V5S3RS0_FET

=PPDDR_S3_MEMVREF

=PP1V5_S3_MEM_A

=PP1V5_S3_MEMRESET

=PP3V3R1V5_S0_AUDIO

VOLTAGE=12.8V

PPVIN_SW_TBTBST

=PPBUS_G3H

=PPVIN_S5_HS_OTHER_ISNS_R

=PP1V5_S3RS0_FET

=PP1V8R1V5_S0_PCH_VCCVRM

=PP3V3R1V5_S0_PCH_VCCSUSHDA

=PP1V8_S0_P1V05S0LDO

=PP1V8_S0_PCH_VCC_DFTERM

=PP1V8_S0_CPU_VCCPLL

=PP1V8_S0_REG

=PP1V5_S3_CPU_VCCDDR

=PP3V3_S0_P3V3S0FET

=PPHV_SW_DPAPWRSW =PPHV_SW_TBTAPWRSW

VOLTAGE=17.8V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

MAKE_BASE=TRUE

PP15V_TBT

=PPVDDIO_S0_SBCLK

MIN_LINE_WIDTH=2 mm

VOLTAGE=1.5V

MIN_NECK_WIDTH=0.17 mm

PP1V5_S0

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

PP1V5_S3RS0

VOLTAGE=1.5V

=PP1V8_S0_P1V5S0

MIN_NECK_WIDTH=0.1 MM

MIN_LINE_WIDTH=0.8 MM

VOLTAGE=1.5V MAKE_BASE=TRUE

PP1V5_S3

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

MAKE_BASE=TRUE

VOLTAGE=1.8V

PP1V8_S0

=PPDDR_S3_REG

=PP15V_TBT_REG

=PP3V3_TBT_PCH_GPIO

=PP3V3_TBTLC_RTR

=PPVDDIO_TBT_CLK

=PP3V3_TBTLC_FET

PP3V3_TBTLC

MIN_LINE_WIDTH=0.4 MM

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

PP1V05_S0_PCH_VCCADPLL

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

VOLTAGE=1.25V

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM

PPVCORE_S0_CPU

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

PPVCORE_S0_AXG

MAKE_BASE=TRUE

=PP1V05_S0_PCH_VCCADPLL

=PP1V05_S0_LDO

=PPVCORE_S0_CPU =PPCPUVCORE_S0_VSENSE

=PPVCORE_S0_AXG_REG

=PPVCORE_S0_CPU_VCCAXG =PPGFXVCORE_S0_VSENSE

MIN_LINE_WIDTH=0.6 MM

PP1V5_S3_CPU_VCCDQ

MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V MAKE_BASE=TRUE

=PP1V5_S3_CPU_VCCDQ

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

PP1V05_S0_CPU_VCCPQE

MIN_NECK_WIDTH=0.2 MM

=PP1V05_S0_CPU_VCCPQE

=PP1V8_S0_CPU_VCCPLL_R

=PP1V05_TBTLC_FET

=PP1V05_TBTLC_RTR

PP1V05_TBTLC

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

=PP1V05_TBTCIO_RTR

PP1V05_TBTCIO

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=1.05V

=PP1V05_TBTCIO_FET

=PP1V5_S3RS0_VMON

MAKE_BASE=TRUE

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V05_SUS

=PP1V05_SUS_PCH_JTAG

=PP1V05_SUS_LDO

=PPCPUVCCIO_S0_REG

=PP1V05_S0_PCH =PP1V05_S0_PCH_VCCIO =PP1V05_S0_PCH_VCCIO_PCIE

=PP1V05_S0_PCH_VCCASW

=PP1V05_S0_PCH_VCC_CORE =PP1V05_S0_VMON =PPVCCIO_S0_CPUIMVP =PP1V05_S0_PCH_VCCDIFFCLK

=PPVCCIO_S0_XDP =PPVCCIO_S0_SMC =PP1V05_S0_P1V05TBTFET

MIN_LINE_WIDTH=2 mm

VOLTAGE=0.75V

PP0V75_S0_DDRVTT

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.17 mm

=PP0V75_S0_MEM_VTT_A =PP0V75_S0_MEM_VTT_B

=PPVTT_S0_VTTCLAMP

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

VOLTAGE=0.75V

PPVTTDDR_S3

=PPVCCSA_S0_VSENSE

PPVCCSA_S0_CPU

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

VOLTAGE=0.9V

=PP1V05_S0_PCH_VCCIO_SATA

MIN_LINE_WIDTH=0.6 MM

VOLTAGE=1.8V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

PP1V8_S0_CPU_VCCPLL_R

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

=PP3V3_S3_VREFMRGN

=PP3V3_S3_WLANISNS

=PPVIN_S3_DDRREG

=PPVIN_S5_HS_OTHER_ISNS

PP5V_S5

VOLTAGE=5V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

VOLTAGE=5V

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM

MAKE_BASE=TRUE

PP5V_SUS

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=5V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=5V

PP5V_S0

MIN_NECK_WIDTH=0.2 MM

=PP5V_S5_LDO

=PP5V_S5_P5VSUSFET =PP5V_S5_TPAD

=PP5V_SUS_FET

=PP5V_SUS_PCH

=PP5V_S3_REG

=PP5V_S3_AUDIO_AMP

=PP5V_S3_MEMRESET

=PP5V_S3_DDRREG

=PP5V_S3_P5VS0FET =PP5V_S3_RTUSB =PP5V_S3_LIO_CONN

=PP5V_S0_FET

=PP5V_S0_BKL =PP5V_S0_CPUIMVP =PP5V_S0_CPUVCCIOS0 =PP5V_S0_FAN

=PP5V_S0_LPCPLUS

=PP5V_S0_VCCSA

=PP5V_S0_PCH

=PP5V_S0_VMON

=PP5V_S0_KBDLED

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6MM

PP3V42_G3H

MIN_NECK_WIDTH=0.2MM

VOLTAGE=3.42V

VOLTAGE=3V

PPVRTC_G3H

MIN_LINE_WIDTH=0.2 MM

MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

=PP3V42_G3H_REG

=PP3V3_S5_LPCPLUS

=PP3V42_G3H_CHGR

=PP3V3_S5_SMC

=PP3V42_G3H_PWRCTL =PP3V42_G3H_SMBUS_SMC_BSA =PP3V42_G3H_SMCUSBMUX

=PPVBAT_G3H_SYSCLK =PP3V42_G3H_ONEWIRE

=PPVRTC_G3_PCH

=PPVRTC_G3_OUT

=PP18V5_DCIN_ISOL

=PPDCIN_S5_VSENSE

=PPDCIN_S5_CHGR_ISOL

MAKE_BASE=TRUE

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.6 MM

PPDCIN_G3H_ISOL

PPDCIN_G3H

MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.25 MM

VOLTAGE=18.5V

MAKE_BASE=TRUE

=PP18V5_DCIN_CONN

=PPDCIN_S5_CHGR

=PP3V42_G3H_TPAD =PPVIN_S5_SMCVREF

=PP5V_S5_P1V5DDRFET

=PP3V3_SUS_P1V05SUSLDO

=PP3V3_S5_REG

=PPVIN_SW_TBTBST

PPBUS_G3H

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

VOLTAGE=8.4V

=PP3V3_S5_CPU_VCCDDR

=PP3V3_S3_P3V3S3FET

=PP1V05_S0_CPU_VCCIO

=PP3V3_S3_DBGLEDS

=PP3V3_S3_USB_RESET

=PP3V3_S4_TBTAPWR

=PP3V3_S3_USBMUX =PP3V3_S3_LCD

MIN_LINE_WIDTH=0.50MM

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.20MM

PP3V3_S3

SYNC_DATE=07/29/2011

Power Aliases

SYNC_MASTER=K21_MLB

PP5V_S3

=PP3V3_S3_1V5S3ISNS

=PP3V3_S3_SMBUS_SMC_MGMT

MIN_NECK_WIDTH=0.20 MM

=PP3V3_S4_FET

=PP3V3_S5_P3V3SUSFET

=PP1V05_S0_PCH_VCCSSC =PP1V05_S0_PCH_V_PROC_IO =PP1V05_S0_PCH_VCC_DMI

MIN_NECK_WIDTH=0.2 MM

PP1V05_S0

=PP3V3_S3_USB_HUB

=PP3V3_S3_SMBUS_SMC_A_S3

PP3V3_S0

MIN_LINE_WIDTH=0.5 MM

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.20MM

=PP3V3_S0_CPUVCCIOISNS =PP3V3_S0_AUDIO =PP3V3_S0_BKL_VDDIO =PP3V3_S0_HS_COMPUTING_ISNS =PP3V3_S0_CPUTHMSNS =PP3V3_S0_DP_DDC =PP3V3_S0_FAN =PP3V3_S0_P3V3TBTFET

=PP3V3_S0_FET

=PP3V3_S0_PCH

=PP3V3_S0_P1V8S0

=PP3V3_S0_PCH_GPIO =PP3V3_S0_HS_OTHER_ISNS =PP3V3_S0_PCH_VCC3_3 =PP3V3_S0_PCH_VCCADAC =PP3V3_S0_PWRCTL =PP3V3_S0_RSTBUF =PP3V3_S0_SB_PM =PP3V3_S0_SMBUS_PCH =PP3V3_S0_SMBUS_SMC_0_S0 =PP3V3_S0_SMBUS_SMC_B_S0 =PP3V3_S0_SMC

=PP3V3_S0_SSD =PP3V3_S0_HDDISNS =PP3V3_S0_VMON

=PP3V3_S0_P1V5S0 =PP3V3_S0_TBTPWRCTL =PP3V3_S0_P1V05S0LDO =PP3V3_S0_IMVPISNS =PP3V3_S0_XDP =PP3V3_S0_BKLTISNS =PP3V3_S0_SYSCLKGEN

=PP3V3_S0_SAISNS

=PP3V3_S0_SATAMUX

=PP3V3_S0_3V3S0ISNS =PP3V3_S0_CPU_VCCIO_SEL =PP3V3_S0_PCH_VCC3_3_CLK =PP3V3_S0_PCH_STRAPS

051-9277

2.8.0

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IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

860-1327

USB/SD Card Pogo

870-1938

DisplayPort Pogo

870-1938

CPU Heat Sink Mounting Bosses

Fan Boss

Digital Ground

SMC Aliases

Unused PGOOD signal

4x 860-1327

Unused SMC Signals

Unused PPT

TBT DP Ports

CPU signals

Plated Board Slot

860-1327

Unused SATA ODD Signals

X21 Boss

SSD PCIE Signals

860-1327

SSD Boss

Unused USB

LVDS Aliases

SATA Aliases

EMI I/O Pogo Pins

Can Slots

2x TBT chip

2x USB Connector

2x MDP Connector

2x TBT pin diodes

61

56

16

46 72

STDOFF-4.5OD1.8H-SM

TH-NSP

SL-2.3X3.9-2.9X4.5

STDOFF-4.5OD1.8H-SM

STDOFF-4.5OD1.9H-SMSTDOFF-4.5OD1.9H-SMSTDOFF-4.5OD1.8H-SM

SM

POGO-2.0OD-3.6H-K86-K87

CRITICAL

2.2K

1/20W

5%

201

MF

5%

201

2.2K

1/20W

MF

1/20W

201

5%

MF

2.2K

NO STUFF

2.2K

201

1/20W

5%

MF

NO STUFF

100K

MF

201

5%

1/20W

CRITICAL

0.01

MF

0612-1

0.5%

1W

TH-NSP

SL-1.1X0.4-1.4X0.7

TH-NSP

SL-1.1X0.4-1.4X0.7

TH-NSP

SL-1.1X0.45-1.4X0.75

41

18

34 70

16

16 69

16

9

6

38 66

6

38 66

9

0.002

1%

MF1W

CRITICAL

0612

7 7

46 72

201

10K

5% 1/20W MF

RAMCFG0:LRAMCFG1:L

10K

201

MF

1/20W

5%

201

RAMCFG2:L

10K

5% 1/20W MF

10K

5%

MF

201

1/20W

RAMCFG3:L

201

5% 1/20W MF

10K 10K

MF

5%

201

1/20W

5%

10K

201

MF

1/20W

10K

201

MF

1/20W

5%

34 70

5%

MF 201

10K

1/20W

16

34

SL-1.1X0.45-1.4X0.75

TH-NSP

SL-1.1X0.4-1.4X0.7

TH-NSP

SL-1.1X0.4-1.4X0.7

TH-NSP

470K

1%

MF

201

1/20W

470K

1%

1/20W

201

MF

TH-NSP

SL-1.1X0.4-1.4X0.7

CRITICAL

GND

MIN_NECK_WIDTH=0.075MM

VOLTAGE=0V

MIN_LINE_WIDTH=0.6MM

DPLL_REF_CLKN

MAKE_BASE=TRUE

DPLL_REF_CLK_P

MEM_B_CLK_P<1>

MAKE_BASE=TRUE

TP_MEM_B_CLKN<1>

DPA_IG_DDC_CLK

LVDS_IG_PANEL_PWR

LVDS_IG_A_DATA_P<3>

LVDS_IG_B_DATA_N<0..3>

NC_USB3_EXTC_TX_P

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB3_EXTC_RX_P

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_8_D2RN

NC_PCIE_6_D2RN

NC_PCIE_5_D2RN

NC_PCIE_8_D2RP

NC_PCIE_7_D2RP

=PP3V3_S0_DP_DDC

DPB_IG_DDC_CLK

MAKE_BASE=TRUE

DP_IG_D_CTRL_CLK

MAKE_BASE=TRUE

TP_DP_IG_D_CTRL_DATA

MAKE_BASE=TRUE

XDP_DC3_PCH_GPIO19_SATARDRVR_EN

DPLL_REF_CLKP

MLB_RAMCFG0

MLB_RAMCFG1

DPA_IG_DDC_DATA

TP_DP_IG_C_CTRL_DATA TP_DP_IG_D_CTRL_CLK

TP_MEM_A_CLKP<1>

MAKE_BASE=TRUE

TP_MEM_A_CLKN<1>

MAKE_BASE=TRUE

NC_PCIE_EXCARD_R2D_C_P

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_EXCARD_D2R_P

USB_EXTD_EHCI_N

USB3_EXTD_TX_N

USB3_EXTD_RX_N

MAKE_BASE=TRUE

TP_P1V5S3RS0_RAMP_DONE

NO_TEST=TRUE

NC_USB_EXTC_P

MAKE_BASE=TRUE

PCIE_FW_R2D_C_N

PCIE_FW_D2R_P

MEMVTT_EN

MAKE_BASE=TRUE

USB_EXTC_N

IR_RX_OUT_RC

=PEG_D2R_P<1..0>

=PEG_R2D_C_P<1..0>

=PEG_D2R_N<1..0>

SATA_ODD_D2R_N

SATA_ODD_R2D_C_N

TBT_B_CONFIG1_BUF

TBT_B_D2R_N<1>

LVDS_IG_B_DATA_P<0..3>

LVDS_IG_A_DATA_N<3>

LVDS_IG_BKL_PWM

NC_USB_EXTD_EHCI_P

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_7_D2RN

DPA_IG_HPD

TBT_B_LSTX

NC_TBT_B_LSTX

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_TBT_B_D2R_N<1>

MAKE_BASE=TRUE

DP_TBTPB_HPD

TBT_B_CONFIG2_RC

TBT_B_LSRX

MAKE_BASE=TRUE

TP_LVDS_IG_B_CLKN

NC_PCIE_CLK100M_EXCARD_N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_CLK100M_EXCARD_P

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PEG_CLK100M_N

NO_TEST=TRUE

MAKE_BASE=TRUE

PCIE_EXCARD_R2D_C_N

PCIE_EXCARD_R2D_C_P

PCIE_EXCARD_D2R_P

PCIE_ENET_R2D_C_P

PCIE_ENET_R2D_C_N

PCIE_ENET_D2R_N

PCIE_ENET_D2R_P

PEG_CLK100M_P

PCIE_CLK100M_EXCARD_P

PEG_CLK100M_N

PCIE_CLK100M_EXCARD_N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_EXCARD_R2D_C_N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_EXCARD_D2R_N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_FW_R2D_C_P

MAKE_BASE=TRUE

NC_PCIE_FW_D2R_P

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_FW_R2D_C_N

MAKE_BASE=TRUE

NC_PCIE_FW_D2R_N

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCIE_ENET_R2D_C_P

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCIE_ENET_R2D_C_N

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCIE_ENET_D2R_P

PCIE_CLK100M_FW_P

NC_PCIE_CLK100M_FW_N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_CLK100M_FW_P

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_CLK100M_ENET_P

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCIE_CLK100M_ENET_N

PCIE_CLK100M_ENET_P

PCIE_CLK100M_ENET_N

MEM_A_CLK_P<1> MEM_A_CLK_N<1>

=PEG_R2D_C_N<1..0>

DP_TBTSNK1_ML_C_N<3..0>

MAKE_BASE=TRUE

PCIE_TBT_D2R_P<1>

LCD_BKLT_EN

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_TBT_B_R2D_C_P<1>

TBT_B_D2R_P<0>

TBT_B_D2R_N<0>

DPB_IG_HPD

TBT_B_R2D_C_N<1>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_TBT_B_R2D_C_P<0>

MAKE_BASE=TRUE

NC_TBT_B_R2D_C_N<0>

NO_TEST=TRUE

TBT_B_R2D_C_P<1>

MAKE_BASE=TRUE

NC_DP_TBTPB_AUXCH_C_P

DP_TBTPB_AUXCH_C_N

NC_DP_TBTPB_AUXCH_C_N

MAKE_BASE=TRUE

NC_DP_TBTPB_ML_C_P<3>

MAKE_BASE=TRUE

DP_TBTPB_ML_C_P<1>

NC_DP_TBTPB_ML_C_P<1>

MAKE_BASE=TRUE

DP_TBTPB_ML_C_N<1>

NC_DP_TBTPB_ML_C_N<1>

MAKE_BASE=TRUE

DP_TBTSNK0_ML_C_N<3..0>

TP_DP_IG_B_MLN<3..0>

TP_DP_IG_B_MLP<3..0>

TP_DP_IG_C_MLN<3..0>

MAKE_BASE=TRUE

DP_TBTSNK1_AUXCH_C_N

DPB_IG_AUX_CH_N

TP_DP_IG_C_MLP<3..0>

MAKE_BASE=TRUE

DP_TBTSNK1_AUXCH_C_P

DPA_IG_AUX_CH_P

DP_TBTSNK0_HPD

MAKE_BASE=TRUE

DP_TBTSNK1_HPD

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SMC_SYS_LED

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_A_DATAN<3>

MAKE_BASE=TRUE

LCD_IG_PWR_EN

MAKE_BASE=TRUE

DP_IG_D_HPD

NO_TEST=TRUE

NC_LVDS_IG_B_DATAP<0..3>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_B_DATAN<0..3>

MAKE_BASE=TRUE

TBT_B_R2D_C_P<0>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_TBT_B_D2R_P<0>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_TBT_B_D2R_N<0>

NC_TBT_B_D2R_P<1>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_TBT_B_R2D_C_N<1>

NO_TEST=TRUE

PCIE_SSD_R2D_C_N<1..0>

MAKE_BASE=TRUE

=PPVIN_S5_HS_COMPUTING_ISNS

=PPVIN_S5_HS_COMPUTING_ISNS_R

ISNS_HS_COMPUTING_N

ISNS_LCDBKLT_P

=PPBUS_SW_BKL

MAKE_BASE=TRUE

VOLTAGE=12.6V

PPBUS_SW_BKL

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.375 MM

MAKE_BASE=TRUE

PCIE_TBT_D2R_N<3>

SATA_ODD_R2D_C_P

DDRREG_PGOOD

MAKE_BASE=TRUE

PCIE_SSD_R2D_C_P<1..0>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SATA_ODD_D2RP

NC_SATA_ODD_R2DCN

NO_TEST=TRUE

MAKE_BASE=TRUE

USB_EXTD_EHCI_P

USB3_EXTD_TX_P

USB3_EXTD_RX_P

USB3_EXTC_TX_P

TP_DDRREG_PGOOD

MAKE_BASE=TRUE

NC_PCIE_6_R2D_CN

NC_PCIE_5_R2D_CN

NC_PCIE_5_D2RP

PCIE_TBT_D2R_N<2>

MAKE_BASE=TRUE

PCIE_TBT_D2R_N<0>

MAKE_BASE=TRUE

PCIE_TBT_D2R_N<1>

MAKE_BASE=TRUE

PCIE_TBT_D2R_P<2>

MAKE_BASE=TRUE

PCIE_TBT_D2R_P<3>

MAKE_BASE=TRUE

PCIE_TBT_R2D_C_N<1>

MAKE_BASE=TRUE

PCIE_TBT_R2D_C_N<0>

MAKE_BASE=TRUE

PCIE_TBT_R2D_C_P<3>

MAKE_BASE=TRUE

PCIE_TBT_R2D_C_P<0>

MAKE_BASE=TRUE

PCIE_TBT_R2D_C_P<1>

MAKE_BASE=TRUE

NC_PCIE_7_R2D_CP

NC_PCIE_5_R2D_CP

NC_PCIE_8_R2D_CN

NC_PCIE_7_R2D_CN

PCIE_TBT_R2D_C_N<3>

MAKE_BASE=TRUE

USB3_EXTC_TX_N

P1V5S3RS0_RAMP_DONE

NC_PCIE_8_R2D_CP

NC_PCIE_6_D2RP

PCIE_TBT_R2D_C_N<2>

MAKE_BASE=TRUE

NC_PCIE_6_R2D_CP

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_USB3_EXTC_TX_N

NO_TEST=TRUE

NC_USB3_EXTD_RX_P

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB3_EXTD_RX_N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB3_EXTD_TX_N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB_EXTD_EHCI_N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_IR_RX_OUT_RC

MAKE_BASE=TRUE

LVDS_IG_B_CLK_P

MEM_B_CLK_N<1>

USB3_EXTC_RX_P

TP_MEM_B_CLKP<1>

MAKE_BASE=TRUE

ENET_LOW_PWR_PCH

SATARDRVR_EN

TP_PCH_CLKOUT_DPN

SMC_SYS_LED

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SATA_ODD_D2RN

TP_DP_IG_D_HPD

NO_TEST=TRUE

NC_PEG_CLK100M_P

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCIE_ENET_D2R_N

TP_DP_IG_C_CTRL_CLK

DP_TBTSNK0_AUXCH_C_N

MAKE_BASE=TRUE

PPBUS_SW_LCDBKLT_PWR

MAKE_BASE=TRUE

DP_TBTSNK1_ML_C_P<3..0>

MAKE_BASE=TRUE

DP_TBTSNK0_ML_C_P<3..0>

MAKE_BASE=TRUE

=PP3V3_S0_DP_DDC

DP_TBTPB_ML_C_P<3>

DP_TBTPB_ML_C_N<3>

DP_TBTPB_AUXCH_C_P

DP_IG_D_CTRL_DATA

MAKE_BASE=TRUE

PCIE_FW_R2D_C_P

PCIE_EXCARD_D2R_N

PCIE_SSD_D2R_N<1..0>

MAKE_BASE=TRUE

PCIE_SSD_D2R_P<1..0>

SATA_ODD_D2R_P

TP_PCH_CLKOUT_DPP

DPLL_REF_CLK_N

MAKE_BASE=TRUE

XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH

MAKE_BASE=TRUE

DP_TBTSNK0_DDC_CLK

MAKE_BASE=TRUE

DP_TBTSNK0_DDC_DATA

NO_TEST=TRUE

NC_USB3_EXTD_TX_P

MAKE_BASE=TRUE

TP_LVDS_IG_B_CLKP

MAKE_BASE=TRUE

TBT_B_CIO_SEL

TBT_B_D2R_P<1>

ISNS_HS_COMPUTING_P

TBT_B_R2D_C_N<0>

MAKE_BASE=TRUE

NC_DP_TBTPB_ML_C_N<3>

DPB_IG_AUX_CH_P

DPA_IG_AUX_CH_N

DP_TBTSNK0_AUXCH_C_P

MAKE_BASE=TRUE

PCIE_TBT_D2R_P<0>

PCIE_TBT_R2D_C_P<2>

MAKE_BASE=TRUE

=DDRVTT_EN

MAKE_BASE=TRUE

DPB_IG_DDC_DATA

ISNS_LCDBKLT_N

MLB_RAMCFG2

LVDS_IG_B_CLK_N

LVDS_IG_BKL_ON

MAKE_BASE=TRUE

LCD_BKLT_PWM

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_A_DATAP<3>

MLB_RAMCFG3

USB3_EXTC_RX_N

NC_USB3_EXTC_RX_N

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB_EXTC_N

USB_EXTC_P

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SATA_ODD_R2DCP

PCIE_CLK100M_FW_N

PCIE_FW_D2R_N

SYNC_DATE=11/10/2011

SYNC_MASTER=J13_MLB_NON_POR

Signal Aliases

SM

POGO-2.0OD-3.6H-K86-K87

Z0910

1

Z0912

1

SL0900

1

Z0913

1

Z0911

1

Z0915

1

Z0914

1

Z0905

1

ZS0905

1

R0920

1

2

R0921

1

2

R0922

1

2

R0923

1

2

R0909

1

2

R0910

12 34

SL0901

1

SL0902

1

SL0905

1

R0954

12 34

R0953

1

2

R0952

1

2

R0951

1

2

R0950

1

2

R0917

1

2

R0918

1

2

R0919

1

2

R0914

1

2

R0916

1

2

SL0907

1

SL0903

1

SL0904

1

SL0908

1

R0925

1

2

R0924

1

2

SL0906

1

ZS0906

1

051-9277

2.8.0

9 OF 109

8 OF 73

10 66

11 67

17

16

7 8

17

16 23

10 66

19

17

26

34

17

16

17

34

6

11 67

34 69

65

17

34 70

34 69 17

17

34 69 17

17

34 69

17

34

63

65

34 69

16

34 69

16

34 69

16

34 69

16

11 67

19

16

17

34 69

65

34 69

7 8

34 70

16

19 23

64

6

34

17

34 69

26 56

17

19

17

65

19

IN

OUT

IN

OUT

IN

OUT

IN

NC

EDP_TX_3

EDP_TX_0 EDP_TX_1 EDP_TX_2

EDP_TX_2* EDP_TX_3*

EDP_TX_0* EDP_TX_1*

EDP_AUX

EDP_AUX*

EDP_COMPIO

EDP_HPD

EDP_ICOMPO

FDI1_LSYNC

DMI_TX_3*

FDI0_LSYNC

FDI0_TX_3

FDI1_TX_1

FDI1_TX_0

FDI1_TX_2 FDI1_TX_3

FDI0_FSYNC FDI1_FSYNC

FDI_INT

FDI1_TX_3*

FDI1_TX_2*

FDI0_TX_1

FDI0_TX_0

FDI0_TX_2

FDI1_TX_1*

FDI0_TX_3*

FDI1_TX_0*

FDI0_TX_2*

FDI0_TX_1*

DMI_TX_1* DMI_TX_2*

DMI_TX_0

DMI_TX_2

DMI_TX_1

DMI_TX_3

FDI0_TX_0*

DMI_RX_2*

DMI_RX_0 DMI_RX_1 DMI_RX_2 DMI_RX_3

DMI_TX_0*

DMI_RX_3*

DMI_RX_1*

DMI_RX_0*

PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO

PEG_RX_2*

PEG_RX_0* PEG_RX_1*

PEG_RX_3* PEG_RX_4* PEG_RX_5*

PEG_RX_7*

PEG_RX_6*

PEG_RX_8* PEG_RX_9*

PEG_RX_10*

PEG_RX_12*

PEG_RX_11*

PEG_RX_14*

PEG_RX_13*

PEG_RX_15*

PEG_RX_0 PEG_RX_1

PEG_RX_3

PEG_RX_2

PEG_RX_4

PEG_RX_6

PEG_RX_5

PEG_RX_7 PEG_RX_8

PEG_RX_10

PEG_RX_9

PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15

PEG_TX_1* PEG_TX_2*

PEG_TX_0*

PEG_TX_3* PEG_TX_4* PEG_TX_5*

PEG_TX_7*

PEG_TX_6*

PEG_TX_10*

PEG_TX_8* PEG_TX_9*

PEG_TX_11* PEG_TX_12* PEG_TX_13* PEG_TX_14* PEG_TX_15*

PEG_TX_1

PEG_TX_0

PEG_TX_2 PEG_TX_3 PEG_TX_4

PEG_TX_6

PEG_TX_5

PEG_TX_7 PEG_TX_8

PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12

PEG_TX_14

PEG_TX_13

PEG_TX_15

(1 OF 9)

PCI EXPRESS BASED INTERFACE SIGNALS

DMI

INTEL FLEXIBLE DISPLAY INTERFACE SIGNALS

EMBEDDED DISPLAY PORT

NC NC

RSVD_26 RSVD_27

RSVD_25

RSVD_23 RSVD_24

RSVD_22

RSVD_21

RSVD_19

RSVD_18

RSVD_16 RSVD_17

RSVD_15

RSVD_14

RSVD_13

RSVD_12

DC_TEST_BG1

DC_TEST_BD1

DC_TEST_BE1

DC_TEST_BG3 DC_TEST_BE3

DC_TEST_BG4

DC_TEST_BG58

DC_TEST_BG59

DC_TEST_BE59 DC_TEST_BG61

DC_TEST_BD61 DC_TEST_BE61

DC_TEST_D61

DC_TEST_A61 DC_TEST_C61

DC_TEST_A59 DC_TEST_C59

DC_TEST_A58

DC_TEST_D3 DC_TEST_D1

DC_TEST_C4

DC_TEST_A4

RSVD_45

RSVD_44

RSVD_41

RSVD_43

RSVD_42

RSVD_39 RSVD_40

RSVD_38

RSVD_36

RSVD_33

RSVD_31 RSVD_32

RSVD_30

CFG_3

CFG_2

CFG_1

CFG_0

CFG_9

CFG_8

CFG_7

CFG_6

CFG_14

CFG_12

CFG_10

CFG_16 CFG_17

VCC_VAL_SENSE

RSVD_8

RSVD_7

RSVD_6

CFG_15

CFG_13

CFG_11

CFG_5

CFG_4

VSS_VAL_SENSE

VAXG_VAL_SENSE

VCC_DIE_SENSE

VSSAXG_VAL_SENSE

RSVD_11

RSVD_9 RSVD_10

RSVD_20

RSVD_37

RSVD_35

RSVD_34

SB_DIMM_VREFDQ

SA_DIMM_VREFDQ

RESERVED

(5 OF 9)

NC NC NC

NC

OUT

S

D

G

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Intel Doc 467283 ChiefRiver Platform design guild rev0.71 section 2.2.12 recommendation.

NOTE: eDP_COMPIO and eDP_ICOMPO can not be left floating

Note. VOLTAGE=1.25V

Note. VOLTAGE=0V

FOR IVYBRIDGE PROCESSOR

CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED

This signal can be left as no-connect if entire eDP interface is disabled.

If HPD is disabled while eDP interface is still enabled,

(refer to latest Processor EDS for DC specifications).

Rise/Fall time <6ns

CR SFF Intel doc #460452

connect it to CPU VCCIo via a 10-kOhm pull-up resistor on the motherboard.

NOTE: Intel provides an internal pull-up OF 5-15k to VCCIO on all CFG signals.

this alnalog sense due to accuracy concern.

NOTE: Intel does not recommend to use

Note. VOLTAGE=0V

to low voltage signals for the processor

shared with other interfaces.

to convert the active high signal from Embedded DisplayPort sink device

Therefore, an inverting level shifter is required on the motherboard

NOTE: The EDP_HPD processor input is a low voltage active low signal.

even if internal Graphics is disabled since they are

Note. VOLTAGE=1.05V

NOTE: Intel validation sense lines per

doc 439028 rev1.0 HR_PPDG sections 6.2.1 and 6.3.1.

CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4

CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS

These can be Placed close to J2500 and Only for debug access

17 66

8

6

8

6

8

6

8

6

8

6

8

6

8

6

9

23 66

9

23 66

9

23 66

9

23 66

9

23 66

9

23 66

9

23 66

9

23 66

9

23

17 66

2C-35W

IVY-BRIDGE

BGA

OMIT_TABLE

CRITICAL

BGA

2C-35W

OMIT_TABLE

CRITICAL

IVY-BRIDGE

47 72

31

PLACE_NEAR=U1000.AG11:12.7MM

5%

1K

1/20W

201

MF

PLACE_NEAR=U1000.G3:12.7MM

24.9

1%

1/20W

MF

201

MF

201

1/20W

1%

24.9

PLACE_NEAR=U1000.AF3:12.7MM

2N7002TXG

SOT-523-3

EDP:YES

1K

NOSTUFF

5%

MF-LF

1/16W

402

5%

1K

NOSTUFF

MF-LF

1/16W

402

NOSTUFF

1K

5%

MF-LF

402

1/16W

5%

1K

MF-LF

1/16W

EDP:YES

402

5%

NOSTUFF

MF-LF

1/16W

1K

402

1/16W

MF-LF

5%

1K

402

NOSTUFF

1/16W

402

MF-LF

1K

5%

NOSTUFF

402

5%

1K

1/16W

MF-LF

NOSTUFF

PLACE_SIDE=BOTTOM

PLACE_NEAR=U1000.H45:50.8MM

49.9

1/16W

402

1%

MF-LF

NOSTUFF

PLACE_NEAR=U1000.H43:50.8MM PLACE_SIDE=BOTTOM

MF-LF

NOSTUFF

1%

402

1/16W

49.9

1%

PLACE_NEAR=U1000.K45:50.8MM

NOSTUFF

PLACE_SIDE=BOTTOM

MF-LF 402

1/16W

49.9

1/16W

PLACE_NEAR=U1000.K43:50.8MM

1%

NOSTUFF

MF-LF

402

49.9

PLACE_SIDE=BOTTOM

402

NOSTUFF

1/16W

MF-LF

5%

1K

SYNC_DATE=10/17/2011

CPU DMI/PEG/FDI/RSVD

SYNC_MASTER=J13_MLB_NON_POR

CPU_CFG<16>

CPU_PEG_COMP

=PEG_D2R_N<2>

=PEG_D2R_P<4>

=PEG_D2R_P<15>

TP_EDP_TX_P<2>

=PEG_R2D_C_P<6>

=PEG_R2D_C_P<9>

=PEG_R2D_C_N<10>

CPU_VCC_VALSENSE_P

CPU_CFG<4> CPU_CFG<5>

=PEG_D2R_N<9>

DP_INT_AUX_CH_P

CPU_VCC_VALSENSE_N

CPU_AXG_VALSENSE_N

CPU_CFG<0>

CPU_CFG<3>

CPU_CFG<2>

CPU_CFG<4>

CPU_CFG<5>

CPU_CFG<6>

CPU_CFG<7>

DP_INT_HPD

EDP_HPD_L

=PEG_D2R_N<14>

=PEG_D2R_P<8>

FDI_DATA_N<7>

FDI_DATA_P<5> FDI_DATA_P<6>

PPCPU_MEM_VREFDQ_A

MIN_LINE_WIDTH=0.3 MM

VOLTAGE=0.75V

MIN_NECK_WIDTH=0.2 MM

=PP1V05_S0_CPU_VCCIO

=PEG_R2D_C_P<14>

CPU_DC_TEST_C61_A61

=PEG_R2D_C_P<15>

=PP1V05_S0_CPU_VCCIO

=PEG_D2R_P<14>

=PP1V05_S0_CPU_VCCIO

=PEG_D2R_P<7>

=PEG_D2R_P<5>

CPU_CFG<6>

CPU_CFG<0>

=PEG_R2D_C_P<1>

=PEG_D2R_N<6>

=PEG_D2R_N<5>

CPU_THERMD_N

CPU_THERMD_P

=PEG_D2R_P<10> =PEG_D2R_P<11> =PEG_D2R_P<12>

CPU_DC_TEST_C59_A59

=PEG_D2R_P<13>

FDI_INT

FDI_FSYNC<0>

DMI_S2N_N<0>

=PEG_R2D_C_P<2>

CPU_CFG<17>

CPU_DC_TEST_C4_BE1_BG1

TP_CPU_DC_TEST_BD1

CPU_DC_TEST_C4_BE3_BG3

TP_CPU_DC_TEST_BG4

TP_CPU_DC_TEST_BG58

CPU_DC_TEST_BG59_BG61

CPU_DC_TEST_BE59_BE61

TP_CPU_DC_TEST_BD61

TP_CPU_DC_TEST_D61

TP_CPU_DC_TEST_D1

TP_CPU_DC_TEST_A4

CPU_CFG<3>

CPU_CFG<2>

CPU_CFG<1>

CPU_CFG<9>

CPU_CFG<8>

CPU_CFG<7>

CPU_CFG<14>

CPU_CFG<12>

CPU_CFG<10>

CPU_CFG<16>

CPU_CFG<15>

CPU_CFG<13>

CPU_CFG<11>

TP_CPU_VCC_DIE_SENSE

FDI_LSYNC<1>

=PEG_R2D_C_P<13>

=PEG_R2D_C_P<7>

=PEG_R2D_C_P<3>

=PEG_R2D_C_N<9>

=PEG_R2D_C_N<8>

=PEG_R2D_C_N<6> =PEG_R2D_C_N<7>

=PEG_R2D_C_N<5>

=PEG_R2D_C_N<4>

=PEG_R2D_C_N<3>

=PEG_R2D_C_N<0>

=PEG_R2D_C_N<2>

=PEG_R2D_C_N<1>

=PEG_D2R_P<9>

=PEG_D2R_P<6>

=PEG_D2R_P<2> =PEG_D2R_P<3>

=PEG_D2R_P<1>

=PEG_D2R_N<15>

=PEG_D2R_N<13>

=PEG_D2R_N<12>

=PEG_D2R_N<8>

=PEG_D2R_N<7>

=PEG_D2R_N<4>

=PEG_D2R_N<3>

=PEG_D2R_N<1>

=PEG_D2R_N<0>

DMI_S2N_N<1>

DMI_S2N_N<3>

DMI_N2S_N<0>

DMI_S2N_P<3>

DMI_S2N_P<2>

DMI_S2N_P<1>

DMI_S2N_P<0>

DMI_S2N_N<2>

FDI_DATA_N<0>

DMI_N2S_P<3>

DMI_N2S_P<1> DMI_N2S_P<2>

DMI_N2S_P<0>

DMI_N2S_N<2>

DMI_N2S_N<1>

FDI_DATA_N<1> FDI_DATA_N<2> FDI_DATA_N<3>

FDI_DATA_P<2>

FDI_DATA_P<0> FDI_DATA_P<1>

FDI_DATA_N<6>

FDI_FSYNC<1>

FDI_DATA_P<4>

FDI_DATA_P<3>

FDI_LSYNC<0>

FDI_DATA_N<4>

=PEG_D2R_P<0>

=PEG_D2R_N<11>

PPCPU_MEM_VREFDQ_B

VOLTAGE=0.75V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.3 MM

=PEG_R2D_C_P<10>

EDP_HPD_L

EDP_COMP

TP_EDP_TX_P<3>

TP_EDP_TX_P<1>

DP_INT_ML_P<0>

TP_EDP_TX_N<3>

TP_EDP_TX_N<2>

DP_INT_AUX_CH_N

DP_INT_ML_N<0> TP_EDP_TX_N<1>

=PEG_R2D_C_P<11>

DMI_N2S_N<3>

TP_CPU_DC_TEST_A58

CPU_DC_TEST_C4_D3

=PEG_R2D_C_P<12>

=PEG_R2D_C_P<5>

FDI_DATA_P<7>

FDI_DATA_N<5>

CPU_AXG_VALSENSE_P

=PPVCORE_S0_CPU_VCCAXG

=PPVCORE_S0_CPU

=PEG_D2R_N<10>

=PEG_R2D_C_N<11> =PEG_R2D_C_N<12> =PEG_R2D_C_N<13> =PEG_R2D_C_N<14> =PEG_R2D_C_N<15>

=PEG_R2D_C_P<0>

=PEG_R2D_C_P<4>

=PEG_R2D_C_P<8>

CPU_CFG<1>

U1000

N3

M2

P7

P6

P3

P1

P11

P10

K3

K1

M7

M8

P4

N4

T3

R2

AF4

AG4

AF3

AG11

AD2

AC1

AC3

AA4

AC4

AE10

AE11

AE6

AE7

AA11

AA10

U6

U7

W10

W11

W3

W1

AA7

AA6

AC12

AG8

W7

W6

T4

V4

AA3

Y2

AC8

AC9

U11

G3 G1 G4

K22

H22

K19

J21

F8

G8

C8

A8

C5

B6

H6

H8

F6

E5

K6

K7

C21

B22

D19

D21

C19

A19

D16

D17

C13

B14

D12

D13

C11

A11

C9

B10

F22

G22

A23

C23

K13

J14

G13

H13

K10

M10

G10

F10

D8

D9

K4

J4

D24

D23

E21

F21

G19

H19

B18

C17

K17

K15

G17

F17

E14

F14

C15

A15

U1000

B50 C51

K49 K53 F53 G53 L51 F51 D52 L53

B54 D53 A51 C53 C55 H49 A55 H51

A4

A58 A59

A61

BD1

BD61

BE1

BE3

BE59

BE61

BG1

BG3

BG4

BG58

BG59

BG61

C4

C59

C61

D1

D3

D61

AG13

AH2

AM14 AM15

AT21

AT49

AU19 AU21

AV19

AY21

AY22

BA19

BA22

BB19

BB21

BD21 BD22 BD25 BD26

BE22

BE24

BE26 BF23

BG22

BG26

H48

K24

K48

L42 L45 L47

M13 M14

N42

N50

P13

U14 W14

BE7 BG7

H45

F48

H43 K43

K45

R1031

1

2

R1010

12

R1030

12

Q1031

3

1

2

R1047

1

2

R1046

1

2

R1045

1

2

R1044

1

2

R1042

1

2

R1043

1

2

R1041

1

2

R1040

1

2

R1070

1

2

R1064

1

2

R1071

1

2

R1065

1

2

R1049

1

2

051-9277

2.8.0

10 OF 109

9 OF 73

9

23

66

6

63 66

9

23 66

9

23 66

9

23 66

9

23 66

9

23 66

9

23 66

9

23 66

63

9

7 9

10 12 14

7 9

10 12 14

7 9

10 12 14

9

66

6

63 66

6

63 66

6

7

12 15

7

12 14

9

23 66

IN

OUT

BI

IN

BI

NC

SM_RCOMP_2

SM_RCOMP_1

SM_RCOMP_0

SM_DRAMRST*

BCLK_ITP

BCLK_ITP*

DPLL_REF_CLK*

DPLL_REF_CLK

BCLK*

BCLK

RESET*

SM_DRAMPWROK

UNCOREPWRGOOD

PM_SYNC

PROC_SELECT*

PROC_DETECT*

PREQ*

TMS

TRST*

TDI TDO

DBR*

BPM_0* BPM_1* BPM_2* BPM_3* BPM_4* BPM_5* BPM_6* BPM_7*

TCK

PRDY*

THERMTRIP*

CATERR*

PROCHOT*

PECI

(2 OF 9)

CLOCKS

THERMAL

PWR MGMT

JTAG & BPM

DDR3 MISC

IN

OUT

BI

OUT

IN

OUT

IN

BI

IN

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(IPU) (IPU)

(IPU)

Intel Doc 460452 ChiefRiver SFF DG rev1.0 section 2.7.11 recommendation R1115.

16 66

23 66

23 25 66

23 66

16 66

23 66

BGA

2C-35W

IVY-BRIDGE

OMIT_TABLE

CRITICAL

201

MF

1/20W

5%

1K

NOSTUFFNOSTUFF

51

5% 1/20W MF 201

1K

5%

1/20W

MF

201

NOSTUFF

PLACE_NEAR=U1000.B46:12.7MM

5% 1/20W MF 201

10K

8

66

NOSTUFF

201

1%

4.99K

MF

1/20W

PLACE_NEAR=U1000.BG43:12.7MM

201

200

1/20W MF

1%

PLACE_NEAR=U1000.BE43:12.7MM

25.5

MF 201

1/20W

1%

19

41 66

19 42 66

19 23 66

17 66

26

16 66

PLACE_NEAR=U1000.BE45:12.7MM

130

201

MF

1/20W

1%

201

MF

1/20W

5%

62

56

5%

1/20W

MF

201

PLACE_NEAR=R1121.2:1MM

201

MF

1/20W

1%

200

41 42 57 66

PLACE_NEAR=U1000.BF44:12.7MM

201

MF

1/20W

1%

140

201

1/20W

MF

1%

43.2

201

MF

1/20W

1%

75

17 26 66

8

66

23 25

16 66

23 66

CPU CLOCK/MISC/JTAG

SYNC_MASTER=J30_MLB

SYNC_DATE=07/27/2011

XDP_CPU_PRDY_L

XDP_CPU_TCK

XDP_BPM_L<7>

XDP_BPM_L<6>

XDP_BPM_L<5>

XDP_BPM_L<4>

XDP_BPM_L<3>

XDP_BPM_L<2>

XDP_BPM_L<1>

XDP_BPM_L<0>

XDP_DBRESET_L

XDP_CPU_TDO

XDP_CPU_TDI

XDP_CPU_TRST_L

XDP_CPU_TMS

XDP_CPU_PREQ_L

DMI_CLK100M_CPU_P DMI_CLK100M_CPU_N

DPLL_REF_CLKP DPLL_REF_CLKN

ITPCPU_CLK100M_N

ITPCPU_CLK100M_P

CPU_PECI

CPU_CATERR_L

PM_THRMTRIP_L

=MEM_RESET_L

CPU_PROCHOT_R_L

CPU_PROC_SEL_L

PM_SYNC

CPU_SM_RCOMP<0>

PLT_RESET_LS1V1_L

=PP1V05_S0_CPU_VCCIO

CPU_RESET_L

=PP1V5_S3_CPU_VCCDDR

CPU_PROCHOT_L

PM_MEM_PWRGD

=PP1V05_S0_CPU_VCCIO

CPU_PWRGD

CPU_SM_RCOMP<2>

CPU_SM_RCOMP<1>

PM_MEM_PWRGD_R

U1000

J3 H2

N59 N58

G58 E55 E59 G55 G59 H60 J59 J61

C49

K58

AG3 AG1

A48

C48

N53 N55

C57

F49

C45

D44

BE45

AT30

BF44 BE43 BG43

L56

M60 L59

D45

L55 J58

B46

R1102

1

2

R1104

1

2

R1100

1

2

R1111

1

2

R1115

1

2

R1114

1

2

R1113

1

2

R1121

12

R1101

1

2

R1103

12

R1120

1

2

R1112

1

2

R1125

12

R1126

1

2

051-9277

2.8.0

11 OF 109

10 OF 73

66

7 9

10 12 14

7

12 15 26

7 9

10 12 14

66

BI

OUT

BI

OUT

BI

OUT

BI

OUT

SA_MA_14 SA_MA_15

SA_MA_12 SA_MA_13

SA_MA_11

SA_MA_9

SA_MA_10

SA_MA_8

SA_MA_7

SA_MA_6

SA_MA_5

SA_MA_4

SA_MA_3

SA_MA_2

SA_MA_1

SA_MA_0

SA_DQS_7

SA_DQS_5 SA_DQS_6

SA_DQS_3 SA_DQS_4

SA_DQS_2

SA_DQS_0 SA_DQS_1

SA_DQS_7*

SA_DQS_6*

SA_DQS_5*

SA_DQS_4*

SA_DQS_3*

SA_DQS_2*

SA_DQS_0* SA_DQS_1*

SA_ODT_1

SA_ODT_0

SA_CS_1*

SA_CS_0*

SA_CKE_1

SA_CK_1*

SA_CK_1

SA_CKE_0

SA_CK_0*

SA_CK_0

SA_WE*

SA_RAS*

SA_CAS*

SA_BS_0 SA_BS_1 SA_BS_2

SA_DQ_62 SA_DQ_63

SA_DQ_61

SA_DQ_60

SA_DQ_59

SA_DQ_58

SA_DQ_57

SA_DQ_56

SA_DQ_55

SA_DQ_54

SA_DQ_53

SA_DQ_52

SA_DQ_50 SA_DQ_51

SA_DQ_49

SA_DQ_48

SA_DQ_47

SA_DQ_46

SA_DQ_45

SA_DQ_44

SA_DQ_42 SA_DQ_43

SA_DQ_41

SA_DQ_39 SA_DQ_40

SA_DQ_38

SA_DQ_37

SA_DQ_36

SA_DQ_34 SA_DQ_35

SA_DQ_31

SA_DQ_33

SA_DQ_32

SA_DQ_29 SA_DQ_30

SA_DQ_26

SA_DQ_28

SA_DQ_27

SA_DQ_24 SA_DQ_25

SA_DQ_23

SA_DQ_22

SA_DQ_21

SA_DQ_19 SA_DQ_20

SA_DQ_18

SA_DQ_17

SA_DQ_16

SA_DQ_13 SA_DQ_14 SA_DQ_15

SA_DQ_11 SA_DQ_12

SA_DQ_9 SA_DQ_10

SA_DQ_8

SA_DQ_7

SA_DQ_6

SA_DQ_5

SA_DQ_4

SA_DQ_3

SA_DQ_2

SA_DQ_1

SA_DQ_0

(3 OF 9)

MEMORY CHANNEL A

SB_MA_15

SB_MA_14

SB_MA_12 SB_MA_13

SB_MA_11

SB_MA_10

SB_MA_9

SB_MA_7 SB_MA_8

SB_MA_6

SB_MA_5

SB_MA_4

SB_MA_3

SB_MA_2

SB_MA_1

SB_MA_0

SB_DQS_7

SB_DQS_6

SB_DQS_5

SB_DQS_4

SB_DQS_3

SB_DQS_2

SB_DQS_1

SB_DQS_0

SB_DQS_7*

SB_DQS_6*

SB_DQS_5*

SB_DQS_4*

SB_DQS_3*

SB_DQS_2*

SB_DQS_1*

SB_DQS_0*

SB_ODT_0 SB_ODT_1

SB_CS_1*

SB_CS_0*

SB_CKE_1

SB_CK_1

SB_CK_1*

SB_CK_0*

SB_CKE_0

SB_CK_0

SB_DQ_37

SB_DQ_36

SB_DQ_34 SB_DQ_35

SB_DQ_33

SB_DQ_31 SB_DQ_32

SB_DQ_30

SB_DQ_29

SB_DQ_26 SB_DQ_27 SB_DQ_28

SB_DQ_24 SB_DQ_25

SB_DQ_21 SB_DQ_22 SB_DQ_23

SB_DQ_20

SB_DQ_19

SB_DQ_18

SB_DQ_17

SB_DQ_16

SB_DQ_15

SB_DQ_14

SB_DQ_13

SB_DQ_12

SB_DQ_11

SB_DQ_10

SB_DQ_8 SB_DQ_9

SB_DQ_7

SB_DQ_6

SB_DQ_4 SB_DQ_5

SB_DQ_3

SB_DQ_2

SB_DQ_1

SB_DQ_0

SB_DQ_39

SB_DQ_38

SB_DQ_40 SB_DQ_41 SB_DQ_42

SB_DQ_44

SB_DQ_43

SB_DQ_46

SB_DQ_45

SB_DQ_47

SB_DQ_49

SB_DQ_48

SB_DQ_51

SB_DQ_50

SB_DQ_52

SB_DQ_54

SB_DQ_53

SB_DQ_56

SB_DQ_55

SB_DQ_57

SB_DQ_59

SB_DQ_58

SB_DQ_61

SB_DQ_60

SB_DQ_62

SB_BS_0

SB_DQ_63

SB_BS_2

SB_BS_1

SB_RAS*

SB_CAS*

SB_WE*

(4 OF 9)

MEMORY CHANNEL B

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

27 67

28 67

27 28 32 67

29 67

30 67

29 30 32 67

27 28 32 67

8

67

8

67

27 28 32 67

27 67

28 67

27 67

28 67

27 28 32 67

29 30 32 67

8

67

8

67

29 30 32 67

29 67

30 67

29 67

30 67

29 30 32 67

2C-35W

IVY-BRIDGE

BGA

OMIT_TABLE

CRITICAL

BGA

IVY-BRIDGE

2C-35W

OMIT_TABLE

CRITICAL

CPU DDR3 INTERFACES

SYNC_DATE=07/27/2011

SYNC_MASTER=J30_MLB

MEM_A_DQ<3>

MEM_A_CLK_P<0>

MEM_B_A<15>

MEM_B_A<14>

MEM_B_A<12> MEM_B_A<13>

MEM_B_A<11>

MEM_B_A<10>

MEM_B_A<9>

MEM_B_A<7> MEM_B_A<8>

MEM_B_A<6>

MEM_B_A<5>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_A<2>

MEM_B_A<1>

MEM_B_A<0>

MEM_B_DQS_P<7>

MEM_B_DQS_P<6>

MEM_B_DQS_P<5>

MEM_B_DQS_P<4>

MEM_B_DQS_P<3>

MEM_B_DQS_P<2>

MEM_B_DQS_P<1>

MEM_B_DQS_P<0>

MEM_B_DQS_N<7>

MEM_B_DQS_N<6>

MEM_B_DQS_N<5>

MEM_B_DQS_N<4>

MEM_B_DQS_N<3>

MEM_B_DQS_N<2>

MEM_B_DQS_N<1>

MEM_B_DQS_N<0>

MEM_B_ODT<0> MEM_B_ODT<1>

MEM_B_CS_L<1>

MEM_B_CS_L<0>

MEM_B_CKE<1>

MEM_B_CLK_P<1> MEM_B_CLK_N<1>

MEM_B_CLK_N<0>

MEM_B_CKE<0>

MEM_B_CLK_P<0>

MEM_B_DQ<37>

MEM_B_DQ<36>

MEM_B_DQ<34> MEM_B_DQ<35>

MEM_B_DQ<33>

MEM_B_DQ<31> MEM_B_DQ<32>

MEM_B_DQ<30>

MEM_B_DQ<29>

MEM_B_DQ<26> MEM_B_DQ<27> MEM_B_DQ<28>

MEM_B_DQ<24> MEM_B_DQ<25>

MEM_B_DQ<21> MEM_B_DQ<22> MEM_B_DQ<23>

MEM_B_DQ<20>

MEM_B_DQ<19>

MEM_B_DQ<18>

MEM_B_DQ<17>

MEM_B_DQ<16>

MEM_B_DQ<15>

MEM_B_DQ<14>

MEM_B_DQ<13>

MEM_B_DQ<12>

MEM_B_DQ<11>

MEM_B_DQ<10>

MEM_B_DQ<8> MEM_B_DQ<9>

MEM_B_DQ<7>

MEM_B_DQ<6>

MEM_B_DQ<4> MEM_B_DQ<5>

MEM_B_DQ<3>

MEM_B_DQ<2>

MEM_B_DQ<1>

MEM_B_DQ<0>

MEM_B_DQ<39>

MEM_B_DQ<38>

MEM_B_DQ<40> MEM_B_DQ<41> MEM_B_DQ<42>

MEM_B_DQ<44>

MEM_B_DQ<43>

MEM_B_DQ<46>

MEM_B_DQ<45>

MEM_B_DQ<47>

MEM_B_DQ<49>

MEM_B_DQ<48>

MEM_B_DQ<51>

MEM_B_DQ<50>

MEM_B_DQ<52>

MEM_B_DQ<54>

MEM_B_DQ<53>

MEM_B_DQ<56>

MEM_B_DQ<55>

MEM_B_DQ<57>

MEM_B_DQ<59>

MEM_B_DQ<58>

MEM_B_DQ<61>

MEM_B_DQ<60>

MEM_B_DQ<62>

MEM_B_BA<0>

MEM_B_DQ<63>

MEM_B_BA<2>

MEM_B_BA<1>

MEM_B_RAS_L

MEM_B_CAS_L

MEM_B_WE_L

MEM_A_A<14> MEM_A_A<15>

MEM_A_A<12> MEM_A_A<13>

MEM_A_A<11>

MEM_A_A<9> MEM_A_A<10>

MEM_A_A<8>

MEM_A_A<7>

MEM_A_A<6>

MEM_A_A<5>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_A<2>

MEM_A_A<1>

MEM_A_A<0>

MEM_A_DQS_P<7>

MEM_A_DQS_P<5> MEM_A_DQS_P<6>

MEM_A_DQS_P<3> MEM_A_DQS_P<4>

MEM_A_DQS_P<2>

MEM_A_DQS_P<0> MEM_A_DQS_P<1>

MEM_A_DQS_N<7>

MEM_A_DQS_N<6>

MEM_A_DQS_N<5>

MEM_A_DQS_N<4>

MEM_A_DQS_N<3>

MEM_A_DQS_N<2>

MEM_A_DQS_N<0> MEM_A_DQS_N<1>

MEM_A_ODT<1>

MEM_A_ODT<0>

MEM_A_CS_L<1>

MEM_A_CS_L<0>

MEM_A_CKE<1>

MEM_A_CLK_N<1>

MEM_A_CLK_P<1>

MEM_A_CKE<0>

MEM_A_CLK_N<0>

MEM_A_WE_L

MEM_A_RAS_L

MEM_A_CAS_L

MEM_A_BA<0> MEM_A_BA<1> MEM_A_BA<2>

MEM_A_DQ<62> MEM_A_DQ<63>

MEM_A_DQ<61>

MEM_A_DQ<60>

MEM_A_DQ<59>

MEM_A_DQ<58>

MEM_A_DQ<57>

MEM_A_DQ<56>

MEM_A_DQ<55>

MEM_A_DQ<54>

MEM_A_DQ<53>

MEM_A_DQ<52>

MEM_A_DQ<50> MEM_A_DQ<51>

MEM_A_DQ<49>

MEM_A_DQ<48>

MEM_A_DQ<47>

MEM_A_DQ<46>

MEM_A_DQ<45>

MEM_A_DQ<44>

MEM_A_DQ<42> MEM_A_DQ<43>

MEM_A_DQ<41>

MEM_A_DQ<39> MEM_A_DQ<40>

MEM_A_DQ<38>

MEM_A_DQ<37>

MEM_A_DQ<36>

MEM_A_DQ<34> MEM_A_DQ<35>

MEM_A_DQ<31>

MEM_A_DQ<33>

MEM_A_DQ<32>

MEM_A_DQ<29> MEM_A_DQ<30>

MEM_A_DQ<26>

MEM_A_DQ<28>

MEM_A_DQ<27>

MEM_A_DQ<24> MEM_A_DQ<25>

MEM_A_DQ<23>

MEM_A_DQ<22>

MEM_A_DQ<21>

MEM_A_DQ<19> MEM_A_DQ<20>

MEM_A_DQ<18>

MEM_A_DQ<17>

MEM_A_DQ<16>

MEM_A_DQ<13> MEM_A_DQ<14> MEM_A_DQ<15>

MEM_A_DQ<11> MEM_A_DQ<12>

MEM_A_DQ<9> MEM_A_DQ<10>

MEM_A_DQ<8>

MEM_A_DQ<7>

MEM_A_DQ<6>

MEM_A_DQ<5>

MEM_A_DQ<4>

MEM_A_DQ<2>

MEM_A_DQ<1>

MEM_A_DQ<0>

U1000

BD37 BF36 BA28

BE39

AU36 AV36

AT40 AU40

AY26

BB26

BB40 BC41

AG6 AJ6

AU6 AV9 AR6

AP8 AT13 AU13

BC7

BB7 BA13 BB11

AP11

BA7

BA9

BB9 AY13 AV14 AR14 AY17 AR19 BA14 AU14

AL6

BB14 BB17 BA45 AR43 AW48 BC48 BC45 AR45 AT48 AY48

AJ10

BA49 AV49 BB51 AY53 BB49 AU49 BA53 BB55 BA55 AV56

AJ8

AP50 AP53 AV54 AT54 AP56 AP52 AN57 AN53 AG56 AG53

AL8

AN55 AN52 AG55 AK56

AL7 AR11

AP6

AJ11

AL11

AR10

AR8

AY11

AV11

AU17

AT17

AW45

AV45

AV51

AY51

AT56

AT55

AK54

AK55

BG35 BB34

BE37 BA30 BC30 AW41 AY28 AU26

BE35 BD35 AT34 AU34 BB32 AT32 AY32 AV32

AY40 BA41

BD39 AT41

U1000

BG39 BD42 AT22

AV43

BA34 AY34

BA36 BB36

AR22

BF27

BE41 BE47

AL4 AL1

AV4 BA4 AU3 AR3 AY2 BA3 BE9

BD9 BD13 BF12

AN3

BF8 BD10 BD14 BE13 BF16 BE17 BE18 BE21 BE14 BG14

AR4

BG18 BF19 BD50 BF48 BD53 BF52 BD49 BE49 BD54 BE53

AK4

BF56 BE57 BC59 AY60 BE54 BG54 BA58 AW59 AW58 AU58

AK3

AN61 AN59 AU59 AU61 AN58 AR58 AK58 AL58 AG58 AG59

AN4

AM60 AL59 AF61 AH60

AR1

AU4

AT2

AM2

AL3

AV1

AV3

BE11

BG11

BD18

BD17

BE51

BG51

BA61

BA59

AR59

AT60

AK61

AK59

BF32 BE33

BD43 AT28 AV28 BD46 AT26 AU22

BD33 AU30 BD30 AV30 BG30 BD29 BE30 BE28

AT43 BG47

BF40 BD45

051-9277

2.8.0

12 OF 109

11 OF 73

OUT

IN

BI

OUT

VCCIO_29

VCCIO_28

VCCIO_27

VCCIO_26

VCCIO_25

VCCIO_24

VCCIO_23

VCCIO_22

VCCIO_21

VCCIO_20

VCCIO_19

VCCIO_18

VCCIO_17

VCCIO_16

VCCIO_15

VCCIO_14

VCCIO_13

VCCIO_12

VCCIO_11

VCCIO_10

VCCIO_9

VCCIO_8

VCCIO_7

VCCIO_6

VCCIO_49

VCCIO_48

VCCIO_5

VCCIO_4

VCCIO_3

VCCIO_47

VCCIO_46

VCCIO_45

VCCIO_44

VCCIO_43

VCCIO_1

VCCIO_42

VCCIO_41

VCCIO_40

VCCIO_39

VCCIO_38

VCCIO_37

VCCIO_36

VCCIO_35

VCCIO_34

VCCIO_33

VCCIO_32

VCCIO_31

VCCIO_30

VCCIO_51

VCCIO_50

VCC_76

VCC_75

VCC_74

VCC_73

VCC_72

VCC_71

VCC_70

VCC_69

VCC_68

VCC_67

VCC_66

VCC_64

VCC_63

VCC_62

VCC_61

VCC_60

VCC_59

VCC_58

VCC_57

VCC_56

VCC_55

VCC_54

VCC_53

VCC_52

VCC_51

VCC_50

VCC_49

VCC_48

VCC_47

VCC_46

VCC_45

VCC_44

VCC_43

VCC_42

VCC_41

VCC_40

VCC_39

VCC_38

VCC_37

VCC_36

VCC_35

VCC_34

VCC_33

VCC_32

VCC_31

VCC_30

VCC_29

VCC_28

VCC_27

VCC_26

VCC_25

VCC_24

VCC_23

VCC_22

VCC_21

VCC_20

VCC_19

VCC_18

VCC_17

VCC_16

VCC_15

VCC_14

VCC_13

VCC_12

VCC_11

VCC_10

VCC_9

VCC_8

VCC_7

VCC_6

VCC_5

VCC_4

VCC_3

VCC_2

VCC_1

VCCIO_SEL

VCCPQE_1 VCCPQE_2

VIDALERT*

VIDSCLK VIDSOUT

VCC_SENSE VSS_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

LINES

SENSE SVID QUIET

RAIL

PEG AND DDR

CORE SUPLLY

(6 OF 9)

(7 OF 9)

SENSE

LINE

1.8V

RAIL

SA RAIL

QUIET

RAIL

SENSE

LINE

DDR3-1.5V RAILS

GRPHICS

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8

VDDQ_10

VDDQ_9

VDDQ_11 VDDQ_12 VDDQ_13 VDDQ_14 VDDQ_15 VDDQ_16 VDDQ_17 VDDQ_18

VDDQ_20

VDDQ_19

VDDQ_21 VDDQ_22 VDDQ_23 VDDQ_24 VDDQ_25 VDDQ_26

VCCDQ_1 VCCDQ_2

VDDQ_SENSE

VSS_SENSE_VDDQ

VCCSA_SENSE

VCCSA_VID_0 VCCSA_VID_1

SM_VREF

VAXG_1 VAXG_2

VAXG_4

VAXG_3

VAXG_5 VAXG_6 VAXG_7 VAXG_8 VAXG_9 VAXG_10 VAXG_11 VAXG_12 VAXG_13 VAXG_14 VAXG_15 VAXG_16 VAXG_17 VAXG_18 VAXG_19 VAXG_20 VAXG_21 VAXG_22 VAXG_23 VAXG_24 VAXG_25

VAXG_28

VAXG_26 VAXG_27

VAXG_30

VAXG_29

VAXG_33

VAXG_31 VAXG_32

VAXG_35

VAXG_34

VAXG_36 VAXG_37 VAXG_38 VAXG_39 VAXG_40 VAXG_41 VAXG_42 VAXG_43

VAXG_45

VAXG_44

VAXG_46 VAXG_47 VAXG_48 VAXG_49 VAXG_50 VAXG_51 VAXG_52 VAXG_53 VAXG_54 VAXG_55 VAXG_56

VAXG_SENSE VSSAXG_SENSE

VCCPLL_1 VCCPLL_2 VCCPLL_3

VCCSA_2

VCCSA_1

VCCSA_3 VCCSA_4 VCCSA_5 VCCSA_6 VCCSA_7 VCCSA_8 VCCSA_9 VCCSA_10 VCCSA_11 VCCSA_12 VCCSA_13

VCCSA_15

VCCSA_14

VCCSA_16

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

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NOTICE OF PROPRIETARY PROPERTY:

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D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.

Note. VOLTAGE=0V

Note. VOLTAGE=1.05V

Note. VOLTAGE=0V

Note. VOLTAGE=1.05V

Note. VOLTAGE=0V

PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.

Note. VOLTAGE=1.25V

(IPU)

(NOT controlled by VCCIO_SEL)

Note. VOLTAGE=1.05V

Note. VOLTAGE=0V

VCCIO_SEL can be NC.

IVB supports 1.05V VCCIO.

Fixed at 1.05V

(IPU)

57 66

59 66

54

201

MF

1%

75

1/20W

PLACE_NEAR=U7400.17:2.54mm

PLACE_NEAR=U1000.A44:38mm

201

MF435%

1/20W

MF5%

0

201

1/20W

MF5%

0

57 66

201

1/20W

10K

5%

MF

201

1/20W

MF

5%

10K

54

IVY-BRIDGE

2C-35W

BGA

CRITICAL

OMIT_TABLE

CRITICAL

OMIT_TABLE

BGA

IVY-BRIDGE

2C-35W

10% 16V X5R-CERM

0.1UF

0201

PLACE_NEAR=U1000.AY43:2.54mm

PLACE_NEAR=U1000.C44:2.54mm 1/20W MF

1%

130

201

PLACE_NEAR=U1000.F43:50.8mm

PLACE_SIDE=BOTTOM

MF-LF

100

1%

1/16W

402

PLACE_NEAR=U1000.AN16:50.8mm

1%

PLACE_SIDE=BOTTOM

1/16W

402

MF-LF

100

PLACE_SIDE=BOTTOM

PLACE_NEAR=U1000.G43:50.8mm

1%

MF-LF

1/16W

402

MF-LF

100

1% 1/16W

402

PLACE_SIDE=BOTTOM

PLACE_NEAR=U1000.AN17:50.8mm

PLACE_SIDE=BOTTOM

1%

100

MF-LF

1/16W

PLACE_NEAR=U1000.F45:50.8mm

402

100

1%

PLACE_NEAR=U1000.G45:50.8mm

PLACE_SIDE=BOTTOM

MF-LF

1/16W

402

MF

1/20W

1%

100

PLACE_NEAR=U1000.BC43:50.8mm

PLACE_SIDE=BOTTOM

201

PLACE_NEAR=U1000.U10:50.8mm

100

1%

MF

1/20W

PLACE_NEAR=U1000.BA43:50.8mm

201

MF

100

1%

1/20W

PLACE_SIDE=BOTTOM

1K

5%

1/20W

MF

201

PLACE_NEAR=U1000.AY43:2.54mm

1K

5%

1/20W

MF

201

PLACE_NEAR=U1000.AY43:2.54mm

1/20W

NOSTUFF

201

MF

5%

10K

SYNC_MASTER=J13_MLB_NON_POR

SYNC_DATE=11/10/2011

CPU POWER

CPU_VCCSENSE_N

CPU_VCCIOSENSE_N

CPU_VIDALERT_L_R

CPU_VCCIOSENSE_P

CPU_VCCSA_VID<1>

CPU_DDR_VREF

VOLTAGE=0.75V

CPU_AXG_SENSE_N

CPU_AXG_SENSE_P

CPU_VIDALERT_L

=PPVCCSA_S0_CPU

=PP1V05_S0_CPU_VCCIO

CPU_VIDSCLK

CPU_VIDSOUT_R

=PP1V05_S0_CPU_VCCIO

=PPVCORE_S0_CPU

=PPVCORE_S0_CPU_VCCAXG

=PP1V05_S0_CPU_VCCIO

CPU_VCCIO_SEL

=PP3V3_S0_CPU_VCCIO_SEL

CPU_DDR_VREF

=PP1V5_S3_CPU_VCCDDR

CPU_VDDQ_SENSE_N

=PPVCCSA_S0_CPU

CPU_VCCSASENSE

=PP1V5_S3_CPU_VCCDDR

CPU_VDDQ_SENSE_P

=PPVCORE_S0_CPU

CPU_VCCSENSE_P

=PP1V5_S3_CPU_VCCDQ

=PP1V8_S0_CPU_VCCPLL_R

=PP1V05_S0_CPU_VCCPQE

CPU_VIDSCLK_R

CPU_VIDSOUT

=PP1V5_S3_CPU_VCCDDR

CPU_VCCSA_VID<0>

R1300

1

2

R1310

12

R1311

12

R1312

12

R1314

1

2

R1313

1

2

U1000

A26 A29 A31 A34 A35 A38 A39 A42 C26 C27 C32 C34 C37 C39 C42 D27 D32 D34 D37 D39 D42 E26 E28 E32 E34 E37 E38 F25 F26 F28 F32 F34 F37 F38 F42 G42 H25 H26 H28 H29 H32 H34 H35 H37 H38 H40 J25 J26 J28 J29 J32 J34 J35 J37 J38 J40 J42 K26 K27 K29 K32 K34 K35 K37 K39 K42 L25 L28 L33 L36 L40 N26 N30 N34 N38

F43

AA14 AA15 AB17 AB20 AC13 AD16 AD18 AD21 AE14 AE15 AF16 AF18 AF20

AF46

AG15 AG16 AG17 AG20 AG21

AG48 AG50 AG51

AJ14 AJ15

AJ17 AJ21 AJ25 AJ43 AJ47 AK50 AK51 AL14 AL15 AL16 AL20 AL22 AL26 AL45 AL48 AM16 AM17 AM21 AM43 AM47 AN20 AN42 AN45 AN48

BC22

AN16

W16 W17

AM25 AN22

A44 B43 C44

G43

AN17

U1000

AY43

AA46 AB47 AB50 AB51 AB52 AB53 AB55 AB56 AB58 AB59 AC61 AD47 AD48 AD50 AD51 AD52 AD53 AD55 AD56 AD58 AD59 AE46

N45 P47 P48 P50 P51 P52 P53 P55 P56 P61

F45

T48 T58 T59 T61 U46 V47 V48 V50 V51 V52 V53 V55 V56 V58 V59 W50 W51 W52 W53 W55 W56 W61 Y48 Y61

AM28 AN26

BB3 BC1 BC4

L17 L21 N16 N20 N22 P17 P20 R16 R18 R21

U10

U15 V16 V17 V18 V21

D48 D49

W20

AJ28 AJ33 AJ36 AJ40 AL30 AL34 AL38 AL42 AM33 AM36 AM40 AN30 AN34 AN38 AR26 AR28 AR30 AR32 AR34 AR36 AR40 AV41 AW26 BA40 BB28 BG33

BC43 BA43

G45

C1330

1

2

R1302

1

2

R1360

1

2

R1362

1

2

R1361

1

2

R1363

1

2

R1370

1

2

R1371

1

2

R1380

1

2

R1382

1

2

R1381

1

2

R1330

1

2

R1331

1

2

R1320

1

2

051-9277

2.8.0

13 OF 109

12 OF 73

12

7

12 15

7 9

10 12 14

7 9

10 12 14

7 9

12 14

7 9

12 15

7 9

12 15

7

12

7

10 12 15 26

7

12 15

7

10 12 15 26

7 9

12 14

7

15

7

14

7

14

54

(8 OF 9)

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS

VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS

VSS_NCTF VSS_NCTF

VSS_NCTF

VSS_NCTF VSS_NCTF

(9 OF 9)

VSS

Apple Inc.

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NOTICE OF PROPRIETARY PROPERTY:

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A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

CRITICAL

OMIT_TABLE

IVY-BRIDGE

2C-35W

BGA

2C-35W

OMIT_TABLE

CRITICAL

IVY-BRIDGE

CPU GROUNDS

SYNC_MASTER=J30_MLB

SYNC_DATE=07/27/2011

U1000

A13 A17 A21 A25 A28 A33 A37 A40 A45 A49 A53

A9

AA1

AA13 AA50 AA51 AA52 AA53 AA55 AA56

AA8

AB16 AB18 AB21 AB48 AB61

AC10 AC14 AC46

AC6

AD17 AD20

AD4

AD61

AE13

AE8

AF1 AF17 AF21 AF47 AF48 AF50 AF51 AF52 AF53 AF55 AF56 AF58 AF59

AG10 AG14 AG18 AG47 AG52 AG61

AG7

AH4 AH58

AJ13 AJ16 AJ20 AJ22 AJ26 AJ30 AJ34 AJ38 AJ42 AJ45 AJ48

AJ7

AK1 AK52 AL10 AL13 AL17 AL21 AL25 AL28 AL33 AL36 AL40 AL43 AL47 AL61

AM13 AM20 AM22 AM26 AM30

AM34 AM38

AM4

AM42 AM45 AM48 AM58 AN1 AN21 AN25 AN28 AN33 AN36 AN40 AN43 AN47 AN50 AN54

AP10 AP51 AP55

AP7

AR13 AR17 AR21 AR41 AR48 AR61

AR7

AT14 AT19 AT36

AT4

AT45 AT52 AT58 AU1

AU11 AU28 AU32 AU51

AU7

AV17 AV21 AV22 AV34 AV40 AV48 AV55

AW13 AW43 AW61

AW7

AY14 AY19 AY30 AY36

AY4

AY41 AY45 AY49 AY55 AY58

AY9

BA1 BA11 BA17 BA21 BA26 BA32 BA48 BA51 BB53

BC13

BC5

BC57

BD12 BD16 BD19 BD23 BD27 BD32 BD36 BD40 BD44 BD48 BD52 BD56

BD8

BE5 BG9

U1000

BG13 BG17 BG21 BG24 BG28 BG37 BG41 BG45 BG49 BG53

C29 C35 C40

D10 D14 D18 D22 D26 D29 D35

D4

D40 D43 D46 D50 D54 D58

D6

E25 E29

E3

E35 E40 F13 F15 F19 F29 F35 F40 F55

G48 G51

G6

G61

H10 H14 H17 H21

H4

H53 H58

J1 J49 J55

K11 K21 K51

K8

L16 L20 L22 L26 L30 L34 L38 L43 L48 L61

M11 M15

M4

M58

M6

N1 N17 N21 N25 N28 N33 N36 N40 N43 N47 N48 N51 N52 N56 N61

A5 A57 BC61 BD3 BD59 BE4 BE58 BG5 BG57 C3 C58 D59 E1 E61

P14 P16 P18 P21 P58 P59

P9

R17 R20

R4

R46 T1 T47 T50 T51 T52 T53 T55 T56

U13

U8

V20 V61

W13 W15 W18 W21 W46

W8

Y4 Y47 Y58 Y59

051-9277

2.8.0

14 OF 109

13 OF 73

Apple Inc.

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124578

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87 6 5 4 3

C

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NOTICE OF PROPRIETARY PROPERTY:

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12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

CPU VCORE DECOUPLING

Processor Load Line : -2.9 mOhms

PLACEMENT_NOTE (C1640-C1645):

CPU VCCPLL DECOUPLING

CPU VCCIO/VCCPQ DECOUPLING

CPU VCCPLL Low pass filter

PLACEMENT_NOTE (C1684-C167F):

PLACEMENT_NOTE (C1672-C1681):

Intel recommendation (Section 6.5): 26x 1uF, 10x 10uF, 2x 330uF

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

Note:The smallest 10mOhm available in the library are 0805s

PLACEMENT_NOTE (C1646-C1671):

Intel recommendation (section 6.4): 2x 1uF, 1x 330uF

Intel recommendation (Table 7-1): 16x 2.2uF, 12x 22uF, 3x 330uF

All INTEL recommendations from Intel doc #4439028 Huron River Platform Power Design Guide

PLACEMENT_NOTE (C1667-C1679):

PLACEMENT_NOTE (C1655-C1666):

10%

10%10%10%

10%

10%10%10%10%

10%10%10%10%10%10%10%

10%

10%10%10%10%10%10%

10%10%10%10%10%

10%

10V

10V10V10V

10V

10V10V10V10V

10V10V10V10V10V10V10V

10V

10V10V10V10V10V10V

10V10V10V10V10V

10V

=PPVCORE_S0_CPU

=PP1V05_S0_CPU_VCCIO

=PP1V05_S0_CPU_VCCPQE

=PP1V8_S0_CPU_VCCPLL

=PP1V8_S0_CPU_VCCPLL_R

CPU DECOUPLING-I

SYNC_MASTER=J11_MLB

SYNC_DATE=10/03/2011

PLACE_NEAR=U1000.BB3:2.54 mm:NO_VIA

1UF

X5R 402

Place near U1000 on top side

0

402

5%

MF-LF

1/16W

Place near U1000 on bottom side

10UF

CERM-X5R

20%

6.3V 0402-1

1UF

X5R 402

1UF

X5R 402

1UF

X5R 402

1UF

X5R 402

1UF

X5R 402

X5R

1UF

402

1UF

X5R 402

1UF

X5R 402

1UF

X5R 402

1UF

X5R 402

1UF

X5R 402

1UF

X5R 402

1UF

X5R 402

1UF

X5R 402

1UF

X5R 402

6.3V 0201

20%

1UF

X5R

CRITICAL

20%

6.3V X5R

1UF

CRITICAL

0201

6.3V X5R

1UF

CRITICAL

20%

02010201

1UF

X5R

6.3V

20%

CRITICAL

0201

X5R

1UF

20%

6.3V

CRITICALCRITICAL

1UF

X5R

6.3V

20%

0201

X5R 402

1UF

X5R 402

1UF

X5R 402

Place on bottom side of U1000

1UF

X5R 402

CERM-X5R

20%

0402-1

CRITICAL

10UF

6.3V

Place close to U1000 on top side.

CRITICAL

10UF

20%

6.3V 0402-1

CERM-X5R

6.3V X5R

1UF

20%

CRITICAL

0201

20% X5R

0201

6.3V

CRITICAL

1UF

X5R

6.3V

20%

1UF

CRITICAL

0201

CRITICAL

20% X5R

1UF

6.3V

0201

6.3V

1UF

X5R

20%

CRITICAL

0201

6.3V

1UF

X5R

20%

CRITICAL

0201

1UF

20%

6.3V X5R

CRITICAL

20%

0201

6.3V

1UF

X5R

CRITICAL

0201

X5R

6.3V

1UF

20%

CRITICAL

X5R

6.3V

20%

0201

1UF

CRITICAL

Place on bottom side of U1000

X5R 402

1UF

0201

X5R

6.3V

1UF

20%

CRITICAL

0201

1UF

20%

CRITICAL

6.3V X5R

0201

CRITICAL

6.3V

1UF

X5R

20%

0201

6.3V

1UF

X5R

20%

CRITICAL

0201

X5R

6.3V

1UF

20%

CRITICALCRITICAL

1UF

X5R

20%

0201

6.3V

1UF

6.3V 0201

X5R

20%

CRITICAL

0201

CRITICAL

1UF

6.3V X5R

20%

CRITICAL

0201

6.3V X5R

1UF

20%

CRITICAL

0201

X5R

6.3V

1UF

20%

X5R

Place on bottom side of U100.

1UF

402

6.3V

1UF

20%

CRITICAL

0201

X5R

0201

1UF

6.3V X5R

20%

CRITICAL

20%

6.3V

1UF

0201

X5R

CRITICAL

0201

X5R

20%

1UF

CRITICAL

6.3V

0201

6.3V

1UF

X5R

20%

CRITICAL

1UF

0201

20%

6.3V X5R

CRITICALCRITICAL

0201

20%

6.3V

1UF

X5R

CRITICAL

20%

1UF

X5R 0201

6.3V

0201

6.3V

1UF

20%

CRITICAL

X5R

0201

1UF

X5R

CRITICAL

20%

6.3V

0201

6.3V

1UF

X5R

20%

CRITICAL

0201

6.3V X5R

1UF

20%

CRITICAL

0201

20%

6.3V X5R

1UF

CRITICAL

0201

6.3V

1UF

X5R

20%

CRITICAL

0201

6.3V

1UF

X5R

20%

CRITICAL

0201

20%

6.3V

1UF

X5R

CRITICAL

0201

6.3V X5R

20%

CRITICAL

1UF

10UF

20% CERM-X5R

6.3V 0402-1

CRITICAL

X5R 402

1UF

Place on bottom side of U1000

CRITICAL

6.3V 0402-1

CERM-X5R

20%

10UF10UF

CRITICAL

6.3V 0402-1

CERM-X5R

20%

6.3V CERM-X5R

CRITICAL

0402-1

20%

10UF

CRITICAL

CERM-X5R

20%

0402-1

6.3V

10UF

20%

10UF

6.3V 0402-1

CERM-X5R

CRITICAL

6.3V

20% CERM-X5R

CRITICAL

0402-1

10UF

CERM-X5R

CRITICAL

20%

0402-1

6.3V

10UF

0402-1

CRITICAL

20% CERM-X5R

6.3V

10UF

CRITICAL

6.3V 0402-1

CERM-X5R

20%

10UF

0402-1

20%

CRITICAL

6.3V

10UF

CERM-X5R

1UF

X5R 402

10UF

0402-1

20%

6.3V

CRITICAL

CERM-X5R

CASE-B2-SM

TANT

270UF

2V

20%

2V

20% TANT

PLACE_NEAR=U1000.BC2:5mm

CASE-B2-SM

270UF

2V TANT CASE-B2-SM

270UF

20%

CASE-B2-SM

270UF

TANT

20% 2V

270UF

TANT CASE-B2-SM

2V

20%

CASE-B2-SM

2V

20% TANT

270UF

CASE-B2-SM

TANT

20% 2V

270UF

20%

270UF

2V TANT CASE-B2-SM

10UF

6.3V

20% CERM-X5R

0402-1

CRITICAL

CERM-X5R

6.3V

10UF

20%

0402-1

CRITICAL

1UF

X5R 402

2V TANT

20%

270UF

CASE-B2-SM

20% 2V

CASE-B2-SM

TANT

270UF

Place near U1000 on bottom side

10UF

CERM-X5R 0402-1

20%

6.3V

Place near U1000 on bottom side

10UF

CERM-X5R 0402-1

20%

6.3V

Place near U1000 on bottom side

10UF

CERM-X5R 0402-1

20%

6.3V

Place near U1000 on bottom side

10UF

CERM-X5R 0402-1

20%

6.3V

1UF

X5R 402

Place near U1000 on bottom side

10UF

CERM-X5R 0402-1

20%

6.3V

Place near U1000 on bottom side

10UF

CERM-X5R 0402-1

20%

6.3V

Place near U1000 on bottom side

10UF

CERM-X5R 0402-1

20%

6.3V

Place near U1000 on bottom side

10UF

CERM-X5R 0402-1

20%

6.3V

CERM-X5R

10UF

6.3V

20%

0402-1

Place near U1000 on bottom side

1UF

X5R 402

1UF

PLACE_NEAR=U1000.BC1:2.54 mm:NO_VIA

1UF

X5R 402

0.010

MF

0603

1%

1/4W

R1601

12

C167F

1

2

C1697

1

2

C161F

1

2

C1698

1

2

C1699

1

2

C169A

1

2

C169B

1

2

C169C

1

2

C1684

1

2

C1685

1

2

C1686

1

2

C1655

1

2

C1656

1

2

C1687

1

2

C1688

1

2

C1689

1

2

C1600

1

2

C1601

1

2

C1602

1

2

C1603

1

2

C1604

1

2

C1605

1

2

C169D

1

2

C169E

1

2

C169F

1

2

C161A

1

2

C161B

1

2

C161C

1

2

C161D

1

2

C1690

1

2

C1691

1

2

C1692

1

2

C1693

1

2

C1694

1

2

C1695

1

2

C1696

1

2

R1600

12

C160X

1

2

C160Y

1

2

C161E

1

2

C162A

1

2

C162B

1

2

C162C

1

2

C162D

1

2

C162E

1

2

C167A

1

2

C167B

1

2

C167C

1

2

C167D

1

2

C1680

1

2

C1657

1

2

C1658

1

2

C1681

1

2

C1682

1

2

C1683

1

2

C167E

1

2

C167G

1

2

C167H

1

2

C160Z

1

2

C1679

1

2

C1659

1

2

C1660

1

2

C1661

1

2

C1662

1

2

C1663

1

2

C1664

1

2

C1665

1

2

C1666

1

2

C1667

1

2

C1668

1

2

C1669

1

2

C1670

1

2

C1606

1

2

C1607

1

2

C1608

1

2

C1609

1

2

C1610

1

2

C1611

1

2

C1612

1

2

C1613

1

2

C1614

1

2

C1615

1

2

C1616

1

2

C1617

1

2

C1618

1

2

C1619

1

2

C1620

1

2

C1621

1

2

C1622

1

2

C1623

1

2

C1624

1

2

C1625

1

2

C1626

1

2

C1627

1

2

C1628

1

2

C1629

1

2

C1630

1

2

C1631

1

2

C1632

1

2

C1633

1

2

C1634

1

2

C1635

1

2

C1636

1

2

C1637

1

2

C1638

1

2

C1639

1

2

C1640

1

2

C1641

1

2

C1642

1

2

051-9277

2.8.0

16 OF 109

14 OF 73

12

9 7

12 10

9 7

12

7

12

7

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Intel recommendation (section 6.3): 18x 1uF(9 no-stuff), 10x 104F(2 no-stuff), 8x 22uF(2 no stuff), 4x 470uF(2 no-stuff)

PLACEMENT_NOTE (C1711-C1716):

PLACEMENT_NOTE (C1717-C1722):

CPU VDDQ/VCCDQ DECOUPLING

Intel recommendation (Section 6.6): 3x 1uf, 3x 10uf, 1x 330uf

VAXG DECOUPLING

PLACEMENT_NOTE (C1700-C1710):

Graphics Load Line : -3.9 mOhms

PLACEMENT_NOTE (C1738-C1747):

PLACEMENT_NOTE (C1758-C1762):

CPU VCCSA DECOUPLING

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

Intel recommendation (Section 6.13): 10x 1uF, 8x 10uF, 1x 330uF

PLACEMENT_NOTE (C1723-C1724):

10%10%

10% 10%

10%10%10%10%10%

10%10%10%

10%

10%10%10%10%10%10%

10%10%10%10%10%10%10%10%

10V10V

10V 10V

10V10V10V10V10V

10V10V10V

10V

10V10V10V10V10V10V

10V10V10V10V10V10V10V10V

=PP1V5_S3_CPU_VCCDQ

=PPVCCSA_S0_CPU

=PP1V5_S3_CPU_VCCDDR

=PPVCORE_S0_CPU_VCCAXG

SYNC_DATE=07/29/2011

CPU DECOUPLING-II

SYNC_MASTER=K21_MLB

Place on bottom side of U100.

X5R 402

1UF

402

X5R

Place on bottom side of U1000

1UF

Place on bottom side of U1000

X5R

1UF

402

CRITICAL

X5R 402

1UF

CRITICAL

X5R

1UF

402

X5R 402

Place on bottom side of U1000

1UF

X5R

1UF

402

Place on bottom side of U1000

X5R 402

Place on bottom side of U100.

1UF

X5R

Place on bottom side of U1000

1UF

402

X5R

1UF

CRITICAL

X5R 402

1UF

CRITICAL

X5R

1UF

CRITICAL

402

1UF

402

X5R

402

X5R

1UF

CRITICALCRITICAL

X5R 402

1UF

X5R 402

1UF

CRITICAL

Place on bottom side of U1000

1UF

402

X5R

CRITICAL

X5R

Place on bottom side of U100.

402

CRITICAL

1UF1UF

X5R

CRITICAL

402

Place on bottom side of U1000

402

X5R

1UF

402

1UF

X5RX5R

402

1UF

6.3V

20%

X5R-CERM1 0603

22UF

AXG_ACOUSTIC:NO

22UF

20%

6.3V X5R-CERM1 0603

AXG_ACOUSTIC:NO

22UF

20%

6.3V X5R-CERM1 0603

AXG_ACOUSTIC:NO

402

1UF

X5RX5R

1UF

402402

X5R

1UF

Place on bottom side of U1000

X5R 402

1UF

22UF

4V X5R

20%

402

AXG_ACOUSTIC:YES

X5R

4V

20%

22UF

402

AXG_ACOUSTIC:YES

X5R

4V

20%

22UF

402

AXG_ACOUSTIC:YES

20% 4V X5R

22UF

402

AXG_ACOUSTIC:YES

4V X5R

22UF

20%

402

AXG_ACOUSTIC:YES

22UF

20%

6.3V

0603

X5R-CERM1

AXG_ACOUSTIC:NO

20%

22UF

4V X5R 402

AXG_ACOUSTIC:YES

Place close to U1000 on bottom side

0402-1

CERM-X5R

10UF

20%

6.3V

0402-1

20%

6.3V

CERM-X5R

10UF

Place close to U1000 on bottom side

270UF

CASE-B2-SM

2V

20%

TANT

270UF

TANT

2V

CASE-B2-SM

20%

TANT

2V

20%

270UF

CASE-B2-SM

10UF

CERM-X5R

6.3V

20%

0402-10402-1

20%

6.3V

CERM-X5R

10UF

22UF

X5R-CERM1

20%

6.3V

0603

AXG_ACOUSTIC:NO

0402-1

20%

6.3V

CERM-X5R

10UF

20%

6.3V

CERM-X5R

10UF

0402-10402-1

20%

6.3V

CERM-X5R

10UF

0402-1

20%

6.3V

CERM-X5R

10UF

Place close to U1000 on bottom sidePlace close to U1000 on bottom side

10UF

CERM-X5R

6.3V

20%

0402-10402-1

20%

6.3V

CERM-X5R

10UF

Place close to U1000 on bottom sidePlace close to U1000 on bottom side

10UF

CERM-X5R

6.3V

20%

0402-10402-1

20%

CERM-X5R

10UF

Place close to U1000 on bottom side

6.3V

0603

X5R-CERM1

20%

6.3V

22UF

AXG_ACOUSTIC:NO

0402-1

6.3V

CERM-X5R

20%

10UF

Place close to U1000 on bottom side

10UF

6.3V

20%

0402-1

CRITICAL

CERM-X5R

0402-1

20%

6.3V

CERM-X5R

CRITICAL

10UF

6.3V

0402-1

20%

CERM-X5R

10UF

CRITICAL

CERM-X5R

0402-1

20%

10UF

6.3V

CRITICAL

0402-1

10UF

CERM-X5R

6.3V

20%

CRITICAL

10UF

CRITICAL

20%

6.3V

CERM-X5R

0402-1

270UF

TANT

2V

20%

CASE-B2-SM

2V

20%

TANT

270UF

CASE-B2-SM

1UF

X5R 402

Place on bottom side of U1000

MF

1/4W

1%

0.010

0603

R1702

12

C1757

1

2

C1738

1

2

C1739

1

2

C1740

1

2

C1717

1

2

C1718

1

2

C1719

1

2

C1741

1

2

C1742

1

2

C1743

1

2

C1744

1

2

C1720

1

2

C1721

1

2

C1722

1

2

C1745

1

2

C1746

1

2

C1747

1

2

C1700

1

2

C1701

1

2

C1702

1

2

C1704

1

2

C1705

1

2

C1706

1

2

C1707

1

2

C1708

1

2

C1709

1

2

C1758

1

2

C1759

1

2

C1760

1

2

C1761

1

2

C1762

1

2

C1710

1

2

C1703

1

2

C1756

1

2

C1768

1

2

C1711

1

2

C1712

1

2

C1713

1

2

C1714

1

2

C1715

1

2

C1716

1

2

C1748

1

2

C1749

1

2

C1751

1

2

C1752

1

2

C1753

1

2

C1755

1

2

C1763

1

2

C1764

1

2

C1765

1

2

C1766

1

2

C1767

1

2

C1723

1

2

C1724

1

2

C1725

1

2

C1754

1

2

C1750

1

2

C1727

1

2

C1728

1

2

C1729

1

2

C1730

1

2

C1731

1

2

C1732

1

2

051-9277

2.8.0

17 OF 109

15 OF 73

12

7

12

7

26 12 10

7

12

9 7

IN

OUT

BI

IN

OUT

IN

OUT

BI

OUT

BI

IN

OUT

IN

OUT

BI

OUT

IN

OUT

IN

OUT

IN

OUT

BI

OUT

BI

NC

IHDA

(1 OF 10)

JTAG

SATA

LPC

RTCSPI

HDA_SDIN2

HDA_SDIN0

HDA_SYNC

SPI_CS1*

JTAG_TMS

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

FWH4/LFRAME*

HDA_DOCK_EN*/GPIO33 HDA_DOCK_RST*/GPIO13

HDA_SDIN1

HDA_SDIN3

HDA_SDO

JTAG_TCK

JTAG_TDI

JTAG_TDO

LDRQ0*

LDRQ1*/GPIO23

RTCX2

SATA0GP/GPIO21

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

SATA1GP/GPIO19

SATA1RXN SATA1RXP SATA1TXN SATA1TXP

SATA2RXN SATA2RXP SATA2TXN SATA2TXP

SATA3COMPI SATA3RBIAS

SATA3RCOMPO

SATA3RXN SATA3RXP SATA3TXN SATA3TXP

SATA4RXN SATA4RXP SATA4TXN SATA4TXP

SATA5RXN SATA5RXP SATA5TXN SATA5TXP

SATAICOMPI

SATAICOMPO

SATALED*

SERIRQ

SPI_CLK

SPI_CS0*

SPI_MISO

SPI_MOSI

HDA_RST*

SPKR

RTCX1

HDA_BCLK

INTVRMEN

INTRUDER*

SRTCRST*

RTCRST*

IN

OUT

IN

C-LINK

SMBUS

PCI-E*

CLOCKS

FLEX

CLOCKS

(2 OF 10)

XTAL25_OUT

XTAL25_IN

XCLK_RCOMP

SML1DATA/GPIO75

SML1CLK/GPIO58

SML1ALERT*/PCHHOT*/GPIO74

SML0DATA

SML0CLK

SML0ALERT*/GPIO60

SMBDATA

SMBCLK

SMBALERT*/GPIO11

REFCLK14IN

PETP8

PETP7

PETP6

PETP5

PETP4

PETP3

PETP1

PETN8

PETN7

PETN6

PETN5

PETN4

PETN3

PETN2

PETN1

PERP8

PERP7

PERP6

PERP5

PERP4

PERP3

PERP1

PERN8

PERN6

PERN5

PERN4

PERN3

PERN2

PERN1

PEG_B_CLKRQ*/GPIO56

PEG_A_CLKRQ*/GPIO47

PCIECLKRQ7*/GPIO46

PCIECLKRQ6*/GPIO45

PCIECLKRQ5*/GPIO44

PCIECLKRQ4*/GPIO26

PCIECLKRQ3*/GPIO25

PCIECLKRQ2*/GPIO20

PCIECLKRQ1*/GPIO18

PCIECLKRQ0*/GPIO73

CL_RST1*

CL_DATA1

CL_CLK1

CLKOUT_PEG_B_P

CLKOUT_PEG_B_N

CLKOUT_PEG_A_P

CLKOUT_PEG_A_N

CLKOUT_PCIE7P

CLKOUT_PCIE7N

CLKOUT_PCIE6P

CLKOUT_PCIE6N

CLKOUT_PCIE5P

CLKOUT_PCIE5N

CLKOUT_PCIE4P

CLKOUT_PCIE4N

CLKOUT_PCIE3P

CLKOUT_PCIE3N

CLKOUT_PCIE2P

CLKOUT_PCIE2N

CLKOUT_PCIE1P

CLKOUT_PCIE1N

CLKOUT_PCIE0P

CLKOUT_PCIE0N

CLKOUT_ITPXDP_P

CLKOUT_ITPXDP_N

CLKOUT_DP_P

CLKOUT_DP_N

CLKOUT_DMI_P

CLKOUT_DMI_N

CLKOUTFLEX3/GPIO67

CLKOUTFLEX2/GPIO66

CLKOUTFLEX1/GPIO65

CLKOUTFLEX0/GPIO64

CLKIN_SATA_P

CLKIN_SATA_N

CLKIN_PCILOOPBACK

CLKIN_GND1_P

CLKIN_GND1_N

CLKIN_DOT_96P

CLKIN_DOT_96N

CLKIN_DMI_P

CLKIN_DMI_N

PERN7

PETP2

PERP2

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(IPU-RSMRST#)

1.8V -> 1.1V

(IPD-PLTRST#)

(IPD-PWROK)

(IPU)

(IPD-PWROK)

(IPU)

(IPD)

VSel strap not functional (VCCVRM = 1.8V)

(IPD)

(IPD-BOOT)

(IPD) (IPD)

(IPU)

(IPD)

(IPD-BOOT)

(IPU)

(IPU/IPD) (IPU/IPD)

(IPD-PWROK)

(IPU-RSMRST#)

Unused clock terminations for FCIM Mode

Controlled by PCIECLKRQ5#

DOES THIS NEED LENGTH MATCH???

If HDA = S0, must also ensure that signal cannot be high in S3.

Connect to ENET_MEDIA_SENSE via 12K R if HDA = 1.5V.

Connect to ENET_MEDIA_SENSE via alias if HDA = 3.3V.

25 69

43 69

6

41 43

38 68

6

37 69

6

37 69

44 69

330K

MF

5%

1/20W

201

1M

MF 201

5% 1/20W

20K

MF

201

5%

1/20W

20K

MF 201

5% 1/20W

37.4

MF 201

1% 1/20W

PLACE_NEAR=U1800.AB10:2.54mm

10K

MF 201

5% 1/20W

PLACE_NEAR=U1800.AC49:2.54mm

90.9

MF

201

1%

1/20W

44 69

16

23 69

23

69

NO STUFF

0

MF

201

5%

1/20W

5%

201

MF

0

NO STUFF

1/20W

201

MF

1K

1%

25 69

25

MF 201

1%

PLACE_NEAR=U1800.AH4:2.54mm

201

1% 1/20W

49.9

MF

PLACE_NEAR=U1800.AF12:2.54mm

23

8

23

6

37 69

6

37 69

16 37

16

44 69

10 66

8

16 68

25 69

16

8

16

34 69

16 36

1/20W

MF5%

201

4.7K

201

10K

MF5%

1/20W

5% MF

10K

201

10K

201

1/20W

5% MF

1/20W

5%

201

MF

10K

5%

1/20W

201

MF

10K

5%

1/20W

MF

10K

201

MF

10K

5%

1/20W

5%

201

MF

10K 10K

1/20W

5%

201

MF

201

10K

MF5%

1/20W

5%

201

MF

10K

201

MF

1/20W

5%

10K

5% MF

10K

1/20W

201

1/20W

MF

201

10K

5%

10K

1/20W

MF

201

16 24

16

1/20W

5%

201

MF

10K 10K

1/20W

5%

201

MF

1/20W

5%

201

MF

33

PLACE_NEAR=U1800.F35:1.27mm

1/20W

MF

33

5%

201

PLACE_NEAR=U1800.K37:1.27mm

1/20W

5% MF33201

PLACE_NEAR=U1800.H35:1.27mm

1/20W

5%

201

MF

33

PLACE_NEAR=U1800.H37:1.27mm

6

40 69

6

40 69

6

40 69

6

40 69

6

41 43 69

6

41 43 69

6

41 43 69

6

41 43 69

1/20W

201

MF

33

5%

1/20W

5% MF33201

1/20W

5%

201

MF

33

1/20W

5%

201

MF

33

6

41 43 69

1/20W

5% MF33201

1/20W

5%

201

MF

10K

1/20W

201

MF

10K

5%

MF

1/20W

5%

10K

201

5%

201

MF

10K

1/20W

5%

201

MF

10K

1/20W

5%

10K

201

MF

1/20W

5%

201

MF

10K

1/20W

5%

201

MF

10K

1/20W

5%

201

MF

10K

OMIT_TABLE

PCH-PPT-MB-SFF-ES1

BGA

QP8D-MM915462

43 69

23 69

16 34

6

40 69

BGA

OMIT_TABLE

PCH-PPT-MB-SFF-ES1

QP8D-MM915462

1.0UF

20%

X5R

0201-MUR

6.3V

1.0UF

20%

6.3V

X5R 0201-MUR

604

1%MF1/20W

PLACE_NEAR=U1800.W49:5.1mm

201

8

69

8

69

8

6

38 66

6

38 66

6

16 38

SYNC_DATE=07/27/2011

PCH SATA/PCIe/CLK/LPC/SPI

SYNC_MASTER=J30_MLB

=PP1V05_S0_PCH_VCCIO_SATA

TP_SATA_C_R2D_CN

TP_SATA_E_D2RP

TP_SATA_E_R2D_CP

HDA_SYNC_R

HDA_RST_R_L

HDA_SDOUT_R

LPC_AD<0>

SML_PCH_1_DATA

SML_PCH_1_CLK

PEGCLKRQB_L_GPIO56

PCH_INTVRMEN_L

PCIE_CLK100M_FW_P

PCIE_CLK100M_FW_N

PCIE_CLK100M_ENET_P

PCIE_CLK100M_ENET_N

NC_PCIE_8_R2D_CN NC_PCIE_8_R2D_CP

FW_CLKREQ_L

PCIE_CLK100M_EXCARD_P

PCIE_CLK100M_EXCARD_N

SSD_CLKREQ_L

TP_PCIE_CLK100M_PEBN

ENET_CLKREQ_L

PCIE_CLK100M_SSD_P

TP_PCIE_CLK100M_PEBP

PEG_CLK100M_N PEG_CLK100M_P

PCIE_CLK100M_TBT_N

ITPXDP_CLK100M_P

PCIE_CLK100M_SSD_N

ITPXDP_CLK100M_N

PEG_CLKREQ_L

AP_CLKREQ_L

PCIE_CLK100M_AP_P

PCIE_CLK100M_AP_N

=PP1V05_S0_PCH

LPC_AD_R<0> LPC_AD_R<1>

NC_PCIE_7_D2RP

PCH_CLKIN_GNDN1

SML_PCH_0_DATA

LPC_AD_R<2>

NC_PCIE_5_R2D_CP

NC_PCIE_5_D2RN NC_PCIE_5_D2RP

PCIE_EXCARD_R2D_C_P

NC_PCIE_6_D2RN NC_PCIE_6_D2RP NC_PCIE_6_R2D_CN

PCH_SPKR

RTC_RESET_L LPC_AD_R<3>

PCH_SPKR

SYSCLK_CLK25M_SB_R

SYSCLK_CLK25M_SB

NC_PCIE_6_R2D_CP

PCH_CLK96M_DOT_P

PCH_CLK96M_DOT_N

DMI_CLK100M_CPU_P

TP_PCH_CLKOUT_DPN

HDA_BIT_CLK

HDA_SYNC

HDA_SDOUT

PCH_SRTCRST_L PCH_INTRUDER_L

PCH_CLKIN_GNDP1

PCIE_CLK100M_PCH_P

PCH_CLK100M_SATA_N

PCH_CLK96M_DOT_P

=PP3V3_S0_PCH

PCIE_CLK100M_PCH_N

PCH_CLK100M_SATA_P

PCH_CLK96M_DOT_N

PCH_CLK14P3M_REFCLK

LPC_AD<3>

LPC_AD<2>

NC_PCIE_8_D2RN NC_PCIE_8_D2RP

NC_PCIE_7_D2RN

NC_PCIE_7_R2D_CP

PCIE_AP_R2D_C_N PCIE_AP_R2D_C_P

USB_EXTB_SEL_XHCI SML_PCH_0_CLK

USB_EXTD_SEL_XHCI

TP_CLINK_DATA TP_CLINK_RESET_L

PEGCLKRQA_L_GPIO47 TP_PCIE_CLK100M_PEGAN TP_PCIE_CLK100M_PEGAP

DMI_CLK100M_CPU_N

TP_PCH_CLKOUT_DPP

PCIE_CLK100M_PCH_N

PCH_CLKIN_GNDN1 PCH_CLKIN_GNDP1

PCH_CLK100M_SATA_P

PCH_CLK100M_SATA_N

=PP1V05_S0_PCH_VCCDIFFCLK

TP_PCH_GPIO64_CLKOUTFLEX0

TP_PCH_GPIO65_CLKOUTFLEX1

TP_PCH_GPIO66_CLKOUTFLEX2

HDA_BIT_CLK_R

=PPVRTC_G3_PCH

RTC_RESET_L

PCH_SRTCRST_L

PCH_INTRUDER_L

PCH_INTVRMEN_L

HDA_BIT_CLK_R

HDA_RST_R_L

SPI_MOSI_R

SPI_MISO

LPC_SERIRQ

PCH_SATALED_L

TP_SATA_F_R2D_CP

TP_SATA_F_D2RN

TP_SATA_E_R2D_CN

TP_SATA_E_D2RN

TP_SATA_D_R2D_CP

TP_SATA_D_R2D_CN

TP_SATA_D_D2RP

TP_SATA_D_D2RN

PCH_SATA3RBIAS

PCH_SATA3COMP

TP_SATA_C_R2D_CP

TP_SATA_C_D2RP

TP_SATA_C_D2RN

SATA_ODD_R2D_C_P

SATA_ODD_R2D_C_N

SATA_ODD_D2R_P

SATA_ODD_D2R_N

SATA_HDD_R2D_C_P

SATA_HDD_R2D_C_N

SATA_HDD_D2R_P

SATA_HDD_D2R_N

XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL

TBT_PWR_EN_PCH

TP_LPC_DREQ0_L

XDP_PCH_TDI

XDP_PCH_TCK

HDA_SDOUT_R

TP_HDA_SDIN1

ENET_MEDIA_SENSE_RDIV

LPC_FRAME_R_L

LPC_AD_R<3>

LPC_AD_R<2>

LPC_AD_R<1>

LPC_AD_R<0>

XDP_PCH_TMS

TP_SPI_CS1_L

HDA_SYNC_R

HDA_SDIN0

TP_HDA_SDIN2

HDA_RST_L

ITPCPU_CLK100M_N

LPC_FRAME_L

PCIE_EXCARD_R2D_C_N

PCIE_FW_R2D_C_P

PCIE_FW_R2D_C_N

PCIE_FW_D2R_N PCIE_FW_D2R_P

PCIE_EXCARD_D2R_N PCIE_EXCARD_D2R_P

PCIE_ENET_D2R_N

PCIE_ENET_R2D_C_P

TP_SATA_F_R2D_CN

TP_SATA_F_D2RP

PCIE_AP_D2R_P

PCIE_AP_D2R_N

PCIE_ENET_R2D_C_N

PCIE_ENET_D2R_P

LPC_AD<1>

JTAG_DPMUXUC_TRST_L

EXCARD_CLKREQ_L

TP_PCIE_CLK100M_PE4N TP_PCIE_CLK100M_PE4P

TBT_CLKREQ_L

PCH_SATAICOMP

NC_PCIE_5_R2D_CN

XDP_DC3_PCH_GPIO19_SATARDRVR_EN

LPC_FRAME_R_L

FW_CLKREQ_L

PCH_SATALED_L

DP_AUXCH_ISOL SATARDRVR_EN

SYSCLK_CLK32K_RTC

NC_PCIE_7_R2D_CN

PCIE_CLK100M_PCH_P

PCH_CLK14P3M_REFCLK

TP_PCH_GPIO67_CLKOUTFLEX3

PCIE_CLK100M_TBT_P

SSD_CLKREQ_L

PCH_CLK33M_PCIIN

SYSCLK_CLK25M_SB_R

PCH_XCLK_RCOMP

TP_CLINK_CLK

SMBUS_PCH_DATA

SMBUS_PCH_CLK

SMBUS_PCH_ALERT_L

ENET_MEDIA_SENSE_RDIV

ITPCPU_CLK100M_P

AP_CLKREQ_L

JTAG_DPMUXUC_TRST_L ENET_CLKREQ_L

PEGCLKRQA_L_GPIO47

TBT_CLKREQ_L

PEG_CLKREQ_L

EXCARD_CLKREQ_L

USB_EXTD_SEL_XHCI

SMBUS_PCH_ALERT_L USB_EXTB_SEL_XHCI

=PP3V3_S0_PCH_GPIO

=PP3V3_SUS_PCH_GPIO

PEGCLKRQB_L_GPIO56

750

1/20W

TP_HDA_SDIN3

23

SPI_CS0_R_L

SPI_CLK_R

XDP_PCH_TDO

69

JTAG_ISP_TMS

R1800

1

2

R1801

1

2

R1802

1

2

R1803

1

2

R1830

1

2

R1820

1

2

R1890

1

2

R1840

12

R1841

12

R1886

1

2

R1832

1

2

R1831

1

2

R1877

12

R1878

12

R1834

12

R1842

12

R1869

12

R1844

12

R1845

12

R1847

12

R1814

21

R1815

12

R1843

12

R1833

12

R1879

12

R1846

12

R1853

12

R1848

12

R1854

12

R1855

12

R1812

12

R1813

12

R1810

12

R1811

12

R1861

12

R1862

12

R1863

12

R1864

12

R1860

12

R1891

12

R1892

12

R1893

12

R1894

12

R1895

12

R1896

12

R1897

12

R1870

12

R1871

12

U1800

A37 A39 C39 C37 K40

H35

K35 M35

F35

D36 B36 C35 A35

K37

H37

K22

C21

M17

U12

M12

M15

H40 F37

F19

A19 C19

M2

AN3 AN1 AU3 AU1

R1

AN6 AN8 AR3 AR1

AD4 AD2 AL3 AL1

AF12 AH4

AF10

AD8 AD6 AG3 AG1

AE3 AE1 AH8 AH6

AC3 AC1 AJ3 AJ1

AB12

AB10

W10

Y4

AD12

AB8

AB6

Y2

W8

N1

A23

U1800

L3 J1 M8

BD17 BF17

M24 K24

BB26 AY26

E51

AK8 AK6

BB24 AY24

AN10 AN12

AR12 AR10

AD48 AD50

AE49 AE51

AD40 AD42

AA49 AA51

Y48 Y50

AB40 AB42

AB44 AB46

W44 W46

AF44 AF46

AF40 AF42

H50

D48

G49

J51

M4

U8

T4

B8

M19

K8

J3

H4

R8

C4

BJ33

BJ35

BH36

BJ37

BJ39

BH40

BJ41

BJ43

BL33

BL35

BK36

BL37

BL39

BK40

BL41

BL43

BB30

BB33

BF33

BD35

AY35

BD37

AY37

AY40

AY30

AY33

BD33

BF35

BB35

BF37

BB37

BB40

J49

H12 F17 F10

H22 K12 A9

C9 D12 C11

AC49

W49 W51

C1802

1

2

C1803

1

2

R1885

12

051-9277

2.8.0

18 OF 109

16 OF 73

7

22

6

16 69

16 25 69

16

8

16

6

23 66

7

22

16

8

16

8

16

16 16

16

16 69

8

16

16 68

7

22

16 68

8

6

16

7

20 22

6

16 69

7

17 20

16

16 69

16

6

16 69

6

16

16 69

6

10 66

6

68

8

16

23 25

8

6

16 38

16 69

6

16

10 66

16 37

16

16 36

16

16 24

7

17 18 19 25 36

7

17 18 19

16

6

25

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

BI

OUT

IN

OUT

IN

OUT

FDI

(3 OF 10)

DMI

SYSTEM POWER

MANAGEMENT

DMI_ZCOMP

DMI3TXN

DMI2TXN

DMI1TXN

DMI0TXN

FDI_LSYNC1

DSWVRMEN

FDI_FSYNC1

FDI_FSYNC0

FDI_RXP5

FDI_RXP4

FDI_RXP3

FDI_RXP2

FDI_RXP1

FDI_RXP0

APWROK

CLKRUN*/GPIO32

DMI0RXN DMI1RXN DMI2RXN

DMI2RXP

DMI3RXN

DMI3RXP

DMI3TXP

DPWROK

DRAMPWROK

FDI_INT

FDI_LSYNC0

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP6 FDI_RXP7

PMSYNCH

PWROK

SLP_A*

SLP_LAN*/GPIO29

SLP_S3*

SLP_S4*

SLP_S5*/GPIO63

SLP_SUS*

SUSACK*

SUSCLK/GPIO62

SUS_STAT*/GPIO61

SYS_PWROK

SYS_RESET*

WAKE*

RI*

BATLOW*/GPIO72

ACPRESENT/GPIO31

PWRBTN*

SUSWARN*/SUSPWRDNACK/GPIO30

RSMRST*

DMI1RXP

DMI0RXP

DMI_IRCOMP

DMI2RBIAS

DMI0TXP DMI1TXP DMI2TXP

(4 OF 10)

LVDS

DIGITAL DISPLAY INTERFACE

CRT

LVDSA_DATA0* LVDSA_DATA1*

LVDSB_DATA3*

LVDSB_DATA2*

CRT_BLUE

CRT_DDC_CLK CRT_DDC_DATA

CRT_GREEN

CRT_HSYNC

CRT_IRTN

CRT_RED

CRT_VSYNC

DAC_IREF

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPB_AUXN DDPB_AUXP

DDPB_HPD

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPC_AUXN DDPC_AUXP

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_HPD

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

DDPD_AUXN DDPD_AUXP

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_HPD

LVDSA_CLK

LVDSA_CLK*

LVDSA_DATA2* LVDSA_DATA3*

LVDSA_DATA0 LVDSA_DATA1

LVDSA_DATA3

LVDSB_CLK

LVDSB_CLK*

LVDSB_DATA0* LVDSB_DATA1*

LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3

LVD_VREFH LVD_VREFL

L_DDC_CLK L_DDC_DATA

SDVO_CTRLCLK

SDVO_CTRLDATA

SDVO_INTN SDVO_INTP

SDVO_STALLN SDVO_STALLP

SDVO_TVCLKINN SDVO_TVCLKINP

L_BKLTEN L_VDD_EN

L_BKLTCTL

LVD_IBG LVD_VBG

LVDSA_DATA2

L_CTRL_CLK L_CTRL_DATA

NC NC NC NC

NC

NC NC

NC

NC NC

NC

NC NC

NC

NC NC

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(IPD-DeepS4/S5)

(IPU)

(IPD-PLTRST#)

(IPD) (IPD)

9

66

9

66

9

66

9

66

9

66

9

66

49.9

1/20W

1%

201

MF

PLACE_NEAR=U1800.BF19:12.7mm

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

1/20W

5%

201

1K

MF

PLACE_NEAR=U1800.R51:2.54mm

750

MF

1% 1/20W

201

PLACE_NEAR=U1800.BK20:2.54mm

390K

MF 201

5% 1/20W

1/20W

5%

201

MF

10K

0

MF

201

5%

1/20W

17 62

1/20W

5%

201

MF

100K

25 41

23 25 41

10 26 66

25

62

17 23 41

41 42 62

42

6

17 37

6

17 41 43

6

25 41 43

42 69

17 41 62

17 26 37 41 49 62

17 26 41 62

10 66

41

8

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

5%

201

1/20W

MF

100K

1/20W

5% MF1K201

1/20W

5%

201

8.2K

MF

1/20W

5%

201

MF

1K

5%

201

MF

100K

1/20W

5%

1/20W

201

MF

100K

1/20W

5%

201

MF

10K

1/20W

5%

201

MF

5% MF

10K

201

1/20W

17 56

OMIT_TABLE

QP8D-MM915462

BGA

PCH-PPT-MB-SFF-ES1 PCH-PPT-MB-SFF-ES1

OMIT_TABLE

QP8D-MM915462

BGA

MF

5%

100K

1/20W

201

PCH DMI/FDI/PM/Graphics

SYNC_MASTER=J30_MLB

SYNC_DATE=07/27/2011

DMI_N2S_P<1>

PM_PWRBTN_L

PCIE_WAKE_L

PM_SLP_SUS_L

PM_SLP_S5_L

PM_SLP_S3_L

FDI_INT

MEM_VDD_SEL_1V5_L

PM_SLP_S4_L

PM_CLKRUN_L

PCH_SUSWARN_L

=PP3V3_SUS_PCH_GPIO

PM_PWRBTN_L

PCH_SUSWARN_L

PCH_DMI_COMP

DMI_S2N_P<0>

DMI_S2N_P<3>

=PP1V05_S0_PCH_VCCIO_PCIE

=PP3V3_SUS_PCH_GPIO

FDI_DATA_N<0>

FDI_DATA_N<2>

TP_SDVO_INTN

TP_DP_IG_C_MLP<0>

TP_DP_IG_C_MLP<1>

TP_DP_IG_C_MLP<2>

TP_DP_IG_B_MLP<0>

TP_DP_IG_B_MLP<1>

LVDS_IG_PANEL_PWR

LVDS_IG_BKL_ON

LVDS_IG_BKL_PWM

TP_SDVO_INTP

DPA_IG_DDC_DATA

TP_SDVO_TVCLKINP

TP_DP_IG_D_MLP<2>

TP_DP_IG_D_MLN<1>

TP_CRT_IG_DDC_DATA

PCH_SUSACK_L

=PP3V3_SUS_PCH_GPIO

=PP3V3_S5_PCH

=PP3V3_S0_PCH_GPIO

TP_CRT_IG_HSYNC

TP_CRT_IG_DDC_CLK

TP_CRT_IG_RED

TP_CRT_IG_BLUE

FDI_DATA_N<5>

FDI_DATA_P<1> FDI_DATA_P<2> FDI_DATA_P<3>

FDI_DATA_N<7>

FDI_DATA_P<4>

FDI_FSYNC<0>

PCH_RI_L

PCH_DMI2RBIAS

DMI_S2N_P<2>

DMI_S2N_N<2>

FDI_DATA_P<0>

PM_DSW_PWRGD

DMI_S2N_P<1>

DMI_N2S_P<0>

PM_RSMRST_L

PM_BATLOW_L

PCIE_WAKE_L

PM_SYSRST_L

PM_PCH_SYS_PWROK

LPC_PWRDWN_L

PCH_SUSACK_L

PM_SLP_SUS_L

PM_SLP_S5_L PM_SLP_S4_L PM_SLP_S3_L

TP_PM_SLP_A_L

PM_PCH_PWROK

PM_SYNC

FDI_DATA_N<6>

FDI_DATA_N<4>

FDI_DATA_N<3>

FDI_DATA_N<1>

PM_MEM_PWRGD

DMI_N2S_P<3>

DMI_N2S_N<3>

DMI_N2S_P<2>

DMI_N2S_N<2>

DMI_N2S_N<1>

DMI_N2S_N<0>

PM_CLKRUN_L

PM_PCH_APWROK

PCH_DSWVRMEN

DMI_S2N_N<0> DMI_S2N_N<1>

DMI_S2N_N<3>

=PPVRTC_G3_PCH

FDI_LSYNC<0> FDI_LSYNC<1>

FDI_FSYNC<1>

FDI_DATA_P<5>

FDI_DATA_P<7>

FDI_DATA_P<6>

PM_CLK32K_SUSCLK_R

MEM_VDD_SEL_1V5_L

TP_SDVO_TVCLKINN

TP_SDVO_STALLP

TP_SDVO_STALLN

DPA_IG_DDC_CLK

TP_DP_IG_D_HPD

TP_DP_IG_D_CTRL_DATA

TP_DP_IG_D_CTRL_CLK

TP_DP_IG_D_AUXP

TP_DP_IG_D_AUXN

TP_DP_IG_D_MLP<3>

TP_DP_IG_D_MLN<3>

TP_DP_IG_D_MLN<2>

TP_DP_IG_D_MLP<1>

TP_DP_IG_D_MLP<0>

TP_DP_IG_D_MLN<0>

DPB_IG_HPD

DPB_IG_DDC_DATA

DPB_IG_DDC_CLK

DPB_IG_AUX_CH_P

DPB_IG_AUX_CH_N

TP_DP_IG_C_MLP<3>

TP_DP_IG_C_MLN<3>

TP_DP_IG_C_MLN<2>

TP_DP_IG_C_MLN<1>

TP_DP_IG_C_MLN<0>

DPA_IG_HPD

DPA_IG_AUX_CH_P

DPA_IG_AUX_CH_N

TP_DP_IG_B_MLP<3>

TP_DP_IG_B_MLN<3>

TP_DP_IG_B_MLP<2>

TP_DP_IG_B_MLN<2>

TP_DP_IG_B_MLN<1>

TP_DP_IG_B_MLN<0>

PCH_DAC_IREF

TP_CRT_IG_VSYNC

TP_CRT_IG_GREEN

SMC_ADAPTER_EN

R1900

1

2

R1951

1

2

R1920

1

2

R1915

1

2

R1905

1

2

R1986

12

R1909

1

2

R1923

21

R1925

12

R1991

12

R1985

12

R1922

21

R1921

21

R1924

21

R1983

1

2

R1982

12

U1800

H19

G3

H10

T2

BL21

BJ21

BD22

BF22

BL23

BJ23

BB22

AY22

BK20

BJ19

BL19

BB19

AY19

BL17

BJ17

BB17

AY17

BD19

BF19

A21

B12

F22

BH12 BK8

BB10

BK12 BH8

BL13 BJ15 BD12 BJ11 AY15 AY12 BJ9 BF10

BJ13 BL15 BF12 BL11 BB15 BB12 BL9 BD10

BB8

K19

M22

F12

B20

C7

A7

D4

K10

F6

A15

G6

F15

D3

C13

M10

L1

D8

U1800

M46

R49 N49

R46

M50

T48

U46

N51

R51

AY48 AY50 AY44 AY46 BB44 BB46 BA49 BA51

AW51 AW49 AY42

BC49 BC51 BD48 BD50 BF46 BF45 BE49 BE51

AU51 AU49

T50 U44

BE46

BG51 BG49 BF42 BD42 BJ47 BL47 BL45 BJ45

AU46 AU44

M48 U42

BK44

L49

M44

R42 M40

L51 K46

M42

AH42 AH40

AG51 AG49

AK46

AK44

AR44

AR46

AN51

AN49

AN46

AN44

AK42

AK40

AH44

AH46

AM48

AM50

AL51

AL49

AJ49

AJ51

AH48

AH50

W42 R44

AT50 AT48

AR51 AR49

AU40 AU42

R1955

1

2

051-9277

2.8.0

19 OF 109

17 OF 73

17 23 41

6

17 37

17 62

17 41 62

17 26 41 62

17 56

17 26 37 41 49 62

6

17 41 43

17

7

16 17 18 19

17

7

16 17 18 19

6

8

6

8

6

17

7

16 17 18 19

7

16 18 19 25 36

6

17

7

16 20

6

8

6

NC

NC NC

NC

NC NC NC

NC

BI

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

BI

IN

(5 OF 10)

USB

PCI

PME*

PLTRSTB*

PIRQA*

TP2

TP5

TP4

TP11

USB3RN4

USB3RN2

CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4

GNT1*/GPIO51 GNT2*/GPIO53 GNT3*/GPIO55

OC0*/GPIO59 OC1*/GPIO40 OC2*/GPIO41 OC3*/GPIO42 OC4*/GPIO43

OC5*/GPIO9 OC6*/GPIO10 OC7*/GPIO14

PIRQB* PIRQC* PIRQD*

PIRQE*/GPIO2 PIRQF*/GPIO3 PIRQG*/GPIO4 PIRQH*/GPIO5

REQ1*/GPIO50 REQ2*/GPIO52 REQ3*/GPIO54

RSVD

TP1

TP3

TP6 TP7 TP8 TP9 TP10

TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20 TP21 TP22 TP23 TP24

TP41 TP42

USB3RN1

USB3RN3

USB3RP1 USB3RP2 USB3RP3 USB3RP4

USB3TN1 USB3TN2 USB3TN3 USB3TN4

USB3TP1 USB3TP2 USB3TP3 USB3TP4

USBP0N USBP0P

USBP10N USBP10P

USBP11N USBP11P

USBP12N USBP12P

USBP1N USBP1P

USBP2N USBP2P

USBP3N USBP3P

USBP4N USBP4P

USBP5N USBP5P

USBP6N USBP6P

USBP7N USBP7P

USBP8N USBP8P

USBP9N USBP9P

USBRBIAS

USBRBIAS*

USBP13P

USBP13N

NC

BI

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Redundant to pull-up on audio page

USB Hub (All LS/FS Devices)

Ext D (XHCI) (Mobiles: Trackpad?)

Redundant to pull-up on audio page

Ext A (XHCI/EHCI)

Ext B (XHCI)

Ext C (XHCI/EHCI)

Unused

Ext D (EHCI)

Ext B (EHCI)

Camera

RSVD: BT (HS)

RSVD: SD

RSVD: WiFi

Unused

(IPD)

(IPU)

(IPU-PCIERST#)

24 68

8

24 68

8

24 68

39 68

40 68

8

201

1/20W

10K

MF5%

1/20W

5%

201

MF

10K

5% MF

201

1/20W

10K

MF

1/20W

5%

201

10K

MF

201

5%

1/20W

NO STUFF

1/20W

MF

10K

201

5%

10K

MF

201

5%

1/20W

10K

MF

201

5%

MF

10K

201

5%

1/20W

201

10K

MF5%

1/20W

NO STUFF

10K

MF

201

5%

1/20W

5%

10K

MF

201

1/20W

18

6

18 40

18 34

6

18 40

1/20W

5%

201

MF

10K

1/20W

5%

201

MF

10K 10K

MF

1/20W

5%

201

1/20W

5%

201

MF

10K

NO STUFF

10K

MF

201

5%

1/20W

10K

MF

201

5%

1/20W

NO STUFF

18 23

23

39 68

23

BGA

PCH-PPT-MB-SFF-ES1

QP8D-MM915462

OMIT_TABLE

39 68

6

40 68

6

40 68

1%

201

MF

1/20W

22.6

PLACE_NEAR=U1800.A33:2.54mm

25 26

25 69

PCH PCI/USB/TP/RSVD

SYNC_DATE=11/10/2011

SYNC_MASTER=J13_MLB_NON_POR

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L

AUD_I2C_INT_L

BLC_I2C_MUX_SEL

BLC_GPIO

PCH_GPIO54

JTAG_GMUX_TMS

XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L

AP_PWR_EN

TP_PCH_STRP_ESI_L PCH_STRP_TOPBLK_SWP_L

XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

TBT_PWR_REQ_L

=PP3V3_S3_PCH_GPIO

USB_EXTD_XHCI_N

USB_EXTD_EHCI_P

XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L

JTAG_GMUX_TMS

PCH_GPIO54

AUD_IP_PERIPHERAL_DET TBT_PWR_REQ_L AUD_I2C_INT_L

USB3_EXTC_TX_P

PCI_INTB_L

BLC_I2C_MUX_SEL

USB_EXTB_EHCI_P

USB_EXTD_EHCI_N

AUD_IP_PERIPHERAL_DET

=PP3V3_S0_PCH_GPIO

TP_USB_WLANP

TP_USB_WLANN

TP_PCH_STRP_BBS1

USB_EXTA_P

USB_EXTA_N

USB_EXTB_XHCI_P

USB_EXTB_XHCI_N

USB_EXTC_N USB_EXTC_P

USB_EXTD_XHCI_P

TP_USB_4N TP_USB_4P TP_USB_SDN

TP_USB_SDP

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L

XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L

XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

XDP_DB2_PCH_GPIO10_AP_PWR_EN

PCH_USB_RBIAS

TP_USB_13N TP_USB_13P

USB_EXTB_EHCI_N

USB_CAMERA_N USB_CAMERA_P

USB_HUB_UP_N USB_HUB_UP_P

TP_USB_12P

TP_USB_BT_HSN TP_USB_BT_HSP

TP_USB_12N

TP_PCH_TP23

USB3_EXTC_RX_N

USB3_EXTB_RX_N

USB3_EXTA_RX_N

USB3_EXTA_RX_P USB3_EXTB_RX_P

USB3_EXTD_RX_P

USB3_EXTC_RX_P

USB3_EXTA_TX_N USB3_EXTB_TX_N USB3_EXTC_TX_N USB3_EXTD_TX_N

USB3_EXTB_TX_P

USB3_EXTA_TX_P

USB3_EXTD_TX_P

PCI_INTC_L

=PP3V3_S0_PCH_GPIO

PCI_INTA_L

PCI_INTD_L

LPC_CLK33M_SMC_R

TP_PCI_CLK33M_OUT2 TP_PCI_CLK33M_OUT3

LPC_CLK33M_LPCPLUS_R

PCH_CLK33M_PCIOUT

TP_PCI_PME_L

PLT_RESET_L

BLC_GPIO

USB3_EXTD_RX_N

=PP3V3_SUS_PCH_GPIO

R2070

1

2

R2067

21

R2068

12

R2061

12

R2062

12

R2033

12

R2060

12

R2030

12

R2018

12

R2016

12

R2017

12

R2014

12

R2031

12

R2010

12

R2011

12

R2012

12

R2013

12

R2054

21

R2069

12

U1800

G51 E49 H48 J43 G45

F42 H42 D44

C17 A17 A13 D16 A11 B16 C23 H15

D49 C48 C47 C45

A47 C41 F45 F40

F7

H2

G46 K44 F46

AU6 AU8

BB6 BC1 BC3 BD2 BD4 BE1 BE3 BE6 BF6 BF7

AW1

BG1 BG3 BH3 BH4 BJ4 BJ5 BJ7 BK6 BL5

AW3 AY2 AY4 AY6 AY8 BA1 BA3

BH24

D20 M30

E3 AM4 AT4 AT2

AD10

B24 D24

AD44

BK24

AD46 BJ48

BL7 W40 K30

BH20 BK16

BH49 BB42

BH16 AN42 AN40 AR40 AR42

BJ25 BJ27 BJ31 BJ29

BL25 BL27 BL31 BL29

BF26 BB28 BF28 BF30

BD26 AY28 BD28 BD30

F24 H24

C31 A31

H33 F33

H30 F30

M33 K33

C25 A25

C27 A27

H28 F28

M26 K26

D28 B28

H26 F26

D32 B32

M28 K28

C29 A29

A33

C33

051-9277

2.8.0

20 OF 109

18 OF 73

18 23

6

18 40

18

18 23

23 37 62

18 23

18 34

7

25

6

18 40

7

16 17 18 19 25 36

68

7

16 17 18 19 25 36

6

7

16 17 19

OUTOUT

BI

IN

NC

IN

OUT

IN

BI

IN

OUT

IN

OUT

BI

IN

OUT

NCTF

CPU/MISC

(6 OF 10)

GPIO

GPIO1 GPIO6

VSS_NCTF

TS_VSS4

TS_VSS3

TS_VSS2

TS_VSS1

THRMTRIP*

STP_PCI*/GPIO34

SATA3GP/GPIO37

SATA2GP/GPIO36

RCIN*

PROCPWRGD

PECI

NC_1

INIT3_3V*

GPIO71

GPIO70

GPIO69

GPIO68

GPIO35

GPIO8

GPIO7

DF_TVS

A20GATE

GPIO24 GPIO27 GPIO28

BMBUSY*/GPIO0

LAN_PHY_PWR_CTRL/GPIO12 GPIO15 SATA4GP/GPIO16 GPIO17 SCLOCK/GPIO22

SLOAD/GPIO38 SDATAOUT0/GPIO39 SDATAOUT1/GPIO48 SATA5GP/GPIO49 GPIO57

D

SG

D

GS

D

SG

OUT

IN

OUT

IN

OUT

NC

08

NC

OUT

NC

08

OUT

NC

IN

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Stuff R2160 or R2574, not both

Must stuff R2197 when R2180 NO STUFFed.

Set to Vcc when High

Set to Vss when Low

DF_TVS:DMI & FDI Term Voltage

(IPD)

(IPU)

(IPU-DeepS4/S5)

THIS SIGNAL IS INTENDED FOR FIRMWARE HUB AND WE ARE NOT USING IT.

(IPU)

(IPD-PLTRST#?)

(IPU-RSMRST#)

(IPD-PLTRST#)

Systems with no chip-down memory should pull all 4 RAMCFG GPIOs high.

(IPU-RSMRST#)

Systems with chip-down memory should add pull-downs on another page and set straps per software.

This has internal pull up and should not pulled low.

NOTE: TDO from CR is Push-Pull CMOS

TBT_PWR_EN goes high for JTAG Programming

NOTE: TMS/TDI from PCH is Open Drain

NOTE: TCK from PCH is Push-Pull CMOS

JTAG Isolation due to glitch in and out of sleep

(TBT_CIO_PLUG_EVENT_ISOL)

SMC_RUNTIME_SCI_L

XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH

TBT_CIO_PLUG_EVENT_ISOL

NO STUFF

10K

TBT_CIO_PLUG_EVENT

JTAG_ISP_TMS

=PP3V3_S0_PCH_STRAPS

74LVC1G08

=PP3V3_TBT_PCH_GPIO

19

XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH

SSM3K15FV

=PP3V3_S0_PCH_GPIO

SSM6N15AFE

JTAG_ISP_TCK

TBT_PWR_EN

CRITICAL

PCH GPIO/MISC/NCTF

X5R-CERM

SYNC_MASTER=J11_MLB

201

=PP3V3_S0_PCH_STRAPS

JTAG_TBT_TCK

SOT891

=PP3V3_S0_PCH_GPIO

1/20W

MF

PCH_RCIN_L

=PP3V3_S5_PCH_GPIO

10K

MF 201

5% 1/20W

1/20W

5%

201

MF

XDP_FC1_PCH_GPIO0

16V

X5R-CERM

10%

0.1UF

0201

1/20W

5%

MF

10K

MF5%

201

16V

10%

0.1UF

0201

74LVC1G08

CRITICAL

SOT891

10K

1/20W

SSM6N15AFE

XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL

ENET_LOW_PWR_PCH

SMC_RUNTIME_SCI_L

201

JTAG_TBT_TMS

=PP3V3_TBT_PCH_GPIO

TBT_GO2SX_BIDIR

10K

5% 1/20W MF 201

CRITICAL

JTAG_ISP_TDO

=PP3V3_TBT_PCH_GPIO

5%

JTAG_ISP_TDI JTAG_TBT_TDI

1/20W

5%

201

MF

10K

SOD-VESM-HF

1/20W

5%

201

MF

10K

SOT563

5%

201

MF

CRITICAL

SOT563

5%

201

MF

10K

1/20W

5%

201

MF

10K

PCH_A20GATE

MLB_RAMCFG0

MF

201

XDP_FC0_PCH_GPIO15

5%

LPCPLUS_GPIO

XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK

XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL

PM_THRMTRIP_L_R

SMC_WAKE_SCI_L

TBT_GO2SX_BIDIR

XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L TBT_SW_RESET_R_L

XDP_DC1_PCH_GPIO35_MXM_GOOD

JTAG_ISP_TDO JTAG_ISP_TDI FW_PWR_EN_PCH

10 23 66

SPIROM_USE_MLB

8

19

23

MF

1/20W

LPCPLUS_GPIO

10 42 66

5%

MF

1/20W

5%

201

MF

10K

RAMCFG2:H

8

23

=PP1V8_S0_PCH_VCC_DFTERM

CPU_PROC_SEL_L

=PP3V3_S0_PCH_GPIO

MLB_RAMCFG1

MLB_RAMCFG2

MLB_RAMCFG3

CPU_PECI

CPU_PWRGD

PM_THRMTRIP_L

PCH_INIT3V3_L

PCH_RCIN_L

PCH_PROCPWRGD

XDP_FC1_PCH_GPIO0 FW_PME_L DPMUX_UC_IRQ

PCH_PECI

PCH_DF_TVS

WOL_EN

FW_PME_L

TBT_SW_RESET_L

TP_PCH_GPIO8

ODD_PWR_EN_L

WOL_EN

RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H

RAMCFG_SLOT

SYNC_DATE=09/16/2011

OMIT_TABLE

PCH-PPT-MB-SFF-ES1

QP8D-MM915462

BGA

19

23

66 42 10

1/20W

5%

201

MF

390

0

MF

201

5%

1/20W

5%

201

MF

43

NO STUFF

1/20W

201

MF

201

1/20W

5% MF

10K

1/20W

5% MF

10K

1/20W

5% MF

23 19

36

1/20W

0

MF

201

23

1/20W

5%

201

MF

10K

5%

201

MF

10K

5%

201

MF5%

5%

1/20W

201

10K 10K

5%

1/20W

MF

201

10K

MF

1/20W

5%

201

1/20W

5% MF

100K

201

1/20W

5% MF

10K

1/20W

5%

201

MF

10K

5%

201

MF

100K

20K

1/20W

5%

201

1/20W

5%

201

MF

2.2K

1/20W

201

MF

1K

19

41 19

8

41 19

RAMCFG0:H

10K

MF 201

5% 1/20W

10K

MF

201

5%

1/20W

RAMCFG1:HRAMCFG3:H

10K

MF

201

5%

1/20W

50 43 19

6

23

19

NO STUFF

1K

201

5%

1/20W

19

43 19

6

23

100K

JTAG_TBT_TDO

1/20W

CRITICAL

ODD_PWR_EN_L

AUD_IPHS_SWITCH_EN_PCH

DPMUX_UC_IRQ

SMC_WAKE_SCI_L

SPIROM_USE_MLB

PCH_A20GATE

FW_PWR_EN_PCH

TBT_SW_RESET_R_L

201

1/20W

=PP3V3_S0_PCH_GPIO

=PP3V3_SUS_PCH_GPIO

10K

NO STUFF

R2130

1

2

R2172

1

2

R2173

1

2

R2174

1

2

R2175

1

2

R2178

12

R2179

1

2

R2111

21

R2195

21

R2191

12

R2192

12

R2193

12

R2194

12

R2184

12

R2197

12

R2190

12

R2196

12

R2185

12

R2160

12

R2112

21

R2180

12

R2198

21

R2116

21

R2150

12

R2155

12

R2170

12

R2140

12

R2156

12

U1800

U3

W1

BC7

B40

K6

B44

K15 C15

G1

W12

K17

C43

K42 A43

A45

D40 A41

H17

R6

C5

U40

AU12

AU10

U6

W6 M6

AA3

AA1

W3

U10

U1

N3

R3

BC9

AK10 AH12 AK12 AH10

A4 A5

BJ51

BL1 BL3 BL4

BL48 BL49 BL51 C3 C49 C51

A48

D1 D51 E1

A49 A51 BH1

BH51

BJ1 BJ3

BJ49

Q2160

6

2

1

Q2162

3

1

2

Q2160

3

5

4

R2162

1

2

R2186

1

2

R2161

1

2

R2199

1

2

R2188

1

2

R2163

1

2

C2113

1

2

U2100

2

1

3

6

4

R2113

1

2

U2101

2

1

3

6

4

C2114

1

2

R2166

1

2

R2167

1

2

051-9277

2.8.0

21 OF 109

19 OF 73

5

16 19

19

18

34

19

43

17 16

7

19

25 23

19

22 20

7

8

10

36 25 19 18 17 16

7

8

19

23 19

42

50 43 19

6

19

8

23 19

41 19

19

6

41 19

19

23

19

34 19

36 25 18 17

7

19

NC

VCC CORE

LVDS

(7 OF 10)

DMI

DFT/SPI

CRTFDI

VCCIO

VCCCORE

VCC3_3

VCCADAC

VCCADMI_VRM

VCCAFDIPLL

VCCAFDI_VRM

VCCALVDS

VCCDFTERM

VCCDMI

VCCIO

VCCSPI

VCCTX_LVDS

VSSALVDS

VSSA_DAC

VCCAPLLEXP

VCCACLK

V_PROC_IO

VCCCLKDMI

VCCRTC

DCPSUSBYP

VCCDSW3_3

VCCAPLLDMI2

DCPRTC

VCCADPLLB

VCCADPLLA

VCCDIFFCLKN

DCPSST

V5REF

V5REF_SUS

VCCAPLL_SATA3

VCCASW

VCCIO

VCCPUSB

VCCSSC

VCCSUS3_3

VCCSUSHDA

VCCVRM

DCPSUS

USB

SATA

PCI/GPIO/LPC

(8 OF 10)

HDA

CLK/MISC

CPURTC

NC

NC NC

NC

NC NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AL24 left as NC per DG

PCH output, for decoupling only

NC-ed per DG

1.44 A Max, 474mA Idle

VCCACLK pin left as NC per DG

PCH output, for decoupling only

55mA Max, 5mA Idle

10 mA Max, 1mA Idle

VCCAPLLDMI2 pin left as NC per DG

QP8D-MM915462

OMIT_TABLE

BGA

PCH-PPT-MB-SFF-ES1PCH-PPT-MB-SFF-ES1

OMIT_TABLE

QP8D-MM915462

BGA

PLACE_NEAR=U1800.N16:2.54mm

X5R-CERM

10%

0.1UF

16V

0201

PLACE_NEAR=U1800.N16:2.54mm

0201

0.1UF

10% 16V X5R-CERM

PLACE_NEAR=U1800.U17:2.54mm

16V

0.1UF

10%

X5R-CERM

0201

PLACE_NEAR=U1800.N16:2.54mm

0201

1UF

20%

6.3V X5R

PLACE_NEAR=U1800.R15:2.54mm

0.1UF

10% 16V

X5R-CERM

0201

PCH POWER

SYNC_MASTER=J11_MLB

SYNC_DATE=09/30/2011

PP3V3_S0_PCH_VCC3_3_CLK_F

=PP3V3_S0_PCH_VCC3_3

=PP1V05_S0_PCH_VCC_CORE

PP3V3_S0_PCH_VCCA_DAC_F

=PP1V05_S0_PCH_VCC_DMI

=PP1V8R1V5_S0_PCH_VCCVRM =PP1V8_S0_PCH_VCC_DFTERM

=PP1V8R1V5_S0_PCH_VCCVRM

=PP3V3_SUS_PCH_VCC_SPI

TP_1V05_S0_PCH_VCCAPLLEXP

=PP1V05_S0_PCH_VCCIO

=PP3V3R1V5_S0_PCH_VCCSUSHDA

=PP1V05_S0_PCH_VCCSSC

=PP3V3_SUS_PCH_VCCSUS_USB

=PP5V_SUS_PCH_V5REFSUS

=PP1V05_S0_PCH_VCCDIFFCLK

PP1V05_S0_PCH_VCCADPLLA_F PP1V05_S0_PCH_VCCADPLLB_F

MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

PPVOUT_G3_PCH_DCPRTC

MIN_LINE_WIDTH=0.2 mm

=PP3V3_S5_PCH_VCCDSW

TP_PPVOUT_PCH_DCPSUSBYP

=PPVRTC_G3_PCH

PP1V05_S0_PCH_VCCCLKDMI_F

=PP1V05_S0_PCH_V_PROC_IO

=PP1V05_S0_PCH_VCCIO

=PP1V05_S0_PCH_VCCASW

=PP1V8R1V5_S0_PCH_VCCVRM

PPVOUT_S0_PCH_DCPSST

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

=PP5V_S0_PCH_V5REF

=PP3V3_SUS_PCH_VCCSUS

U1800

AB19 AC19 AF6 BK28 R40 T39 U37 V37 V39

U51

AU21

AU19

AP13 AP15

AF33 AG33

AP19

AB21 AB23

AG25 AG27 AJ21 AJ23 AJ25 AJ27 AJ29 AJ31 AK29 AK31

AC21

AK33 AM33 AM35

AC23 AE21 AE23 AF21 AF23 AG21 AG23

AJ13 AJ15 AK15 AL13

AM23 AU15 AW16

AP27 AR15 AR23 AR25 AR27 AR29 AT13 AU23 AU25 AU27 AU29 AU35 AW34

AM21

Y19

AF37 AG37 AG39 AJ37

V50

AC33 AE33

U1800

R15 U15

U17

AR33 AU31 AU33 V13

R10

N36

M37

AM17

AC51

BF40 BD40

AM2

AW31

AB27 AB29

U19 U21 V19 V21 V23 V25 Y21 Y23

Y25

Y27

AB31

Y29 Y31

AC27 AC29 AC31 AE27 AE29 AE31

R19

AP39

AC37 AE37 AE39

R12

AA13 AB15 AC13

N18 R23 R25 U23 U25

AC15 AF15 AG13 AG15 AJ17 AK21

U27 U29

N16

AC35

AM27 N27 R27 R29 R33 R35 U33 U35

V31

AC39 AE19 AF17 AW18 AW21

C2232

1

2

C2233

1

2

C2222

1

2

C2231

1

2

C2210

1

2

051-9277

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20 OF 73

22

7

22

7

22

7

22

7

20

7

19 22

7

20

7

22

7

20 22

7

22 25

7

22

7

22

7

16 22

22

7

22

7

16 17

22

7

22

7

20 22

7

22

7

20

22

7

22

(9 OF 10)

VSSVSS

(10 OF 10)

VSSVSS

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

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A

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PAGE TITLE

SHEET

R

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SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

OMIT_TABLE

QP8D-MM915462

PCH-PPT-MB-SFF-ES1

BGA

PCH-PPT-MB-SFF-ES1

OMIT_TABLE

QP8D-MM915462

BGA

SYNC_MASTER=J30_MLB

SYNC_DATE=07/27/2011

PCH GROUNDS

U1800

AA7 AA9

AB25

AP25 AP29 AP31 AP33 AP35 AP37 AP41 AP43 AP45 AP48

AB33

AP50 AR6 AR8 AR17 AR19 AR21 AR31 AR35 AR37 AT7

AB35

AT9 AT11 AT39 AT41 AT43 AT45 AU17 AU37 AV2 AV4

AB37

AV48 AV50 AW7 AW9 AW11 AW13 AW23 AW25 AW27 AW29

AB48

AW36 AW39 AW41 AW43 AW45 AY10 B6 B10 B14 B18

AB50

B22 B26 B30 B34 B38 B42 B46 BA7 BA9 BA11

AC7

BA13 BA16 BA18 BA21 BA23 BA25 BA27 BA29 BA31 BA34

AC9

BA36 BA39 BA41 BA43 BA45 BB2 BB4 BB48 BB50 BC11

AC11

BC13 BC16 BC18 BC21

AC17

AA11

AC25 AC41 AC43 AC45

AE7

AE9 AE11 AE13 AE15 AE17

AA39

AE25 AE35 AE41 AE43 AE45

AF2

AF4

AF8 AF19 AF25

AA41

AF27 AF29 AF31 AF35 AF48 AF50

AG7

AG9 AG11 AG17

AA43

AG19 AG29 AG31 AG35 AG41 AG43 AG45

AH2

AJ7

AJ9

AA45

AJ11 AJ19 AJ33 AJ35 AJ39 AJ41 AJ43 AJ45

AK2

AK4

AB2

AK17 AK19 AK23 AK25 AK27 AK35 AK37 AK48 AK50

AL7

AB4

AL9 AL11 AL39 AL41 AL43 AL45 AM15 AM19 AM25 AM29

AB17

AM31 AM37

AP2 AP4 AP7 AP9 AP11 AP17 AP21 AP23

U1800

BC23 BC25 BC27 BC29 BC31 BC34 BC36 BC39 BC41 BC43 BC45 BD15 BD24

BE7

BE9 BE11 BE13 BE16 BE18 BE21 BE23 BE25 BE27 BE29 BE31 BE34 BE36 BE39 BE41 BE43 BE45

BF2

BF4 BF15 BF24 BF48 BF50

BH6 BH10 BH14 BH18 BH22 BH26 BH28 BH30 BH32 BH34 BH38 BH42 BH44 BH46 BH48 BK10 BK14 BK18 BK22 BK26 BK30 BK32 BK34 BK38 BK42 BK46

D6 D10 D14 D18 D22 D26 D30 D34 D38 D42 D46

F2

F4 F48 F50

G7

G9 G11 G13 G16 G18 G21 G23 G25 G27 G29 G31 G34 G36

G39 G41 G43 J7 J9 J11 J13 J16 J18 J21 J23 J25 J27 J29 J31 J34 J36 J39 J41 J45 K2 K4 K48 K50 L7 L9 L11 L13 L16 L18 L21 L23 L25 L27 L29 L31 L34 L36 L39 L41 L43 L45 N7 N9 N11 N13 N21 N23 N25 N29 N31 N34 N39 N41 N43 N45 P2 P4 P48 P50 R17 R21 R31 R37 T7 T9 T11 T13 T41 T43 T45 U31 U49 V2 V4 V7 V9 V11 V15 V17 V27 V29 V33 V35 V41 V43 V45 V48 Y15 Y17 Y33 Y35 Y37

051-9277

2.8.0

23 OF 109

21 OF 73

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

68 mA

(PCH Reference for 5V Tolerance on PCI)

(PCH USB 1.05V PWR)

(PCH SUSPEND USB 3.3V PWR)

PCH V5REF_SUS Filter & Follower

NEED PWR CONSTRAINT

<1 MA

PCH V5REF Filter & Follower

1 mA S0-S5

1 mA

PCH VCCIO BYPASS

PCH VCCSUSHDA BYPASS

(PCH HD Audio 3.3V/1.5V PWR)

PCH VCCSUS3_3 BYPASS

PCH VCCCORE BYPASS

(PCH 1.05V CORE PWR)

69 mA

(PCH DPLLA PWR)

PCH VCCADPLLA Filter

PCH VCCADPLLB Filter (PCH DPLLB PWR)

(PCH Reference for 5V Tolerance on USB)

NEED PWR CONSTRAINT

10%

10% 10%

10%

201

10V

PP1V05_S0_PCH_VCCCLKDMI_R

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM VOLTAGE=1.05V

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM VOLTAGE=1.05V MAKE_BASE=TRUE

PP1V05_S0_PCH_VCCCLKDMI_F

PP3V3_S0_PCH_VCCA_DAC_F

MAKE_BASE=TRUE MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

PP1V05_S0_PCH_VCCADPLLB_F

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM VOLTAGE=1.05V

=PP3V3_S0_PCH

MIN_NECK_WIDTH=0.2 MM

PP3V3_S0_PCH_VCC3_3_CLK_F

MIN_LINE_WIDTH=0.4 MM VOLTAGE=3.3V

=PP1V05_S0_PCH_VCCASW

PP3V3_S0_PCH_VCC3_3_CLK_R

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

=PP3V3_S0_PCH_VCC3_3_CLK

=PP3V3_SUS_PCH_VCCSUS_USB

=PP3V3R1V5_S0_PCH_VCCSUSHDA

=PP1V05_S0_PCH_V_PROC_IO

=PP3V3_S0_PCH_VCC3_3

=PP3V3_SUS_PCH_VCCSUS

=PP3V3_S5_PCH_VCCDSW

=PP3V3_SUS_PCH_VCCSUS

=PP1V05_S0_PCH_VCC_DMI

=PP5V_S0_PCH

=PP3V3_S0_PCH_VCCADAC

=PP1V05_S0_PCH_VCCIO

=PP5V_SUS_PCH

=PP3V3_SUS_PCH

=PP1V05_S0_PCH_VCCIO

=PP1V05_S0_PCH_VCCIO_SATA

=PP1V05_S0_PCH_VCCDIFFCLK

=PP3V3_SUS_PCH_VCC_SPI

=PP5V_SUS_PCH_V5REFSUS

MIN_LINE_WIDTH=0.4 MM VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_PCH_VCCADPLLA_F

=PP3V3_S0_PCH_VCC3_3

=PP1V05_S0_PCH_VCCSSC

=PP1V05_S0_PCH_VCC_CORE

PP5V_SUS_PCH_V5REFSUS

MIN_NECK_WIDTH=0.25MM MAKE_BASE=TRUE

VOLTAGE=5V

MIN_LINE_WIDTH=0.3MM

=PP1V8_S0_PCH_VCC_DFTERM

=PP1V05_S0_PCH

=PP3V3_S0_PCH_VCC3_3

=PP5V_S0_PCH_V5REF

MAKE_BASE=TRUE

PP5V_S0_PCH_V5REF

MIN_LINE_WIDTH=0.3MM VOLTAGE=5V

MIN_NECK_WIDTH=0.25MM

=PP3V3_S0_PCH_VCC3_3

=PP1V05_S0_PCH_VCCADPLL

=PP3V3_S0_PCH_VCC3_3

PCH DECOUPLING

SYNC_DATE=10/03/2011

SYNC_MASTER=J11_MLB

0

MF

1/20W

5%

1

5%

MF-LF

402

1/16W

10UH-0.12A-0.36OHM

0603

6.3V

20%

CERM-X5R

10UF

0402-1

PLACE_NEAR=U1800.V37:2.54mm

X5R 402

1UF

6.3V

20%

0201

X5R

1UF

PLACE_NEAR=U1800.AW16:2.54mm

PLACE_NEAR=U1800.AB19:2.54mm

0201

X5R-CERM

0.1UF

16V

PLACE_NEAR=U1800.BD40:2.54MM

0.1UF

0201

16V X5R-CERM

6.3V

PLACE_NEAR=U1800.BD40:2.54MM

0201

X5R

20%

1UF

X5R-CERM

0.1UF

0201

16V

PLACE_NEAR=U1800.BF40:2.54MM

X5R

6.3V

1UF

20%

0201

PLACE_NEAR=U1800.BF40:2.54MM

0.1UF

X5R-CERM 0201

16V

PLACE_NEAR=U1800.T39:2.54mm

0.1UF

X5R-CERM

PLACE_NEAR=U1800.BK28:2.54mm

16V 0201

0201

PLACE_NEAR=U1800.R40:2.54mm

X5R-CERM

16V

0.1UF

PLACE_NEAR=U1800.AF6:2.54mm

0201

X5R-CERM

0.1UF

16V

CERM

20%

0.1UF

PLACE_NEAR=U1800.M37:2.54mm

402

1/20W

5% MF

10

SOT-363

BAT54DW-X-G

PLACE_NEAR=U1800.N36:2.54mm

X5R

1UF

402

100

MF

5%

1/20W

SOT-363

BAT54DW-X-G

0

MF

1/20W

5%

0402-2

10UF

20%

6.3V

CERM-X5R

PLACE_NEAR=U1800.U51:2.54mm PLACE_NEAR=U1800.U51:2.54mm

0.1UF

X5R-CERM

16V

0201

X5R-CERM

16V

0201

0.01UF

PLACE_NEAR=U1800.U51:2.54mm

10UH-0.12A-0.36OHM

0603

CERM-X5R

PLACE_NEAR=U1800.AP39:2.54mm

0402-2

10UF

6.3V

20%

PLACE_NEAR=U1800.AJ17:2.54mm

6.3V

20%

0201

X5R

1UF

6.3V

1UF

20%

0201

X5R

PLACE_NEAR=U1800.U27:2.54mm

PLACE_NEAR=U1800.AC37:2.54mm

6.3V 0201

X5R

1UF

20%

PLACE_NEAR=U1800.AB15:2.54mm

6.3V

20%

0201

X5R

1UF

6.3V

20%

0201

X5R

1UF

PLACE_NEAR=U1800.AC35:2.54mm

PLACE_NEAR=U1800.AG13:2.54mm

6.3V

20%

0201

X5R

1UF

PLACE_NEAR=U1800.R33:2.54mm

1UF

X5R 0201

20%

6.3V

0201

X5R

20%

6.3V

PLACE_NEAR=U1800.AM23:2.54mm

1UF

0201

16V

X5R-CERM

0.1UF

PLACE_NEAR=U1800.R12:2.54mm

X5R 0201

6.3V

1UF

20%

PLACE_NEAR=U1800.Y19:2.54mm

0201

16V

PLACE_NEAR=U1800.R27:2.54mm

0.1UF

X5R-CERM

20%

6.3V X5R 402

4.7UF

PLACE_NEAR=U1800.AM17:2.54mm

X5R-CERM

PLACE_NEAR=U1800.AM17:2.54mm

16V 0201

0.1UF

PLACE_NEAR=U1800.N27:2.54mm

16V 0201

X5R-CERM

0.1UF

PLACE_NEAR=U1800.AM17:2.54mm

0201

16V X5R-CERM

16V 0201

X5R-CERM

0.1UF

PLACE_NEAR=U1800.V31:2.54mm

X5R-CERM 0201

PLACE_NEAR=U1800.AJ13:2.54mm

0.1UF

16V

PLACE_NEAR=U1800.AB21:2.54mm

0201

1UF

X5R

20%

6.3V

PLACE_NEAR=U1800.AB21:2.54mm

1UF

X5R 0201

20%

6.3V

PLACE_NEAR=U1800.AB21:2.54mm

1UF

X5R 0201

20%

6.3V

PLACE_NEAR=U1800.AB21:2.54mm

0402-2

CERM-X5R

6.3V

20%

10UF

1UF

X5R

PLACE_NEAR=U1800.AR25:2.54mm

0201

20%

6.3V 6.3V

PLACE_NEAR=U1800.AU25:2.54mm

X5R 0201

1UF

20%

PLACE_NEAR=U1800.AR29:2.54mm

6.3V

1UF

20%

0201

X5R

PLACE_NEAR=U1800.AU29:2.54mm

6.3V

20%

0201

X5R

1UF

PLACE_NEAR=U1800.AU27:2.54mm

10UF

0402-2

20%

6.3V

CERM-X5R

PLACE_NEAR=U1800.AB27:2.54mm

1UF

X5R

20%

6.3V 0201

PLACE_NEAR=U1800.AB27:2.54mm

X5R

20%

6.3V

1UF

0201

PLACE_NEAR=U1800.AB27:2.54mm

1UF

X5R 0201

20%

6.3V

PLACE_NEAR=U1800.AB27:2.54mm

22UF

20%

6.3V

X5R-CERM1

0603

22UF

PLACE_NEAR=U1800.AB27:2.54mm

20%

0603

X5R-CERM1

6.3V

402

1/16W MF-LF

0

5%

MF-LF

0

402

5%

1/16W

R2460

12

R2465

12

C2420

1

2

C2428

1

2

C2496

1

2

C2456

1

2

C2426

1

2

C2401

1

2

C2463

1

2

C2407

1

2

C2414

1

2

C2429

1

2

C2460

1

2

C2483

1

2

C2482

1

2

C2481

1

2

C2440

1

2

C2441

1

2

C2430

1

2

C2413

1

2

C2417

1

2

C2416

1

2

C2484

1

2

C2442

1

2

C2499

1

2

C2419

1

2

C2476

1

2

C2452

1

2

C2475

1

2

C2444

1

2

C2434

1

2

C2446

1

2

C2469

1

2

C2411

1

2

L2406

12

C2455

1

2

C2451

1

2

C2450

1

2

R2450

12

D2400

1

6

R2405

12

C2439

1

2

D2400

4

3

R2404

12

C2438

1

2

C2423

1

2

C2485

1

2

C2421

1

2

C2424

1

2

C2461

1

2

C2402

1

2

C2466

1

2

C2465

1

2

C2422

1

2

C2418

1

2

C2486

1

2

C2453

1

2

L2451

12

R2451

12

R2415

12

051-9277

2.8.0

24 OF 109

22 OF 73

5

2

20

16

7

20

7

20

7

25 20

7

20

7

22 20

7

22 20

7

20

7

22 20

7

22 20

7

22 20

7

25

7

22 20

7

22 20

7

16

7

20 16

7

20

7

20

22 20

7

20

7

20

7

20 19

7

16

7

22 20

7

20

22 20

7

22 20

7

IN

OUT

IN

OUT

NC

IN

OUT

IN

BI

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

NC

OUT

OUTOUT

IN

OUT

IN

OUT

OUTOUT

BI

IN

BI

IN

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page

XDP SIGNALS

PCH Micro2-XDP

support chipset debug.

Use with 921-0133 Adapter Flex to

518S0847

PCH SIGNALS

- ’Output’ non-XDP signals require pulls.

PCH/XDP Signal Isolation Notes:

- ’Output’ PCH/XDP signals require pulls.

OBSFN_B1

OBSFN_B0

518S0847

CPU Micro2-XDP

NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page

OBSDATA_A3

OBSDATA_A0

OBSFN_C0

OBSDATA_C1

Use with 921-0133 Adapter Flex to

OBSDATA_B3

SCL

TCK1

HOOK1

OBSDATA_A0

TCK0

OBSDATA_D1

OBSDATA_D2

OBSFN_C1

ITPCLK#/HOOK5

TRSTn

TDO

TMS

TDI

HOOK1

SDA

TCK0

HOOK3

OBSFN_D0

OBSDATA_C2

OBSDATA_C3

OBSDATA_C2

OBSDATA_C1

OBSFN_D1

OBSFN_D0

OBSFN_A0 OBSFN_A1

OBSDATA_A1

OBSFN_B0

OBSDATA_A3

TDO TRSTn

support chipset debug.

OBSDATA_B0

OBSFN_B1

OBSFN_C1

OBSDATA_C0

OBSFN_C0

TCK1

SCL

SDA

HOOK3

VCC_OBS_AB

- For isolated GPIOs:

doc id 404081.

it is functional in that state, else add BOM options.

OBSDATA_B0

OBSFN_A1

OBSDATA_A1

OBSDATA_B3

VCC_OBS_CD

OBSDATA_B2

PWRGD/HOOK0

HOOK2

VCC_OBS_AB

OBSDATA_A2

XDP_PRESENT#

ITPCLK/HOOK4

OBSDATA_D0

DBR#/HOOK7

OBSDATA_D3

OBSDATA_D2

OBSDATA_D1

OBSDATA_B2

- Following Intel’s Debug Prot Design Guid for HR and CR v1.3

TDI TMS

OBSDATA_B1

PCH SIGNALS

OBSFN_A0

RESET#/HOOK6

OBSDATA_D3

OBSDATA_D0

OBSDATA_C3

OBSFN_D1

ITPCLK#/HOOK5 VCC_OBS_CD

Non-XDP Signals

(R2560-R2563)

(R2520-R2537)

ITPCLK/HOOK4

1K series R on PCH Support Page

NOTE: This is not the standard XDP pinout.

OBSDATA_C0

XDP_PRESENT#

DBR#/HOOK7

RESET#/HOOK6

and path to non-XDP signal destination.

Initially, stuffing both 33 and 0 ohms and validate whether

(R2564-R2567)

R252x, R253x, R257x and R259x should be placed where signal path needs to split between route from PCH to J2550

OBSDATA_A2

OBSDATA_B1

NOTE: This is not the standard XDP pinout.

HOOK2

PWRGD/HOOK0

10 25

10 66

9

23 66

9

66

9

66

25

16 23 69

9

66

16 23 69

9

66

23 44

10 23 25 66

23 41

17 25 41

10 23 66

10 23 25 66

9

10 23

16 66

10 23 66

1/16W

5%

MF-LF

1K

NO STUFF

PLACE_NEAR=R1841.1:2.54mm

XDP

5%01/20W

MF

1/20W

PLACE_NEAR=R1840.1:2.54mm

MF

0

XDP

5%

5% MF

XDP

1K

1/20W

PLACE_NEAR=U1000.D44:2.54mm

XDP

5%

1/20W

51

PLACE_NEAR=J2550.51:2.54mm

MF

5%

51

XDP

MF

1/20W

PLACE_NEAR=U1800.U12:2.54mm

1/20W

5%

51

XDP

MF

PLACE_NEAR=U1800.M15:2.54mm

1/20W

5%

51

XDP

MF

PLACE_NEAR=U1800.M17:2.54mm

PLACE_NEAR=U1000.B50:2.54mm

MF

1K

1/20W

5%

XDP

0

PLACE_NEAR=U4900.J3:2.54mm

1/20W

5%

XDP

MF

PLACE_NEAR=U1000.B46:2.54mm

XDP

1/20W

MF

1K

5%

10 66

9

66

9

66

9

66

9

66

33

5% MF

XDP

1/20W 1/20W

5% MF

XDP

33 33

MF

XDP

1/20W

5%

33

1/20W

5% MF

XDP

33

1/20W

5% MF

XDP

33

1/20W

5% MF

XDP

33

1/20W

5% MF

XDP

33

1/20W

5% MF

XDP

33

MF

XDP

1/20W

5%

33

1/20W

MF

XDP

5%

33

5% MF

XDP

1/20W

19 23

8

19

19 23

19

9

23 66

8

16

16 23

19

18 23

18

18 23

XDP

1/20W

5% MF

0

PLACE_NEAR=U4900.J3:2.54mm

25 41 52 62

17 23 41

23

33

MF

XDP

1/20W

5%

33

26

16 25

19 25

0

1/20W

5% MF

MF5%

0

MF5%

1/20W

0

MF5%

1/20W

0

1/20W

MF5%

0

18 23

19 23

33

1/20W

5% MF

XDP

33

1/20W

5% MF

XDP

33

1/20W

5% MF

XDP

1/20W

5% MF

XDP

33

1/20W

5% MF

33

XDP

33

1/20W

MF

XDP

5%

19

18

0

MF5%

9

66

16 23

18 37 62

18 23

8

19 19 23

1K

MF

5%5%

MF

1/20W

1K

39 18 23

40 18 23

M-ST-SM1

CRITICAL XDP_CONN

DF40RC-60DP-0.4V

XDP_CONN

MF-LF

XDP_CPU:BPM

5%

1/16W

0

MF-LF

XDP_CPU:BPM

0

5%

1/16W

PLACE_SIDE=BOTTOM

1/16W

XDP_CPU:BPM

0

5%

MF-LF

PLACE_SIDE=BOTTOM

1/16W

XDP_CPU:BPM

0

5%

MF-LF

5%

XDP_CPU:CFG

0

1/16W

5%

XDP_CPU:CFG

0

MF-LF1/16W

1/16W MF-LF

XDP_CPU:CFG

0

5%

0

XDP_CPU:CFG

MF-LF1/16W

5%

XDP

5%

MF-LF1/16W

330

51

1/16W MF-LF

5%

XDP

PLACE_NEAR=J2500.52:2.54mm

XDP

5%

MF-LF1/16W

51

PLACE_NEAR=U1000.M60:2.54mm

51

1/16W MF-LF

5%

XDP

PLACE_NEAR=U1000.L55:2.54mm

PLACE_NEAR=U1000.L56:2.54mm

XDP

5%

MF-LF1/16W

51

XDP

5%

MF-LF1/16W

51

PLACE_NEAR=U1000.J58:2.54mm

34 19 23

10 66

9

66

9

66

9

66

9

66

23 44

10 23 66

9

66

10 19 66

9

66

10 66

CPU & PCH XDP

SYNC_DATE=10/17/2011

SYNC_MASTER=J13_MLB_NON_POR

CPU_CFG<12>

XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH

XDP_CPU_TRST_L

=PP1V05_SUS_PCH_JTAG

XDP_PCH_TDO

XDP_DB3_SDCONN_STATE_CHANGE

XDP_FC0

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L

CPU_CFG<17>

TP_XDP_PCH_HOOK5

XDP_DD1_JTAG_ISP_TCK

XDP_DC3_SATARDRVR_EN

XDP_DC2_DP_AUXCH_ISOL

XDP_DC1_MXM_GOOD

XDP_DC0_ISOLATE_CPU_MEM_L

XDP_DA0_USB_EXTA_OC_L

XDP_DA2_USB_EXTC_OC_L

TP_XDP_PCH_OBSFN_D<0>

XDP_DD0_DP_GPU_TBT_SEL

XDPPCH_PLTRST_L XDP_DBRESET_L

XDP_PCH_TMS

XDP_PCH_TDI

TP_XDP_PCH_OBSFN_B<0>

XDP_DB1_USB_EXTD_OC_EHCI_L

XDP_PCH_PWRBTN_L

TP_XDPPCH_HOOK3

TP_XDPPCH_HOOK2

=SMBUS_XDP_SDA =SMBUS_XDP_SCL

XDP_DA3_USB_EXTD_OC_L

TP_XDP_PCH_OBSFN_A<0>

XDP_DB2_AP_PWR_EN

XDP_CPU_CLK100M_N

CPU_CFG<5>

CPU_CFG<9>

CPU_CFG<3>

CPU_CFG<2>

CPU_CFG<0>

CPU_CFG<16>

XDP_BPM_L<0> XDP_BPM_L<1>

XDP_BPM_L<2>

CPU_CFG<8>

CPU_CFG<4>

CPU_CFG<6>

XDP_CPU_CLK100M_P

XDP_CPURST_L XDP_DBRESET_L

XDP_CPU_TMS

XDP_CPU_TDI

XDP_CPU_PRDY_L

CPU_CFG<10> CPU_CFG<11>

XDP_CPU_PWRBTN_L

=SMBUS_XDP_SDA =SMBUS_XDP_SCL

XDP_BPM_L<3>

XDP_CPU_PREQ_L

XDP_PCH_TMS

XDP_PCH_TCK

XDP_PCH_TDI

PM_PWRBTN_L

=PP3V3_S0_XDP

ITPXDP_CLK100M_P

XDP_FC0

XDP_DA3_USB_EXTD_OC_L

XDP_DB0_USB_EXTB_OC_EHCI_L XDP_DB1_USB_EXTD_OC_EHCI_L

XDP_DC1_MXM_GOOD

XDP_DD0_DP_GPU_TBT_SEL

XDP_FC1

XDP_DB2_AP_PWR_EN

ALL_SYS_PWRGD

XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH

XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK

XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L

CPU_PWRGD

CPU_RESET_L

ITPXDP_CLK100M_N

XDP_BPM_L<7>

XDP_BPM_L<5>

XDP_BPM_L<4>

XDP_VR_READY

PM_PCH_SYS_PWROK

XDP_DD2_AUD_IPHS_SWITCH_EN

TP_XDP_PCH_HOOK4

XDP_DD3_ENET_LOW_PWR

TP_XDP_PCH_OBSFN_D<1>

XDP_DB3_SDCONN_STATE_CHANGE

XDP_DB0_USB_EXTB_OC_EHCI_L

XDP_DA1_USB_EXTB_OC_L

=PPVCCIO_S0_XDP

XDP_PCH_TCK

CPU_CFG<7>

XDP_CPU_TDO

XDP_CPU_TDI

=PPVCCIO_S0_XDP

XDP_CPU_TMS

XDP_CPU_TCK

XDP_CPU_TRST_L

XDP_PCH_TDO TP_XDP_PCH_TRST_L

USB_EXTA_OC_L USB_EXTB_OC_L

AP_PWR_EN

ISOLATE_CPU_MEM_L

DP_AUXCH_ISOL

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L

XDP_DB2_PCH_GPIO10_AP_PWR_EN XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL

XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH

XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK

TP_XDP_PCH_OBSFN_A<1>

TP_XDP_PCH_OBSFN_B<1>

XDP_PCH_S5_PWRGD

CPU_CFG<13>

XDP_DA1_USB_EXTB_OC_L

XDP_DA0_USB_EXTA_OC_L

XDP_DA2_USB_EXTC_OC_L

XDP_DC0_ISOLATE_CPU_MEM_L

XDP_DC2_DP_AUXCH_ISOL XDP_DC3_SATARDRVR_EN

XDP_DD1_JTAG_ISP_TCK

XDP_DD2_AUD_IPHS_SWITCH_EN XDP_DD3_ENET_LOW_PWR

=PP3V3_S5_XDP

XDP_FC1

SDCONN_STATE_RST_L

XDP_BPM_L<6>

XDP_OBSDATA_B<2>

CPU_CFG<14> CPU_CFG<15>

XDP_CPU_TCK

CPU_CFG<1>

XDP_OBSDATA_B<1>

XDP_OBSDATA_B<0>

XDP_OBSDATA_B<3>

CPU_CFG<0>

PM_PWRBTN_L

M-ST-SM1

CRITICAL

XDP_CPU_CFG<0>

XDP_CPU_PWRGD

1/20W

9

402

402 402 402 402

402

XDP XDP

XDPXDP

X7R-CERM

0402

0.1UF

X7R-CERM 0402

0.1UF

X7R-CERM 0402

0.1UF

X7R-CERM

0402

0.1UF

16V 16V

16V16V

201

201 201 201 201

201

201 201 201 201

201 201

201

201 201

201

201201

10% 10%

10%10%

XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L

XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L

XDP_CPU_TDO

201

XDP

MF5%

1/20W

1K

PLACE_NEAR=J2550.50:2.54mm

201MF5%

1/20W

1K

XDP_FC1_PCH_GPIO0

23

17

XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L

XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L

XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L

XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L

XDP_DB2_PCH_GPIO10_AP_PWR_EN

XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

XDP_FC0_PCH_GPIO15

XDP_FC1_PCH_GPIO0

XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL

XDP_DC3_PCH_GPIO19_SATARDRVR_EN

XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL

XDP_DC1_PCH_GPIO35_MXM_GOOD

XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L

19 23

TBT_CIO_PLUG_EVENT_ISOL

1/20W

66

AUD_IPHS_SWITCH_EN_PCH

JTAG_ISP_TCK

1/20W

2015%

1/20W

MF

0

201

0

MF

1/20W

5%

C2501

1

2

C2500

1

2

C2580

1

2

C2581

1

2

R2540

1

2

R2515

12

R2516

12

R2505

12

R2550

21

R2551

21

R2552

21

R2556

21

R2501

12

R2502

12

R2500

12

R2524

12

R2525

12

R2526

12

R2527

12

R2530

12

R2532

12

R2533

12

R2534

12

R2535

12

R2536

12

R2537

12

R2584

12

R2585

12

R2521

12

R2597

12

R2596

12

R2572

12

R2570

12

R2576

12

R2528

12

R2529

12

R2520

12

R2522

12

R2523

12

R2531

12

R2575

12

R2580

12

R2581

12

R2590

12

R2592

12

J2500

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

61

62

6364

78

9

J2550

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

61

62

6364

78

9

R2560

12

R2561

12

R2562

12

R2563

12

R2564

12

R2565

12

R2566

12

R2567

12

R2504

12

R2510

12

R2511

12

R2512

12

R2513

12

R2514

12

R2574

12

051-9277

2.8.0

25 OF 109

23 OF 73

7

16 23 69

23

6

23

23 23

23

6

23

6

23

6

23

6

23

66

16 23 69

7

23

6

23

6

23

7

23

10 23 66

7

23

10 23 66

6

7

23

66

BI

IN

VCC

GND

SELOE*

D+ D-

Y+ Y-

M+ M-

BI

NC

BI

VDD33

PLLFILT

CRFILT

SUSP_IND/LOCAL_PWR/NON_REM0

SDA/SMBDATA/NON_REM1

SCL/SMBCLK/CFG_SEL0

HS_IND/CFG_SEL1

XTALIN/CLKIN XTALOUT

TEST

RESET*

THRM_PAD

USBDP_UP

NC

OSC3*

OCS1* OCS2*

USBDM_UP

RBIAS

VBUS_DET

NC

NC NC

USBDP_DN3/PRT_DIS_P3

USBDM_DN3/PRT_DIS_M3

USBDP_DN2/PRT_DIS_P2

USBDM_DN2/PRT_DIS_M2

USBDP_DN1/PRT_DIS_P1

USBDM_DN1/PRT_DIS_M1

PRTPWR3/BC_EN3*

PRTPWR1/BC_EN1* PRTPWR2/BC_EN2*

SYM VER 1

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_5_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

1 1 Port 1, 2, and 3 are non removable

SMC Port

PULL-UP TO 3.3V SUS ON PCH PAGE, SEL PIN IS LEAKAGE-SAFE

SDCARD(NA to K78)

IPU

TO LIO CONNECTOR

SEL=0 CHOOSE USB EHCI2 PORT

PCH GPIO60

BlueTooth

SEL=1 CHOOSE USB XHCI PORT

0 1 Port 1 is non removable

0 0 All ports are removable

BOM TABLE

TO PCH XHCI

Trackpad/Keyboard

TO USB HUB

PCH PORT 1 (XHCI)

PCH PORT 9 (EHCI2)

TO TP/KB

TO CONNECT TP/KB TO PCH XHCI

LIO External D

1 0 Port 1 and 2 are non removable

NON_REM1 NON_REM0 DESCRIPTION

IPU

NOSTUFF R2611 & R2615, STUFF R2621 & R2622,R2616 & R2617

USB XHCI/EHCI2 PORT MUX FOR EXT B

NC_USB_HUB1_PRTPWR2

USB_SDCARD_P

USB_BT_P

USB_TPAD_HUB_P

USB_SMC_P

USB_SMC_N

USB_SDCARD_N

TP_USB_HUB1_PRTPWR1

NC_USB_HUB1_OCS2

NC_USB_HUB1_PRTPWR3

USB_HUB1_RBIAS

NC_USB_HUB1_OCS4

NC_USB_HUB1_OCS3

USB_HUB_UP_N

USB_HUB1_CFG_SEL0

USB_HUB1_CFG_SEL1

USB_BT_N

USB_HUB_UP_P

USB_HUB1_TEST

USB_HUB_RESET_L

USB_EXTB_P

USB_TPAD_HUB_N

USB_EXTB_N

USB_EXTB_SEL_XHCI

USB_EXTB_EHCI_P

USB_HUB1_VBUS_DET

USB_HUB_RESET_L

=PP3V3_S3_USB_HUB

USB_EXTB_XHCI_N

=PP3V3_S3_USB_RESET

USB_SMC_N

USB_EXTB_EHCI_N

USB_EXTB_XHCI_P

USB_HUB1_NONREM0

USB_HUB1_NONREM1

USB_HUB1_XTAL1 USB_HUB1_XTAL2

USB_SMC_P

USB_TPAD_HUB_P

=PP3V3_S3_USB_HUB

TP_USB_HUB1_OCS1

NC_USB_HUB1_PRTPWR4

PPUSB_HUB1_CRFILT

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.8V

=PP3V3_S3_USB_HUB

USB_TPAD_HUB_N

USB_TPAD_R_N

USB_EXTD_XHCI_P

USB_TPAD_R_P

USB_EXTD_XHCI_N

MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.8V

PPUSB_HUB1_PLLFILT

MIN_LINE_WIDTH=0.4MM

=PP3V3_S3_USB_HUB

=PP3V3_S3_USBMUX

IC,USB2513B,USB 2.0,HUB CNTRL,3PRT,36QFN

CRITICAL

USBHUB2513B

338S0923

1

U2600

USBHUB2512B

CRITICAL

IC,USB2512B,USB 2.0 HUB CNTRL,36-QFN

U2600

1

338S0983

HUB_ALLREM

HUB_NONREM1_0,HUB_NONREM0_0

HUB_1NONREM

HUB_NONREM1_0,HUB_NONREM0_1

HUB_NONREM1_1,HUB_NONREM0_1

HUB_3NONREM

HUB_2NONREM

HUB_NONREM1_1,HUB_NONREM0_0

IC,USB2514B,USB 2.0,HUB CNTRL,4PRT

U2600

USBHUB2514B

CRITICAL

338S0824

1

USB HUB & MUX

SYNC_DATE=11/10/2011

SYNC_MASTER=J13_MLB_NON_POR

HUB_NONREM1_0

5%

10K

1/20W

MF

201

1/20W

10K

HUB_NONREM0_0

5%

MF 201

HUB_NONREM1_1

10K

MF

5%

1/20W

201

HUB_NONREM0_1

5%

10K

1/20W MF 201

1/20W

10K

201

MF

5%

5% 1/20W MF

10K

201

1/20W

5%

10K

201

MF

0.1UF

0201

X5R-CERM

16V

10%

CRITICAL

OMIT_TABLE

QFN

USB2513B

NP0-C0G-CERM

CRITICAL

201

6.0PF

+/-0.1PF

25V

CRITICAL

1M

1/20W

5%

MF

201

CRITICAL

25V

6.0PF

+/-0.1PF

NP0-C0G-CERM

5%

100

1/20W

MF

201

68 37

4.7UF

20%

6.3V

X5R-CERM1

402

BYPASS=U2600.23::5mm

BYPASS=U2600.5::5mm

20%

4.7UF

6.3V

402

X5R-CERM1

0201

BYPASS=U2600.29::2mm

16V

10%

X5R-CERM

0.1UF

BYPASS=U2600.5::2mm

0.1UF

10%

0201

X5R-CERM

16V

BYPASS=U2600.10::2mm

X5R-CERM

0.1UF

10% 16V

0201

X5R-CERM

BYPASS=U2600.34::2mm

0.1UF

16V

10%

0201

BYPASS=U2600.23::2mm

0201

16V

10%

X5R-CERM

0.1UF

BYPASS=U2600.15::2mm

10%

0201

16V

0.1UF

X5R-CERM

68 37

1UF

0201

20%

6.3V X5R

X5R-CERM

0.1UF

10% 16V

0201

68 18

CRITICAL

MF 201

12K

1% 1/20W

68 18

24.000MHZ-50PPM-6PF

2.50X2.00MM-SM

CRITICAL

1/20W MF

5%

201

NOSTUFF

10K

NOSTUFF

10K

1/20W

201

MF

5%

68 18

TPAD_PCH:YES

1/20W

5%

0

201

MF

68 18

TPAD_PCH:YES

201

0

5%

1/20W

MF

68 33

PLACE_NEAR=U2600.26:2.5MM

0201

10% 16V

X5R-CERM

0.1UF

10K

201

1/20W

5%

MF

201

5%

10K

1/20W

TPAD_PCH:YES

201

MF

10K

5%

1/20W

TPAD_PCH:YES

68 24

MF

0

5%

1/20W

201

TPAD_PCH:NO

MF

5%

1/20W

0

201

TPAD_PCH:NO

68 33

10%

0.1UF

X5R-CERM

16V

0201

68 24

68 41 24

68 18

68 24

PI3USB102ZLE

TQFN

CRITICAL

16

68 40

6

68 40

6

0201

20%

6.3V X5R

1UF

C2618

1

2

C2617

1

2

C2616

1

2

C2615

1

2

R2620

1

2

R2600

1

2

C2612

1

2

C2611

1

2

C2603

1

2

C2610

1

2

C2609

1

2

C2608

1

2

C2602

1

2

C2607

1

2

R2605

12

C2620

1

2

R2630

12

C2619

1

2

U2600

14

25

8 9

20

21

13 17 19

34

12 16 18

35

26

24

22

28

11

37

1

3

6

30

2

4

7

31

27

510152329

36

33 32

R2607

1

2

R2606

1

2

R2603

1

2

R2601

1

2

R2604

1

2

R2602

1

2

U2660

6

7

3

4

5

8

10

9

2

1

C2663

1

2

R2615

12

R2611

12

R2617

1

2

R2616

1

2

R2612

1

2

C2604

1

2

R2621

12

R2622

12

R2619

1

2

R2618

1

2

Y2600

24

13

051-9277

2.8.0

26 OF 109

24 OF 73

24

7

68 41 24

24

7

24

7

68 49

24

7

OUT

PAD

+3.42V

VDD_25M

+V3.3A

VDDIO_25M_C

VDDIO_25M_B

VDDIO_25M_A

25MHZ_C

25MHZ_B

25MHZ_A

X1

X2

VDD_RTC_OUT

THRM

GND

32KHZ_A

NC NC

OUT

IN

NC

OUT

IN

OUT

IN

BIIN

NC

OUT

08

Y1

Y2

GND

B2

VCC

A1 B1 A2

IN

OUT

D

SG

D

SG

IN

OUT

D

GS

IN

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

GPIO Glitch Prevention

System RTC Power Source & 32kHz / 25MHz Clock Generator

No Coin-Cell: 3.3V S5

For SB RTC Power

Ground VDDIO of unused CLK

Buffered

DP_AUXIO_EN Inversion

Coin-Cell: VBAT (300-ohm & 10uF RC)

VTT voltage divider on CPU page

PCH Reset Button

Platform Reset Connections

Unbuffered

GreenClk 25MHz Power

create VDD_RTC_OUT.

Powered in S0

SB XTAL Power

TBT XTAL Power

available ~3.3V power

Coin-Cell & G3Hot: 3.42V G3Hot

No Coin-Cell: 3.42V G3Hot (no RC)

No bypass necessary

Coin-Cell & No G3Hot: 3.3V S5

IPD = 9-50k

SMC controls strap enable to allow in-field control of strap setting. Q2620 & 5V pull-up allows circuit to work regardless of HDA voltage.

If high, ME is disabled. This allows for full re-flashing of SPI ROM.

PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.

VBAT and +V3.3A are

internally ORed to

+V3.3A should be first

to reduce VBAT draw.

outputs for power savings

PCH ME Disable Strap

Buffered

scrub for layout optimization

NOTE: 30 PPM crystal required

PCH S0 PWRGD

5%

12PF

0201

NP0-C0G-CERM

25V

5%

12PF

0201

NP0-C0G-CERM

25V

5%

201

CRITICAL

SMC_DELAYED_PWRGD

25.000MHZ-12PF-20PPM

AUD_IPHS_SWITCH_EN

=PP3V3_S0_SYSCLKGEN

=PPVDDIO_TBT_CLK

SYSCLK_CLK25M_TBT

=PP3V3_S5_PCHPWRGD

MAKE_BASE=TRUE

PM_PCH_PWROK

=PP3V3_S0_RSTBUF

PLT_RST_CPU_BUF_L

MAKE_BASE=TRUE

=PP3V3_S0_RSTBUF

=PPVBAT_G3H_SYSCLK

XDP_DBRESET_L

PM_SYSRST_L

=PP3V3_S0_SB_PM

=PPVRTC_G3_OUT

SPI_DESCRIPTOR_OVERRIDE_LS5V

BKLT_PLT_RST_L

SPI_DESCRIPTOR_OVERRIDE

MAKE_BASE=TRUE

LPCPLUS_RESET_L

CPU_RESET_L

DP_AUXIO_EN

DP_AUXCH_ISOL

SYS_PWROK_R

PCH_CLK33M_PCIOUT

LPC_CLK33M_LPCPLUS

PCH_CLK33M_PCIIN

SYSCLK_CLK32K_RTC

SYSCLK_CLK25M_SB

LPC_CLK33M_SMC

SMC_LRESET_L

=PP5V_S0_PCH

=PP3V3R1V5_S0_PCH_VCCSUSHDA

HDA_SDOUT_R

SPI_DESCRIPTOR_OVERRIDE_L

AUD_IPHS_SWITCH_EN_PCH

=PP3V3_S0_SB_PM

=PP3V3_S5_SYSCLK

=PPVDDIO_S0_SBCLK

PM_PCH_APWROK

LPC_CLK33M_LPCPLUS_R

LPC_CLK33M_SMC_R

=PP3V3_S0_PCH_GPIO

SYSCLK_CLK25M_X2_R

PM_S0_PGOOD

PM_PCH_SYS_PWROK

SYSCLK_CLK25M_X2

SYSCLK_CLK25M_X1

CPUIMVP_PGOOD

ALL_SYS_PWRGD

SDCARD_PLT_RST_L

=TBT_RESET_L

TBT_RESET_L

MAKE_BASE=TRUE

PLT_RESET_L

AP_RESET_L

PCA9557D_RESET_L

PLT_RST_BUF_L

XDPPCH_PLTRST_L

SSD_RESET_L

LPC_PWRDWN_L

PM_PCH_PWROK

=PP3V3_S5_PCHPWRGD

SYNC_MASTER=K21_MLB

SYNC_DATE=07/29/2011

Clock (CK505) and Chipset Support

25 17

MF

1/20W

0

37

1K

1/20W

MF

XDP

23

0

1/20W

MF

36

0

1/20W

MF

31

XDP

0

1/20W

MF

10K

MF

1/20W

0201

X5R

1UF

20%

6.3V

0201

20%

X5R

1UF

0201

0.1UF

10%

X5R-CERM

16V

MF

1/20W

100K

38

6

0

MF

1/20W

SC70-HF

MC74VHC1G08

CRITICAL

23 16

NO STUFF

1/20W

10K

MF

CRITICAL

SSM3K15FV

SOD-VESM-HF

1/20W

MF

10K

0.1UF

0201

10% 16V

X5R-CERM

64

41

SSM6N37FEAPE

SOT563

SSM6N37FEAPE

69 16

1/20W MF

1K

1/20W MF

100K

23 19

43 41 17

6

16

40

6

34

MF-LF

1/16W

0

NO STUFF

SILK_PART=SYS RESET

402

0

1/20W

MF

1M

NO STUFF

1/20W

0

MF

1/20W

0201

X5R-CERM

0.1UF

10%

16V

0.1UF

0201

16V

10%

X5R-CERM

66 23 10 41 17

57

62 52 41 23

1K

1/20W

MF

PLACE_NEAR=U1800.P12:7mm

MC74VHC1G08

SC70-HF

16V X5R-CERM

10%

0.1UF

0201

MC74VHC1G08

SC70-HF

0.1UF

10% 16V

0201

X5R-CERM

0

MF

1/20W

MF

3.0K

0

NO STUFF

MF

1/20W

PLACE_NEAR=U1800.M10:5.54mm

NO STUFF

1/20W

MF

0

17

25 17

41 23 17

69 18

PLACE_NEAR=U1800.G45:2.54MM:5.1mm

MF

1/20W

22

MF

1/20W

22

PLACE_NEAR=U1800.E49:5.1mm

MF

22

1/20W

PLACE_NEAR=U1800.G51:5.1mm

69 16

69 43

6

69 41

0.1UF

16V

0201

10%

X5R-CERM

SC70

74LVC1G07

100K

1/20W MF

0

1/20W

MF

26 18

MF

1/20W

33

1/20W

MF

33

23 10

65

33

41

69 43

6

SM-3.2X2.5MM

SLG3NB148A

CRITICAL

TQFN

69 34

69 16

CRITICAL

74LVC2G08GT

SOT833

TBT_PWR_EN_PCH

TBT_PWR_EN

0201

0.1UF

10%

X5R-CERM

16V

=PP3V3_S3_PCH_GPIO

U2700

9

8

15

12

71016

13

2

17

5

1

11

6

14

4

3

Y2705

24

13

C2705

12

C2706

12

R2783

12

R2781

12

R2793

12

R2780

1

2

U2780

2

3

5

4

C2780

1

2

R2727

12

R2726

12

R2729

12

R2761

1

2

R2763

12

R2762

12

R2760

12

C2760

1

2

U2760

3

2

1

4

5

C2750

1

2

U2750

3

2

1

4

5

R2750

1

2

C2722

1

2

C2724

1

2

R2705

12

R2706

1

2

R2782

12

R2797

1

2

U2752

1

5

2

6

4

8

7

3

R2720

1

2

R2721

1

2

Q2720

3

5

4

Q2720

6

2

1

C2739

1

2

R2730

12

Q2730

3

1

2

R2731

1

2

U2771

3

2

1

4

5

R2772

12

R2770

1

2

C2771

1

2

C2752

1

2

C2702

1

2

C2710

1

2

R2795

1

2

R2796

12

R2771

12

R2773

12

R2789

12

R2788

12

051-9277

2.8.0

27 OF 109

25 OF 73

1

7

25

7

25

7

25

7

25

7

22

7

22 20

7

25

7

36 19 18 17 16

7

69

42 41 36

69

18

7

25

7

IN

D

SG

D

SG

D

SG

D

SG

OUT

D

SG

D

SG

IN

OUT

G

D

S

D

SG

IN

D

SG

IN

S0_READY

ISOL*

S0_EN

S3_EN

RST_IN*

GND

THRM

VDD

VTT_EN

VDDIO_EN

RST_OUT*

PAD

OUT

IN

OUT

IN

D

SG

D

SG

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Step ISOLATE_CPU_MEM_L PLT_RESET_L PM_SLP_S3_L PM_SLP_S4_L CPU_MEM_RESET_L MEM_RESET_L MEMVTT_EN P1V5CPU_EN

(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO.

transition. Rails will power-up as if from S3, but MEM_RESET_L will not properly assert. Software

7 1 1 1 1 1 CPU_MEM_RESET_L 1 1

3 0 0 0 1 X 1 0 0

0 1 1 1 1 1 CPU_MEM_RESET_L 1 1

S3

S0

2 0 0 1 1 1 1 0 1

WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.

ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.

The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well

1V5 S0 "PGOOD" for CPU

75mA max load @ 0.75V

60mW max power

to

S0

MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L

MEMVTT_EN = (ISOLATE_CPU_MEM_L + PLT_RST_L) * PM_SLP_S3_L

WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated.

MEMVTT Clamp

Ensures CKE signals are held low in S3

must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.

PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page

NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0

6 0 1 1 1 1 1 1 1

5 0 1 1 1 0 (*) 1 1 1

4 0 0 1 1 X 1 0 1

1 0 1 1 1 1 1 1 1

P1V5CPU_EN = (ISOLATE_CPU_MEM_L + PM_SLP_S3_L) * PM_SLP_S4_L

as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.

26 37 41 49 62

10K

5% 1/20W MF

CPUMEM_SLG:NO

18 25 26

SOT563

SSM6N37FEAPE

CPUMEM_SLG:NO

SSM6N37FEAPE

MF

100K

1/20W

5%

CPUMEM_SLG:NO

SOT563

SSM6N37FEAPE

CPUMEM_SLG:NO

100K

5%

1/20W

MF

SSM6N37FEAPE

CPUMEM_SLG:NO

SOT563

26 61

26 27 28 29 30

SOT563

SSM6N37FEAPE

CPUMEM_SLG:NO

SOT563

SSM6N37FEAPE

CPUMEM_SLG:NO

23 26

5% MF

100K

CPUMEM_SLG:NO

1/20W

10

10 17 66

10K

5% 1/20W MF

CPUMEM_SLG:NO

MF-LF

603

5%

1/10W

10

SOT-563

CRITICAL

DMB53D0UV

MF

1/20W

5%

10K

SOT-563

DMB53D0UV

SSM6N37FEAPE

SOT563

100K

5% MF

1/20W

17 26 41 62

SOT563

SSM6N37FEAPE

MF

1%

27.4K

1/20W

8

56

0.1UF

0201

X5R-CERM

0

5%

1/20W

MF

CPUMEM_SLG:NO

TQFN

SLG4AP022

CPUMEM_SLG:YES

8

26

26 27 28 29 30

23 26

18 25 26

17 26 41 62

17 26 37 41 49 62

26 61

10 26

X5R

6.3V

0.1UF

CPUMEM_SLG:YES

SOT563

CPUMEM_SLG:NO

SSM6N37FEAPE

43.2K

1%

MF

1K

5% 1/20W MF

SOT563

SSM6N37FEAPE

CPUMEM_SLG:NO

8

26

CPU Memory S3 Support

SYNC_DATE=11/10/2011

SYNC_MASTER=J13_MLB_NON_POR

ISOLATE_CPU_MEM_L_R

VTTCLAMP_EN

=PP1V5_S3_MEMRESET

MEM_RESET_L

PM_MEM_PWRGD_L

PM_MEM_PWRGD

=PP3V3_S5_CPU_VCCDDR

=PPVTT_S0_VTTCLAMP

=PP3V3_S3_MEMRESET

MEM_RESET_L

P1V5CPU_EN

=DDRVTT_EN

=PP5V_S3_MEMRESET

VTTCLAMP_L

PLT_RESET_L

ISOLATE_CPU_MEM_L

P1V5CPU_EN

PM_SLP_S4_L

=PP5V_S3_MEMRESET

MEMVTT_EN_L

P1V5CPU_EN_L

MEMVTT_EN

PM_SLP_S3_L

CPU_MEM_RESET_L

MAKE_BASE=TRUE

PM_SLP_S3_L

ISOLATE_CPU_MEM_L

=MEM_RESET_L

=PP1V5_S3_CPU_VCCDDR

P1V5_S0_DIV

PM_SLP_S4_L

CRITICAL

1/20W

201

201201

201

NO STUFF

X7R-CERM

0201

1000PF

X7R-CERM

0201

1000PF

=MEM_RESET_L

MEMRESET_ISOL_LS5V_L

PLT_RESET_L

CPUMEM_SLG:NO

SOT563

=PP3V3_S3_MEMRESET

26

17

16V

10%

NO STUFF

16V

X7R-CERM

0402

0.047UF

10%

R2805

1

2

Q2805

6

2

1

Q2805

3

5

4

R2810

1

2

Q2810

6

2

1

Q2810

3

5

4

R2801

1

2

Q2800

3

5

4

R2802

1

2

Q2800

6

2

1

Q2815

3

5

4

Q2815

6

2

1

R2815

1

2

R2850

1

2

Q2820

6

2

1

R2822

1

2

Q2820

5

3

4

C2820

1

2

Q2850

6

2

1

C2851

1

2

R2851

1

2

Q2850

3

5

4

R2820

1

2

C2816

1

2

C2817

1

2

R2890

12

U2800

5

9

7

8

3

1

6

11

10

4

2

C2800

1

2

R2821

1

2

R2816

1

2

051-9277

2.8.0

28 OF 109

26 OF 73

31

7

26

7

26

7

26

7

26

7

10 12 15

NF_DQ6 NF_DQ7

NF_DQ5

NF_DQ4

A1

VREFDQ

VREFCA

VDD

VDDQ

ODT0 ODT1

RESET*

ZQ0

A0

A2 A3 A4

A6

A10/AP A11 A12/BC* A13

A14

BA0 BA1 BA2

CKE1

RAS*

WE*

CAS*

CS1* CS0*

ZQ1

DQ0 DQ1 DQ2 DQ3

DQS*

DM/TDQS

NF_TDQS*

NC

VSS

CK*

CKE0

DQS

CK

VSSQ

A8 A9

A5

A7

A15

NF_DQ6 NF_DQ7

NF_DQ5

NF_DQ4

A1

VREFDQ

VREFCA

VDD

VDDQ

ODT0 ODT1

RESET*

ZQ0

A0

A2 A3 A4

A6

A10/AP A11 A12/BC* A13

A14

BA0 BA1 BA2

CKE1

RAS*

WE*

CAS*

CS1* CS0*

ZQ1

DQ0 DQ1 DQ2 DQ3

DQS*

DM/TDQS

NF_TDQS*

NC

VSS

CK*

CKE0

DQS

CK

VSSQ

A8 A9

A5

A7

A15

NF_DQ6 NF_DQ7

NF_DQ5

NF_DQ4

A1

VREFDQ

VREFCA

VDD

VDDQ

ODT0 ODT1

RESET*

ZQ0

A0

A2 A3 A4

A6

A10/AP A11 A12/BC* A13

A14

BA0 BA1 BA2

CKE1

RAS*

WE*

CAS*

CS1* CS0*

ZQ1

DQ0 DQ1 DQ2 DQ3

DQS*

DM/TDQS

NF_TDQS*

NC

VSS

CK*

CKE0

DQS

CK

VSSQ

A8 A9

A5

A7

A15

NF_DQ6 NF_DQ7

NF_DQ5

NF_DQ4

A1

VREFDQ

VREFCA

VDD

VDDQ

ODT0 ODT1

RESET*

ZQ0

A0

A2 A3 A4

A6

A10/AP A11 A12/BC* A13

A14

BA0 BA1 BA2

CKE1

RAS*

WE*

CAS*

CS1* CS0*

ZQ1

DQ0 DQ1 DQ2 DQ3

DQS*

DM/TDQS

NF_TDQS*

NC

VSS

CK*

CKE0

DQS

CK

VSSQ

A8 A9

A5

A7

A15

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

NC

A14/A15 FOR 2G/4G MONO ONLY

CS1 IS FOR 2G DDP RANK CONTROL

240

MF

1%

1/20W

201201

1/20W

1%

MF

240

1/20W

MF

240

201

1%

240

201

1/20W

1%

MF

MT41K1G4

512MX8-4GBIT-DDR3-1600

OMIT_TABLE

FBGA-9P5X11P65-COMBO

MT41K1G4

512MX8-4GBIT-DDR3-1600

OMIT_TABLE

FBGA-9P5X11P65-COMBO

MT41K1G4

512MX8-4GBIT-DDR3-1600

OMIT_TABLE

FBGA-9P5X11P65-COMBO

512MX8-4GBIT-DDR3-1600

OMIT_TABLE

FBGA-9P5X11P65-COMBO

MT41K1G4

201

4V

CERM-X5R-1

0.47UF

20%

201

4V

CERM-X5R-1

0.47UF

20%

201

4V

CERM-X5R-1

0.47UF

20%

201

4V

CERM-X5R-1

0.47UF

20%

201

20%

0.47UF

CERM-X5R-1

4V

201

4V

CERM-X5R-1

0.47UF

20%

201

20%

0.47UF

CERM-X5R-1

4V

201

4V

CERM-X5R-1

0.47UF

20%

201

4V

CERM-X5R-1

0.47UF

20%

201

20%

0.47UF

CERM-X5R-1

4V

201

4V

CERM-X5R-1

0.47UF

20%

201

4V

CERM-X5R-1

0.47UF

20%

201

240

1/20W

1%

MF

201

240

1/20W

1%

MF

201

240

1/20W

1%

MF

201

240

1/20W

1%

MF

SYNC_MASTER=K21_MLB

SYNC_DATE=07/28/2011

DDR3 DRAM CHANNEL A (0-31)

MEM_A_A<15>

MEM_A_A<14>

MEM_A_A<12>

MEM_A_A<13>

MEM_A_CLK_P<0>

MEM_A_BA<0>

MEM_A_A<15>

MEM_A_A<9>

MEM_A_A<0>

MEM_A_A<7>

MEM_A_A<8>

MEM_A_CLK_P<0>

MEM_A_DQS_P<0>

MEM_A_CKE<0>

MEM_A_CLK_N<0>

MEM_A_DQS_N<0>

MEM_A_DQ<4>

MEM_A_CS_L<0>

MEM_A_CAS_L

MEM_A_WE_L

MEM_A_RAS_L

MEM_A_CKE<1>

MEM_A_BA<2>

MEM_A_BA<1>

MEM_A_BA<0>

MEM_A_A<11>

MEM_A_A<10>

MEM_A_A<6>

MEM_A_A<3>

MEM_A_A<2>

MEM_RESET_L

MEM_A_ODT<0>

MEM_A_A<1>

MEM_A_DQ<5>

MEM_A_DQ<0>

MEM_A_DQ<6>

MEM_A_A<7>

MEM_A_A<9>

MEM_A_DQS_P<1>

MEM_A_CKE<0>

MEM_A_CLK_N<0>

MEM_A_DQS_N<1>

MEM_A_DQ<12>

MEM_A_DQ<15>

MEM_A_DQ<14>

MEM_A_DQ<8>

MEM_A_CS_L<0>

MEM_A_CS_L<1>

MEM_A_CAS_L

MEM_A_WE_L

MEM_A_RAS_L

MEM_A_CKE<1>

MEM_A_BA<2>

MEM_A_BA<1>

MEM_A_BA<0>

MEM_A_A<14>

MEM_A_A<13>

MEM_A_A<12>

MEM_A_A<11>

MEM_A_A<6>

MEM_A_A<5>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_A<2>

MEM_A_A<0>

MEM_RESET_L

MEM_A_ODT<1>

MEM_A_ODT<0>

MEM_A_A<1>

MEM_A_DQ<10>

MEM_A_DQ<13>

MEM_A_DQ<9>

MEM_A_DQ<11>

MEM_A_A<7>

MEM_A_A<9>

MEM_A_A<8>

MEM_A_CLK_P<0>

MEM_A_DQS_P<2>

MEM_A_CKE<0>

MEM_A_CLK_N<0>

MEM_A_DQS_N<2>

MEM_A_DQ<20>

MEM_A_DQ<23>

MEM_A_CS_L<0>

MEM_A_CS_L<1>

MEM_A_CAS_L

MEM_A_WE_L

MEM_A_RAS_L

MEM_A_CKE<1>

MEM_A_BA<2>

MEM_A_BA<1>

MEM_A_BA<0>

MEM_A_A<14>

MEM_A_A<13>

MEM_A_A<12>

MEM_A_A<11>

MEM_A_A<10>

MEM_A_A<6>

MEM_A_A<5>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_A<2>

MEM_A_A<0>

MEM_RESET_L

MEM_A_ODT<1>

MEM_A_ODT<0>

MEM_A_A<1>

MEM_A_DQ<22>

MEM_A_DQ<16>

MEM_A_DQ<21>

MEM_A_DQ<18>

MEM_A_A<7>

MEM_A_A<9>

MEM_A_A<8>

MEM_A_CLK_P<0>

MEM_A_DQS_P<3>

MEM_A_CKE<0>

MEM_A_CLK_N<0>

MEM_A_DQS_N<3>

MEM_A_DQ<30>

MEM_A_DQ<27>

MEM_A_DQ<28>

MEM_A_CS_L<0>

MEM_A_CS_L<1>

MEM_A_CAS_L

MEM_A_WE_L

MEM_A_RAS_L

MEM_A_CKE<1>

MEM_A_BA<2>

MEM_A_BA<1>

MEM_A_A<14>

MEM_A_A<13>

MEM_A_A<12>

MEM_A_A<11>

MEM_A_A<10>

MEM_A_A<6>

MEM_A_A<5>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_A<2>

MEM_A_A<0>

MEM_RESET_L

MEM_A_ODT<1>

MEM_A_ODT<0>

MEM_A_A<1>

MEM_A_DQ<25>

MEM_A_DQ<24>

MEM_A_DQ<31>

MEM_A_DQ<29>

MEM_A_DQ<2>

MEM_A_DQ<17>

MEM_A_DQ<19>

=PP1V5_S3_MEM_A

PP0V75_S3_MEM_VREFCA_A

PP0V75_S3_MEM_VREFDQ_A

=PP1V5_S3_MEM_A

PP0V75_S3_MEM_VREFCA_A

PP0V75_S3_MEM_VREFDQ_A PP0V75_S3_MEM_VREFDQ_A

=PP1V5_S3_MEM_A

PP0V75_S3_MEM_VREFCA_A

=PP1V5_S3_MEM_A

MEM_A_DQ<26>

MEM_A_DQ<7>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_A<4>

MEM_A_A<5>

MEM_A_A<8>

MEM_A_A<10>

MEM_A_CS_L<1>

PP0V75_S3_MEM_VREFCA_A

MEM_A_ZQ0

MEM_A_ZQ4

MEM_A_ZQ1

MEM_A_ZQ5

MEM_A_ZQ2

MEM_A_ZQ6

MEM_A_ZQ3

MEM_A_ZQ7

MEM_A_ODT<1>

MEM_A_DQ<1>

MEM_A_DQ<3>

MEM_A_ZQ5

MEM_A_ZQ6

MEM_A_ZQ7

MEM_A_ZQ4

R2930

12

R2920

12

R2910

12

R2900

12

U2930

K3 L7

H7 M7 K7 N3 N7 J7

L3 K2 L8 L2 M8 M2 N8 M3

J2 K8 J3

G3

F7 G7

G9 F9

H2

H1

B7

B3 C7 C2 C8

C3

D3

A3

79 80 81 82

E3 E8 D2 E7

A7

G1

F1

F3

N2

A2A9D7G2G8K1K9M1M9B9C1E2E9

J8

E1

A1

A8

N1

N9

B1D8F2F8J1J9L1

L9

B2B8C9D1D9

H3

H8 H9

U2920

K3 L7

H7 M7 K7 N3 N7 J7

L3 K2 L8 L2 M8 M2 N8 M3

J2 K8 J3

G3

F7 G7

G9 F9

H2

H1

B7

B3 C7 C2 C8

C3

D3

A3

79 80 81 82

E3 E8 D2 E7

A7

G1

F1

F3

N2

A2A9D7G2G8K1K9M1M9B9C1E2E9

J8

E1

A1

A8

N1

N9

B1D8F2F8J1J9L1

L9

B2B8C9D1D9

H3

H8 H9

U2910

K3 L7

H7 M7 K7 N3 N7 J7

L3 K2 L8 L2 M8 M2 N8 M3

J2 K8 J3

G3

F7 G7

G9 F9

H2

H1

B7

B3 C7 C2 C8

C3

D3

A3

79 80 81 82

E3 E8 D2 E7

A7

G1

F1

F3

N2

A2A9D7G2G8K1K9M1M9B9C1E2E9

J8

E1

A1

A8

N1

N9

B1D8F2F8J1J9L1

L9

B2B8C9D1D9

H3

H8 H9

U2900

K3 L7

H7 M7 K7 N3 N7 J7

L3 K2 L8 L2 M8 M2 N8 M3

J2 K8 J3

G3

F7 G7

G9 F9

H2

H1

B7

B3 C7 C2 C8

C3

D3

A3

79 80 81 82

E3 E8 D2 E7

A7

G1

F1

F3

N2

A2A9D7G2G8K1K9M1M9B9C1E2E9

J8

E1

A1

A8

N1

N9

B1D8F2F8J1J9L1

L9

B2B8C9D1D9

H3

H8 H9

C2900

1

2

C2901

1

2

C2902

1

2

C2910

1

2

C2911

1

2

C2912

1

2

C2920

1

2

C2921

1

2

C2922

1

2

C2930

1

2

C2931

1

2

C2932

1

2

R2901

12

R2911

12

R2921

12

R2931

12

27 OF 73

29 OF 109

051-9277

2.8.0

11 27 28 32 67

11 67

11 27 28 32 67

11 67

11 27 28 32 67

26 27 28 29 30

11 27 28 32 67

11 67

11 27 28 32 67

11 27 28 32 67 11 67

11 27 28 32 67

11 67

11 27 28 32 67

26 27 28 29 30

11 27 28 32 67

11 67

11 27 28 32 67

11 67

11 27 28 32 67

11 67

11 27 28 32 67

26 27 28 29 30

11 27 28 32 67

11 67

11 27 28 32 67

11 67

11 27 28 32 67

11 67

11 27 28 32 67

26 27 28 29 30

11 27 28 32 67

11 67

11 67 11 67

11 67

7

27 28 32

27 28 31 67

7

27 28 32

27 28 31 67

27 28 31 67 27 28 31 67

7

27 28 32

27 28 31 67

7

27 28 32

11 67

27 28 31 67

11 27 28 32 67

27 28 31 67

11 27 28 32 67

11 67

27

NF_DQ6 NF_DQ7

NF_DQ5

NF_DQ4

A1

VREFDQ

VREFCA

VDD

VDDQ

ODT0 ODT1

RESET*

ZQ0

A0

A2 A3 A4

A6

A10/AP A11 A12/BC* A13

A14

BA0 BA1 BA2

CKE1

RAS*

WE*

CAS*

CS1* CS0*

ZQ1

DQ0 DQ1 DQ2 DQ3

DQS*

DM/TDQS

NF_TDQS*

NC

VSS

CK*

CKE0

DQS

CK

VSSQ

A8 A9

A5

A7

A15

NF_DQ6 NF_DQ7

NF_DQ5

NF_DQ4

A1

VREFDQ

VREFCA

VDD

VDDQ

ODT0 ODT1

RESET*

ZQ0

A0

A2 A3 A4

A6

A10/AP A11 A12/BC* A13

A14

BA0 BA1 BA2

CKE1

RAS*

WE*

CAS*

CS1* CS0*

ZQ1

DQ0 DQ1 DQ2 DQ3

DQS*

DM/TDQS

NF_TDQS*

NC

VSS

CK*

CKE0

DQS

CK

VSSQ

A8 A9

A5

A7

A15

NF_DQ6 NF_DQ7

NF_DQ5

NF_DQ4

A1

VREFDQ

VREFCA

VDD

VDDQ

ODT0 ODT1

RESET*

ZQ0

A0

A2 A3 A4

A6

A10/AP A11 A12/BC* A13

A14

BA0 BA1 BA2

CKE1

RAS*

WE*

CAS*

CS1* CS0*

ZQ1

DQ0 DQ1 DQ2 DQ3

DQS*

DM/TDQS

NF_TDQS*

NC

VSS

CK*

CKE0

DQS

CK

VSSQ

A8 A9

A5

A7

A15

NF_DQ6 NF_DQ7

NF_DQ5

NF_DQ4

A1

VREFDQ

VREFCA

VDD

VDDQ

ODT0 ODT1

RESET*

ZQ0

A0

A2 A3 A4

A6

A10/AP A11 A12/BC* A13

A14

BA0 BA1 BA2

CKE1

RAS*

WE*

CAS*

CS1* CS0*

ZQ1

DQ0 DQ1 DQ2 DQ3

DQS*

DM/TDQS

NF_TDQS*

NC

VSS

CK*

CKE0

DQS

CK

VSSQ

A8 A9

A5

A7

A15

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

NC

A14/A15 FOR 2G/4G MONO ONLY

NC

CS1 IS FOR 2G DDP RANK CONTROL

NC

201

1/20W

1%

MF

240

1/20W

1%

MF

240

201

1/20W

1%

MF

240

201

OMIT_TABLE

MT41K1G4

512MX8-4GBIT-DDR3-1600

FBGA-9P5X11P65-COMBO

MT41K1G4

512MX8-4GBIT-DDR3-1600

OMIT_TABLE

FBGA-9P5X11P65-COMBO

MT41K1G4

512MX8-4GBIT-DDR3-1600

OMIT_TABLE

FBGA-9P5X11P65-COMBO

MT41K1G4

512MX8-4GBIT-DDR3-1600

FBGA-9P5X11P65-COMBO

OMIT_TABLE

201

4V

CERM-X5R-1

0.47UF

20%

1/20W

1%

MF

240

201

20%

0.47UF

CERM-X5R-1

4V

201

4V

CERM-X5R-1

0.47UF

20%

201

4V

CERM-X5R-1

0.47UF

20%

201

4V

CERM-X5R-1

0.47UF

20%

201

4V

CERM-X5R-1

0.47UF

20%

201

4V

CERM-X5R-1

0.47UF

20%

201

4V

CERM-X5R-1

0.47UF

20%

201

4V

CERM-X5R-1

0.47UF

20%

201

20%

0.47UF

CERM-X5R-1

4V

201

4V

CERM-X5R-1

0.47UF

20%

201

20%

0.47UF

CERM-X5R-1

4V

201

MF

1%

1/20W

240

201

MF

1%

1/20W

240

201

MF

1%

1/20W

240

201

MF

1%

1/20W

240

201

DDR3 DRAM CHANNEL A (32-63)

SYNC_MASTER=K21_MLB

SYNC_DATE=07/28/2011

MEM_A_ZQ12

MEM_A_ZQ8

MEM_A_A<15>

MEM_A_A<7>

MEM_A_A<5>

MEM_A_A<9>

MEM_A_A<8>

MEM_A_CLK_P<0>

MEM_A_DQS_P<4>

MEM_A_CKE<0>

MEM_A_CLK_N<0>

MEM_A_DQS_N<4>

MEM_A_DQ<35>

MEM_A_DQ<34>

MEM_A_DQ<33>

MEM_A_DQ<39>

MEM_A_CS_L<0>

MEM_A_CS_L<1>

MEM_A_CAS_L

MEM_A_WE_L

MEM_A_RAS_L

MEM_A_CKE<1>

MEM_A_BA<2>

MEM_A_BA<1>

MEM_A_BA<0>

MEM_A_A<14>

MEM_A_A<13>

MEM_A_A<12>

MEM_A_A<11>

MEM_A_A<10>

MEM_A_A<6>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_A<2>

MEM_A_A<0>

MEM_RESET_L

MEM_A_ODT<1>

MEM_A_ODT<0>

=PP1V5_S3_MEM_A

PP0V75_S3_MEM_VREFCA_A

PP0V75_S3_MEM_VREFDQ_A

MEM_A_A<1>

MEM_A_DQ<36>

MEM_A_DQ<37>

MEM_A_DQ<32>

MEM_A_DQ<38>

MEM_A_ZQ15

MEM_A_ZQ11

MEM_A_ZQ14

MEM_A_ZQ10

MEM_A_ZQ13

MEM_A_ZQ9

MEM_A_A<14>

MEM_A_ZQ15

MEM_A_ZQ14

MEM_A_ZQ13

MEM_A_ZQ12

PP0V75_S3_MEM_VREFCA_A

=PP1V5_S3_MEM_A

PP0V75_S3_MEM_VREFDQ_A

=PP1V5_S3_MEM_A

PP0V75_S3_MEM_VREFDQ_A

PP0V75_S3_MEM_VREFCA_A

MEM_A_A<2>

MEM_A_CLK_P<0>

MEM_A_BA<2>

MEM_A_BA<1>

PP0V75_S3_MEM_VREFCA_A

=PP1V5_S3_MEM_A

PP0V75_S3_MEM_VREFDQ_A

MEM_A_ODT<1>

MEM_A_A<14>

MEM_A_BA<1>

MEM_A_DQ<47>

MEM_A_DQ<40>

MEM_A_DQ<45>

MEM_A_A<1>

MEM_A_ODT<0>

MEM_A_ODT<1>

MEM_RESET_L

MEM_A_A<0>

MEM_A_A<2>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_A<5>

MEM_A_A<6>

MEM_A_A<10>

MEM_A_A<11>

MEM_A_A<12>

MEM_A_A<13>

MEM_A_CKE<1>

MEM_A_RAS_L

MEM_A_WE_L

MEM_A_CAS_L

MEM_A_CS_L<1>

MEM_A_CS_L<0>

MEM_A_DQ<43>

MEM_A_DQ<44>

MEM_A_DQS_N<5>

MEM_A_CLK_N<0>

MEM_A_DQS_P<5>

MEM_A_A<8>

MEM_A_A<9>

MEM_A_A<7>

MEM_A_DQ<54>

MEM_A_DQ<49>

MEM_A_DQ<53>

MEM_A_DQ<52>

MEM_A_A<1>

MEM_A_ODT<0>

MEM_A_ODT<1>

MEM_RESET_L

MEM_A_A<0>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_A<5>

MEM_A_A<6>

MEM_A_A<10>

MEM_A_A<11>

MEM_A_A<12>

MEM_A_A<13>

MEM_A_A<14>

MEM_A_BA<0>

MEM_A_BA<1>

MEM_A_BA<2>

MEM_A_CKE<1>

MEM_A_RAS_L

MEM_A_WE_L

MEM_A_CAS_L

MEM_A_CS_L<1>

MEM_A_CS_L<0>

MEM_A_DQ<50>

MEM_A_DQ<51>

MEM_A_DQ<55>

MEM_A_DQ<48>

MEM_A_DQS_N<6>

MEM_A_CLK_N<0>

MEM_A_CKE<0>

MEM_A_DQS_P<6>

MEM_A_CLK_P<0>

MEM_A_A<8>

MEM_A_A<9>

MEM_A_A<7>

MEM_A_CKE<0>

MEM_A_BA<0>

MEM_A_A<15>

MEM_A_DQ<46>

MEM_A_DQ<42>

MEM_A_DQ<41>

MEM_A_DQ<62>

MEM_A_DQ<60>

MEM_A_DQ<61>

MEM_A_DQ<58>

MEM_A_A<1>

MEM_A_ODT<0>

MEM_RESET_L

MEM_A_A<0>

MEM_A_A<2>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_A<6>

MEM_A_A<10>

MEM_A_A<11>

MEM_A_A<12>

MEM_A_A<13>

MEM_A_BA<0>

MEM_A_BA<2>

MEM_A_CKE<1>

MEM_A_RAS_L

MEM_A_WE_L

MEM_A_CAS_L

MEM_A_CS_L<1>

MEM_A_CS_L<0>

MEM_A_DQ<59>

MEM_A_DQ<57>

MEM_A_DQ<63>

MEM_A_DQ<56>

MEM_A_DQS_N<7>

MEM_A_CLK_N<0>

MEM_A_CKE<0>

MEM_A_DQS_P<7>

MEM_A_CLK_P<0>

MEM_A_A<8>

MEM_A_A<9>

MEM_A_A<5>

MEM_A_A<7>

MEM_A_A<15>

R3030

12

R3020

12

R3010

12

R3000

12

U3010

K3 L7

H7 M7 K7 N3 N7 J7

L3 K2 L8 L2 M8 M2 N8 M3

J2 K8 J3

G3

F7 G7

G9 F9

H2

H1

B7

B3 C7 C2 C8

C3

D3

A3

79 80 81 82

E3 E8 D2 E7

A7

G1

F1

F3

N2

A2A9D7G2G8K1K9M1M9B9C1E2E9

J8

E1

A1

A8

N1

N9

B1D8F2F8J1J9L1

L9

B2B8C9D1D9

H3

H8 H9

U3020

K3 L7

H7 M7 K7 N3 N7 J7

L3 K2 L8 L2 M8 M2 N8 M3

J2 K8 J3

G3

F7 G7

G9 F9

H2

H1

B7

B3 C7 C2 C8

C3

D3

A3

79 80 81 82

E3 E8 D2 E7

A7

G1

F1

F3

N2

A2A9D7G2G8K1K9M1M9B9C1E2E9

J8

E1

A1

A8

N1

N9

B1D8F2F8J1J9L1

L9

B2B8C9D1D9

H3

H8 H9

U3030

K3 L7

H7 M7 K7 N3 N7 J7

L3 K2 L8 L2 M8 M2 N8 M3

J2 K8 J3

G3

F7 G7

G9 F9

H2

H1

B7

B3 C7 C2 C8

C3

D3

A3

79 80 81 82

E3 E8 D2 E7

A7

G1

F1

F3

N2

A2A9D7G2G8K1K9M1M9B9C1E2E9

J8

E1

A1

A8

N1

N9

B1D8F2F8J1J9L1

L9

B2B8C9D1D9

H3

H8 H9

U3000

K3 L7

H7 M7 K7 N3 N7 J7

L3 K2 L8 L2 M8 M2 N8 M3

J2 K8 J3

G3

F7 G7

G9 F9

H2

H1

B7

B3 C7 C2 C8

C3

D3

A3

79 80 81 82

E3 E8 D2 E7

A7

G1

F1

F3

N2

A2A9D7G2G8K1K9M1M9B9C1E2E9

J8

E1

A1

A8

N1

N9

B1D8F2F8J1J9L1

L9

B2B8C9D1D9

H3

H8 H9

C3000

1

2

C3001

1

2

C3002

1

2

C3010

1

2

C3011

1

2

C3012

1

2

C3020

1

2

C3021

1

2

C3022

1

2

C3030

1

2

C3031

1

2

C3032

1

2

R3001

12

R3011

12

R3021

12

R3031

12

051-9277

2.8.0

30 OF 109

28 OF 73

11 27 28 32 67

11 67

11 27 28 32 67

11 67

11 27 28 32 67

26 27 28 29 30

11 27 28 32 67

7

27 28 32

27 28 31 67

11 27 28 32 67

11 67

11 27 28 32 67

28

27 28 31 67

7

27 28 32

27 28 31 67

7

27 28 32

27 28 31 67

11 27 28 32 67

27 28 31 67

7

27 28 32

27 28 31 67

11 27 28 32 67

11 67

11 27 28 32 67

26 27 28 29 30

11 27 28 32 67

11 67

11 27 28 32 67

11 67

11 27 28 32 67

11 67

11 27 28 32 67

26 27 28 29 30

11 27 28 32 67

11 67

11 27 28 32 67

11 67

11 27 28 32 67

11 67

11 27 28 32 67

26 27 28 29 30

11 27 28 32 67

11 67

11 27 28 32 67

11 67

11 27 28 32 67

NF_DQ6 NF_DQ7

NF_DQ5

NF_DQ4

A1

VREFDQ

VREFCA

VDD

VDDQ

ODT0 ODT1

RESET*

ZQ0

A0

A2 A3 A4

A6

A10/AP A11 A12/BC* A13

A14

BA0 BA1 BA2

CKE1

RAS*

WE*

CAS*

CS1* CS0*

ZQ1

DQ0 DQ1 DQ2 DQ3

DQS*

DM/TDQS

NF_TDQS*

NC

VSS

CK*

CKE0

DQS

CK

VSSQ

A8 A9

A5

A7

A15

NF_DQ6 NF_DQ7

NF_DQ5

NF_DQ4

A1

VREFDQ

VREFCA

VDD

VDDQ

ODT0 ODT1

RESET*

ZQ0

A0

A2 A3 A4

A6

A10/AP A11 A12/BC* A13

A14

BA0 BA1 BA2

CKE1

RAS*

WE*

CAS*

CS1* CS0*

ZQ1

DQ0 DQ1 DQ2 DQ3

DQS*

DM/TDQS

NF_TDQS*

NC

VSS

CK*

CKE0

DQS

CK

VSSQ

A8 A9

A5

A7

A15

NF_DQ6 NF_DQ7

NF_DQ5

NF_DQ4

A1

VREFDQ

VREFCA

VDD

VDDQ

ODT0 ODT1

RESET*

ZQ0

A0

A2 A3 A4

A6

A10/AP A11 A12/BC* A13

A14

BA0 BA1 BA2

CKE1

RAS*

WE*

CAS*

CS1* CS0*

ZQ1

DQ0 DQ1 DQ2 DQ3

DQS*

DM/TDQS

NF_TDQS*

NC

VSS

CK*

CKE0

DQS

CK

VSSQ

A8 A9

A5

A7

A15

NF_DQ6 NF_DQ7

NF_DQ5

NF_DQ4

A1

VREFDQ

VREFCA

VDD

VDDQ

ODT0 ODT1

RESET*

ZQ0

A0

A2 A3 A4

A6

A10/AP A11 A12/BC* A13

A14

BA0 BA1 BA2

CKE1

RAS*

WE*

CAS*

CS1* CS0*

ZQ1

DQ0 DQ1 DQ2 DQ3

DQS*

DM/TDQS

NF_TDQS*

NC

VSS

CK*

CKE0

DQS

CK

VSSQ

A8 A9

A5

A7

A15

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

CS1 IS FOR 2G DDP RANK CONTROL

NC

NC NC

NC

NC NC

NC

A14/A15 FOR 2G/4G MONO ONLY

MF

1%

1/20W

240

201

1%

MF

240

1/20W

201

1%

MF

240

1/20W

201

1/20WMF1%

240

201

512MX8-4GBIT-DDR3-1600

OMIT_TABLE

FBGA-9P5X11P65-COMBO

MT41K1G4

FBGA-9P5X11P65-COMBO

MT41K1G4

OMIT_TABLE

512MX8-4GBIT-DDR3-1600

MT41K1G4

OMIT_TABLE

512MX8-4GBIT-DDR3-1600

FBGA-9P5X11P65-COMBO

MT41K1G4

512MX8-4GBIT-DDR3-1600

FBGA-9P5X11P65-COMBO

OMIT_TABLE

20%

0.47UF

CERM-X5R-1

4V

201

20%

0.47UF

CERM-X5R-1

4V

201

20%

0.47UF

CERM-X5R-1

4V

201

20%

0.47UF

CERM-X5R-1

4V

201

CERM-X5R-1

4V

20%

0.47UF

201 201

4V

CERM-X5R-1

0.47UF

20%

4V

CERM-X5R-1

0.47UF

20%

201

CERM-X5R-1

0.47UF

4V

20%

201

20%

0.47UF

CERM-X5R-1

4V

201

CERM-X5R-1

4V

20%

201

0.47UF

4V

20%

0.47UF

CERM-X5R-1

201

20%

0.47UF

4V

CERM-X5R-1

201

1/20WMF1%

201

240

1/20W

240

1%

201

MF

240

1%

1/20W

201

MF

240

MF

201

1/20W

1%

DDR3 DRAM CHANNEL B (0-31)

SYNC_DATE=07/28/2011

SYNC_MASTER=K21_MLB

MEM_B_ZQ7

MEM_B_ZQ3

MEM_B_ZQ6

MEM_B_ZQ2

MEM_B_ZQ5

MEM_B_ZQ1

MEM_B_ZQ4

MEM_B_ZQ0

MEM_B_DQ<7>

MEM_B_DQ<1>

MEM_B_CS_L<1>

MEM_B_ZQ6

MEM_B_ZQ5

MEM_B_ZQ7

MEM_B_ZQ4

MEM_B_DQS_N<0>

MEM_B_DQS_P<0>

PP0V75_S3_MEM_VREFCA_B

MEM_B_A<14>

MEM_B_A<10>

MEM_B_ODT<0>

=PP1V5_S3_MEM_B

PP0V75_S3_MEM_VREFDQ_B

PP0V75_S3_MEM_VREFCA_B

=PP1V5_S3_MEM_B

PP0V75_S3_MEM_VREFDQ_B

MEM_B_DQ<16>

MEM_B_DQ<18>

MEM_B_DQ<20>

MEM_B_DQ<22>

MEM_B_DQ<21>

MEM_B_DQ<23>

MEM_B_DQ<17>

MEM_B_DQ<19>

MEM_B_DQS_N<2>

MEM_B_A<9>

MEM_B_A<6>

MEM_B_A<5>

MEM_B_DQS_P<2>

MEM_B_A<10>

MEM_B_ODT<0>

MEM_B_ODT<1>

MEM_RESET_L

MEM_B_A<0>

MEM_B_A<1>

MEM_B_A<2>

MEM_B_A<3>

MEM_B_A<4>

MEM_B_A<10>

MEM_B_A<11>

MEM_B_A<12>

MEM_B_A<13>

MEM_B_A<14>

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_BA<2>

MEM_B_CKE<1>

MEM_B_RAS_L

MEM_B_WE_L

MEM_B_CAS_L

MEM_B_CS_L<1>

MEM_B_CS_L<0>

MEM_B_DQ<30>

MEM_B_DQ<28>

MEM_B_DQ<27>

MEM_B_DQ<25>

MEM_B_DQ<31>

MEM_B_DQ<24>

MEM_B_DQS_N<3>

MEM_B_CLK_N<0>

MEM_B_CKE<0>

MEM_B_DQS_P<3>

MEM_B_CLK_P<0>

MEM_B_A<8>

MEM_B_A<7>

MEM_B_ODT<0>

MEM_B_ODT<1>

MEM_B_A<0>

MEM_B_A<1>

MEM_B_A<2>

MEM_B_A<3>

MEM_B_A<4>

MEM_B_A<5>

MEM_B_A<6>

MEM_B_A<10>

MEM_B_A<11>

MEM_B_A<12>

MEM_B_A<13>

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_BA<2>

MEM_B_CKE<1>

MEM_B_RAS_L

MEM_B_WE_L

MEM_B_CAS_L

MEM_B_CS_L<1>

MEM_B_CS_L<0>

MEM_B_CLK_N<0>

MEM_B_CKE<0>

MEM_B_CLK_P<0>

MEM_B_A<8>

MEM_B_A<9>

MEM_B_A<7>

MEM_B_ODT<0>

MEM_B_ODT<1>

MEM_RESET_L

MEM_B_A<0>

MEM_B_A<1>

MEM_B_A<2>

MEM_B_A<3>

MEM_B_A<4>

MEM_B_A<5>

MEM_B_A<12>

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_BA<2>

MEM_B_CKE<1>

MEM_B_RAS_L

MEM_B_WE_L

MEM_B_CAS_L

MEM_B_CS_L<0>

MEM_B_DQ<9>

MEM_B_DQ<15>

MEM_B_DQ<13>

MEM_B_DQ<14>

MEM_B_DQ<12>

MEM_B_DQ<11>

MEM_B_DQ<8>

MEM_B_DQS_N<1>

MEM_B_CLK_N<0>

MEM_B_CKE<0>

MEM_B_DQS_P<1>

MEM_B_CLK_P<0>

MEM_B_A<8>

MEM_B_A<9>

MEM_B_ODT<1>

MEM_RESET_L

MEM_B_A<2>

MEM_B_A<5>

MEM_B_A<6>

MEM_B_A<12>

MEM_B_A<13>

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_BA<2>

MEM_B_RAS_L

MEM_B_WE_L

MEM_B_CAS_L

MEM_B_CS_L<1>

MEM_B_CS_L<0>

MEM_B_DQ<5>

MEM_B_DQ<3>

MEM_B_DQ<4>

MEM_B_DQ<6>

MEM_B_DQ<0>

MEM_B_CLK_N<0>

MEM_B_CKE<0>

MEM_B_CLK_P<0>

MEM_B_A<8>

MEM_B_A<7>

MEM_B_A<14>

MEM_B_A<3>

MEM_B_A<4>

MEM_B_A<14>

MEM_B_A<15>

MEM_B_A<15> MEM_B_A<15>

MEM_B_A<13>

MEM_B_A<15>

MEM_B_A<7>

MEM_B_A<6>

MEM_B_A<11>

MEM_B_A<9>

MEM_B_A<1>

MEM_B_A<0>

MEM_B_CKE<1>

MEM_B_DQ<2>

MEM_RESET_L

MEM_B_DQ<29>

MEM_B_DQ<26>

=PP1V5_S3_MEM_B

PP0V75_S3_MEM_VREFDQ_B

MEM_B_A<11>

PP0V75_S3_MEM_VREFCA_B

=PP1V5_S3_MEM_B

PP0V75_S3_MEM_VREFCA_B

MEM_B_DQ<10>

R3130

12

R3120

12

R3110

12

R3100

12

U3100

K3 L7

H7 M7 K7 N3 N7 J7

L3 K2 L8 L2 M8 M2 N8 M3

J2 K8 J3

G3

F7 G7

G9 F9

H2

H1

B7

B3 C7 C2 C8

C3

D3

A3

79 80 81 82

E3 E8 D2 E7

A7

G1

F1

F3

N2

A2A9D7G2G8K1K9M1M9B9C1E2E9

J8

E1

A1

A8

N1

N9

B1D8F2F8J1J9L1

L9

B2B8C9D1D9

H3

H8 H9

U3110

K3 L7

H7 M7 K7 N3 N7 J7

L3 K2 L8 L2 M8 M2 N8 M3

J2 K8 J3

G3

F7 G7

G9 F9

H2

H1

B7

B3 C7 C2 C8

C3

D3

A3

79 80 81 82

E3 E8 D2 E7

A7

G1

F1

F3

N2

A2A9D7G2G8K1K9M1M9B9C1E2E9

J8

E1

A1

A8

N1

N9

B1D8F2F8J1J9L1

L9

B2B8C9D1D9

H3

H8 H9

U3120

K3 L7

H7 M7 K7 N3 N7 J7

L3 K2 L8 L2 M8 M2 N8 M3

J2 K8 J3

G3

F7 G7

G9 F9

H2

H1

B7

B3 C7 C2 C8

C3

D3

A3

79 80 81 82

E3 E8 D2 E7

A7

G1

F1

F3

N2

A2A9D7G2G8K1K9M1M9B9C1E2E9

J8

E1

A1

A8

N1

N9

B1D8F2F8J1J9L1

L9

B2B8C9D1D9

H3

H8 H9

U3130

K3 L7

H7 M7 K7 N3 N7 J7

L3 K2 L8 L2 M8 M2 N8 M3

J2 K8 J3

G3

F7 G7

G9 F9

H2

H1

B7

B3 C7 C2 C8

C3

D3

A3

79 80 81 82

E3 E8 D2 E7

A7

G1

F1

F3

N2

A2A9D7G2G8K1K9M1M9B9C1E2E9

J8

E1

A1

A8

N1

N9

B1D8F2F8J1J9L1

L9

B2B8C9D1D9

H3

H8 H9

C3100

1

2

C3101

1

2

C3102

1

2

C3110

1

2

C3111

1

2

C3112

1

2

C3120

1

2

C3121

1

2

C3122

1

2

C3130

1

2

C3131

1

2

C3132

1

2

R3101

12

R3111

12

R3121

12

R3131

12

051-9277

2.8.0

31 OF 109

29 OF 73

11 67

11 29 30 32 67

29

11 67

29 30 31

11 29 30 32 67

7

29 30 32

29 30 31

7

29 30 32

29 30 31

11 67

11 29 30 32 67

11 67 11 29 30 32 67

11 29 30 32 67

26 27 28 29 30

11 29 30 32 67

11 67

11 29 30 32 67

11 67

11 29 30 32 67

26 27 28 29 30

11 29 30 32 67

11 67

11 29 30 32 67

11 67

11 29 30 32 67

26 27 28 29 30

11 29 30 32 67

11 67

11 29 30 32 67

11 29 30 32 67 11 29 30 32 67

11 29 30 32 67

11 67

26 27 28 29 30

11 67

7

29 30 32

29 30 31

11 29 30 32 67

29 30 31

7

29 30 32

29 30 31

11 67

NF_DQ6 NF_DQ7

NF_DQ5

NF_DQ4

A1

VREFDQ

VREFCA

VDD

VDDQ

ODT0 ODT1

RESET*

ZQ0

A0

A2 A3 A4

A6

A10/AP A11 A12/BC* A13

A14

BA0 BA1 BA2

CKE1

RAS*

WE*

CAS*

CS1* CS0*

ZQ1

DQ0 DQ1 DQ2 DQ3

DQS*

DM/TDQS

NF_TDQS*

NC

VSS

CK*

CKE0

DQS

CK

VSSQ

A8 A9

A5

A7

A15

NF_DQ6 NF_DQ7

NF_DQ5

NF_DQ4

A1

VREFDQ

VREFCA

VDD

VDDQ

ODT0 ODT1

RESET*

ZQ0

A0

A2 A3 A4

A6

A10/AP A11 A12/BC* A13

A14

BA0 BA1 BA2

CKE1

RAS*

WE*

CAS*

CS1* CS0*

ZQ1

DQ0 DQ1 DQ2 DQ3

DQS*

DM/TDQS

NF_TDQS*

NC

VSS

CK*

CKE0

DQS

CK

VSSQ

A8 A9

A5

A7

A15

NF_DQ6 NF_DQ7

NF_DQ5

NF_DQ4

A1

VREFDQ

VREFCA

VDD

VDDQ

ODT0 ODT1

RESET*

ZQ0

A0

A2 A3 A4

A6

A10/AP A11 A12/BC* A13

A14

BA0 BA1 BA2

CKE1

RAS*

WE*

CAS*

CS1* CS0*

ZQ1

DQ0 DQ1 DQ2 DQ3

DQS*

DM/TDQS

NF_TDQS*

NC

VSS

CK*

CKE0

DQS

CK

VSSQ

A8 A9

A5

A7

A15

NF_DQ6 NF_DQ7

NF_DQ5

NF_DQ4

A1

VREFDQ

VREFCA

VDD

VDDQ

ODT0 ODT1

RESET*

ZQ0

A0

A2 A3 A4

A6

A10/AP A11 A12/BC* A13

A14

BA0 BA1 BA2

CKE1

RAS*

WE*

CAS*

CS1* CS0*

ZQ1

DQ0 DQ1 DQ2 DQ3

DQS*

DM/TDQS

NF_TDQS*

NC

VSS

CK*

CKE0

DQS

CK

VSSQ

A8 A9

A5

A7

A15

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

CS1 IS FOR 2G DDP RANK CONTROL

NC

NC NC

NC

NC NC

NC

A14/A15 FOR 2G/4G MONO ONLY

MF

1%

201

240

1/20W

201

240

1/20W

1%

MF

201

1/20W

1%

MF

240

OMIT_TABLE

MT41K1G4

FBGA-9P5X11P65-COMBO

512MX8-4GBIT-DDR3-1600

FBGA-9P5X11P65-COMBO

MT41K1G4

OMIT_TABLE

512MX8-4GBIT-DDR3-1600

MT41K1G4

FBGA-9P5X11P65-COMBO

OMIT_TABLE

MT41K1G4

512MX8-4GBIT-DDR3-1600

FBGA-9P5X11P65-COMBO

201

CERM-X5R-1

4V

0.47UF

20%

240

1%MF1/20W

201

4V

CERM-X5R-1

0.47UF

20%

0.47UF

201

20%

CERM-X5R-1

4V

201

0.47UF

20%

CERM-X5R-1

4V

201

0.47UF

20%

CERM-X5R-1

4V

0.47UF

CERM-X5R-1

201

4V

20%

CERM-X5R-1

201

0.47UF

4V

20%

201

0.47UF

4V

CERM-X5R-1

20%

CERM-X5R-1

201

20%

0.47UF

4V

201

20%

0.47UF

CERM-X5R-1

4V

201

20%

4V

CERM-X5R-1

0.47UF

201

20%

0.47UF

CERM-X5R-1

4V

MF

201

1/20W

240

1%

240

201

1%MF1/20W

201

1%MF1/20W

240

201

1/20W

240

MF

1%

SYNC_MASTER=K21_MLB

SYNC_DATE=07/28/2011

DDR3 DRAM CHANNEL B (32-63)

MEM_B_CLK_N<0>

MEM_B_DQ<39>

=PP1V5_S3_MEM_B

MEM_B_DQ<55>

PP0V75_S3_MEM_VREFCA_B

MEM_B_DQ<41>

PP0V75_S3_MEM_VREFCA_B

PP0V75_S3_MEM_VREFDQ_B

MEM_B_ZQ15

MEM_B_ZQ11

MEM_B_ZQ13

MEM_B_ZQ9

MEM_B_ZQ12

MEM_B_ZQ8

MEM_B_ZQ15

MEM_B_ZQ14

MEM_RESET_L

MEM_B_ODT<1>

MEM_B_DQS_P<4>

MEM_B_DQS_N<4>

MEM_B_ZQ13

MEM_B_ZQ12

MEM_RESET_L

MEM_B_ODT<0>

MEM_B_ODT<1>

MEM_B_A<9>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_A<1>

MEM_B_A<4>

MEM_B_A<7>

MEM_B_A<10>

MEM_B_A<9>

MEM_B_A<8>

MEM_B_CLK_P<0>

MEM_B_CKE<0>

MEM_B_DQ<32>

MEM_B_DQ<34>

MEM_B_DQ<37>

MEM_B_DQ<38>

MEM_B_DQ<33>

MEM_B_DQ<36>

MEM_B_DQ<35>

MEM_B_CS_L<0>

MEM_B_CS_L<1>

MEM_B_CAS_L

MEM_B_WE_L

MEM_B_RAS_L

MEM_B_CKE<1>

MEM_B_BA<2>

MEM_B_BA<1>

MEM_B_BA<0>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_A<11>

MEM_B_A<6>

MEM_B_A<5>

MEM_B_A<3>

MEM_B_A<2>

MEM_B_A<0>

MEM_B_ODT<0>

MEM_B_A<7>

MEM_B_A<9>

MEM_B_DQS_P<7>

MEM_B_DQS_N<7>

MEM_B_DQ<56>

MEM_B_DQ<62>

MEM_B_DQ<61>

MEM_B_DQ<59>

MEM_B_DQ<60>

MEM_B_DQ<58>

MEM_B_DQ<57>

MEM_B_DQ<63>

MEM_B_CS_L<0>

MEM_B_CS_L<1>

MEM_B_CAS_L

MEM_B_WE_L

MEM_B_RAS_L

MEM_B_CKE<1>

MEM_B_BA<2>

MEM_B_BA<1>

MEM_B_BA<0>

MEM_B_A<14>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_A<11>

MEM_B_A<10>

MEM_B_A<6>

MEM_B_A<5>

MEM_B_A<4>

MEM_B_A<2>

MEM_B_A<1>

MEM_B_A<0>

MEM_RESET_L

MEM_B_ODT<1>

MEM_B_ODT<0>

MEM_B_A<7>

MEM_B_A<5>

MEM_B_A<8>

MEM_B_CLK_P<0>

MEM_B_DQS_P<5>

MEM_B_CKE<0>

MEM_B_CLK_N<0>

MEM_B_DQS_N<5>

MEM_B_DQ<46>

MEM_B_DQ<42>

MEM_B_CS_L<0>

MEM_B_CS_L<1>

MEM_B_CAS_L

MEM_B_WE_L

MEM_B_RAS_L

MEM_B_CKE<1>

MEM_B_BA<2>

MEM_B_BA<1>

MEM_B_BA<0>

MEM_B_A<14>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_A<11>

MEM_B_A<10>

MEM_B_A<6>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_A<2>

MEM_B_A<0>

MEM_B_A<1>

MEM_B_DQ<47>

MEM_B_DQ<45>

MEM_B_DQ<40>

MEM_B_DQ<43>

MEM_B_A<14>

MEM_B_A<15>

MEM_B_CKE<0>

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

=PP1V5_S3_MEM_B

MEM_B_DQ<54>

MEM_B_DQ<52>

MEM_B_DQ<49>

MEM_B_DQ<50>

MEM_B_A<1>

PP0V75_S3_MEM_VREFDQ_B

PP0V75_S3_MEM_VREFCA_B

MEM_B_ODT<0>

MEM_B_ODT<1>

MEM_RESET_L

MEM_B_A<0>

MEM_B_A<2>

MEM_B_A<3>

MEM_B_A<4>

MEM_B_A<6>

MEM_B_A<10>

MEM_B_A<11>

MEM_B_A<12>

MEM_B_A<13>

MEM_B_A<14>

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_BA<2>

MEM_B_CKE<1>

MEM_B_RAS_L

MEM_B_WE_L

MEM_B_CAS_L

MEM_B_CS_L<1>

MEM_B_CS_L<0>

MEM_B_DQ<53>

MEM_B_DQ<51>

MEM_B_DQ<48>

MEM_B_DQS_N<6>

MEM_B_CLK_N<0>

MEM_B_CKE<0>

MEM_B_DQS_P<6>

MEM_B_CLK_P<0>

MEM_B_A<8>

MEM_B_A<9>

MEM_B_A<5>

MEM_B_A<7>

MEM_B_A<15>

MEM_B_ZQ10

MEM_B_ZQ14

=PP1V5_S3_MEM_B

PP0V75_S3_MEM_VREFDQ_B

MEM_B_DQ<44>

MEM_B_A<3>

MEM_B_A<8>

=PP1V5_S3_MEM_B

PP0V75_S3_MEM_VREFCA_B

R3230

12

R3220

12

R3210

12

R3200

12

U3230

K3 L7

H7 M7 K7 N3 N7 J7

L3 K2 L8 L2 M8 M2 N8 M3

J2 K8 J3

G3

F7 G7

G9 F9

H2

H1

B7

B3 C7 C2 C8

C3

D3

A3

79 80 81 82

E3 E8 D2 E7

A7

G1

F1

F3

N2

A2A9D7G2G8K1K9M1M9B9C1E2E9

J8

E1

A1

A8

N1

N9

B1D8F2F8J1J9L1

L9

B2B8C9D1D9

H3

H8 H9

U3200

K3 L7

H7 M7 K7 N3 N7 J7

L3 K2 L8 L2 M8 M2 N8 M3

J2 K8 J3

G3

F7 G7

G9 F9

H2

H1

B7

B3 C7 C2 C8

C3

D3

A3

79 80 81 82

E3 E8 D2 E7

A7

G1

F1

F3

N2

A2A9D7G2G8K1K9M1M9B9C1E2E9

J8

E1

A1

A8

N1

N9

B1D8F2F8J1J9L1

L9

B2B8C9D1D9

H3

H8 H9

U3210

K3 L7

H7 M7 K7 N3 N7 J7

L3 K2 L8 L2 M8 M2 N8 M3

J2 K8 J3

G3

F7 G7

G9 F9

H2

H1

B7

B3 C7 C2 C8

C3

D3

A3

79 80 81 82

E3 E8 D2 E7

A7

G1

F1

F3

N2

A2A9D7G2G8K1K9M1M9B9C1E2E9

J8

E1

A1

A8

N1

N9

B1D8F2F8J1J9L1

L9

B2B8C9D1D9

H3

H8 H9

U3220

K3 L7

H7 M7 K7 N3 N7 J7

L3 K2 L8 L2 M8 M2 N8 M3

J2 K8 J3

G3

F7 G7

G9 F9

H2

H1

B7

B3 C7 C2 C8

C3

D3

A3

79 80 81 82

E3 E8 D2 E7

A7

G1

F1

F3

N2

A2A9D7G2G8K1K9M1M9B9C1E2E9

J8

E1

A1

A8

N1

N9

B1D8F2F8J1J9L1

L9

B2B8C9D1D9

H3

H8 H9

C3200

1

2

C3201

1

2

C3202

1

2

C3210

1

2

C3211

1

2

C3212

1

2

C3220

1

2

C3221

1

2

C3222

1

2

C3230

1

2

C3231

1

2

C3232

1

2

R3201

12

R3211

12

R3221

12

R3231

12

051-9277

2.8.0

32 OF 109

30 OF 73

11 29 30 32 67

11 67

7

29 30 32

11 67

29 30 31

11 67

29 30 31

30

26 27 28 29 30

11 29 30 32 67

11 67

30

26 27 28 29 30

11 29 30 32 67

29 30 31

11 29 30 32 67

11 67

11 29 30 32 67

11 29 30 32 67 11 67

11 67

11 29 30 32 67

26 27 28 29 30

11 29 30 32 67

11 67

11 29 30 32 67

11 67

11 29 30 32 67

11 67

11 29 30 32 67

7

29 30 32

11 67

11 29 30 32 67

29 30 31

11 29 30 32 67

26 27 28 29 30

11 29 30 32 67

11 67

11 29 30 32 67

11 67

11 29 30 32 67

7

29 30 32

29 30 31

11 67

11 29 30 32 67

7

29 30 32

29 30 31

OUT

V-

V+

V-

V+

V-

V+

IN

NC

D

SG

D

SG

V-

V+

NC

RESET*

A0 A1 A2

SCL SDA

P0 P1 P2

P5 P6 P7

P3 P4

THRM

VCC

GND

PAD

NC

IN

BI

VDD

VOUTD

VOUTC

VOUTB

VOUTA

SCL

SDA

A0

A1

GND

IN

BI

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

NOTE: MEMVREG and FRAMEBUF share

NOTE: CPU DAC output step sizes:

DDR3L (1.35V) 6.99mV per step

DDR3 (1.5V) 7.70mV per step

RST* on ’platform reset’ so that system

watchdog will disable margining.

NOTE: Margining will be disabled across all

Addr=0x30(WR)/0x31(RD)

Addr=0x98(WR)/0x99(RD)

both at the same time!

8.59mV / step @ output

+61uA - -61uA (- = sourced)

1.5V (DAC: 0x3A)

7.69mV / step @ output

1.267V (DAC: 0x8B)

MEM VREG

PCA9557D Pin:

0.000V - 3.300V (0x00 - 0xFF)

Nominal value

DAC range:

VRef current:

DAC Channel:

MEM A VREF DQ

1

AB

234

C

5

D

0.000V - 3.000V (0x00 - 0x74)

1.056V - 1.442V (+/- 180mV)

+6.0mA - -5.0mA (- = sourced)

1.51mV / step @ output

6

D

- =I2C_PCA9557D_SCL

VREFDQ:LDO_DAC - Margined LDO outputs sent to DQ inputs.

(OD)

Page Notes

a DAC output, cannot enable

MEM B VREF DQ

Margined target:

10mA max load

1.000V - 2.000V (+/- 500mV)

GPU Frame Buffer (1.8V, 70% VRef)

VREFCA:LDO_DAC - DAC margined LDO outputs sent to CA inputs.

DAC step size:

soft-resets and sleep/wake cycles.

VREFDQ:M1_M3 - CPU margined DDR voltage divider sent to DQ inputs.

Signal aliases required by this page:

MEM B VREF CA

0.300V - 1.200V (+/- 450mV)

0.000V - 1.501V (0x00 - 0x74)

+3.4mA - -3.4mA (- = sourced)

VREFCA:LDO - LDO outputs sent to CA inputs.

VREFDQ:M1_DAC - DAC margined DDR voltage divider sent to DQ inputs.

- =I2C_VREFDACS_SDA

- =I2C_VREFDACS_SCL

- =PPDDR_S3_MEMVREF

- =PPVTT_S3_DDR_BUF

- =PP3V3_S3_VREFMRGN

Power aliases required by this page:

- =I2C_PCA9557D_SDA

BOM options provided by this page:

VREFDQ:LDO - LDO outputs sent to DQ inputs.

DDRVREF_DAC - Stuffs Apple margining circuit.

MEM A VREF CA

C

0.75V (DAC: 0x3A)

Required zero ohm resistors when no VREF margining circuit stuffed

NOTE: Must not enable more than two SO-DIMM margining

buffers at once or VRef source may be overloaded.

56

0.1UF

6.3V X5R 201

10%

DDRVREF_DAC

1%

33.2K

1/20W

MF

201

PLACE_NEAR=R7315.2:1mm

DDRVREF_DAC

100K

5%

1/20W

MF

201

DDRVREF_DAC

UCSP

MAX4253

DDRVREF_DAC

MAX4253

UCSP

DDRVREF_DAC

MAX4253

UCSP

DDRVREF_DAC

1/20W

MF

201

1%

PLACE_NEAR=U2900.J8:2.54mm

200

VREFCA:LDO_DAC

SHORT

NONE

402

NONE

OMIT

NONE

OMIT

SHORT

402

NONE

25

200

1/20W

PLACE_NEAR=U2900.E1:2.54mm

201

MF

1%

VREFDQ:LDO_DAC

201

MF

133

1%

VREFDQ:LDO_DAC

PLACE_NEAR=R3303.2:1mm

1/20W

201

1/20W

DDRVREF_DAC

100K

5%

MF

1K

1% 1/20W

201

MF

VREFDQ:M1_M3

PLACE_NEAR=Q3320.6:1mm

0201

16V

10%

0.1UF

VREFDQ:M1_M3

PLACE_NEAR=Q3320.6:2mm

X5R-CERM

201

MF

1/20W

1K

1%

VREFDQ:M1_M3

PLACE_NEAR=R3321.2:1mm

CRITICAL

VREFDQ:M1_M3

SSM6N15AFE

SOT563

SSM6N15AFE

SOT563

CRITICAL

VREFDQ:M1_M3

MF

1%

201

VREFDQ:M1_M3

PLACE_NEAR=Q3320.3:2mm

1K

1/20W

X5R-CERM

16V

10%

0.1UF

VREFDQ:M1_M3

0201

PLACE_NEAR=Q3320.3:2mm

MF

1/20W

VREFDQ:M1_M3

1K

1%

PLACE_NEAR=R3311.2:1mm

201

VREFDQ:LDO_DAC

PLACE_NEAR=Q3310.3:1mm

5% 1/20W MF 201

0

DDRVREF_DAC

MAX4253

UCSP

1%

201

MF

1/20W

200

PLACE_NEAR=U3100.J8:2.54mm

VREFCA:LDO_DAC

201

MF

1/20W

1%

133

VREFCA:LDO_DAC

PLACE_NEAR=R3305.2:1mm

MF

1/20W

100K

5%

201

DDRVREF_DAC

0

NOSTUFF

5% 1/20W MF 201

PLACE_NEAR=R3309:1mm

5%

100K

1/20W

MF

201

DDRVREF_DAC

1%

1/20W

201

133

MF

PLACE_NEAR=R3309.2:1mm

VREFCA:LDO_DAC

CRITICAL

QFN

PCA9557

DDRVREF_DAC

44

DAC5574

MSOP

DDRVREF_DAC

CRITICAL

44

16V X5R-CERM 0201

10%

0.1UF

DDRVREF_DAC

6.3V

20%

402-LF

CERM

2.2UF

DDRVREF_DAC

0.1UF

X5R-CERM

0201

10% 16V

0.1UF

10% 16V

X5R-CERM

0201

DDRVREF_DAC

SYNC_MASTER=J11_MLB

SYNC_DATE=08/04/2011

FSB/DDR3/FRAMEBUF Vref Margining

RES,MF,332OHM,1,1/20W,0201

118S0303

R3304

1

VREFDQ:M1_DAC

RES,MF,1KOHM,1,1/20W,0201

118S0012

4

R3321,R3322,R3311,R3312

VREFCA:LDO

R3309,R3305

2

RES,MF,1/20W,0.0 OHM,5,0201,SMD

117S0002

1

117S0002

VREFDQ:LDO

RES,MF,1/20W,0.0 OHM,5,0201,SMD

R3303,R3360

VREFMRGN_CA_SODIMMA_EN

VREFMRGN_CA_SODIMMB_EN

VREFMRGN_MEMVREG_EN

VREFMRGN_MEMVREG_FBVREF

VREFMRGN_SODIMMS_CA

VREFMRGN_DQ_SODIMMA_EN

=PP3V3_S3_VREFMRGN

VREFMRGN_CA_SODIMMA_BUF

VREFMRGN_CA_SODIMMB_BUF

VREFMRGN_SODIMMA_DQ

VOLTAGE=3.3V

PP3V3_S3_VREFMRGN_DAC

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

VREFMRGN_MEMVREG_BUF

PP0V75_S3_MEM_VREFDQ_A

PCA9557D_RESET_L

PP3V3_S3_VREFMRGN_CTRL

MIN_LINE_WIDTH=0.3 mm

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

PP0V75_S3_MEM_VREFCA_A

VOLTAGE=0.75V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

VREFMRGN_DQ_SODIMMA_BUF

=PPVTT_S3_DDR_BUF

PP0V75_S3_MEM_VREFCA_B

VOLTAGE=0.75V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

=I2C_PCA9557D_SDA

MEMRESET_ISOL_LS5V_L

PP0V75_S3_MEM_VREFDQ_B

PPCPU_MEM_VREFDQ_B

MEMRESET_ISOL_LS5V_L

PPCPU_MEM_VREFDQ_A

=I2C_PCA9557D_SCL

=I2C_VREFDACS_SCL

=I2C_VREFDACS_SDA

PP0V75_S3_MEM_VREFDQ_B

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V

DDRREG_FB

=PPDDR_S3_MEMVREF

PP0V75_S3_MEM_VREFDQ_A

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V

U3301

3

4

5

8

6

7

9

10

11

12

13

14

15

1

2

17

16

C3303

1

2

C3302

1

2

R3301

12

R3310

12

U3300

9

10

3

6

7

8

1

2

4

5

C3301

1

2

C3300

1

2

C3305

1

2

R3314

12

R3313

1

2

U3302

C3

C2

C1

C4

B1

B4

U3302

A3

A2

A1

A4

B1

B4

U3304

C3

C2

C1

C4

B1

B4

R3309

12

R3318

12

R3319

12

R3303

12

R3304

12

R3307

1

2

R3321

1

2

C3320

1

2

R3322

1

2

Q3320

6

2

1

Q3320

3

5

4

R3311

1

2

C3310

1

2

R3312

1

2

R3360

1

2

U3304

A3

A2

A1

A4

B1

B4

R3305

12

R3306

12

R3315

1

2

R3361

1

2

051-9277

2.8.0

33 OF 109

31 OF 73

7

27 28 31 67

27 28 67

7

56

29 30

26 31

29 30 31

9

26 31

9

29 30 31

7

31

7

31

27 28 31 67

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

COLUMN OF THREE CAPS BETWEEN PACKAGES

2 CAPS ALONG PACKAGE EDGE

COLUMN OF THREE CAPS BETWEEN PACKAGES

2 CAPS ALONG PACKAGE EDGE

COLUMN OF THREE CAPS BETWEEN PACKAGES

2 CAPS ALONG PACKAGE EDGE

Place RC end termination after last DRAM

MEM CLOCK TERMINATION

Place Source Cterm at neckdown at first DRAM

JEDEC recommends 30 Ohm term to VTT for CS,CKE,ODT and 36 Ohm for BA,A,RAS,CAS,WE

MEM_B_RAS_L

MEM_A_A<8>

MEM_A_A<14>

MEM_A_A<13>

MEM_A_A<6>

MEM_A_A<11>

MEM_A_BA<2>

MEM_A_A<9>

MEM_A_A<15>

MEM_A_A<7>

MEM_A_BA<0>

MEM_A_A<1>

MEM_A_CS_L<1>

MEM_A_A<2>

MEM_A_CS_L<0>

MEM_A_A<12>

MEM_A_ODT<1>

MEM_A_CKE<0>

=PP0V75_S0_MEM_VTT_B

MEM_B_BA<0>

=PP1V5_S3_MEM_B

MEM_B_A<1>

MEM_B_A<3> MEM_B_ODT<0>

MEM_B_A<6> MEM_B_A<12>

MEM_B_A<15>

MEM_B_CS_L<1>

=PP1V5_S3_MEM_A

MEM_B_A<8>

=PP1V5_S3_MEM_B

MEM_B_A<10>

MEM_B_CKE<0>

=PP1V5_S3_MEM_A

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

VOLTAGE=0V

MEM_B_CLK_TERM_R

VOLTAGE=0V

MEM_B_CS_L<0> MEM_B_A<13>

MEM_B_A<7>

MEM_B_CKE<1>

MEM_B_A<9> MEM_B_CAS_L

MEM_B_A<0>

MEM_B_BA<1> MEM_B_A<14>

MEM_B_A<4>

MEM_B_A<2>

MEM_B_A<5>

MEM_B_ODT<1>

MEM_B_A<11>

MEM_B_WE_L

MEM_B_BA<2>

=PP0V75_S0_MEM_VTT_A

MEM_A_A<5>

MEM_A_CAS_L

MEM_A_BA<1>

MEM_A_CKE<1>

MEM_A_RAS_L MEM_A_A<0> MEM_A_A<3>

MEM_A_ODT<0>

MEM_A_WE_L MEM_A_A<10> MEM_A_A<4>

DDR3 Bypassing/Termination

SYNC_MASTER=K21_MLB

SYNC_DATE=07/28/2011

20%

0.47UF

201

4V CERM-X5R-1

20%

0.47UF

201

4V CERM-X5R-1

36

5%

1/32W

4X0201

36

5%

4X0201

1/32W

4X0201

5%

1/32W

36

6.3V

2.2UF

402-LF

CERM

20%

4X0201

1/32W

5%

36 36

4X0201

1/32W

5%

20%

0.47UF

201

CERM-X5R-1

4V

20%

201

4V

0.47UF

CERM-X5R-1

6.3V

20%

402-LF

CERM

2.2UF

402-LF

6.3V

20%

CERM

6.3V

2.2UF

20%

402-LF

CERM 402-LF

20%

2.2UF

6.3V

CERM 402-LF

20%

6.3V

2.2UF

CERM 402-LF

20%

2.2UF

6.3V

2.2UF

20%

402-LF

CERM

6.3V

2.2UF

402-LF

20%

CERM

20%

6.3V

2.2UF

402-LF

6.3V

20%

CERM

2.2UF

6.3V

2.2UF

20%

402-LF

CERM

6.3V

20%

402-LF

2.2UF

6.3V

20%

402-LF

CERM

2.2UF

CERM 402-LF

20%

6.3V

CERM 402-LF

20%

2.2UF

6.3V

2.2UF

20%

402-LF

CERM

20%

2.2UF

6.3V

402-LF

CERM 402-LF

20%

2.2UF

6.3V

CERM 402-LF

20%

2.2UF

6.3V

CERM 402-LF

20%

2.2UF

6.3V

2.2UF

20%

CERM 402-LF

6.3V

2.2UF

20%

402-LF

CERM

2.2UF

6.3V CERM 402-LF

20%

CERM

20%

2.2UF

6.3V

402-LF

CERM 402-LF

20%

6.3V

2.2UF

20%

6.3V CERM

2.2UF

402-LF

6.3V

20%

CERM

2.2UF

402-LF

20%

CERM 402-LF

6.3V

2.2UF

20%

6.3V CERM 402-LF

2.2UF

20%

2.2UF

6.3V CERM 402-LF

2.2UF

20%

6.3V CERM 402-LF

2.2UF

402-LF

6.3V

20%

CERM

CERM 402-LF

20%

2.2UF

6.3V

20%

6.3V

402-LF

CERM

2.2UF

6.3V

2.2UF

20%

402-LF

CERM

1/32W

5%

36

4X0201

67 28 27 11

402-LF

CERM

6.3V

2.2UF

20%

67 28 27 11

4X0201

36

1/32W

5%

4X0201

5%361/32W

36

1/32W

5%

4X0201

36

1/32W

5%

4X0201

1/32W

5%

36

402-LF

2.2UF

20%

6.3V CERM

4X0201

5%

1/32W

36

1/32W

5%

4X0201

5%

1/32W

36

4X0201

5%

1/32W

36

5%

1/32W

4X0201

1/32W

5%

36

5%

1/32W

36

4X0201

5%

1/32W

4X0201

36

4X0201

36

1/32W

5%

67 28 27 11

CERM

6.3V

2.2UF

20%

402-LF

67 28 27 11

36

5%

1/32W

4X0201

5%361/32W

5%

1/32W

36

4X0201

36

4X0201

1/32W

5%

4X0201

5%

1/32W

36

4X0201

36

5%

1/32W

402-LF

CERM

20%

2.2UF

6.3V 4X0201

36

1/32W

5%

4X0201

36

1/32W

5%

1/32W

4X0201

36

5%

1/32W

4X0201

36

4X0201

5%

1/32W

36

4X0201

1/32W

5%

4X0201

36

5%

1/32W

20% 4V

201

CERM-X5R-1

0.47UF

67 30 29 11

6.3V

2.2UF

20%

402-LF

CERM

67 30 29 11

0.47UF

CERM-X5R-1

20% 4V

201

6.3V

2.2UF

20%

402-LF

CERM

1/32W

4X0201

5%

36

4X0201

5%

1/32W

36

5%

1/32W

36

4X0201

36

1/32W

5%

4X0201

67 30 29 11

5%

36

4X0201

1/32W

67 30 29 11

20%

2.2UF

6.3V

402-LF

CERM

6.3V

20%

CERM 402-LF

2.2UF

402-LF

20%

6.3V CERM

2.2UF

20%

6.3V CERM 402-LF

CERM

6.3V

20%

2.2UF

402-LF

6.3V

20%

2.2UF

402-LF

CERM

6.3V

20%

2.2UF

402-LF

2.2UF

6.3V

402-LF

20%

CERM

36

5%

1/32W

4X0201

CERM

6.3V

2.2UF

20%

402-LF

4X0201

36

5%

1/32W

36

5%

4X0201

1/32W

5%

36

4X0201

1/32W

5%

36

4X0201

1/32W

1/32W365%

4X0201

5%

4X0201

1/32W

36

2.2UF

CERM 402-LF

20%

6.3V

36

5%

4X0201

1/32W

5%361/32W

4X0201

36

5%

1/32W

4X0201

1/32W365%

20%

2.2UF

6.3V

402-LF

CERM

CERM 402-LF

6.3V

20%

2.2UF

6.3V

2.2UF

20%

402-LF

CERM

6.3V

2.2UF

20%

402-LF

CERM

30

201

1/20W

MF

5%

201

CERM

25V

5%

3.3PF

30

201

5%

1/20W

MF

1/20W

5%

30

201

CERM

25V

5%

3.3PF

201

30

5%

1/20W

MF

0.1UF

201

10% X5R

6.3V

0.1UF

MEM_A_CLK_TERM_R

10% X5R

6.3V

201

2.2UF

20%

402-LF

CERM

6.3V

2.2UF

20%

CERM

6.3V

402-LF

20%

2.2UF

402-LF

CERM

6.3V

4V CERM-X5R-1 201

0.47UF

20%

2.2UF

6.3V

20%

402-LF

CERM

CERM-X5R-1

20% 4V

201

0.47UF

201

20%

CERM-X5R-1

4V

0.47UF

20%

201

CERM-X5R-1

4V

402-LF

2.2UF

6.3V

20%

CERM

402-LF

2.2UF

6.3V

20%

CERM

201

4V

0.47UF

20%

CERM-X5R-1

20%

0.47UF

201

CERM-X5R-1

4V

0.47UF

4V CERM-X5R-1

20%

201

20%

201

CERM-X5R-1

4V

0.47UF

CERM-X5R-1

0.47UF

201

4V

20%

67 30 29 11

6.3V

2.2UF

CERM

20%

402-LF

67 30 29 11

4X0201

5%

1/32W

36

1/32W

5%

36

4X0201

1/32W

5%

36

1/32W

4X0201

5%

36

5%

1/32W

4X0201

CERM 402-LF

20%

2.2UF

6.3V

36

4X0201

5%

1/32W

4X0201

1/32W365%

20%

0.47UF

201

CERM-X5R-1

4V

20%

0.47UF

201

CERM-X5R-1

4V

20% 4V

0.47UF

CERM-X5R-1 201

20%

201

CERM-X5R-1

4V

0.47UF

20% 4V CERM-X5R-1 201

C3420

1

2

C3421

1

2

C3410

1

2

C3411

1

2

C3412

1

2

C3400

1

2

C3401

1

2

C3424

1

2

C3425

1

2

C3414

1

2

C3415

1

2

C3416

1

2

C3404

1

2

C3405

1

2

C3450

1

2

C3451

1

2

C3440

1

2

C3441

1

2

C3442

1

2

C3430

1

2

C3431

1

2

C3454

1

2

C3455

1

2

C3444

1

2

C3445

1

2

C3446

1

2

C3434

1

2

C3435

1

2

C3422

1

2

C3423

1

2

C3470

1

2

C3471

1

2

C3472

1

2

C3402

C3403

1

2

C3426

1

2

C3427

1

2

C3474

1

2

C3475

1

2

C3476

1

2

C3406

1

2

C3407

1

2

C3452

1

2

C3453

1

2

C3490

1

2

C3491

1

2

C3492

1

2

C3432

1

2

C3433

1

2

C3456

1

2

C3457

1

2

C3494

1

2

C3495

1

2

C3496

1

2

C3436

1

2

C3437

1

2

C3481

1

2

C3460

1

2

RP3410

36

RP3409

36

RP3411

27

RP3408

45

RP3411

36

C3462

1

2

C3464

1

2

C3467

1

2

C3461

1

2

C3463

1

2

C3465

1

2

C3466

1

2

RP3408

36

RP3410

45

RP3408

18

RP3410

27

RP3414

27

RP3413

27

RP3414

18

C3483

1

2

C3485

1

2

C3480

1

2

C3482

1

2

C3484

1

2

C3487

1

2

C3486

1

2

C3488

1

2

C3489

1

2

C3469

1

2

C3479

1

2

R3468

12

C3468

1

2

R3469

12

R3478

12

C3478

1

2

R3479

12

RP3413

18

RP3410

18

RP3409

18

RP3413

36

RP3413

45

RP3409

45

RP3408

27

RP3409

27

RP3414

45

RP3411

18

RP3414

36

C3408

1

2

C3409

1

2

C3418

1

2

C3419

1

2

C3428

1

2

C3429

1

2

C3438

1

2

C3439

1

2

RP3411

45

RP3412

18

RP3412

27

RP3412

36

RP3412

45

C3493

1

2

C3477

1

2

RP3406

27

RP3402

27

RP3401

45

RP3401

27

RP3402

18

RP3403

18

RP3406

18

RP3407

36

RP3404

36

RP3402

36

RP3406

45

RP3404

18

RP3403

45

RP3407

27

RP3407

45

RP3407

18

RP3403

36

RP3402

45

RP3401

18

RP3401

36

RP3404

45

RP3404

27

RP3406

36

RP3405

18

RP3405

27

RP3405

36

RP3405

45

RP3403

27

051-9277

2.8.0

34 OF 109

32 OF 73

7

32

30 29

7

32 28 27

7

32 30 29

7

32 28 27

7

67 30 29 11

67 28 27 11

7

VDD

WRITE_PROTECT_SW

CARD_DETECT_SW CARD_DETECT_GND

DAT6 DAT7

DAT1

CD/DAT3

DAT2

DAT4

DAT5

VSS

CLK CMD DAT0

SHLD_PIN

SHLD_PIN SHLD_PIN

SHLD_PIN

GPIO2

RSTZ*

THRM_PAD

TEST

SD_WP

D7

D6

D5

D0

SD_CLK

D3

D2

GPIO1

DVDD

IOVDD

MS_INS

SD_CDZ

SD_CMD

PLLVDD

AVDD

D4

D1

PMOS

RREF

GPIO0

DP DM

NC

DET_OUT

DET_IN

RST_IN*

DET_CHNGD*

LOW_PWR

RST_OUT*

VDD

THRM

GND PAD

(IPU)

(OD)

DLY

XOR

LOGIC

RST

NC

IN

OUT

IN

BI

D

SG

D

SG

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SD Detect & Reset Logic

SDCONN_DETECT Debounce, Inversion, Detect-Changed PCH GPIO Latch Circuit Converts SDCONN from active-low level signal to active-high pulses

516-0237

PDMOD: POWER DOWN MODES

10K LOW = POWER SAVING MODE ENABLE 10K HIGH = REMOTE WAKE UP ENABLE

NC = DISABLE (DEFAULT)

(IPD)

*** Need to confirm with SW weather LATCH is required.

Connector shorts GND with Card_Detect_SW signal when SD card inserted.

DLY block is 20ms nominal When LOW_PWR gated dessarts, RST_OUT# deassserts for >80ms, then asserts for 10ms

Max Current = 800 mA

Keep this net short!

R3505 is for rail discharge. GL822 may cycle PMOS to recover from card error. Off duration is 100ms and card voltage must be less than 0.5V for at least 1ms per spec.

(IPU)

regardless of RST_IN# state. Otherwise RST_OUT# follows RST_IN#

(SDCONN_STATE_RST_L will be required with LATCH)

-> To GL822 Chip

(Low active pulse signal)

-> To SMC & Isolation Circuit (then to PCH GPIO)

From SD CONN ->

RESET_IN* musts be pulled to GND if not used. SD detect logic will only function if Reset logic is low.

CRITICAL

0805-1

0.22UH

CRITICAL

F-RT-TH

SD-CARD-K16

CRITICAL

GL822

QFN

X5R 201

BYPASS=U3500.8:5 mm

0.1UF

6.3V6.3V

0.1UF

201

X5R

BYPASS=U3500.8:5 mm

201

10K

MF

1/20W

X5R-CERM1

6.3V

4.7UF

20%

4.7UF

X5R-CERM1

6.3V

20%

20133MF

1/20W

MF-LF1/16W

0

1/16W

0

MF-LF

1/16W

0

MF-LF

0

MF-LF1/16W

0

1/16W

0

MF-LF

0

1/16W

0

MF-LF

0

1/16W MF-LF

1/16W

0

MF-LF

1/16W

MF-LF

0

NO STUFF

1/16W MF-LF

0

47NH-1.3OHM

0402

TDFN

SLG4AP014V

6

33

42

33

6

33

201

MF01/20W

X5R

6.3V

20%

0.22UF

0201

201

MF

1/20W

10K

201

X5R

6.3V

0.1UF

X5R

6.3V

BYPASS=U3500.1:16:5 mm

201

6.3V

0.1UF

BYPASS=U3500.3:5:5 mm

X5R

24 68

MF

47K

1/20W

201

1%

MF

1/20W

201

715

NO STUFF

10K

MF

1/20W

201

MF

201

10K

1/20W

NO STUFF

25V

NPO

201

SOT563

SSM6N37FEAPE

SOT563

SSM6N37FEAPE

23

25

SecureDigital Card Reader

SYNC_DATE=11/10/2011

SYNC_MASTER=J13_MLB_NON_POR

SD_CD_L

GL137_RESET_L_R

GL137_RESET_L

GL137_RREF

GL137_GPIO0

=PP3V3_S3_CARDREADER

GL137_GPIO1

SD_WP

SD_D_R<6>

SD_D_R<5>

SD_D_R<0>

SD_CLK_R

SD_D_R<2>

SDCARD_IOVDD

SD_CMD_R

SDCARD_PLLVDD

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.40MM

PP3V3_S3_CARDREADER_AVDD

SD_D_R<4>

SD_D_R<1>

MIN_LINE_WIDTH=0.30 MM

VOLTAGE=3.3V

PP3V3_SW_SD_PWR

MIN_NECK_WIDTH=0.20 MM

MAKE_BASE=TRUE

USB_SDCARD_P

USB_SDCARD_N

SD_CD_L

SD_D<7>

SD_D<6>

SD_D<5>

SD_D<3>

SD_D<2>

SD_CMD SD_D<0>

SD_CLK_R1 SD_CLK_R2

SD_D<1>

SD_CLK

SD_D<4>

SD_CLK_L

SDCONN_STATE_CHANGE_SMC

SDCONN_DETECT_L

=PP3V3_S4_SD_HPD

SDCARD_PLT_RST_L

SDCARD_PLT_RST

SDCONN_STATE_RST_L

SDCONN_DETECT_L

SD_D_R<7>

SD_D_R<3>

10PF

5%

C0G-CERM 0402

10PF

5%

C0G-CERM 0402

10PF

5%

C0G-CERM

0402

10PF

5%

C0G-CERM 0402

10PF

5%

C0G-CERM

0402

10PF

5%

C0G-CERM 0402

10PF

5%

C0G-CERM

0402

10PF

5%

C0G-CERM 0402

10PF

5%

C0G-CERM 0402

10PF

5%

50V

402

10%10%

10%

C3505

1

2

C3503

1

2

C3504

1

2

R3505

1

2

R3506

1

2

R3507

1

2

R3509

1

2

C3515

1

2

Q3500

3

5

4

Q3500

6

2

1

L3500

2

1

J3500

15

14

1

5

2

7

8

9

10

11

12

13

17

18

19

20

4

3

6

16

U3500

5

13 14 9 10 18 19 20 21

2

3

1716

22

6

17

82528

15

4

26 23

12

11

24

27

29

C3501

1

2

C3502

1

2

R3510

1

2

C3514

1

2

C3507

1

2

C3520

1

2

C3521

1

2

C3522

1

2

C3523

1

2

C3524

1

2

C3525

1

2

C3526

1

2

C3527

1

2

R3520

12

R3521

12

R3522

1

2

R3523

12

R3524

12

R3525

12

R3526

1

2

R3527

12

R3528

1

2

R3519

12

C3519

1

2

R3529

12

R3530

1

2

R3531

12

L3504

12

U3510

8

6

7

5

2

3

4

9

1

R3513

12

C3513

1

2

R3590

1

2

051-9277

2.8.0

35 OF 109

33 OF 73

7

6

7

OUT

BI

IN

BI

IN

OUT

PETN_3

PETN_2

PETP_2

PETP_1 PETN_1

PETP_0 PETN_0

MONOBS_N

MONDC0 MONDC1

PERN_3

PERP_3

PERN_2

PERP_2

PERN_1

PERP_1

PERP_0 PERN_0

MONOBS_P

TMU_CLK_IN

TMU_CLK_OUT

DPSRC_3_P

DPSRC_2_P

DPSRC_3_N

DPSRC_1_P

DPSRC_2_N

DPSRC_1_N

DPSRC_0_P

DPSRC_AUX_P

DPSRC_0_N

DPSRC_HPD_OD

DPSRC_AUX_N

GPIO_2/GO2SX

GPIO_15

GPIO_9/OK2GO2SX_OD*

GPIO_14

GPIO_8/EN_CIO_PWR_OD*

GPIO_7/CIO_SCL_OD

GPIO_6/CIO_SDA_OD

GPIO_5/CIO_PLUG_EVENT

GPIO_4/WAKE_N_OD

GPIO_3

PB_CIO3_TX_N/DP_SRC_2_N

PB_CONFIG2/CIO_2_LSOE

PB_CIO2_RX_N

PB_CONFIG1/CIO_2_LSEO

PB_CIO2_RX_P

PB_CIO2_TX_P/DP_SRC_0_P PB_CIO2_TX_N/DP_SRC_0_N

PB_CIO3_TX_P/DP_SRC_2_P

PB_DPSRC_3_N

PB_DPSRC_1_N

PB_DPSRC_1_P

PB_LSRX/CIO_3_LSOE

PB_CIO3_RX_N

PB_LSTX/CIO_3_LSEO

PB_CIO3_RX_P

PB_DPSRC_3_P

GPIO_11/PB_CIO_SEL/BYP1

GPIO_13/PB_DP_PWRDN/BYP2

GPIO_1/PB_HV_EN/BYP0

PB_DPSRC_HPD

PB_AUX_N

PB_AUX_P

THERMDA

EE_DI EE_DO EE_CS_N

TDI

EE_CLK

TDO

DPSNK0_2_P

DPSNK0_3_N

DPSNK0_1_P

DPSNK0_2_N

DPSNK0_0_P

DPSNK0_1_N

DPSNK0_AUX_P

DPSNK0_0_N

DPSNK0_HPD

DPSNK0_AUX_N

DPSNK1_3_N

DPSNK1_3_P

DPSNK1_2_N

DPSNK1_2_P

DPSNK1_1_N

DPSNK1_1_P

DPSNK1_0_N

DPSNK1_0_P

DPSNK1_AUX_N

DPSNK1_AUX_P

DPSNK1_HPD

PA_CIO0_TX_N/DP_SRC_0_N

PA_CIO0_TX_P/DP_SRC_0_P

PA_CIO0_RX_N

PA_CIO0_RX_P

PA_CONFIG2/CIO_0_LSOE

PA_CONFIG1/CIO_0_LSEO

PA_CIO1_TX_N/DP_SRC_2_N

PA_CIO1_TX_P/DP_SRC_2_P

PA_CIO1_RX_N

PA_CIO1_RX_P

PA_LSRX/CIO_1_LSOE

PA_LSTX/CIO_1_LSEO

PA_DPSRC_1_N

PA_DPSRC_1_P

PA_DPSRC_3_N

PA_DPSRC_3_P

PA_AUX_P

PA_DPSRC_HPD

PA_AUX_N

GPIO_10/PA_CIO_SEL/BYP1

GPIO_0/PA_HV_EN/BYP0

GPIO_12/PA_DP_PWRDN/BYP2

PETP_3

RSENSE

REFCLK_100_IN_P REFCLK_100_IN_N

XTAL_25_IN

XTAL_25_OUT

TMS TCK

TEST_EN TEST_PWR_GOOD

DPSNK0_3_P

PWR_ON_POC_RSTN

PERST_N

NC

RBIAS

PCIE_RST_0_N PCIE_RST_1_N

PCIE_RST_3_N

PCIE_RST_2_N

PCIE_CLKREQ_OD_N

EN_LC_PWR

PCIE RESET

PCIE GEN2

MISC

(SYM 1 OF 2)

CLOCKS

JTAG/TEST PORT

RECEIVE

TRANSMIT

EEPROM

SINK PORT 0SINK PORT 1

SOURCE PORT 0

PORT3 PORT2

PORT0PORT1

DISPLAYPORT

PORTS

OUT

NC

IN

OUT

IN

BI

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

BI

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

D

C

Q

S*

W*

HOLD*

PAD

VSS

THM

VCC

IN

OUT

IN

OUT

BI

IN

OUT

IN

OUT

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

For unused port, pull CONFIG1, CONFIG2, LSRX, HPD and CIO_SEL low (10k). All other port signals can be NC.

(TBT_SPI_MOSI)

(TBT_SPI_CLK)

DEBUG: For monitoring current/voltage

DEBUG: For monitoring clock

(TBT_SPI_MISO)

SNK1 AC Coupling

SNK0 AC Coupling

Not used in host mode.

(TBT_SPI_CS_L)

DEBUG: For monitoring current/voltage

Use AA8 GND ball for THERM_DN

DEBUG: For monitoring clock

8 - GPIO_15 9 - GPIO_11 10 - GPIO_14 11 - GPIO_0 12 - GPIO_12 13 - GPIO_10 14 - PB_LSTX 15 - PB_LSRX

NOTE: The following pins require testpoints:

1 - GPIO_1

0 - GPIO_13

3 - GPIO_3

2 - GPIO_2

4 - GPIO_5

7 - PCIE_RST_3_N

6 - PCIE_RST_2_N

5 - PCIE_RST_1_N

(FORCE_PWR)

if necessary. Stuff one of R3861/2.

of GPIO_2/GPIO_9

allows separation

R3681 for CYA,

(TBT_EN_CIO_PWR_L)

TP_DP_TBTSRC_AUXCH_CP

TP_DP_TBTSRC_ML_CN<0>

TP_DP_TBTSRC_ML_CP<0>

TP_DP_TBTSRC_ML_CN<1>

TP_DP_TBTSRC_ML_CP<1>

TP_DP_TBTSRC_ML_CN<2>

TP_DP_TBTSRC_ML_CN<3>

TP_DP_TBTSRC_ML_CP<2>

TBT_PCIE_RESET_L

SYSCLK_CLK25M_TBT_R TP_TBT_XTAL25OUT

TBT_TMU_CLK_OUT

TP_DP_TBTSRC_ML_CP<3>

10%

201

201 201

201

201201

201

201 201

201

16V

0.1UF

402

X5R

=PP3V3_TBTLC_RTR

TBT_B_R2D_C_P<1> TBT_B_R2D_C_N<1>

TBT_B_D2R_P<1> TBT_B_D2R_N<1>

TBT_B_LSRX

TBT_B_LSTX

DP_TBTPB_ML_C_P<1>

=PP3V3_S4_TBT

DP_TBTPA_HPD

TBT_B_CONFIG1_BUF

DP_TBTPB_ML_C_P<3>

TBT_EN_LC_PWR

TBTROM_HOLD_L

TBTROM_WP_L

=PP3V3_TBTLC_RTR

TBT_PWR_ON_POC_RST_L

PCIE_TBT_R2D_C_P<3>

=PP3V3_S4_TBT

DP_TBTSNK0_ML_P<0>

DP_TBTSNK0_ML_N<0>

DP_TBTSNK1_ML_P<2>

TP_DP_TBTSRC_AUXCH_CN

TBT_SPI_CS_L TBT_SPI_CLK

DP_TBTSNK0_ML_N<2>

=PP3V3_TBTLC_RTR

PCIE_TBT_R2D_C_P<1>

PCIE_TBT_R2D_C_N<0>

PCIE_TBT_R2D_C_P<0>

DP_TBTSNK0_ML_C_P<3>

PCIE_TBT_D2R_P<2>

PCIE_TBT_D2R_P<1>

PCIE_TBT_D2R_N<0>

PCIE_TBT_D2R_P<0>

PCIE_TBT_D2R_N<1>

PCIE_TBT_D2R_N<3>

PCIE_TBT_R2D_C_N<1>

DP_TBTSNK1_ML_C_P<0>

DP_TBTSNK0_ML_C_P<2>

DP_TBTSNK0_ML_C_P<1>

DP_TBTSNK0_ML_C_N<0>

DP_TBTSNK0_ML_C_P<0>

DP_TBTSNK0_ML_C_N<1>

DP_TBTSNK0_ML_C_N<3>

DP_TBTSNK0_AUXCH_C_P

DP_TBTSNK0_AUXCH_C_N

DP_TBTSNK1_ML_C_N<0>

DP_TBTSNK1_AUXCH_C_P

DP_TBTSNK1_ML_C_N<2>

DP_TBTSNK1_ML_C_P<1>

DP_TBTSNK1_AUXCH_N

DP_TBTSNK0_ML_P<1>

DP_TBTSNK1_ML_P<3>

DP_TBTSNK1_ML_C_P<2>

DP_TBTSNK1_ML_C_N<1>

DP_TBTSNK0_ML_C_N<2>

DP_TBTSNK0_ML_N<2>

DP_TBTSNK0_ML_N<1>

DP_TBTSNK1_ML_N<0>

DP_TBTSNK1_ML_P<2>

DP_TBTSNK1_ML_N<3>

DP_TBTSNK1_AUXCH_P

DP_TBTSNK1_ML_N<2>

DP_TBTSNK1_ML_N<1>

DP_TBTSNK1_ML_P<1>

PCIE_TBT_D2R_P<3>

DP_TBTSNK1_ML_P<0>

PCIE_TBT_R2D_C_P<2>

DP_TBTSNK0_AUXCH_P

DP_TBTSNK0_ML_N<3>

DP_TBTSNK0_ML_P<3>

PCIE_TBT_D2R_N<2>

SYSCLK_CLK25M_TBT

DP_TBTSNK1_ML_C_N<3>

TP_TBT_PCIE_RESET2_L TP_TBT_PCIE_RESET3_L

TP_TBT_PCIE_RESET1_L

TBT_RBIAS

DP_TBTSNK0_ML_P<3>

JTAG_TBT_TCK

JTAG_TBT_TMS

TBT_RSENSE

PCIE_TBT_D2R_C_P<3>

TBT_A_DP_PWRDN

TBT_A_HV_EN TBT_A_CIO_SEL

DP_TBTPA_AUXCH_C_N

DP_TBTPA_AUXCH_C_P

DP_TBTPA_ML_C_P<3> DP_TBTPA_ML_C_N<3>

DP_TBTPA_ML_C_P<1> DP_TBTPA_ML_C_N<1>

TBT_A_LSTX TBT_A_LSRX

TBT_A_D2R_N<1>

TBT_A_R2D_C_P<1> TBT_A_R2D_C_N<1>

TBT_A_CONFIG2_RC

TBT_A_D2R_P<0>

TBT_A_R2D_C_P<0>

DP_TBTSNK1_HPD

DP_TBTSNK1_ML_P<0> DP_TBTSNK1_ML_N<0>

DP_TBTSNK1_ML_P<1> DP_TBTSNK1_ML_N<1>

DP_TBTSNK1_ML_N<2>

DP_TBTSNK1_ML_P<3> DP_TBTSNK1_ML_N<3>

DP_TBTSNK0_AUXCH_N

DP_TBTSNK0_HPD

DP_TBTSNK0_ML_N<0>

DP_TBTSNK0_AUXCH_P

DP_TBTSNK0_ML_N<1>

DP_TBTSNK0_ML_P<0>

DP_TBTSNK0_ML_P<1>

DP_TBTSNK0_ML_N<3>

DP_TBTSNK0_ML_P<2>

JTAG_TBT_TDO

JTAG_TBT_TDI

TBT_SPI_MISO

TP_TBT_THERM_DP

DP_TBTPB_AUXCH_C_P DP_TBTPB_AUXCH_C_N

DP_TBTPB_HPD

TBT_B_HV_EN

TBT_B_DP_PWRDN

TBT_B_CIO_SEL

TBT_B_R2D_C_P<0>

PCIE_TBT_R2D_N<0>

PCIE_TBT_R2D_P<0>

PCIE_TBT_R2D_P<1> PCIE_TBT_R2D_N<1>

PCIE_TBT_R2D_P<2> PCIE_TBT_R2D_N<2>

PCIE_TBT_R2D_P<3> PCIE_TBT_R2D_N<3>

TP_TBT_MONDC1

PCIE_TBT_D2R_C_N<0>

PCIE_TBT_D2R_C_P<0>

PCIE_TBT_D2R_C_N<1>

PCIE_TBT_D2R_C_P<1>

PCIE_TBT_D2R_C_P<2> PCIE_TBT_D2R_C_N<2>

PCIE_TBT_D2R_C_N<3>

TBT_MONOBSN

TBT_MONOBSP

DP_TBTSNK1_AUXCH_N

TBT_B_CONFIG2_RC

DP_TBTSNK1_AUXCH_P

TBT_A_D2R_P<1>

TBT_B_R2D_C_N<0>

DP_TBTPB_ML_C_N<1>

DP_TBTPB_ML_C_N<3>

DP_TBTSNK0_AUXCH_N

DP_TBTSNK0_ML_P<2>

DP_TBTSNK1_ML_C_P<3>

DP_TBTSNK1_AUXCH_C_N

TBT_A_CONFIG1_BUF

TBT_A_D2R_N<0>

TBT_A_R2D_C_N<0>

TBT_B_D2R_P<0> TBT_B_D2R_N<0>

=TBT_WAKE_L

TBT_TEST_EN TBT_TEST_PWR_GOOD

TP_TBT_PCIE_RESET0_L

=TBT_CLKREQ_L

PCIE_TBT_R2D_C_N<2>

PCIE_TBT_R2D_C_N<3>

TBT_A_HV_EN TBT_B_HV_EN

TBT_GPIO_14

TBT_GPIO_9

TBT_GO2SX_BIDIR

TBT_DDC_XBAR_EN_L

TBT_SPI_MOSI

PCIE_CLK100M_TBT_P PCIE_CLK100M_TBT_N

TBT_TMU_CLK_IN

TBT_PWR_EN

TBT_B_DP_PWRDN

TBT_A_DP_PWRDN

TBT_PWR_REQ_L

TBT_DDC_XBAR_EN_L

TBT_GPIO_14

TBT_GPIO_9

MAKE_BASE=TRUE

TBT_EN_CIO_PWR_L

DP_TBTSRC_HPD

Thunderbolt Host (1 of 2)

SYNC_MASTER=J11_MLB

SYNC_DATE=09/30/2011

69

8

69

8

69

8

69

8

69

8

69

8

69

8

69

8

69

8

69

8

69

8

69

8

69

8

69

8

69

8

69

8

X5R-CERM

0201

X5R-CERM

0201

X5R-CERM

0201

X5R-CERM

0201

3.3K

5%

MF

1/20W

0201

X5R-CERM

0201

X5R-CERM

0201

X5R-CERM

0201

X5R-CERM

0201

X5R-CERM

0201

5%

3.3K

MF

1/20W

X5R-CERM

0201

X5R-CERM

0201

X5R-CERM

0201

36

0

5% 1/20W MF

MF

5% 1/20W

10K

MF

5%

1/20W

10K

NO STUFF

10K

1/20W

5%

MF

34 19

23

34

1/20W

10K

5%

MF

10K

1/20W

5%

MFMF

5%

1/20W

10K

1/20W

5%

MF

5%

1/20W

100K

34

18

44

42

25

100K

5% 1/16W MF-LF

36

MF

47K

1/20W

5%

NO STUFF

0201

X5R-CERM

36

NONE

NOSTUFF

NONE NONE

OMIT

OMIT_TABLE

M95256-RMC6XG

MLP

CRITICAL

6.3V

20%

1UF

0201

70

8

70

8

70

8

70

8

70

8

70

8

70

8

70

8

70

8

70

8

70

8

70

8

70

8

70

8

34

8

34

70 64

64

70 64

64

70 64

64

64 36 34

64

64 34

69 16

5%

1/20W

MF

10K

NO STUFF

MF

1/20W

5%

1K

806

1%

MF

1/20W

10K

5%

MF

1/20W

69 25

36

CACTUSRIDGE4C

FCBGA

OMIT_TABLE

CRITICAL

8

16

19

8

69

8

69

8

69

8

69

8

69

8

69

8

69

8

69

8

69

8

69

8

0201

X5R-CERM

0201

X5R-CERM

0201

X5R-CERM

0201

X5R-CERM

0201

X5R-CERM

0201

X5R-CERM

0201

X5R-CERM

0201

X5R-CERM

0201

X5R-CERM

0201

X5R-CERM

0201

X5R-CERM

1K

1%

MF

1/20W

0201

X5R-CERM

0201

X5R-CERM

0201

X5R-CERM

0201

X5R-CERM

0201

X5R-CERM

0201

X5R-CERM

69

8

69

8

69

8

69

8

69

8

69

8

69

8

69

8

69

8

69

8

0201

X5R-CERM

5%

MF

1/20W

3.3K

5%

0

MF

1/20W

MF

5%

1/20W

100K

MF

5%

1/20W

5%

0

MF

1/20W

8

5%

3.3K

MF

1/20W

36

TP_TBT_MONDC0

TBT_GO2SX_BIDIR

=I2C_TBTRTR_SCL

=I2C_TBTRTR_SDA

TBT_CIO_PLUG_EVENT

R3690

1

2

R3692

1

2

R3691

1

2

R3655

1

2

C3601

12

C3600

12

C3602

12

C3603

12

C3604

12

C3605

12

C3606

12

C3607

12

C3640

12

C3641

12

C3642

12

C3643

12

C3645

12

C3644

12

C3646

12

C3647

12

R3625

1

2

R3630

1

2

R3631

1

2

R3629

1

2

R3693

1

2

C3629

12

C3628

12

C3627

12

C3626

12

C3625

12

C3624

12

C3623

12

C3622

12

C3621

12

C3620

12

C3630

12

C3631

12

C3632

12

C3633

12

C3634

12

C3635

12

C3636

12

C3637

12

C3638

12

C3639

12

U3600

D19

E20

D17

E18

D15

E16

D13

E14

B5

A6

U6

D11

E12

D9

E10

D7

E8

D5

E6

B3

A4

T5

B9

A8

B11

A10

B13

A12

B15

A14

D3

C2

V3

W4

AD3

R4

P5

K5

G2

M3 L2

H3 L4

T3

V5

M1

Y1

W2

J4

AA2

AB1

AC2

P3

M5

AD23

AC24

W16

W18

F1

F3

E22

G22

E24

G24

J22

L22

J24

L24

K1

G4

B17

A16

B19

A18

H1

J6

N2

E2

D1

N22

R22

N24

R24

U22

W22

U24

W24

P1

H5

B21

A20

B23

A22

K3

G6

L6

W6

N6

T1

Y5

U2

AA10

AB13

AA16

AB19

AB9

AA12

AB15

AA18

R6

AD7

AD11

AD15

AD19

AD5

AD9

AD13

AD17

J2

W20

AD21

AB21

U20

AA6

V1

R2

N4

AB5

Y7

AB3

Y3

AA4

AA24

AB23

R3698

1

2

R3695

12

R3696

1

2

R3699

1

2

C3690

1

2

U3690

6

5

7

2

1

9

8

4

3

R3615

1

2

C3610

1

2

R3610

1

2

R3632

1

2

R3697

1

2

R3685

1

2

R3688

1

2

R3687

1

2

R3686

1

2

R3682

1

2

R3683

1

2

R3680

1

2

R3681

1

2

051-9277

2.8.0

36 OF 109

34 OF 73

U4

36 35 34

7

36 35 34

7

36 35 34

7

36 35 34

7

69 34

70

69 34

36 35 34

7

69 34

69

69 34

70

47

69

69 34

64 36 34

34

34 19

34

70

69

34

64 34

34

VSSPE VSSPE

VSSPE

VSSPE VSSPE

VSSPE

VSSPE VSSPE

VSSPE VSSPE VSSPE

VSSPE VSSPE

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VCC1P0_DPAUX

VCC3P3_POC

VSSPE

VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE

VCC1P0_PE

VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE

VCC1P0 VCC1P0

VCC3P3_DP VCC3P3_DP

VCC3P3_DP

VCC3P3_CIO

VCC3P3

VCC1P0

VCC1P0 VCC1P0

VCC1P0

VCC1P0_ON

VCC3P3

VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE

VSSPE

VSSPE VSSPE VSSPE VSSPE

VSSPE

VSSPE VSSPE VSSPE

VSSPE

VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE

VSSPE

VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE

VSSPE

VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE

VSSPE

VCC3P3_DP

VCC3P3_DPAUX

(SYM 2 OF 2)

VCCGND

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

EDP: 240 mA

250 mA (Dual-Port)

??? mA (Single-Port)

EDP: 3000 mA

2700 mA (Dual-Port)

???? mA (Single-Port)

250 mA (Dual Port)

???? mA (Single Port)

EDP: 10 mA

EDP: 1000 mA

20%

X5R

6.3V

1.0UF

0201-MUR

6.3V CERM-X5R 0402-1

10UF

20%

X5R

6.3V

1.0UF

0201-MUR

20%

X5R

6.3V

1.0UF

0201-MUR

6.3V

20%

1.0UF

X5R 0201-MUR

1.0UF

20%

X5R 0201-MUR

6.3V

CERM-X5R

20%

6.3V

0402-1

10UF

20%

10UF

0402-1

CERM-X5R

6.3V

X5R

6.3V

20%

1.0UF

0201-MUR

CRITICAL

OMIT_TABLE

CACTUSRIDGE4C

FCBGA

6.3V CERM-X5R 0402-1

10UF

20%20%

X5R

6.3V

1.0UF

0201-MUR

20%

X5R

6.3V

1.0UF

0201-MUR

X5R

20%

6.3V

1.0UF

20%

X5R

1.0UF

0201-MUR

6.3V

X5R

6.3V

0201-MUR

20%

1.0UF

X5R

6.3V

1.0UF

20%

0201-MUR

1.0UF

0201-MUR

6.3V X5R

20%

6.3V X5R 0201-MUR

1.0UF

20%

X5R 0201-MUR

1.0UF

20%

6.3V

20%

6.3V

1.0UF

0201-MUR

X5R

20%

X5R

6.3V

1.0UF

0201-MUR

20%

X5R

6.3V

1.0UF

0201-MUR

20%

X5R

6.3V

1.0UF

0201-MUR

20%

X5R

6.3V

1.0UF

0201-MUR

Thunderbolt Host (2 of 2)

SYNC_DATE=10/04/2011

SYNC_MASTER=J11_MLB

=PP3V3_TBTLC_RTR

=PP1V05_TBTCIO_RTR

=PP1V05_TBTLC_RTR

=PP3V3_S4_TBT

C3714

1

2

C3710

1

2

C3712

1

2

C3718

1

2

C3713

1

2

C3700

1

2

C3701

1

2

U3600

K11

K15

R10

R14

T11

U10

V11

W10

L10

L14

M11

M15

N10

N14

P11

P15

G8

H9

J10

J12

J14

J16

J8

K17

T15

U14

V7

W8

G10

G12

V15

V19

W12

W14

G14

G16

G18

H19

K19

M19

P19

T19

M7

P7

T7

L18

N18

R18

H11

H13

H15

H17

H7

K7

AD1

K13

N16

N8

P13

P17

P9

R12

R16

R8

T13

T17

K9

T9

U12

U16

U8

V9

L12

L16

L8

M13

M17

M9

N12

A2

A24

AC12

AC14

AC16

AC18

AC20

AC22

AC4

AC6

AC8

B1

AA14

B7

C10

C12

C14

C16

C18

C20

C22

C24

C4

AA20

C6

C8

D21

D23

E4

F11

F13

F15

F17

F19

AA22

F21

F23

F5

F7

F9

G20

H21

H23

J18

J20

AA8

K21

K23

L20

M21

M23

N20

P21

P23

R20

T21

AB11

T23

U18

V13

V17

V21

V23

Y11

Y13

Y15

Y17

AB17

Y19

Y21

Y23

Y9

AB7

AC10

C3760

1

2

C3772

1

2

C3771

1

2

C3770

1

2

C3790

1

2

C3729

1

2

C3732

1

2

C3730

1

2

C3744

1

2

C3743

1

2

C3742

1

2

C3741

1

2

C3740

1

2

C3745

1

2

C3705

1

2

C3773

1

2

C3774

1

2

051-9277

2.8.0

37 OF 109

35 OF 73

7

34 36

7

34 36

IN

D

GS

D

SG

D

SG

IN

SGD

NC

VIN

FBX

EN/UVLO

INTVCC

VC

RT

SS

SYNC

SW

SGND

GND

NC

SNS1

SNS2

OUT

IN

RESET*

OUT

EN

MR*

GND

THRM

IN

VDD

SENSE

+

-

PAD

(OD)

0.7V

DLY

IN

OUT

IN

GND

VOUT

ON

VIN

GND

VOUT

ON

VIN

D

SG

OUT

SENSE

THRM

RESET*

CT

GND

MR*

VDD

PAD

VOUT

GND

ON

VIN

D

SG

IN

D

GS

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Part

Type

R(on) @ 2.5V

Max Current = 2A (85C)

3.3V TBT "LC" Switch

18.5 mOhm Typ

TPS22924C

Load Switch

25.8 mOhm Max

U3810

1.05V TBT "LC" Switch

@ 1.05V

Load Switch

Freq = 300KHz

Max Current = 1.0A

Vout = 15.1V

UVLO(falling) = 1.22 * (R1 + R2) / R2

UVLO = 4.55V (falling), 4.95 (rising)

UVLO(rising) = UVLO(falling) + (2uA * R1)

1.05V TBT "CIO" Switch

Vt = 2.33V +/- 2%

8 mOhm Typ

U3815

Part

GND inside package,

Max Vgs: 10V

Vgs(max): +/-12V

Vds(max): -30V

- =PP18V_TBT_REG (18V Boost Output)

- =PP1V05_TBT_P1V05TBTFET (1.05V FET Input)

Signal aliases required by this page:

BOM options provided by this page:

8-13V Input Changes required for 2S.

Id(max): 3.7A @ 70C

TPS22924C

- =PP1V05_TBT_FET (1.05V FET Output)

Type

28.6 mOhm Max

Page Notes

TBTBST:Y - Stuffs 18V boost circuitry.

- =TBT_CLKREQ_L

- =TBT_RESET_L

- =PPVIN_SW_TBTBST (8-13V Boost Input)

<Ra>

add property on another page.

- =PP3V3_S0_TBTPWRCTL

- =PP3V3_TBT_P3V3TBTFET (3.3V FET Input)

<R1>

<Rb>

SI8409DB:

R(on)

TPS22920

U3820

11.5 mOhm Max

Type

R(on)

(IPU)

Delay = 27.3ms

Part

20.3 mOhm Typ

Pull-up: R3610

Supervisor & CLKREQ# Isolation

@ 1.0V

Max Current = 4A (85C)

WF: C value may need tuning.

Rds(on): 46mOhm @ 4.5V Vgs

Voltage not specified here,

Vgs(th): -1.4V

<R2>

SGND shorted to

Vout = 1.6V * (1 + Ra / Rb)

TBT 15V Boost Regulator

Pull-up provided by SB page.

RC guarantees minimum 5ms to reach 0.5V

Max Current = 2A (85C)

Load Switch

C3816 must be 10%

- =PP3V3_TBT_FET (3.3V FET Output)

Power aliases required by this page:

TPS3808G25

Platform (PCIe) Reset

TBT "POC" Power-up Reset

Intel investigating whether RC is sufficient.

no XW necessary.

DLY = 60 ms +/- 20%

0201

CSP

1/20W

201

MF

5%

0

NO STUFF

100PF

MIN_NECK_WIDTH=0.2 mm

22PF

MF

34 64

1/20W

5%

MF

470K

25V X5R

0.1UF

SOD-VESM-HF

1/20W

MF

1%

73.2K

1/20W MF

5%

330K

SOT563

SSM6N37FEAPE

SOT563

6.3V

0.33UF

CERM-X5R

330K

5% 1/20W

25 41 42

MF-LF

1/16W

15.8K

CRITICAL

SI8409DB

BGA

MF

1%

200K

1/20W

QFN

LT3957

SM

DFLS230L

CRITICAL

150K

5%

MF

1/20W

10K

1/20W

MF

1%

MF-LF

1/16W

1%

133K

6.8UH-4.0A

CRITICAL

34

100K

5% 1/20W MF

TDFN

CRITICAL

0201

X5R-CERM

0.1UF

25

16

34

X5R-CERM

6.3V

1.0UF

0201

6.3V

0201

100K

5% 1/20W MF

SOT563

SSM6N37FEAPE

34

TPS3808

QFN

X5R-CERM

CRITICAL

TPS22920

6.3V

X5R-CERM

1.0UF

0201

MF

5%

100K

SSM6N37FEAPE

34

19

49.9K

1/16W

1%

MF-LF

VESM

MF

1/20W

5%

10K

10UF

0603

X5R-CERM

25V

20%

X5R-CERM 0603

25V

20%

10UF

805

X5R

4.7UF

TBT Power Support

SYNC_DATE=11/10/2011

SYNC_MASTER=J13_MLB_NON_POR

=TBT_RESET_L

TBTBST_EN_UVLO

TBTPOCRST_MR_L

TBT_SW_RESET_L

TBT_PWR_ON_POC_RST_L

TBT_PCIE_RESET_L

=PP3V3_S0_PCH_GPIO

=PP3V3_S4_TBT

=PP3V3_S0_P3V3TBTFET

TBT_EN_CIO_PWR_L

=PP3V3_TBTLC_RTR

TBTBST_FBX

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

TBTBST_RT

MIN_LINE_WIDTH=0.2 mm

=PP3V3_TBTLC_RTR

=TBT_CLKREQ_L

MAKE_BASE=TRUE

TBT_EN_LC_ISOL

TBTBST_PWREN_L

TBTBST_BOOST

MIN_LINE_WIDTH=0.5 mm

DIDT=TRUE

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.25 mm

PPVIN_SW_TBTBST

MIN_LINE_WIDTH=0.5 mm

=PPVIN_SW_TBTBST

TBTBST_VC

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

TBTBST_INTVCC

MIN_LINE_WIDTH=0.2 mm

VOLTAGE=0V

SMC_DELAYED_PWRGD

MIN_NECK_WIDTH=0.25 mm

MIN_NECK_WIDTH=0.2 mm

PIMB062D-SM

MIN_NECK_WIDTH=0.2 mm

1%

TBTBST_SS

20% 25V

10UF

25V

20%

X5R-CERM

20% 25V

X5R-CERM

20% 25V

25V

20%

0603

X5R-CERM

PP1V05_TBTLC

SSM3K15FV

TBT_A_HV_EN

TBTBST_PWREN_DIV_L

GND_TBTBST_SGND

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

25V

5%

47PF

0201

SSM6N37FEAPE

TBTBST_SNS2

CRITICAL

MIN_LINE_WIDTH=0.2 mm

CERM

5%

CERM

TBTBST_VSNS_RC

SOT563

MIN_NECK_WIDTH=0.2 mm

TBTBST_SNS1

10UF

=PP1V05_S0_P1V05TBTFET

TBTPOCRST_CT

CRITICAL

=PP1V05_TBTCIO_FET

0.1UF

X7R-CERM 0201

330PF

16V

50V

402

41.2K

1%

1/20W

MF

TBTBST_VC_RC

NP0-C0G-CERM

10V

201

10%

10V X7R-CERM 0201

3300PF

10%

TBTBST_SHDN_DIV

=PP1V05_S0_P1V05TBTFET

CERM

25V

10%

0.0047UF

0402

10UF

X5R-CERM

25V

20%

0603

20% 25V X5R-CERM

10UF

0603

20% 25V X5R-CERM

10UF

0.001UF

50V

10%

=PP15V_TBT_REG

PLACE_NEAR=C3895.1:2 mm

10UF

X5R-CERM

10UF

POWERDI-123

X5R-CERM

TBTBST_VSNS

0402

X7R-CERM

34

TBT_CLKREQ_L

201

1/20W

MF

1%

1/20W

10%

0201

X5R-CERM

6.3V

36.5K

SSM3K15AMFVAPE

TBT_EN_LC_PWR

CSP

TPS22924

TBT_EN_CIO_PWR

TBT_CLKREQ_ISOL_L

SLG4AP016V

=PP3V3_S0_TBTPWRCTL

CRITICAL

X5R-CERM

1.0UF

=PP1V05_TBTLC_FET

TBT_EN_LC_1V05

TPS22924

CRITICAL

CSP

10%

NO STUFF

1.0UF

6.3V

X5R-CERM

0201

=PP3V3_TBTLC_FET

201

MF

1/20W

5%

0

TBT_EN_LC_3V3

R3880

1

2

C3880

1

2

Q3805

3

1

2

R3892

1

2

R3887

1

2

Q3888

3

5

4

Q3888

6

2

1

R3894

1

2

C3894

1

2

R3888

1

2

C3889

1

2

R3896

1

2

Q3880

23

1

4

R3891

1

2

U3890

25

31

1213141516

17

28

1

2

10

35

36

33

6

3

42324

37

32

8

9

202138

34

30

27

XW3895

12

R3889

1

2

D3895

A

K

C3899

1

2

C3893

1

2

R3881

1

2

R3893

1

2

R3895

1

2

L3895

12

R3807

1

2

U3800

6

5

7

3

8

4

2

9

1

C3800

1

2

U3810

C1

C2

A2

B2

A1

B1

C3810

1

2

U3815

C1

C2

A2

B2

A1

B1

C3815

1

2

C3816

1

2

R3830

1

2

Q3825

3

5

4

U3830

3

5

4

62

7

1

C3830

1

2

U3820

D1

D2

A2

B2

C2

A1

B1

C1

C3820

1

2

R3820

1

2

Q3825

6

2

1

R3890

12

R3816

1

2

Q3840

3

1

2

R3840

1

2

C3825

1

2

C3890

1

2

C3891

1

2

C3892

1

2

C3895

1

2

C3897

1

2

C3884

1

2

C3883

1

2

C3896

1

2

C3898

1

2

C3887

1

2

C3888

1

2

C3831

1

2

C3882

1

2

C3881

1

2

C3811

1

2

R3811

12

051-9277

2.8.0

38 OF 109

36 OF 73

7

16 17 18 19

7

34 35

7

36

7

34 35 36

7

34 35

6 7

7

36

7

25

7

OUT

IN

OUT

RESET*

OUT

EN

MR*

GND

THRM

IN

VDD

SENSE

+

-

PAD

(OD)

0.7V

DLY

OUT

IN

OUT

BI

VCC

GND

SEL OE*

D+ D-

Y+ Y-

M+ M-

OUT

D

GS

IN

G

S

D

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DLY = 60 MS +/- 20%

BLUETOOTH

LOADING

H USB_BT

L USB_BT_WAKE

20-30 MOHM @2.5V

SEL OUTPUT

514S0335

CHANNEL

0.750 A (EDP)

P-TYPE

3V S3 WLAN FET

TPCP8102

MOSFET

RDS(ON)

AIRPORT

6

17

62

0.1UF

X5R

6.3V

PLACEMENT_NOTE=Place close to J4001.

16 69

PLACEMENT_NOTE=Place close to J4001.

0.1UF

6.3V

X5R

6

16 69

6

16 69

X5R

6.3V

0.1UF

PLACEMENT_NOTE=Place close to Q4050.

6

16 69

6

16 69

0.020

MF-LF

CRITICAL

1%

0.25W 805

46 72

SLG4AP016V

TDFN

CRITICAL

6.3V X5R

0.1UF

16

25

18 23 62

5% MF

100K

1/20W

100K

MF

1%

1/20W

232K

1/20W

1% MF

0.1UF

6.3V X5R

SSD-K99

CRITICAL

F-RT-SM1

6

41 42

603

10UF

X5R

PLACEMENT_NOTE=Place close to Q4050.

20%

0.1UF

0201

X5R-CERM

16V

5%

0

MF

1/20W

NOSTUFF

MF

1/20W

1%

15K

1% 1/20W

15K

MF

NOSTUFF

BTPWR:S4

15K

MF

1/20W

1%

24 68

0.1UF

6.3V X5R

TQFN

CRITICAL

PI3USB102ZLE

42

BTPWR:S4

SOD-VESM-HF

SSM3K15FV

BTPWR:S4

0

1/20W

5%

17 26 41 49 62

MF

1/20W

5%

0

BTPWR:S3

MF

15K

1/20W

1%

NOSTUFF

15K

1% 1/20W MF

15K

1/20W

NOSTUFF

BTPWR:S4

MF-LF

5%

0

402

1/16W

BTPWR:S3

1/16W

0

5%

MF-LF

402

DFN2563-6

CRITICAL

DMP2018LFK

402

16V

0.033UF

X5R

100K

1/20W

5% MF

5% 1/20W MF

10K

SYNC_DATE=10/11/2011

SYNC_MASTER=J11_MLB

X21 WIRELESS CONNECTOR

PP3V3_WLAN_R

VOLTAGE=3.3V

MIN_LINE_WIDTH=20 mm

MIN_NECK_WIDTH=0.2 mm

=PP3V3_S3_WLAN

P3V3WLAN_SS

PP3V3_S3RS4_BT_F

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=3.3V

USB_BT_CONN_P

USB_BT_CONN_N

PCIE_WAKE_L

AP_RESET_CONN_L

AP_CLKREQ_Q_L

PCIE_AP_D2R_N

USB_BT_WAKE_P

PP3V3_S3RS4_BT_F

=PP3V3_S3_WLAN

BTMUX_SEL

USB_BT_WAKE_N

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=3.3V

MIN_LINE_WIDTH=20 mm

PP3V3_WLAN_F

PCIE_CLK100M_AP_N

PCIE_CLK100M_AP_P

USB_BT_N

=BT_WAKE_L

USB_BT_P

PCIE_AP_R2D_C_N

PCIE_AP_R2D_C_P

WIFI_EVENT_L

PP3V3_WLAN_F

=PP3V3_S4_BT

PM_SLP_S4_L

AP_CLKREQ_L

AP_CLKREQ_L_R

P3V3WLAN_VMON

AP_RESET_L

PCIE_AP_R2D_N

AP_PWR_EN

PCIE_AP_R2D_P

PM_WLAN_EN_L

ISNS_AIRPORT_P ISNS_AIRPORT_N

=PP3V3_S3_BT

PLACE_NEAR=J4001.18:1.5mm

1%

MF

PCIE_AP_D2R_P

MF

NOSTUFF

0.01UF

16V

X7R-CERM

0402

10V

201

201201

201

201201

201

10%

C4021

1

2

C4051

1

2

R4050

12

R4051

1

2

C4030

12

C4031

12

R4052

12 34

U4002

6

5

7

3

8

4

2

9

1

C4053

1

2

R4053

1

2

R4055

1

2

R4054

1

2

C4032

1

2

J4001

19

20

21

1

10

11

12

13

14

15

16

17

18

2

3

4

5

6

7

8

9

C4020

1

2

C4050

12

R4090

12

R4014

1

2

R4013

1

2

R4012

1

2

C4010

1

2

U4010

6

7

3

4

5

8

10

9

2

1

Q4010

3

1

2

R4011

12

R4018

1

2

R4017

1

2

R4016

1

2

R4015

1

2

R4001

12

R4002

12

Q4050

4

3

1

2

C4011

1

2

051-9277

2.8.0

40 OF 109

37 OF 73

7

37

6

37

6

68

6

68

6

68

6

37

7

37

68

6

37 42

6

37 42

7

6

69

6

69

7

OUT

IN

A1_P A1_N

SEL

XSD

B0_P

B1_P

B0_N

B1_N

C0_P

C1_P

C0_N

C1_N

VDD

VSS

THRM

A0_P A0_N

PAD

OUT

IN

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PCIE/SATA GUMSTICK2 CONNECTOR

353S3361

514S0393

Per PCIe Spec, only TX side should have AC cap

FERR-70-OHM-4A

CRITICAL

0603

PLACE_NEAR=J4501.1:3mm

46 72

0.1UF

X5R-CERM 02010201

0.1UF

X5R-CERM

8

66

8

66

8

66

8

66

0.1UF

PLACE_NEAR=U4510.1:2 mm

0201

X5R-CERM

PLACE_NEAR=U4510.10:2 mm

0.01UF

16V X5R-CERM 0201

VQFN

CBTL02043ABQ

CRITICAL

16 68

6

41

42

6

41

10K

5%

MF

1/20W

16V

0201

X5R-CERM

0.1UF

6 8

66

6 8

66

8

66

8

66

0.1UF

X5R-CERM

16V

0201

5%

MF

1/20W

470K

16V

0201

X5R-CERM

0.1UF

0201

0.1UF

16V

X5R-CERM

0201

16V

0.1UF

0201

16V

X5R-CERM

0.1UF

0.01UF

16V

0201

X5R-CERM

0.01UF

16V

0201

X5R-CERM

0.01UF

16V

0201

X5R-CERM

0.01UF

16V

0201

X5R-CERM

X5R-CERM 0201

PLACE_NEAR=U4510.6:2 mm

0.1UF

CRITICAL

GND_VOID=TRUE GND_VOID=TRUE

F-RT-SM

SSD-J5

GND_VOID=TRUE

6

25

6

16

6

16 66

6

16 66

61 62

MF

1/20W

0

5%

6.3V

100UF

20%

1206-1

CERM-X5R

MF

1W

1%

0.002

CRITICAL

0612

CERM-X5R

100UF

1206-1

20%

6.3V

NOSTUFF

SYNC_DATE=10/17/2011

SSD CONNECTOR

SYNC_MASTER=J13_MLB_NON_POR

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.150mm

PP3V3_S0_SSD_FLT

MIN_NECK_WIDTH=0.150mm

MIN_LINE_WIDTH=0.6mm

VOLTAGE=3.3V

PP3V3_S0_SSD_R

PCIE_SSD_R2D_MUX_IN_P

SATA_SSD_R2D_N

ISNS_SSD_N

ISNS_SSD_P

=PP3V3_S0_SSD

SATA_SSD_R2D_P

PCIE_SSD_D2R_MUX_OUT_N

SATA_SSD_D2R_MUX_OUT_P

PCIE_SSD_R2D_C_P<1>

=PP3V3_S0_SATAMUX

SMC_OOB1_TX_L

SMC_OOB1_RX_L

SSD_RESET_L

PCIE_SSD_R2D_N<1>

PCIE_SSD_R2D_C_N<1>

SSD_P3V3S0_EN

=P3V3S0_EN

SATA_SSD_R2D_MUX_IN_P

SATAMUX_EN_L

SATA_HDD_D2R_P

SATA_HDD_D2R_N

SATA_HDD_R2D_C_N

SATA_SSD_R2D_MUX_IN_N

PCIE_SSD_D2R_N<0>

PCIE_SSD_D2R_P<0>

SATA_SSD_D2R_MUX_OUT_N

PCIE_SSD_R2D_C_P<0>

PCIE_SSD_R2D_C_N<0>

PCIE_SSD_D2R_MUX_OUT_P

SATA_HDD_R2D_C_P

PCIE_SSD_R2D_MUX_IN_N

SATA_SSD_D2R_N

PCIE_SSD_R2D_P<1>

PCIE_CLK100M_SSD_P PCIE_CLK100M_SSD_N

SATA_PCIE_SEL

SATA_SSD_D2R_P

SSD_CLKREQ_L

PCIE_SSD_D2R_N<1>

PCIE_SSD_D2R_P<1>

10V10V

201

10%10%

10% 10%

10%

L4500

12

C4502

1

2

C4501

1

2

C4514

1

2

C4519

1

2

U4510

4

3

8

7

18

19

16

17

14

15

12

13

9

21

1610

5

11

20

2

R4510

1

2

C4521

12

C4520

12

R4505

1

2

C4518

12

C4517

12

C4513

12

C4512

12

C4516

12

C4515

12

C4511

12

C4510

12

C4505

1

2

J4501

27 28 29 30 31 32 33 34 35

1

10 11 12 13 14 15 16 17 18

19

2

20 21 22 23 24 25 26

3 4 5 6 7 8 9

R4520

12

C4503

1

2

R4599

12 34

C4504

1

2

051-9277

2.8.0

45 OF 109

38 OF 73

6

66

6

68

7

6

68

66

68

7

6

66

6

68

66

6

68

6

66

6

68

OUT

IN

L2

L1

L2

L1

NC

GND

VBUS

IO

NC

GND

SSRX-

SXRX+

GND

D+

GND

SSTX+ SSTX-

D-

VBUS

SYM_VER-1

BI

IN

OUT

IN

OUT

GND

THRM

OUT2

OUT1

ILIM

IN_0 IN_1

EN2

FAULT1* FAULT2*

EN1

PAD

VCC

GND

SELOE*

D+ D-

Y+ Y-

M+ M-

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Mojo SMC Debug Mux

SEL=0 Choose SMC SEL=1 Choose USB

Right USB Port A

Current limit per port (R4600): 2.18A min / 2.63A max

USB Port Power Switch

10%

201

10V

PP5V_S3_RTUSB_A_ILIM

VOLTAGE=5V

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.15 mm

USB2_EXTA_MUXED_N

USB2_EXTA_MUXED_F_N

USB2_EXTA_MUXED_P

USB2_EXTA_MUXED_F_P

USB3_EXTA_RX_F_N

USB3_EXTA_RX_F_P

USB3_EXTA_TX_F_N

USB3_EXTA_RX_P

USB3_EXTA_TX_F_P

USB3_EXTA_RX_N

USB3_EXTA_TX_C_N

USB3_EXTA_TX_C_P

PP5V_S3_RTUSB_A_F

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.375 mm VOLTAGE=5V

SMC_DEBUGPRT_RX_L

USB_EXTA_P USB_EXTA_N

=PP3V42_G3H_SMCUSBMUX

SMC_DEBUGPRT_EN_L

USB3_EXTA_TX_N

USB3_EXTA_TX_P

SMC_DEBUGPRT_TX_L

USB_EN2

USB_EXTA_OC_L

=PP5V_S3_RTUSB

=USB_PWR_EN

USB_ILIM

SYNC_DATE=09/30/2011

SYNC_MASTER=J11_MLB

External A USB3 Connector

FERR-120-OHM-3A

0603

CRITICAL

220UF-35MOHM

6.3V

20%

CASE-B2-SM1

POLY-TANT

1/16W

402

MF-LF

1%

23.2K

PI3USB102ZLE

CRITICAL

TQFN

MOJO:YES

SIGNAL_MODEL=MOJO_MUX

SON

TPS2561DR

CRITICAL

0402-2

CERM-X5R

10UF

6.3V

20%

23

MOJO:NO

5%

0

MF

1/20W

MOJO:NO

0

5%

1/20W

MF

41

68 42 41

MF

1/20W

10K

MOJO:YES

5%

0201

X5R-CERM

0.1UF

MOJO:YES

68 18

0201

16V X5R-CERM

0.1UF

10UF

0402-2

CERM-X5R

6.3V

20%

DLP0NS

90-OHM

CRITICAL

TSSLP-2-1

ESD0P2RF-02LS

CRITICAL

TSSLP-2-1

ESD0P2RF-02LS

CRITICAL

ESD0P2RF-02LS

TSSLP-2-1

CRITICAL

TSSLP-2-1

ESD0P2RF-02LS

CRITICAL

F-RT-TH

USB3.0-J11-J13

1/20W

MF

0

5%

SLP1210N6

CRITICAL

RCLAMP0582N

80OHM-25%-100MA

GND_VOID=TRUE

CRITICAL

0504

CRITICAL

80OHM-25%-100MA

0504

GND_VOID=TRUE

X5R

6.3V

0.1UF

GND_VOID=TRUE

0.1UF

GND_VOID=TRUE

6.3V

X5R

68 18

0201

X5R-CERM

0.01UF

16V

C4695

1

2

C4691

1

2

C4650

1

2

R4650

1

2

R4651

12

R4652

12

C4690

1

2

U4600

4

5

10

6

1

7

2

3

9

8

11

U4650

6

7

3

4

5

8

10

9

2

1

R4600

1

2

C4696

1

2

L4605

12

C4605

1

2

C4620

12

C4621

12

L4610

1

2

3

4

L4620

1

2

3

4

D4600

1

4523

6

R4601

1

2

J4600

5 6

4

7

10

11 12 13 14 15 16 17 18

9

3

2

8

1

D4610

1

2

D4620

1

2

D4621

1

2

D4611

1

2

L4600

12

34

051-9277

2.8.0

46 OF 109

39 OF 73

68

68 68

68

7

62 40

6

IN

BI

OUT

IN

OUT

IN

OUT

BI

OUT

IN

OUT

BI

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(Right Speaker Enable)

ON MLB SIDE AS LIO CAN’T FIT CAPS

998-4617

10% 16V

0201

X5R-CERM

PLACE_NEAR=J4700.17:1.5mm

0.1UF

6

41 42 49

6

16 69

X5R-CERM

0201

10% 16V

PLACE_NEAR=J4700.7:1.5mm

0.1UF

6

18 68

6

18 68

6

24 68

6

24 68

6

18

6

25

6

51 72

6

51 72

6

41 42

6

39 62

6

18

6

41

6

44

6

44

23

6

16 69

6

44

6

44

6

16 69

6

16 69

6

16 69

GND_VOID=TRUE

1/20W

0

MF

5%

201

16V

10%

GND_VOID=TRUE

0.1UF

0201

X5R-CERM

NOSTUFF

0201

0.1UF

GND_VOID=TRUE

16V

X5R-CERM

10%

NOSTUFF

0.1UF

0201

16V

10%

X5R-CERM

GND_VOID=TRUE

201

5%

1/20W MF

0

GND_VOID=TRUE

0201

10% 16V

0.1UF

X5R-CERM

18 68

DF40CG3.0-48DS-0.4V

CRITICAL

F-ST-SM

ESD0P2RF-02LS

CRITICAL

TSSLP-2-1

CRITICAL

ESD0P2RF-02LS

TSSLP-2-1

CRITICAL

ESD0P2RF-02LS

TSSLP-2-1

CRITICAL

ESD0P2RF-02LS

TSSLP-2-1

X5R-CERM

PLACE_NEAR=J4700.9:1.5mm

0.1UF

0201

16V

10%

Left I/O (LIO) Connector

SYNC_MASTER=J13_MLB_NON_POR

SYNC_DATE=11/10/2011

USB3_EXTB_RX_RC_N

=PP3V42_G3H_ONEWIRE

USB_CAMERA_N

USB3_EXTB_RX_RC_P

USB3_EXTB_TX_C_N

USB3_EXTB_TX_C_P

USB3_EXTB_RX_P

USB3_EXTB_RX_N

USB3_EXTB_TX_P

USB3_EXTB_TX_N

SPKRAMP_INR_N

AUD_IPHS_SWITCH_EN

=PP3V3_S0_AUDIO

=PP3V3R1V5_S0_AUDIO

AUD_I2C_INT_L

=USB_PWR_EN

SMC_BC_ACOK

=I2C_LIO_SCL

SYS_ONEWIRE

=I2C_LIO_SDA

AUD_GPIO_3

SMC_LID

HDA_RST_L

USB_EXTB_OC_L

=I2C_MIKEY_SCL HDA_SYNC

=I2C_MIKEY_SDA

HDA_SDIN0 HDA_BIT_CLK HDA_SDOUT

USB_EXTB_P USB_EXTB_N

USB_CAMERA_P

AUD_IP_PERIPHERAL_DET

SPKRAMP_INR_P

GND_VOID=TRUE

C4700

1

2

C4710

1

2

C4720

1

2

R4710

12

C4731

12

C4732

12

C4722

12

R4720

12

C4721

12

J4700

1

10 11 12 13 14 15 16

19

2

20 21 22 23 24 25 26 27 28 29

3

30 31 32

35 36 37 38 39

4

40 41 42 43 44 45 46 47 48

49

5

50

51 52

6

78 9

D4711

1

2

D4710

1

2

D4720

1

2

D4721

1

2

051-9277

2.8.0

47 OF 109

40 OF 73

6

68

6 7

6

68

6

68

6

68

6 7

LPC0AD3 LPC0CLK LPC0FRAME*

LPC0AD1 LPC0AD2

AIN08

AIN07 LPC0CLKRUN* LPC0PD*

AIN13

AIN14

PM7/FAN0TACH0

PM6/FAN0PWM0

AIN04

C1-

I2C2SDA

AIN05

AIN09

AIN11

AIN21

AIN23

PK7/FAN0TACH1

AIN15

AIN06

AIN10

AIN20

AIN22

T1CCP1/PJ1

PK5

LPC0AD0

AIN12

PECI0RX PECI0TX

PK6/FAN0PWM1

LPC0RESET*

PQ0/IRQ124

PP6/IRQ122

PN3/FAN0TACH2

I2C0SDA

AIN01

AIN00

PQ1/IRQ125

I2C0SCL

U1TX/PB1

USB0DP

USB0DM

AIN03

AIN02

T0CCP1/PB7

T0CCP0/PB6

PQ2/IRQ126

U1RX/B0

LPC0SCI*

AIN17

AIN16

PN2/FAN0PWM2

WT4CCP1/PH7

AIN18

AIN19

WT4CCP0/PH6

WT3CCP1/PH5

WT5CCP1/PM3

LPC0SERIRQ

PH3/FAN0TACH5

WT3CCP0/PH4

PH2/FAN0PWM5

PP3/IRQ119 PP4/IRQ120

C0-

WT2CCP0/PH0 WT2CCP1/PH1

PQ5/IRQ129

PP7/IRQ123

WT0CCP0/PG4

I2C3SDA

SSI1FSS/PF3

PC5/C1+

U0RX

SSI0RX/PA4

PP5/IRQ121

PQ7/IRQ131

WT0CCP1/PG5

I2C3SCL

SSI1CLK/PF2

PN4/FAN0PWM3

PP1/IRQ117

U0TX

SSI0CLK/PA2 SSI0FSS/PA3

I2C1SCL

PP2/IRQ118

PQ6/IRQ130

I2C4SDA

SSI1RX/PF0

PN7/FAN0TACH4

PP0/IRQ116

SSI0TX/PA5

I2C1SDA

I2C5SDA

PQ3/IRQ127 PQ4/IRQ128

I2C4SCL

I2C2SCL

SSI1TX/PF1

PN6/FAN0PWM4

PN5/FAN0TACH3

I2C5SCL

T3CCP0/PJ4/C2+

T3CCP1/PJ5/C2-

PF4 PF5

T1CCP0/PJ0

T2CCP0/PJ2 T2CCP1/PJ3

C0+

(1 OF 2)

VDDC

VREFA-

SWO/TDO

TDI

RST*

HIB*

WAKE*

XOSC0

VREFA+

VDDA

GNDA

PK4/RTCCLK

GND

NC

OSC0

XOSC1

SWCLK/TCK SWDIO/TMS

OSC1

VBAT

VDD

(2 OF 2)

IN

BI

IN

BI

OUT

IN

OUT

BI

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

NC

OUT

NC

BI

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

BI

IN

OUT

IN

NC

OUT

IN

OUT

IN

OUT

BI

IN

OUT

BI

IN

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

NC FOR STACK BRD

NC FOR ENG PKG

1.2V FOR ENG PKG

(OD)

NC FOR ENG PKG

NC FOR STACK BRD

(OD)

NC FOR ENG PKG

(OD)

NC FOR STACK BRD

(OD)

NOTE:

(OD)

NC FOR ENG PKG

NC FOR STACK BRD

NC FOR ENG PKG

(OD)

NC FOR STACK BRD

those designated as inputs require pull-ups.

pins designed as outputs can be left floating,

(OD)

SMS Interrupt can be active high or low, rename net accordingly.

Unused pins have "SMC_Pxx" names. Unused

If SMS interrupt is not used, pull up to SMC rail.

SMC_VCCIO_CPU_DIV2

CPU_PROCHOT_L

SMC_ADC21

SMC_ADC18

CPU_THRMTRIP_3V3

CPU_CATERR_L

SPI_DESCRIPTOR_OVERRIDE_L

SMC_S5_PWRGD_VIN

=PP3V3_S5_SMC

PP1V2_S5_SMC_VDDC

MIN_LINE_WIDTH=0.25MM MIN_NECK_WIDTH=0.1MM VOLTAGE=1.2V

PM_SYSRST_L

SMBUS_SMC_1_S0_SCL

SMBUS_SMC_0_S0_SCL

LPC_CLK33M_SMC

LPC_AD<2>

SMC_ADC8

SMC_ADC7

SMC_FAN_0_CTL

SMC_ADC4

SMC_ADC9

SMC_ADC11

SMC_ADC15

SMC_ADC6

SMC_ADC10

SMC_ADC12

SMC_ADC1

SMC_ADC3

SMC_ADC2

SMC_ADC16

SMC_ADC19

SMC_BATLOW_L

SMC_THRMTRIP

SPI_SMC_CLK

SMBUS_SMC_4_ASF_SCL

SMBUS_SMC_2_S3_SCL

S5_PWRGD PM_PCH_SYS_PWROK

SMC_TDO

SMC_RESET_L

WIFI_EVENT_L

SMC_TCK SMC_TMS

SMC_CLK32K

SMC_WAKE_L

SMC_DELAYED_PWRGD

SPI_SMC_CS_L

SPI_SMC_MISO

SYS_ONEWIRE

SMC_ADC13

SMC_BIL_BUTTON_L

SMC_T25_EN_L

SMBUS_SMC_4_ASF_SDA

SMC_RUNTIME_SCI_L

LPC_SERIRQ

LPC_AD<3>

SMBUS_SMC_2_S3_SDA

SMBUS_SMC_1_S0_SDA

LPC_PWRDWN_L

PM_CLKRUN_L

LPC_FRAME_L

LPC_AD<1>

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_5_G3_SDA

SMBUS_SMC_5_G3_SCL

SMC_PECI_L

SMC_XTAL

NC_SMC_XOSC1

NC_SMC_HIB_L

SMC_EXTAL

SMC_TDI

MIN_NECK_WIDTH=0.1MM

MIN_LINE_WIDTH=0.25MM

PP3V3_S5_SMC_VDDA

VOLTAGE=3.3V

SMC_ADC22

SMC_ADC20

SMC_ADC17

LPC_AD<0>

SMC_LRESET_L

SMBUS_SMC_3_SCL

SMC_WAKE_SCI_L

SMC_ADC14

SPI_SMC_MOSI

SMC_OOB1_TX_L

SMC_OOB1_RX_L

SMC_ADAPTER_EN

SMC_GFX_OVERTEMP

SMC_DEBUGPRT_EN_L

SMBUS_SMC_3_SDA

SMC_PROCHOT

SMC_DEBUGPRT_RX_L SMC_DEBUGPRT_TX_L SMC_SYS_LED

PP3V3_S5_AVREF_SMC

GND_SMC_AVSS

MEM_EVENT_L

SMC_FAN_0_TACH SMC_FAN_1_CTL SMC_FAN_1_TACH SMC_MPM5_LED_PWR

SMC_SYS_KBDLED

HISIDE_ISENSE_OC

CPU_PECI_R

SMC_MPM5_LED_CHG

PM_DSW_PWRGD

SMC_S4_WAKESRC_EN

SMC_LID

USB_SMC_P

PM_SLP_S5_L

SMC_PM_G2_EN

SMC_GFX_THROTTLE_L

ALL_SYS_PWRGD

BDV_BKL_PWM

SMC_DP_HPD_L

SMC_ONOFF_L

PM_PWRBTN_L

SMC_ADC23

SYS_TDM_ONEWIRE

SMC_ODD_DETECT

USB_SMC_N

SMC_TX_L

SMC_RX_L

PM_SLP_S4_L

PM_SLP_S3_L

G3_POWERON_L

SMC_BC_ACOK

SMS_INT_L

ENET_ASF_GPIO

SMC_PME_S4_DARK_L

SMC_PME_S4_WAKE_L

IR_RX_OUT_RC

SMC_ADC5

SMC_ADC0

SYNC_DATE=10/17/2011

SYNC_MASTER=J13_MLB_NON_POR

SMC

PLACE_NEAR=U4900.D1:1MM

PLACE_NEAR=U4900.D2:1MM

1UF

6.3V 0201

X5R

20%

42

PLACE_NEAR=U4900.D2:1MM

0.01UF

X5R

PLACE_NEAR=U4900.D1:1MM

1.0UF

0201-1

X5R-CERM

20%

1.0UF

0201-1

X5R-CERM

20%

NOSTUFF

20%

X5R-CERM 0201-1

1.0UF

42

68 24

42

8

42

20%

1UF

6.3V X5R 0201

0.1UF

X5R-CERM 0201

0.1UF

X5R-CERM 0201

0.1UF

0201

X5R-CERM

0.1UF

X5R-CERM 0201

0.1UF

X5R-CERM 0201

0.1UF

42

66 10

25 23 17

40

6

42 38

6

42

38

6

66 57 42 10

30-OHM-1.7A

0402

25

62

42

42 37

6

62 42

42

49 42

6

62 17

62 49 37 26 17

62 26 17

42

42 40

6

42

49 42 40

6

49 42

6

42

48

49

42

43 42

6

43 42

6

42

19

62 42 17

25 17

23 17

42

62 52 25 23

42

39

69 42

8

68 42 39

42

42 36 25

17

62

42

71 44

42

71 44

19

43 25 17

6

43 17

6

43 16

6

25

69 43 16

6

69 25

69 43 16

6

69 43 16

6

69 43 16

6

69 43 16

6

X5R-CERM

0.1UF

0201

0.1UF

0201

X5R-CERM

0201

X5R-CERM

0.1UF

0201

0.1UF

X5R-CERM

0201

X5R-CERM

0.1UF

0201

X5R-CERM

0201

0.1UF

X5R-CERM

1M

MF

5% 1/20W

69 42

53 43 42

6

PLACE_NEAR=U4900.A1:4MM

SM

OMIT_TABLE

LM4FSXAH5BB

BGA

OMIT_TABLE

BGA

LM4FSXAH5BB

10V

10V10V10V

10V

10V 10V 10V 10V 10V

10V

10V 10V

201

10%

10% 10% 10% 10% 10%

10%

10% 10%

U4900

E2 E1 F2 F1 B3 A3 B4 A4 B5 A5 B6 A6 C1 C2 B1 B2 G2 G1 H1 H2 B7 A7 B8 A8

K2 K1 L2

E10 D13

M4 N2 N8 M8 L8 K8 N7 M7 N4 N3

B13 A13 C12 D11 H12

G11

D12

F13

C13

F12

H13

L1

C4 C6

L9 K9

J4 J2

B12

C11

A12

H11 L13

G3

D10

L11 N12 N11 M11

M13 L12

M5

J12

J13

L5 D8 K6

D4 E4 F5

N5 N6 K5 M6 L6

M2 M3 L4 N1

L10 K10

M9 N9

F4 F3

C9 B9 A9 C8

D5

C5

L3 M1

F11 E11

E13 E12

K7 L7

K3 K4

J3 H4 H3 G4

H10

U4900

A1 C7

K11

D9 E5 F9 H5 H9 J5 J8 J11

C3 E3

M12

G12

G13

B11

G10 C10

A10 A11 B10

K12

D7 E6 E8 E9

F10

J7 J9

J10

D3

J1 J6

K13

D6

D1

D2

N13

M10

N10

XW4900

12

R4902

1

2

C4906

1

2

C4905

1

2

C4909

1

2

C4908

1

2

C4904

1

2

C4903

1

2

C4907

1

2

L4901

12

C4917

1

2

C4916

1

2

C4915

1

2

C4914

1

2

C4913

1

2

C4901

1

2

C4902

1

2

C4910

1

2

C4911

1

2

C4912

1

2

C4920

1

2

C4921

1

2

051-9277

2.8.0

49 OF 109

41 OF 73

A2

42

7

42

43 42

6

43 42

6

43 42

6

42

43 42

6

42

46 45 42

IN

OUT

BI

IN

REFOUT

MR1*

THRM

GND

RESET*

DELAY

MR2*

VIN

V+

SN0903048

PAD

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

D

GS

D

GS

D

SG

D

SG

BI

OUT

IN

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SMC12 SPI Support

topology of 2 SPI Masters are verified.

SMC12 Eng Pkg Support

Module has 3.3K PU

SMC Crystal Circuit

SMC USB Clock require these crystal values:5,6,8,10,12,16,18,20,24,25 MHz

From SMC

with comparators on Stack Board.

MR1* and MR2* must both be low to cause manual reset.

Mobiles: 3.42V

Desktops: 5V

SMC Reset "Button", Supervisor & AVREF Supply

From/To CPU/PCH

(IPU)

PM_BATLOW_L in PCH.

To SMC

Internal 20K pull-up on

(IPU)

Debug Power "Buttons"

Used on mobiles to support SMC reset via keyboard. NOTE: Internal pull-ups are to VIN, not V+.

Eng Package requires 1.2V ON SMC_ADC23 pin.

BATLOW# Isolation

ADC10 and ADC11 are shared

SMC12 PECI Support

Note:

Series resistors are no stuffed until the

MF

10K

1/20W

MF

100K

1/20W 1/20W

10K

MF MF

100K

1/20W

10K

1/20W

MF

10K

1/20W

MF MF

10K

1/20W

10K

1/20W

MF

1/20W

MF

10K

41 42

19

PLACE_SIDE=BOTTOM

1/10W

0

SILK_PART=PWR_BTN

OMIT

MF-LF 603

10 41 57 66

41

NO STUFF

1/20W

MF

10K

1/20W

MF

1/20W

MF

100K

MF

10K

1/20W

PLACE_SIDE=TOP

1/10W

0

OMIT

MF-LF

603

SILK_PART=PWR_BTN

SILK_PART=SMC_RST

PLACEMENT_NOTE=Place R5001 on BOTTOM side

0

OMIT

1/10W 603

MF-LF

6

41 42 49

6

49

0.01UF

X5R

CERM-X5R

0.47UF

6.3V 402

VREF-3.3V-VDET-3.0V

CRITICAL

DFN

0.01UF

X5R

MF

1/20W

100K

6

41 43 53

17 69

22

1/20W

PLACE_NEAR=U1800.D3:5.1mm

MF

41 69

100K

1/20W

MF

6

41 49

100K

MF

1/20W

41 62 17

100K

MF

1/20W

NOSTUFF

0

MF-LF

402

1/16W

10K

MF

1/20W

MF

1/20W

100K

10K

1/20W

MF

1/20W MF

1K

100K

1/20W

MF

NO STUFF

43 50 69 69

43 50 69 41

0

1/20W

SMC_PACKAGE:ENG

MF

1% MF

1/20W

100K

MF

1/20W

1%

100K

MF

1/20W

10K

6

41 42 49

41

MF

NOSTUFF

1/20W

1.6K

0

1/20W

MF

1/20W MF

330

NO STUFF

10K

1/20W

MF MF

100K

1/20W

VESM

SSM3K15AMFVAPE

CRITICAL

VESM

CRITICAL

SSM3K15AMFVAPE

CRITICAL

SOT563

SSM6N15AFE

CRITICAL

SOT563

100K

1/20W

MF

NO STUFF

33K

1/20W

MF

10 19

66

41

PLACE_NEAR=R2170.2:5mm

43

MF

1/20W

10 19 66

DFN1006-3

CRITICAL

MMBT3904LP-7

41 42

10UF

X5R-CERM

0402-1

20%

1/20W

3.3K

MF

34

1/20W

100K

MF

100K

MF

1/20W

12.000MHZ-30PPM-10PF

3.2X2.5MM-SM

CRITICAL

MF

1/20W

1%

2.49K

SYNC_MASTER=J13_MLB_NON_POR

SMC Support

SYNC_DATE=11/10/2011

PM_CLK32K_SUSCLK_R

SMC_PECI_L

CPU_PECI_R

PM_THRMTRIP_R_L

SMC_ONOFF_L

MEM_EVENT_L CPU_THRMTRIP_3V3

SMC_THRMTRIP

MAKE_BASE=TRUE

SMC_LCDBKLT_ISENSE

MAKE_BASE=TRUE

SMC_3V3S0_ISENSE

NC_SMC_ADC20

MAKE_BASE=TRUE

G3_POWERON_L

SMC_BC_ACOK

SMC_DEBUGPRT_RX_L

SMC_TX_L

SMS_INT_L

SMC_S5_PWRGD_VIN

SMC_TCK

SMC_TDI

SMC_ROMBOOT

SMC_ONOFF_L

SMC_DP_HPD_L

NC_SMC_DP_HPD_L

MAKE_BASE=TRUE

SMC_BC_ACOK

MAKE_BASE=TRUE

=CHGR_ACOK

=TBT_WAKE_L

ENET_ASF_GPIO

SMC_ADC17

SMC_ADC19

SMC_ADC21

SMC_GFX_OVERTEMP

=PP3V3_S0_SMC

=PP3V3_S4_SMC

SMC_PME_S4_DARK_L

MAKE_BASE=TRUE

SMC_GFX_VSENSE

SMC_BIL_BUTTON_L

SMC_TDO

SMC_DEBUGPRT_TX_L

SMC_TMS

SMC_LID

SMC_OOB1_TX_L

SMC_ODD_DETECT

=PPVIN_S5_SMCVREF

=PP3V3_SUS_SMC

=PP3V3_S4_SMC

SMC_ADC6

SMC_ADC3

SMC_ADC15

CPU_PECI

SMC_PECI_L_R

=PPVCCIO_S0_SMC

MAKE_BASE=TRUE

NC_SMC_ADC21

NC_SCM_ADC17

MAKE_BASE=TRUE

SMC_ADC5

SMC_DCIN_ISENSE

MAKE_BASE=TRUE

SMC_ADC14

MAKE_BASE=TRUE

SMC_OTHER_HI_ISENSE

MAKE_BASE=TRUE

SMC_HS_COMPUTING_ISENSE

SMC_ADC8

SMC_ADC4

MAKE_BASE=TRUE

SMC_DCIN_VSENSE

SMC_ADC2

SMC_HDD_ISENSE

MAKE_BASE=TRUE

SMC_ONOFF_L

=PPVCCIO_S0_SMC

PP3V3_WLAN_F

WIFI_EVENT_L

=PP3V3_S5_SMC

=PP3V3_S5_SMCBATLOW

PM_BATLOW_L

SMC_TPAD_RST_L

SMC_PROCHOT

SMC_BATLOW_L

SMC_PBUS_VSENSE

MAKE_BASE=TRUE

SMC_ADC9

SMC_CPU_ISENSE

MAKE_BASE=TRUE

SMC_ADC23

SMBUS_SMC_4_ASF_SCL

MAKE_BASE=TRUE

SMC_CPUVCCIO_ISENSE

NC_SMC_GFX_OVERTEMP

MAKE_BASE=TRUE

SMC_CPU_SA_ISENSE

SMC_ADC23

SMC_ADC12

SMC_ADC10

SMC_ADC11

SMC_RESET_L

SMC_ADC13

SMC_ADC16

SMC_VCCIO_CPU_DIV2

MAKE_BASE=TRUE

NC_HISIDE_ISENSE_OC

MAKE_BASE=TRUE

NC_SMBUS_SMC_4_ASF_SDA

MAKE_BASE=TRUE

NC_SMBUS_SMC_4_ASF_SCL

SMC_MANUAL_RST_L

MIN_LINE_WIDTH=0.4 mm VOLTAGE=3.3V

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.4 mm

GND_SMC_AVSS

MIN_NECK_WIDTH=0.1 mm VOLTAGE=0V

SMC_ADC0

MAKE_BASE=TRUE

SMC_WLAN_ISENSE

SMC_1V5S3_ISENSE

MAKE_BASE=TRUE

SMC_BMON_ISENSE

SMC_ADC7

SMC_GFX_ISENSE

MAKE_BASE=TRUE

PP1V2_S5_SMC_VDDC

PM_THRMTRIP_L

SMC_ADC22

SMC_ADC20

SMC_ADC18

SMC_CLK32K

HISIDE_ISENSE_OC

SMBUS_SMC_4_ASF_SDA

MAKE_BASE=TRUE

NC_SMC_ADC22

NC_SMC_ADC19

MAKE_BASE=TRUE

SMC_ADC23

MAKE_BASE=TRUE

NC_SMC_GFX_THROTTLE_L

NC_ENET_ASF_GPIO

MAKE_BASE=TRUE

NC_SMC_MPM5_LED_PWR

MAKE_BASE=TRUE

SDCONN_STATE_CHANGE_SMC

NC_BDV_BKL_PWM

MAKE_BASE=TRUE

BDV_BKL_PWM

SMC_PME_S4_DARK_L

MAKE_BASE=TRUE

SMC_T25_EN_L

MAKE_BASE=TRUE

SMC_PME_S4_WAKE_L

=BT_WAKE_L

MAKE_BASE=TRUE

NC_SYS_TDM_ONEWIRE

MAKE_BASE=TRUE

NC_SMC_MPM5_LED_CHG

SMC_FAN_1_TACH

SMC_GFX_THROTTLE_L

SMC_FAN_1_CTL

NC_SMC_T25_EN_L

MAKE_BASE=TRUE

SMC_ADC1

SMC_CPU_VSENSE

MAKE_BASE=TRUE

SMC_VCCSA_VSENSE

MAKE_BASE=TRUE

=PP3V3_S5_SMC

SMC_RX_L

SMC_S4_WAKESRC_EN

SMC_ADAPTER_EN

SMC_DELAYED_PWRGD

SMC_THRMTRIP

SMC_XTAL

SMC_EXTAL

SMC_XTAL_R

CPU_PROCHOT_L

PM_THRMTRIP_L_R

CPU_THRMTRIP_3V3

PP3V3_S5_AVREF_SMC

69

SPI_SMC_MOSI SPI_MLB_MOSI

MF

1/20W

15

PLACE_NEAR=U6100.5:1MM

SPI_MLB_CLK

15

1/20W

MF

PLACE_NEAR=U6100.6:1MM

15

SPI_MLB_CS_L

PLACE_NEAR=U6100.1:1MM

69

SPI_SMC_CS_L

1/20W

MF

41

24.9

MF

SPI_SMC_MISO SPI_MLB_MISO

SYS_TDM_ONEWIRE

SMC_MPM5_LED_CHG

SMC_MPM5_LED_PWR

MAKE_BASE=TRUE

NC_SMC_FAN_1_TACH

MAKE_BASE=TRUE

NC_SMC_FAN_1_CTL

1%

1/20W

SPI_SMC_CLK

PLACE_NEAR=U6100.2:1MM

5%

5% 5% 5%

5% 5% 5% 5%

5%

5% 5%

5%

5% 5%

5%

25V NP0-C0G-CERM 0201

12PF

5%

25V NP0-C0G-CERM 0201

12PF

5%

10V

201

201 201 201

201 201 201 201

201

201 201

201

201 201

201

10%

R5070

12

R5071

12

R5073

12

R5074

12

R5077

12

R5078

12

R5079

12

R5080

12

R5085

12

R5015

1

2

R5089

12

R5081

12

R5092

12

R5072

12

R5016

1

2

R5001

1

2

C5001

1

2

C5020

1

2

U5010

4

2

6 7

8

5

9

1

3

C5026

1

2

R5000

1

2

R5012

12

R5090

12

R5082

1

2

R5040

1

2

R5041

12

R5075

12

R5076

12

R5086

12

R5088

1

2

R5068

12

R5099

1

2

R5097

1

2

R5096

1

2

R5093

12

R5053

1

2

R5052

12

R5051

1

2

R5014

12

R5017

12

Q5040

3

1

2

Q5050

3

1

2

Q5059

6

2

1

Q5059

3

5

4

R5067

12

R5066

12

R5034

12

Q5058

1

3

2

C5025

1

2

R5058

12

R5087

12

R5091

12

Y5010

24

13

R5010

12

C5010

1

2

C5011

1

2

R5022

12

R5023

12

R5024

12

R5021

12

051-9277

2.8.0

50 OF 109

42 OF 73

41

41 42

46

45

41

6

40 41 42

39 41 68

6

41 43

41

6

41 43

6

41 43

6

43

6

41 42 49

41

6

40 41 42 45 53

41

7

42

41 42

45

41

6

41 43

39 41 68

6

41 43

6

40 41 49

6

38 41

41

7

42

41

7

42

41

46

41

46

41

45

41

46

7

42

6

37

6

37 41

7

41 42

7

45

41

45

41 42

41

45

41 42

41

41 45 46

41

46

46 41

45

41

41 42

33

41

41 42

41

37

41

45

7

41 42

6

41 43

41 62

17 41 62

25 36 41

41 42

41

OUT

IN

OUT

IN

OUT

IN

OUT

IN

BI

OUT

IN

BI

IN

OUT

BI

IN

OUT

IN

OUT

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

LPC+SPI Connector

998-4235

SPI Bus Series Termination

42 50 69

1/20W

201

5%

MF

16 69

6

41 42

6

41 42

6

41 42

6

41 42

6

42

6

41 42 53

6

41 42

6

19

6

25 69

6

16 41 69

6

16 41 69

6

43

6

16 41 69

6

25 69

6

16 41 69

6

41 42

6

17 25 41

6

16 41

6

43

6

43

6

17 41

6

19 50

6

16 41 69

6

43

LPCPLUS

CRITICAL

M-ST-SM

DF40C-30DP-0.4V

42 50 69

5%

MF

16

42 50 69

PLACE_NEAR=U1800.AD12:5mm

5%

MF

15

69

42 50 69 16 69

SYNC_MASTER=J11_MLB

SYNC_DATE=09/08/2011

LPC+SPI Debug Connector

SMC_TDO TP_SMC_TRST_L TP_SMC_MD1 SMC_TX_L

SMC_TMS

SMC_RX_L

SMC_ROMBOOT

SMC_RESET_L

SMC_TCK

SMC_TDI

LPC_AD<0>

LPC_CLK33M_LPCPLUS

=PP3V3_S5_LPCPLUS

SPI_ALT_MISO

SPI_ALT_CLK

LPC_SERIRQ LPC_PWRDWN_L

SPI_ALT_MOSI

LPC_AD<1> LPC_AD<3>

SPI_MISO

SPI_CLK

SPI_MOSI

SPI_MOSI_R

SPI_ALT_CLK

PM_CLKRUN_L

SPIROM_USE_MLB

LPC_FRAME_L

SPI_ALT_CS_L

=PP5V_S0_LPCPLUS

LPC_AD<2>

SPI_ALT_MISO SPI_ALT_MOSI

LPCPLUS_GPIO LPCPLUS_RESET_L

SPI_CLK_R

PLACE_NEAR=U1800.AB8:5mm

15

1/20W

SPI_CS0_L

PLACE_NEAR=U1800.W8:5mm

16

69

SPI_CS0_R_L

15

SPI_ALT_CS_L

LPCPLUS

43

5% 1/20W MF

LPCPLUS

43

5% 1/20W MF

PLACE_NEAR=J5100.14:5mm PLACE_NEAR=J5100.12:5mm

MF

1/20W

5%

LPCPLUS

43

PLACE_NEAR=J5100.9:5mm

SPI_MLB_CS_L

PLACE_NEAR=R5125.2:5mm

5%

MF

43

SPI_MLB_CLK

43

1/20W

MF

5%

43

1/20W

MF

5%

PLACE_NEAR=R5127.2:5mm

SPI_MLB_MOSI

1/20W

PLACE_NEAR=R5126.2:5mm

SPI_MLB_MISO

MF

1/20W

1%

24.9

LPCPLUS

PLACE_NEAR=U6100.2:5mm

24.9

1%

1/20W

MF

1/20W

201

201 201201201

R5110

12

R5111

12

R5112

12

J5100

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

31

32

33

34

4

5

6

7

8

9

R5125

1

2

R5126

1

2

R5127

1

2

R5120

12

R5121

12

R5122

12

R5123

12

R5128

1

2

051-9277

2.8.0

51 OF 109

43 OF 73

6

6 7

69

6

43

6 7

6

43

6

43

6

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PCH S0 SMBus "0" Connections

Analogix T-con - (Write: 0x7B/0x87 Read: 0x7C/0x88) N Y * Y *

U3600

(Write: 0x72 Read: 0x73)

(* = Multiple options)

Battery Manager - (Write: 0x16 Read: 0x17)

ISL6258 - U7000

(Write: 0x12 Read: 0x13)

EMC1414-A: U5570

U9701

(WRITE: 0x58 READ: 0x59)

LED BACKLIGHT

Left I/O Board

(See Table)

J4700

CPU Temp

U4900

(MASTER)

VRef DACs

U1800

Battery

J6955

U4900

(MASTER)

Battery

U1800

SMC

(See Table)

(MASTER)

U4900

SMC

(MASTER)

U1800

Cougar-Point

U4900

Margin Control

SMC

(MASTER)

XDP Connectors

SMLink 1 is slave port to

Cougar-Point

Battery Charger

SMC

(MASTER)

U3301

(Write: 0x98 Read: 0x99)

U3300

(Write: 0x90 Read: 0x91)

J5700

Trackpad

EMC1704: U5400

(Write: 0x98 Read: 0x99)

Internal DP

(See Table)

J9000

K21 K78

Samsung LGD Samsung LGD AUO

TBT & Inlet Temp

Cougar-Point

(Write: 0x98 Read: 0x99)

(Write: 0x30 Read: 0x31)

TBT

(Write: 0xXXX Read: 0xXXX)

ALS - (write: 0x72 Read: 0x73) Finstack Temp - (Write: 0x92 Read: 0x93)

SMC S0 "1" SMBus Connections

Parade T-con - (0x10-0x1F or 0x30-0x3F) Y N * N *

NOTE: SMC RMT bus remains powered and may be active in S3 state

DVR - (Write: 0x4E Read: 0x4F) Y Y Y Y N

SMC

SMC "0" SMBus S0 Connections

SMC "2" SMBus S3 Connections

SMC "5" SMBus G3H Connections

SMC "3" SMBus S3 Connections

Mikey

U6800

Left I/O Board

J2600 & J2650

(MASTER)

Internal DP

PCH S0 "SMLink 0" Connections

(Write: 0x88 Read: 0x89)

PCH S0 "SMLink 1" Connections

access PCH

201

4.7K

5% 1/20W MFMF

4.7K

201

5%

1/20W

2.0K

1/20W

MF

201

5%

2.0K

MF

5% 1/20W

201

1/20W

1K

201

5%

MF

201

5%

MF

1K

1/20W

201

MF

5% 1/20W

4.7K

201

4.7K

MF

1/20W

5%

201

MF

1/20W

5%

8.2K

201

MF

8.2K

1/20W

5%

1K

MF 201

5% 1/20W1/20W

MF

1K

5%

201

MF

5%

2.0K

1/20W

2.0K

1/20W

5%

MF

201

SYNC_MASTER=J11_MLB

SYNC_DATE=10/04/2011

SMBus Connections

=PP3V3_S0_SMBUS_PCH

MAKE_BASE=TRUE

SMBUS_PCH_CLK

=I2C_CPUTHMSNS_SCL

=I2C_CPUTHMSNS_SDA

=I2C_LIO_SDA

=I2C_LIO_SCL

=SMBUS_CHGR_SCL

=I2C_BKL_1_SDA

=PP3V3_S3_SMBUS_SMC_MGMT

SML_PCH_0_DATA

MAKE_BASE=TRUE

=SMBUS_BATT_SDA

=SMBUS_BATT_SCL

=PP3V42_G3H_SMBUS_SMC_BSA

=PP3V3_S0_SMBUS_PCH

=I2C_VREFDACS_SCL

=SMBUS_CHGR_SDA

=I2C_VREFDACS_SDA

=SMBUS_XDP_SDA

=I2C_PCA9557D_SDA

=I2C_TBT_INLET_THMSNS_SDA

=I2C_TPAD_SDA

=I2C_BKL_1_SCL

=PP3V3_S3_SMBUS_SMC_A_S3

=I2C_TBT_INLET_THMSNS_SCL

=I2C_TPAD_SCL

SMBUS_SMC_2_S3_SCL

MAKE_BASE=TRUE

SMBUS_SMC_2_S3_SDA

MAKE_BASE=TRUE

SMBUS_SMC_3_SCL

MAKE_BASE=TRUE

SMBUS_SMC_3_SDA

MAKE_BASE=TRUE

SMBUS_SMC_5_G3_SDA

SMBUS_SMC_5_G3_SCL

MAKE_BASE=TRUE

=I2C_PCA9557D_SCL

=I2C_TBTRTR_SCL

MAKE_BASE=TRUE

SMBUS_SMC_1_S0_SDA

SMBUS_SMC_1_S0_SCL

MAKE_BASE=TRUE

=PP3V3_S0_SMBUS_SMC_B_S0

=I2C_TCON_SDA

=I2C_TCON_SCL

=I2C_TBTRTR_SDA

=I2C_MIKEY_SCL

=SMBUS_XDP_SCL

MAKE_BASE=TRUE

SMBUS_PCH_DATA

=PP3V3_S0_SMBUS_SMC_0_S0

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SCL

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SDA

=I2C_MIKEY_SDA

SML_PCH_1_CLK

SML_PCH_0_CLK

MAKE_BASE=TRUE

SML_PCH_1_DATA

R5261

1

2

R5260

1

2

R5280

1

2

R5281

1

2

R5270

1

2

R5271

1

2

R5251

1

2

R5250

1

2

R5210

1

2

R5211

1

2

R5201

1

2

R5200

1

2

R5291

1

2

R5290

1

2

051-9277

2.8.0

52 OF 109

44 OF 73

7

44

16 69

47

6

40

6

40

53

65

7

16 69

6

52

6

52

7

44

31

53

31

23

31

46

6

49

65

7

46

6

49

41 71

31

34

41 71

7

63

34

6

40

23

16 69

7

41 71

6

40

16 69

OUT

IN

OUT

S

D

N-CHANNEL

G

D

G

P-CHANNEL

OUT

IN

V+

REFIN+

IN-

OUT

GND

OUT

IN

V+

V-

THRM

V+

V-

THRM

OUT

S

D

N-CHANNEL

G

D

G

P-CHANNEL

OUT

IN

OUT

IN

V-

V+

+

-

V-

V+

+

-

OUT

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

divider when SUS present.

divider when AC present.

Enables DC-In VSense

divider when in S0.

GFX/IG Vcore Voltage Sense / Filter

GFX/IG VCore Load Side Current Sense / Filter

Max VOut: 3.3V at 19.77V Input

DC-In Voltage Sense Enable & Filter

PBUS Voltage Sense Enable & Filter

Sense R is R7510 Sense R is 0.75mOhm

(200V/V)

CPU 1.05V VCCIO Current Sense / Filter

VCCSA Voltage Sense / Filter

RTHEVENIN = 4573 Ohms

CPU VCore Load Side Current Sense / Filter

EDP: 33A TDP :28.05A

Max VOut: 2.73V at 39.934A

Scale: 12.1A / V

Scale: ???A / V

3.3V S0 FET Current Sense / Filter

Gain: 200x

Gain:161.765x

EDP: 8.5A TDP :7.225A

Enables PBUS VSense

RTHEVENIN = 4573 Ohms

Max VOut: 3.3V at 19.77V Input

Scale: 8.24A / V

Max VOut: 3.3V at 8.25A

Sense R is R7640, 2mOhm

Sense R is 1mOhm

Max VOut: ???V at ???A

Gain:???

Max VOut: ???V at ???A

Gain:110.181x

Sense R is R7550

EDP: 5A

Gain:???

Scale: ???A / V

Sense R is 0.75mOhm EDP: 18A TDP: 15.3A

CPU SA Current Sense / Filter

Scale: 2.5A / V

Sense R is R7831

Sense R is 1mOhm

EDP: 6A

Sense R is R7140

CPU Vcore Voltage Sense / Filter

Max VOut: 2.18V at 27.2A

42

0.22UF

0201

6.3V

20% X5R

PLACE_NEAR=U4900.C1:5MM

4.53K

1%

PLACE_NEAR=U4900.C1:5MM

201

MF

1/20W

62

1%

MF

201

100K

1/20W

100K

1%

1/20W

MF

201

42

20%

0201

X5R

6.3V

0.22UF

PLACE_NEAR=U4900.A3:5MM

27.4K

1/20W

MF

201

1%

PLACE_NEAR=U4900.A3:5MM

201

5.49K

1% MF

1/20W

NTUD3169CZ

SOT-963

42

1/20W

201

MF

4.53K

1%

VCCIOISNS_ENG

PLACE_NEAR=U4900.A6:5MM

VCCIOISNS_ENG

6.3V 0201

20% X5R

0.22UF

PLACE_NEAR=U4900.A6:5MM

6.3V X5R

0.1UF

10%

201

VCCIOISNS_ENG

59 72

SC70

VCCIOISNS_ENG

CRITICAL

INA210

PLACE_NEAR=R7640.3:5MM

PLACE_NEAR=R7640.4:5MM

PLACE_NEAR=U4900.E1:5MM

1%

4.53K

MF

1/20W

201

42

PLACE_NEAR=U4900.E1:5MM

PLACE_NEAR=U4900.M11:5MM

0.22UF

6.3V

20% X5R

0201

PLACE_NEAR=U4900.H1:5MM

PLACE_NEAR=U4900.M13:5MM

0201

6.3V X5R

20%

0.22UF

PLACE_NEAR=U5340.8:3MM

10% X5R

6.3V 201

0.1UF

PLACE_NEAR=U4900.H1:5MM

4.53K

201

MF

1/20W

1%

58 72

57 58 72

58 72

CRITICAL

OPA2333

DFN

CRITICAL

OPA2333

DFN

42

1%

MF

201

1/20W

PLACE_NEAR=U4900.F1:5MM

27.4K

20%

0201

0.22UF

6.3V X5R

PLACE_NEAR=U4900.F1:5MM

1%

MF

1/20W

5.49K

201

PLACE_NEAR=U4900.F1:5MM

100K

1%

MF

1/20W

201

NTUD3169CZ

SOT-963

MF

1%

201

1/20W

100K

42

20%

0.22UF

X5R

6.3V 0201

PLACE_NEAR=U4900.C2:5MM

201

1/20W

MF

1%

4.53K

PLACE_NEAR=U4900.C2:5MM

0.1UF

10%

PLACE_NEAR=U5370.5:3MM

X5R 201

6.3V

54 72

42

0.22UF

PLACE_NEAR=U4900.B1:5MM

20% X5R

6.3V 0201

PLACE_NEAR=U4900.B1:5MM

MF

201

1%

1/20W

4.53K

61 72

SC70-5

OPA333DCKG4

CRITICAL

SC70-5

OPA333DCKG4

PLACE_NEAR=U5380.5:3MM

0.1UF

201

X5R

6.3V

10%

42

1%

PLACE_NEAR=U4900.F2:5MM

201

4.53K

MF

1/20W

0.22UF

PLACE_NEAR=U4900.F2:5MM

20%

6.3V X5R 0201

SM

PLACE_NEAR=R7140.2:5 MM

0201

1/20W

4.42K

0.1%

MF

PLACE_NEAR=R7510.3:5MM

MF

0201

1/20W

PLACE_NEAR=R7510.4:5MM

4.42K

0.1%

PLACE_NEAR=R7550.3:5MM

0201

MF

1/20W

0.1%

4.42K

PLACE_NEAR=R7550.4:5MM

MF

0201

1/20W

4.42K

0.1%

0201

487K

0.1%

MF

1/20W

MF

715K

0.1%

1/20W

0201

SIGNAL_MODEL=EMPTY

0201

0.1%

MF

487K

1/20W

SIGNAL_MODEL=EMPTY

715K

MF

1/20W

0.1%

0201

PLACE_NEAR=R7140.3:5MM

1.82K

0201

MF

0.1%

1/20W

PLACE_NEAR=R7140.4:5MM

0201

1.82K

0.1%

1/20W

MF

PLACE_NEAR=R7831.3:5MM

1.82K

0201

0.1%

1/20W

MF

PLACE_NEAR=R7831.4:5MM

0201

1.82K

0.1%

1/20W

MF

MF 0201

1/20W

0.1%

1.00M

0201

SIGNAL_MODEL=EMPTY

1.00M

1/20W

MF

0.1%

0201

SIGNAL_MODEL=EMPTY

1.00M

1/20W

MF

0.1%

1.00M

0201

MF

1/20W

0.1%

NOSTUFF

201

0

5%

MF

1/20W

42 53

62

201

1/20W

MF

5%

0

SM

PLACE_NEAR=R7550.2:5 MM

42

4.53K

1/20W

201

MF

1%

PLACE_NEAR=U4900.E2:5MM

0.22UF

20%

6.3V X5R 0201

PLACE_NEAR=U4900.E2:5MM

PLACE_NEAR=R7510.2:5 MM

SM

SYNC_DATE=12/02/2011

SYNC_MASTER=J11_MLB

Voltage & Load Side Current Sensing

DCINVSENS_EN

PM_SUS_EN

=PPDCIN_S5_VSENSE

PDCINVSENS_EN_L_DIV

=CHGR_ACOK

DCIN_S5_VSENSE

CPUIMVP_ISUM_IOUT

CPUIMVP_ISUM_R_N

CPUIMVP_ISUM_R_P

CPUIMVP_ISUMG_R_P

CPUIMVP_ISUMG_IOUT

CPUIMVP_ISUMG_R_N

GND_SMC_AVSS

SMC_VCCSA_VSENSE

=PP3V3_S0_SAISNS

VCCSAISNS_R_N

VCCSAISNS_R_P

SMC_CPUVCCIO_ISENSE

CPUVSENSE_IN

DCINVSENS_EN_L

SMC_DCIN_VSENSE

GND_SMC_AVSS

=PBUSVSENS_EN

PBUSVSENS_EN_L

PBUS_S0_VSENSE

GND_SMC_AVSS

=PPBUS_S0_VSENSE

SMC_PBUS_VSENSE

GFXVSENSE_IN

SMC_GFX_VSENSE

GND_SMC_AVSS

SMC_CPU_SA_ISENSE

SMC_GFX_ISENSE

GND_SMC_AVSS

CPUVCCIOS0_CS_N

CPUVCCIOS0_CS_P

GND_SMC_AVSS

CPUIMVP_ISNS1_N

CPUIMVP_ISNS1G_N

=PPGFXVCORE_S0_VSENSE

SMC_3V3S0_ISENSE

=PP3V3_S0_IMVPISNS

CPUIMVP_ISNS1_P

=PPCPUVCORE_S0_VSENSE

=PP3V3_S0_3V3S0ISNS

GND_SMC_AVSS

=PP3V3_S0_CPUVCCIOISNS

ISNS_3V3S0_P

ISNS_3V3S0_N

ISENSE_3V3S0_IOUT

ISNS_3V3S0_R_N

ISNS_3V3S0_R_P

CPUVCCIO_IOUT

CPUIMVP_ISNS1G_P

ISENSE_SA_IOUT

PBUSVSENS_EN_L_DIV

VCCSAS0_CS_N

VCCSAS0_CS_P

=PPVCCSA_S0_VSENSE

VCCSAVSENSE_IN

SMC_CPU_VSENSE

SMC_CPU_ISENSE

C5330

1

2

R5330

12

XW5330

12

R5320

12

C5320

1

2

XW5320

12

R5302

1

2

R5301

1

2

C5304

1

2

R5303

1

2

R5304

1

2

Q5300

6

3

2

5

1

4

R5361

12

C5361

1

2

C5360

1

2

U5360

2

5

4

6

1

3

R5341

12

C5341

1

2

C5351

1

2

C5340

1

2

R5351

12

U5340

3

2

1

9

4

8

U5340

5

6

7

9

4

8

R5313

1

2

C5314

1

2

R5314

1

2

R5312

1

2

Q5310

6

3

2

5

1

4

R5311

1

2

C5371

1

2

R5371

12

C5370

1

2

C5381

1

2

R5381

12

U5370

1

3

4

2

5

U5380

1

3

4

2

5

C5380

1

2

R5340

12

C5350

1

2

XW5340

12

R5342

12

R5343

12

R5352

12

R5353

12

R5344

1

2

R5355

12

R5345

12

R5354

1

2

R5372

12

R5373

12

R5382

12

R5383

12

R5374

1

2

R5375

12

R5385

12

R5384

1

2

R5315

1

2

R5316

1

2

051-9277

2.8.0

53 OF 109

45 OF 73

72

41 42 45 46

72

41 42 45 46

7

41 42 45 46

7

41 42 45 46

7

72

7

OUT

IN

OUT

IN

V+

REFIN+

IN-

OUT

GND

V+

REFIN+

IN-

OUT

GND

V+

REFIN+

IN-

OUT

GND

IN

OUT

IN

OUT

IN-

IN+ REF

V+

GND

BI

OUT

IN

OUT

ALERT*

THERM*/ADDR

DP1

SMCLK

SMDATA

VDD

DN1

DP2/DN3

DN2/DP3

GND

IN

V+

REFIN+

IN-

OUT

GND

V+

REFIN+

IN-

OUT

GND

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DDR3 1V5R1V35 Current Sense / Filter

AirPort Current Sense / Filter

GAIN: 200X

(200V/V)

Scale: 0.25A / V MAX VOUT: 3V AT 0.825A

PLACEMENT_NOTEs:

SCALE: 5A / V

Max Vdiff: 15 mV

Max Vdiff: 31 mV

TBT/Inlet Temp Sensor

Sense R is R4052, 20mOhm

Sense R is R7350, 1mOhm

OTHER High Side Current Sense / Filter

DC-IN (AMON) Current Sense Filter

EDP Current: 15.5 A

Sense R is R5430, 5mOhm

Read Address: 0x99

MAX VOUT: 3.1V at 16.5A

Sense R is R5400, 2mOhm

Max Vdiff: 31 mV

SCALE: 0.667A / V MAX VOUT: 3.3V AT 2.2A

(For R and C)

Max VOut: 1.4V at 8.25A

(500V/V)

MAX VOUT: 3.3V AT 0.66A

SCALE: 0.2A / V

Sense R is R0910, 10mOhm

GAIN: 500X

ISL6259 Gain: 20x

DC-In AMON

Scale: 2.5A / V

EDP Current: 3.5A

Sense R is R7020, 20mOhm

(500V/V)

PLACEMENT_NOTEs:

(For R and C)

PLACEMENT_NOTEs:

EDP Current: 12 A

PLACEMENT_NOTEs:

MAX VOUT: 2.4V AT 16.5A

Gain: 200x

Max Vdiff: 7.0 mV

EDP Current: 0.67 A Max Vdiff: 6.7 mV

(For R and C)

EDP Current: 0.750 A

(For R and C)

EDP Current: 2.36A

Sense R is R4599, 3mOhm

GAIN: 500X

(100V/V)

PLACEMENT_NOTEs:

(For R and C)

PLACEMENT_NOTEs:

GAIN: 50X

MAX VOUT: 3.1V at 16.5A

GAIN: 100X

EDP Current: 15.5 A

SCALE: 5A/ V

Charger BMON (Production) Solution

EDP Current: 310A

ISL6259 Gain: 36x

Max VOut: 3.3V at 9.167A

Scale: 2.78A / V

From charger

CHARGER BMON High Side (BATTERY DISCHAEGE) Current Sense, MUX & Filter

LCD Backlight Driver Input Current Sense / Filter

Write Address: 0x98

COMPUTING High Side Current Sense / Filter

(For R and C)

SCALE: 5A/ V

Max Vdiff: 24 mV

HDD Current Sense / Filter

(50V/V)

42

PLACE_NEAR=U4900.B3:5MM

0.22UF

20%

6.3V X5R 0201

PLACE_NEAR=U4900.B3:5MM

4.53K

MF

1%

1/20W

53

42

PLACE_NEAR=U4900.B6:5mm

Place close to SMC

X5R

20%

6.3V

0.22UF

0201

PLACE_NEAR=U4900.B6:5mm

4.53K

1%

Place close to SMC

MF

1/20W

0.1UF

6.3V X5R

56 72

PLACE_NEAR=U4900.B2:5mm

Place close to SMC

0.22UF

X5R

20%

6.3V

AIRPORTISNS_ENG

0201

PLACE_NEAR=U4900.B2:5mm

Place close to SMC

1%

1/20W

MF

4.53K

AIRPORTISNS_ENG

PLACE_NEAR=U4900.B4:5mm

HDDISNS_ENG

Place close to SMC

6.3V

20%

0.22UF

X5R 0201

PLACE_NEAR=U4900.B4:5mm

1/20W

HDDISNS_ENG

Place close to SMC

1%

4.53K

MF

X5R

0.1UF

6.3V

AIRPORTISNS_ENG

INA210

SC70

HDDISNS_ENG

INA211

SC70

PLACE_NEAR=U4900.G2:5mm

LCDBKLTISNS_ENG

6.3V

0.22UF

20%

X5R 0201

Place close to SMC

PLACE_NEAR=U4900.G2:5mm

4.53K

1%

1/20W

MF

LCDBKLTISNS_ENG

6.3V X5R

0.1UF

SC70

INA211

LCDBKLTISNS_ENG

37 72

38 72

8

72

8

72

PLACE_NEAR=U4900.A4:5MM

1/20W

MF

1%

300K

42

PLACE_NEAR=U4900.B5:5mm

0201

Place close to SMC

6.3V

20%

X5R

0.22UF

PLACE_NEAR=U4900.B5:5mm

MF

Place close to SMC

1/20W

4.53K

1%

X5R

6.3V

0.1UF

8

72

8

72

SC70

INA214

X5R

6.3V

HDDISNS_ENG

0.1UF

5% 1/20W MF

10K10K

5%

1/20W

MF

44

6.3V X5R

0.1UF

MF

5%

1/20W

47

PLACE_NEAR=U5410.3:5mm

PLACE_NEAR=U5410.2:5mm

0201

2200PF

X7R-CERM

SIGNAL_MODEL=EMPTY

47 72

PLACE_NEAR=U5410.5:5mm

PLACE_NEAR=U5410.4:5mm

SIGNAL_MODEL=EMPTY

X7R-CERM

0201

2200PF

47

42

Place close to SMC

PLACE_NEAR=U4900.A5:5mm

0.22UF

0201

X5R

20%

6.3V

PLACE_NEAR=U4900.A5:5mm

1/20W

1%

MF

4.53K

Place close to SMC

6.3V X5R

0.1UF

MF

1%

CRITICAL

1W

0.005

0612

7

EMC1414-1-AIZL

CRITICAL

MSOP

53

INA210

SC70

CRITICAL

SC70

INA213

High Side Current Sensing

SYNC_MASTER=J13_MLB_NON_POR

SYNC_DATE=10/17/2011

=PP3V3_S3_1V5S3ISNS

ISNS_1V5_S3_P

ISNS_1V5_S3_N

ISNS_1V5S3_IOUT

ISNS_P5VWLAN_IOUT

=PP3V3_S0_HDDISNS

=TBTTHMSNS_D2_P

=TBTTHMSNS_D2_N

SMC_1V5S3_ISENSE

ISNS_HS_COMPUTING_P

INLET_THMSNS_D1_N

SMC_DCIN_ISENSE

TBT_INLET_THM_L

=PP3V3_S0_HS_COMPUTING_ISNS

GND_SMC_AVSS

TBT_INLET_ALERT_L

=I2C_TBT_INLET_THMSNS_SDA

ISNS_SSD_N

ISNS_SSD_P

GND_SMC_AVSS

ISNS_P5VHDD_IOUT

ISNS_AIRPORT_P

GND_SMC_AVSS

SMC_LCDBKLT_ISENSE

SMC_HDD_ISENSE

ISNS_LCDBKLT_P

ISNS_LCDBKLT_N

GND_SMC_AVSS

SMC_WLAN_ISENSE

ISNS_LCDBKLT_IOUT

=PP3V3_S0_BKLTISNS

CHGR_AMON

ISNS_AIRPORT_N

GND_SMC_AVSS

=PP3V3_S3_WLANISNS

GND_SMC_AVSS

SMC_HS_COMPUTING_ISENSE

SMC_OTHER_HI_ISENSE

=PPVIN_S5_HS_OTHER_ISNS_R

ISNS_HS_COMPUTING_IOUT

=PP3V3_S0_HS_COMPUTING_ISNS

ISNS_HS_COMPUTING_N

=I2C_TBT_INLET_THMSNS_SCL

INLET_THMSNS_D1_P

GND_SMC_AVSS

SMC_BMON_ISENSE

CHGR_BMON

=PPVIN_S5_HS_OTHER_ISNS

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

PP3V3_S0_HS_COMPUTING_ISNS_R

GND_SMC_AVSS

HS_OTHER_IOUT

ISNS_HS_OTHER_N

ISNS_HS_OTHER_P

=PP3V3_S0_HS_OTHER_ISNS

10V

201

201201

201

10%

PLACE_NEAR=U4900.A4:5MM

10V X7R-CERM 0201

3300PF

10%

C5431

1

2

R5431

12

C5465

1

2

R5465

12

C5460

1

2

C5475

1

2

R5475

12

C5485

1

2

R5485

12

C5470

1

2

U5470

2

5

4

6

1

3

U5480

2

5

4

6

1

3

C5495

1

2

R5495

12

C5490

1

2

U5490

2

5

4

6

1

3

R5422

12

C5422

1

2

C5455

1

2

R5455

12

C5450

1

2

U5450

2

5

4

6

1

3

C5480

1

2

R5412

1

2

R5411

1

2

C5410

1

2

R5410

12

C5411

1

2

C5412

1

2

C5433

1

2

R5433

12

C5430

1

2

R5430

12

34

U5410

83

5

2

4

6

10

9

7

1

U5460

2

5

4

6

1

3

U5430

2

5

4

6

1

3

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7

46

41 42 45 46

7

41 42 45 46

7

41 42 45 46

7

46

41 42 45 46

72

7

BI

THRM_PAD

DN2/DP3

DP2/DN3

VDD

SMDATA

SMCLK

GND

DN1

DP1

THERM*/ADDR

ALERT*

BI

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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D

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C

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NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Place Q5510 next to DDR/5V/3.3V supply on TOP side

Placement note:

Detect DDR/5V/3.3V Proximity Temperature

TBT,MLB Bottom & Inlet Proximity Sensors

Placement note:

To connect Proximity Sensor, Stuff R5540 & R5541, No Stuff R5550,R5551

TBT Die

Write Address: 0x98

Detect TBT Die Temperature

Placement note:

Place Q5520 close to TBT on TOP side

Place Q5530 between near rear vent on bottom side

Use GND pin B1 on U3600 for N leg

To connect Die Sensor, Stuff R5550 & R5551, No stuff R5540 & R5541

Placement note:

Place U5510 under CPU

Placement note:

Read Address: 0x99

CPU Proximity Sensor

Detect CPU Die Temperature

Replacing caps with 100K PD on ISENSE SMC inputs

Place Q5540 on MLB bottom side opposite U5400

10K

MF

1/20W

5%

MF

1/20W

5%

10K

PLACE_NEAR=U5510.2:5mm PLACE_NEAR=U5510.3:5mm

SIGNAL_MODEL=EMPTY

X7R-CERM

2200PF

0201

9

72

9

72

DFN

EMC1413

CRITICAL

34

SM

PLACE_NEAR=U3600.B1:2mm

5%

0

MF

1/20W

5%

MF

1/20W

0

1/20W

5%

MF

0

NO STUFF

1/20W

5%

MF

0

DFN1006H4-3

BC846BLP

DFN1006H4-3

BC846BLP

DFN1006H4-3

BC846BLP

DFN1006H4-3

44

6.3V X5R

0.1UF

47

5%

MF

1/20W

X7R-CERM

SIGNAL_MODEL=EMPTY

PLACE_NEAR=U5510.4:5mm PLACE_NEAR=U5510.5:5mm

0201

2200PF

Thermal Sensors

SYNC_DATE=08/03/2011

SYNC_MASTER=J11_MLB

AIRPORTISNS_PROD

RES,MF,1/20W,100K OHM,5,0201,SMD

C5475

1

117S0008

RES,MF,1/20W,100K OHM,5,0201,SMD

1

VCCIOISNS_PROD

C5361

C5485

HDDISNS_PROD

1

RES,MF,1/20W,100K OHM,5,0201,SMD

117S0008

C5495

LCDBKLTISNS_PROD

117S0008

1

RES,MF,1/20W,100K OHM,5,0201,SMD

=MLBBOT_THMSNS_D3_N

=MLBBOT_THMSNS_D3_P

TBTTHMSNS_D2_R_P

TBTTHMSNS_D2_R_N

INLET_THMSNS_D1_P

INLET_THMSNS_D1_N

CPUTHMSNS_D2_P

CPUTHMSNS_D2_N

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.25 mm

PP3V3_S0_CPUTHMSNS_R

MIN_NECK_WIDTH=0.25 mm

=TBTTHMSNS_D2_P

=I2C_CPUTHMSNS_SCL

TBT_THERMD_N

=TBTTHMSNS_D2_N

TBT_THERMD_P

MAKE_BASE=TRUE

=TBTTHMSNS_D2_N

TBT_MLBBOT_THMSNS_N

MAKE_BASE=TRUE

CPUTHMSNS_THM_L

CPUTHMSNS_ALERT_L

=I2C_CPUTHMSNS_SDA

CPU_THERMD_P

CPU_THERMD_N

=PP3V3_S0_CPUTHMSNS

=TBTTHMSNS_D2_P

TP_TBT_THERM_DP

TBT_MLBBOT_THMSNS_P

MAKE_BASE=TRUE

=MLBBOT_THMSNS_D3_P

=MLBBOT_THMSNS_D3_N

=TBTTHMSNS_D2_P

=TBTTHMSNS_D2_N

10V

201201

201

10%

C5510

1

2

R5510

12

C5512

1

2

R5512

1

2

R5511

1

2

C5511

1

2

U5510

83

5

2

4

6

10

9

7

11

1

XW5520

12

R5540

12

R5541

12

R5550

12

R5551

12

Q5510

1

3

2

Q5530

1

3

2

Q5520

1

3

2

Q5540

1

3

2

051-9277

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47

72

46 72

72

46 47

72

46 47

72

46 47

72

7

46 47

72

47

46 47

D

GS

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

NC

GND

MOTOR CONTROL

TACH

5V DC

NC

FAN CONNECTOR

518S0793

47K

201

MF

1/20W

5%

201

47K

1/20W

5% MF

100K

MF

1/20W

5%

201

SOD-VESM-HF

SSM3K15FV

FF14A-4C-R11DL-B-3H

F-RT-SM

CRITICAL

SYNC_MASTER=K21_MLB

SYNC_DATE=07/28/2011

Fan

FAN_RT_PWM

FAN_RT_TACH

SMC_FAN_0_CTL

SMC_FAN_0_TACH

=PP3V3_S0_FAN

=PP5V_S0_FAN

R5665

12

R5660

1

2

R5661

1

2

Q5660

3

1

2

J5600

5

6

1

2

3

4

051-9277

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56 OF 109

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6

41

7

6 7

IN

BI

VIN

SW

OUT

FB

EN

NC

THRM

GND

PAD

NC

VCC

GND

SELOE*

D+ D-

Y+ Y-

M+ M-

BI

OUT

IN

OUT

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

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D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Keyboard Backlight Driver & Detection

Keyboard Backlight Connector

IPD Flex Connector

grounded when KB BL flex connected.

SEL=0 Choose pull up/down SEL=1 Choose USB

518S0794

tristate and read SMC_SYS_KBDLED:

518S0793

If HIGH, keyboard backlight not present

If LOW, keyboard backlight present

R5853 always stuffed, R5854 only

on keyboard backlight flex

J5815 pin 1 is grounded

To detect Keyboard backlight, SMC will

MF

10K

5%

1/20W

MF

10K

5%

17 26 37 41 62

1/20W05% MF

24 68

FF14A-4C-R11DL-B-3H

F-RT-SM

CRITICAL

NOSTUFF

16V

0201

MLF

MIC2292

CRITICAL

50V

0603-1

X5R-CERM

0.22UF

0603-1

X5R-CERM

50V

0.22UF

X5R-CERM

0201

0.1UF

16V

TQFN

PI3USB102ZLE

CRITICAL

PLACE_NEAR=J5700.13:1.5MM

0.1UF

6.3V X5R

6

44 49

FF14A-14C-R11DL-B-3H

F-RT-SM

CRITICAL

6.3V

0.1UF

X5R

PLACE_NEAR=J5700.1:1.5MM

6

44 49

6

41 42 49

6

40 41 42 49

6

42 49

PLACE_NEAR=J5700.10:1.5MM

0402-LF

FERR-120-OHM-1.5A

1/20W

5% MF

0

6

41 42

402

4.7

5% 1/16W MF-LF

10UH-0.58A-0.35OHM

1098AS-SM

CRITICAL

BYPASS=U5750.1:2:2 MM

402-1

X5R

1UF

41

0201

0.1UF

X5R-CERM

16V

SYNC_DATE=11/10/2011

IPD / KBD Backlight

SYNC_MASTER=J13_MLB_NON_POR

=I2C_TPAD_SDA

SMC_TPAD_RST_L

KBDLED_SW

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.3 MM

SWITCH_NODE=TRUE

SMC_SYS_KBDLED

SMC_ONOFF_L

SMC_LID

SMC_ONOFF_L

=I2C_TPAD_SCL

SMC_PME_S4_WAKE_L

SMC_LID

=I2C_TPAD_SDA =I2C_TPAD_SCL

=PP3V3_S4_TPAD

PP5V_TPAD_FILT

VOLTAGE=5V

MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.20mm

VOLTAGE=3.3V

=PP5V_S5_TPAD

MIN_NECK_WIDTH=0.2 MM

KBDLED_ANODE

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.2 MM MIN_LINE_WIDTH=0.25 MM

KBDLED_FB

=PP5V_S0_KBDLED

PM_SLP_S4_L

USB_TPAD_M_N

USB_TPAD_M_P

USB_TPAD_N

USB_TPAD_P

USB_TPAD_MUX_SEL

=PP3V3_S4_TPAD

USB_TPAD_R_N

USB_TPAD_R_P

PLACE_NEAR=J5700.10:1.5MM

0.1UF

X5R-CERM

=PP3V42_G3H_TPAD

PP3V3_TPAD_CONN

100PF

5%

25V

NP0-CERM

PLACE_NEAR=J5700.11:1.5MM

NP0-CERM

25V

5%

100PF

5%

25V

NP0-CERM

100PF

5%

25V

NP0-CERM

SMC_TPAD_RST_L

0201

PLACE_NEAR=J5700.14:1.5MM

PLACE_NEAR=J5700.12:1.5MM

PLACE_NEAR=J5700.9:1.5mm

PLACE_NEAR=J5700.8:1.5MM

0201

100PF

5%

25V

NP0-CERM

10V

201

10%

10%10%

10%

C5700

1

2

C5720

1

2

J5700

15

16

1

10

11

12

13

14

2

3

4

5

6

7

8

9

L5720

12

R5730

12

R5755

1

2

L5750

12

C5750

1

2

C5701

1

2

R5703

1

2

R5702

1

2

R5704

12

J5715

5

6

1

2

3

4

C5704

1

2

U5750

3

6

4

8

1

7

9

2

C5756

1

2

C5755

1

2

C5710

1

2

U5700

6

7

3

4

5

8

10

9

2

1

C5732

1

2

C5733

1

2

C5734

1

2

C5735

1

2

C5736

1

2

57 OF 109

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051-9277

49 OF 73

5

6 7

6

44 49

6

40 41 42 49

6

41 42 49

6

44 49

7

49

6

7

6 6

7

68

7

49

6

42 49

OUT

IN

IN IN

IN

RST*/HOLD*

CE* WP*

SCK

VSS

THRM_PAD

SI/SIO0

SO/SOI1

VDD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

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NOTICE OF PROPRIETARY PROPERTY:

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A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

High Speed CLK Frequency - 50MHz for fast read dual I/O

DUAL I/O MODE (MODE 0 & 3) SUPPORTED

ROM will ignore SPI cycles.

NOTE: If HOLD* is asserted

=PP3V3_SUS_ROM

SPI_MLB_CLK

SPI_MLB_CS_L SPI_WP_L

SPI_MLB_MISO

SPIROM_USE_MLB

SPI_MLB_MOSI

SPI ROM

SYNC_MASTER=K21_MLB

SYNC_DATE=07/28/2011

X5R-CERM

10%

0.1UF

16V

0201

SST25VF064C

OMIT_TABLE

64MBIT

WSON

CRITICAL

43 19

6

69 43 42 69 43 42

69 43 42

3.3K

5%

201

1/20W MF

R6101

1

2

U6100

1

7

6

5

2

984

3

C6100

1

2

051-9277

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61 OF 109

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7

IN

IN-

IN+

OUT+ OUT-

GAINSHDN*

PVDD

NC

PGND

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

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NOTICE OF PROPRIETARY PROPERTY:

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D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.50MM, MIN_NECK_WIDTH=0.25MM

6DB

SPEAKER LOWPASS

GAIN

APN:353S2888

80 HZ < FC < 132 HZ

SPEAKER AMPLIFIERS

SPKRAMP_ROUT_N

MIN_LINE_WIDTH=0.30 mm

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 mm

SPKRAMP_ROUT_P

SPKRAMP_INR_N

SPKRAMP_INR_P

AUD_GPIO_3

R_AMP_GAIN

R_SPKRAMP_SHDN

MAX98300_R_P

=PP5V_S3_AUDIO_AMP

MAX98300_R_N

PP5V_S3_U6210

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.25 mm

VOLTAGE=5V

SYNC_MASTER=J11_MLB

SYNC_DATE=09/30/2011

AUDI0: SPEAKER AMP

CRITICAL

0201

X5R-CERM

16V

10%

0.1UF

0201

16V

10%

0.1UF

CRITICAL

X5R-CERM

0

5%

1/20W

MF

201

100K

MF

5%

201

NOSTUFF

1/20W

5%

201

MF

100K

1/20W MF

5%

201

100K

CRITICAL

WLP

MAX98300

72 40

6

40

6

5%

201

MF

0

1/20W

20%

6.3V POLY-TANT

47UF

2012-LLP

CRITICAL

6.3V

10%

X5R

0.1UF

201

72 40

6

C6207

1

2

C6201

1

2

R6210

12

U6210

C3

B3

A3

C1

B1

A2

A1

C2

R6212

1

2

R6211

1

2

R6213

1

2

R6214

12

C6210

12

C6211

12

051-9277

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62 OF 109

51 OF 73

B2

72 52

6

72 52

6

72

7

72

IN

BI

D

GS

IN

NC

SW

BOOST

VIN

BIAS

SHDN*

GND

NC

FB

PAD

THRM

G

D

S

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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D

87 6 5 4 3

C

B

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NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

5.1V Zener

Supply needs to guarantee 3.31V delivered to SMC VRef generator

3.425V "G3Hot" Supply

<Rb>

60MA MAX OUTPUT

Vout = 3.425V

(Switcher limit)

Battery Connector

K16-Specific

Vout = 1.25V * (1 + Ra / Rb)

<Ra>

Debug LEDs

(For development only)

Right Speaker Connector

518S0519

518S0540

518S0508

MLB to LIO Power Cable Connector

10%

201

X7R

10V

402

50V

16V

6

44

SC-75

CRITICAL

MF

1/20W

5%

10K

1UF

X5R

M-RT-SM

CRITICAL

M-RT-SM

WTB-PWR-M82

CRITICAL

MF-LF

1/16W

5%

1K

S3_S0_LEDS3_S0_LED

1/20W

MF

5%

1K

S3_S0_LED

SSM3K15FV

S3_S0_LED

SOD-VESM-HF

2.0X1.25MM-SM

GREEN-3.6MCD

23

M-RT-SM

78171-0002

CRITICAL

6

51 72

6

51

CRITICAL

DP418C-SM

CERM

0.22UF

BAT30CWFILM

SOT-323

CRITICAL

805

5%

MF-LF

1/8W

4.7

1/8W

5%

805

MF-LF

10

1%

348K

1/20W

MF

1/20W

MF

200K

1%

DFN

CRITICAL

LT3470A

MF

603-1

0.1UF

0201

CRITICAL

1UF

25V X5R

1UF

25V X5R

CRITICAL

5.6UF

20%

POLY-TANT CASE-B2-SM

25V

CRITICAL

0402-1

X5R-CERM

20%

10UF

0402-1

X5R-CERM

20%

10UF

X5R

35V

1UF

CRITICAL

1UF

35V

603

DC-In & Battery Connectors

SYNC_DATE=11/10/2011

=PP18V5_DCIN_CONN

=PP5V_S3_LIO_CONN

MIN_NECK_WIDTH=0.2 mm VOLTAGE=18.5V

PPVIN_G3H_P3V42G3H

MIN_LINE_WIDTH=0.4 mm

SPKRAMP_ROUT_P

=SMBUS_BATT_SCL

PPBUS_G3H

P3V42G3H_BOOST

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

PPVBAT_G3H_CONN

SYS_DETECT_L

=SMBUS_BATT_SDA

SPKRAMP_ROUT_N

DBGLED_S3

DBGLED_S0

DBGLED_S0_D

DIDT=TRUE

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=18.5V

ALL_SYS_PWRGD

VOLTAGE=18.5V

PPBUS_G3H_R

=PP3V42_G3H_REG

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

41

CRITICAL

MIN_NECK_WIDTH=0.2 mm

=PP3V3_S3_DBGLEDS

72

GREEN-3.6MCD

2.0X1.25MM-SM

33UH-20%-0.39A-0.435OHM

CRITICAL

P3V42G3H_FB

PPDCIN_G3H_OR_PBUS_R

P3V42G3H_SW

WTB-PWR-M82

NO STUFF

RCLAMP2402B

SYNC_MASTER=J13_MLB_NON_POR

22PF

5%

NP0-C0G-CERM 0201

X5R

201

603

0.1UF

X5R-CERM

MIN_LINE_WIDTH=0.4 mm

40.2K

1% 1/20W

44

0.1UF

X5R

25V

402

10%

GDZ-0201

100K

MF

1/20W

5%

S3_S0_LED

NO STUFF

62

SI5419DU

POWERPAK

=PP18V5_DCIN_ISOL

10%

402

25V X5R

0.1UF

DIDT=TRUE

25

201

GDZT2R6.8

CRITICAL

DCIN_ISOL_GATE

1

RES,MF,1/20W,90.9KOHM,1,0201,SMD

118S0560 MPM5:YES

R6912

MPM5:YES

1

R6911

117S0008

RES,MF,1/20W,100KOHM,1,0201,SMD

MPM5:NO

MPM5:YES

0

1/20W

MF

5%

201

MPM5:NO

DCIN_ISOL_GATE_R

D6950

3

1

2

R6950

1

2

C6950

1

2

C6951

1

2

J6950

1

2

3

4

5

6

7

8

9

J6900

1

2

3

4

5

6

R6941

1

2

R6940

1

2

D6911

A

K

Q6940

3

1

2

D6910

A

K

J6903

3

4

1

2

L6995

12

C6994

1

2

D6905

1

2

3

R6906

12

R6905

12

R6995

1

2

R6996

1

2

U6990

2

3

1

5

8 4

9

6

R6910

1

2

Q6910

1

4

5

5A

R6912

1

2

D6912

A

K

C6905

1

2

C6906

1

2

C6991

1

2

C6990

1

2

C6992

1

2

C6999

1

2

C6998

1

2

C6908

1

2

C6907

1

2

C6995

1

2

C6912

1

2

R6911

12

051-9277

2.8.0

69 OF 109

52 OF 73

7

6 7

6

53

6

7

OUT

IN

BI

OUT

AMON BMON ACOK

LGATE

PHASE

BOOT

SGATE AGATE

CSIP CSIN

DCIN

VNEG CSOP CSON

THRM_PAD

PGND

VDDP

VDD

BGATE

UGATE ICOMP VCOMP

ACIN

SDA VFRQ CELL

VHST

SCL

SMB_RST_N

IN

S

G

D

IN

G

D

S

G

D

S

SW

BOOST

VIN

BIAS

SHDN*

GND

NC

FB

PAD

THRM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

<Ra>

FROM ADAPTER

(AGND)

Reverse-Current Protection

(CHGR_AGATE)

DIVIDER SETS ACIN THRESHOLD AT 12.18V

through body diodes:

Need to stuff R7092 if either PP5v5_DCIN:Yes or PP5v5_VDDP are used

For Erp Lot6 spec

Q7055.

(CHGR_DCIN)

TO SYSTEM

5.5v "G3Hot" Supply

(Switcher limit)

* R7051 HAS 2.2OHM TO COMPENSATE UNBALANCED VOLTAGE

(GND)

.

36V/V

(CHGR_CSO_P)

(CHGR_CSO_N)

(PPVBAT_G3H_CHGR_R)

20V/V

Input impedance of ~40K meets

(CHGR_BGATE)

(PPVBAT_G3H_CHGR_R)

Inrush Limiter

(OD)

<Rb>

(CHGR_SGATE)

This node is powered

DUE TO DIFFERENT CURRENT ON _P AND _N. (FROM INTERSIL)

f = 400 kHz

Vout = 5.50V 200MA MAX OUTPUT

Float CELL for 1S

30mA max load

Vout = 1.25V * (1 + Ra / Rb)

TO/FROM BATTERY

* DCIN through Q7080. * PBUS through Q7085, Charger TOP FETs and

Max Current = 8A

sparkitecture requirements

ACIN pin threshold is 3.2V, +/- 50mV

10%

10% 10%10%

10%

10% 10%

10% 10% 10%10%

10%

201

201201

201

X7R

10V

10V10V

10V

X5R-X7R-CERM

0201

16V

470PF

16V

MIN_NECK_WIDTH=0.2 mm

1%

220

0.01UF

402

402402

402

402 402

402

50V

0.047UF

0402

X7R-CERM

16V

6.3V X5R

0.1UF

1UF

X5R

402-1

X5R

1UF

5%

4.7

1/16W MF-LF

SM

PLACE_NEAR=U7000.22:1mm

PLACE_NEAR=U7000.29:1mm

1UF

X5R

0.1UF

25V

0.1UF

25V X5R

0.22UF

CERM

PLACE_NEAR=U7000.25:2mm

1/20W

10

MF

5%

10

MF

1/20W

25V

20%

CASE-D3L

33UF-0.06OHM

CRITICAL

25V

20%

CASE-D3L

33UF-0.06OHM

POLY-TANT

CRITICAL

1206

8AMP-24V

1/20W

MF

332K

1%

62K

5% 1/20W MF

46

44

X5R

42 45

0.01

0.5%

1W

MF

0612-3

TQFN

ISL6259HRTZ

CRITICAL OMIT_TABLE

MF

100K

5%

1/20W

62

CRITICAL

SI7615DN

PWRPK-1212-8

1%

100

1/20W

MF

BAT30CWFILM

CRITICAL

SOT-323

X5R

25V

0.1UF

1/20W

MF

5%

100K

MF

1/20W

1%

470K

1UF

25V X5R 603-1

X5R 603-1

25V

1UF

0

1/20W

MF

5%

6

41 42 43

POWERPAK

CRITICAL

SI5419DU

CRITICAL

25V X5R 603-1

1UF

25V

0.1UF

X5R

25V25V X5R 805

10UF

1/20W

5% MF

MF5%01/20W

255K

1% 1/20W MF

MF

1/20W

CASE-B

62UF

POLY

11V

20%

CRITICAL

62UF

CASE-B

POLY

11V

20%

CASE-B

CRITICAL

62UF

20% 11V

POLY

WPAK

RJK03P0DPA

CRITICAL

PIMC104T4R7MN-SM

0.5%

0612

0.020

1W

MF-LF

CRITICAL

MF-LF

5%

603

20

1/10W

603

X5R

10UF

CRITICAL

20%

603

CRITICAL

X5R

10UF

20%

1%

MF

1/20W

681K

MF

1%

1/20W

200K

0.22UF

CERM

LT3470A

CRITICAL

MF-LF

5%

0

PP5V5_DCIN:YES

1/16W

PP5V5_VDDP

MF-LF

1/16W

5%

0

NO STUFF

0

5%

1/16W

MF-LF

25V

0603

X5R-CERM

4.7UF

CRITICAL

10UH-30%-0.85A-460MOHM

2520

X5R-CERM

0603-1

0.22UF

66.5K

1% 1/20W MF

23.7K

1/20W MF

1%

SYNC_MASTER=J13_MLB_NON_POR

SYNC_DATE=11/10/2011

PBus Supply & Battery Charger

CHGR_SGATE

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm

P5V1_FB

PPDCIN_G3H_CHGR

=PPDCIN_S5_CHGR

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

GATE_NODE=TRUE

CHGR_UGATE

DIDT=TRUE

P5V1_BOOST

VOLTAGE=5.5V

PP5V5_CHGR_VDDP

MIN_NECK_WIDTH=0.25 mm MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE DIDT=TRUE

P5V1_SW

MIN_LINE_WIDTH=0.5 mm

MIN_LINE_WIDTH=0.2 mm

CHGR_CSO_N

CHGR_DCIN

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

CHGR_VNEG_R

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

CHGR_VNEG

=PP3V42_G3H_CHGR

CHGR_CSO_R_P

MIN_LINE_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.2 mm

CHGR_CSO_R_N

VOLTAGE=8.4V

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.6 mm

PPVBAT_G3H_CHGR_REG

CHGR_BGATE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.25 mm

MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.5 mm

PPCHGR_DCIN_D_R

CHGR_DCIN_D

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.2 mm

PPDCIN_G3H_INRUSH

VOLTAGE=18.5V

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm

MIN_NECK_WIDTH=0.2 mm

CHGR_CSI_R_P

CHGR_BMON =CHGR_ACOK

CHGR_LGATE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

GATE_NODE=TRUE

DIDT=TRUE

PPVBAT_G3H_CONN

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.15 mm VOLTAGE=8.4V

SMC_RESET_L

=PPBUS_G3H

CHGR_RST_L =SMBUS_CHGR_SCL =SMBUS_CHGR_SDA

CHGR_DCIN

PP5V1_CHGR_VDDP

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

PPCHGR_DCIN_D_R

VOLTAGE=18.5V

CHGR_SGATE_DIV

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm

CHGR_CSI_P

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.25 mm

CHGR_AGATE

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5.1V

PP5V1_CHGR_VDDP

CHGR_CSI_N

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

DIDT=TRUE

CHGR_BOOT

DIDT=TRUE

SWITCH_NODE=TRUE

CHGR_PHASE

VOLTAGE=8.4V

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

CHGR_VCOMP

MIN_LINE_WIDTH=0.2 mm

CHGR_AMON

PP5V1_CHGR_VDD

VOLTAGE=5.1V

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

CHGR_CSO_P

MIN_LINE_WIDTH=0.6 mm

PPVBAT_G3H_CHGR_R

VOLTAGE=8.4V

MIN_NECK_WIDTH=0.25 MM

CHGR_VCOMP_R

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

CHGR_ICOMP

=PPDCIN_S5_CHGR_ISOL

GND_CHGR_AGND

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

VOLTAGE=0V

CHGR_ACIN

POLY-TANT

DFN

NP0-C0G-CERM

5%

22PF

0201

PLACE_NEAR=Q7030.5:1.5mm

X7R-CERM 0402

0.001UF

PLACE_NEAR=L7030.2:1.5mm

X7R-CERM

0201

1000PF

X7R-CERM 0201

1000PF

46

CHGR_VFRQ CHGR_CELL

470PF

X5R-X7R-CERM

0.47UF

10%

X5R

10V

0402

SI5419DU

POWERPAK

MIN_LINE_WIDTH=0.25 mm

CRITICAL

2.2

MIN_NECK_WIDTH=0.1 mm

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

CHGR_CSI_R_N

402

4.7UH-17A

CHGR_AGATE_DIV

X5R

PP5V5_DCIN:NO

CRITICAL

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.15 mm VOLTAGE=18.5V

50V

NO STUFF

25V

X5R-CERM

0603

4.7UF

10%

PPDCIN_G3H_OR_PBUS

VOLTAGE=18.5V MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm

C7042

1

2

C7002

1

2

C7000

1

2

R7001

12

XW7000

12

C7001

1

2

C7021

1

2

C7022

1

2

C7020

1

2

C7025

1

2

R7022

12

R7021

12

C7030

1

2

C7031

1

2

F7040

12

R7086

1

2

R7081

1

2

C7011

1

2

C7026

1

2

R7050

21

43

C7037

1

2

C7045

1

2

U7000

3

14

1

9

16

15

25

6

27

28

17

18

2

5

21

22

23

11

10

26

13

29

24

7

19

20

4

12

8

R7002

1

2

Q7055

5

4

123

R7013

1

2

D7005

1

2

3

C7085

1

2

R7080

1

2

R7085

1

2

C7035

1

2

C7036

1

2

R7000

12

Q7080

1

4

5

5A

Q7085

1

4

5

5A

C7014

1

2

C7013

1

2

C7012

1

2

C7017

1

2

R7051

12

R7052

12

R7015

1

2

R7016

1

2

C7040

1

2

C7043

1

2

C7041

1

2

Q7030

2

1

6

7

345

L7030

12

R7020

123

4

R7005

12

C7099

1

2

C7098

1

2

R7095

1

2

R7096

1

2

C7094

1

2

U7090

2

3

1

5

8 4

9

6

R7090

12

R7091

12

R7092

12

C7090

1

2

L7095

12

C7005

1

2

R7010

1

2

R7011

1

2

C7095

1

2

C7015

1

2

C7016

1

2

C7050

1

2

C7084

1

2

051-9277

2.8.0

70 OF 109

53 OF 73

7

71

7

71

53

7

71

53

6

52

7

53

71

53

71

7

71

OUT

IN

FB

EN

PVCC

VCC

SREF

VO

OCSET

PGOOD

FSEL

RTN

PHASE

LGATE

UGATE

BOOT

PGND

GND

SET0

SET1

VID0

VID1

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(VCCSAS0_OCSET)

0 1 0.725V

VID1 VID0 Voltage

0 0 0.9V

1 0 0.8V

(ENDIAN SWAP)

(VCCSAS0_VO)

6A Max Output

f = 300 kHz

OCP = 8.5A

OCP = R7141 x 8.5uA / R7140

INTEL TABLE:

1 1 0.675V

1000PF

0402

0.022UF

X5R-X7R-CERM

MIN_NECK_WIDTH=0.1 mm

1/20W

0201-10201-1

COG-CERM

5%

10PF

COG-CERM

5%

10PF

MIN_LINE_WIDTH=0.2 mm

=PPVIN_S0_VCCSAS0

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

VCCSAS0_FSEL

=PVCCSA_EN

VCCSAS0_DRVL

GATE_NODE=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

VOLTAGE=5V

PP5V_S0_VCCSAS0_VCC

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

VCCSAS0_VBST

DIDT=TRUE

VCCSAS0_DRVH

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm

PVCCSA_PGOOD

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

CPU_VCCSASENSE

MIN_LINE_WIDTH=0.6 mm

PPVCCSA_S0_REG_R

VOLTAGE=1.05V

=PPVCCSA_S0_REG

=PP5V_S0_VCCSA

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

VCCSAS0_BOOT_RC

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE

VCCSAS0_LL

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm

VCCSAS0_CS_P

VCCSAS0_CS_N

VCCSAS0_SET0

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.2 mm

VCCSAS0_SET1

VCCSAS0_OCSET

MIN_LINE_WIDTH=0.2 mm

VCCSAS0_SET1_R

MIN_LINE_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.1 mm

VOLTAGE=0V

MIN_LINE_WIDTH=0.6 mm

VCCSAS0_AGND

MIN_NECK_WIDTH=0.15 mm

VCCSAS0_VO

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.2 mm

VCCSAS0_SREF

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.2 mm

VCCSAS0_RTN

CPU_VCCSASENSE_R

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

System Agent Supply

SYNC_MASTER=J13_MLB_NON_POR

SYNC_DATE=10/17/2011

FDV0630H-SM

1.0UH-7.7A

CRITICAL

SIZ710DT

MF

3.24K

1/20W

1% 1%

3.24K

MF

1/20W

2.2UF

20%

0402

X5R-CERM

MF

1%

VCCSAS0_RTN_R

1/20W

1.62K

MF

1%

1/20W

56K

MF

1/20W

1%

1% MF

1/20W

511K

1%

49.9K

MF

1% MF

1/20W

20K

12

CRITICAL

ISL95870AH

UTQFN

MF

0

5%

1/20W

62UF

20%

CASE-B

CRITICAL

POLY

11V

270UF

CASE-B2-SM

TANT

2V

20%

SM

PLACE_NEAR=C1763.2:3mm

0805

10UF

12

X5R-CERM

10UF

CRITICAL

0805

0.001

1%

MF-1 0612

1W

CRITICAL

5%

25V

1%

1K

MF

1/20W

MF

1/20W

1%

1K

NP0-C0G

5%

25V

0.22UF

CERM

1/16W

5%

0

MF-LF

0402-1

X5R-CERM

10UF

20%

CRITICAL

2.2

MF-LF

1/16W

5%

SM

PLACE_NEAR=U7100.3:1mm

62

16V

16V 16V

50V 50V

402

CPU_VCCSA_VID<0>

MIN_NECK_WIDTH=0.1 mm

CPU_VCCSA_VID<1>

MIN_NECK_WIDTH=0.2 mm

402

NP0-C0G

1000PF

PLACE_NEAR=Q7100.2:1.5mm

CRITICAL

X5R-CERM

CRITICAL

0.1UF

16V

X7R-CERM

0402

POWERPAK-6X3.7

10V

201 201

201

10%

R7103

1

2

C7102

1

2

XW7100

12

R7101

1

2

C7101

1

2

R7130

1

2

C7130

1

2

C7140

12

R7141

1

2

R7142

1

2

C7122

1

2

R7140

12

34

C7120

1

2

C7119

1

2

XW7101

1

2

C7141

1

2

C7123

1

2

U7100

1815

10

13

3

1

11

2

14

16

20

4

8

9

7

17

19

6

5

12

R7147

1

2

R7148

1

2

R7149

1

2

R7150

12

R7151

12

R7153

12

R7152

1

2

R7154

1

2

Q7100

1

6

45

237

8

L7100

12

C7105

1

2

C7106

1

2

C7103

1

2

C7121

1

2

051-9277

2.8.0

71 OF 109

54 OF 73

7

72 45

6

OUT

IN IN

EN

EN2EN1

DRVL2

SKIPSEL1 SKIPSEL2

DRVL1

V5SW

VBST2VBST1

VREG5

VREF2

VIN

THRM_PAD

SW2SW1

RF

PGOOD2PGOOD1

GND

DRVH2DRVH1

CSP2 CSN2CSN1

COMP2COMP1

VREG3

VFB1 VFB2

OCSEL

MODE

CSP1

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

F=400KHZ

Vout = 3.3V

6.5A MAX OUTPUT7.2A MAX OUTPUT

Vout = 5.0V

353S2678

152S1424

P5VP3V3_VREF2

P5VS3_PGOOD

10%

0201-1

X7R-CERM

16V

270PF

MIN_LINE_WIDTH=0.2 mm

NO STUFF

P3V3S5_PGOOD

MIN_NECK_WIDTH=0.1 mm

MF

10% 10%

10%

10% 10%

10%

10%10%

10%

10% 10%

10%

201

201201

201

201201

201

201201

201

201 201

201

X7R X7R

10V

10V 10V

10V

402

402402

402

402 402

402

16V16V

16V

16V16V

16V

16V 16V

16V

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

P5VS3_CSN1

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

P5VS3_VBST_R

P5VS3_EN_R

=P3V3S5_EN

=P5VS3_EN

P5VS3_VFB1-R

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

P5VP3V3_VREG3

MIN_NECK_WIDTH=0.1 mm

P3V3S5_VFB2_R MIN_LINE_WIDTH=0.2 mm

=PP3V3_S5_REG

=P5V3V3_REG_EN

P5VS3_COMP1

P3V3S5_COMP2_R

P5VP3V3_VREF2

P5VS3_COMP1_R

P5VS3_FUNC

P3V3S5_RF

P3V3S5_COMP2 MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

DIDT=TRUE

GATE_NODE=TRUE

P5VS3_DRVH MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUE

DIDT=TRUE

P5VS3_DRVL

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

P5VS3_CSP1

=PP5V_S3_REG

P5VS3_LL

DIDT=TRUE

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

P5VS3_VFB1

P5VS3_CSP1_R MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

P3V3S5_EN_R

=PP5V_S3_REG

P5VP3V3_SKIPSEL

MIN_LINE_WIDTH=0.6 mm

P3V3S5_VBST_R

MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

P3V3S5_VBST

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

P3V3S5_DRVL

GATE_NODE=TRUE

P3V3S5_DRVH

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

GATE_NODE=TRUE

DIDT=TRUE

P5VP3V3_VREF2

MIN_NECK_WIDTH=0.2 mm

P5VP3V3_VREG3

MIN_LINE_WIDTH=0.2 mm

=PPVIN_S5_P5VP3V3

P5VS3_VBST MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

=PP5V_S5_LDO

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=0V

GND_P5VP3V3_SGND MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.2 mm

P3V3S5_CSN2

P3V3S5_CSP2_R

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.2 mm

P3V3S5_CSP2

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.2 mm

P3V3S5_VFB2

SWITCH_NODE=TRUE

P3V3S5_LL

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

5V / 3.3V Power Supply

SYNC_DATE=10/17/2011

SYNC_MASTER=J13_MLB_NON_POR

MF

1/20W

1%

6.65K

X5R-CERM

20%

2.2UF

SKIP_5V3V3:INAUDIBLE

0

5% 1/20W MF

SKIP_5V3V3:AUDIBLE

MF

1/20W

5%

0

POWERPAK-6X3.7

SIZ710DT

CRITICAL

CASE-B

11V

POLY

CRITICAL

20%

62UF

11V

CASE-B

62UF

20%

CRITICAL

POLY

CRITICAL

62UF

POLY

CASE-B

20% 11V

CASE-B

CRITICAL

POLY

11V

62UF

20%

603

20%

10UF

PCMC063T-SM

1.5UH-20%-18A-15MOHM

CRITICAL

10UF

20%

603

10UF

20%

603

SIZ710DT

POWERPAK-6X3.7

CRITICAL

CASE-B2-SM

6.3V

20%

POLY-TANT

CRITICAL

150UF

62UF

20%

6.3V

CASE-B2S

ELEC

CRITICAL

0

5%

MF-LF

1/16W

4700PF

62

5%

PLACE_NEAR=U7201.21:2mm

0

MF

1/20W

0

5% 1/20W MF

PLACE_NEAR=U7201.4:2mm

0

5% 1/16W MF-LF

QFN

CRITICAL

TPS51980

0

1/20W

MF

5%

0

MF

1/20W

62 62

4700PF

1/20W

7.5K

1%

MF

220PF

X7R-CERM

25V

NO STUFF

1%

MF

1/20W

20K

150UF-0.018OHM-1.8A

TANT

20%

CRITICAL

6.3V

CASE-B2-SM

PLACE_NEAR=L7220.1:3mm

SM

PLACE_NEAR=L7260.2:3mm

20K

MF

1%

NO STUFF

1/20W

1%

1/20W

7.5K

SM

PLACE_NEAR=L7220.2:3mm

SM

PLACE_NEAR=L7220.1:3mm

1%

4.22K

1/20W

MF

1/20W

MF

1.33K

1%

SM

PLACE_NEAR=L7260.1:3mm

1/20W

1%

1.54K

MF

PLACE_NEAR=U7201.28:1mm

SM

10K

MF

1/20W

1%

41.2K

MF

1/20W

1%

10K

1/20W MF

1% 1/20W MF

23.2K

0.22UF

CERM

SM

PLACE_NEAR=L7260.2:3mm

62

249K

1/20W

1%

MF

1UF

20%

POLY-TANT

150UF

6.3V

CRITICAL

CASE-B2-SM

25V 25V

1UF

PCMC063T-SM

2.5UH-14A

CRITICAL

1UF

X5R

X5R X5R

X5R

0.1UF 0.1UF

X7R-CERM

0402

0.1UF

X7R-CERM

0402

0.1UF

PLACE_NEAR=L7260.2:1.5mm

PLACE_NEAR=Q7260.2:1.5mm

PLACE_NEAR=Q7220.2:1.5mm

PLACE_NEAR=L7220.1.2:1.5mm

X7R-CERM 0201

1000PF

X7R-CERM 0201

1000PF

X7R-CERM 0201

1000PF

X7R-CERM 0201

1000PF

C7200

1

2

L7260

12

C7241

1

2

C7264

1

2

C7224

1

2

C7252

1

2

C7281

1

2

R7206

1

2

XW7261

1

2

C7201

1

2

R7260

1

2

R7261

1

2

R7220

1

2

R7221

1

2

XW7200

12

R7246

12

XW7260

1

2

C7218

12

R7247

12

R7256

1

2

XW7220

1

2

XW7221

1

2

R7236

1

2

R7237

1

2

XW7262

1

2

XW7222

1

2

C7292

1

2

R7239

1

2

C7239

1

2

R7238

1

2

C7238

1

2

R7248

12

R7249

1

2

C7272

1

2

C7283

1

2

C7270

1

2

C7271

1

2

U7201

10

15

8

17

7

18

1

24

30

27

12

4

21

28

11

14

5

20

3

6

19

32

25

33

2

31

26

9

16

23

13

22

29

R7245

1

2

R7251

1

2

R7252

1

2

C7236

1

2

C7288

12

R7264

2

1

C7254

1

2

C7253

1

2

Q7260

1

6

45

237

8

C7290

1

2

C7250

1

2

L7220

12

C7205

1

2

C7242

1

2

C7240

1

2

C7284

1

2

C7282

1

2

Q7220

1

6

45

237

8

R7200

1

2

R7201

1

2

C7203

1

2

R7216

1

2

C7237

1

2

55 OF 73

72 OF 109

2.8.0

051-9277

55

7

55 55

55

7

55

7

55

7

D

GS

IN

V5IN

REFIN

S5

VREF

S3

MODE TRIP

SW

DRVL

PGOOD

VDDQSNS

VTT

VTTSNS

VTTREF

DRVH

VBST

VLDOIN

THRM

VTT

GND

PGND

PADGND

OUT

IN

OUT

G

D

S

G

D

S

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

C7360, C7361 close to memory

If LVDDR3_HW:NO is turned ON, switch R2821 & R7971 back to the original value for 1.5V DDR unless 1V5R1V35_SW is turned ON

(DDRREG_DRVL)

(DDRREG_VDDQSNS)

10mA max load

(DDRREG_DRVH)

(DDRREG_LL)

VTT Enable

VDDQ/VTTREF Enable

Vout = 1.5V

f = 400 kHz

14.1A max output

(Q7335 limit)

10%

201

10V

16V

0.1UF

0402

X7R-CERM

PLACE_NEAR=U7300.6:1mm

0.1UF

402

X5R

SSM3K15AMFVAPE

CRITICAL

VESM

1V5R1V35_SW

17

PLACE_NEAR=U7300.9:3mm

10UF

603

20%

CRITICAL

6.3V

MF

1/20W

1%

84.5K

PLACE_NEAR=U7300.18:3mm

PLACE_NEAR=U7300.12:1mm

603

20%

10UF

25V

603-1

1UF

25V

6.3V

603

10UF

20%

SM

62

CRITICAL

QFN

TPS51916

8

SM

PLACE_NEAR=C7361.1:3mm

SM

PLACE_NEAR=U7300.21:1mm

CERM

0.22UF

PLACE_NEAR=C3101.1:1mm

603

CRITICAL

6.3V

20%

10UF

8

26

PLACE_NEAR=C3101.1:3mm

10UF

603

6.3V

20%

CRITICAL

200K

PLACE_NEAR=U7300.19:3mm

1/20W

20K

PLACE_NEAR=U7300.8:5mm

1%

MF

LVDDR3_HW:NO

1%

100K

MF

1/20W

PLACE_NEAR=U7300.8:5mm

0.01UF

CERM

PLACE_NEAR=U7300.8:1mm

PLACE_NEAR=U7300.2:1mm

20%

603

10UF

1/16W

0

5%

MF-LF

0.88UH-20%-19A-2.3MOHM

CRITICAL

1%

MF

1206

CRITICAL

46 72

72

CRITICAL

PQFN3.3X3.3

CRITICAL

POLY

11V

20%

62UF

CASE-B

62UF

11V POLY

CRITICAL

20%

CASE-B

CRITICAL

POLY

11V

20%

62UF

CASE-B

1V5R1V35_SW

PLACE_NEAR=U7300.8:5mm

150K

1%

MF

1/20W

RES,MF,60.4KOHM,1,1/20W,0201

LVDDR3_HW:YES

R7316

118S0460

1

1.5V DDR3 Supply

SYNC_MASTER=J11_MLB

SYNC_DATE=12/02/2011

MIN_NECK_WIDTH=0.1 mm

DDRREG_FB

MIN_LINE_WIDTH=0.2 mm

=PPVIN_S3_DDRREG

DDRREG_P1V35_L

MEM_VDD_SEL_1V5_L

=DDRVTT_EN

=PPVIN_S0_DDRREG_LDO

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

SWITCH_NODE=TRUE

DIDT=TRUE

DDRREG_LL

DDRREG_DRVH

GATE_NODE=TRUE

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

GATE_NODE=TRUE

DDRREG_DRVL

=PPVTT_S0_DDR_LDO

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

=PPVTT_S3_DDR_BUF

DDRREG_PGOOD

DDRREG_MODE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

DDRREG_VBST_RC

DIDT=TRUE

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.8 MM

MIN_NECK_WIDTH=0.1 MM

ISNS_1V5_S3_N

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.2 mm

DDRREG_VTTSNS

=PP5V_S3_DDRREG

DDRREG_VDDQSNS

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=0.2 mm

ISNS_1V5_S3_P

=PPDDR_S3_REG

DIDT=TRUE

DDRREG_VBST

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=0.6 mm

=DDRREG_EN

DDRREG_TRIP

MIN_LINE_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.1 mm

DDRREG_1V8_VREF

VOLTAGE=0V

MIN_NECK_WIDTH=0.15 mm

MIN_LINE_WIDTH=0.6 mm

GND_DDRREG_SGND

1/20W

1%

MF

CRITICAL

46

IRFHM830DPBF

0.5W

0.001

IRFHM831PBF

PLACE_NEAR=C7340.1:1mm

MPCG1040LR88-SM

PPDDR_S3_REG_R

CRITICAL

POLY-TANT

2.0V

20%

330UF

CASE-B2-SM1

CRITICAL

POLY-TANT

2.0V

20%

330UF

CASE-B2-SM1

50V X7R-CERM 0402

0.001UF

50V

X7R-CERM

0402

0.001UF

C7300

1

2

C7332

1

2

C7325

12

C7333

1

2

C7345

1

2

C7346

1

2

XW7301

1

2

U7300

14

11

7

19

10

20

8

17

16

13

21

18

12 15

9

2

6

3

4

5

1

XW7360

12

XW7300

1

2

C7350

1

2

C7360

1

2

C7315

1

2

C7361

1

2

R7317

1

2

R7315

1

2

R7316

1

2

C7316

1

2

C7301

1

2

R7325

12

L7330

12

R7350

12 34

Q7330

5

4

123

Q7335

5

4

123

C7330

1

2

C7331

1

2

C7334

1

2

R7314

1

2

Q7319

3

1

2

C7362

1

2

R7318

1

2

C7340

1

2

C7341

1

2

051-9277

2.8.0

73 OF 109

56 OF 73

31

7

31

7

IN

OUT

IN

OUT

IN

OUT

NC

OUT

NC

PAD

IMAXA

SR

IMAXB

ALERT*

THERMA THERMB

VDIO

POKB

CLK

EN

POKA

CSPA3

DRVPWMA

GNDSB

GNDSA

THRM

CSPB1

DHB LXB

BSTB

DLA2

DLB

CSNB

FBB

LXA1

DHA1

BSTA1

TON

DLA1

CSPA1

CSPAAVE

FBA

CSNA

BSTA2

CSPA2

DHA2 LXA2

VCC

VDDA

VDDB

VR_HOT*

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

10%

201

201 201

201

201201

201

201201

201

10V

10V10V

0.01UF

402

402402402

402

50V

1000PF

0201

X7R-CERM

16V

1000PF

0201

X7R-CERM

16V

1000PF

0201

X7R-CERM

16V

1000PF

0201

X7R-CERM

16V

0201

NO STUFF

X5R-CERM

NO STUFF

X5R-CERM

CPUIMVP_AXG_PGOOD

NO STUFF

47PF

5% 25V NP0-C0G-CERM 0201

100PF

8.25K

6.34K

100PF

5%

25V

NP0-CERM

0201

NO STUFF

0201

NP0-CERM

25V

5%

NO STUFF

CPU IMVP7 & AXG VCore Regulator

NP0-CERM

25V

5%

100PF

02010201

5%

NP0-CERM

NO STUFFNO STUFF

NP0-CERM

25V

5%

100PF

02010201

100PF

5% 25V NP0-CERM

NO STUFF

CPU_AXG_SENSE_R

MIN_LINE_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.2 mm

CPUIMVP_FBA

CPUIMVP_PHASE1

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

=PPVIN_S0_CPUIMVP

CPUIMVP_ISUM

=PP5V_S0_CPUIMVP

CPUIMVP_ISUM_R

MIN_NECK_WIDTH=0.1 mm

CPUIMVP_ISUM_N

CPUIMVP_ISUMG_P

MIN_NECK_WIDTH=0.2 mm

CPU_VCCSENSE_R

MIN_LINE_WIDTH=0.2 mm

=PPVCCIO_S0_CPUIMVP

CPUIMVP_SLEW

CPUIMVP_ISNS1_P

CPU_VCCSENSE_P

CPU_VIDSCLK

CPUIMVP_UGATE1G CPUIMVP_PHASE1G

CPUIMVP_BOOT1G

CPUIMVP_LGATE1G

CPUIMVP_FBB

CPUIMVP_UGATE1_R

CPUIMVP_BOOT1

CPUIMVP_TON

CPUIMVP_LGATE1

CPUIMVP_FBA

CPU_AXG_SENSE_N

CPU_VCCSENSE_N

CPUIMVP_PGOOD

CPUIMVP_VR_ON

CPU_AXG_SENSE_P

CPUIMVP_FBB_R

MIN_LINE_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

CPUIMVP_FBA_R

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.2 mm

CPUIMVP_ISUM_P

CPUIMVP_ISUMG_N

CPUIMVP_IMAXA

GND_CPUIMVP_SGND

VOLTAGE=0V

CPUIMVP_NTC

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.2 mm

CPU_VIDSOUT

MIN_NECK_WIDTH=0.2 mm

CPUIMVP_FBB

MIN_LINE_WIDTH=0.2 mm

CPUIMVP_IMAXB

MIN_LINE_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.1 mm

CPUIMVP_NTCG

CPU_VIDALERT_L

CPU_PROCHOT_L

VOLTAGE=5V

MIN_LINE_WIDTH=0.4 mm

P5V_S0_CPUIMVP_VDD

MIN_NECK_WIDTH=0.2 mm

SYNC_MASTER=J11_MLB

SYNC_DATE=10/14/2011

TQFN

CRITICAL

MAX15120

MF

1/20W

1%

2.2

MF-LF

5%

1/16W

1%

1/20W

MF

1/20W

10K

1%

MF

1/20W

137K

MF

1%

1/20W

1%

MF

215K

PLACE_NEAR=Q7550.1:2mm

CRITICAL

0603

100KOHM-1%-100MW

PLACE_NEAR=Q7510.1:2mm

CRITICAL

0603

100KOHM-1%-100MW

2200PF

X7R-CERM 0201

0.0022UF

CERM

5.76K

1%

MF

1/20W

5.76K

1% 1/20W MF

1%

MF-LF

90.9K

1/16W

137K

1%

MF

1/20W

MF

1/20W

215K

1%

58

PLACE_NEAR=U7400.16:2mm

1/20W MF

1%

130

PLACE_NEAR=U7400.18:2mm

MF

1%

54.9

1/20W

72 58

72 58 45

1/20W

MF

10

5%

66 12

5%

MF

10

1/20W

66 12

10

1/20W

5%

MF

1/20W

MF

5%

10

1%

200K

1/20W

NO STUFF

MF

X5R-CERM

2.2UF

20%

PLACE_NEAR=U7400.15:2mm

SM

72 58

58

72 58

58

66 42 41 10

62

25

NO STUFF

0402

X5R-CERM

0.039UF

5%

1

MF

1/20W

MIN_LINE_WIDTH=0.2 mm

MF

5%

1/20W

300

66 12

X5R-CERM

2.2UF

20%

PLACE_NEAR=U7400.24:2mm

2.2UF

X5R-CERM

20%

1/16W MF-LF

5%

10

CPUIMVP_UGATE1

100PF

25V

72

470PF

NP0-C0G-CERM

5%

0402

NO STUFF

R7401

12

C7401

1

2

C7402

1

2

R7406

12

R7410

12

C7408

12

XW7400

12

C7403

1

2

R7464

1

2

R7440

12

R7441

12

C7440

1

2

C7441

1

2

C7412

1

2

R7413

12

C7422

1

2

R7423

12

R7479

1

2

R7480

1

2

R7460

1

2

R7461

1

2

R7402

12

R7468

1

2

R7466

1

2

C7407

1

2

C7404

1

2

R7469

1

2

R7467

1

2

R7462

1

2

R7463

1

2

R7465

1

2

R7412

12

R7403

12

R7422

12

U7400

17

20

28

11

18

37

9

36

38

39

35

8

22

26

13

23

25

14

31

1

4

6

3

7

29 30

21

27

12

19 10

32

33 34

41

2

402415

16

5

C7418

1

2

C7419

1

2

C7414

1

2

C7415

1

2

C7462

12

C7452

12

C7444

1

2

C7409

12

C7442

1

2

C7443

1

2

051-9277

2.8.0

74 OF 109

57 OF 73

58

7

57

IN

OUT

S

G

D

G

S

VSW

PGND

TGR

TG

BG

VIN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

CPU=IV Bridge ULV, AXG=GT2

376S1005

376S0984

376S0985

AXG PHASE

THESE TWO CAPS ARE FOR EMC

PHASE 1

152S1323

THESE TWO CAPS ARE FOR EMC

10%

10% 10%

10%10%

10%

201

201 201

201

10V

402

50V 50V

50V50V

50V

16V

1000PF

0201

X7R-CERM

NO STUFF

0.001UF

0402

X7R-CERM

0.001UF

0402

X7R-CERM

0.001UF

0402

X7R-CERM

0.001UF

0402

X7R-CERM

0.001UF

CASE-B

62UF

CRITICAL

POLY

20% 11V

POLY CASE-B

CRITICAL

PIMB104T-SM

DIDT=TRUE

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.25 MM

CPUIMVP_VSWG

SWITCH_NODE=TRUE

CPUIMVP_PHASE1G

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

GATE_NODE=TRUE

DIDT=TRUE

CPUIMVP_UGATE1G_R

MIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

GATE_NODE=TRUE

DIDT=TRUE

CPUIMVP_LGATE1G

MIN_NECK_WIDTH=0.2 MM

CPUIMVP_ISNS1G_P CPUIMVP_ISNS1G_N

CPUIMVP_ISUMG_P

=PPVCORE_S0_CPU_REG

CPUIMVP_UGATE1G

GATE_NODE=TRUE

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

DIDT=TRUE

CPUIMVP_BOOT1G_RC

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

CPUIMVP_BOOT1G

MIN_LINE_WIDTH=0.5 MM

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

CPUIMVP_BOOT1

MIN_LINE_WIDTH=0.5 MM

CPUIMVP_ISNS1_N

CPUIMVP_ISUM_P

CPUIMVP_ISUMG_N

CPUIMVP_ISNS1_P

GATE_NODE=TRUE

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

CPUIMVP_UGATE1

MIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

SWITCH_NODE=TRUE

CPUIMVP_PHASE1

MIN_LINE_WIDTH=0.5 MM

DIDT=TRUE

GATE_NODE=TRUE

CPUIMVP_LGATE1

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

VOLTAGE=1.25V

MIN_LINE_WIDTH=0.5 MM

PPVCORE_S0_CPU_PH1

MIN_NECK_WIDTH=0.25 MM

=PPVIN_S0_CPUIMVP

CPUIMVP_BOOT1_RC

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

CPUIMVP_ISUM_N

=PPVCORE_S0_AXG_REG

DIDT=TRUE

VOLTAGE=1.25V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

CPUIMVP_AXG_SNUB

PPVCORE_S0_AXG_R

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.25 MM

VOLTAGE=1.05V

=PPVIN_S0_CPUAXG

CPU IMVP7 & AXG VCore Output

SYNC_MASTER=J13_MLB_NON_POR

SYNC_DATE=10/17/2011

20% 11V

CRITICAL

POLY CASE-B

62UF

CSD58872Q5D

SON5X6

CRITICAL

10

5%

1/16W

MF-LF

CRITICAL

DIRECTFET-MX

IRF6894MTRPBF

10UF

20%

X5R-CERM 0603

CRITICAL

25V

20%

CRITICAL

10UF

25V X5R-CERM 0603

0603

CRITICAL

25V

20%

10UF

X5R-CERM

CRITICAL

11V

20%

62UF

POLY CASE-B

20%

62UF

CRITICAL

POLY

11V

CASE-B

CRITICAL

IRF6811STRPBF

SQ

CRITICAL

PIMB104T-SM

0.36UH-20%-30A-1.2MOHM

20%

CRITICAL

62UF

11V POLY CASE-B

20% 11V POLY

CRITICAL

62UF

CASE-B

POLY

11V

20%

62UF

CASE-B

CRITICAL

POLY

11V

20%

62UF

CASE-B

CRITICAL

POLY

20%

62UF

11V

CASE-B

62UF

20% 11V

CRITICAL

2200PF

0201

X7R-CERM

NO STUFF

1/20W

1%

MF

46.4

1%

MF

1/20W

1% 1W MF

0612

0.00075

CRITICAL

1%

0612

MF

1W

0.00075

CRITICAL

5% 1/16W MF-LF

4.7

72 57 45

72 57

MF

10

1% 1/20W

MF

10

1% 1/20W

57

0.22UF

CERM

NOSTUFF

2.2

NOSTUFF

1/10W

5%

603

MF-LF

X5R

1UF

0.22UF

CERM

MF-LF

5%

0

1/16W

57

1UF

X5R

10UF

20% 25V

0603

X5R-CERM

CRITICAL

0.36UH-20%-30A-1.2MOHM

L7510

12

C7515

1

2

C7517

1

2

C7518

1

2

C7519

1

2

R7511

1

2

C7511

1

2

C7559

1

2

C7558

1

2

C7557

1

2

R7552

1

2

C7552

1

2

C7551

1

2

R7514

1

2

R7554

1

2

R7555

12

R7510

12

34

R7550

12

34

R7553

1

2

R7513

1

2

C7571

1

2

C7574

1

2

C7513

1

2

C7514

1

2

C7540

1

2

C7541

1

2

C7560

1

2

C7553

1

2

C7554

1

2

L7550

12

Q7510

1

2

5

64

3

C7510

1

2

C7520

1

2

C7516

1

2

C7555

1

2

C7556

1

2

Q7520

1267

5

34

R7551

1

2

Q7550

5

9

3

4

1

6 7 8

C7561

1

2

051-9277

2.8.0

75 OF 109

58 OF 73

72 45 72 45

7

72 45

57

7

OUT

IN

BOOT

UGATE

LGATE

PHASE

RTN

FSEL

PGOOD

OCSET

VO

SREF

VCC

PVCC

GND

PGND

EN

FB

VSW

PGND

TGR

TG

BG

VIN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(CPUVCCIOS0_VO)

(CPUVCCIOS0_OCSET)

OCP = 25.6A

<Ra>

CPU VCCIO (1.05V S0) Regulator

21A Max Output

Vout = 1.05V

f = 300 kHz

OCP = R7641 x 8.5uA / R7640

Vout = 0.5V * (1 + Ra / Rb)

<Rb>

10%

201

201 201

201

10V

0.047UF

0402

X7R-CERM

16V

402

16V

NP0-C0G-CERM

02010201

47PF

5%

25V

47PF

5% 25V NP0-C0G-CERM

10UF

VOLTAGE=0V

=PPVIN_S0_CPUVCCIOS0

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.2 mm

CPUVCCIOS0_VO

CPUVCCIOS0_CS_N

CPUVCCIOS0_AGND

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.15 mm

CPUVCCIOS0_OCSET

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.2 mm

PPCPUVCCIO_S0_REG_R

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

=PP5V_S0_CPUVCCIOS0

CPUVCCIOS0_PGOOD

CPU_VCCIOSENSE_P

CPUVCCIOS0_FSEL

=CPUVCCIOS0_EN

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=5V

PP5V_S0_CPUVCCIOS0_VCC

=PPCPUVCCIO_S0_REG

CPUVCCIOS0_DRVH

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

GATE_NODE=TRUE

CPUVCCIOS0_RTN

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

CPU_VCCIOSENSE_N

CPUVCCIOS0_FB

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

CPUVCCIOS0_SREF

CPUVCCIOS0_CS_P

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

CPUVCCIOS0_VBST

DIDT=TRUE

CPUVCCIOS0_BOOT_RC

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

DIDT=TRUE

CPUVCCIOS0_DRVL

GATE_NODE=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

CPUVCCIOS0_R

MIN_NECK_WIDTH=0.2 mm

CPUVCCIOS0_LL

MIN_LINE_WIDTH=0.6 mm

SWITCH_NODE=TRUE DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

PPCPUVCCIO_S0_REG

VOLTAGE=1.05V

CPU VCCIO (1.05V) Power Supply

SYNC_DATE=10/17/2011

SYNC_MASTER=J13_MLB_NON_POR

1/20W

MF

3.01K

1%

2.74K

MF

1/20W

1% 1/20W MF

2.74K

CRITICAL

CSD58872Q5D

SON5X6

CRITICAL

CASE-B

POLY

11V

20%

62UF

CASE-B

CRITICAL

POLY

11V

20%

62UF

CASE-B

62UF

20% 11V POLY

CRITICAL

0.001

1% 1W MF

0612

PIMB104T-SM

0.68UH-22A-2.7MOHM

CRITICAL

MF

1/20W

5%

2.2

270UF

2V

TANT

CASE-B2-SM

CRITICAL

20%

CASE-B2-SM

CRITICAL

TANT

2V

20%

270UF

0

1/16W

MF-LF

5%

MF-LF

1/10W

603

5%

0

25V

PLACE_NEAR=Q7630.1:1.5mm

NP0-C0G

5%

25V

NP0-C0G

5%

PLACE_NEAR=L7630.2:1.5mm

25V

NP0-C0G

5%

1/20W

MF

1%

3.01K

MF

1/20W

1%

3.01K

1UF

20%

603

CRITICAL

ISL95870

UTQFN

SM

PLACE_NEAR=U7600.1:1mm

0

MF

1/20W

5%

2.2UF

603

62

3.01K

1%

MF

1/20W

X5R

1000PF

C7603

1

2

R7645

1

2

R7605

1

2

R7604

1

2

R7644

1

2

C7602

1

2

R7603

1

2

XW7600

12

U7600

12

3

6

5

1

15

7

16

9

10

14

2

4

11

13

8

C7601

1

2

C7630

1

2

R7642

1

2

R7641

1

2

C7640

12

C7623

1

2

C7622

1

2

R7630

1

2

R7631

12

C7648

1

2

C7649

1

2

R7601

1

2

L7630

12

R7640

12 34

C7619

1

2

C7620

1

2

C7621

1

2

Q7630

5

9

3

4

1

6 7 8

C7605

1

2

C7604

1

2

051-9277

2.8.0

76 OF 109

59 OF 73

7

72 45

7

66 12

7

66 12

72 45

IN

BIAS

NC

OUT

THRM

EN

PADGND

NC

IN

BIAS

NC

OUT

THRM

EN

PADGND

NC NC NC

LX

VDD

VIN

THRM_PAD

PGND

SGND

EN

PG

SYNCH

LX

VFB

NC

IN

OUT

NC

IN

BIAS

NC

OUT

THRM

EN

PADGND

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Cougar Point requires JTAG pull-ups to be powered at 1.05V when SUS suspend well is active.

1.05V SUS LDO

Pull-ups (3) must be 51 ohms to support XDP (not required in production). 70mA is required to support pull-ups. Alternative is strong voltage

Max Current = 0.020A

Vout = 1.05V

Freq = 1 MHz

Max Current = 0.02A

Max Current = 0.35A

Vout = 1.05V

<Ra>

152S1302

1.8V S0 Regulator

dividers (200/100) to 3.3V S5, which burns 100mW in all S-states.

1.05V S0 LDO

<Rb>

Vout = 0.8V * (1 + Ra / Rb)

Vout = 1.794V

Max Current = 1.8A

Vout = 1.5V

1.5V S0 LDO

10% 10% 10%

10%10%

10%

402 402 402

402402

16V

201

5% 25V

=PP3V3_S0_P1V8S0

P1V8S0_PGOOD

=PP3V3_SUS_P1V05SUSLDO

=PP1V8_S0_REG

=P1V8S0_EN

P1V8S0_SW

DIDT=TRUE

SWITCH_NODE=TRUE

=1V05_S0_LDO_EN

=PP3V3_S0_P1V05S0LDO

=PP1V8_S0_P1V05S0LDO

=PP1V05_S0_LDO

=PP3V3_S0_P1V5S0

=PP1V8_S0_P1V5S0

=P1V5S0_EN

=PP1V5_S0_REG

P1V8S0_FB

=PP1V05_SUS_LDO

SYNC_MASTER=K21_MLB

SYNC_DATE=07/28/2011

Misc Power Supplies

62

7

6.3V CERM

1UF

PLACE_NEAR=U7770.4:1mm

1UF

CERM

6.3V

PLACE_NEAR=U7770.6:1mm

SON

TPS72015

CRITICAL

2.2UF

6.3V

1/20W

MF

90.9K

1%

62

QFN

ISL8014A

CRITICAL

22UF

6.3V

CRITICAL

20%

X5R-CERM-1

603

CRITICAL

1.0UH-20%-4.5A-24MOHM

PIMB042T-SM

1/20W

MF

113K

1%

22UF

6.3V

20%

CRITICAL

X5R-CERM-1

603

22UF

CRITICAL

20%

6.3V X5R-CERM-1 603

PLACE_NEAR=U7780.4:1mm

6.3V CERM

1UF

PLACE_NEAR=U7780.6:1mm

1UF

CERM

6.3V

SON

TPS720105

CRITICAL

2.2UF

6.3V

XDP_PCH

2.2UF

6.3V

SON

CRITICAL

TPS720105

XDP_PCH

1UF

CERM

6.3V

XDP_PCH

0201

NP0-C0G-CERM

47PF

X5R

X7R-CERM

0201

1000PF

C7740

1

2

U7740

4

3

5

6

1

7

C7741

1

2

C7781

1

2

U7780

4

3

5

6

1

7

C7780

1

2

C7782

1

2

C7721

1

2

C7722

1

2

R7720

1

2

L7720

12

C7720

1

2

U7720

5

14

15

6

16

13

7

11

12

9

10

4

17

3

8

1

2

C7724

1

2

R7721

1

2

C7772

1

2

U7770

4

3

5

6

1

7

C7771

1

2

C7770

1

2

C7723

1

2

051-9277

2.8.0

77 OF 109

60 OF 73

2

7

62

7

IN

D

SG

D

SG

IN

THRM

GND

G

PG

SHDN*

D

VCC

S

ON

PAD

OUT

IN

D

SG

D

SG

D

SG

D

S

G

D

S

G

D

S

G

D

S

G

S

D

S

G

IN

G

S

D

GS

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

3.3V S3 FET

1.5V S3/S0 FET

PQFN2X2

3.3V S4 FET

376S0945

LOADING

RDS(ON)

0.7? A (EDP)

26 mOhm @1.8V

SiA427

3.3V_SUS FET

3.2 A (EDP)

SiA427

N-TYPE

1.5V S3/S0 FET

APN 376S0928

1.608 A (EDP)

31 mOhm @1.8V

SiA427

P-TYPE 8V/5V

MOSFET

CHANNEL

5 A (EDP)

9.4 mOhm @4.5V

RDS(ON)

LOADING

CHANNEL

29 mOhm @4.5V

P-TYPE 12V/8V

100? mA (EDP)

26 mOhm @1.8V

SiA427

LOADING

CHANNEL

RDS(ON)

MOSFET

RDS(ON)

3.3V S0 FET

RDS(ON)

P-TYPE 8V/5V

CHANNEL

1.678 A (EDP)LOADING

CHANNEL

LOADING

MOSFET TPCP8102

P-TYPE

100? mA (EDP)

P-TYPE 8V/5V

LOADING

3.3V S3 FET

5.0V S0 FET

MOSFET

5V_SUS FET

18 MOHM @4.5V

LOADING

RDS(ON)

CHANNEL

MOSFET

5V SUS FET

26 mOhm @1.8V

3.3V SUS FET

MOSFET

3.3V S0 FET

5.0V S0 FET

RDS(ON)

P-TYPE 8V/5V

MOSFET

CHANNEL

3.3V S4 FET

26

0.01UF

X5R

0.033UF

16V X5R 402

5%

1/20W

47K

MF

X5R

0.01UF

0.033UF

402

16V X5R

62

38 62

SSM6N37FEAPE

SOT563

SSM6N37FEAPE

SOT563

62

5%

1/20W

MF

10K

0.033UF

402

16V

X5R

402

0.01UF

CERM

16V

TDFN

CRITICAL

SLG5AP020

20%

0.1UF

CERM

402

1/16W

402

0

5%

MF-LF

603

4.7UF

X5R-CERM

6.3V

NO STUFF

8

61 62

SOT563

SSM6N37FEAPE

402

16V X5R

0.033UF

16V

402

X5R

0.033UF

0.01UF

CERM

16V

402

X5R

0.01UF

SOT563

SSM6N37FEAPE

SOT563

SSM6N37FEAPE

MF

5% 1/20W

100K

1/20W

5% MF

12K

3.3K

MF

1/20W

5%

1/20W MF

5%

220K

SIA427DJ

SC70-6L

CRITICAL

SIA427DJ

CRITICAL

SC70-6L

SIA427DJ

CRITICAL

5%

91K

1/20W

MF

10K

MF

1/20W

5%

220K

MF

5% 1/20W

100K

5% 1/20W MF

SC70-6L

SIA413DJ

CRITICAL

MF-LF

1206

1/4W

5%

0

CRITICAL

FDMC2514SDC

POWER33

CRITICAL

1/10W

5%

603

0

MF-LF

402

5%

MF-LF

1/16W

0

CRITICAL

402

0

5% 1/16W MF-LF

1W

1%

0.001

0612

MF-1

CRITICAL

NOSTUFF

5%

1/16W

0

MF-LF

402

CRITICAL

SIA427DJ

SC70-6L

16V

CERM

0.01UF

402

0.033UF

402

16V

X5R

402

MF-LF

5%

1/16W

47K

MF-LF

402

1/16W

5%

220K

62

CRITICAL

DMP2018LFK

DFN2563-6

402

5%

1/16W

0

MF-LF

SSM3K15AMFVAPE

VESM

SYNC_MASTER=K21_MLB

Power FETs

SYNC_DATE=07/28/2011

=P3V3S4_EN

P3V3S4_EN_L

P3V3S3_S4

=PP3V3_S3_P3V3S3FET

P3V3S3_EN_L

P3V3S3_SS

=PP1V5_S3_P1V5S3RS0_FET

P1V5S0FET_GATE_R

ISNS_3V3S0_P

ISNS_3V3S0_N

=PP3V3_S0_FET

=PP1V5_S3RS0_FET

P3V3S0_SS

P3V3S0_EN_L

=P3V3S3_EN

=P5V_3V3_SUS_EN

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM

VOLTAGE=3.3V

PP3V3_S3_FET_R

=PP3V3_S3_FET

P1V5S3RS0_RAMP_DONE

=PP5V_S5_P1V5DDRFET

=P5VS0_EN

=P3V3S0_EN

=P5V_3V3_SUS_EN

P5VSUS_EN_L

P5V0S0_EN_L

P1V5CPU_EN

P1V5S0FET_GATE

=PP3V3_SUS_FET

P3V3SUS_SS

PP3V3_SUS_FET_R

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM

=PP3V3_S5_P3V3SUSFET

P3V3SUS_EN_L

P5VSUS_SS

=PP5V_S5_P5VSUSFET

=PP5V_S0_FET

=PP5V_SUS_FET

PP1V5_S3RS0_FET_R

VOLTAGE=1.5V MIN_NECK_WIDTH=0.2 MM MIN_LINE_WIDTH=0.6 MM

PP3V3_S0_FET_R

MIN_LINE_WIDTH=0.50MM

MIN_NECK_WIDTH=0.20MM

VOLTAGE=3.3V

=PP3V3_S0_P3V3S0FET

P5V0S0_SS

=PP5V_S3_P5VS0FET

VOLTAGE=5V

MIN_NECK_WIDTH=0.20MM

PP5V_S0_FET_R

MIN_LINE_WIDTH=0.40MM

=PP3V3_S4_P3V3S4FET

=PP3V3_S4_FET

PP3V3_S4_FET_R

10V

201

10%

C7810

12

C7811

1

2

R7810

12

C7830

12

C7831

1

2

Q7812

6

2

1

Q7812

3

5

4

R7860

12

C7861

1

2

C7860

12

U7801

5

7

4

2

8

6

3

9

1

C7801

1

2

R7801

12

C7802

1

2

Q7822

6

2

1

C7841

1

2

C7821

1

2

C7840

12

C7820

12

Q7822

3

5

4

Q7802

3

5

4

R7812

1

2

R7820

12

R7840

12

R7862

1

2

Q7830

1

3

47

Q7820

1

3

47

Q7810

1

3

47

R7830

12

R7832

1

2

R7842

1

2

R7822

1

2

Q7840

1

3

47

R7850

12

Q7801

5

4

123

R7811

12

R7821

12

R7841

12

R7831

12 34

R7803

12

Q7800

1

3

47

C7800

12

C7809

1

2

R7800

1

2

R7802

1

2

Q7860

4

3

1

2

R7804

12

Q7809

3

1

2

051-9277

2.8.0

78 OF 109

61 OF 73

7

45 72

7

G

D

S

IN

G

D

S

OUT

IN

OUT

D

GS

IN

OUT

IN

NC

Q3

Q2

Q4

Q1

SENSE

CT

VDD

GND

RESET*

MR*

IN

G

D

S

OUT

VDD

MR*

RST*V4MON

V3MON

V2MON

GND

THRM_PAD

OUT

IN

VDD

OUT_A*

OUT_A

THRM

GND

IN_A

DLY_1C

IN_B

OUT_B

DLY

(OD,IPU)

(IPD)

1.3V

PAD

2:1

-

+

OUT

VCC

A

Y

GND

B

C

IN

OUT

IN

G

D

S

NC

OUT

NC

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PM_SLP_S5_L:100K pull down on PCH page

DP S4 Power Enable

VFRQ Low: Fix Frequency

(PM_SLP_S3_R_L)

Q3: 0.640V

S0 Rail PGOOD (BJT Version)

S5 Rail Enables & PGOOD

Threshold: ??

DLY > 10 ms

343S0497

3.3V,5V S3 ENABLE

(90K IPU)

(AC_EN_L)

(IPU)

P1V5S0_PGOOD from U7710

Q4: 0.660V

353S2809

Thresholds: VDD: 2.734V-3.010V

(PM_SLP_S3_L)

"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))

WLAN Enable Generation

Unused fet

S5_PWRGD (old name RSMRST_PWRGD)-->SMC SMC-->PM_DSW_PWRGD

Worst-Case Thresholds:

S0 Rail PGOOD Circuitry

V3MON: 0.572V-0.630V

V2MON: 2.815V-3.099V

V4MON: 0.572V-0.630V

(ISL Version in development)

PM_SLP_S3_L

1

0

01

1

PM_SLP_S4_L

1

PM_SLP_S5_L

1

PM_SUS_EN

0

1

X

SMC_PM_G2_ENABLE

1

SMC_S4_WAKESRC_EN

1

11 01 00 0

0

00

0

00

0

1

0

10

1

0

1

0

1

Battery Off (G3HotAC)

Battery Off (G3Hot)

Run (S0)

Sleep (S3AC)

Sleep (S3)

State

Deep Sleep (S4AC)

Deep Sleep (S5)

Deep Sleep (S4)

Deep Sleep (S5AC)

Internal pull-ups 100K +/- 20%

SMC_ADAPTER_EN

toggle 3Hz

353S2310

0

CPUVCORE ENABLE

NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.

SMC_BATLOW_L:100K pull up on SMC page

3.3V w/Divider: 2.345V

Q2: 0.XXXV

PP1V5_S3RS0

3.3V/5.0V Sus ENABLE

No stuff C7931, 12ms Min delay time

3.3V SUS Detect

PM_RSMRST_L goes to U1800.C21

PCH power down timing t235

Could stuff R7930 to satisfy

threhold is 3.07V

S0 ENABLE

CHGR VFRQ Generation

VFRQ High: Variable Frequency

1

Mobile System Power State Table

U7930 Sense input

2N7002DW-X-G

SOT-363

17 41 42

17 26 41 62

SOT-363

2N7002DW-X-G

37

55

56

61

PLACE_NEAR=Q7812.2:6mm

CERM-X5R 402

0.47UF

6.3V

57

PLACE_NEAR=U7400.1:5mm

1/20W

MF

5%

0

61

38 61

45

59

60

54

MF

1/20W

5%

5.1K

PLACE_NEAR=U7300.16:6mm

0.47UF

402

CERM-X5R

6.3V

17 26 37 41

49

PLACE_NEAR=U7720.5:6mm

0.47UF

CERM-X5R 402

6.3V

1/20W

PLACE_NEAR=U7720.5:6mm

MF

5.1K

5%

PLACE_NEAR=U7600.3:6mm

402

CERM-X5R

0.47UF

6.3V

PLACE_NEAR=U7100.15:6mm

CERM-X5R

0.47UF

6.3V

402

33K

MF

1/20W

5%

PLACE_NEAR=U7100.15:6mm

1/20W

MF

10K

5%

53

SOD-VESM-HF

SSM3K15FV

17 26 41 62

NO STUFF

5%

0

MF

1/20W

5%

10K

MF

1/20W

23 25 41 52 62

5%

100

1/20W

MF

5%

MF

1/20W

100

5%

1/20W

100

MF

100

MF

1/20W

5%

60

55

5%

100

MF

1/20W

5%

MF

1/20W

330

S0PGOOD_ISL

59

54

MF

1%

150K

1/20W

S0PGOOD_ISL

6.3V X5R

0.1UF

1/20W MF

15K

1%

7.15K

1/20W MF

1%

DFN2015H4-8

CRITICAL

ASMCC0179

5%

1K

1/20W

MF

1/20W

1K

MF

5%

CRITICAL

TPS3808G33DBVRG4

SOT23-6

1/20W

MF

100K

5%

6.3V X5R

0.1UF

PLACE_NEAR=U7930.6:2.3mm

5%

MF

1/20W

NO STUFF

100

57

SOT-363

2N7002DW-X-G

5%

100

MF

1/20W

60

CERM-X5R

PLACE_NEAR=U7770.3:6mm

0.47UF

6.3V

402

17

ISL88042IRTEZ

CRITICAL

TDFN

S0PGOOD_ISL

1/20W

MF

1%

S0PGOOD_ISL

15K

S0PGOOD_ISL

12.4K

MF

1/20W

1%

15K

S0PGOOD_ISL

1%

MF

1/20W

1%

MF

10K

1/20W

S0PGOOD_ISL

1/20W

1%

MF

S0PGOOD_ISL

6.04K

MF

1%

S0PGOOD_ISL

6.04K

1/20W

55

X5R 402

NO STUFF

0.033UF

1/20W

100

MF

5%

41

6.3V X5R

0.1UF

41

TDFN

SLG4AP012

CRITICAL

220PF

X7R-CERM

25V

6

39 40

5%

1/20W

MF

0

NO STUFF

402

0.068UF

CERM

60

20K

PLACE_NEAR=U7600.3:6mm

1/20W MF

5%

1/20W

MF

NO STUFF

5%

0

SOT891

74AUP1G3208

PLACE_NEAR=U7940.5:2.3mm

X5R

0.1UF

6.3V

17

41 42

61

PLACE_NEAR=U7770.3:6mm

1/20W MF

39K

5%

PLACE_NEAR=Q7812.2:6mm

MF

1/20W

5%

9.1K

MF

5%

100

1/20W

55

18 23 37

SOT-363

2N7002DW-X-G

5%

1K

1/20W

MF

64

MF-LF

0

NOSTUFF

5%

1/16W

402

SOT891

74LVC1G32

17 41

20%

PLACE_NEAR=U7940.1:2.3mm

0.1uF

402

CERM

41 42

64

MF

1/20W

5%

0

NO STUFF

61

SYNC_MASTER=J13_MLB_NON_POR

SYNC_DATE=11/10/2011

Power Control 1/ENABLE

MAKE_BASE=TRUE

P5V3V3_S4_EN

=P3V3S4_EN

=TBTAPWRSW_EN

MAKE_BASE=TRUE

SMC_S4_WAKESRC_EN

=PP3V3_S5_PWRCTL

=PP3V3_S0_PWRCTL

PM_SLP_S5_L

PM_SLP_S3_L

PVCCSA_EN

MAKE_BASE=TRUE

=PVCCSA_EN

=1V05_S0_LDO_EN =CPUVCCIOS0_EN

P1V5S0_EN

MAKE_BASE=TRUE

=P1V5S0_EN

MAKE_BASE=TRUE

P1V8S0_EN

=P1V8S0_EN

=TBT_S0_EN

=P3V3S0_EN

=PBUSVSENS_EN

=P5VS0_EN

CPUVCCIOS0_EN

MAKE_BASE=TRUE

CHGR_VFRQ

=PP3V42_G3H_PWRCTL

P1V8S0_PGOOD

DDRREG_EN

MAKE_BASE=TRUE

=PP3V3_SUS_PWRCTL

MAKE_BASE=TRUE

PM_SLP_S4_L

ALL_SYS_PWRGD

=P3V3S5_EN

P3V3S3_EN

MAKE_BASE=TRUE

P5VS3_EN

MAKE_BASE=TRUE

=P5VS3_EN

AP_PWR_EN

CPUVCCIOS0_PGOOD

=PP5V_S0_VMON

=PP1V05_S0_VMON

VMON_3V3_DIV VMON_Q2_BASE

=PP3V3_S5_VMON

S0PGD_C

VMON_Q4_BASE

S0PGD_BJT_GND_R

S4_PGOOD_CT

=PP3V3_SUS_PWRCTL

=P3V3S3_EN

=USB_PWR_EN

=DDRREG_EN

=PP1V5_S3RS0_VMON

SMC_ADAPTER_EN

=PP3V3_S0_VMON

=PP1V5_S3RS0_VMON

=PP1V05_S0_VMON

P3V3S5_PGOOD

PVCCSA_PGOOD

AC_EN_L

PM_WLAN_EN_L

S5PGOOD_DLY

MAKE_BASE=TRUE

P5V3V3_REG_EN

PM_SLP_S3_L

CPUIMVP_AXG_PGOOD

SMC_PM_G2_EN

MAKE_BASE=TRUE

=PP3V42_G3H_PWRCTL

=PP3V3_S5_PWRCTL

ALL_SYS_PWRGD_R

P1V05_DIV_VMON

P1V5_DIV_VMON

P5V_DIV_VMON

=PP3V3_S0_VMON

ALL_SYS_PWRGD

P5VS3_PGOOD

P3V3S5_EN

MAKE_BASE=TRUE

=P5V3V3_REG_EN

MAKE_BASE=TRUE

S5_PWRGD

=PP3V3_S5_PWRCTL

=P5V_3V3_SUS_EN

PM_SUS_EN

MAKE_BASE=TRUE

=PP3V3_S5_PWRCTL

SMC_BATLOW_L

ALL_SYS_PWRGD

PM_SLP_SUS_L

VMON_Q3_BASE

CPUIMVP_VR_ON

PM_SLP_S3_R_L

MAKE_BASE=TRUE

PM_RSMRST_L

SUS_PGOOD_MR_L

16V

NO STUFF

16V X7R-CERM 0201

1000PF

10V

201

201201

201

10%10%

10%

10%10%

10%

Q7920

6

2

1

Q7925

6

2

1

C7912

1

2

R7974

12

R7911

1

2

C7910

1

2

C7986

1

2

R7986

1

2

C7981

1

2

C7987

1

2

R7987

1

2

R7931

12

Q7931

3

1

2

R7929

1

2

R7967

1

2

R7957

1

2

R7966

12

R7964

12

R7901

12

R7963

12

R7962

12

R7956

1

2

C7960

1

2

R7951

1

2

R7952

1

2

Q7950

5

7

1

6

4

8

2

3

R7954

12

R7955

12

U7930

4

2

3

15

6

C7931

1

2

R7933

1

2

C7930

1

2

R7968

12

Q7920

3

5

4

R7978

12

C7988

1

2

U7960

4

1

8

9

3 5 6

2

7

R7973

1

2

R7971

1

2

R7961

1

2

R7970

1

2

R7972

1

2

R7960

1

2

C7942

1

2

R7941

12

C7940

1

2

U7941

7

5

2

6

3

4

8

9

1

C7941

1

2

R7913

12

C7913

1

2

R7981

1

2

R7917

12

U7940

1

3

6

2

5

4

C7943

1

2

R7988

1

2

R7912

1

2

R7965

12

Q7925

3

5

4

R7953

12

R7915

12

U7970

2

1

3

6

4

C7970

1

2

R7930

1

2

051-9277

2.8.0

79 OF 109

62 OF 73

5

7

62

7

7 62

7

62

23 25 41 52 62

7

62

7

62

7

62

7

62

7

62

7

62

7

62

7

62

7

62

7

62

45

7

62

23 25 41 52 62

GND

THRM

ON

VIN_1

VIN_2

VOUT_1

VOUT_2

PAD

NC

OUT

IN

BI

IN

NC

NC NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Pull-ups on panel side,

4.7 kOhm to 3.3V

LED Backlight I/F

(DP_INT_AUX_CH_C_N)

Internal DP Connector: 518S0787

LCD Connector

DisplayPort I/F

CHECK IF LVDS_IG_PANEL_PWR GLITCHES ON POWER UP

(DP_INT_AUX_CH_C_P)

10%

10%10% 10%

50V

16V

201201

201

1000PF

0201

X7R-CERM

1000PF

MIN_NECK_WIDTH=0.20 MM

PP3V3_SW_LCD

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.30 MM

DP_INT_AUX_CH_C_P

DP_INT_HPD

DP_INT_ML_F_P<0>

LED_RETURN_3

DP_INT_AUX_CH_C_N

DP_INT_HPD_CONN

=I2C_TCON_SCL

I2C_TCON_SCL_R

LED_RETURN_2

LED_RETURN_5

LED_RETURN_6

DP_INT_AUX_CH_P

=I2C_TCON_SDA

LED_RETURN_1

PPVOUT_SW_LCDBKLT

DP_INT_ML_N<0>

DP_INT_ML_P<0>

DP_INT_AUX_CH_N

LCD_IG_PWR_EN

I2C_TCON_SDA_R

LED_RETURN_4

DP_INT_ML_F_N<0>

MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V

MIN_LINE_WIDTH=0.30 MM

PP3V3_SW_LCD_UF

=PP3V3_S3_LCD

1

518S0829

CONNTWIN-AX,P=0.4,30P,W-BOSS,HF

J9000

SYNC_DATE=07/28/2011

SYNC_MASTER=K21_MLB

Internal DisplayPort Connector

0402-LF

FERR-120-OHM-1.5A

MF

1/20W

5%

1M

PLACE_NEAR=J9000.24:1mm

1/20W

5%

1M

PLACE_NEAR=J9000.25:1mm

MF

5%

0

MF

1/20W

5%

0

1/20W

MF

44

66

9

66

9

8

66

9

66

9

65

6

65

6

65

6

65

6

65

6

65

6

9

1/20W

5%

100K

MF

1/20W

5%

100K

5%

0

MF

1/20W

100K

1/20W

MF

5%

PLACE_NEAR=J9000.14:2mm

F-RT-SM

CABLINE-CA

CRITICAL

OMIT_TABLE

0.1UF

0201

X5R-CERM

0201

0.1UF

X5R-CERM

0.1UF

X5R-CERM

0201

X5R-CERM

0.1UF

C0G-CERM

5%

603

PLACE_NEAR=J9000.3:2mm

MFET-2X2-8IN

FPF1009

CRITICAL

0.1UF

X5R

6.3V

1/20W

1K

5%

MF

6.3V X5R

0.1UF 10UF

603

X5R

6.3V

20%

L9004

12

C9012

1

2

C9011

1

2

R9014

1

2

C9009

1

2

U9000

617

2

3

4

5

C9017

1

2

C9015

1

2

C9024

12

C9025

12

C9020

12

C9021

12

J9000

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

31

32

33

34

35

36

37

38

39

4

40

41

5

6

7

8

9

R9050

1

2

R9060

12

R9080

1

2

R9070

1

2

R9061

12

R9062

12

R9017

1

2

R9018

1

2

051-9277

2.8.0

90 OF 109

63 OF 73

6

66

6

66

6

66

6

65

6

66

6

7

IN

OUT

IN

DPMLO+ DPMLO-

VDD

DP-

DP+

DDC_CLK

AUX+

AUX-

AUXIO_EN

AUXIOAUXIO+

THMPAD

GND

BIASIN

BIASOUT

DDC_DAT

CA_DETOUT

CA_DET

DP_PD

LSTX LSRX

HPDOUT

HPD

OUT

BI

IN

OUT

IN

BI

IN

DP_PWR

AUX_CHP

ML_LANE3P

ML_LANE3N

CONFIG1

AUX_CHN

RETURN

GND

ML_LANE0N

ML_LANE0P

CONFIG2

HOT_PLUG_DETECT

GND

ML_LANE1P ML_LANE1N

ML_LANE2P ML_LANE2N

SHIELD PINS

YA

B

C

VCC

GND

OUT

ISET_S3

V3P3OUT

ISET_S0

EN

S0

HV_EN

RSVD

GND

THRM

OUT

VHV

ISET_V3P3

RSVD

V3P3

PAD

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Y = B

TBT: LSX_A_R2P/P2R (P/N)

TBT: RX_1 Bias Sink

470k R’s for ESD protection

TBT: TX_0

TBT Dir

(Both D’s)

514-0818

TBT: LSX_R2P/P2R (P/N)

TBT: Unused

greater than or equal

(Both C’s)

TBT: TX_1

down HPD input with

Sink HPD range:

below

For J9400 TBT SMT pads

Nominal Min Max

requires two R’s per HV

Single R on ISET_V3P3 OK.

TBT Dir

DP Dir

ISET_Sx with CD3210.

ILIM = 40000 / RISET

(Both C’s)

For 12V systems:

12V: See

18.9V Max

Nominal Min Max

Low: 0 - 0.8V

High: 2.0 - 5.0V

(0-18.9V)

DP Dir

(0-18.9V)

(Both C’s)

to 100K (DPv1.1a).

3.3V/HV Power MUX

IHVS0/S3 1120mA 1090mA 1170mA (12W minimum)

V3P3 must be S4 to support

(3, 5, 17 & 19):

on AC-coupled signals.

DP Source must pull

wake from Thunderbolt devices.

Thunderbolt Connector A

Single-fault protection

IV3P3 1100mA 1030mA 1200mA IHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum) IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W)

10%

10% 10%

10%

10% 10%

10%

201

201 201

201201

201

201201

201

201 201

201

201 201

201

10V

0.01UF

0402

X7R-CERM

50V

0.01UF

0402

X7R-CERM

0.01UF

402

50V 50V

0402

TBT_A_D2R_C_N<1>

TBT_A_D2R_C_P<1>

16V 16V

16V

16V 16V

16V

330PF

0201

X7R-CERM

330PF

0201

X7R-CERM

34 70

1/20W

12

5%

MF

SIGNAL_MODEL=EMPTY

1K

MF

1/20W

5%

1K

SIGNAL_MODEL=EMPTY

MF

1/20W

5%

100K

MF

1/20W

5%

CRITICAL

GND_VOID=TRUE

SIGNAL_MODEL=EMPTY

650NH-5%-0.430MA-0.52OHM

0603

GND_VOID=TRUE

CRITICAL

0603

0402

20%

10UF

X5R-CERM

0201

0.1UF

0201

22UF

603

CRITICAL

20%

6.3V

X5R-CERM-1

CRITICAL

CASE-B2-SM

100UF

20%

6.3V

POLY-TANT

1/20W

1M

MF

5%

1M

MF

5% 1/20W

GND_VOID=TRUE

2.2K

MF

1/20W

5%

2.2K

GND_VOID=TRUE

MF

1/20W

5%

FERR-120-OHM-3A

0603

34

0.1UF

X5R

TSLP-2-7

CRITICAL

BAR90-02LRH

SIGNAL_MODEL=TBTPIN

GND_VOID=TRUE

CRITICAL

TSLP-2-7

GND_VOID=TRUE

SIGNAL_MODEL=TBTPIN

BAR90-02LRH

470K

MF

1/20W

GND_VOID=TRUE

5%

MF

470K

1/20W

GND_VOID=TRUE

5%

34 70

GND_VOID=TRUE

470K

1/20W MF

5%

470K

1/20W MF

GND_VOID=TRUE

5%

34 36

62

MF

36.5K

1% 1/20W

25V

0.1UF

X5R

HVQFN

CBTL05023

CRITICAL

SIGNAL_MODEL=TBT_MUX

5%

1/20W

MF

100K

1/20W MF

5%

X5R-CERM

0.1UF

0201

0.1UF

0201

X5R-CERM

34

8

25

34

5%

1/20W

MF

1M

10K

MF

1/20W

5%

0201

X5R-CERM

0.1UF

34

34 70

0.1UF

X5R-CERM

0201

X5R-CERM

0.1UF

0201

34 70

470K

5%

1/20W

MF

5%

1/20W

MF

470K

GND_VOID=TRUEGND_VOID=TRUEGND_VOID=TRUE

1%

MF

22.6K

1/20W

TBTHV:P15V

MF

1/20W

1%

22.6K

TBTHV:P15V

CERM-X5R-1

GND_VOID=TRUE

4V

20%

0.47UF

GND_VOID=TRUE

CERM-X5R-1

4V

20%

0.47UF

20%

4V

CERM-X5R-1

GND_VOID=TRUE

0.47UF

GND_VOID=TRUE

20%

4V

TBTHV:P15V

1/20W

22.6K

MF

1%

TBTHV:P15V

1/20W

22.6K

MF

1%

0.22UF

20% X5R

6.3V 0201

X5R

6.3V

20%

0.22UF

0201

GND_VOID=TRUE

0.22UF

0201

6.3V

20% X5R

GND_VOID=TRUE

0201

0.22UF

6.3V

20% X5R

GND_VOID=TRUE

0201

6.3V

X5R

20%

0.22UF

GND_VOID=TRUE

0201

0.22UF

6.3V

20% X5R

0201

0.22UF

6.3V

20% X5R

0201

X5R

20%

6.3V

0.22UF

X5R-CERM

0201

25V

X5R-CERM

0201

X5R-CERM

25V

CRITICAL

74AUP1T97

SOT891

CERM

20%

0.1UF

34

QFN

CRITICAL

TBTHV:P12V

RES,MF,1/20W,17.8K,1,0201

118S0145

R9410,R9413

2

RES,MF,1/20W,17.8K,1,0201

118S0145

R9411,R9414

2

TBTHV:P12V

SYNC_DATE=10/03/2011

SYNC_MASTER=J11_MLB

Thunderbolt Connector A

TBT_A_LSRX

PP3V3_SW_TBTAPWR

TBT_A_LSRX_UNBUF

TBT_A_LSTX

DP_TBTPA_HPD

TBT_A_DP_PWRDN

TBT_A_HPD

TBT_A_CONFIG1_RC

TBT_A_CONFIG1_BUF

DP_TBTSNK0_DDC_DATA

TBT_A_CIO_SEL

DP_AUXIO_EN

DP_TBTSNK0_DDC_CLK

DP_A_LSX_ML_N<1>

DP_A_LSX_ML_P<1>

PP3V3_SW_TBTAPWR

DP_A_AUXCH_DDC_N DP_A_AUXCH_DDC_P

VOLTAGE=3.3V

TBT_A_BIAS

DP_TBTPA_ML_C_N<1>

DP_TBTPA_ML_N<1>

DP_TBTPA_AUXCH_C_N

DP_TBTPA_ML_C_P<1>

DP_TBTPA_AUXCH_C_P

DP_TBTPA_ML_P<1>

DP_TBTPA_AUXCH_P

DP_TBTPA_AUXCH_N

DP_A_LSX_ML_N<1>

TBT_A_D2R1_AUXDDC_P

TBT_A_D2R_N<1>

TBT_A_HPD

DP_TBTPA_ML_P<3>

TBTACONN_7_C

VOLTAGE=18.9V

DP_A_LSX_ML_P<1>

TBT_A_D2R_P<1>

TBT_A_CONFIG1_RC

DP_A_AUXCH_DDC_P

TBT_A_R2D_C_N<1>

TBT_A_R2D_N<1>

TBT_A_BIAS

DP_TBTPA_ML_C_N<3>

DP_TBTPA_ML_N<3>

DP_TBTPA_ML_C_P<3>

TBT_A_R2D_C_P<1>

TBT_A_R2D_C_N<0>

TBT_A_D2R_C_P<0>

PP3V3RHV_SW_TBTAPWR

TBT_A_D2R_N<0>

TBT_A_D2R_P<0>

TBT_A_R2D_C_P<0>

TBT_A_R2D_P<0>

TBTACONN_1_C

MIN_LINE_WIDTH=0.38 MM

VOLTAGE=18.9V

MIN_NECK_WIDTH=0.20 MM

TBT_A_R2D_P<1>

TBT_A_R2D_N<0>

TBTAPWRSW_ISET_V3P3

=PPHV_SW_TBTAPWRSW

MIN_NECK_WIDTH=0.20 MM VOLTAGE=15V

MIN_LINE_WIDTH=0.38 MM

PPHV_SW_TBTAPWR

TBT_A_HV_EN

=TBT_S0_EN

=TBTAPWRSW_EN

TBTAPWRSW_ISET_S0

MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V

MIN_LINE_WIDTH=0.38 MM

PP3V3_SW_TBTAPWR

TBTAPWRSW_ISET_S3

TBT_A_CONFIG2_RC

MIN_LINE_WIDTH=0.38 MM

TBT_A_D2R_C_N<0>

VOLTAGE=18.9V

GND_VOID=TRUEGND_VOID=TRUE

SIGNAL_MODEL=EMPTY

CERM-X5R-1

DP_A_AUXCH_DDC_N

C0G-NP0

5%

30PF

C0G-NP0

5%

30PF

0402

VOLTAGE=15V

MIN_NECK_WIDTH=0.20 MM

50V

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM

TBTACONN_20_RC

MDP-J11

F-RT-TH

MIN_NECK_WIDTH=0.20 MM

CRITICAL

GND_VOID=TRUE

TBTAPWRSW_ISET_S0_R

TBTAPWRSW_ISET_S3_R

TBT_A_D2R1_AUXDDC_N

650NH-5%-0.430MA-0.52OHM

MIN_LINE_WIDTH=0.38 MM

=PP3V3_S4_TBTAPWRSW

X5R-CERM

0.1UF

CERM-X5R

6.3V

CD3210A0RGP

25V25V

X5R-CERM

0603

4.7UF

10%

L9400

12

C9400

1

2

R9401

1

2

C9401

1

2

R9494

1

2

R9495

1

2

R9441

1

2

L9498

12

L9499

12

C9486

1

2

C9485

1

2

C9481

1

2

C9480

1

2

C9487

1

2

R9452

1

2

R9451

1

2

C9494

1

2

C9495

1

2

R9498

1

2

R9499

1

2

C9410

1

2

D9499

AK

D9498

AK

R9470

1

2

R9471

1

2

R9473

1

2

R9472

1

2

R9412

1

2

C9411

1

2

U9420

7

8

2

23

22

1

24

1816

5

4

10

11

6

20

19

9

21

1712

13

14

25

3

15

R9429

1

2

R9428

1

2

C9420

1

2

C9421

1

2

R9426

1

2

R9427

1

2

C9425

1

2

C9430

12

C9431

12

R9479

12

R9478

12

J9400

18

16

4 6

20

1

713

814

2

21222324252627

28

5

3

11

9

17

15

12

10

19

R9410

1

2

R9411

1

2

C9415

1

2

C9474

12

C9475

12

C9476

12

C9477

12

R9413

1

2

R9414

1

2

C9433

12

C9432

12

C9470

12

C9471

12

C9472

12

C9473

12

C9479

12

C9478

12

C9405

12

C9406

12

C9402

1

2

U9460

2

3

1

6

5

4

C9460

1

2

U9410

5

123

4

13

11 10

9

8

12 14

1516

17

21

19 20

18

6 7

C9498

1

2

C9499

1

2

051-9277

2.8.0

94 OF 109

64 OF 73

7

64

64 70

7

64

64 70

64

70

64 70

70

64

70

64 70

70

64

64 70

70

64

70

64 70

70

7

64

VDDIO

VIN

VLDO

SW_0 SW_1

FB

OUT3

OUT2

OUT1

OUT4 OUT5 OUT6

GND_SW

GND_S

GND_L

GND_SW

VSYNC

ISET

FILTER

FSET

SCLK

PWM

SDA

FAULT

EN

IN

D

SG

D

SG

OUT

IN

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

see spec for others

Fpwm=9.62kHz

PPBUS S0 LCDBkLT FET

Addr: 0x58(Wr)/0x59(Rd)

(EEPROM should set EN_I_RES=1)

I_LED=369/Riset

measurement on LED strings.

10.2 ohm resistors for current

AND PPBUS_SW_BKL

THERE IS A SENSE RESISTOR BETWEEN

LOADING

0.65 A (EDP)

P-TYPE

MOSFET

CHANNEL

FDC638APZ

43 mOhm @4.5V

RDS(ON)

*C9797 AND C9799 SHOULD BE PLACED IN T-BONE FOR ACOUSTICS

*PPBUS_SW_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.

I_LED=20.3mA

ON THE SENSOR PAGE

*LCD_BKLT_PWM SHOULD BE AWAY FROM BOOST CIRCUIT

PPBUS_SW_LCDBKLT_PWR

PLACE_NEAR=U9701.A5:3mm

X7R-CERM

50V

220PF

PLACE_NEAR=C9797.1:5mm

PLACE_NEAR=D9701.2:3mm

PLACE_NEAR=D9701.2:5mm

1210-1

PPBUS_SW_LCDBKLT_PWR_SW

5%

16V

0.1UF

0402

X7R-CERM

0.1UF

402

X5R

X5RX5R

X5R

X5R X5R

VOLTAGE=50V

50V 50V

5%

25V

25V25V

0201

NPO-C0G

33PF

1/20W

PLACE_NEAR=U9701.C4:4mm

BKL_VSYNC_R

=PP5V_S0_BKL

=PPBUS_SW_BKL

LCDBKLT_EN_DIV

=PPBUS_S0_LCDBKLT

BKL_PWM

=PP3V3_S0_BKL_VDDIO

BKL_FSET

LCD_BKLT_PWM

=I2C_BKL_1_SDA BKL_SDA

=I2C_BKL_1_SCL

BKL_EN

PPBUS_SW_LCDBKLT_PWR

BKL_ISET

LCDBKLT_EN_L

BKLT_PLT_RST_L

LCD_BKLT_EN

LCDBKLT_DISABLE

MIN_LINE_WIDTH=0.5 mm

LED_RETURN_5

MIN_NECK_WIDTH=0.20 mm

LED_RETURN_4

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

LED_RETURN_1

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

LED_RETURN_2

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

LED_RETURN_3

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

LED_RETURN_6

VOLTAGE=12.6V

PPBUS_SW_LCDBKLT_PWR

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm

MIN_NECK_WIDTH=0.375 MM

PPVOUT_SW_LCDBKLT

MIN_LINE_WIDTH=0.5 MM

PLACE_SIDE=BOTTOM

TP_BKL_FAULT

MIN_LINE_WIDTH=0.1 MM

PPVOUT_SW_LCDBKLT_FB

MIN_NECK_WIDTH=0.1 MM

GND_BKL_SGND

VOLTAGE=0V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.4 mm

PPBUS_S0_LCDBKLT_FUSED

MIN_NECK_WIDTH=0.150 MM

SWITCH_NODE=TRUE DIDT=TRUE

MIN_LINE_WIDTH=0.5 MM

BKL_ISEN6

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

BKL_ISEN5

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

BKL_FLTR

BKL_ISEN1

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

BKL_ISEN2

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

BKL_ISEN3

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

BKL_ISEN4

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

BKL_SCL

BKLT:ENG

3

R9717,R9718,R9719

103S0198

RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM

BKLT:ENG

RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM

3

R9720,R9721,R9722

103S0198

SYNC_DATE=07/28/2011

SYNC_MASTER=K21_MLB

LCD Backlight Driver

44

8

SM

PLACEMENT_NOTE=Keep away from noise nodes(E4, A1, A2, B1, B2 pins)

603-1

PLACE_NEAR=U9701.D1:5mm

1UF

0

1/16W MF-LF

BKLT:PROD

PLACE_NEAR=U9701.E5:10mm

BOTTOM

BKLT:PROD

1/16W MF-LF

0

PLACE_NEAR=U9701.C5:10mm

BOTTOM

0

MF-LF

1/16W

BKLT:PROD

PLACE_NEAR=U9701.D5:10mm

BOTTOM

63

6

63

6

63

6

63

6

63

6

63

6

MF-LF

1/16W

BKLT:PROD

0

BOTTOM

PLACE_NEAR=U9701.E3:10mm

0

1/16W MF-LF

BKLT:PROD

PLACE_NEAR=U9701.E2:10mm

BOTTOM

0

1/16W MF-LF

BKLT:PROD

PLACE_NEAR=U9701.E1:10mm

BOTTOM

RB160M-60G

PLACE_NEAR=L9701.2:3mm

SOD-123

CRITICAL

PLACE_NEAR=L9701.1:3mm

CRITICAL

10UF

805

PLACE_NEAR=L9701.1:3mm

PLACE_NEAR=U9701.D1:3mm

0.01UF

6.3V

MF

1/20W

10K

1/20W

90.9K

MF

1%

MF

33

0

MF

1/20W

MF

0

MF

10K

1/20W

1% 1/20W

100K

MF

200K

1/20W

1%

MF

1/20W

1%

18.2K

SM

CRITICAL

FDC638APZ_SBMS001

SSOT6-HF

1%

301K

MF

1/20W

603-HF

3AMP-32V-467

BOTTOM

SOT563

SSM6N15FEAPE

1%

147K

MF

1/20W

SOT563

SSM6N15FEAPE

8

25

CRITICAL

25-BUMP-MICRO

LP8550

CRITICAL

15UH-2.8A

PIMB053T-SM

1210-1

10UF

CRITICAL CRITICAL

10UF

0402

10V

201

201 201

201

10%

10%10%

10%

10% 10%

C9712

1

2

C9713

1

2

D9701

AK

R9722

12

R9721

12

R9720

12

R9718

12

R9719

12

R9717

12

C9710

1

2

XW9710

12

C9799

1

2

C9797

1

2

L9701

12

U9701

A3

C3

A5

C2

B4

E4B5A1

A2

B3

E5

D5

C5

E3

E2

E1

A4

D3

D4

B1

B2

C4C1D1

D2

Q9707

3

5

4

R9789

1

2

Q9707

6

2

1

F9700

12

R9788

1

2

C9782

1

2

Q9706

1256

3

4

XW9720

12

R9714

1

2

R9731

12

R9715

1

2

R9741

12

R9753

12

R9757

12

R9704

12

R9716

1

2

R9755

1

2

C9711

1

2

C9714

1

2

C9704

1

2

C9796

1

2

051-9277

2.8.0

97 OF 109

65 OF 73

7

8

7

65

8

65

8

63

6

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

PCI-Express Interface Constraints

Note: DisplayPort tables are on Page 103

CPU PCIE Spacing

Note: CPU_8MIL and CPU_ITP can be converted

back to TABLE_SPACING_RULE once rdar://10308147 is resolved

ELECTRICAL_CONSTRAINT_SET

CPU Signal Constraints

PCIE Clock Spacing

PCH PCIE Spacing

SOURCE: 471984_Chief_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback.

DMI/FDI

PCIe SSD

DP

(FSB_CPURST_L)

(XDP_BPM_L_R_CFG)

SPACING

PHYSICAL

NET_TYPE

CPU Net Properties

PCIE_PCH_TXPCIE_PCH_TX

*

PCIE_TX2TX

PCIE_RX2RX

*

PCIE_PCH_RX PCIE_PCH_RX

*

PCIE_PCH_TX

*_PCH_TX

PCIE_TX2OTHERTX

PCIE_PCH_RX

*

PCIE_RX2OTHERRX

*_PCH_RX

PCIE_2OTHERHS

*_RX

*

PCIE_PCH_TX

PCIE_PCH_RX

*

PCIE_2OTHERHS

*_TX

PCIE_PCH_TX

PCIE_2OTHERHS

*

*_TX

*_PCH_RX

*

PCIE_TX2RX

PCIE_PCH_TX

*_PCH_TX

*

PCIE_RX2TX

PCIE_PCH_RX

*_RX

*

PCIE_2OTHERHS

PCIE_PCH_RX

PCIE_PCH_TX

*

PCIE_2OTHER

*

PCIE_PCH_RX

**

PCIE_2OTHER

PCIE_CPU_RX

*

PCIE_2OTHER

*

PCIE_CPU_TX

**

PCIE_2OTHER

PCIE_CPU_RX

*

PCIE_2OTHERHS

*_RX

*

PCIE_CPU_TX

*_RX

PCIE_2OTHERHS

PCIE_CPU_RX

*_TX

*

*_CPU_TX

PCIE_CPU_TX

*

PCIE_TX2OTHERTX

*_CPU_RX

PCIE_RX2OTHERRX

*

PCIE_CPU_RX

*

PCIE_RX2RX

PCIE_CPU_RX

PCIE_CPU_TX

*

PCIE_TX2TX

PCIE_CPU_TX

?

=2x_DIELECTRIC

CPU_AGTL

TOP,BOTTOM

**

CPU_COMP

CPU_COMP_2OTHER

CPU_COMP_2SELF

*

CPU_COMPCPU_COMP

?

TOP,BOTTOM

=5x_DIELECTRIC

PCIE_TX2OTHERTX

?

TOP,BOTTOM

PCIE_RX2OTHERRX

=5x_DIELECTRIC

?

=7x_DIELECTRIC

TOP,BOTTOMPCIE_TX2RX

TOP,BOTTOM?=6x_DIELECTRIC

PCIE_2OTHERHS

PCIE_2OTHER

=5x_DIELECTRIC

?

TOP,BOTTOM

PCIE_TX2OTHERTX

=4x_DIELECTRIC

* ?

?

PCIE_TX2TX

=2.5x_DIELECTRIC

*

=2.5x_DIELECTRIC

PCIE_RX2RX

?*

* ?

PCIE_RX2OTHERRX

=4x_DIELECTRIC

?*

PCIE_TX2RX

=6x_DIELECTRIC

*

=3x_DIELECTRIC

?

PCIE_2OTHER

*

PCIE_RX2TX

?

=6x_DIELECTRIC

*

CLK_PCIE

*

CLK_PCIE_2OTHER

*

CLK_PCIE CLK_PCIE

CLK_PCIE_2SELF

CPU_VCCSENSE_2OTHER

?

TOP,BOTTOM

=10x_DIELECTRIC

=45_OHM_SE

*

=STANDARD

CPU_45S

=45_OHM_SE=45_OHM_SE =45_OHM_SE

=STANDARD

CPU_8MIL_2ANY

* ?

8 MIL

=27P4_OHM_SE

0.100 MM

*

CPU_27P4S

=27P4_OHM_SE =27P4_OHM_SE 0.100 MM=27P4_OHM_SE

CPU_VCCSENSE

CPU_VCCSENSE_2SELF

*

CPU_VCCSENSE

TOP,BOTTOM

?

PCIE_RX2TX

=7x_DIELECTRIC

PCIE_CPU_TX

*_TX

*

PCIE_2OTHERHS

*

PCIE_RX2TX

PCIE_CPU_RX

*_CPU_TX

PCIE_TX2RX

*

*_CPU_RX

PCIE_CPU_TX

CLK_PCIE_2SELF

* ?

=4x_DIELECTRIC

CPU_VCCSENSE_2OTHER

**

CPU_VCCSENSE

CLK_PCIE_2OTHER =10x_DIELECTRIC

TOP,BOTTOM

?

=5x_DIELECTRIC

?

TOP,BOTTOMPCIE_RX2RX

?*

=4x_DIELECTRIC

PCIE_2OTHERHS

?

TOP,BOTTOM

=5x_DIELECTRIC

PCIE_TX2TX

=6x_DIELECTRIC

* ?

CLK_PCIE_2OTHER

?

TOP,BOTTOM

=6x_DIELECTRIC

CPU_VCCSENSE_2SELF

=6x_DIELECTRIC

* ?

CPU_COMP_2OTHER

=4x_DIELECTRIC

* ?

CPU_COMP_2SELF

**

CPU_ITP_2ANY

CPU_ITP

CPU_8MIL

CPU_8MIL_2ANY

**

?*

CPU_AGTL

=STANDARD

SYNC_MASTER=J13_CONSTRAINTS

CPU Constraints

SYNC_DATE=01/11/2012

=80_OHM_DIFF =80_OHM_DIFF=80_OHM_DIFF =80_OHM_DIFF

=80_OHM_DIFF

CLK_PCIE_80D

*

=80_OHM_DIFF

CLK_PCIE_2SELF =6x_DIELECTRIC

?

TOP,BOTTOM

=80_OHM_DIFF=80_OHM_DIFF

=80_OHM_DIFF

*

PCIE_80D =80_OHM_DIFF=80_OHM_DIFF

CPU_VCCSENSE_2OTHER

=6x_DIELECTRIC

* ?

CPU_VCCSENSE_2SELF

=4x_DIELECTRIC

* ?

=4x_DIELECTRIC

* ?

CPU_ITP_2ANY

CPU_COMP_2SELF?TOP,BOTTOM

=6x_DIELECTRIC

TOP,BOTTOM

CPU_COMP_2OTHER

?

=10x_DIELECTRIC

CPU_45S

XDP_DBRESET_L

CPU_ITP

CPU_45S

PM_SYNC

CPU_AGTL

CPU_PECI

CPU_PECI CPU_COMP

CPU_45S

FDI_INT

CPU_AGTL

PCIE_80DFDI_DATA

FDI_DATA_N<7:0>

PCIE_PCH_RX

DMI_N2S

DMI_N2S_P<3:0>

PCIE_80D

PCIE_PCH_RX

DMI_S2N

PCIE_80D

DMI_S2N_N<3:0>

PCIE_PCH_TX

DMI_S2N

DMI_S2N_P<3:0>

PCIE_80D

PCIE_PCH_TX

CPU_ITP

XDP_CPU_PREQ_L

CPU_45S

CPU_SM_RCOMP

CPU_27P4S

CPU_SM_RCOMP<1>

CPU_COMP

CPU_SM_RCOMP<0>

CPU_27P4S

CPU_SM_RCOMP CPU_COMP

CPU_27P4S

CPU_SM_RCOMP

CPU_SM_RCOMP<2>

CPU_COMP

CPU_45S

CPU_CFG<11..0>

CPU_ITP

CPU_45S

CPU_CATERR_L

CPU_AGTL

CPU_45S

CPU_PROCHOT_L

CPU_AGTL

CPU_45S

CPU_VCCIO_SEL

CPU_AGTL

CPU_45S

CPU_PWRGD

CPU_AGTL

DMI_CLK100M

DMI_CLK100M_CPU_P

CLK_PCIE_80D CLK_PCIE

CPU_45S

PM_THRMTRIP_L

CPU_8MIL

DMI_CLK100M

DMI_CLK100M_CPU_N

CLK_PCIE_80D CLK_PCIE

DPLL_REF_CLK120M

DPLL_REF_CLKP

CLK_PCIECLK_PCIE_80D

DPLL_REF_CLKN

DPLL_REF_CLK120M

CLK_PCIECLK_PCIE_80D

CLK_PCIE_80D

ITPCPU_CLK100M

ITPCPU_CLK100M_P

CLK_PCIE

ITPCPU_CLK100M

CLK_PCIE_80D

ITPCPU_CLK100M_N

CLK_PCIE

ITPCPU_CLK100M

ITPXDP_CLK100M_P

CLK_PCIE_80D CLK_PCIE

ITPCPU_CLK100M

CLK_PCIE_80D

ITPXDP_CLK100M_N

CLK_PCIE

ITPCPU_CLK100M

XDP_CPU_CLK100M_N

CLK_PCIECLK_PCIE_80D

CPU_COMP

CPU_PEG_COMP

CPU_27P4S

CPU_COMP

EDP_COMP

CPU_27P4S

XDP_CPU_TDO

XDP_TDO CPU_ITPCPU_45S

CPU_ITP

XDP_BPM_L<7..4>

XDP_BPM_L_R_CFG

CPU_45S

CPU_CFG<15..12>

CPU_ITPCPU_45S

CPU_VCCSENSE_P

CPU_VCCSENSE

SENSE_1TO1_P2MM

CPU_VCCSENSE

CPU_VCCSENSE_N

CPU_VCCSENSE

SENSE_1TO1_P2MM

CPU_VCCSENSE CPU_VCCIOSENSE

CPU_VCCIOSENSE_P

SENSE_1TO1_P2MM

CPU_VCCSENSE

CPU_VCCIOSENSE

CPU_VCCIOSENSE_N

SENSE_1TO1_P2MM

CPU_VCCSENSE

CPU_VALSENSE

CPU_VDDQ_SENSE_P

CPU_27P4S

CPU_VCCSENSE

CPU_AXG_SENSE_N

SENSE_1TO1_P2MM

CPU_VCCSENSE

CPU_AXG_SENSE

CPU_27P4S

CPU_VALSENSE

CPU_VDDQ_SENSE_N

CPU_VCCSENSE

CPU_VALSENSE

CPU_27P4S

CPU_AXG_VALSENSE_P

CPU_VCCSENSE

CPU_VALSENSE

CPU_27P4S

CPU_VCCSENSE

CPU_AXG_VALSENSE_N

CPU_27P4S

CPU_VALSENSE CPU_VCCSENSE

CPU_VCC_VALSENSE_P

CPU_VALSENSE

CPU_27P4S

CPU_VCCSENSE

CPU_VCC_VALSENSE_N

CPU_VIDALERT_L

CPU_SVIDALERT_L

CPU_45S

CPU_COMP

CPU_45S

CPU_SVIDSCLK

CPU_VIDSCLK

CPU_COMP

CPU_VIDSOUT

CPU_45S

CPU_SVIDSOUT CPU_COMP

PCIE_80D

PCIE_CPU_RX

PCIE_CPU_MUX_D2R

PCIE_SSD_D2R_N<0> PCIE_SSD_D2R_MUX_OUT_P

PCIE_80D

PCIE_CPU_RX

PCIE_SSD_R2D_C_N<1>

PCIE_80D

PCIE_CPU_RX

PCIE_CPU_SSD_R2D

PCIE_SSD_R2D_N<1>

PCIE_80D

PCIE_CPU_TX

PCIE_SSD_D2R_N<1>

PCIE_80D

PCIE_CPU_RX

PCIE_CPU_SSD_D2R

PCIE_SSD_D2R_C_N<1>

PCIE_80D

PCIE_CPU_RX

PCIE_SSD_D2R_P<1>

PCIE_80D

PCIE_CPU_RX

PCIE_CPU_SSD_D2R

PCIE_SSD_R2D_C_P<1>

PCIE_80D

PCIE_CPU_RX

PCIE_CPU_SSD_R2D

PCIE_SSD_D2R_MUX_OUT_N

PCIE_80D

PCIE_CPU_RX

PCIE_SSD_D2R_C_P<1>

PCIE_80D

PCIE_CPU_RX

PCIE_CLK100M_SSD

PCIE_CLK100M_SSD_P

CLK_PCIECLK_PCIE_80D

DP_80D

DP_TX

DP_INT_ML_F_P<3..0>

DP_INT_ML

DP_80D

DP_INT_ML_N<3..0>

DP_TX

DP_80D

DP_INT_ML_F_N<3..0>

DP_TX

DP_INT_AUXCH

DP_80D

DP_INT_AUX_CH_C_P

DP_AUX

DP_80D DP_AUX

DP_INT_AUX_CH_P

DP_80D

DP_INT_AUXCH

DP_INT_AUX_CH_C_N

DP_AUX

DP_80D

DP_INT_AUX_CH_N

DP_AUX

CLK_PCIE_80D

ITPCPU_CLK100M

XDP_CPU_CLK100M_P

CLK_PCIE

XDP_TDI

XDP_CPU_TDI

CPU_ITPCPU_45S

XDP_CPU_TCK

CPU_ITPCPU_45SXDP_TCK

CPU_AXG_SENSE_P

CPU_AXG_SENSE

SENSE_1TO1_P2MM

CPU_VCCSENSE

PCIE_80D

PCIE_SSD_R2D_P<1>

PCIE_CPU_TX

PCIE_CLK100M_SSD

CLK_PCIECLK_PCIE_80D

PCIE_CLK100M_SSD_N

DP_INT_ML

DP_80D

DP_TX

DP_INT_ML_P<3..0>

CPU_ITP

XDP_OBSDATA_B<3..0>

CPU_45S

XDP_CPURST_L

CPU_45S CPU_ITP

CPU_ITP

XDP_BPM_L<3..0>

XDP_BPM_L

CPU_45S

XDP_CPU_TRST_L

CPU_ITPCPU_45S

XDP_TRST_L

XDP_CPU_TMS

XDP_TMS CPU_ITPCPU_45S

CPU_45S

FDI_FSYNC<1..0>

CPU_AGTL

FDI_LSYNC<1..0>

CPU_AGTL

CPU_45S

PCIE_80D

DMI_N2S

DMI_N2S_N<3:0>

PCIE_PCH_RX

PCIE_80D

FDI_DATA_P<7:0>

FDI_DATA

PCIE_PCH_RX

CPU_45S

PM_MEM_PWRGD

CPU_AGTL

XDP_CPU_PRDY_L

CPU_ITPCPU_45S

PCIE_SSD_R2D_C_P<0>

PCIE_80D

PCIE_CPU_MUX_R2D

PCIE_CPU_TX

PCIE_80D

PCIE_SSD_D2R_P<0>

PCIE_CPU_RX

PCIE_CPU_MUX_D2R

PCIE_80D

PCIE_CPU_TX

PCIE_SSD_R2D_MUX_IN_N

PCIE_SSD_R2D_MUX_IN_P

PCIE_80D

PCIE_CPU_TX

PCIE_80D

PCIE_SSD_R2D_C_N<0>

PCIE_CPU_MUX_R2D

PCIE_CPU_TX

051-9277

2.8.0

100 OF 109

66 OF 73

10 23 25

10 17

10 19 42

9

17

9

17

9

17

9

17

9

17

10 23

10

9

23

10 41

10 41 42 57

12

10 19 23

10 16

10 19 42

10 16

8

10

8

10

10 16

16 23

23

9

10 23

9

23

12 57

12 59

12

12 57

12

9

12 57

8

38

8

38

6

38

6 8

38

6 8

38

8

38

6

16 38

6

63

9

63

6

63

6

63

9

63

6

63

9

63

23

10 23

12 57

6

38

6

16 38

9

63

23

10 23

9

17

9

17

9

17

9

17

10 17 26

10 23

8

38

8

38

8

38

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

SPACING

NET_TYPE

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

Memory Net Properties

Memory to Power Spacing

Memory to GND Spacing

Memory Bus Spacing Group Assignments

Spacing Rule Sets

Memory Bus Constraints

=8.6x_DIELECTRIC

=5.7x_DIELECTRIC

=2x_DIELECTRIC

=GND_P2MM

=PWR_P2MM

=4x_DIELECTRIC

PalPilot Spacing

=4x_DIELECTRIC

=3x_DIELECTRIC

"Real" Spacing

=2x_DIELECTRIC

=GND_P2MM

=PWR_P2MM

=6x_DIELECTRIC

=5.7x_DIELECTRIC

=8.6x_DIELECTRIC

MEM_*

GND *

MEM_2GND

=45_OHM_SE =45_OHM_SE

*

MEM_45S

=45_OHM_SE =45_OHM_SE =45_OHM_SE =45_OHM_SE

=72_OHM_DIFF

MEM_72D

*

=72_OHM_DIFF

=72_OHM_DIFF=72_OHM_DIFF =72_OHM_DIFF =72_OHM_DIFF

=80_OHM_DIFF

*

=80_OHM_DIFF=80_OHM_DIFF=80_OHM_DIFF

=80_OHM_DIFF

MEM_80D

=6x_DIELECTRIC

MEM_2OTHER

?*

DEFAULT

**

MEM_PWR

MEM_B_DATA_2

MEM_2OTHER

**

MEM_2OTHER

MEM_B_DATA_3

**

MEM_B_DATA_4

MEM_2OTHER

**

MEM_B_DATA_5

MEM_2OTHER

**

MEM_B_DQS_1

MEM_2OTHER

**

MEM_2OTHER

*

MEM_B_DQS_2

*

MEM_2OTHER

*

MEM_B_DQS_3

*

MEM_2OTHER

*

MEM_B_DQS_6

*

MEM_2OTHER

*

MEM_B_DQS_5

*

MEM_2OTHER

*

MEM_B_DQS_4

*

MEM_2OTHER

*

MEM_A_DQS_1

*

MEM_2OTHER

*

MEM_A_DQS_0

*

MEM_2OTHER

*

MEM_A_DATA_0

*

MEM_2OTHER

*

MEM_A_DATA_1

*

MEM_2OTHER

*

MEM_A_DATA_6

*

MEM_2OTHER

*

MEM_A_DATA_7

*

MEM_2OTHER

*

MEM_A_DATA_5

*

MEM_2OTHER

*

MEM_A_DATA_4

*

MEM_2OTHER

*

MEM_A_DATA_3

*

MEM_2OTHER

*

MEM_A_DATA_2

*

MEM_2OTHER

*

MEM_B_DATA_0

*

MEM_2OTHER

*

MEM_B_DATA_1

*

MEM_2OTHER

*

MEM_B_DQS_7

*

MEM_CLK MEM_CLK

*

MEM_CLK2CLK

MEM_CMD MEM_CMD

*

MEM_CMD2CMD

MEM_CMD

MEM_CTRL

*

MEM_CMD2CTRL

MEM_CTRL MEM_CTRL

*

MEM_CTRL2CTRL

*

MEM_A_DQS_0

MEM_A_DATA_0

MEM_DQS2OWNDATA

*

MEM_DQS2OWNDATA

MEM_A_DQS_1

MEM_A_DATA_1

*

MEM_DQS2OWNDATA

MEM_A_DQS_6

MEM_A_DATA_6

*

MEM_DQS2OWNDATA

MEM_A_DQS_7

MEM_A_DATA_7

*

MEM_DQS2OWNDATA

MEM_A_DQS_5

MEM_A_DATA_5

*

MEM_DQS2OWNDATA

MEM_A_DQS_4

MEM_A_DATA_4

*

MEM_DQS2OWNDATA

MEM_A_DQS_3

MEM_A_DATA_3

*

MEM_DQS2OWNDATA

MEM_A_DQS_2

MEM_A_DATA_2

*

MEM_DQS2OWNDATA

MEM_B_DATA_0

MEM_B_DQS_0

*

MEM_DQS2OWNDATA

MEM_B_DQS_4

MEM_B_DATA_4

*

MEM_DQS2OWNDATA

MEM_B_DQS_5

MEM_B_DATA_5

*

MEM_DQS2OWNDATA

MEM_B_DQS_6

MEM_B_DATA_6

*

MEM_DQS2OWNDATA

MEM_B_DQS_3

MEM_B_DATA_3

*

MEM_DQS2OWNDATA

MEM_B_DQS_2

MEM_B_DATA_2

*

MEM_DQS2OWNDATA

MEM_B_DQS_7

MEM_B_DATA_7

MEM_2OTHERMEM

*

MEM_*MEM_*

*

MEM_DATA2SELF

MEM_*_DATA_*

=SAME

MEM_2PWR

*

MEM_PWR

MEM_*

MEM_2OTHER

*

MEM_A_DQS_2

*

MEM_2OTHER

*

MEM_A_DQS_3

*

MEM_2OTHER

*

MEM_A_DQS_4

*

MEM_2OTHER

*

MEM_A_DQS_5

*

MEM_2OTHER

*

MEM_A_DQS_6

*

MEM_2OTHER

*

MEM_A_DQS_7

*

MEM_2OTHER

*

MEM_B_DQS_0

*

MEM_DQS2OWNDATA

*

MEM_B_DQS_1

MEM_B_DATA_1

SYNC_MASTER=J13_CONSTRAINTS

Memory Constraints

SYNC_DATE=01/11/2012

*

MEM_2OTHER

MEM_B_DATA_7

*

MEM_2OTHER

*

MEM_B_DATA_6

*

MEM_CTRL

**

MEM_2OTHER

MEM_CMD

**

MEM_2OTHER

MEM_CLK

**

MEM_2OTHER

=GND_P2MM

?*

MEM_2GND

=PWR_P2MM

?*

MEM_2PWR

=4x_DIELECTRIC

?*

MEM_2OTHERMEM

=6x_DIELECTRIC

?*

MEM_CLK2CLK

=3x_DIELECTRIC

?*

MEM_CTRL2CTRL

=2x_DIELECTRIC

?

MEM_DATA2SELF

*

=3x_DIELECTRIC

?

MEM_DQS2OWNDATA

*

=3x_DIELECTRIC

MEM_CMD2CMD

* ?

=3x_DIELECTRIC

?*

MEM_CMD2CTRL

MEM_A_DQS_P<3>

MEM_80D

MEM_A_DQS3

MEM_A_DQS_3

MEM_80D

MEM_A_DQS6

MEM_A_DQS_N<6>

MEM_A_DQS_6

MEM_80D

MEM_A_DQS7

MEM_A_DQS_N<7>

MEM_A_DQS_7

MEM_72D MEM_CLK

MEM_B_CLK

MEM_B_CLK_N<5..0>

MEM_PWR

PP1V5_S3RS0

MEM_45SMEM_A_DQ_BYTE4

MEM_A_DQ<39..32>

MEM_A_DATA_4

MEM_A_DQ<47..40>

MEM_45SMEM_A_DQ_BYTE5

MEM_A_DATA_5

MEM_B_DQS_4

MEM_80D

MEM_B_DQS4

MEM_B_DQS_P<4>

MEM_80D

MEM_B_DQS3

MEM_B_DQS_3

MEM_B_DQS_P<3>

MEM_80D

MEM_B_DQS_N<2>

MEM_B_DQS2

MEM_B_DQS_2

MEM_B_DQS3

MEM_80D

MEM_B_DQS_3

MEM_B_DQS_N<3>

MEM_80D

MEM_B_DQS2

MEM_B_DQS_2

MEM_B_DQS_P<2>

MEM_80D

MEM_B_DQS1

MEM_B_DQS_1

MEM_B_DQS_N<1>

MEM_B_DQS_P<1>

MEM_80D

MEM_B_DQS1

MEM_B_DQS_1

MEM_B_DQS_N<0>

MEM_80D

MEM_B_DQS0

MEM_B_DQS_0

MEM_45SMEM_B_DQ_BYTE7

MEM_B_DATA_7

MEM_B_DQ<63..56>

MEM_45SMEM_B_DQ_BYTE5

MEM_B_DATA_5

MEM_B_DQ<47..40>

MEM_45SMEM_B_DQ_BYTE4

MEM_B_DATA_4

MEM_B_DQ<39..32>

MEM_B_DQS5

MEM_B_DQS_N<5>

MEM_B_DQS_5

MEM_80D

MEM_A_DQS_P<0>

MEM_80D

MEM_A_DQS0

MEM_A_DQS_0

MEM_45SMEM_A_DQ_BYTE7

MEM_A_DQ<63..56>

MEM_A_DATA_7

MEM_A_DQS_P<1>

MEM_80D

MEM_A_DQS1

MEM_A_DQS_1

MEM_A_DQS_N<2>

MEM_80D

MEM_A_DQS2

MEM_A_DQS_2

MEM_80D

MEM_A_DQS3

MEM_A_DQS_N<3>

MEM_A_DQS_3

MEM_80D

MEM_A_DQS7

MEM_A_DQS_P<7>

MEM_A_DQS_7

MEM_80D

MEM_B_DQS5

MEM_B_DQS_5

MEM_B_DQS_P<5>

MEM_80D

MEM_B_DQS_N<6>

MEM_B_DQS6

MEM_B_DQS_6

MEM_45SMEM_B_DQ_BYTE6

MEM_B_DATA_6

MEM_B_DQ<55..48>

MEM_80D

MEM_B_DQS0

MEM_B_DQS_0

MEM_B_DQS_P<0>

MEM_B_DQS7

MEM_80D

MEM_B_DQS_P<7>

MEM_B_DQS_7

MEM_80D

MEM_A_DQS1

MEM_A_DQS_N<1>

MEM_A_DQS_1

MEM_A_DQS_P<2>

MEM_80D

MEM_A_DQS2

MEM_A_DQS_2

MEM_45SMEM_A_DQ_BYTE6

MEM_A_DQ<55..48>

MEM_A_DATA_6

MEM_72D MEM_CLK

MEM_A_CLK

MEM_A_CLK_P<5..0>

MEM_45S

MEM_CTRL

MEM_A_CTRL

MEM_A_CKE<3..0>

MEM_45S MEM_CMD

MEM_A_CMD

MEM_A_A<15..0>

MEM_45SMEM_A_DQ_BYTE2

MEM_A_DQ<23..16>

MEM_A_DATA_2

MEM_A_DQS4

MEM_A_DQS_P<4>

MEM_80D

MEM_A_DQS_4 MEM_A_DQS_4

MEM_A_DQS4

MEM_A_DQS_N<4>

MEM_80D MEM_80D

MEM_A_DQS5

MEM_A_DQS_P<5>

MEM_A_DQS_5

MEM_B_DQS4

MEM_80D

MEM_B_DQS_N<4>

MEM_B_DQS_4

MEM_45S

MEM_CTRL

MEM_A_CTRL

MEM_A_ODT<3..0>

MEM_45S

MEM_CTRL

MEM_A_CTRL

MEM_A_CS_L<3..0>

MEM_72D MEM_CLK

MEM_A_CLK

MEM_A_CLK_N<5..0>

MEM_45S MEM_CMD

MEM_A_CMD

MEM_A_BA<2..0>

MEM_B_CLK_P<5..0>

MEM_72D MEM_CLK

MEM_B_CLK

MEM_45S MEM_CMD

MEM_B_CMD

MEM_B_BA<2..0>

MEM_45S MEM_CMD

MEM_B_CMD

MEM_B_CAS_L

MEM_45SMEM_B_DQ_BYTE0

MEM_B_DQ<7..0>

MEM_B_DATA_0

MEM_45SMEM_B_DQ_BYTE2

MEM_B_DQ<23..16>

MEM_B_DATA_2

MEM_80D

MEM_B_DQS_P<6>

MEM_B_DQS_6

MEM_B_DQS6

MEM_A_DQS_N<5>

MEM_A_DQS5

MEM_80D

MEM_A_DQS_5

MEM_A_DQS_P<6>

MEM_80D

MEM_A_DQS6

MEM_A_DQS_6

MEM_B_CKE<3..0>

MEM_45S

MEM_B_CTRL

MEM_CTRL

MEM_45S

MEM_CTRL

MEM_B_CTRL

MEM_B_CS_L<3..0>

MEM_45S MEM_CMD

MEM_B_CMD

MEM_B_A<15..0>

MEM_45SMEM_B_DQ_BYTE1

MEM_B_DQ<15..8>

MEM_B_DATA_1

MEM_PWR

PP0V75_S3_MEM_VREFCA_A

MEM_45SMEM_B_DQ_BYTE3

MEM_B_DQ<31..24>

MEM_B_DATA_3

MEM_A_DQ<15..8>

MEM_45SMEM_A_DQ_BYTE1

MEM_A_DATA_1

MEM_45SMEM_A_DQ_BYTE0

MEM_A_DQ<7..0>

MEM_A_DATA_0

MEM_45S

MEM_A_DQ<31..24>

MEM_A_DATA_3

MEM_A_DQ_BYTE3

MEM_45S MEM_CMD

MEM_A_CMD

MEM_A_RAS_L

MEM_CMDMEM_45S

MEM_A_CMD

MEM_A_WE_L

MEM_80D

MEM_A_DQS0

MEM_A_DQS_N<0>

MEM_A_DQS_0

MEM_45S MEM_CMD

MEM_A_CMD

MEM_A_CAS_L

MEM_45S MEM_CMD

MEM_B_CMD

MEM_B_WE_L

MEM_B_RAS_L

MEM_45S MEM_CMD

MEM_B_CMD

MEM_45S

MEM_CTRL

MEM_B_CTRL

MEM_B_ODT<3..0>

MEM_PWR

PP0V75_S3_MEM_VREFDQ_A

MEM_PWR

PP1V5_S3

MEM_80D

MEM_B_DQS_N<7>

MEM_B_DQS_7

MEM_B_DQS7

051-9277

2.8.0

101 OF 109

67 OF 73

11 27

11 28

8

11 29 30 32

6 7

11 28

11 30

11 29

11 30

11 27

11 28

11 27

11 28

11 30

11 29

11 30

11 27

11 28

8

11 27 28 32

11 27

11 28

11 30

11 27 28 32

8

11 27 28 32

8

11 29 30 32

11 29

11 30

11 28

11 29 30 32

11 29

27 28 31

11 29

11 27

11 27 28 32

11 27

11 27 28 32

11 29 30 32

27 28 31

6 7

11 30

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SOURCE: 471984_Cheif_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback.

USB 2.0 Interface Constraints

UART Interface Constraints

SOURCE: 471984_Chief_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback.

SATA SSD

SATA Interface Constraints

ELECTRICAL_CONSTRAINT_SET

SPACING

NET_TYPE

PHYSICAL

PCH Net Properties

USB 3.0 Interface Constraints

SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.8

USB Hub nets

USB EXTA nets (Right USB port)

USB Camera nets

USB EXTB nets (Left USB port)

(USB_TPAD_HUB) (USB_TPAD_HUB)

Unused USB nets

PCH Constraints 1

SYNC_MASTER=J13_CONSTRAINTS

SYNC_DATE=01/11/2012

PCH_USB_RBIAS

8 MIL

=STANDARD

8 MIL

=STANDARD

*

=STANDARD =STANDARD

=2x_DIELECTRIC

*USB ?

*

USB3_PCH_RX USB3_PCH_RX

USB3_RX2RX

*_TXSATA3_PCH_RX

SATA3_2OTHERHS

*

*_RXSATA3_PCH_TX

SATA3_2OTHERHS

=4x_DIELECTRIC

* ?

SATA3_TX2OTHERTX

=80_OHM_DIFF=80_OHM_DIFF

*

=80_OHM_DIFF=80_OHM_DIFF=80_OHM_DIFFSATA_80D

=80_OHM_DIFF

?*

SATA_ICOMP

=4x_DIELECTRIC

SATA3_PCH_RX

*

SATA3_RX2TX

*_PCH_TX

SATA3_PCH_TX

SATA3_TX2OTHERTX

*

*_PCH_TX

SATA3_PCH_TX SATA3_PCH_TX

SATA3_TX2TX

*

SATA3_PCH_RX

SATA3_RX2OTHERRX

*_PCH_RX

*

SATA3_PCH_TX

SATA3_TX2RX

*_PCH_RX

*

SATA3_PCH_RX SATA3_PCH_RX

SATA3_RX2RX

*

SATA3_2OTHERHS

*_TXSATA3_PCH_TX

*

SATA3_PCH_RX

*

SATA3_2OTHERHS

*_RX

SATA3_2OTHERSATA3_PCH_TX

**

SATA3_PCH_RX

**

SATA3_2OTHER

=5x_DIELECTRIC

?

SATA3_TX2TX

TOP,BOTTOM

=5x_DIELECTRIC

?

SATA3_RX2RX

=5x_DIELECTRIC

?

TOP,BOTTOM

SATA3_TX2OTHERTX

=5x_DIELECTRIC

?

TOP,BOTTOM

SATA3_2OTHER

=5x_DIELECTRIC

TOP,BOTTOM

SATA3_RX2OTHERRX

?

=7x_DIELECTRIC

?

TOP,BOTTOM

SATA3_TX2RX

=7x_DIELECTRIC

SATA3_RX2TX

TOP,BOTTOM

?

=6x_DIELECTRICSATA3_2OTHERHS

TOP,BOTTOM

?

SATA3_RX2TX

=6x_DIELECTRIC

?*

SATA3_TX2TX

=2.5x_DIELECTRIC

* ?

SATA3_RX2RX

=2.5x_DIELECTRIC

* ?

=4x_DIELECTRIC

SATA3_RX2OTHERRX

?*

SATA3_TX2RX

=6x_DIELECTRIC

* ?

?*

SATA3_2OTHERHS =4x_DIELECTRIC

SATA3_2OTHER

=3x_DIELECTRIC

*

?

* ?

UART

=2x_DIELECTRIC

UART_45S

*

=45_OHM_SE =45_OHM_SE =45_OHM_SE =45_OHM_SE=45_OHM_SE =45_OHM_SE

TOP,BOTTOM

=4x_DIELECTRIC

USB ?

TOP,BOTTOM

=5x_DIELECTRIC

?

USB3_TX2TX

TOP,BOTTOM

?

USB3_RX2RX

=5x_DIELECTRIC

?

USB3_TX2OTHERTX

TOP,BOTTOM

=5x_DIELECTRIC

?

USB3_RX2OTHERRX

=7x_DIELECTRIC

?

TOP,BOTTOMUSB3_TX2RX

TOP,BOTTOM

?

USB3_RX2TX

=7x_DIELECTRIC

TOP,BOTTOM?=6x_DIELECTRIC

USB3_2OTHERHS

=5x_DIELECTRIC

?

USB3_2OTHER

TOP,BOTTOM

USB3_RX2RX

?

=2.5x_DIELECTRIC

*

USB3_TX2RX

?

=6x_DIELECTRIC

*

USB3_TX2OTHERTX

?

=4x_DIELECTRIC

*

USB3_RX2OTHERRX

?

=4x_DIELECTRIC

*

USB3_RX2TX

?

=6x_DIELECTRIC

*

?

USB3_2OTHER

=3x_DIELECTRIC

*

=4x_DIELECTRIC

USB3_2OTHERHS

?*

*

USB3_PCH_TX USB3_PCH_TX

USB3_TX2TX

*_PCH_TX

*

USB3_PCH_RX

USB3_RX2TX

*_PCH_TX

*

USB3_TX2OTHERTX

USB3_PCH_TX

*_PCH_RX

*

USB3_PCH_RX

USB3_RX2OTHERRX

*_PCH_RX

*

USB3_PCH_TX

USB3_TX2RX

USB3_2OTHERHS

*_TX

*

USB3_PCH_RX

USB3_2OTHERHS

*_TX

*

USB3_PCH_TX

USB3_2OTHERHS

*_RX

*

USB3_PCH_TX

**

USB3_PCH_RX USB3_2OTHER

USB3_2OTHERHS

*_RX

*

USB3_PCH_RX

**

USB3_PCH_TX USB3_2OTHER

=2.5x_DIELECTRIC

USB3_TX2TX

?*

USB_80D

=80_OHM_DIFF

*

=80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF=80_OHM_DIFF

UART_45S UART

SMC_DEBUGPRT_TX_L

USB_EXTA

USB_80D

USB

USB_EXTA_N

USB3_EXTB_RX_RC_P

USB3_PCH_RX

USB_80D

USB3_EXTB_RX_RC_N

USB3_PCH_RX

USB_80D

USB3_EXTB_RX_N

USB3_EXTB_RX

USB3_PCH_RX

USB_80D

USB_EXTB_P

USB

USB_EXTB

USB_80D

USB_EXTB_EHCI_N

USB_80D

USB

USB_EXTB_N

USB_80D

USB

USB_EXTB

USB_EXTB_EHCI_P

USB_80D

USB

USB_EXTB_XHCI_N

USB_80D

USB

USB3_EXTB_RX_P

USB_80D

USB3_PCH_RX

USB3_EXTB_RX

USB_EXTB_XHCI_P

USB

USB_80D

USB3_EXTB_TX_C_P

USB_80D

USB3_PCH_TX

USB3_EXTB_TX_C_N

USB_80D

USB3_PCH_TX

USB3_EXTB_TX_P

USB3_EXTB_TX

USB_80D

USB3_PCH_TX

USB3_EXTB_RX_CONN_N

USB_80D

USB3_PCH_RX

USB3_EXTB_TX_N

USB3_EXTB_TX

USB_80D

USB3_PCH_TX

USB3_EXTB_RX_CONN_P

USB3_PCH_RX

USB_80D

CLK_PCIE_80D CLK_PCIE

PCH_DIFFCLK_UNUSED_

PCH_CLK100M_SATA_N

CLK_PCIE

PCH_CLK14P3M_REFCLK

CPU_45S

PCH_DIFFCLK_UNUSED_

CLK_PCIECLK_PCIE_80D

PCH_CLK96M_DOT_N

PCH_DIFFCLK_UNUSED_

CLK_PCIE

PCH_CLK100M_SATA_P

CLK_PCIE_80D

PCH_DIFFCLK_UNUSED_

CLK_PCIE

PCH_CLK96M_DOT_P

CLK_PCIE_80D

CLK_PCIE

PCH_DIFFCLK_UNUSED_

CLK_PCIE_80D

PCIE_CLK100M_PCH_N

PCH_DIFFCLK_UNUSED_

CLK_PCIECLK_PCIE_80D

PCIE_CLK100M_PCH_P

PCH_USB_RBIAS PCH_USB_RBIAS

PCH_USB_RBIAS

USB_EXTD_XHCI_N

USB_80D

USB

USB_80D

USB

USB_EXTD_XHCI_P

USB3_EXTA_RX_F_P

USB_80D

USB3_PCH_RX

USB3_PCH_TX

USB_80D

USB3_EXTA_TX_C_P

USB_80D

USB3_PCH_TX

USB3_EXTA_TX

USB3_EXTA_TX_N

USB3_PCH_TX

USB_80D

USB3_EXTA_TX_P

USB3_EXTA_TX

USB_80D

USB3_EXTA_RX

USB3_EXTA_RX_N

USB3_PCH_RX

USB_80D

USB3_EXTA_RX_P

USB3_EXTA_RX

USB3_PCH_RX

USB

USB_80D

USB2_EXTA_MUXED_F_N

USB

USB2_EXTA_MUXED_F_P

USB_80D

USB

USB_80D

USB2_EXTA_MUXED_N

USB

USB2_EXTA_MUXED_P

USB_80D

USB3_PCH_TX

USB_80D

USB3_EXTA_TX_C_N

USB3_PCH_TX

USB_80D

USB3_EXTA_TX_F_P

USB3_PCH_TX

USB_80D

USB3_EXTA_TX_F_N

USB_80D

USB3_PCH_RX

USB3_EXTA_RX_F_N

UARTUART_45S

SMC_DEBUGPRT_RX_L

USB_EXTA

USB_80D

USB

USB_EXTA_P

USB_CAMERA

USB

USB_80D

USB_CAMERA_P

USB_CAMERA

USB

USB_80D

USB_CAMERA_N

USB_SMC

USB

USB_80D

USB_SMC_N

USB_SMC

USB

USB_80D

USB_SMC_P

USB_SDCARD

USB_80D

USB

USB_SDCARD_P

USB_TPAD_M

USB

USB_80D

USB_TPAD_M_N

USB_SDCARD

USB_80D

USB

USB_SDCARD_N

USB_TPAD_R_N

USB_80D

USB

USB_TPAD_M

USB

USB_80D

USB_TPAD_M_P

USB_TPAD_R_P

USB_80D

USB

USB_TPAD_HUB

USB

USB_80D

USB_TPAD_HUB_N

USB_TPAD_HUB

USB

USB_TPAD_HUB_P

USB_80D

USB

USB_80D

USB_TPAD_CONN_N

USB

USB_80D

USB_TPAD_CONN_P

USB_TPAD

USB_80D

USB

USB_TPAD_N

USB_80D

USB

USB_BT_WAKE_N

USB_TPAD

USB_80D

USB

USB_TPAD_P

USB_80D

USB

USB_BT_CONN_N

USB_80D

USB

USB_BT_CONN_P

USB_80D

USB

USB_BT_WAKE_P

USB_BT

USB

USB_80D

USB_BT_P

USB_BT

USB

USB_80D

USB_BT_N

USB_HUB_UP_P

USB_80D

USB_HUB1_UP

USB

USB_80D

USB_HUB_UP_N

USB_HUB1_UP

USB

PCH_SATAICOMP

PCH_SATA_ICOMP

SATA_ICOMP

SATA3_PCH_RX

SATA_SSD_D2R_N

SATA_80D

SATA_MUX_SSD_D2R

SATA3_PCH_RXSATA_80D

SATA_SSD_D2R_P

SATA_MUX_SSD_D2R

SATA_80D

SATA_SSD_D2R_MUX_OUT_N

SATA3_PCH_RX

SATA_PCH_MUX_D2R

SATA3_PCH_RX

SATA_HDD_D2R_N

SATA_80D

SATA_PCH_MUX_D2R

SATA_HDD_D2R_P

SATA3_PCH_RXSATA_80D

SATA_80D

SATA_SSD_D2R_MUX_OUT_P

SATA3_PCH_RX

SATA_80D

SATA_HDD_R2D_C_P

SATA3_PCH_TX

SATA_PCH_MUX_R2D

SATA3_PCH_TX

SATA_SSD_R2D_N

SATA_80D

SATA_MUX_SSD_R2D

SATA3_PCH_TXSATA_80D

SATA_SSD_R2D_P

SATA_MUX_SSD_R2D

SATA_80D SATA3_PCH_TX

SATA_SSD_R2D_MUX_IN_P

SATA_80D SATA3_PCH_TX

SATA_HDD_R2D_C_N

SATA_PCH_MUX_R2D

SATA_80D SATA3_PCH_TX

SATA_SSD_R2D_MUX_IN_N

051-9277

2.8.0

102 OF 109

68 OF 73

39 41 42

18 39

6

40

6

40

18 40

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18 24

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24 40

18 24

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18 24

6

40

6

40

18 40

16

18

18 24

39

18 39

39

39 41 42

18 39

6

18 40

6

18 40

24 41

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49

24 33

24 49

49

24 49

24

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49

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49

6

37

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37

24 37

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16

6

38

6

38

16 38

38

16 38

6

38

6

38

16 38

38

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

DisplayPort

SPACING

NET_TYPE

PHYSICAL

Clock Net Properties

ELECTRICAL_CONSTRAINT_SET

Chipset Net Properties

ELECTRICAL_CONSTRAINT_SET

System Clock Signal Constraints

SPACING

NET_TYPE

PHYSICAL

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

PCH Net Properties

PHYSICAL

HD Audio Interface Constraints

NOTE: 25MHz system clocks very sensitive to noise.

SPACING

LPC Bus Constraints

XDP Constraints

SPI Interface Constraints

SMBus Interface Constraints

SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.15

SIO Signal Constraints

SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.15

SMB_45S_R_50S

=45_OHM_SE =45_OHM_SE =45_OHM_SE

*

=STANDARD=STANDARD

=45_OHM_SE

=45_OHM_SE =45_OHM_SE

=STANDARD

*

=45_OHM_SE

PCH_45S

=45_OHM_SE

=STANDARD

=45_OHM_SE

SPI_45S

*

=STANDARD=STANDARD

=45_OHM_SE =45_OHM_SE=45_OHM_SE

*SPI ?

=4x_DIELECTRIC

*

PCH_ITP

?

=2:1_SPACING

* ?

=4x_DIELECTRIC

CLK_SLOW

* ?

CLK_SLOW

=2x_DIELECTRIC

*

=2x_DIELECTRIC

?HDA

SMB *

=2x_DIELECTRIC

?

SMB_45S_R_50S

TOP,BOTTOM =50_OHM_SE =50_OHM_SE =50_OHM_SE=50_OHM_SE

LPC_45S

=45_OHM_SE=45_OHM_SE =45_OHM_SE =45_OHM_SE

*

=STANDARD =STANDARD

*

=5x_DIELECTRIC

?

CLK_25M

=STANDARD

=45_OHM_SE=45_OHM_SE=45_OHM_SE

HDA_45S

*

=STANDARD

=45_OHM_SE

?

CLK_LPC

*

=4x_DIELECTRIC

* ?

=3x_DIELECTRIC

LPC

=45_OHM_SE =45_OHM_SE

*

=STANDARD =STANDARD

=45_OHM_SE=45_OHM_SE

CLK_LPC_45S

=45_OHM_SE=45_OHM_SE=45_OHM_SE

*

CLK_SLOW_45S

=STANDARD

=45_OHM_SE

=STANDARD

TOP,BOTTOM

=4x_DIELECTRIC

?

DP_2DP

=6x_DIELECTRIC

DP_2OTHERHS?TOP,BOTTOM

DP_AUX

TOP,BOTTOM

=4x_DIELECTRIC

?

DP_2OTHER

?

=4x_DIELECTRIC

TOP,BOTTOM

=80_OHM_DIFF=80_OHM_DIFF

DP_80D

=80_OHM_DIFF

*

=80_OHM_DIFF=80_OHM_DIFF

DP_2DP

=3x_DIELECTRIC

* ?

=4x_DIELECTRIC

DP_2OTHERHS

?

*

=3x_DIELECTRIC

?*

DP_AUX

DP_2OTHER

?

*

=3x_DIELECTRIC

DP_2OTHERHS

*_TX

DP_TX

*

DP_TX DP_TX

DP_2DP

DP_2OTHERHS

DP_TX

*

*_RX

*

DP_TX

*

DP_2OTHER

SYNC_DATE=01/11/2012

PCH Constraints 2

SYNC_MASTER=J13_CONSTRAINTS

=45_OHM_SE=45_OHM_SE=45_OHM_SE=45_OHM_SE

*

=STANDARD =STANDARD

CLK_25M_45S

=45_OHM_SE=45_OHM_SE=45_OHM_SE

*

=STANDARD =STANDARD

CLK_SLOW_45S

=45_OHM_SE

PCH_45S

XDP_PCH_TDI

PCH_ITPXDP_TDI

PCIE_TBT_D2R_P<3..0>

PCIE_80D

PCIE_PCH_RX

PCIE_TBT_D2R

PCIE_PCH_TX

PCIE_80D

PCIE_TBT_R2D_N<3..0>

PCIE_TBT_R2D

PCIE_TBT_D2R_C_P<3..0>

PCIE_80D

PCIE_PCH_RX

PCIE_TBT_D2R_C_N<3..0>

PCIE_80D

PCIE_PCH_RX

PCIE_CLK100M_TBT_P

CLK_PCIE_80D

PCIE_CLK100M_TBT

CLK_PCIE

PCIE_CLK100M_TBT_N

PCIE_CLK100M_TBT

CLK_PCIE_80D CLK_PCIE

PCIE_80DPCIE_TBT_D2R

PCIE_PCH_RX

PCIE_TBT_D2R_N<3..0>

PCIE_AP_D2R_N

PCIE_80D

PCIE_AP_D2R PCIE_PCH_RX

SPI_45S

SPI

SPI_MLB_CLK

SPI_CS0

SPI

SPI_CS0_R_L

SPI_45S

SPI_MISO

SPI_45S

SPI

SPI_MISO

XDP_TCK

XDP_PCH_TCK

PCH_45S PCH_ITP

XDP_TDO

XDP_PCH_TDO

PCH_45S PCH_ITP

CLK_PCIECLK_PCIE_80D

PEG_CLK100M_P

PCIE_CLK100M_AP_N

PCIE_CLK100M_AP

CLK_PCIECLK_PCIE_80D

PCIE_80D

PCIE_PCH_TX

PCIE_AP_R2D_C_N

SPI_45S

SPI

SPI_SMC_MISO

SPI_45S

SPI

SPI_SMC_MOSI

XDP_PCH_TMS

XDP_TMS PCH_ITPPCH_45S

PCIE_PCH_TX

PCIE_80D

PCIE_TBT_R2D_C_N<3..0>

HDA

HDA_45S

HDA_BIT_CLK_R

HDA

HDA_SYNC_R

HDA_45S HDA_45S

HDA_RST_R_L

HDA_RST_L

HDA

SPI_45S

SPI

SPI_CLK

SPI_CLK_R

SPI_45S

SPI_CS0_L

SPI

PCIE_PCH_TX

PCIE_80D

PCIE_AP_R2D

PCIE_AP_R2D_P

PCIE_PCH_TX

PCIE_80D

PCIE_AP_R2D

PCIE_AP_R2D_N

PCIE_80D

PCIE_PCH_TX

PCIE_AP_R2D_C_P

SMB_45S_R_50S

SMB

SMBUS_PCH_CLK

HDA_45S

HDA_BIT_CLK

HDA

HDA_BIT_CLK

SPI

SPI_45S

SPI_MLB_MISO

SPI_MLB_MOSI

SPI

SPI_45S

SPI_SMC_CLK

SPI_45S

SPI

SPI_45S

SPI_CLK

HDA_RST_L

HDA

HDA_45S

HDA_SYNC

HDA

HDA_45S

HDA_SYNC

CLK_LPC_45S

CLK_LPC

PCH_CLK33M_PCIOUT

CLK_LPC_45S

LPC_CLK33M_LPCPLUS_R

CLK_LPC

SPI

SPI_45S

SPI_MOSI

SPI_MOSI_R

SPI_45S

SPI

SPI_MOSI

PM_CLK32K_SUSCLK_R

PM_SUS_CLK

CLK_SLOW_45S CLK_SLOW

HDA_45S

HDA

HDA_SDIN0

HDA

HDA_45S

HDA_SDOUT

HDA_45S

HDA

HDA_SDOUT_R

SMC_CLK32K

CLK_SLOWCLK_SLOW_45S

LPC_CLK33M

CLK_LPC_45S

LPC_CLK33M_SMC

CLK_LPC

CLK_LPC_45S

CLK_LPC

LPC_CLK33M_SMC_R

CLK_LPC

LPC_CLK33M_LPCPLUS

CLK_LPC_45S

LPC_CLK33M

SMBUS_SMC_1_S0_SDA

SMB

SMB_45S_R_50S

SML_PCH_1_DATA

SMBUS_SMC_1_S0_SCL

SMB

SMB_45S_R_50S

SML_PCH_1_CLK

SMBUS_PCH_0_CLK

SMB

SML_PCH_0_CLK

SMB_45S_R_50S

SMB

SMBUS_PCH_DATA

CLK_LPC_45S

CLK_LPC

PCH_CLK33M_PCIIN

LPC_CLK33M

LPC_45S

LPC

LPCPLUS_RESET_L

LPC_FRAME_L

LPC_45S

LPC_FRAME_L

LPC

SPI_45S

SPI

SPI_SMC_CS_L

PCIE_AP_D2R

PCIE_80D

PCIE_PCH_RX

PCIE_AP_D2R_P

PCIE_CLK100M_AP_P

CLK_PCIECLK_PCIE_80D

PCIE_CLK100M_AP

CLK_PCIECLK_PCIE_80D

PEG_CLK100M_N

PCIE_80D

PCIE_PCH_TX

PCIE_TBT_R2D_C_P<3..0>

PCIE_TBT_R2D

PCIE_PCH_TX

PCIE_80D

PCIE_TBT_R2D_P<3..0>

SPI

SPI_45S

SPI_MLB_CS_L

SMB_45S_R_50S

SMBUS_PCH_0_DATA

SMB

SML_PCH_0_DATA

LPC_AD

LPC_45S

LPC

LPC_AD<3..0>

DP_80D

DP_TX

DP_TBT_ML

DP_TBTSNK0_ML_P<3..0>

DP_80D

DP_TX

DP_TBT_ML

DP_TBTSNK0_ML_N<3..0>

DP_80D

DP_TX

DP_TBTSNK0_ML_C_P<3..0>

DP_80D

DP_TX

DP_TBTSNK0_ML_C_N<3..0>

DP_80D DP_AUX

DP_TBTSNK0_AUXCH_P

DP_TBT_AUXCH

DP_80D

DP_TBTSNK0_AUXCH_N

DP_TBT_AUXCH

DP_AUX

DP_80D DP_AUX

DP_TBTSNK0_AUXCH_C_P

DP_80D

DP_TBTSNK0_AUXCH_C_N

DP_AUX

DP_TBTSNK1_ML_P<3..0>

DP_80D

DP_TX

DP_TBT_ML

DP_TBTSNK1_ML_N<3..0>

DP_TX

DP_80D

DP_TBT_ML

DP_TBTSNK1_ML_C_P<3..0>

DP_TX

DP_80D

DP_TBTSNK1_ML_C_N<3..0>

DP_TX

DP_80D

DP_AUXDP_80D

DP_TBTSNK1_AUXCH_P

DP_TBT_AUXCH

DP_AUXDP_80D

DP_TBTSNK1_AUXCH_N

DP_TBT_AUXCH

DP_AUXDP_80D

DP_TBTSNK1_AUXCH_C_P

DP_AUXDP_80D

DP_TBTSNK1_AUXCH_C_N

CLK_25M

CLK_25M_45S

SYSCLK_CLK25M_X2_R

CLK_25M_45S

CLK_25M

SYSCLK_CLK25M_X2

CLK_25M_45S

CLK_25M

SYSCLK_CLK25M_XTAL

SYSCLK_CLK25M_X1

CLK_25M_45S

CLK_25M

SYSCLK_CLK25M_TBT_R

SYSCLK_CLK25M_TBT

CLK_25M

CLK_25M_45S

SYSCLK_CLK25M_TBT

CLK_25M

SYSCLK_CLK25M_SB_R

CLK_25M_45S

SYSCLK_CLK25M_SB

CLK_25M

CLK_25M_45S

SYSCLK_CLK25M_SB

SYSCLK_CLK32K_RTC

CLK_SLOW_45S

SYSCLK_CLK32K_RTC

CLK_SLOW

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16 23

8

34

16

16 43

43

6

37

6

37

16 37

16 44

6

16 40

42 43 50

41 42

43

6

16 40

6

16 40

18 25

16 43

43

17 42

6

16 40

6

16 40

16 25

41 42

25 41

18 25

6

25 43

16 44

16 25

6

25 43

6

16 41 43

41 42

6

16 37

6

16 37

8

16

8

34

42 43 50

16 44

6

16 41 43 34

34

8

34

8

34

8

34

8

34

8

34

8

34

8

34

8

34

25

34

25 34

16

16 25

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

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87 6 5 4 3

C

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A

NOTICE OF PROPRIETARY PROPERTY:

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SHEET

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REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

Only used on dual-port hosts.

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

NET_TYPE

Thunderbolt IC Net Properties

SPACING

Only used on hosts supporting Thunderbolt video-in

Thunderbolt/DP Net Properties

DisplayPort Signal Constraints

Thunderbolt SPI Signal Constraints

NOTE: DisplayPort Physical/Spacing Constraints provided by Chipset or GPU page.

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

PHYSICAL

SPACING

Thunderbolt/DP Connector Signal Constraints

TBTDP_TX2TX

TBTDP_TX TBTDP_TX

*

Thunderbolt Constraints

SYNC_DATE=01/11/2012

SYNC_MASTER=J13_CONSTRAINTS

=10x_DIELECTRIC

TBTDP_TX2RX?TOP,BOTTOM

TBTDP_2OTHERHS

=10x_DIELECTRIC

TOP,BOTTOM

?

=6x_DIELECTRIC

TBTDP_RX2RX?TOP,BOTTOM

TBTDP_TX

*_TX

TBTDP_2OTHERHS

*

TBTDP_2OTHER

TBTDP_RX

**

TBTDP_2OTHER

*

TBTDP_TX

*

*_RX

TBTDP_2OTHERHS

*

TBTDP_RX

TBTDP_2OTHER

=6x_DIELECTRIC

?

TOP,BOTTOM

TBTDP_TX2RX

TBTDP_TX TBTDP_RX

*

?

TBTDP_TX2TX

*

=4x_DIELECTRIC

TBTDP_TX2RX

?

*

=6x_DIELECTRIC

TBTDP_RX2RX

?

*

=4x_DIELECTRIC

TBTDP_2OTHER

?

*

=6x_DIELECTRICTBTDP_2OTHERHS

*

?

*_TX

TBTDP_2OTHERHS

*

TBTDP_RX

TBTDP_2OTHERHS

*_RX

*

TBTDP_TX

TBT_SPI

*

=2x_DIELECTRIC

?

=80_OHM_DIFF

TBTDP_80D

*

=80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF

TBTDP_RX TBTDP_RX

*

TBTDP_RX2RX

TBTDP_TX

TBTDP_TX2RX

TBTDP_RX

*

=6x_DIELECTRIC

TBTDP_TX2TX?TOP,BOTTOM

TBT_SPI_45S

*

=45_OHM_SE =45_OHM_SE =45_OHM_SE =45_OHM_SE

=STANDARD =STANDARD

TBTDP_RX

TBTDP_80D

TBT_A_D2R_C_P<1..0>

TBTDP_RX

TBTDP_80D

TBT_A_D2R1

TBT_A_D2R_P<1>

TBTDP_RX

TBT_A_D2R1

TBT_A_D2R_N<1>

TBTDP_80D

TBTDP_RX

TBT_A_D2R0

TBT_A_D2R_P<0>

TBTDP_80D

TBTDP_RX

TBT_A_D2R0

TBT_A_D2R_N<0>

TBTDP_80D

DP_AUX

TBT_A_AUXCH

DP_80D

DP_TBTPA_AUXCH_C_P

DP_AUXDP_80D

TBT_A_AUXCH

DP_TBTPA_AUXCH_C_N

DP_AUX

DP_TBTPA_AUXCH_P

DP_80D

DP_AUX

DP_TBTPA_AUXCH_N

DP_80D

DP_AUXDP_80D

DP_A_AUXCH_DDC_P

TBTDP_RX

TBTDP_80D

TBT_A_D2R_C_N<1..0>

TBTDP_RX

TBTDP_80D

TBT_A_D2R1_AUXDDC_P

TBTDP_RX

TBTDP_80D

TBT_A_D2R1_AUXDDC_N

TBTDP_TX

TBT_B_R2D_C_N<1..0>

TBT_B_R2D TBTDP_80D

TBTDP_TX

TBT_B_R2D_N<1..0>

TBTDP_80D

TBTDP_TX

TBT_A_R2D_C_P<1..0>

TBT_A_R2D TBTDP_80D

TBTDP_TX

TBT_A_R2D_C_N<1..0>

TBT_A_R2D TBTDP_80D

TBTDP_TX

TBT_A_R2D_N<1..0>

TBTDP_80D

TBTDP_TX

TBT_A_R2D_P<1..0>

TBTDP_80D

DP_TBTSRC_ML_C_P<3..0>

DP_80D

DP_TX

DP_TBTSRC_ML_C_N<3..0>

DP_80D

DP_TX

DP_TBTSRC_AUXCH_C_P

DP_80D DP_AUX

DP_TBTSRC_AUXCH_C_N

DP_80D DP_AUX

TBT_SPI_CLK

TBT_SPI_CLK TBT_SPI_45S

TBT_SPI

TBT_SPI_MOSI

TBT_SPI_45S

TBT_SPI

TBT_SPI_MISO

TBT_SPI_45S

TBT_SPI

TBT_SPI_CS_L

TBT_SPI_45S

TBT_SPI

TBT_SPI_CS_L

TBTDP_TX

TBT_B_R2D

TBT_B_R2D_C_P<1..0>

TBTDP_80D

TBTDP_TX

TBT_B_R2D_P<1..0>

TBTDP_80D

DP_TBTPB_ML

DP_TBTPB_ML_C_P<3..1:2>

DP_80D

DP_TX

DP_TBTPB_ML_P<3..1:2>

DP_80D

DP_TX

DP_TBTPB_ML_C_N<3..1:2>

DP_TBTPB_ML

DP_80D

DP_TX

DP_TBTPB_ML_N<3..1:2>

DP_80D

DP_TX

DP_80D

DP_TX

DP_B_LSX_ML_N<1>

DP_80D

DP_TX

DP_B_LSX_ML_P<1>

TBTDP_RX

TBTDP_80D

TBT_B_D2R_C_P<1..0>

TBTDP_RX

TBT_B_D2R_C_N<1..0>

TBTDP_80D

TBTDP_RX

TBT_B_D2R_P<1..0>

TBTDP_80DTBT_B_D2R

TBTDP_RX

TBT_B_D2R_N<1..0>

TBT_B_D2R TBTDP_80D

DP_AUX

DP_TBTPB_AUXCH_C_P

TBT_B_AUXCH

DP_80D

DP_AUX

DP_TBTPB_AUXCH_C_N

TBT_B_AUXCH

DP_80D

DP_AUX

DP_B_AUXCH_DDC_P

DP_80D

DP_AUX

DP_TBTPB_AUXCH_P

DP_80D

DP_AUX

DP_TBTPB_AUXCH_N

DP_80D

DP_AUX

DP_B_AUXCH_DDC_N

DP_80D

TBTDP_RX

TBT_B_D2R1_AUXDDC_P

TBTDP_80D

TBTDP_RX

TBT_B_D2R1_AUXDDC_N

TBTDP_80D

DP_AUXDP_80D

DP_A_AUXCH_DDC_N

DP_TX

DP_80D

DP_A_LSX_ML_P<1>

DP_TX

DP_80D

DP_TBTPA_ML1

DP_TBTPA_ML_C_N<1>

DP_TX

DP_80D

DP_TBTPA_ML1

DP_TBTPA_ML_C_P<1>

DP_80D

DP_TX

DP_TBTPA_ML3

DP_TBTPA_ML_C_P<3>

DP_80D

DP_A_LSX_ML_N<1>

DP_TX

DP_TBTPA_ML3

DP_TBTPA_ML_C_N<3>

DP_80D

DP_TX

DP_TBTPA_ML_N<3..1:2>

DP_80D

DP_TX

DP_TBTPA_ML_P<3..1:2>

DP_80D

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34

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34

8

34

8

34

64

34 64

64

34 64

64

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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D

87 6 5 4 3

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NOTICE OF PROPRIETARY PROPERTY:

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DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SMC SMBus Net Properties

PHYSICAL

NET_TYPE

PHYSICAL

SPACING

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

ELECTRICAL_CONSTRAINT_SET

SMBus Charger Net Properties

SMC Constraints

SYNC_MASTER=J13_CONSTRAINTS

SYNC_DATE=01/11/2012

1:1_DIFFPAIR

0.1 MM

=STANDARD

*

=STANDARD =STANDARD=STANDARD

0.1 MM

SMBUS_SMC_1_S0_SCL

SMB

SMBUS_SMC_1_S0_SCL

SMB_45S_R_50S

SMBUS_SMC_1_S0_SDA

SMB

SMBUS_SMC_1_S0_SDA

SMB_45S_R_50S

CHGR_CSO_R_N

1:1_DIFFPAIR

CHGR_CSO_R_P

1:1_DIFFPAIR

SENSE_DIFFPAIR

CHGR_CSI_N

1:1_DIFFPAIR

CHGR_CSI_R_P

1:1_DIFFPAIR

CHGR_CSI_R_N

1:1_DIFFPAIR

SENSE_DIFFPAIR

1:1_DIFFPAIR

CHGR_CSO_N

SENSE_DIFFPAIR

1:1_DIFFPAIR

CHGR_CSO_P

SENSE_DIFFPAIR

CHGR_CSI_P

1:1_DIFFPAIR

SMB_45S_R_50S

SMBUS_SMC_0_S0_SCL

SMB

SMB_45S_R_50S

SMBUS_SMC_0_S0_SDA

SMB

SMBUS_SMC_2_S3_SCL

SMB

SMB_45S_R_50S

SMBUS_SMC_2_S3_SDA

SMB

SMB_45S_R_50S

SMBUS_SMC_5_G3_SCL

SMB

SMBUS_SMC_5_G3_SCL

SMB_45S_R_50S

SMBUS_SMC_5_G3_SDA

SMB

SMBUS_SMC_5_G3_SDA

SMBUS_SMC_3_SCL

SMB

SMB_45S_R_50S

SMBUS_SMC_3_SDA

SMB

SMBUS_SMC_3_SDA

SMB_45S_R_50S

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Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

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A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

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REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

SPACING

PHYSICAL

J11/J13 Specific Net Properties

SB_POWER CLK_PCIE

*

PWR_P2MM

GND *

GND_P2MMUSB*

SATA*

GND *

GND_P2MM

GND

PCIE*

GND_P2MM

*

GND_P2MM

GND *

CLK_PCIE

*GND

GND_P2MMCPU_VCCSENSE

GND_P2MMCPU_COMP

*GND

=45_OHM_SE

=1:1_DIFFPAIR

*

=45_OHM_SE =45_OHM_SE

=1:1_DIFFPAIR

SENSE_1TO1_45S

0.200 MM

=1:1_DIFFPAIR

0.100 MM

SENSE_1TO1_P2MM

=1:1_DIFFPAIR*=1:1_DIFFPAIR

=1:1_DIFFPAIR

=45_OHM_SE=45_OHM_SE =45_OHM_SE

=1:1_DIFFPAIR=1:1_DIFFPAIR

THERM_1TO1_45S

=1:1_DIFFPAIR

*

0.300 MM

=1:1_DIFFPAIR

0.100 MM

=1:1_DIFFPAIR=1:1_DIFFPAIR

*

SPKR_DIFFPAIR

=1:1_DIFFPAIR

?

=2:1_SPACING

SENSE

*

?

=2:1_SPACING

AUDIO

*

?

=STANDARD

*GND

* ?

=2:1_SPACING

THERM

SB_POWER

*

SATA*

PWR_P2MM

*

0.20 MM

1000PWR_P2MM

SB_POWER

SATA*

*

PWR_P2MM

1000GND_P2MM

*

0.20 MM

GND

LVDS*

*

GND_P2MM

Project Specific Constraints

SYNC_MASTER=J13_CONSTRAINTS

SYNC_DATE=01/11/2012

ISNS_3V3S0_R_P

SENSE_1TO1_45S

SENSE

SENSE_DIFFPAIR THERM_1TO1_45S

THERM

INLET_THMSNS_D1_P

THERM_1TO1_45S

THERM

INLET_THMSNS_D1_N

SENSE_DIFFPAIR

THERM_1TO1_45S

TBTTHMSNS_D2_R_P

THERM

SENSE

SENSE_1TO1_P2MM

SENSE_DIFFPAIR

CPUVCCIOS0_CS_P

CPUTHMSNS_D2_N

SENSE_DIFFPAIR SENSE_1TO1_45S

SENSE

CPUTHMSNS_D2_P

SENSE_DIFFPAIR SENSE_1TO1_45S

SENSE

THERM_1TO1_45S

TBTTHMSNS_D2_R_N

THERM

SENSE_1TO1_45S

SENSE

CPU_THERMD_P

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_45SSENSE_DIFFPAIR

ISNS_1V5_S3_N

SENSE_1TO1_P2MM

SENSE

CPUIMVP_ISNS1G_P

SENSE_DIFFPAIR

SENSE_1TO1_P2MM

SENSE

CPUIMVP_ISNS1G_N

SENSE_DIFFPAIR

SENSE_1TO1_P2MM

SENSE

SENSE_DIFFPAIR

CPUIMVP_ISNS1_N

SENSE_1TO1_45S

SENSE

CPUIMVP_ISUM_R_P

VCCSAISNS_R_N

SENSE

SENSE_1TO1_45S

ISNS_3V3S0_N

SENSE_1TO1_45S

SENSE

SENSE_DIFFPAIR

CPUIMVP_ISUMG_P

SENSE

SENSE_1TO1_P2MM

SENSE_DIFFPAIR

SENSE_DIFFPAIR SENSE_1TO1_45S

SENSE

CPU_THERMD_N

CPUVCCIOS0_CS_N

SENSE_1TO1_P2MM

SENSE

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_P2MM

CPUIMVP_ISNS1_P

SENSE_1TO1_45S

SENSE

CPUIMVP_ISUM_R_N

SENSE

CPUIMVP_ISUMG_R_P

SENSE_1TO1_45S

SENSE

ISNS_HS_OTHER_P

SENSE_1TO1_45SSENSE_DIFFPAIR

SENSE

CPUIMVP_ISUMG_R_N

SENSE_1TO1_45S

VCCSAS0_CS_P

SENSE

SENSE_DIFFPAIR

SENSE_1TO1_P2MM

TBT_MLBBOT_THMSNS_P

THERM_1TO1_45S

THERM

TBT_THERMD_N

THERM_1TO1_45S

THERM

SENSE_DIFFPAIR

SENSE_DIFFPAIR THERM_1TO1_45S

THERM

TBT_THERMD_P

THERM

TBT_MLBBOT_THMSNS_N

THERM_1TO1_45S

CPUIMVP_ISUMG_N

SENSE_1TO1_P2MM

SENSE

SENSE_DIFFPAIR

ISNS_3V3S0_R_N

SENSE_1TO1_45S

SENSE

SENSE_1TO1_45S

ISNS_3V3S0_P

SENSE

SENSE_DIFFPAIR

VCCSAISNS_R_P

SENSE

SENSE_1TO1_45S

VCCSAS0_CS_N

SENSE

SENSE_DIFFPAIR

SENSE_1TO1_P2MM

CPUIMVP_ISUM_P

SENSE

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_45S

ISNS_HS_OTHER_N

SENSE_DIFFPAIR

SENSE

ISNS_1V5_S3_P

SENSE_1TO1_45S

ISNS_AIRPORT_N

SENSE_1TO1_45S

SENSE

SENSE_DIFFPAIR

CPUIMVP_ISUM_N

SENSE

SENSE_DIFFPAIR

SENSE_1TO1_P2MM

SENSE

ISNS_HS_COMPUTING_N

SENSE_DIFFPAIR SENSE_1TO1_45S

SENSE_1TO1_45SSENSE_DIFFPAIR

ISNS_AIRPORT_P

SENSE

SENSE_DIFFPAIR SENSE_1TO1_45S

SENSE

ISNS_SSD_N

ISNS_HS_COMPUTING_P

SENSE_1TO1_45S

SENSE

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_45S

ISNS_SSD_P

SENSE_DIFFPAIR

ISNS_LCDBKLT_N

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_45S

SENSE_DIFFPAIR

SENSE

ISNS_LCDBKLT_P

SENSE_1TO1_45S

SPKRAMP_ROUT_N

SPKR_DIFFPAIR

AUDIO

SPKR_OUT

SB_POWER

PP3V3_S5

SB_POWER

PP3V3_S0

SPKRAMP_INR_P

AUDIO

1:1_DIFFPAIR

AUD_DIFF

SPKRAMP_INR_N

AUDIO

1:1_DIFFPAIR

AUD_DIFF

AUDIO

1:1_DIFFPAIR

MAX98300_R_P

AUDIO

1:1_DIFFPAIR

MAX98300_R_N

SPKR_DIFFPAIR

AUDIO

SPKR_OUT

SPKRAMP_ROUT_P

GND

051-9277

2.8.0

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45

46 47

47

45 59

47

9

47

46 56

45 58

45

45 61

57 58

9

47

45 59

45 57 58

45

46

45

45 54

47

57 58

45

45 61

45

45 54

57 58

46

46 56

37 46

57 58

8

46

37 46

38 46

8

46

38 46

8

46

8

46

6

51 52

6 7

6

40 51

6

40 51

51

6

51 52

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_BOARD_INFO

VERSION

ALLEGRO

(MIL or MM)

BOARD UNITS

BOARD LAYERS

BOARD AREAS

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

Single-ended Physical Constraints

Differential Pair Physical Constraints

Spacing Constraints

J11/J13 Board-Specific Spacing & Physical Constraints

100 MM

55_OHM_SE

100 MM

N*

=STANDARD =STANDARD =STANDARD

80_OHM_DIFF

Y

0.132 MM 0.132 MM 0.130 MM 0.130 MM

TOP,BOTTOM

80_OHM_DIFF

ISL3,ISL10

Y

0.081 MM 0.081 MM 0.115 MM 0.115 MM

0.090 MM

Y

0.090 MM

TOP,BOTTOM

55_OHM_SE

0.096 MM

ISL3,ISL10

40_OHM_SE

0.096 MM

Y

16.2

MM

NO_TYPE,BGA

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

?

0.100 MM

*

1:1_SPACING

**BGA

BGA_P1MM

MEM_CLK

* BGA

BGA_P2MM

CLK_SLOW

* BGA

BGA_P2MM

CLK_PCIE

* BGA

BGA_P2MM

DEFAULT

0 MM0 MM

10 MM

*N

100 MM100 MM

?

0.071 MM

TOP,BOTTOM

1x_DIELECTRIC

?

0.053 MM

ISL3,ISL10

1x_DIELECTRIC

*

0.1 MM

?

DEFAULT

=45_OHM_SE=45_OHM_SE

Y

DEFAULT

ISL4,ISL9

=45_OHM_SE=45_OHM_SE

Y

DEFAULT

ISL2,ISL11

=45_OHM_SE=45_OHM_SE

Y

ISL3,ISL10

DEFAULT

100 MM

=STANDARD=STANDARD=STANDARD35_OHM_SE

*N

100 MM

0.170 MM0.170 MM

40_OHM_SEYTOP,BOTTOM

0.096 MM0.096 MM

40_OHM_SEYISL2,ISL11

=STANDARD40_OHM_SE =STANDARD=STANDARD

*N

100 MM 100 MM

ISL4,ISL9

Y

40_OHM_SE

0.099 MM 0.099 MM

0.135 MM0.135 MM

45_OHM_SEYTOP,BOTTOM

0.075 MM0.075 MM

45_OHM_SEYISL2,ISL11

=STANDARD45_OHM_SE =STANDARD

*N

100 MM 100 MM

=STANDARD

0.080 MM0.080 MM

45_OHM_SE ISL4,ISL9

Y

0.075 MM0.075 MM

45_OHM_SE

ISL3,ISL10

Y

=STANDARD50_OHM_SE =STANDARD=STANDARD

*N

100 MM 100 MM

0.165 MM 0.130 MM0.130 MM0.165 MM

72_OHM_DIFF

TOP,BOTTOM

Y

72_OHM_DIFFYISL3,ISL10

0.109 MM 0.109 MM 0.150 MM 0.150 MM

72_OHM_DIFFYISL2,ISL11

0.109 MM 0.109 MM 0.150 MM 0.150 MM

72_OHM_DIFFYISL4,ISL9

0.114 MM 0.114 MM 0.150 MM 0.150 MM

ISL2,ISL11

80_OHM_DIFF

0.081 MM 0.081 MM 0.115 MM 0.115 MM

Y

100 MM 100 MM

72_OHM_DIFF

N*

=STANDARD =STANDARD =STANDARD

100 MM

80_OHM_DIFF

=STANDARD=STANDARD=STANDARD

*N

100 MM

80_OHM_DIFF

ISL4,ISL9

Y

0.088 MM 0.088 MM 0.110 MM 0.110 MM

TOP,BOTTOM

Y

50_OHM_SE

0.110 MM 0.110 MM

0.125 MM0.125 MM

35_OHM_SE ISL4,ISL9

Y

ISL2,ISL11

0.125 MM

Y

35_OHM_SE

0.125 MM

35_OHM_SE

0.125 MM0.125 MM

ISL3,ISL10

Y

35_OHM_SE

0.195 MM 0.195 MM

Y

TOP,BOTTOM

*

=DEFAULT

?

BGA_P1MM

=DEFAULT

?

BGA_P2MM

*

* ?

=DEFAULTSTANDARD

1x_DIELECTRIC

?

0.090 MM

*

?

0.050 MM

ISL4,ISL9

1x_DIELECTRIC

Y

=50_OHM_SE =50_OHM_SETOP,BOTTOM

DEFAULT

SYNC_MASTER=J13_CONSTRAINTS

SYNC_DATE=01/11/2012

PCB Rule Definitions

=DEFAULT =DEFAULT=DEFAULT=DEFAULT

*

STANDARD =DEFAULT=DEFAULT

TOP,BOTTOM

0.310 MM 0.310 MM

27P4_OHM_SE

Y

ISL2,ISL11

0.182 MM0.182 MM

27P4_OHM_SE

Y

27P4_OHM_SE

0.182 MM

ISL3,ISL10

Y

0.182 MM

0.182 MM 0.182 MM

27P4_OHM_SEYISL4,ISL9

=STANDARD =STANDARD =STANDARD

100 MM100 MM

*N

27P4_OHM_SE

051-9277

2.8.0

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