Apple A1466 Schematics

TABLE_TABLEOFCONTENTS_ITEM

DRAWING

TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_HEAD

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

PROPRIETARY PROPERTY OF APPLE INC.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

DESCRIPTION OF REVISION

CK APPD

21

1245678

B

D

6543

C

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

THE INFORMATION CONTAINED HEREIN IS THE

C

A

D

DATE

R

SHEET

Apple Inc.

THE POSESSOR AGREES TO THE FOLLOWING:

DRAWING TITLE

D

SIZE

REVISION

DRAWING NUMBER

BRANCH

REV ECN

7

B

3

II NOT TO REPRODUCE OR COPY IT

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

8

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

Schematic / PCB #’s

SCHEM,MLB,J13

2/23/12

1 OF 73

2012-02-23

1 OF 109

2.8.0

051-9277

Voltage & Load Side Current Sensing

12/02/2011

53

45

J11_MLB

SMBus Connections

10/04/2011

52

44

J11_MLB

LPC+SPI Debug Connector

09/08/2011

51

43

J11_MLB

SMC Support

11/10/2011

50

42

J13_MLB_NON_POR

SMC

10/17/2011

49

41

J13_MLB_NON_POR

Left I/O (LIO) Connector

11/10/2011

47

40

J13_MLB_NON_POR

External A USB3 Connector

09/30/2011

46

39

J11_MLB

SSD CONNECTOR

10/17/2011

45

38

J13_MLB_NON_POR

X21 WIRELESS CONNECTOR

10/11/2011

40

37

J11_MLB

TBT Power Support

11/10/2011

38

36

J13_MLB_NON_POR

Thunderbolt Host (2 of 2)

10/04/2011

37

35

J11_MLB

Thunderbolt Host (1 of 2)

09/30/2011

36

34

J11_MLB

SecureDigital Card Reader

11/10/2011

35

33

J13_MLB_NON_POR

DDR3 Bypassing/Termination

07/28/2011

34

32

K21_MLB

FSB/DDR3/FRAMEBUF Vref Margining

08/04/2011

33

31

J11_MLB

DDR3 DRAM CHANNEL B (32-63)

07/28/2011

32

30

K21_MLB

DDR3 DRAM CHANNEL B (0-31)

07/28/2011

31

29

K21_MLB

DDR3 DRAM CHANNEL A (32-63)

07/28/2011

30

28

K21_MLB

DDR3 DRAM CHANNEL A (0-31)

07/28/2011

29

27

K21_MLB

CPU Memory S3 Support

11/10/2011

28

26

J13_MLB_NON_POR

Clock (CK505) and Chipset Support

07/29/2011

27

25

K21_MLB

USB HUB & MUX

11/10/2011

26

24

J13_MLB_NON_POR

CPU & PCH XDP

10/17/2011

25

23

J13_MLB_NON_POR

PCH DECOUPLING

10/03/2011

24

22

J11_MLB

PCH GROUNDS

07/27/2011

23

21

J30_MLB

PCH POWER

09/30/2011

22

20

J11_MLB

PCH GPIO/MISC/NCTF

09/16/2011

21

19

J11_MLB

PCH PCI/USB/TP/RSVD

11/10/2011

20

18

J13_MLB_NON_POR

PCH DMI/FDI/PM/Graphics

07/27/2011

19

17

J30_MLB

PCH SATA/PCIe/CLK/LPC/SPI

07/27/2011

18

16

J30_MLB

CPU DECOUPLING-II

07/29/2011

17

15

K21_MLB

CPU DECOUPLING-I

10/03/2011

16

14

J11_MLB

CPU GROUNDS

07/27/2011

14

13

J30_MLB

CPU POWER

11/10/2011

13

12

J13_MLB_NON_POR

CPU DDR3 INTERFACES

07/27/2011

12

11

J30_MLB

CPU CLOCK/MISC/JTAG

07/27/2011

11

10

J30_MLB

CPU DMI/PEG/FDI/RSVD

10/17/2011

10

9

J13_MLB_NON_POR

Signal Aliases

11/10/2011

9

8

J13_MLB_NON_POR

Power Aliases

07/29/2011

8

7

K21_MLB

Functional Test / No Test

07/29/2011

7

6

K21_MLB

BOM Configuration

07/27/2011

5

J30_MLB

Revision History

07/27/2011

4

J30_MLB

Revision History

11/10/2011

3

J13_MLB_NON_POR

System Block Diagram

11/10/2011

2

J13_MLB_NON_POR

PCB Rule Definitions

01/11/2012

J13_CONSTRAINTS

109

73

Project Specific Constraints

01/11/2012

J13_CONSTRAINTS

108

72

SMC Constraints

01/11/2012

J13_CONSTRAINTS

106

71

Thunderbolt Constraints

01/11/2012

J13_CONSTRAINTS

105

70

PCH Constraints 2

01/11/2012

J13_CONSTRAINTS

103

69

PCH Constraints 1

01/11/2012

J13_CONSTRAINTS

102

68

Memory Constraints

01/11/2012

J13_CONSTRAINTS

101

67

CPU Constraints

01/11/2012

J13_CONSTRAINTS

100

66

LCD Backlight Driver

07/28/2011

K21_MLB

97

65

Thunderbolt Connector A

10/03/2011

J11_MLB

94

64

Internal DisplayPort Connector

07/28/2011

K21_MLB

90

63

Power Control 1/ENABLE

11/10/2011

J13_MLB_NON_POR

79

62

Power FETs

07/28/2011

K21_MLB

78

61

Misc Power Supplies

07/28/2011

K21_MLB

77

60

CPU VCCIO (1.05V) Power Supply

10/17/2011

J13_MLB_NON_POR

76

59

CPU IMVP7 & AXG VCore Output

10/17/2011

J13_MLB_NON_POR

75

58

CPU IMVP7 & AXG VCore Regulator

10/14/2011

J11_MLB

74

57

1.5V DDR3 Supply

12/02/2011

J11_MLB

73

56

5V / 3.3V Power Supply

10/17/2011

J13_MLB_NON_POR

72

55

System Agent Supply

10/17/2011

J13_MLB_NON_POR

71

54

PBus Supply & Battery Charger

11/10/2011

J13_MLB_NON_POR

70

53

DC-In & Battery Connectors

11/10/2011

J13_MLB_NON_POR

69

52

AUDI0: SPEAKER AMP

09/30/2011

J11_MLB

62

51

SPI ROM

07/28/2011

K21_MLB

61

50

IPD / KBD Backlight

11/10/2011

J13_MLB_NON_POR

57

49

Fan

07/28/2011

K21_MLB

56

48

Thermal Sensors

08/03/2011

J11_MLB

55

47

TITLE=MLB ABBREV=DRAWING

LAST_MODIFIED=Thu Feb 23 17:52:06 2012

CRITICAL

1 PCB

PCBF,MLB,J13

820-3209

Page

Date

(.csa)

Contents

Sync Page

(.csa)

Date

Sync

Contents

1 SCH

051-9277

SCHEM,MLB,J13

CRITICAL

SCHEM,MLB,J13

Table of Contents

07/27/2011

1

J30_MLB

High Side Current Sensing

10/17/2011

J13_MLB_NON_POR

54

46

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PCI-E

TMDS OUT

64-bit

MEMORY

DDR3-1600MHZ

DUAL Channel

A

x8

PG 27,28

MEMORY

B

PA_AUX

PA_DPSRC_1

x4

DPC

DP0, x1

EDP

PG 9

PCI-E

PG 9

PCIE1

RTC

PG 16

Xtal

25MHz

EEPROM

PA_LSTX/LSRX

SPI

PA_CIO0

PA_CIO1

PA_DPSRC_3

PCIe x4

U3690

U3600

PG 34

PG 34,35 37

PG 25

TBT Host

PG 11

CONN

LEFT SPEAKER

U6201

LID

I2C

LEFT L/O CONN

USB PORT B

J4610

CAMERA +ALS CONN

I2C

USB CAMERA

LEFT USB EXTB

PG 7

HALL

J4750

Re-DRIVER

U4700

PG 40

USB3

PG 24

U2660

EXTERNAL

(LEFT PORT)

THERMAL

EFFECT

SPK

U6210

SPEAKER

AMP

PG 51

J6903

PG 52

CONN

RIGHT SPEAKER

PG 7

MIC

LINE IN JACK

HEADPHONE/

PG 9

Filter

J4600

SD CARD

SERIAL PORT

Boot ROM

SPI

BUFFER

1

USB 3

6

47

0

1

4

3

8

9234

Conn

CLOCK

U2700

DPMLO

MUX

AUXIO

DISPLAY PORT

PG 64

U9420

DP OUT

DPB

/ TBT

PG 64

J9400

HDMI OUT

LVDS OUT

UP TO 8 LANES

61835

SPI

PG 38

HDD

SATA

J4501

EDP

CONN

J9000

5

7

Audio Codec

PG

J6700

2

J6701

SPEAKER

AMP

PG 10

U6620

PG 11

HDA

J4720

CONN

J6702

J4001

SNK1

SNK0

J4700

PG 11

U4650

CONN

U5700

USB

PM_SLP S3/S4

U4900

43

U3500

CONTROLLER

I2C

PG 7

PG

FILTER

LIO BOARD

CONN

LPC+SPI

J5100

U4730

1

MOJO SMC

DEBUG MUX

J3500

U5510

U5410

J5700

USB MUX

USB A

ADC

FAN0

SMB_3

SMB_5 SMB_1

PG 54-60

POWER CIRCUIT

PG 52,53

SMC

PG 41

2

SD CARD

USB

(UP TO 10 DEVICES)

U6100

U2600

USB HUB

PG 6

X21

CONN

PG 37

WIRELESS

PG 63

PWR

PG 17

PG 18

SMBUS

PCI

HDA

Misc

PG 18

2

LINE IN

CTRL

PG 17

PG 16

GPIOs

25MHz

SATA0

SATA

UP TO 6

PG 16

JTAG

DVI OUT

RGB OUT

PG 16

J2550

PG 23

XDP CONN

PCH

HEADPHONE

SYSTEM

SENSOR

PG 24

PG 35

PG 39

PG 40

PG 43

PG 49

SMB_2

LID

KBDLED

PG 48

FAN CONN

J5600

PG 45,46

PG 49

KBD CONN

J5715

PG 49

U5750

J4001

Bluetooth

PG 37

(ON AP)

PG 50

CPU TEMP SENSOR

PG 46,47

PG 38

U4510

MUX

LPC

1017P

U1800

PANTHER POINT - MPCH

PG 19

J6950,U7000

PG 47

TBT/MLBBOT/INLET TEMP SENSOR

VOLTAGE/CURRENT SENSOR

PG 16

PG 19

PG 23

PG 49

TRACKPAD

U1000

PG 17

DMI

CLK

32KHz

PCIE0

IVY BRIDGE 2C-35W

AXG=GT2, ULV, 1023P

INTEL CPU

PG 17

FDI

PG 11

DMI

PG 9PG 9

EDP

INTEL

PG 10

JTAG

FDI

MUX

XHCI/EHCI2

KBD DRIVER

CHARGER

J2500

CPU

XDP CONN

U3100-U3130 U3200-U3230

MEMORY

x8

PG 29,30

U3000-U3030

U2900-U2930

SYNC_MASTER=J13_MLB_NON_POR

SYNC_DATE=11/10/2011

System Block Diagram

051-9277

2.8.0

2 OF 109

2 OF 73

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

3.3V

(R/H)

TPS51980

A

AC

ADAPTER

A

R7050

PPVBAT_G3H_CHRG_RET

1

D7005

SMC_GFX_VSENSE

PPDCIN_G3H_OR_PBUS

PP5V5_CHAR_VDDP

1

SMC_DCIN_ISENSE

R7020

J6900

26

TBT_PWR_EN

PM_SLP_S3_L

RSMRST_OUT(P15)

1V05_S0_LDO_EN

U1800

PM_PCH_PWRGD

(PAGE 16~21)

(PAGE 41)

BATTERY CHARGER

CHGR_BGATE

F6901

U7000

ISL6259HRTZ

EN/UVLO

1

(PAGE 53)

LT3470A

VOUT

F7040

PPBUS_G3H

CPUIMVP_AXG_PGOOD

25-1

PPVCORE_S0_AXG_REG

(PAGE 36)

TPS22920

A

VOUT

R0954

VR_ON

(PAGE 57)

PGOOD

PGOODG

VLDOIN

PPVTT_S0_DDR_LDO

VOUT2

SMC_SYS_KBDLED

PP3V3_S0_SSD_R

PPVOUT_SW_LCDBKLT

16

PP1V05_S0_VMON

PP1V5_S3RS0_VMON

PP5V_S0_VMON

PP5V_S0_FET

PGOOD

LCD_BKLT_EN

SMC_BATT_ISENSE

PP5V5_CHRG_VDDP

VIN

SMC_RESET_L

U7090

(PAGE 53)

PBUS SUPPLY/

V

ENABLE

2

ENABLE

PP3V42_G3H_REG

(PAGE 52)

LT3470A

3.425V G3HOT

U6990

D6905

SMC_GFX_ISENSE

R7510

CPUVCCIOS0_PGOOD

CPUIMVP_PGOOD

PPDDR_S3_REG

Q7801

SMC

J6950

2S3P

(6 TO 8.4V)

U4900

Q7840

PP5V_SUS_FET

P3V3S3_EN

P5V_3V3_SUS_EN

TPS720105

(PAGE 60)

V

P3V3S5_EN

A

PPVBATT_G3H_CONN

Q7055

PPVBAT_G3H_CHGR_R

IN

DCIN(14.5V)

4

6A FUSE

Q5310

VOUT

ISL95870AH

0.75V

U7300

(PAGE 56)

TPS51916

24

1.5V

U7100

(PAGE 54)

PVCCSA_PGOOD

VCC

U7400

CPU VCORE

EN

VID1

Q5300

USB_PWR_EN

(PCH)

DDRREG_EN

PG62

DELAY

RC

R7962

PP1V05_SUS_LDO

U7960

ISL88042IRTEZ

VDD

MIC2292

OUT

PAGE49

PP3V3_S0_VMON

6

IMVP_VR_ON(P16)

R7978

PM_SLP_S3_L

CPU

U2760

8

PP5V_S0_KBDLED

Q7860

14

PP5V_S3_REG

V2MON

15

4

SMC_ONOFF_L

10-4

CPU_VCCSA_VID<0>

PGOOD

PVCCSA_PGOOD

PPVCCSA_S0_REG

R6906

23-1

PM_SLP_S5_L

DPWROK

SMC_DELAYED_PWRGD

ALL_SYS_PWRGD

DRAMPWROK

P1V5CPU_EN

A

U2750

VOUT1

PM_S0_PGOOD

CPUVCCIOS0_PGOOD

A

P3V3S5_PGOOD

P5VS3_PGOOD

P1V8S0_PGOOD

R7550

PLTRST#

16

R7350

DDRREG_PGOOD

RST*

COUGAR-POINT

SYS_RERST#

SLP_S3#(F4)

(PAGE 16~21)

SLP_S5_L(P95)

99ms DLY

P17(BTN_OUT)

(PAGE 9~13)

PWRBTN#

SMC

P5VS3_PGOOD

PP3V3_S5_REG

CPU_VCCSA_VID<1>

PP5V_S0_VCCSA

VOUT1

(L/H)

SMC_PBUS_VSENSE

P3V3S5_EN

CPUIMVP_VR_ON

PM_RSMRST_L

SLP_SUS#

U1800

SLP_S4#(H4)

CPUVCCIOS0_EN

21

14-1

PP3V3_S5

DDRVTT_EN

DDRREG_EN

VCC

VID0

PPVIN_S5_P5VP3V3

PPVCORE_S0_CPU_REG

V3MON

22

VIN

EN

PVCCSA_EN

MAX15120

CPUIMVP_VR_ON

25

PP1V05_TBTCIO_FET

SMC_CPU_ISENSE

EN

R7140

16-1

R7640

21

A

PGOOD

VIN

VOUT

VIN

SMC_CPU_FSB_ISENSE

(PAGE 59)

VIN

PP3V3_SUS_FET

A

VOUT

14-1

TBTBST_EN_UVLO

Q9706

BKLT_PLT_RST_L

13-2

P3V3S5_PGOOD

(PAGE 55)

VOUT2

3A 32V

F9700

PBUSVSENS_EN

(PAGE 65)

PM_SLP_S4_L

14

BKL_EN

15

Q7820

LP8550

U9701

SMC_PBUS_VSENSE

Q5300

PGOOD

A

P5V_3V3_SUS_EN

(PAGE 36)

P1V8_S0_EN

17

PP3V3_T29_FET

PP1V5S0_EN

10-2

A

R4599

R7831

T29_PWR_EN

Q7810

Q7830

P3V3S0_EN

14

PP3V3_S3_FET

EN

VIN

U7740

10-3

14-1

PP3V3_S0

R5430

P5VS3_EN

11

PM_SLP_S5_L

7

U7201

13

PP5V_S0_CPUVCCIOS0.

6-1

SYSRST(PA2)

PM_SYSRST_L

PM_PWRBTN_L

SMC_RESET_L

U4900

5

PPCPUVCCIO_S0_REG

29

PM_RSMRST_L

PM_PWRBTN_L

PM_SYSRST_L

PM_DSW_PWRGD

28

PM_MEM_PWRGD

10

P15

4

26

12

PROCPWRGD

RSMRST#

4

SMC_RESET_L

22

U5010

SN0903048

SMC POWER

(PAGE 42)

3

U7600

CPUVCCIOS0_EN

(PCH)

U1000

RSMRST_IN(P13)

PWR_BUTTON(P90)

PWRGD(P12)

SLP_S3_L(P93)

9

PM_SLP_S4_L

V4MON

(PAGE 62)

18

19

U7770

TPS72015

(PAGE 60)

TPS720105

U7780

(PAGE 60)

EN

P1V8S0_PGOOD

S5

S3

VOUT

PP1V8_S0_REG

U7720

ISL8014A

EN

(PAGE 60)

EN

9

R6905

5V

EN1

EN2

7

PG 17

PG62

VIN

EN

VOUT

PP15V_T29_REG

(PAGE 36)

VIN

LT3957

U3890

Q3880

&&

13

PG62

PG 17

T29_A_HV_EN

14-1

PBUSVSENS_EN

PG62

P5V_3V3_SUS_EN

P3V3S0_EN

P5VS3_EN

6

RC

DELAY

U7940

RC

SLP_S5#(E4)

SMC_PM_G2_EN

P60

PM_SLP_S3_R_L

21

22

17

19

1V05_S0_LDO_EN

PVCCSA_EN

RC

DELAY

RC

P1V8S0_EN

P1V5S0_EN

DELAY

RC

DELAY

P5VS0_EN

14-1

EN

(PAGE 41)

27

U3816/U3820

PM_DSW_PWRGD

ISL95870

1.05V

PPVIN_G3H_P3V42G3H

22-1

15

A

TPS22924

U3810

PP1V05_S0_LDO.

PP1V5_S0_REG

PLT_RERST_L

CPU_PWRGD

30

SM_DRAMPWROK

UNCOREPWRGOOD

RESET*

23

PP1V5_S3RS0_FET

13-1

PM_SLP_SUS_L

COUGAR-POINT

DELAY

P3V3S3_EN

PG61

10-1

J13 POWER SYSTEM ARCHITECTURE

P5VS0_EN

U5750

KBDLED_ANPDE

ALL_SYS_PWRGD

S5_PWRGD

25

SLP_S4_L(P94)

Revision History

SYNC_DATE=11/10/2011

3 OF 73

3 OF 109

2.8.0

051-9277

TABLE_BOMGROUP_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

BOM Variants

Bar Code Labels / EEEE #’s

Sub BOM

J13_CMNPTS,EEEE:F27Q,CPU:1.8GHZ,DDR3:SAMSUNG_8GB

PCBA,MLB,1.8GHZ,SA 8GB,J13

639-3791

J13_CMNPTS,EEEE:F27R,CPU:2.0GHZ,DDR3:SAMSUNG_8GB

PCBA,MLB,2.0GHZ,SA 8GB,J13

639-3792

J13_CMNPTS,EEEE:F27V,CPU:1.7GHZ,DDR3:SAMSUNG_8GB

PCBA,MLB,1.7GHZ,SA 8GB,J13

639-3790

PCBA,MLB,2.0GHZ,EL 8GB,J13

639-3767

J13_CMNPTS,EEEE:F25V,CPU:2.0GHZ,DDR3:ELPIDA_8GB

J13_CMNPTS,EEEE:F27W,CPU:1.7GHZ,DDR3:ELPIDA_4GB

PCBA,MLB,1.7GHZ,EL 4GB,J13

639-3793

PCBA,MLB,2.0GHZ,HY 4GB,J13

639-3766

J13_CMNPTS,EEEE:F25R,CPU:2.0GHZ,DDR3:HYNIX_4GB

639-3765

PCBA,MLB,2.0GHZ,HY 8GB,J13

J13_CMNPTS,EEEE:F25W,CPU:2.0GHZ,DDR3:HYNIX_8GB

639-3764

PCBA,MLB,2.0GHZ,SA 4GB,J13

J13_CMNPTS,EEEE:F25N,CPU:2.0GHZ,DDR3:SAMSUNG_4GB

639-3762

PCBA,MLB,1.8GHZ,HY 4GB,J13

J13_CMNPTS,EEEE:F25Y,CPU:1.8GHZ,DDR3:HYNIX_4GB

J13_CMNPTS,EEEE:F25T,CPU:1.8GHZ,DDR3:HYNIX_8GB

639-3761

PCBA,MLB,1.8GHZ,HY 8GB,J13

J13_CMNPTS,EEEE:F0TD,CPU:1.7GHZ,DDR3:ELPIDA_8GB

639-3644

PCBA,MLB,1.7GHZ,EL 8GB,J13

PCBA,MLB,1.7GHZ,HY 8GB,J13

639-3556

J13_CMNPTS,EEEE:DYRK,CPU:1.7GHZ,DDR3:HYNIX_8GB

085-3939

J13 MLB DEVELOPMENT BOM

J13_DEVEL:ENG

J13_CMNPTS,EEEE:F25Q,CPU:1.8GHZ,DDR3:SAMSUNG_4GB

PCBA,MLB,1.8GHZ,SA 4GB,J13

639-3760

639-3763

PCBA,MLB,1.8GHZ,EL 8GB,J13

J13_CMNPTS,EEEE:F25P,CPU:1.8GHZ,DDR3:ELPIDA_8GB

PCBA,MLB,1.5GHZ,EL 8GB,J13

639-3645

J13_CMNPTS,EEEE:F0TC,CPU:1.5GHZ,DDR3:ELPIDA_8GB

SYNC_DATE=07/27/2011

SYNC_MASTER=J30_MLB

Revision History

J13_CMNPTS,EEEE:F27Y,CPU:1.8GHZ,DDR3:ELPIDA_4GB

PCBA,MLB,1.8GHZ,EL 4GB,J13

639-3794

J13_CMNPTS,EEEE:DYRM,CPU:1.5GHZ,DDR3:SAMSUNG_4GB

639-3553

PCBA,MLB,1.5GHZ,SA 4GB,J13

CRITICAL

EEEE:F25Q

[EEEE_F25Q]

825-7670

LBL,P/N LABEL,PCB,28MM X 6 MM

1

[EEEE_F25R]

1

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

825-7670

EEEE:F25R

1

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

825-7670

[EEEE_F27V]

EEEE:F27V

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

1

825-7670

[EEEE_F27W]

EEEE:F27W

[EEEE_F25W]

1

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

825-7670

EEEE:F25W

LBL,P/N LABEL,PCB,28MM X 6 MM

825-7670 CRITICAL

1

[EEEE_DYRQ]

EEEE:DYRQ

EEEE:F25P

[EEEE_F25P]

825-7670

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

1

[EEEE_F25N]

EEEE:F25N

825-7670

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

1

[EEEE_F25V]

1

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

825-7670

EEEE:F25V

1

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

825-7670

[EEEE_F27R]

EEEE:F27R

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

1

825-7670

[EEEE_F27Y]

EEEE:F27Y

1

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

825-7670

[EEEE_F27Q]

EEEE:F27Q

[EEEE_F27T]

1

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

825-7670

EEEE:F27T

[EEEE_F25T]

1

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

825-7670

EEEE:F25T

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

1

825-7670

[EEEE_F25Y]

EEEE:F25Y

J13_CMNPTS

CMN PTS,PCBA,MLB,J13

607-9090

CMNPTS

CRITICAL

1

085-3939

DEVEL_BOM

DEVEL

1

CRITICAL

J13 MLB DEVELOPMENT

825-7670

EEEE:F0TD

[EEEE_F0TD]

1

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_DYRP]

EEEE:DYRP

825-7670

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

1

EEEE:DYRM

[EEEE_DYRM]

825-7670

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

1

LBL,P/N LABEL,PCB,28MM X 6 MM

EEEE:F0TC

[EEEE_F0TC]

825-7670 CRITICAL

1

EEEE:DYRL

[EEEE_DYRL]

825-7670

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

1

EEEE:DYRN

[EEEE_DYRN]

825-7670

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

1

[EEEE_DYRK]

EEEE:DYRK

825-7670

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

1

J13_CMNPTS,EEEE:DYRN,CPU:1.5GHZ,DDR3:HYNIX_4GB

639-3554

PCBA,MLB,1.5GHZ,HY 4GB,J13

J13_CMNPTS,EEEE:DYRL,CPU:1.5GHZ,DDR3:HYNIX_8GB

639-3555

PCBA,MLB,1.5GHZ,HY 8GB,J13

J13_CMNPTS,EEEE:DYRP,CPU:1.7GHZ,DDR3:HYNIX_4GB

639-3557

PCBA,MLB,1.7GHZ,HY 4GB,J13

J13_CMNPTS,EEEE:DYRQ,CPU:1.7GHZ,DDR3:SAMSUNG_4GB

639-3552

PCBA,MLB,1.7GHZ,SA 4GB,J13

CMN PTS,PCBA,MLB,J13

J13_COMMON

607-9090

J13_CMNPTS,EEEE:F27T,CPU:2.0GHZ,DDR3:ELPIDA_4GB

639-3795

PCBA,MLB,2.0GHZ,EL 4GB,J13

051-9277

2.8.0

4 OF 109

4 OF 73

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

Module Parts

DRAM CFG CHART

MICRON

Programmable Parts

Alternate Parts

1

0

B

A

DIE REV

CFG 3

00

CFG 1 CFG 0

VENDOR

HYNIX

1

0

CFG 2

1

0

1

ELPIDA

SIZE

4GB

SAMSUNG

8GB

PD Module Parts

J13 BOM GROUPS

371S0558371S0713

ALL

337S4196337S4236

ALL

337S4198

152S1462

353S1428

372S0185

152S1307

Murata alt to Taiyo Yuden

Coilcraft alt to Murata

CPUMEM_SLG:NO,HUB_3NONREM,TBT,MPM5:YES,PP5V5_DCIN:NO,TPAD_PCH:NO,SKIP_5V3V3:INAUDIBLE,BTPWR:S4,TBTHV:P15V,LVDDR3_HW:YES,AXG_ACOUSTIC:NO

BOOTROM_PROG,SMC_PROG,TBTROM:PROG

ALTERNATE,BKLT:ENG,XDP_CONN,XDP_CPU:BPM,XDP_PCH,LPCPLUS,DDRVREF_DAC,VREFDQ:M1_M3,VREFCA:LDO_DAC,S0PGOOD_ISL,S3_S0_LED,VCCIOISNS_ENG,AIRPORTISNS_ENG,HDDISNS_ENG,LCDBKLTISNS_ENG

LPCPLUS,XDP_CONN

DEVEL_BOM,MOJO:YES,XDP

BKLT:PROD,MOJO:YES,XDP,XDP_CPU:BPM,VREFDQ:LDO,VREFCA:LDO,LPCPLUS,VCCIOISNS_PROD,AIRPORTISNS_PROD,HDDISNS_PROD,LCDBKLTISNS_PROD

RAMCFG0:L,RAMCFG1:L,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:HYNIX_4GB

ALTERNATE,COMMON,J13_MISC,J13_DEBUG:ENG,J13_PROGPARTS,USBHUB2514B,EDP:YES,PCH_C1

IC,SDRAM,2GBIT,DDR3L-1600,REV D.78P FBGA

IC,SDRAM,2GBIT,DDR3L-1600,REV D,78P FBGA

DRAM_TYPE:ELPIDA_4GB

333S0628

U3200,U3210,U3220,U3230

CRITICAL

4

U3100,U3110,U3120,U3130

CRITICAL

4

CRITICAL

IC,SDRAM,4GBIT,DDR3L-1600,REV B,78P FBGA

DRAM_TYPE:ELPIDA_8GB

U2900,U2910,U2920,U2930

CRITICAL

IC,SDRAM,4GBIT,DDR3L-1600,REV B.78P FBGA

DRAM_TYPE:ELPIDA_8GB

CRITICAL

4

U3000,U3010,U3020,U3030

IC,SDRAM,4GBIT,DDR3L-1600,REV B,78P FGBA

DRAM_TYPE:ELPIDA_8GB

4

CRITICAL

U3100,U3110,U3120,U3130

IC,SDRAM,4GBIT,DDR3L-1600,REV B,78P FBGA

DRAM_TYPE:ELPIDA_8GB

CRITICAL

U3200,U3210,U3220,U3230

CRITICAL

1

806-3083

SHLD,USB,MLB,J11/J13

USBCAN

K78, mDP Spring

1

806-2377

CRITICAL

MDPSPRING

NOSTUFF

MDPCAN

1

CRITICAL

806-3216

CAN,MDP,J11/J13

CAN,TOPSIDE_2Piece_Fence,J11/J13

CRITICAL

1

806-3705

TBTTOPSIDE_2P_FENCE

1

CAN,TOPSIDE,J11/J13

806-3214

CRITICAL

TBTTOPSIDE_1P

CAN,TOPSIDE_2Piece_Cover,J11/J13

1

CRITICAL

806-3706

TBTTOPSIDE_2P_COVER

CRITICAL

1

806-3215

CAN,COVER,T29,J11/J13

TBTCOVER

1

U7000

IC,ISL6259,BATCHARGER,3%,4X4MM,QFN28

CRITICAL

353S2929

806-3142

CRITICAL

1

CAN,T29,J11/J13

TBTFENCE

GLUE

946-3115

1

MLB,DYMAX UV EB 0.22GRAM,K21

CRITICAL

RAMCFG0:H,RAMCFG1:H,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:ELPIDA_4GB

RAMCFG0:L,RAMCFG1:H,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:SAMSUNG_8GB

RAMCFG0:L,RAMCFG1:H,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:SAMSUNG_4GB

IC,SDRAM,2GBIT,256MX8,DDR3-1600,78P FBGA

4

DRAM_TYPE:HYNIX_4GB

333S0622

CRITICAL

U3100,U3110,U3120,U3130

4

CRITICAL

IC,SDRAM,4GBIT,512MXB,DDR3-1600,82 FGBA

IC,SDRAM,4GBIT,DDR3-1600,78P FBGA,C-DIE

U3200,U3210,U3220,U3230

CRITICAL

4

U3100,U3110,U3120,U3130

U3000,U3010,U3020,U3030

CRITICAL

IC,SDRAM,4GBIT,DDR3-1600,78P FBGA,C-DIE

DRAM_TYPE:SAMSUNG_8GB

4

IC,SDRAM,4GBIT,DDR3-1600,78P FBGA,C-DIE

333S0623

DRAM_TYPE:SAMSUNG_4GB

CRITICAL

4

IC,SDRAM,2GBIT,DDR3-1600,78P FBGA,D-DIE

CRITICAL

DRAM_TYPE:SAMSUNG_4GB

4

CRITICAL

333S0623

IC,SDRAM,2GBIT,DDR3-1600,78P FBGA,D-DIE

U3200,U3210,U3220,U3230

IC,SDRAM,4GBIT,512MXB,DDR3-1600,82 FBGA

CRITICAL

4

IC,SDRAM,4GBIT,512MXB,DDR3-1600,82 FPGA

DRAM_TYPE:HYNIX_8GB

CRITICAL

4

IC,SDRAM,4GBIT,512MXB,DDR3-1600,82 FBGA

U2900,U2910,U2920,U2930

DRAM_TYPE:HYNIX_8GB

4

U3200,U3210,U3220,U3230

CRITICAL

4

IC,SDRAM,2GBIT,256MX8,DDR3-1600,78P FBGA

333S0622

NXP alt to NXP

ALL

371S0652371S0709

376S0928376S0790

TI alt to Fairchild

138S0671

ALL

Taiyo alt to Murata

138S0673

TBTROM:BLANK

CRITICAL

1

IC,SERIAL SPI EEPROM,256KBIT,20MHZ,MLP8

335S0865

376S0604

Diodes alt to Fairchild

ALL

376S0855

ALL

376S0903

197S0432197S0431

ALL

Toko alt for NEC inductor

152S1295

ALL

152S1493 152S1300

ALL

353S3238

ALL

Intersil alt to OPA2333

U4900

SMC_BLANK

CRITICAL

1

IC,SMC12,40MHZ/50DMIPS MCU, 9X9,157BGA

338S1065

64 MBIT SPI SERIAL DUAL I/O FLASH,Macronix

CRITICAL

1

BOOTROM_BLANK

335S0809

U6100

376S0855

Diodes alt to Toshiba

376S0613

ALL

U3100,U3110,U3120,U3130

CRITICAL

333S0622

IC,SDRAM,2GBIT,256MX8,DDR3-1600,78P FGBA

4

IC,SDRAM,2GBIT,256MX8,DDR3-1600,78P FPGA

DRAM_TYPE:HYNIX_4GB

CRITICAL

4

333S0622

CPU:1.7GHZ

CRITICAL

1

U1000

CPU:1.5GHZU1000

1

CRITICAL

CPU:1.8GHZ

CRITICAL

U1000

1

U1000

CRITICAL

1

U1800

PCH_ES1

1

U3600

338S1047

TBT

IC,TBT,CR-4C,ES1,288 FCBGA,12X12MM

PCH_ES2

CRITICAL337S4180

CRITICAL

U1800

1

PCH_C0

IC,PCH,PPT-MB,QS77,C1,QS

337S4275

PCH_C1

1

U1800

CRITICAL

ALL

Toko alt for Cyntec

152S1085

ALL

Murata alt to Taiyo Yuden

138S0648

ALL

138S0684 138S0660

ALL

372S0186

64 MBIT SPI SERIAL DUAL I/O FLASH,Numonyx

CRITICAL

BOOTROM_BLANK

U6100

1

335S0803

ALL

376S0859

Diodes alt to Toshiba

376S0977

138S0676

ALL

138S0691

Murata alt to Samsung

ALL

Rohm alt to Toshiba

376S0972 376S0612

J13_DEBUG:PROD

J13_DEVEL:PVT

J13_DEVEL:ENG

J13_PROGPARTS

J13_MISC

J13_COMMON

J13_DEBUG:ENG

DDR3:SAMSUNG_8GB

DDR3:ELPIDA_4GB

BOM Configuration

SYNC_DATE=07/27/2011

SYNC_MASTER=J30_MLB

J13_DEBUG:PVT

DDR3:HYNIX_4GB

RAMCFG0:L,RAMCFG1:L,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:HYNIX_8GB

DDR3:HYNIX_8GB

DDR3:SAMSUNG_4GB

IC,EEPROM,CR,V24.1,J11/J13

341S3475

TBTROM:PROG

1

IC,EFI ROM,PROTO1B,J13 J11

341S3482 CRITICAL

BOOTROM_PROG

U6100

1

341S3433

U4900

CRITICAL

1

SMC_PROG

IC,SMC,V2.1A43,Proto1B,J13

IC,SMC12-A3,40MHZ/50DMIPS MCU,9X9,157BGA

SMC_BLANK

CRITICAL

1

338S1098

DDR3:ELPIDA_8GB

376S0796

376S1053

376S0613

NXP alt to Diodes

Diodes alt to Toshiba

Fairchild alt to Siliconix

Epson alt to NDK

TDP 1.5GHZ alt to Nominal

TDP 1.7GHZ alt to Nominal

Diodes alt to ST Micro

128S0333

ALL

Sanyo alt to Kemet

998-4435

128S0357

Sanyo alt to POS caps

998-4435

ALL

Kemet_Rect alt to POS caps

998-4435998-4715

ALL

Kemet_.0045 Flute alt to POS caps

998-4435998-4716

ALL

DRAM_TYPE:SAMSUNG_8GB

DRAM_TYPE:HYNIX_8GB

DRAM_TYPE:SAMSUNG_4GB

DRAM_TYPE:SAMSUNG_8GB

CRITICAL

4

333S0623

U2900,U2910,U2920,U2930

U3000,U3010,U3020,U3030

IC,SDRAM,2GBIT,DDR3L-1600,REV D,78P FGBA

IC,SDRAM,2GBIT,DDR3L-1600,REV D,78P FBGA

333S0623

333S0625

4

333S0629

333S0628

333S0642

4

IC,SDRAM,2GBIT,DDR3-1600,78P FGBA,D-DIE

IC,SDRAM,2GBIT,DDR3-1600,78P FBGA,D-DIE

IC,SDRAM,4GBIT,DDR3-1600,78P FGBA,C-DIE

333S0629

4

138S0703

CRITICAL

U3000,U3010,U3020,U3030

RAMCFG0:H,RAMCFG1:H,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:ELPIDA_8GB

DEVEL_BOM,BKLT:PROD,MOJO:YES,XDP,XDP_CPU:BPM,VREFDQ:LDO,VREFCA:LDO,VCCIOISNS_PROD,AIRPORTISNS_PROD,HDDISNS_PROD,LCDBKLTISNS_PROD

CRITICAL

ALL

337S4197

U3690

U4900

DRAM_TYPE:HYNIX_4GB

CRITICAL

U2900,U2910,U2920,U2930

U3200,U3210,U3220,U3230

U3100,U3110,U3120,U3130

U3000,U3010,U3020,U3030

U2900,U2910,U2920,U2930

U3000,U3010,U3020,U3030

U2900,U2910,U2920,U2930

DRAM_TYPE:HYNIX_4GB

DRAM_TYPE:HYNIX_8GB

DRAM_TYPE:SAMSUNG_4GB

IVB,QBP8,ES2,K0,1.5,17W,2+2,0.95,4M,ULVB

U1800

CRITICAL

CPU:1.7GHZTDP

CPU:1.5GHZTDP

CPU:2.0GHZ

CRITICAL

U1000

CRITICAL

IC,PCH,PPT-MB,SFF,ES2,B0

IC,PCH,PPT-MB,SFF,ES1

1

337S4235

337S4197

IC,PCH,PPT-MB,SFF,P-QS,C0

1

IVB,QBQF,ES2,K0,1.7,17W,2+2,1.0,4M,ULV,TDP

IVB,QBP8,ES2,K0,1.5,17W,2+2,0.95,4M,ULVB

IVB,QC55,QS,L0,1.7,17W,2+2,1.0,3M,ULVBGA

IVB,QC54,QS,L0,1.8,17W,2+2,1.1,3M,ULVBGA

IVB,QC52,QS,L0,2.0,17W,2+2,1.1,4M,ULVBGA

1

337S4165

337S4236

337S4198

337S4296

337S4298

337S4299

051-9277

2.8.0

5 OF 109

5 OF 73

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

FUNC_TEST

(Need to add 2 GND TPs)

POWER SIGNALS

NO_TEST

NO_TEST Nets

FUNC_TEST

J5600: Fan Connector

(Need to add 1 GND TP)

FUNC_TEST

(Need to add 5 GND TPs)

J5700: IPD Flex Connector

(Need to add 6 GND TPs)

FUNC_TEST

J5100: LPC+SPI Connector

(Need to add 8 GND TPs)

(Need 5 TPs)

Functional Test Points

FUNC_TEST

(Need 2 TPs)

(Need to add 2 GND TP)

J5715: KB BKLT CONNECTOR

FUNC_TEST

(Need to add 27 GND TPs)

(Need 5 TPs)

(Need to add 6 GND TPs)

J4501: SATA SSD Connector

FUNC_TEST

(Need 6 TPs)

(Need to add 5 GND TPs)

J6900: DC-In Connector

FUNC_TEST

(Need 4 TPs)

(Need to add 3 GND TPs)

J6903: Speaker Connector

FUNC_TEST

(Need 2 TPs)

(Need to add 5 GND TPs)

FUNC_TEST

J4001: AirPort / BT Connector

J4700: LIO Connector

(Need to add 4 GND TPs near

J6950: Battery Connector

J9000: Internal DP Connector

J6950 and 1 for shield)

FUNC_TEST

(Need 2 TPs)

Misc Voltages & Control Signals

(Need to add 5 GND TPs)

J4800: SD Card Connector

SYNC_DATE=07/29/2011

SYNC_MASTER=K21_MLB

Functional Test / No Test

TRUE

PPVBAT_G3H_CONN

TRUE

SPKRAMP_ROUT_N

TRUE

=SMBUS_BATT_SDA

TRUE

USB_BT_CONN_P

TRUE

NC_PCIE_CLK100M_PE7N

MAKE_BASE=TRUE

TRUE

PP1V5_S0

TP_PCI_CLK33M_OUT3

TP_PCI_PME_L

NC_PCIE_CLK100M_PE7P

TRUE MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE4N

TRUE MAKE_BASE=TRUE

AP_CLKREQ_Q_L

TRUE

PCIE_AP_D2R_N

TRUE

PCIE_AP_D2R_P

TRUE

PCIE_CLK100M_AP_P

TRUE

PCIE_CLK100M_AP_N

TRUE

PCIE_AP_R2D_P

AP_RESET_CONN_L

TRUE

DP_INT_ML_F_N<1>

TRUE

DP_INT_ML_F_P<1>

TRUE

DP_INT_ML_F_P<0>

TRUE

DP_INT_AUX_CH_C_P

TRUE

DP_INT_AUX_CH_C_N

TRUE

LED_RETURN_1

TRUE

LED_RETURN_2

TRUE

LED_RETURN_3

TRUE

LED_RETURN_5

TRUE

LED_RETURN_6

I2C_TCON_SCL_R

TRUE

I2C_TCON_SDA_R

PPVOUT_SW_LCDBKLT

TRUE

PP3V3_SW_LCD

TRUE

PP3V3_S4

PP5V_S0

PP5V_S3

PPDCIN_G3H_ISOL

PPBUS_S5_HS_OTHER_ISNS

PP1V05_TBTCIO

PP1V8_S0_CPU_VCCPLL_R

TRUE

PP1V5_S3_CPU_VCCDQ

TRUE

PP1V05_S0_CPU_VCCPQE

TRUE

PPVCORE_S0_AXG

TRUE

PPVCORE_S0_CPU

TRUE

PP1V05_S0_PCH_VCCADPLL

TRUE

PP1V05_TBTLC

PP3V3_TBTLC

TRUE

PP15V_TBT

TRUE

PPVCCSA_S0_CPU

TRUE

PP1V05_SUS

TRUE

PP0V75_S0_DDRVTT

TRUE

PPVTTDDR_S3

TRUE

PP1V05_S0

PP1V5_S3RS0

TRUE

PP1V5_S3

TRUE

PP3V3_S0

TRUE

PP1V8_S0

TRUE

PP3V3_SUS

TRUE

PP3V3_S3

TRUE

PP3V3_S5

TRUE

PP5V_SUS

TRUE

PP5V_S5

PPVRTC_G3H

TRUE

PP3V42_G3H

TRUE

PPDCIN_G3H

TRUE

PPVIN_SW_TBTBST

TRUE

PPBUS_S5_HS_COMPUTING_ISNS

PPBUS_G3H

TRUE

SYS_DETECT_L

TRUE

=SMBUS_BATT_SCL

TRUE

=PP5V_S3_LIO_CONN

=PP18V5_DCIN_CONN

TRUE

SSD_P3V3S0_EN

TRUE

SSD_RESET_L

TRUE

SATA_PCIE_SEL

TRUE

SATA_SSD_R2D_P

TRUE

SSD_CLKREQ_L

PCIE_SSD_D2R_N<1>

TRUE

SATA_SSD_R2D_N

SMC_OOB1_TX_L

TRUE

PCIE_CLK100M_SSD_P

SATA_SSD_D2R_N

TRUE

SMC_OOB1_RX_L

TRUE

SATA_SSD_D2R_P

TRUE

PP3V3_S0_SSD_FLT

TRUE

KBDLED_FB

TRUE

KBDLED_ANODE

USB3_EXTB_TX_C_P

TRUE

USB3_EXTB_TX_C_N

TRUE

USB_EXTB_P

USB_EXTB_N

TRUE

SPKRAMP_INR_P

SPKRAMP_INR_N

TRUE

AUD_GPIO_3

TRUE

AUD_I2C_INT_L

TRUE

AUD_IP_PERIPHERAL_DET

TRUE

AUD_IPHS_SWITCH_EN

TRUE

=I2C_MIKEY_SDA

TRUE

=I2C_MIKEY_SCL

TRUE

=I2C_LIO_SCL

TRUE

=I2C_LIO_SDA

TRUE

SMC_LID

TRUE

=USB_PWR_EN

SMC_BC_ACOK

TRUE

SYS_ONEWIRE

TRUE

=PP3V3R1V5_S0_AUDIO

TRUE

=PP3V3_S0_AUDIO

TRUE

=PP3V42_G3H_ONEWIRE

TRUE

HDA_SDOUT

TRUE

USB_CAMERA_P

TRUE

SMC_TDO

TRUE

TP_SMC_TRST_L

SD_CMD

TRUE

LPC_PWRDWN_L

PCIE_AP_R2D_N

TRUE

WIFI_EVENT_L

TRUE

PP3V3_WLAN_F

TRUE

NC_CPU_RSVD<8..27>

MAKE_BASE=TRUE

TP_CPU_RSVD<8..27>

TRUE

=I2C_TPAD_SCL

TP_PCIE_CLK100M_PEBN

PCIE_WAKE_L

TRUE

TP_CRT_IG_DDC_CLK

TP_CRT_IG_VSYNC

TP_LVDS_IG_CTRL_CLK

TP_PCH_LVDS_VBG

TP_HDA_SDIN1

TP_HDA_SDIN2

TP_CLINK_RESET_L

TP_PCIE_CLK100M_PEBP

TP_CLINK_DATA

TP_CLINK_CLK

TP_CRT_IG_HSYNC

TP_HDA_SDIN3

TP_LVDS_IG_CTRL_DATA

TP_SDVO_TVCLKINP

TP_SDVO_TVCLKINN

TP_SDVO_STALLN

TP_SDVO_INTP

TP_SDVO_INTN

TP_SDVO_STALLP

TP_XDP_PCH_OBSFN_D<0..1>

TP_XDPPCH_HOOK3

TP_XDP_PCH_OBSFN_B<0..1>

TP_XDPPCH_HOOK2

TP_XDP_PCH_OBSFN_A<0..1>

TP_XDP_PCH_HOOK4

TP_XDP_PCH_HOOK5

TP_PCH_GPIO64_CLKOUTFLEX0

TP_PCH_GPIO67_CLKOUTFLEX3

TP_PCH_GPIO66_CLKOUTFLEX2

TP_PCH_GPIO65_CLKOUTFLEX1

SMC_BS_ALRT_L

TP_LVDS_IG_BKL_PWM

TP_LVDS_IG_B_CLKP

TP_LVDS_IG_B_CLKN

TP_PCH_TP1

TP_PCH_TP2

TP_PCH_TP3

TP_PCH_TP4

TP_PCH_TP5

TP_PCH_TP6

TP_PCH_TP7

TP_PCH_TP8

TP_PCH_TP9

TP_PCH_TP10

TP_PCH_TP12

TP_PCH_TP13

TP_PCH_TP14

TP_PCH_TP15

TP_PCH_TP16

TP_PCH_TP18

TP_PCH_TP17

TP_SATA_E_D2RP

TP_SATA_E_D2RN

TP_SATA_F_R2D_CP

TP_SATA_D_D2RP

TP_SATA_D_D2RN

TP_SATA_D_R2D_CN

TP_SATA_D_R2D_CP

TP_SATA_B_R2D_CP

TP_SATA_B_D2RP

TP_SATA_B_D2RN

TP_PSOC_P1_3

TP_PCIE_CLK100M_PE7P

TP_SATA_B_R2D_CN

TP_PCIE_CLK100M_PE7N

TP_PCIE_CLK100M_PE5P

TP_PCIE_CLK100M_PE6P

TP_PCIE_CLK100M_PE6N

TP_CPU_THERMDC

TP_EDP_AUX_N

TP_EDP_TX_N<0..3>

TP_EDP_AUX_P

TP_EDP_TX_P<0..3>

TRUE

LPCPLUS_GPIO

TRUE

SMC_RX_L

TRUE

SMC_RESET_L

SMC_TDI

TRUE

SPI_ALT_CS_L

TRUE

SPI_ALT_CLK

TRUE

SPIROM_USE_MLB

TRUE

LPC_CLK33M_LPCPLUS

TRUE

SMC_TX_L

TRUE

LPCPLUS_RESET_L

TRUE

PM_CLKRUN_L

TRUE

SMC_TMS

TRUE

SPI_ALT_MISO

TRUE

LPC_FRAME_L

PP3V3_S3RS4_BT_F

TRUE

USB_BT_CONN_N

NC_PCIE_CLK100M_PE6N

MAKE_BASE=TRUE

TRUE

TRUE MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE6P

NC_SATA_B_R2D_CN

TRUE

MAKE_BASE=TRUE

NC_PSOC_P1_3

TRUE

MAKE_BASE=TRUE

TRUE

NC_SATA_B_D2RN

TRUE

MAKE_BASE=TRUE

NC_SATA_D_R2D_CP

TRUE

MAKE_BASE=TRUE

NC_SATA_F_R2D_CP

NC_SATA_F_R2D_CN

TRUE

MAKE_BASE=TRUE

NC_SATA_F_D2RN

MAKE_BASE=TRUE

TRUE

NC_SATA_E_R2D_CP

TRUE

MAKE_BASE=TRUE

NC_SATA_F_D2RP

TRUE

MAKE_BASE=TRUE

NC_SATA_E_D2RN

MAKE_BASE=TRUE

TRUE

NC_SATA_E_R2D_CN

TRUE

MAKE_BASE=TRUE

NC_SATA_E_D2RP

TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_PCH_TP17

TRUE

MAKE_BASE=TRUE

NC_PCH_TP18

TRUE

MAKE_BASE=TRUE

NC_PCH_TP16

TRUE

MAKE_BASE=TRUE

NC_PCH_TP15

TRUE

MAKE_BASE=TRUE

TRUE

NC_PCH_TP14

MAKE_BASE=TRUE

NC_PCH_TP13

TRUE

MAKE_BASE=TRUE

NC_PCH_TP12

TRUE

MAKE_BASE=TRUE

NC_PCH_TP10

TRUE

NC_PCH_TP9

TRUE

MAKE_BASE=TRUE

NC_PCH_TP8

TRUE

MAKE_BASE=TRUE

NC_PCH_TP7

MAKE_BASE=TRUE

TRUE

NC_PCH_TP6

MAKE_BASE=TRUE

TRUE

NC_PCH_TP5

TRUE

PCH_VSS_NCTF<15>

MAKE_BASE=TRUE

TRUE

NC_PCH_TP4

NC_PCH_TP3

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_PCH_TP2

NC_PCH_TP1

MAKE_BASE=TRUE

TRUE

PCH_VSS_NCTF<17>

TRUE

PCH_VSS_NCTF<19>

TRUE

PCH_VSS_NCTF<19>

TRUE

PCH_VSS_NCTF<25>

TRUE

PCH_VSS_NCTF<21>

TRUE

PCH_VSS_NCTF<27>

TRUE

PCH_VSS_NCTF<29>

TRUE

MAKE_BASE=TRUE

NC_LVDS_IG_B_CLKN

MAKE_BASE=TRUE

TRUE

NC_LVDS_IG_B_CLKP

MAKE_BASE=TRUE

TRUE

NC_LVDS_IG_BKL_PWM

MAKE_BASE=TRUE

TRUE

NC_SMC_BS_ALRT_L

PCH_VSS_NCTF<1>

TRUE

PCH_VSS_NCTF<5>

TRUE

PCH_VSS_NCTF<2>

TRUE

PCH_VSS_NCTF<9>

TRUE

PCH_VSS_NCTF<11>

TRUE

PCH_VSS_NCTF<12>

TRUE MAKE_BASE=TRUE

NC_PCH_GPIO67_CLKOUTFLEX3

TRUE MAKE_BASE=TRUE

NC_PCH_GPIO66_CLKOUTFLEX2

MAKE_BASE=TRUE

TRUE

NC_PCH_GPIO65_CLKOUTFLEX1

MAKE_BASE=TRUE

TRUE

NC_PCH_GPIO64_CLKOUTFLEX0

NC_TP_XDP_PCH_HOOK5

MAKE_BASE=TRUE

TRUE

NC_TP_XDP_PCH_HOOK4

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

NC_TP_XDP_PCH_OBSFN_A<0..1>

MAKE_BASE=TRUE

TRUE

NC_TP_XDPPCH_HOOK2

MAKE_BASE=TRUE

TRUE

NC_TP_XDP_PCH_OBSFN_B<0..1>

TRUE MAKE_BASE=TRUE

NC_TP_XDPPCH_HOOK3

TRUE MAKE_BASE=TRUE

NC_TP_XDP_PCH_OBSFN_D<0..1>

MAKE_BASE=TRUE

TRUE

NC_SDVO_STALLP

TRUE MAKE_BASE=TRUE

NC_SDVO_STALLN

MAKE_BASE=TRUE

TRUE

NC_SDVO_INTP

MAKE_BASE=TRUE

TRUE

NC_SDVO_TVCLKINP

TRUE MAKE_BASE=TRUE

NC_SDVO_TVCLKINN

TRUE MAKE_BASE=TRUE

NC_SDVO_INTN

XDP_AP_CLKREQ_L

TRUE

XDP_PCH_AUD_IPHS_SWITCH_EN

TRUE

XDP_FW_CLKREQ_L

TRUE

XDP_PCH_PWRBTN_L

TRUE

XDP_PCH_ISOLATE_CPU_MEM_L

TRUE

XDP_PCH_S5_PWRGD

TRUE

XDP_PCH_ENET_PWR_EN

TRUE

TRUE MAKE_BASE=TRUE

NC_CRT_IG_VSYNC

MAKE_BASE=TRUE

TRUE

NC_LVDS_IG_CTRL_CLK

MAKE_BASE=TRUE

TRUE

NC_HDA_SDIN1

TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE

TRUE

NC_HDA_SDIN3

TRUE MAKE_BASE=TRUE

NC_HDA_SDIN2

NC_CLINK_RESET_L

TRUE

MAKE_BASE=TRUE

TRUE

NC_CLINK_CLK

NC_CLINK_DATA

MAKE_BASE=TRUE

TRUE

TRUE MAKE_BASE=TRUE

NC_PCIE_CLK100M_PEBN

TRUE

MAKE_BASE=TRUE

NC_PCI_CLK33M_OUT3

TRUE

NC_CPU_RSVD<30..45>

NC_PCIE_CLK100M_PE5N

TRUE MAKE_BASE=TRUE

LPC_AD<3..0>

TRUE

=PP5V_S0_LPCPLUS

TRUE

SD_CD_L

TRUE

SD_WP

PP5V_TPAD_FILT

TRUE

USB_TPAD_CONN_P

TRUE

=I2C_TPAD_SDA

TRUE

SMC_TPAD_RST_L

TRUE

SMC_LID

SMC_PME_S4_WAKE_L

TRUE

PP3V3_TPAD_CONN

FAN_RT_TACH

TRUE

=PP5V_S0_FAN

TRUE

FAN_RT_PWM

SPI_ALT_MOSI

TRUE

=PP3V42_G3H_TPAD

TRUE

=PP3V3_S5_LPCPLUS

TRUE

NC_EDP_AUXP

TRUE

MAKE_BASE=TRUE

TP_PCIE_CLK100M_PE4N

TP_PCIE_CLK100M_PE4P

TP_PCIE_CLK100M_PE5N

TRUE

MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE

NC_PCI_PME_L

TRUE

NC_CPU_THERMDC

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE4P

TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE

TRUE

NC_PCIE_CLK100M_PE5P

MAKE_BASE=TRUE

TRUE

NC_SATA_B_D2RP

TRUE

MAKE_BASE=TRUE

NC_SATA_B_R2D_CP

MAKE_BASE=TRUE

TRUE

NC_SATA_D_D2RN

NC_SATA_D_D2RP

MAKE_BASE=TRUE

TRUE

NC_SATA_D_R2D_CN

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TP_CPU_THERMDA

TP_CPU_RSVD<30..45>

=PEG_D2R_N<15..2>

=PEG_D2R_P<15..2>

=PEG_R2D_C_N<15..2>

=PEG_R2D_C_P<15..2>

TRUE

NC_PEG_D2RP<15..2>

TRUE

MAKE_BASE=TRUE

NC_PEG_R2D_CP<15..2>

TRUE

MAKE_BASE=TRUE

TRUE

NC_PEG_D2RN<15..2>

MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE

NC_PCIE_CLK100M_PEBP

TP_CRT_IG_DDC_DATA

TRUE

LPC_SERIRQ

TRUE

SMC_TCK

TRUE

SMC_ROMBOOT

TRUE

XDP_PCH_SDCONN_DET_L

TRUE

USB_TPAD_CONN_N

TP_SATA_E_R2D_CN

TP_SATA_E_R2D_CP

TP_SATA_F_D2RN

TP_SATA_F_D2RP

TP_SATA_F_R2D_CN

NC_PCH_LVDS_VBG

MAKE_BASE=TRUE

TRUE

NC_LVDS_IG_CTRL_DATA

MAKE_BASE=TRUE

TRUE

TP_CRT_IG_GREEN

TP_CRT_IG_BLUE

TP_CRT_IG_RED

NC_CRT_IG_GREEN

MAKE_BASE=TRUE

TRUE

TRUE MAKE_BASE=TRUE

NC_CRT_IG_BLUE

NC_CRT_IG_DDC_DATA

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

TRUE MAKE_BASE=TRUE

NC_CRT_IG_RED

TRUE

XDP_PCH_SDCONN_STATE_RST_L

TRUE

XDP_PCH_USB_HUB_SOFT_RST_L

TRUE

VCCSAS0_SET1_R

VCCSAS0_SREF

TRUE

VCCSAS0_SET1

TRUE

XDP_PCH_AP_PWR_EN

TRUE

TP_SMC_MD1

SD_D<7..0>

TRUE

SD_CLK

TRUE

SPKRAMP_ROUT_P

TRUE

NC_CPU_THERMDA

MAKE_BASE=TRUE

PCIE_SSD_D2R_P<1>

TRUE

PCIE_CLK100M_SSD_N

TRUE

PCIE_SSD_R2D_N<1>

TRUE

PCIE_SSD_R2D_P<1>

TRUE

DP_INT_ML_F_N<0>

DP_INT_HPD_CONN

LED_RETURN_4

SMC_ONOFF_L

VCCSAS0_SET0

NC_EDP_AUXN

NC_EDP_TXN<0..3>

NC_EDP_TXP<0..3>

MAKE_BASE=TRUE

NC_PEG_R2D_CN<15..2>

NC_CRT_IG_HSYNC

NC_CRT_IG_DDC_CLK

HDA_SDIN0

HDA_BIT_CLK

USB_CAMERA_N

USB3_EXTB_RX_RC_P

USB3_EXTB_RX_RC_N

HDA_RST_L HDA_SYNC

PP3V3_SW_SD_PWR

USB_EXTB_OC_L

I499

I500

I501

I502

I503

I504

I505

I506

I566

I567

I568

I569

I570

I571

I592

I593

I594

I595

I596

I597

I598

I599

I600

I601

I602

I623

I624

I626

I627

I628

I629

I630

I631

I632

I633

I634

I635

I636

I637

I638

I639

I640

I641

I642

I643

I644

I645

I646

I647

I648

I649

I650

I651

I652

I653

I654

I655

I656

I657

I658

I659

I667

I668

I669

I670

I671

I672

I673

I674

I675

I676

I677

I678

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I686

I687

I688

I689

I690

051-9277

2.8.0

7 OF 109

6 OF 73

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44 52

37 68

7

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63

7

36

7

67

7

67

7

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7

72

7

36

7

52

44 52

7

52

7

52

38

25 38

38

38 68

16 38

8

38 66

38 68

38 41 42

16 38 66

38 68

38 41

38 68

38

49

40 68

40

40 68

24 68

24 40 68

40 51 72

40 51

18

18 40

25 40

40

40 44

40

40 44

6

40 42 49

39 40 62

40 41

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40

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40

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43

33

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37 42

44 49

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17 37

17

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16

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23

16

8

16

9

19 43

41 42 43

41 42 43 53

41 42 43

43

19 43 50

25 43 69

41 42 43

25 43 69

17 41 43

41 42 43

43

16 41 43 69

37

37 68

6

23

16 41 43 69

7

43

33

49

68

44 49

41 42 49

42 49

6

40 41 42 49

41 42 49

49

48

7

48

43

7

49

7

16

9

17

16 41 43

41 42 43

42 43

33

68

16

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43

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33

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

1.8V/1.5V/1.2V/1.05V Rails

"G3Hot" (Always-Present) Rails

3.3V Rails

TBT Rails (off when no cable)

Chipset "VCore" Rails

1V05 S0 LDO

? mA

2A max supply

5V Rails

=PP3V3_S4_TPAD

=PP3V3_S4_BT

=PP3V3_SUS_PCH_VCCSUS =PP3V3_SUS_GPIO

=PP3V3_S4_SMC

=PP3V3_S4_SD_HPD

=PP3V3_S5_PCH_GPIO

=PP3V3_S4_P3V3S4FET

=PP3V3_S5_PWRCTL =PP3V3_S4_TBTAPWRSW

=PP3V3_S5_SYSCLK =PP3V3_S5_VMON

=PP3V3_S5_SMCBATLOW

=PP3V3_S5_PCHPWRGD

=PP3V3_S5_PCH_VCCDSW

PP3V3_S5

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

VOLTAGE=3.3V MAKE_BASE=TRUE

=PP3V3_S5_PCH

VOLTAGE=3.3V MAKE_BASE=TRUE

PP3V3_S4

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

=PPBUS_S0_VSENSE

=PPVIN_S5_HS_COMPUTING_ISNS_R

PPBUS_S5_HS_OTHER_ISNS

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=8.4V

=PP3V3_SUS_SMC =PP3V3_SUS_PCH_VCC_SPI =PP3V3_SUS_PCH_GPIO

VOLTAGE=3.3V MAKE_BASE=TRUE

PP3V3_SW_TBTAPWR

MIN_LINE_WIDTH=0.38 MM

=PP3V3_S3_BT =PP3V3_S3_CARDREADER =PP3V3_S3_MEMRESET

PP3V3_SUS

MIN_LINE_WIDTH=0.50MM

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.20MM

=PP3V3_SUS_PCH_VCCSUS_USB

=PP3V3_SUS_PCH

VOLTAGE=8.4V

MIN_LINE_WIDTH=0.6 mm

PPBUS_S5_HS_COMPUTING_ISNS

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 mm

=PP3V3_S3_FET

=PP3V3_S4_TBT

=PP3V3_SUS_ROM

=PPVIN_S0_CPUAXG

=PPVCCSA_S0_CPU

=PP3V3_S5_XDP

=PPVIN_S0_CPUIMVP

=PP3V3_SUS_FET

=PPVIN_S0_VCCSAS0

=PPVIN_S0_CPUVCCIOS0

=PP3V3_SUS_PWRCTL

=PPVTT_S0_DDR_LDO

=PPVTT_S3_DDR_BUF

=PP3V3_S3_BMON_ISNS =PP3V3_S3_PCH_GPIO

=PP3V3_S3_WLAN

=PPBUS_S0_LCDBKLT

=PP1V5_S0_REG

=PPVCCSA_S0_REG

=PPVIN_S5_P5VP3V3

=PPVIN_S5_HS_COMPUTING_ISNS

=PPVCORE_S0_CPU_REG

=PP1V5_S3_MEM_B

=PPVIN_S0_DDRREG_LDO

=PP1V5_S3_P1V5S3RS0_FET

=PPDDR_S3_MEMVREF

=PP1V5_S3_MEM_A

=PP1V5_S3_MEMRESET

=PP3V3R1V5_S0_AUDIO

VOLTAGE=12.8V

PPVIN_SW_TBTBST

=PPBUS_G3H

=PPVIN_S5_HS_OTHER_ISNS_R

=PP1V5_S3RS0_FET

=PP1V8R1V5_S0_PCH_VCCVRM

=PP3V3R1V5_S0_PCH_VCCSUSHDA

=PP1V8_S0_P1V05S0LDO

=PP1V8_S0_PCH_VCC_DFTERM

=PP1V8_S0_CPU_VCCPLL

=PP1V8_S0_REG

=PP1V5_S3_CPU_VCCDDR

=PP3V3_S0_P3V3S0FET

=PPHV_SW_DPAPWRSW =PPHV_SW_TBTAPWRSW

VOLTAGE=17.8V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

MAKE_BASE=TRUE

PP15V_TBT

=PPVDDIO_S0_SBCLK

MIN_LINE_WIDTH=2 mm

VOLTAGE=1.5V

MIN_NECK_WIDTH=0.17 mm

PP1V5_S0

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

PP1V5_S3RS0

VOLTAGE=1.5V

=PP1V8_S0_P1V5S0

MIN_NECK_WIDTH=0.1 MM

MIN_LINE_WIDTH=0.8 MM

VOLTAGE=1.5V MAKE_BASE=TRUE

PP1V5_S3

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

MAKE_BASE=TRUE

VOLTAGE=1.8V

PP1V8_S0

=PPDDR_S3_REG

=PP15V_TBT_REG

=PP3V3_TBT_PCH_GPIO

=PP3V3_TBTLC_RTR

=PPVDDIO_TBT_CLK

=PP3V3_TBTLC_FET

PP3V3_TBTLC

MIN_LINE_WIDTH=0.4 MM

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

PP1V05_S0_PCH_VCCADPLL

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

VOLTAGE=1.25V

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM

PPVCORE_S0_CPU

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

PPVCORE_S0_AXG

MAKE_BASE=TRUE

=PP1V05_S0_PCH_VCCADPLL

=PP1V05_S0_LDO

=PPVCORE_S0_CPU =PPCPUVCORE_S0_VSENSE

=PPVCORE_S0_AXG_REG

=PPVCORE_S0_CPU_VCCAXG =PPGFXVCORE_S0_VSENSE

MIN_LINE_WIDTH=0.6 MM

PP1V5_S3_CPU_VCCDQ

MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V MAKE_BASE=TRUE

=PP1V5_S3_CPU_VCCDQ

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

PP1V05_S0_CPU_VCCPQE

MIN_NECK_WIDTH=0.2 MM

=PP1V05_S0_CPU_VCCPQE

=PP1V8_S0_CPU_VCCPLL_R

=PP1V05_TBTLC_FET

=PP1V05_TBTLC_RTR

PP1V05_TBTLC

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

=PP1V05_TBTCIO_RTR

PP1V05_TBTCIO

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=1.05V

=PP1V05_TBTCIO_FET

=PP1V5_S3RS0_VMON

MAKE_BASE=TRUE

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V05_SUS

=PP1V05_SUS_PCH_JTAG

=PP1V05_SUS_LDO

=PPCPUVCCIO_S0_REG

=PP1V05_S0_PCH =PP1V05_S0_PCH_VCCIO =PP1V05_S0_PCH_VCCIO_PCIE

=PP1V05_S0_PCH_VCCASW

=PP1V05_S0_PCH_VCC_CORE =PP1V05_S0_VMON =PPVCCIO_S0_CPUIMVP =PP1V05_S0_PCH_VCCDIFFCLK

=PPVCCIO_S0_XDP =PPVCCIO_S0_SMC =PP1V05_S0_P1V05TBTFET

MIN_LINE_WIDTH=2 mm

VOLTAGE=0.75V

PP0V75_S0_DDRVTT

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.17 mm

=PP0V75_S0_MEM_VTT_A =PP0V75_S0_MEM_VTT_B

=PPVTT_S0_VTTCLAMP

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

VOLTAGE=0.75V

PPVTTDDR_S3

=PPVCCSA_S0_VSENSE

PPVCCSA_S0_CPU

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

VOLTAGE=0.9V

=PP1V05_S0_PCH_VCCIO_SATA

MIN_LINE_WIDTH=0.6 MM

VOLTAGE=1.8V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

PP1V8_S0_CPU_VCCPLL_R

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

=PP3V3_S3_VREFMRGN

=PP3V3_S3_WLANISNS

=PPVIN_S3_DDRREG

=PPVIN_S5_HS_OTHER_ISNS

PP5V_S5

VOLTAGE=5V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

VOLTAGE=5V

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM

MAKE_BASE=TRUE

PP5V_SUS

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=5V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=5V

PP5V_S0

MIN_NECK_WIDTH=0.2 MM

=PP5V_S5_LDO

=PP5V_S5_P5VSUSFET =PP5V_S5_TPAD

=PP5V_SUS_FET

=PP5V_SUS_PCH

=PP5V_S3_REG

=PP5V_S3_AUDIO_AMP

=PP5V_S3_MEMRESET

=PP5V_S3_DDRREG

=PP5V_S3_P5VS0FET =PP5V_S3_RTUSB =PP5V_S3_LIO_CONN

=PP5V_S0_FET

=PP5V_S0_BKL =PP5V_S0_CPUIMVP =PP5V_S0_CPUVCCIOS0 =PP5V_S0_FAN

=PP5V_S0_LPCPLUS

=PP5V_S0_VCCSA

=PP5V_S0_PCH

=PP5V_S0_VMON

=PP5V_S0_KBDLED

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6MM

PP3V42_G3H

MIN_NECK_WIDTH=0.2MM

VOLTAGE=3.42V

VOLTAGE=3V

PPVRTC_G3H

MIN_LINE_WIDTH=0.2 MM

MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

=PP3V42_G3H_REG

=PP3V3_S5_LPCPLUS

=PP3V42_G3H_CHGR

=PP3V3_S5_SMC

=PP3V42_G3H_PWRCTL =PP3V42_G3H_SMBUS_SMC_BSA =PP3V42_G3H_SMCUSBMUX

=PPVBAT_G3H_SYSCLK =PP3V42_G3H_ONEWIRE

=PPVRTC_G3_PCH

=PPVRTC_G3_OUT

=PP18V5_DCIN_ISOL

=PPDCIN_S5_VSENSE

=PPDCIN_S5_CHGR_ISOL

MAKE_BASE=TRUE

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.6 MM

PPDCIN_G3H_ISOL

PPDCIN_G3H

MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.25 MM

VOLTAGE=18.5V

MAKE_BASE=TRUE

=PP18V5_DCIN_CONN

=PPDCIN_S5_CHGR

=PP3V42_G3H_TPAD =PPVIN_S5_SMCVREF

=PP5V_S5_P1V5DDRFET

=PP3V3_SUS_P1V05SUSLDO

=PP3V3_S5_REG

=PPVIN_SW_TBTBST

PPBUS_G3H

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

VOLTAGE=8.4V

=PP3V3_S5_CPU_VCCDDR

=PP3V3_S3_P3V3S3FET

=PP1V05_S0_CPU_VCCIO

=PP3V3_S3_DBGLEDS

=PP3V3_S3_USB_RESET

=PP3V3_S4_TBTAPWR

=PP3V3_S3_USBMUX =PP3V3_S3_LCD

MIN_LINE_WIDTH=0.50MM

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.20MM

PP3V3_S3

SYNC_DATE=07/29/2011

Power Aliases

SYNC_MASTER=K21_MLB

PP5V_S3

=PP3V3_S3_1V5S3ISNS

=PP3V3_S3_SMBUS_SMC_MGMT

MIN_NECK_WIDTH=0.20 MM

=PP3V3_S4_FET

=PP3V3_S5_P3V3SUSFET

=PP1V05_S0_PCH_VCCSSC =PP1V05_S0_PCH_V_PROC_IO =PP1V05_S0_PCH_VCC_DMI

MIN_NECK_WIDTH=0.2 MM

PP1V05_S0

=PP3V3_S3_USB_HUB

=PP3V3_S3_SMBUS_SMC_A_S3

PP3V3_S0

MIN_LINE_WIDTH=0.5 MM

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.20MM

=PP3V3_S0_CPUVCCIOISNS =PP3V3_S0_AUDIO =PP3V3_S0_BKL_VDDIO =PP3V3_S0_HS_COMPUTING_ISNS =PP3V3_S0_CPUTHMSNS =PP3V3_S0_DP_DDC =PP3V3_S0_FAN =PP3V3_S0_P3V3TBTFET

=PP3V3_S0_FET

=PP3V3_S0_PCH

=PP3V3_S0_P1V8S0

=PP3V3_S0_PCH_GPIO =PP3V3_S0_HS_OTHER_ISNS =PP3V3_S0_PCH_VCC3_3 =PP3V3_S0_PCH_VCCADAC =PP3V3_S0_PWRCTL =PP3V3_S0_RSTBUF =PP3V3_S0_SB_PM =PP3V3_S0_SMBUS_PCH =PP3V3_S0_SMBUS_SMC_0_S0 =PP3V3_S0_SMBUS_SMC_B_S0 =PP3V3_S0_SMC

=PP3V3_S0_SSD =PP3V3_S0_HDDISNS =PP3V3_S0_VMON

=PP3V3_S0_P1V5S0 =PP3V3_S0_TBTPWRCTL =PP3V3_S0_P1V05S0LDO =PP3V3_S0_IMVPISNS =PP3V3_S0_XDP =PP3V3_S0_BKLTISNS =PP3V3_S0_SYSCLKGEN

=PP3V3_S0_SAISNS

=PP3V3_S0_SATAMUX

=PP3V3_S0_3V3S0ISNS =PP3V3_S0_CPU_VCCIO_SEL =PP3V3_S0_PCH_VCC3_3_CLK =PP3V3_S0_PCH_STRAPS

051-9277

2.8.0

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IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

860-1327

USB/SD Card Pogo

870-1938

DisplayPort Pogo

870-1938

CPU Heat Sink Mounting Bosses

Fan Boss

Digital Ground

SMC Aliases

Unused PGOOD signal

4x 860-1327

Unused SMC Signals

Unused PPT

TBT DP Ports

CPU signals

Plated Board Slot

860-1327

Unused SATA ODD Signals

X21 Boss

SSD PCIE Signals

860-1327

SSD Boss

Unused USB

LVDS Aliases

SATA Aliases

EMI I/O Pogo Pins

Can Slots

2x TBT chip

2x USB Connector

2x MDP Connector

2x TBT pin diodes

61

56

16

46 72

STDOFF-4.5OD1.8H-SM

TH-NSP

SL-2.3X3.9-2.9X4.5

STDOFF-4.5OD1.8H-SM

STDOFF-4.5OD1.9H-SMSTDOFF-4.5OD1.9H-SMSTDOFF-4.5OD1.8H-SM

SM

POGO-2.0OD-3.6H-K86-K87

CRITICAL

2.2K

1/20W

5%

201

MF

5%

201

2.2K

1/20W

MF

1/20W

201

5%

MF

2.2K

NO STUFF

2.2K

201

1/20W

5%

MF

NO STUFF

100K

MF

201

5%

1/20W

CRITICAL

0.01

MF

0612-1

0.5%

1W

TH-NSP

SL-1.1X0.4-1.4X0.7

TH-NSP

SL-1.1X0.4-1.4X0.7

TH-NSP

SL-1.1X0.45-1.4X0.75

41

18

34 70

16

16 69

16

9

6

38 66

6

38 66

9

0.002

1%

MF1W

CRITICAL

0612

7 7

46 72

201

10K

5% 1/20W MF

RAMCFG0:LRAMCFG1:L

10K

201

MF

1/20W

5%

201

RAMCFG2:L

10K

5% 1/20W MF

10K

5%

MF

201

1/20W

RAMCFG3:L

201

5% 1/20W MF

10K 10K

MF

5%

201

1/20W

5%

10K

201

MF

1/20W

10K

201

MF

1/20W

5%

34 70

5%

MF 201

10K

1/20W

16

34

SL-1.1X0.45-1.4X0.75

TH-NSP

SL-1.1X0.4-1.4X0.7

TH-NSP

SL-1.1X0.4-1.4X0.7

TH-NSP

470K

1%

MF

201

1/20W

470K

1%

1/20W

201

MF

TH-NSP

SL-1.1X0.4-1.4X0.7

CRITICAL

GND

MIN_NECK_WIDTH=0.075MM

VOLTAGE=0V

MIN_LINE_WIDTH=0.6MM

DPLL_REF_CLKN

MAKE_BASE=TRUE

DPLL_REF_CLK_P

MEM_B_CLK_P<1>

MAKE_BASE=TRUE

TP_MEM_B_CLKN<1>

DPA_IG_DDC_CLK

LVDS_IG_PANEL_PWR

LVDS_IG_A_DATA_P<3>

LVDS_IG_B_DATA_N<0..3>

NC_USB3_EXTC_TX_P

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB3_EXTC_RX_P

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_8_D2RN

NC_PCIE_6_D2RN

NC_PCIE_5_D2RN

NC_PCIE_8_D2RP

NC_PCIE_7_D2RP

=PP3V3_S0_DP_DDC

DPB_IG_DDC_CLK

MAKE_BASE=TRUE

DP_IG_D_CTRL_CLK

MAKE_BASE=TRUE

TP_DP_IG_D_CTRL_DATA

MAKE_BASE=TRUE

XDP_DC3_PCH_GPIO19_SATARDRVR_EN

DPLL_REF_CLKP

MLB_RAMCFG0

MLB_RAMCFG1

DPA_IG_DDC_DATA

TP_DP_IG_C_CTRL_DATA TP_DP_IG_D_CTRL_CLK

TP_MEM_A_CLKP<1>

MAKE_BASE=TRUE

TP_MEM_A_CLKN<1>

MAKE_BASE=TRUE

NC_PCIE_EXCARD_R2D_C_P

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_EXCARD_D2R_P

USB_EXTD_EHCI_N

USB3_EXTD_TX_N

USB3_EXTD_RX_N

MAKE_BASE=TRUE

TP_P1V5S3RS0_RAMP_DONE

NO_TEST=TRUE

NC_USB_EXTC_P

MAKE_BASE=TRUE

PCIE_FW_R2D_C_N

PCIE_FW_D2R_P

MEMVTT_EN

MAKE_BASE=TRUE

USB_EXTC_N

IR_RX_OUT_RC

=PEG_D2R_P<1..0>

=PEG_R2D_C_P<1..0>

=PEG_D2R_N<1..0>

SATA_ODD_D2R_N

SATA_ODD_R2D_C_N

TBT_B_CONFIG1_BUF

TBT_B_D2R_N<1>

LVDS_IG_B_DATA_P<0..3>

LVDS_IG_A_DATA_N<3>

LVDS_IG_BKL_PWM

NC_USB_EXTD_EHCI_P

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_7_D2RN

DPA_IG_HPD

TBT_B_LSTX

NC_TBT_B_LSTX

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_TBT_B_D2R_N<1>

MAKE_BASE=TRUE

DP_TBTPB_HPD

TBT_B_CONFIG2_RC

TBT_B_LSRX

MAKE_BASE=TRUE

TP_LVDS_IG_B_CLKN

NC_PCIE_CLK100M_EXCARD_N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_CLK100M_EXCARD_P

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PEG_CLK100M_N

NO_TEST=TRUE

MAKE_BASE=TRUE

PCIE_EXCARD_R2D_C_N

PCIE_EXCARD_R2D_C_P

PCIE_EXCARD_D2R_P

PCIE_ENET_R2D_C_P

PCIE_ENET_R2D_C_N

PCIE_ENET_D2R_N

PCIE_ENET_D2R_P

PEG_CLK100M_P

PCIE_CLK100M_EXCARD_P

PEG_CLK100M_N

PCIE_CLK100M_EXCARD_N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_EXCARD_R2D_C_N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_EXCARD_D2R_N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_FW_R2D_C_P

MAKE_BASE=TRUE

NC_PCIE_FW_D2R_P

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_FW_R2D_C_N

MAKE_BASE=TRUE

NC_PCIE_FW_D2R_N

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCIE_ENET_R2D_C_P

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCIE_ENET_R2D_C_N

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCIE_ENET_D2R_P

PCIE_CLK100M_FW_P

NC_PCIE_CLK100M_FW_N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_CLK100M_FW_P

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_CLK100M_ENET_P

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCIE_CLK100M_ENET_N

PCIE_CLK100M_ENET_P

PCIE_CLK100M_ENET_N

MEM_A_CLK_P<1> MEM_A_CLK_N<1>

=PEG_R2D_C_N<1..0>

DP_TBTSNK1_ML_C_N<3..0>

MAKE_BASE=TRUE

PCIE_TBT_D2R_P<1>

LCD_BKLT_EN

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_TBT_B_R2D_C_P<1>

TBT_B_D2R_P<0>

TBT_B_D2R_N<0>

DPB_IG_HPD

TBT_B_R2D_C_N<1>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_TBT_B_R2D_C_P<0>

MAKE_BASE=TRUE

NC_TBT_B_R2D_C_N<0>

NO_TEST=TRUE

TBT_B_R2D_C_P<1>

MAKE_BASE=TRUE

NC_DP_TBTPB_AUXCH_C_P

DP_TBTPB_AUXCH_C_N

NC_DP_TBTPB_AUXCH_C_N

MAKE_BASE=TRUE

NC_DP_TBTPB_ML_C_P<3>

MAKE_BASE=TRUE

DP_TBTPB_ML_C_P<1>

NC_DP_TBTPB_ML_C_P<1>

MAKE_BASE=TRUE

DP_TBTPB_ML_C_N<1>

NC_DP_TBTPB_ML_C_N<1>

MAKE_BASE=TRUE

DP_TBTSNK0_ML_C_N<3..0>

TP_DP_IG_B_MLN<3..0>

TP_DP_IG_B_MLP<3..0>

TP_DP_IG_C_MLN<3..0>

MAKE_BASE=TRUE

DP_TBTSNK1_AUXCH_C_N

DPB_IG_AUX_CH_N

TP_DP_IG_C_MLP<3..0>

MAKE_BASE=TRUE

DP_TBTSNK1_AUXCH_C_P

DPA_IG_AUX_CH_P

DP_TBTSNK0_HPD

MAKE_BASE=TRUE

DP_TBTSNK1_HPD

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SMC_SYS_LED

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_A_DATAN<3>

MAKE_BASE=TRUE

LCD_IG_PWR_EN

MAKE_BASE=TRUE

DP_IG_D_HPD

NO_TEST=TRUE

NC_LVDS_IG_B_DATAP<0..3>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_B_DATAN<0..3>

MAKE_BASE=TRUE

TBT_B_R2D_C_P<0>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_TBT_B_D2R_P<0>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_TBT_B_D2R_N<0>

NC_TBT_B_D2R_P<1>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_TBT_B_R2D_C_N<1>

NO_TEST=TRUE

PCIE_SSD_R2D_C_N<1..0>

MAKE_BASE=TRUE

=PPVIN_S5_HS_COMPUTING_ISNS

=PPVIN_S5_HS_COMPUTING_ISNS_R

ISNS_HS_COMPUTING_N

ISNS_LCDBKLT_P

=PPBUS_SW_BKL

MAKE_BASE=TRUE

VOLTAGE=12.6V

PPBUS_SW_BKL

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.375 MM

MAKE_BASE=TRUE

PCIE_TBT_D2R_N<3>

SATA_ODD_R2D_C_P

DDRREG_PGOOD

MAKE_BASE=TRUE

PCIE_SSD_R2D_C_P<1..0>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SATA_ODD_D2RP

NC_SATA_ODD_R2DCN

NO_TEST=TRUE

MAKE_BASE=TRUE

USB_EXTD_EHCI_P

USB3_EXTD_TX_P

USB3_EXTD_RX_P

USB3_EXTC_TX_P

TP_DDRREG_PGOOD

MAKE_BASE=TRUE

NC_PCIE_6_R2D_CN

NC_PCIE_5_R2D_CN

NC_PCIE_5_D2RP

PCIE_TBT_D2R_N<2>

MAKE_BASE=TRUE

PCIE_TBT_D2R_N<0>

MAKE_BASE=TRUE

PCIE_TBT_D2R_N<1>

MAKE_BASE=TRUE

PCIE_TBT_D2R_P<2>

MAKE_BASE=TRUE

PCIE_TBT_D2R_P<3>

MAKE_BASE=TRUE

PCIE_TBT_R2D_C_N<1>

MAKE_BASE=TRUE

PCIE_TBT_R2D_C_N<0>

MAKE_BASE=TRUE

PCIE_TBT_R2D_C_P<3>

MAKE_BASE=TRUE

PCIE_TBT_R2D_C_P<0>

MAKE_BASE=TRUE

PCIE_TBT_R2D_C_P<1>

MAKE_BASE=TRUE

NC_PCIE_7_R2D_CP

NC_PCIE_5_R2D_CP

NC_PCIE_8_R2D_CN

NC_PCIE_7_R2D_CN

PCIE_TBT_R2D_C_N<3>

MAKE_BASE=TRUE

USB3_EXTC_TX_N

P1V5S3RS0_RAMP_DONE

NC_PCIE_8_R2D_CP

NC_PCIE_6_D2RP

PCIE_TBT_R2D_C_N<2>

MAKE_BASE=TRUE

NC_PCIE_6_R2D_CP

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_USB3_EXTC_TX_N

NO_TEST=TRUE

NC_USB3_EXTD_RX_P

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB3_EXTD_RX_N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB3_EXTD_TX_N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB_EXTD_EHCI_N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_IR_RX_OUT_RC

MAKE_BASE=TRUE

LVDS_IG_B_CLK_P

MEM_B_CLK_N<1>

USB3_EXTC_RX_P

TP_MEM_B_CLKP<1>

MAKE_BASE=TRUE

ENET_LOW_PWR_PCH

SATARDRVR_EN

TP_PCH_CLKOUT_DPN

SMC_SYS_LED

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SATA_ODD_D2RN

TP_DP_IG_D_HPD

NO_TEST=TRUE

NC_PEG_CLK100M_P

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCIE_ENET_D2R_N

TP_DP_IG_C_CTRL_CLK

DP_TBTSNK0_AUXCH_C_N

MAKE_BASE=TRUE

PPBUS_SW_LCDBKLT_PWR

MAKE_BASE=TRUE

DP_TBTSNK1_ML_C_P<3..0>

MAKE_BASE=TRUE

DP_TBTSNK0_ML_C_P<3..0>

MAKE_BASE=TRUE

=PP3V3_S0_DP_DDC

DP_TBTPB_ML_C_P<3>

DP_TBTPB_ML_C_N<3>

DP_TBTPB_AUXCH_C_P

DP_IG_D_CTRL_DATA

MAKE_BASE=TRUE

PCIE_FW_R2D_C_P

PCIE_EXCARD_D2R_N

PCIE_SSD_D2R_N<1..0>

MAKE_BASE=TRUE

PCIE_SSD_D2R_P<1..0>

SATA_ODD_D2R_P

TP_PCH_CLKOUT_DPP

DPLL_REF_CLK_N

MAKE_BASE=TRUE

XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH

MAKE_BASE=TRUE

DP_TBTSNK0_DDC_CLK

MAKE_BASE=TRUE

DP_TBTSNK0_DDC_DATA

NO_TEST=TRUE

NC_USB3_EXTD_TX_P

MAKE_BASE=TRUE

TP_LVDS_IG_B_CLKP

MAKE_BASE=TRUE

TBT_B_CIO_SEL

TBT_B_D2R_P<1>

ISNS_HS_COMPUTING_P

TBT_B_R2D_C_N<0>

MAKE_BASE=TRUE

NC_DP_TBTPB_ML_C_N<3>

DPB_IG_AUX_CH_P

DPA_IG_AUX_CH_N

DP_TBTSNK0_AUXCH_C_P

MAKE_BASE=TRUE

PCIE_TBT_D2R_P<0>

PCIE_TBT_R2D_C_P<2>

MAKE_BASE=TRUE

=DDRVTT_EN

MAKE_BASE=TRUE

DPB_IG_DDC_DATA

ISNS_LCDBKLT_N

MLB_RAMCFG2

LVDS_IG_B_CLK_N

LVDS_IG_BKL_ON

MAKE_BASE=TRUE

LCD_BKLT_PWM

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_A_DATAP<3>

MLB_RAMCFG3

USB3_EXTC_RX_N

NC_USB3_EXTC_RX_N

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB_EXTC_N

USB_EXTC_P

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SATA_ODD_R2DCP

PCIE_CLK100M_FW_N

PCIE_FW_D2R_N

SYNC_DATE=11/10/2011

SYNC_MASTER=J13_MLB_NON_POR

Signal Aliases

SM

POGO-2.0OD-3.6H-K86-K87

Z0910

1

Z0912

1

SL0900

1

Z0913

1

Z0911

1

Z0915

1

Z0914

1

Z0905

1

ZS0905

1

R0920

1

2

R0921

1

2

R0922

1

2

R0923

1

2

R0909

1

2

R0910

12 34

SL0901

1

SL0902

1

SL0905

1

R0954

12 34

R0953

1

2

R0952

1

2

R0951

1

2

R0950

1

2

R0917

1

2

R0918

1

2

R0919

1

2

R0914

1

2

R0916

1

2

SL0907

1

SL0903

1

SL0904

1

SL0908

1

R0925

1

2

R0924

1

2

SL0906

1

ZS0906

1

051-9277

2.8.0

9 OF 109

8 OF 73

10 66

11 67

17

16

7 8

17

16 23

10 66

19

17

26

34

17

16

17

34

6

11 67

34 69

65

17

34 70

34 69 17

17

34 69 17

17

34 69

17

34

63

65

34 69

16

34 69

16

34 69

16

34 69

16

11 67

19

16

17

34 69

65

34 69

7 8

34 70

16

19 23

64

6

34

17

34 69

26 56

17

19

17

65

19

IN

OUT

IN

OUT

IN

OUT

IN

NC

EDP_TX_3

EDP_TX_0 EDP_TX_1 EDP_TX_2

EDP_TX_2* EDP_TX_3*

EDP_TX_0* EDP_TX_1*

EDP_AUX

EDP_AUX*

EDP_COMPIO

EDP_HPD

EDP_ICOMPO

FDI1_LSYNC

DMI_TX_3*

FDI0_LSYNC

FDI0_TX_3

FDI1_TX_1

FDI1_TX_0

FDI1_TX_2 FDI1_TX_3

FDI0_FSYNC FDI1_FSYNC

FDI_INT

FDI1_TX_3*

FDI1_TX_2*

FDI0_TX_1

FDI0_TX_0

FDI0_TX_2

FDI1_TX_1*

FDI0_TX_3*

FDI1_TX_0*

FDI0_TX_2*

FDI0_TX_1*

DMI_TX_1* DMI_TX_2*

DMI_TX_0

DMI_TX_2

DMI_TX_1

DMI_TX_3

FDI0_TX_0*

DMI_RX_2*

DMI_RX_0 DMI_RX_1 DMI_RX_2 DMI_RX_3

DMI_TX_0*

DMI_RX_3*

DMI_RX_1*

DMI_RX_0*

PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO

PEG_RX_2*

PEG_RX_0* PEG_RX_1*

PEG_RX_3* PEG_RX_4* PEG_RX_5*

PEG_RX_7*

PEG_RX_6*

PEG_RX_8* PEG_RX_9*

PEG_RX_10*

PEG_RX_12*

PEG_RX_11*

PEG_RX_14*

PEG_RX_13*

PEG_RX_15*

PEG_RX_0 PEG_RX_1

PEG_RX_3

PEG_RX_2

PEG_RX_4

PEG_RX_6

PEG_RX_5

PEG_RX_7 PEG_RX_8

PEG_RX_10

PEG_RX_9

PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15

PEG_TX_1* PEG_TX_2*

PEG_TX_0*

PEG_TX_3* PEG_TX_4* PEG_TX_5*

PEG_TX_7*

PEG_TX_6*

PEG_TX_10*

PEG_TX_8* PEG_TX_9*

PEG_TX_11* PEG_TX_12* PEG_TX_13* PEG_TX_14* PEG_TX_15*

PEG_TX_1

PEG_TX_0

PEG_TX_2 PEG_TX_3 PEG_TX_4

PEG_TX_6

PEG_TX_5

PEG_TX_7 PEG_TX_8

PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12

PEG_TX_14

PEG_TX_13

PEG_TX_15

(1 OF 9)

PCI EXPRESS BASED INTERFACE SIGNALS

DMI

INTEL FLEXIBLE DISPLAY INTERFACE SIGNALS

EMBEDDED DISPLAY PORT

NC NC

RSVD_26 RSVD_27

RSVD_25

RSVD_23 RSVD_24

RSVD_22

RSVD_21

RSVD_19

RSVD_18

RSVD_16 RSVD_17

RSVD_15

RSVD_14

RSVD_13

RSVD_12

DC_TEST_BG1

DC_TEST_BD1

DC_TEST_BE1

DC_TEST_BG3 DC_TEST_BE3

DC_TEST_BG4

DC_TEST_BG58

DC_TEST_BG59

DC_TEST_BE59 DC_TEST_BG61

DC_TEST_BD61 DC_TEST_BE61

DC_TEST_D61

DC_TEST_A61 DC_TEST_C61

DC_TEST_A59 DC_TEST_C59

DC_TEST_A58

DC_TEST_D3 DC_TEST_D1

DC_TEST_C4

DC_TEST_A4

RSVD_45

RSVD_44

RSVD_41

RSVD_43

RSVD_42

RSVD_39 RSVD_40

RSVD_38

RSVD_36

RSVD_33

RSVD_31 RSVD_32

RSVD_30

CFG_3

CFG_2

CFG_1

CFG_0

CFG_9

CFG_8

CFG_7

CFG_6

CFG_14

CFG_12

CFG_10

CFG_16 CFG_17

VCC_VAL_SENSE

RSVD_8

RSVD_7

RSVD_6

CFG_15

CFG_13

CFG_11

CFG_5

CFG_4

VSS_VAL_SENSE

VAXG_VAL_SENSE

VCC_DIE_SENSE

VSSAXG_VAL_SENSE

RSVD_11

RSVD_9 RSVD_10

RSVD_20

RSVD_37

RSVD_35

RSVD_34

SB_DIMM_VREFDQ

SA_DIMM_VREFDQ

RESERVED

(5 OF 9)

NC NC NC

NC

OUT

S

D

G

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Intel Doc 467283 ChiefRiver Platform design guild rev0.71 section 2.2.12 recommendation.

NOTE: eDP_COMPIO and eDP_ICOMPO can not be left floating

Note. VOLTAGE=1.25V

Note. VOLTAGE=0V

FOR IVYBRIDGE PROCESSOR

CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED

This signal can be left as no-connect if entire eDP interface is disabled.

If HPD is disabled while eDP interface is still enabled,

(refer to latest Processor EDS for DC specifications).

Rise/Fall time <6ns

CR SFF Intel doc #460452

connect it to CPU VCCIo via a 10-kOhm pull-up resistor on the motherboard.

NOTE: Intel provides an internal pull-up OF 5-15k to VCCIO on all CFG signals.

this alnalog sense due to accuracy concern.

NOTE: Intel does not recommend to use

Note. VOLTAGE=0V

to low voltage signals for the processor

shared with other interfaces.

to convert the active high signal from Embedded DisplayPort sink device

Therefore, an inverting level shifter is required on the motherboard

NOTE: The EDP_HPD processor input is a low voltage active low signal.

even if internal Graphics is disabled since they are

Note. VOLTAGE=1.05V

NOTE: Intel validation sense lines per

doc 439028 rev1.0 HR_PPDG sections 6.2.1 and 6.3.1.

CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4

CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS

These can be Placed close to J2500 and Only for debug access

17 66

8

6

8

6

8

6

8

6

8

6

8

6

8

6

9

23 66

9

23 66

9

23 66

9

23 66

9

23 66

9

23 66

9

23 66

9

23 66

9

23

17 66

2C-35W

IVY-BRIDGE

BGA

OMIT_TABLE

CRITICAL

BGA

2C-35W

OMIT_TABLE

CRITICAL

IVY-BRIDGE

47 72

31

PLACE_NEAR=U1000.AG11:12.7MM

5%

1K

1/20W

201

MF

PLACE_NEAR=U1000.G3:12.7MM

24.9

1%

1/20W

MF

201

MF

201

1/20W

1%

24.9

PLACE_NEAR=U1000.AF3:12.7MM

2N7002TXG

SOT-523-3

EDP:YES

1K

NOSTUFF

5%

MF-LF

1/16W

402

5%

1K

NOSTUFF

MF-LF

1/16W

402

NOSTUFF

1K

5%

MF-LF

402

1/16W

5%

1K

MF-LF

1/16W

EDP:YES

402

5%

NOSTUFF

MF-LF

1/16W

1K

402

1/16W

MF-LF

5%

1K

402

NOSTUFF

1/16W

402

MF-LF

1K

5%

NOSTUFF

402

5%

1K

1/16W

MF-LF

NOSTUFF

PLACE_SIDE=BOTTOM

PLACE_NEAR=U1000.H45:50.8MM

49.9

1/16W

402

1%

MF-LF

NOSTUFF

PLACE_NEAR=U1000.H43:50.8MM PLACE_SIDE=BOTTOM

MF-LF

NOSTUFF

1%

402

1/16W

49.9

1%

PLACE_NEAR=U1000.K45:50.8MM

NOSTUFF

PLACE_SIDE=BOTTOM

MF-LF 402

1/16W

49.9

1/16W

PLACE_NEAR=U1000.K43:50.8MM

1%

NOSTUFF

MF-LF

402

49.9

PLACE_SIDE=BOTTOM

402

NOSTUFF

1/16W

MF-LF

5%

1K

SYNC_DATE=10/17/2011

CPU DMI/PEG/FDI/RSVD

SYNC_MASTER=J13_MLB_NON_POR

CPU_CFG<16>

CPU_PEG_COMP

=PEG_D2R_N<2>

=PEG_D2R_P<4>

=PEG_D2R_P<15>

TP_EDP_TX_P<2>

=PEG_R2D_C_P<6>

=PEG_R2D_C_P<9>

=PEG_R2D_C_N<10>

CPU_VCC_VALSENSE_P

CPU_CFG<4> CPU_CFG<5>

=PEG_D2R_N<9>

DP_INT_AUX_CH_P

CPU_VCC_VALSENSE_N

CPU_AXG_VALSENSE_N

CPU_CFG<0>

CPU_CFG<3>

CPU_CFG<2>

CPU_CFG<4>

CPU_CFG<5>

CPU_CFG<6>

CPU_CFG<7>

DP_INT_HPD

EDP_HPD_L

=PEG_D2R_N<14>

=PEG_D2R_P<8>

FDI_DATA_N<7>

FDI_DATA_P<5> FDI_DATA_P<6>

PPCPU_MEM_VREFDQ_A

MIN_LINE_WIDTH=0.3 MM

VOLTAGE=0.75V

MIN_NECK_WIDTH=0.2 MM

=PP1V05_S0_CPU_VCCIO

=PEG_R2D_C_P<14>

CPU_DC_TEST_C61_A61

=PEG_R2D_C_P<15>

=PP1V05_S0_CPU_VCCIO

=PEG_D2R_P<14>

=PP1V05_S0_CPU_VCCIO

=PEG_D2R_P<7>

=PEG_D2R_P<5>

CPU_CFG<6>

CPU_CFG<0>

=PEG_R2D_C_P<1>

=PEG_D2R_N<6>

=PEG_D2R_N<5>

CPU_THERMD_N

CPU_THERMD_P

=PEG_D2R_P<10> =PEG_D2R_P<11> =PEG_D2R_P<12>

CPU_DC_TEST_C59_A59

=PEG_D2R_P<13>

FDI_INT

FDI_FSYNC<0>

DMI_S2N_N<0>

=PEG_R2D_C_P<2>

CPU_CFG<17>

CPU_DC_TEST_C4_BE1_BG1

TP_CPU_DC_TEST_BD1

CPU_DC_TEST_C4_BE3_BG3

TP_CPU_DC_TEST_BG4

TP_CPU_DC_TEST_BG58

CPU_DC_TEST_BG59_BG61

CPU_DC_TEST_BE59_BE61

TP_CPU_DC_TEST_BD61

TP_CPU_DC_TEST_D61

TP_CPU_DC_TEST_D1

TP_CPU_DC_TEST_A4

CPU_CFG<3>

CPU_CFG<2>

CPU_CFG<1>

CPU_CFG<9>

CPU_CFG<8>

CPU_CFG<7>

CPU_CFG<14>

CPU_CFG<12>

CPU_CFG<10>

CPU_CFG<16>

CPU_CFG<15>

CPU_CFG<13>

CPU_CFG<11>

TP_CPU_VCC_DIE_SENSE

FDI_LSYNC<1>

=PEG_R2D_C_P<13>

=PEG_R2D_C_P<7>

=PEG_R2D_C_P<3>

=PEG_R2D_C_N<9>

=PEG_R2D_C_N<8>

=PEG_R2D_C_N<6> =PEG_R2D_C_N<7>

=PEG_R2D_C_N<5>

=PEG_R2D_C_N<4>

=PEG_R2D_C_N<3>

=PEG_R2D_C_N<0>

=PEG_R2D_C_N<2>

=PEG_R2D_C_N<1>

=PEG_D2R_P<9>

=PEG_D2R_P<6>

=PEG_D2R_P<2> =PEG_D2R_P<3>

=PEG_D2R_P<1>

=PEG_D2R_N<15>

=PEG_D2R_N<13>

=PEG_D2R_N<12>

=PEG_D2R_N<8>

=PEG_D2R_N<7>

=PEG_D2R_N<4>

=PEG_D2R_N<3>

=PEG_D2R_N<1>

=PEG_D2R_N<0>

DMI_S2N_N<1>

DMI_S2N_N<3>

DMI_N2S_N<0>

DMI_S2N_P<3>

DMI_S2N_P<2>

DMI_S2N_P<1>

DMI_S2N_P<0>

DMI_S2N_N<2>

FDI_DATA_N<0>

DMI_N2S_P<3>

DMI_N2S_P<1> DMI_N2S_P<2>

DMI_N2S_P<0>

DMI_N2S_N<2>

DMI_N2S_N<1>

FDI_DATA_N<1> FDI_DATA_N<2> FDI_DATA_N<3>

FDI_DATA_P<2>

FDI_DATA_P<0> FDI_DATA_P<1>

FDI_DATA_N<6>

FDI_FSYNC<1>

FDI_DATA_P<4>

FDI_DATA_P<3>

FDI_LSYNC<0>

FDI_DATA_N<4>

=PEG_D2R_P<0>

=PEG_D2R_N<11>

PPCPU_MEM_VREFDQ_B

VOLTAGE=0.75V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.3 MM

=PEG_R2D_C_P<10>

EDP_HPD_L

EDP_COMP

TP_EDP_TX_P<3>

TP_EDP_TX_P<1>

DP_INT_ML_P<0>

TP_EDP_TX_N<3>

TP_EDP_TX_N<2>

DP_INT_AUX_CH_N

DP_INT_ML_N<0> TP_EDP_TX_N<1>

=PEG_R2D_C_P<11>

DMI_N2S_N<3>

TP_CPU_DC_TEST_A58

CPU_DC_TEST_C4_D3

=PEG_R2D_C_P<12>

=PEG_R2D_C_P<5>

FDI_DATA_P<7>

FDI_DATA_N<5>

CPU_AXG_VALSENSE_P

=PPVCORE_S0_CPU_VCCAXG

=PPVCORE_S0_CPU

=PEG_D2R_N<10>

=PEG_R2D_C_N<11> =PEG_R2D_C_N<12> =PEG_R2D_C_N<13> =PEG_R2D_C_N<14> =PEG_R2D_C_N<15>

=PEG_R2D_C_P<0>

=PEG_R2D_C_P<4>

=PEG_R2D_C_P<8>

CPU_CFG<1>

U1000

N3

M2

P7

P6

P3

P1

P11

P10

K3

K1

M7

M8

P4

N4

T3

R2

AF4

AG4

AF3

AG11

AD2

AC1

AC3

AA4

AC4

AE10

AE11

AE6

AE7

AA11

AA10

U6

U7

W10

W11

W3

W1

AA7

AA6

AC12

AG8

W7

W6

T4

V4

AA3

Y2

AC8

AC9

U11

G3 G1 G4

K22

H22

K19

J21

F8

G8

C8

A8

C5

B6

H6

H8

F6

E5

K6

K7

C21

B22

D19

D21

C19

A19

D16

D17

C13

B14

D12

D13

C11

A11

C9

B10

F22

G22

A23

C23

K13

J14

G13

H13

K10

M10

G10

F10

D8

D9

K4

J4

D24

D23

E21

F21

G19

H19

B18

C17

K17

K15

G17

F17

E14

F14

C15

A15

U1000

B50 C51

K49 K53 F53 G53 L51 F51 D52 L53

B54 D53 A51 C53 C55 H49 A55 H51

A4

A58 A59

A61

BD1

BD61

BE1

BE3

BE59

BE61

BG1

BG3

BG4

BG58

BG59

BG61

C4

C59

C61

D1

D3

D61

AG13

AH2

AM14 AM15

AT21

AT49

AU19 AU21

AV19

AY21

AY22

BA19

BA22

BB19

BB21

BD21 BD22 BD25 BD26

BE22

BE24

BE26 BF23

BG22

BG26

H48

K24

K48

L42 L45 L47

M13 M14

N42

N50

P13

U14 W14

BE7 BG7

H45

F48

H43 K43

K45

R1031

1

2

R1010

12

R1030

12

Q1031

3

1

2

R1047

1

2

R1046

1

2

R1045

1

2

R1044

1

2

R1042

1

2

R1043

1

2

R1041

1

2

R1040

1

2

R1070

1

2

R1064

1

2

R1071

1

2

R1065

1

2

R1049

1

2

051-9277

2.8.0

10 OF 109

9 OF 73

9

23

66

6

63 66

9

23 66

9

23 66

9

23 66

9

23 66

9

23 66

9

23 66

9

23 66

63

9

7 9

10 12 14

7 9

10 12 14

7 9

10 12 14

9

66

6

63 66

6

63 66

6

7

12 15

7

12 14

9

23 66

IN

OUT

BI

IN

BI

NC

SM_RCOMP_2

SM_RCOMP_1

SM_RCOMP_0

SM_DRAMRST*

BCLK_ITP

BCLK_ITP*

DPLL_REF_CLK*

DPLL_REF_CLK

BCLK*

BCLK

RESET*

SM_DRAMPWROK

UNCOREPWRGOOD

PM_SYNC

PROC_SELECT*

PROC_DETECT*

PREQ*

TMS

TRST*

TDI TDO

DBR*

BPM_0* BPM_1* BPM_2* BPM_3* BPM_4* BPM_5* BPM_6* BPM_7*

TCK

PRDY*

THERMTRIP*

CATERR*

PROCHOT*

PECI

(2 OF 9)

CLOCKS

THERMAL

PWR MGMT

JTAG & BPM

DDR3 MISC

IN

OUT

BI

OUT

IN

OUT

IN

BI

IN

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(IPU) (IPU)

(IPU)

Intel Doc 460452 ChiefRiver SFF DG rev1.0 section 2.7.11 recommendation R1115.

16 66

23 66

23 25 66

23 66

16 66

23 66

BGA

2C-35W

IVY-BRIDGE

OMIT_TABLE

CRITICAL

201

MF

1/20W

5%

1K

NOSTUFFNOSTUFF

51

5% 1/20W MF 201

1K

5%

1/20W

MF

201

NOSTUFF

PLACE_NEAR=U1000.B46:12.7MM

5% 1/20W MF 201

10K

8

66

NOSTUFF

201

1%

4.99K

MF

1/20W

PLACE_NEAR=U1000.BG43:12.7MM

201

200

1/20W MF

1%

PLACE_NEAR=U1000.BE43:12.7MM

25.5

MF 201

1/20W

1%

19

41 66

19 42 66

19 23 66

17 66

26

16 66

PLACE_NEAR=U1000.BE45:12.7MM

130

201

MF

1/20W

1%

201

MF

1/20W

5%

62

56

5%

1/20W

MF

201

PLACE_NEAR=R1121.2:1MM

201

MF

1/20W

1%

200

41 42 57 66

PLACE_NEAR=U1000.BF44:12.7MM

201

MF

1/20W

1%

140

201

1/20W

MF

1%

43.2

201

MF

1/20W

1%

75

17 26 66

8

66

23 25

16 66

23 66

CPU CLOCK/MISC/JTAG

SYNC_MASTER=J30_MLB

SYNC_DATE=07/27/2011

XDP_CPU_PRDY_L

XDP_CPU_TCK

XDP_BPM_L<7>

XDP_BPM_L<6>

XDP_BPM_L<5>

XDP_BPM_L<4>

XDP_BPM_L<3>

XDP_BPM_L<2>

XDP_BPM_L<1>

XDP_BPM_L<0>

XDP_DBRESET_L

XDP_CPU_TDO

XDP_CPU_TDI

XDP_CPU_TRST_L

XDP_CPU_TMS

XDP_CPU_PREQ_L

DMI_CLK100M_CPU_P DMI_CLK100M_CPU_N

DPLL_REF_CLKP DPLL_REF_CLKN

ITPCPU_CLK100M_N

ITPCPU_CLK100M_P

CPU_PECI

CPU_CATERR_L

PM_THRMTRIP_L

=MEM_RESET_L

CPU_PROCHOT_R_L

CPU_PROC_SEL_L

PM_SYNC

CPU_SM_RCOMP<0>

PLT_RESET_LS1V1_L

=PP1V05_S0_CPU_VCCIO

CPU_RESET_L

=PP1V5_S3_CPU_VCCDDR

CPU_PROCHOT_L

PM_MEM_PWRGD

=PP1V05_S0_CPU_VCCIO

CPU_PWRGD

CPU_SM_RCOMP<2>

CPU_SM_RCOMP<1>

PM_MEM_PWRGD_R

U1000

J3 H2

N59 N58

G58 E55 E59 G55 G59 H60 J59 J61

C49

K58

AG3 AG1

A48

C48

N53 N55

C57

F49

C45

D44

BE45

AT30

BF44 BE43 BG43

L56

M60 L59

D45

L55 J58

B46

R1102

1

2

R1104

1

2

R1100

1

2

R1111

1

2

R1115

1

2

R1114

1

2

R1113

1

2

R1121

12

R1101

1

2

R1103

12

R1120

1

2

R1112

1

2

R1125

12

R1126

1

2

051-9277

2.8.0

11 OF 109

10 OF 73

66

7 9

10 12 14

7

12 15 26

7 9

10 12 14

66

BI

OUT

BI

OUT

BI

OUT

BI

OUT

SA_MA_14 SA_MA_15

SA_MA_12 SA_MA_13

SA_MA_11

SA_MA_9

SA_MA_10

SA_MA_8

SA_MA_7

SA_MA_6

SA_MA_5

SA_MA_4

SA_MA_3

SA_MA_2

SA_MA_1

SA_MA_0

SA_DQS_7

SA_DQS_5 SA_DQS_6

SA_DQS_3 SA_DQS_4

SA_DQS_2

SA_DQS_0 SA_DQS_1

SA_DQS_7*

SA_DQS_6*

SA_DQS_5*

SA_DQS_4*

SA_DQS_3*

SA_DQS_2*

SA_DQS_0* SA_DQS_1*

SA_ODT_1

SA_ODT_0

SA_CS_1*

SA_CS_0*

SA_CKE_1

SA_CK_1*

SA_CK_1

SA_CKE_0

SA_CK_0*

SA_CK_0

SA_WE*

SA_RAS*

SA_CAS*

SA_BS_0 SA_BS_1 SA_BS_2

SA_DQ_62 SA_DQ_63

SA_DQ_61

SA_DQ_60

SA_DQ_59

SA_DQ_58

SA_DQ_57

SA_DQ_56

SA_DQ_55

SA_DQ_54

SA_DQ_53

SA_DQ_52

SA_DQ_50 SA_DQ_51

SA_DQ_49

SA_DQ_48

SA_DQ_47

SA_DQ_46

SA_DQ_45

SA_DQ_44

SA_DQ_42 SA_DQ_43

SA_DQ_41

SA_DQ_39 SA_DQ_40

SA_DQ_38

SA_DQ_37

SA_DQ_36

SA_DQ_34 SA_DQ_35

SA_DQ_31

SA_DQ_33

SA_DQ_32

SA_DQ_29 SA_DQ_30

SA_DQ_26

SA_DQ_28

SA_DQ_27

SA_DQ_24 SA_DQ_25

SA_DQ_23

SA_DQ_22

SA_DQ_21

SA_DQ_19 SA_DQ_20

SA_DQ_18

SA_DQ_17

SA_DQ_16

SA_DQ_13 SA_DQ_14 SA_DQ_15

SA_DQ_11 SA_DQ_12

SA_DQ_9 SA_DQ_10

SA_DQ_8

SA_DQ_7

SA_DQ_6

SA_DQ_5

SA_DQ_4

SA_DQ_3

SA_DQ_2

SA_DQ_1

SA_DQ_0

(3 OF 9)

MEMORY CHANNEL A

SB_MA_15

SB_MA_14

SB_MA_12 SB_MA_13

SB_MA_11

SB_MA_10

SB_MA_9

SB_MA_7 SB_MA_8

SB_MA_6

SB_MA_5

SB_MA_4

SB_MA_3

SB_MA_2

SB_MA_1

SB_MA_0

SB_DQS_7

SB_DQS_6

SB_DQS_5

SB_DQS_4

SB_DQS_3

SB_DQS_2

SB_DQS_1

SB_DQS_0

SB_DQS_7*

SB_DQS_6*

SB_DQS_5*

SB_DQS_4*

SB_DQS_3*

SB_DQS_2*

SB_DQS_1*

SB_DQS_0*

SB_ODT_0 SB_ODT_1

SB_CS_1*

SB_CS_0*

SB_CKE_1

SB_CK_1

SB_CK_1*

SB_CK_0*

SB_CKE_0

SB_CK_0

SB_DQ_37

SB_DQ_36

SB_DQ_34 SB_DQ_35

SB_DQ_33

SB_DQ_31 SB_DQ_32

SB_DQ_30

SB_DQ_29

SB_DQ_26 SB_DQ_27 SB_DQ_28

SB_DQ_24 SB_DQ_25

SB_DQ_21 SB_DQ_22 SB_DQ_23

SB_DQ_20

SB_DQ_19

SB_DQ_18

SB_DQ_17

SB_DQ_16

SB_DQ_15

SB_DQ_14

SB_DQ_13

SB_DQ_12

SB_DQ_11

SB_DQ_10

SB_DQ_8 SB_DQ_9

SB_DQ_7

SB_DQ_6

SB_DQ_4 SB_DQ_5

SB_DQ_3

SB_DQ_2

SB_DQ_1

SB_DQ_0

SB_DQ_39

SB_DQ_38

SB_DQ_40 SB_DQ_41 SB_DQ_42

SB_DQ_44

SB_DQ_43

SB_DQ_46

SB_DQ_45

SB_DQ_47

SB_DQ_49

SB_DQ_48

SB_DQ_51

SB_DQ_50

SB_DQ_52

SB_DQ_54

SB_DQ_53

SB_DQ_56

SB_DQ_55

SB_DQ_57

SB_DQ_59

SB_DQ_58

SB_DQ_61

SB_DQ_60

SB_DQ_62

SB_BS_0

SB_DQ_63

SB_BS_2

SB_BS_1

SB_RAS*

SB_CAS*

SB_WE*

(4 OF 9)

MEMORY CHANNEL B

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

27 67

28 67

27 28 32 67

29 67

30 67

29 30 32 67

27 28 32 67

8

67

8

67

27 28 32 67

27 67

28 67

27 67

28 67

27 28 32 67

29 30 32 67

8

67

8

67

29 30 32 67

29 67

30 67

29 67

30 67

29 30 32 67

2C-35W

IVY-BRIDGE

BGA

OMIT_TABLE

CRITICAL

BGA

IVY-BRIDGE

2C-35W

OMIT_TABLE

CRITICAL

CPU DDR3 INTERFACES

SYNC_DATE=07/27/2011

SYNC_MASTER=J30_MLB

MEM_A_DQ<3>

MEM_A_CLK_P<0>

MEM_B_A<15>

MEM_B_A<14>

MEM_B_A<12> MEM_B_A<13>

MEM_B_A<11>

MEM_B_A<10>

MEM_B_A<9>

MEM_B_A<7> MEM_B_A<8>

MEM_B_A<6>

MEM_B_A<5>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_A<2>

MEM_B_A<1>

MEM_B_A<0>

MEM_B_DQS_P<7>

MEM_B_DQS_P<6>

MEM_B_DQS_P<5>

MEM_B_DQS_P<4>

MEM_B_DQS_P<3>

MEM_B_DQS_P<2>

MEM_B_DQS_P<1>

MEM_B_DQS_P<0>

MEM_B_DQS_N<7>

MEM_B_DQS_N<6>

MEM_B_DQS_N<5>

MEM_B_DQS_N<4>

MEM_B_DQS_N<3>

MEM_B_DQS_N<2>

MEM_B_DQS_N<1>

MEM_B_DQS_N<0>

MEM_B_ODT<0> MEM_B_ODT<1>

MEM_B_CS_L<1>

MEM_B_CS_L<0>

MEM_B_CKE<1>

MEM_B_CLK_P<1> MEM_B_CLK_N<1>

MEM_B_CLK_N<0>

MEM_B_CKE<0>

MEM_B_CLK_P<0>

MEM_B_DQ<37>

MEM_B_DQ<36>

MEM_B_DQ<34> MEM_B_DQ<35>

MEM_B_DQ<33>

MEM_B_DQ<31> MEM_B_DQ<32>

MEM_B_DQ<30>

MEM_B_DQ<29>

MEM_B_DQ<26> MEM_B_DQ<27> MEM_B_DQ<28>

MEM_B_DQ<24> MEM_B_DQ<25>

MEM_B_DQ<21> MEM_B_DQ<22> MEM_B_DQ<23>

MEM_B_DQ<20>

MEM_B_DQ<19>

MEM_B_DQ<18>

MEM_B_DQ<17>

MEM_B_DQ<16>

MEM_B_DQ<15>

MEM_B_DQ<14>

MEM_B_DQ<13>

MEM_B_DQ<12>

MEM_B_DQ<11>

MEM_B_DQ<10>

MEM_B_DQ<8> MEM_B_DQ<9>

MEM_B_DQ<7>

MEM_B_DQ<6>

MEM_B_DQ<4> MEM_B_DQ<5>

MEM_B_DQ<3>

MEM_B_DQ<2>

MEM_B_DQ<1>

MEM_B_DQ<0>

MEM_B_DQ<39>

MEM_B_DQ<38>

MEM_B_DQ<40> MEM_B_DQ<41> MEM_B_DQ<42>

MEM_B_DQ<44>

MEM_B_DQ<43>

MEM_B_DQ<46>

MEM_B_DQ<45>

MEM_B_DQ<47>

MEM_B_DQ<49>

MEM_B_DQ<48>

MEM_B_DQ<51>

MEM_B_DQ<50>

MEM_B_DQ<52>

MEM_B_DQ<54>

MEM_B_DQ<53>

MEM_B_DQ<56>

MEM_B_DQ<55>

MEM_B_DQ<57>

MEM_B_DQ<59>

MEM_B_DQ<58>

MEM_B_DQ<61>

MEM_B_DQ<60>

MEM_B_DQ<62>

MEM_B_BA<0>

MEM_B_DQ<63>

MEM_B_BA<2>

MEM_B_BA<1>

MEM_B_RAS_L

MEM_B_CAS_L

MEM_B_WE_L

MEM_A_A<14> MEM_A_A<15>

MEM_A_A<12> MEM_A_A<13>

MEM_A_A<11>

MEM_A_A<9> MEM_A_A<10>

MEM_A_A<8>

MEM_A_A<7>

MEM_A_A<6>

MEM_A_A<5>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_A<2>

MEM_A_A<1>

MEM_A_A<0>

MEM_A_DQS_P<7>

MEM_A_DQS_P<5> MEM_A_DQS_P<6>

MEM_A_DQS_P<3> MEM_A_DQS_P<4>

MEM_A_DQS_P<2>

MEM_A_DQS_P<0> MEM_A_DQS_P<1>

MEM_A_DQS_N<7>

MEM_A_DQS_N<6>

MEM_A_DQS_N<5>

MEM_A_DQS_N<4>

MEM_A_DQS_N<3>

MEM_A_DQS_N<2>

MEM_A_DQS_N<0> MEM_A_DQS_N<1>

MEM_A_ODT<1>

MEM_A_ODT<0>

MEM_A_CS_L<1>

MEM_A_CS_L<0>

MEM_A_CKE<1>

MEM_A_CLK_N<1>

MEM_A_CLK_P<1>

MEM_A_CKE<0>

MEM_A_CLK_N<0>

MEM_A_WE_L

MEM_A_RAS_L

MEM_A_CAS_L

MEM_A_BA<0> MEM_A_BA<1> MEM_A_BA<2>

MEM_A_DQ<62> MEM_A_DQ<63>

MEM_A_DQ<61>

MEM_A_DQ<60>

MEM_A_DQ<59>

MEM_A_DQ<58>

MEM_A_DQ<57>

MEM_A_DQ<56>

MEM_A_DQ<55>

MEM_A_DQ<54>

MEM_A_DQ<53>

MEM_A_DQ<52>

MEM_A_DQ<50> MEM_A_DQ<51>

MEM_A_DQ<49>

MEM_A_DQ<48>

MEM_A_DQ<47>

MEM_A_DQ<46>

MEM_A_DQ<45>

MEM_A_DQ<44>

MEM_A_DQ<42> MEM_A_DQ<43>

MEM_A_DQ<41>

MEM_A_DQ<39> MEM_A_DQ<40>

MEM_A_DQ<38>

MEM_A_DQ<37>

MEM_A_DQ<36>

MEM_A_DQ<34> MEM_A_DQ<35>

MEM_A_DQ<31>

MEM_A_DQ<33>

MEM_A_DQ<32>

MEM_A_DQ<29> MEM_A_DQ<30>

MEM_A_DQ<26>

MEM_A_DQ<28>

MEM_A_DQ<27>

MEM_A_DQ<24> MEM_A_DQ<25>

MEM_A_DQ<23>

MEM_A_DQ<22>

MEM_A_DQ<21>

MEM_A_DQ<19> MEM_A_DQ<20>

MEM_A_DQ<18>

MEM_A_DQ<17>

MEM_A_DQ<16>

MEM_A_DQ<13> MEM_A_DQ<14> MEM_A_DQ<15>

MEM_A_DQ<11> MEM_A_DQ<12>

MEM_A_DQ<9> MEM_A_DQ<10>

MEM_A_DQ<8>

MEM_A_DQ<7>

MEM_A_DQ<6>

MEM_A_DQ<5>

MEM_A_DQ<4>

MEM_A_DQ<2>

MEM_A_DQ<1>

MEM_A_DQ<0>

U1000

BD37 BF36 BA28

BE39

AU36 AV36

AT40 AU40

AY26

BB26

BB40 BC41

AG6 AJ6

AU6 AV9 AR6

AP8 AT13 AU13

BC7

BB7 BA13 BB11

AP11

BA7

BA9

BB9 AY13 AV14 AR14 AY17 AR19 BA14 AU14

AL6

BB14 BB17 BA45 AR43 AW48 BC48 BC45 AR45 AT48 AY48

AJ10

BA49 AV49 BB51 AY53 BB49 AU49 BA53 BB55 BA55 AV56

AJ8

AP50 AP53 AV54 AT54 AP56 AP52 AN57 AN53 AG56 AG53

AL8

AN55 AN52 AG55 AK56

AL7 AR11

AP6

AJ11

AL11

AR10

AR8

AY11

AV11

AU17

AT17

AW45

AV45

AV51

AY51

AT56

AT55

AK54

AK55

BG35 BB34

BE37 BA30 BC30 AW41 AY28 AU26

BE35 BD35 AT34 AU34 BB32 AT32 AY32 AV32

AY40 BA41

BD39 AT41

U1000

BG39 BD42 AT22

AV43

BA34 AY34

BA36 BB36

AR22

BF27

BE41 BE47

AL4 AL1

AV4 BA4 AU3 AR3 AY2 BA3 BE9

BD9 BD13 BF12

AN3

BF8 BD10 BD14 BE13 BF16 BE17 BE18 BE21 BE14 BG14

AR4

BG18 BF19 BD50 BF48 BD53 BF52 BD49 BE49 BD54 BE53

AK4

BF56 BE57 BC59 AY60 BE54 BG54 BA58 AW59 AW58 AU58

AK3

AN61 AN59 AU59 AU61 AN58 AR58 AK58 AL58 AG58 AG59

AN4

AM60 AL59 AF61 AH60

AR1

AU4

AT2

AM2

AL3

AV1

AV3

BE11

BG11

BD18

BD17

BE51

BG51

BA61

BA59

AR59

AT60

AK61

AK59

BF32 BE33

BD43 AT28 AV28 BD46 AT26 AU22

BD33 AU30 BD30 AV30 BG30 BD29 BE30 BE28

AT43 BG47

BF40 BD45

051-9277

2.8.0

12 OF 109

11 OF 73

OUT

IN

BI

OUT

VCCIO_29

VCCIO_28

VCCIO_27

VCCIO_26

VCCIO_25

VCCIO_24

VCCIO_23

VCCIO_22

VCCIO_21

VCCIO_20

VCCIO_19

VCCIO_18

VCCIO_17

VCCIO_16

VCCIO_15

VCCIO_14

VCCIO_13

VCCIO_12

VCCIO_11

VCCIO_10

VCCIO_9

VCCIO_8

VCCIO_7

VCCIO_6

VCCIO_49

VCCIO_48

VCCIO_5

VCCIO_4

VCCIO_3

VCCIO_47

VCCIO_46

VCCIO_45

VCCIO_44

VCCIO_43

VCCIO_1

VCCIO_42

VCCIO_41

VCCIO_40

VCCIO_39

VCCIO_38

VCCIO_37

VCCIO_36

VCCIO_35

VCCIO_34

VCCIO_33

VCCIO_32

VCCIO_31

VCCIO_30

VCCIO_51

VCCIO_50

VCC_76

VCC_75

VCC_74

VCC_73

VCC_72

VCC_71

VCC_70

VCC_69

VCC_68

VCC_67

VCC_66

VCC_64

VCC_63

VCC_62

VCC_61

VCC_60

VCC_59

VCC_58

VCC_57

VCC_56

VCC_55

VCC_54

VCC_53

VCC_52

VCC_51

VCC_50

VCC_49

VCC_48

VCC_47

VCC_46

VCC_45

VCC_44

VCC_43

VCC_42

VCC_41

VCC_40

VCC_39

VCC_38

VCC_37

VCC_36

VCC_35

VCC_34

VCC_33

VCC_32

VCC_31

VCC_30

VCC_29

VCC_28

VCC_27

VCC_26

VCC_25

VCC_24

VCC_23

VCC_22

VCC_21

VCC_20

VCC_19

VCC_18

VCC_17

VCC_16

VCC_15

VCC_14

VCC_13

VCC_12

VCC_11

VCC_10

VCC_9

VCC_8

VCC_7

VCC_6

VCC_5

VCC_4

VCC_3

VCC_2

VCC_1

VCCIO_SEL

VCCPQE_1 VCCPQE_2

VIDALERT*

VIDSCLK VIDSOUT

VCC_SENSE VSS_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

LINES

SENSE SVID QUIET

RAIL

PEG AND DDR

CORE SUPLLY

(6 OF 9)

(7 OF 9)

SENSE

LINE

1.8V

RAIL

SA RAIL

QUIET

RAIL

SENSE

LINE

DDR3-1.5V RAILS

GRPHICS

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8

VDDQ_10

VDDQ_9

VDDQ_11 VDDQ_12 VDDQ_13 VDDQ_14 VDDQ_15 VDDQ_16 VDDQ_17 VDDQ_18

VDDQ_20

VDDQ_19

VDDQ_21 VDDQ_22 VDDQ_23 VDDQ_24 VDDQ_25 VDDQ_26

VCCDQ_1 VCCDQ_2

VDDQ_SENSE

VSS_SENSE_VDDQ

VCCSA_SENSE

VCCSA_VID_0 VCCSA_VID_1

SM_VREF

VAXG_1 VAXG_2

VAXG_4

VAXG_3

VAXG_5 VAXG_6 VAXG_7 VAXG_8 VAXG_9 VAXG_10 VAXG_11 VAXG_12 VAXG_13 VAXG_14 VAXG_15 VAXG_16 VAXG_17 VAXG_18 VAXG_19 VAXG_20 VAXG_21 VAXG_22 VAXG_23 VAXG_24 VAXG_25

VAXG_28

VAXG_26 VAXG_27

VAXG_30

VAXG_29

VAXG_33

VAXG_31 VAXG_32

VAXG_35

VAXG_34

VAXG_36 VAXG_37 VAXG_38 VAXG_39 VAXG_40 VAXG_41 VAXG_42 VAXG_43

VAXG_45

VAXG_44

VAXG_46 VAXG_47 VAXG_48 VAXG_49 VAXG_50 VAXG_51 VAXG_52 VAXG_53 VAXG_54 VAXG_55 VAXG_56

VAXG_SENSE VSSAXG_SENSE

VCCPLL_1 VCCPLL_2 VCCPLL_3

VCCSA_2

VCCSA_1

VCCSA_3 VCCSA_4 VCCSA_5 VCCSA_6 VCCSA_7 VCCSA_8 VCCSA_9 VCCSA_10 VCCSA_11 VCCSA_12 VCCSA_13

VCCSA_15

VCCSA_14

VCCSA_16

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

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NOTICE OF PROPRIETARY PROPERTY:

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D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.

Note. VOLTAGE=0V

Note. VOLTAGE=1.05V

Note. VOLTAGE=0V

Note. VOLTAGE=1.05V

Note. VOLTAGE=0V

PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.

Note. VOLTAGE=1.25V

(IPU)

(NOT controlled by VCCIO_SEL)

Note. VOLTAGE=1.05V

Note. VOLTAGE=0V

VCCIO_SEL can be NC.

IVB supports 1.05V VCCIO.

Fixed at 1.05V

(IPU)

57 66

59 66

54

201

MF

1%

75

1/20W

PLACE_NEAR=U7400.17:2.54mm

PLACE_NEAR=U1000.A44:38mm

201

MF435%

1/20W

MF5%

0

201

1/20W

MF5%

0

57 66

201

1/20W

10K

5%

MF

201

1/20W

MF

5%

10K

54

IVY-BRIDGE

2C-35W

BGA

CRITICAL

OMIT_TABLE

CRITICAL

OMIT_TABLE

BGA

IVY-BRIDGE

2C-35W

10% 16V X5R-CERM

0.1UF

0201

PLACE_NEAR=U1000.AY43:2.54mm

PLACE_NEAR=U1000.C44:2.54mm 1/20W MF

1%

130

201

PLACE_NEAR=U1000.F43:50.8mm

PLACE_SIDE=BOTTOM

MF-LF

100

1%

1/16W

402

PLACE_NEAR=U1000.AN16:50.8mm

1%

PLACE_SIDE=BOTTOM

1/16W

402

MF-LF

100

PLACE_SIDE=BOTTOM

PLACE_NEAR=U1000.G43:50.8mm

1%

MF-LF

1/16W

402

MF-LF

100

1% 1/16W

402

PLACE_SIDE=BOTTOM

PLACE_NEAR=U1000.AN17:50.8mm

PLACE_SIDE=BOTTOM

1%

100

MF-LF

1/16W

PLACE_NEAR=U1000.F45:50.8mm

402

100

1%

PLACE_NEAR=U1000.G45:50.8mm

PLACE_SIDE=BOTTOM

MF-LF

1/16W

402

MF

1/20W

1%

100

PLACE_NEAR=U1000.BC43:50.8mm

PLACE_SIDE=BOTTOM

201

PLACE_NEAR=U1000.U10:50.8mm

100

1%

MF

1/20W

PLACE_NEAR=U1000.BA43:50.8mm

201

MF

100

1%

1/20W

PLACE_SIDE=BOTTOM

1K

5%

1/20W

MF

201

PLACE_NEAR=U1000.AY43:2.54mm

1K

5%

1/20W

MF

201

PLACE_NEAR=U1000.AY43:2.54mm

1/20W

NOSTUFF

201

MF

5%

10K

SYNC_MASTER=J13_MLB_NON_POR

SYNC_DATE=11/10/2011

CPU POWER

CPU_VCCSENSE_N

CPU_VCCIOSENSE_N

CPU_VIDALERT_L_R

CPU_VCCIOSENSE_P

CPU_VCCSA_VID<1>

CPU_DDR_VREF

VOLTAGE=0.75V

CPU_AXG_SENSE_N

CPU_AXG_SENSE_P

CPU_VIDALERT_L

=PPVCCSA_S0_CPU

=PP1V05_S0_CPU_VCCIO

CPU_VIDSCLK

CPU_VIDSOUT_R

=PP1V05_S0_CPU_VCCIO

=PPVCORE_S0_CPU

=PPVCORE_S0_CPU_VCCAXG

=PP1V05_S0_CPU_VCCIO

CPU_VCCIO_SEL

=PP3V3_S0_CPU_VCCIO_SEL

CPU_DDR_VREF

=PP1V5_S3_CPU_VCCDDR

CPU_VDDQ_SENSE_N

=PPVCCSA_S0_CPU

CPU_VCCSASENSE

=PP1V5_S3_CPU_VCCDDR

CPU_VDDQ_SENSE_P

=PPVCORE_S0_CPU

CPU_VCCSENSE_P

=PP1V5_S3_CPU_VCCDQ

=PP1V8_S0_CPU_VCCPLL_R

=PP1V05_S0_CPU_VCCPQE

CPU_VIDSCLK_R

CPU_VIDSOUT

=PP1V5_S3_CPU_VCCDDR

CPU_VCCSA_VID<0>

R1300

1

2

R1310

12

R1311

12

R1312

12

R1314

1

2

R1313

1

2

U1000

A26 A29 A31 A34 A35 A38 A39 A42 C26 C27 C32 C34 C37 C39 C42 D27 D32 D34 D37 D39 D42 E26 E28 E32 E34 E37 E38 F25 F26 F28 F32 F34 F37 F38 F42 G42 H25 H26 H28 H29 H32 H34 H35 H37 H38 H40 J25 J26 J28 J29 J32 J34 J35 J37 J38 J40 J42 K26 K27 K29 K32 K34 K35 K37 K39 K42 L25 L28 L33 L36 L40 N26 N30 N34 N38

F43

AA14 AA15 AB17 AB20 AC13 AD16 AD18 AD21 AE14 AE15 AF16 AF18 AF20

AF46

AG15 AG16 AG17 AG20 AG21

AG48 AG50 AG51

AJ14 AJ15

AJ17 AJ21 AJ25 AJ43 AJ47 AK50 AK51 AL14 AL15 AL16 AL20 AL22 AL26 AL45 AL48 AM16 AM17 AM21 AM43 AM47 AN20 AN42 AN45 AN48

BC22

AN16

W16 W17

AM25 AN22

A44 B43 C44

G43

AN17

U1000

AY43

AA46 AB47 AB50 AB51 AB52 AB53 AB55 AB56 AB58 AB59 AC61 AD47 AD48 AD50 AD51 AD52 AD53 AD55 AD56 AD58 AD59 AE46

N45 P47 P48 P50 P51 P52 P53 P55 P56 P61

F45

T48 T58 T59 T61 U46 V47 V48 V50 V51 V52 V53 V55 V56 V58 V59 W50 W51 W52 W53 W55 W56 W61 Y48 Y61

AM28 AN26

BB3 BC1 BC4

L17 L21 N16 N20 N22 P17 P20 R16 R18 R21

U10

U15 V16 V17 V18 V21

D48 D49

W20

AJ28 AJ33 AJ36 AJ40 AL30 AL34 AL38 AL42 AM33 AM36 AM40 AN30 AN34 AN38 AR26 AR28 AR30 AR32 AR34 AR36 AR40 AV41 AW26 BA40 BB28 BG33

BC43 BA43

G45

C1330

1

2

R1302

1

2

R1360

1

2

R1362

1

2

R1361

1

2

R1363

1

2

R1370

1

2

R1371

1

2

R1380

1

2

R1382

1

2

R1381

1

2

R1330

1

2

R1331

1

2

R1320

1

2

051-9277

2.8.0

13 OF 109

12 OF 73

12

7

12 15

7 9

10 12 14

7 9

10 12 14

7 9

12 14

7 9

12 15

7 9

12 15

7

12

7

10 12 15 26

7

12 15

7

10 12 15 26

7 9

12 14

7

15

7

14

7

14

54

(8 OF 9)

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS

VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS

VSS_NCTF VSS_NCTF

VSS_NCTF

VSS_NCTF VSS_NCTF

(9 OF 9)

VSS

Apple Inc.

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NOTICE OF PROPRIETARY PROPERTY:

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A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

CRITICAL

OMIT_TABLE

IVY-BRIDGE

2C-35W

BGA

2C-35W

OMIT_TABLE

CRITICAL

IVY-BRIDGE

CPU GROUNDS

SYNC_MASTER=J30_MLB

SYNC_DATE=07/27/2011

U1000

A13 A17 A21 A25 A28 A33 A37 A40 A45 A49 A53

A9

AA1

AA13 AA50 AA51 AA52 AA53 AA55 AA56

AA8

AB16 AB18 AB21 AB48 AB61

AC10 AC14 AC46

AC6

AD17 AD20

AD4

AD61

AE13

AE8

AF1 AF17 AF21 AF47 AF48 AF50 AF51 AF52 AF53 AF55 AF56 AF58 AF59

AG10 AG14 AG18 AG47 AG52 AG61

AG7

AH4 AH58

AJ13 AJ16 AJ20 AJ22 AJ26 AJ30 AJ34 AJ38 AJ42 AJ45 AJ48

AJ7

AK1 AK52 AL10 AL13 AL17 AL21 AL25 AL28 AL33 AL36 AL40 AL43 AL47 AL61

AM13 AM20 AM22 AM26 AM30

AM34 AM38

AM4

AM42 AM45 AM48 AM58 AN1 AN21 AN25 AN28 AN33 AN36 AN40 AN43 AN47 AN50 AN54

AP10 AP51 AP55

AP7

AR13 AR17 AR21 AR41 AR48 AR61

AR7

AT14 AT19 AT36

AT4

AT45 AT52 AT58 AU1

AU11 AU28 AU32 AU51

AU7

AV17 AV21 AV22 AV34 AV40 AV48 AV55

AW13 AW43 AW61

AW7

AY14 AY19 AY30 AY36

AY4

AY41 AY45 AY49 AY55 AY58

AY9

BA1 BA11 BA17 BA21 BA26 BA32 BA48 BA51 BB53

BC13

BC5

BC57

BD12 BD16 BD19 BD23 BD27 BD32 BD36 BD40 BD44 BD48 BD52 BD56

BD8

BE5 BG9

U1000

BG13 BG17 BG21 BG24 BG28 BG37 BG41 BG45 BG49 BG53

C29 C35 C40

D10 D14 D18 D22 D26 D29 D35

D4

D40 D43 D46 D50 D54 D58

D6

E25 E29

E3

E35 E40 F13 F15 F19 F29 F35 F40 F55

G48 G51

G6

G61

H10 H14 H17 H21

H4

H53 H58

J1 J49 J55

K11 K21 K51

K8

L16 L20 L22 L26 L30 L34 L38 L43 L48 L61

M11 M15

M4

M58

M6

N1 N17 N21 N25 N28 N33 N36 N40 N43 N47 N48 N51 N52 N56 N61

A5 A57 BC61 BD3 BD59 BE4 BE58 BG5 BG57 C3 C58 D59 E1 E61

P14 P16 P18 P21 P58 P59

P9

R17 R20

R4

R46 T1 T47 T50 T51 T52 T53 T55 T56

U13

U8

V20 V61

W13 W15 W18 W21 W46

W8

Y4 Y47 Y58 Y59

051-9277

2.8.0

14 OF 109

13 OF 73

Apple Inc.

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124578

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87 6 5 4 3

C

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NOTICE OF PROPRIETARY PROPERTY:

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12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

CPU VCORE DECOUPLING

Processor Load Line : -2.9 mOhms

PLACEMENT_NOTE (C1640-C1645):

CPU VCCPLL DECOUPLING

CPU VCCIO/VCCPQ DECOUPLING

CPU VCCPLL Low pass filter

PLACEMENT_NOTE (C1684-C167F):

PLACEMENT_NOTE (C1672-C1681):

Intel recommendation (Section 6.5): 26x 1uF, 10x 10uF, 2x 330uF

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

Note:The smallest 10mOhm available in the library are 0805s

PLACEMENT_NOTE (C1646-C1671):

Intel recommendation (section 6.4): 2x 1uF, 1x 330uF

Intel recommendation (Table 7-1): 16x 2.2uF, 12x 22uF, 3x 330uF

All INTEL recommendations from Intel doc #4439028 Huron River Platform Power Design Guide

PLACEMENT_NOTE (C1667-C1679):

PLACEMENT_NOTE (C1655-C1666):

10%

10%10%10%

10%

10%10%10%10%

10%10%10%10%10%10%10%

10%

10%10%10%10%10%10%

10%10%10%10%10%

10%

10V

10V10V10V

10V

10V10V10V10V

10V10V10V10V10V10V10V

10V

10V10V10V10V10V10V

10V10V10V10V10V

10V

=PPVCORE_S0_CPU

=PP1V05_S0_CPU_VCCIO

=PP1V05_S0_CPU_VCCPQE

=PP1V8_S0_CPU_VCCPLL

=PP1V8_S0_CPU_VCCPLL_R

CPU DECOUPLING-I

SYNC_MASTER=J11_MLB

SYNC_DATE=10/03/2011

PLACE_NEAR=U1000.BB3:2.54 mm:NO_VIA

1UF

X5R 402

Place near U1000 on top side

0

402

5%

MF-LF

1/16W

Place near U1000 on bottom side

10UF

CERM-X5R

20%

6.3V 0402-1

1UF

X5R 402

1UF

X5R 402

1UF

X5R 402

1UF

X5R 402

1UF

X5R 402

X5R

1UF

402

1UF

X5R 402

1UF

X5R 402

1UF

X5R 402

1UF

X5R 402

1UF

X5R 402

1UF

X5R 402

1UF

X5R 402

1UF

X5R 402

1UF

X5R 402

6.3V 0201

20%

1UF

X5R

CRITICAL

20%

6.3V X5R

1UF

CRITICAL

0201

6.3V X5R

1UF

CRITICAL

20%

02010201

1UF

X5R

6.3V

20%

CRITICAL

0201

X5R

1UF

20%

6.3V

CRITICALCRITICAL

1UF

X5R

6.3V

20%

0201

X5R 402

1UF

X5R 402

1UF

X5R 402

Place on bottom side of U1000

1UF

X5R 402

CERM-X5R

20%

0402-1

CRITICAL

10UF

6.3V

Place close to U1000 on top side.

CRITICAL

10UF

20%

6.3V 0402-1

CERM-X5R

6.3V X5R

1UF

20%

CRITICAL

0201

20% X5R

0201

6.3V

CRITICAL

1UF

X5R

6.3V

20%

1UF

CRITICAL

0201

CRITICAL

20% X5R

1UF

6.3V

0201

6.3V

1UF

X5R

20%

CRITICAL

0201

6.3V

1UF

X5R

20%

CRITICAL

0201

1UF

20%

6.3V X5R

CRITICAL

20%

0201

6.3V

1UF

X5R

CRITICAL

0201

X5R

6.3V

1UF

20%

CRITICAL

X5R

6.3V

20%

0201

1UF

CRITICAL

Place on bottom side of U1000

X5R 402

1UF

0201

X5R

6.3V

1UF

20%

CRITICAL

0201

1UF

20%

CRITICAL

6.3V X5R

0201

CRITICAL

6.3V

1UF

X5R

20%

0201

6.3V

1UF

X5R

20%

CRITICAL

0201

X5R

6.3V

1UF

20%

CRITICALCRITICAL

1UF

X5R

20%

0201

6.3V

1UF

6.3V 0201

X5R

20%

CRITICAL

0201

CRITICAL

1UF

6.3V X5R

20%

CRITICAL

0201

6.3V X5R

1UF

20%

CRITICAL

0201

X5R

6.3V

1UF

20%

X5R

Place on bottom side of U100.

1UF

402

6.3V

1UF

20%

CRITICAL

0201

X5R

0201

1UF

6.3V X5R

20%

CRITICAL

20%

6.3V

1UF

0201

X5R

CRITICAL

0201

X5R

20%

1UF

CRITICAL

6.3V

0201

6.3V

1UF

X5R

20%

CRITICAL

1UF

0201

20%

6.3V X5R

CRITICALCRITICAL

0201

20%

6.3V

1UF

X5R

CRITICAL

20%

1UF

X5R 0201

6.3V

0201

6.3V

1UF

20%

CRITICAL

X5R

0201

1UF

X5R

CRITICAL

20%

6.3V

0201

6.3V

1UF

X5R

20%

CRITICAL

0201

6.3V X5R

1UF

20%

CRITICAL

0201

20%

6.3V X5R

1UF

CRITICAL

0201

6.3V

1UF

X5R

20%

CRITICAL

0201

6.3V

1UF

X5R

20%

CRITICAL

0201

20%

6.3V

1UF

X5R

CRITICAL

0201

6.3V X5R

20%

CRITICAL

1UF

10UF

20% CERM-X5R

6.3V 0402-1

CRITICAL

X5R 402

1UF

Place on bottom side of U1000

CRITICAL

6.3V 0402-1

CERM-X5R

20%

10UF10UF

CRITICAL

6.3V 0402-1

CERM-X5R

20%

6.3V CERM-X5R

CRITICAL

0402-1

20%

10UF

CRITICAL

CERM-X5R

20%

0402-1

6.3V

10UF

20%

10UF

6.3V 0402-1

CERM-X5R

CRITICAL

6.3V

20% CERM-X5R

CRITICAL

0402-1

10UF

CERM-X5R

CRITICAL

20%

0402-1

6.3V

10UF

0402-1

CRITICAL

20% CERM-X5R

6.3V

10UF

CRITICAL

6.3V 0402-1

CERM-X5R

20%

10UF

0402-1

20%

CRITICAL

6.3V

10UF

CERM-X5R

1UF

X5R 402

10UF

0402-1

20%

6.3V

CRITICAL

CERM-X5R

CASE-B2-SM

TANT

270UF

2V

20%

2V

20% TANT

PLACE_NEAR=U1000.BC2:5mm

CASE-B2-SM

270UF

2V TANT CASE-B2-SM

270UF

20%

CASE-B2-SM

270UF

TANT

20% 2V

270UF

TANT CASE-B2-SM

2V

20%

CASE-B2-SM

2V

20% TANT

270UF

CASE-B2-SM

TANT

20% 2V

270UF

20%

270UF

2V TANT CASE-B2-SM

10UF

6.3V

20% CERM-X5R

0402-1

CRITICAL

CERM-X5R

6.3V

10UF

20%

0402-1

CRITICAL

1UF

X5R 402

2V TANT

20%

270UF

CASE-B2-SM

20% 2V

CASE-B2-SM

TANT

270UF

Place near U1000 on bottom side

10UF

CERM-X5R 0402-1

20%

6.3V

Place near U1000 on bottom side

10UF

CERM-X5R 0402-1

20%

6.3V

Place near U1000 on bottom side

10UF

CERM-X5R 0402-1

20%

6.3V

Place near U1000 on bottom side

10UF

CERM-X5R 0402-1

20%

6.3V

1UF

X5R 402

Place near U1000 on bottom side

10UF

CERM-X5R 0402-1

20%

6.3V

Place near U1000 on bottom side

10UF

CERM-X5R 0402-1

20%

6.3V

Place near U1000 on bottom side

10UF

CERM-X5R 0402-1

20%

6.3V

Place near U1000 on bottom side

10UF

CERM-X5R 0402-1

20%

6.3V

CERM-X5R

10UF

6.3V

20%

0402-1

Place near U1000 on bottom side

1UF

X5R 402

1UF

PLACE_NEAR=U1000.BC1:2.54 mm:NO_VIA

1UF

X5R 402

0.010

MF

0603

1%

1/4W

R1601

12

C167F

1

2

C1697

1

2

C161F

1

2

C1698

1

2

C1699

1

2

C169A

1

2

C169B

1

2

C169C

1

2

C1684

1

2

C1685

1

2

C1686

1

2

C1655

1

2

C1656

1

2

C1687

1

2

C1688

1

2

C1689

1

2

C1600

1

2

C1601

1

2

C1602

1

2

C1603

1

2

C1604

1

2

C1605

1

2

C169D

1

2

C169E

1

2

C169F

1

2

C161A

1

2

C161B

1

2

C161C

1

2

C161D

1

2

C1690

1

2

C1691

1

2

C1692

1

2

C1693

1

2

C1694

1

2

C1695

1

2

C1696

1

2

R1600

12

C160X

1

2

C160Y

1

2

C161E

1

2

C162A

1

2

C162B

1

2

C162C

1

2

C162D

1

2

C162E

1

2

C167A

1

2

C167B

1

2

C167C

1

2

C167D

1

2

C1680

1

2

C1657

1

2

C1658

1

2

C1681

1

2

C1682

1

2

C1683

1

2

C167E

1

2

C167G

1

2

C167H

1

2

C160Z

1

2

C1679

1

2

C1659

1

2

C1660

1

2

C1661

1

2

C1662

1

2

C1663

1

2

C1664

1

2

C1665

1

2

C1666

1

2

C1667

1

2

C1668

1

2

C1669

1

2

C1670

1

2

C1606

1

2

C1607

1

2

C1608

1

2

C1609

1

2

C1610

1

2

C1611

1

2

C1612

1

2

C1613

1

2

C1614

1

2

C1615

1

2

C1616

1

2

C1617

1

2

C1618

1

2

C1619

1

2

C1620

1

2

C1621

1

2

C1622

1

2

C1623

1

2

C1624

1

2

C1625

1

2

C1626

1

2

C1627

1

2

C1628

1

2

C1629

1

2

C1630

1

2

C1631

1

2

C1632

1

2

C1633

1

2

C1634

1

2

C1635

1

2

C1636

1

2

C1637

1

2

C1638

1

2

C1639

1

2

C1640

1

2

C1641

1

2

C1642

1

2

051-9277

2.8.0

16 OF 109

14 OF 73

12

9 7

12 10

9 7

12

7

12

7

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Intel recommendation (section 6.3): 18x 1uF(9 no-stuff), 10x 104F(2 no-stuff), 8x 22uF(2 no stuff), 4x 470uF(2 no-stuff)

PLACEMENT_NOTE (C1711-C1716):

PLACEMENT_NOTE (C1717-C1722):

CPU VDDQ/VCCDQ DECOUPLING

Intel recommendation (Section 6.6): 3x 1uf, 3x 10uf, 1x 330uf

VAXG DECOUPLING

PLACEMENT_NOTE (C1700-C1710):

Graphics Load Line : -3.9 mOhms

PLACEMENT_NOTE (C1738-C1747):

PLACEMENT_NOTE (C1758-C1762):

CPU VCCSA DECOUPLING

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

Intel recommendation (Section 6.13): 10x 1uF, 8x 10uF, 1x 330uF

PLACEMENT_NOTE (C1723-C1724):

10%10%

10% 10%

10%10%10%10%10%

10%10%10%

10%

10%10%10%10%10%10%

10%10%10%10%10%10%10%10%

10V10V

10V 10V

10V10V10V10V10V

10V10V10V

10V

10V10V10V10V10V10V

10V10V10V10V10V10V10V10V

=PP1V5_S3_CPU_VCCDQ

=PPVCCSA_S0_CPU

=PP1V5_S3_CPU_VCCDDR

=PPVCORE_S0_CPU_VCCAXG

SYNC_DATE=07/29/2011

CPU DECOUPLING-II

SYNC_MASTER=K21_MLB

Place on bottom side of U100.

X5R 402

1UF

402

X5R

Place on bottom side of U1000

1UF

Place on bottom side of U1000

X5R

1UF

402

CRITICAL

X5R 402

1UF

CRITICAL

X5R

1UF

402

X5R 402

Place on bottom side of U1000

1UF

X5R

1UF

402

Place on bottom side of U1000

X5R 402

Place on bottom side of U100.

1UF

X5R

Place on bottom side of U1000

1UF

402

X5R

1UF

CRITICAL

X5R 402

1UF

CRITICAL

X5R

1UF

CRITICAL

402

1UF

402

X5R

402

X5R

1UF

CRITICALCRITICAL

X5R 402

1UF

X5R 402

1UF

CRITICAL

Place on bottom side of U1000

1UF

402

X5R

CRITICAL

X5R

Place on bottom side of U100.

402

CRITICAL

1UF1UF

X5R

CRITICAL

402

Place on bottom side of U1000

402

X5R

1UF

402

1UF

X5RX5R

402

1UF

6.3V

20%

X5R-CERM1 0603

22UF

AXG_ACOUSTIC:NO

22UF

20%

6.3V X5R-CERM1 0603

AXG_ACOUSTIC:NO

22UF

20%

6.3V X5R-CERM1 0603

AXG_ACOUSTIC:NO

402

1UF

X5RX5R

1UF

402402

X5R

1UF

Place on bottom side of U1000

X5R 402

1UF

22UF

4V X5R

20%

402

AXG_ACOUSTIC:YES

X5R

4V

20%

22UF

402

AXG_ACOUSTIC:YES

X5R

4V

20%

22UF

402

AXG_ACOUSTIC:YES

20% 4V X5R

22UF

402

AXG_ACOUSTIC:YES

4V X5R

22UF

20%

402

AXG_ACOUSTIC:YES

22UF

20%

6.3V

0603

X5R-CERM1

AXG_ACOUSTIC:NO

20%

22UF

4V X5R 402

AXG_ACOUSTIC:YES

Place close to U1000 on bottom side

0402-1

CERM-X5R

10UF

20%

6.3V

0402-1

20%

6.3V

CERM-X5R

10UF

Place close to U1000 on bottom side

270UF

CASE-B2-SM

2V

20%

TANT

270UF

TANT

2V

CASE-B2-SM

20%

TANT

2V

20%

270UF

CASE-B2-SM

10UF

CERM-X5R

6.3V

20%

0402-10402-1

20%

6.3V

CERM-X5R

10UF

22UF

X5R-CERM1

20%

6.3V

0603

AXG_ACOUSTIC:NO

0402-1

20%

6.3V

CERM-X5R

10UF

20%

6.3V

CERM-X5R

10UF

0402-10402-1

20%

6.3V

CERM-X5R

10UF

0402-1

20%

6.3V

CERM-X5R

10UF

Place close to U1000 on bottom sidePlace close to U1000 on bottom side

10UF

CERM-X5R

6.3V

20%

0402-10402-1

20%

6.3V

CERM-X5R

10UF

Place close to U1000 on bottom sidePlace close to U1000 on bottom side

10UF

CERM-X5R

6.3V

20%

0402-10402-1

20%

CERM-X5R

10UF

Place close to U1000 on bottom side

6.3V

0603

X5R-CERM1

20%

6.3V

22UF

AXG_ACOUSTIC:NO

0402-1

6.3V

CERM-X5R

20%

10UF

Place close to U1000 on bottom side

10UF

6.3V

20%

0402-1

CRITICAL

CERM-X5R

0402-1

20%

6.3V

CERM-X5R

CRITICAL

10UF

6.3V

0402-1

20%

CERM-X5R

10UF

CRITICAL

CERM-X5R

0402-1

20%

10UF

6.3V

CRITICAL

0402-1

10UF

CERM-X5R

6.3V

20%

CRITICAL

10UF

CRITICAL

20%

6.3V

CERM-X5R

0402-1

270UF

TANT

2V

20%

CASE-B2-SM

2V

20%

TANT

270UF

CASE-B2-SM

1UF

X5R 402

Place on bottom side of U1000

MF

1/4W

1%

0.010

0603

R1702

12

C1757

1

2

C1738

1

2

C1739

1

2

C1740

1

2

C1717

1

2

C1718

1

2

C1719

1

2

C1741

1

2

C1742

1

2

C1743

1

2

C1744

1

2

C1720

1

2

C1721

1

2

C1722

1

2

C1745

1

2

C1746

1

2

C1747

1

2

C1700

1

2

C1701

1

2

C1702

1

2

C1704

1

2

C1705

1

2

C1706

1

2

C1707

1

2

C1708

1

2

C1709

1

2

C1758

1

2

C1759

1

2

C1760

1

2

C1761

1

2

C1762

1

2

C1710

1

2

C1703

1

2

C1756

1

2

C1768

1

2

C1711

1

2

C1712

1

2

C1713

1

2

C1714

1

2

C1715

1

2

C1716

1

2

C1748

1

2

C1749

1

2

C1751

1

2

C1752

1

2

C1753

1

2

C1755

1

2

C1763

1

2

C1764

1

2

C1765

1

2

C1766

1

2

C1767

1

2

C1723

1

2

C1724

1

2

C1725

1

2

C1754

1

2

C1750

1

2

C1727

1

2

C1728

1

2

C1729

1

2

C1730

1

2

C1731

1

2

C1732

1

2

051-9277

2.8.0

17 OF 109

15 OF 73

12

7

12

7

26 12 10

7

12

9 7

IN

OUT

BI

IN

OUT

IN

OUT

BI

OUT

BI

IN

OUT

IN

OUT

BI

OUT

IN

OUT

IN

OUT

IN

OUT

BI

OUT

BI

NC

IHDA

(1 OF 10)

JTAG

SATA

LPC

RTCSPI

HDA_SDIN2

HDA_SDIN0

HDA_SYNC

SPI_CS1*

JTAG_TMS

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

FWH4/LFRAME*

HDA_DOCK_EN*/GPIO33 HDA_DOCK_RST*/GPIO13

HDA_SDIN1

HDA_SDIN3

HDA_SDO

JTAG_TCK

JTAG_TDI

JTAG_TDO

LDRQ0*

LDRQ1*/GPIO23

RTCX2

SATA0GP/GPIO21

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

SATA1GP/GPIO19

SATA1RXN SATA1RXP SATA1TXN SATA1TXP

SATA2RXN SATA2RXP SATA2TXN SATA2TXP

SATA3COMPI SATA3RBIAS

SATA3RCOMPO

SATA3RXN SATA3RXP SATA3TXN SATA3TXP

SATA4RXN SATA4RXP SATA4TXN SATA4TXP

SATA5RXN SATA5RXP SATA5TXN SATA5TXP

SATAICOMPI

SATAICOMPO

SATALED*

SERIRQ

SPI_CLK

SPI_CS0*

SPI_MISO

SPI_MOSI

HDA_RST*

SPKR

RTCX1

HDA_BCLK

INTVRMEN

INTRUDER*

SRTCRST*

RTCRST*

IN

OUT

IN

C-LINK

SMBUS

PCI-E*

CLOCKS

FLEX

CLOCKS

(2 OF 10)

XTAL25_OUT

XTAL25_IN

XCLK_RCOMP

SML1DATA/GPIO75

SML1CLK/GPIO58

SML1ALERT*/PCHHOT*/GPIO74

SML0DATA

SML0CLK

SML0ALERT*/GPIO60

SMBDATA

SMBCLK

SMBALERT*/GPIO11

REFCLK14IN

PETP8

PETP7

PETP6

PETP5

PETP4

PETP3

PETP1

PETN8

PETN7

PETN6

PETN5

PETN4

PETN3

PETN2

PETN1

PERP8

PERP7

PERP6

PERP5

PERP4

PERP3

PERP1

PERN8

PERN6

PERN5

PERN4

PERN3

PERN2

PERN1

PEG_B_CLKRQ*/GPIO56

PEG_A_CLKRQ*/GPIO47

PCIECLKRQ7*/GPIO46

PCIECLKRQ6*/GPIO45

PCIECLKRQ5*/GPIO44

PCIECLKRQ4*/GPIO26

PCIECLKRQ3*/GPIO25

PCIECLKRQ2*/GPIO20

PCIECLKRQ1*/GPIO18

PCIECLKRQ0*/GPIO73

CL_RST1*

CL_DATA1

CL_CLK1

CLKOUT_PEG_B_P

CLKOUT_PEG_B_N

CLKOUT_PEG_A_P

CLKOUT_PEG_A_N

CLKOUT_PCIE7P

CLKOUT_PCIE7N

CLKOUT_PCIE6P

CLKOUT_PCIE6N

CLKOUT_PCIE5P

CLKOUT_PCIE5N

CLKOUT_PCIE4P

CLKOUT_PCIE4N

CLKOUT_PCIE3P

CLKOUT_PCIE3N

CLKOUT_PCIE2P

CLKOUT_PCIE2N

CLKOUT_PCIE1P

CLKOUT_PCIE1N

CLKOUT_PCIE0P

CLKOUT_PCIE0N

CLKOUT_ITPXDP_P

CLKOUT_ITPXDP_N

CLKOUT_DP_P

CLKOUT_DP_N

CLKOUT_DMI_P

CLKOUT_DMI_N

CLKOUTFLEX3/GPIO67

CLKOUTFLEX2/GPIO66

CLKOUTFLEX1/GPIO65

CLKOUTFLEX0/GPIO64

CLKIN_SATA_P

CLKIN_SATA_N

CLKIN_PCILOOPBACK

CLKIN_GND1_P

CLKIN_GND1_N

CLKIN_DOT_96P

CLKIN_DOT_96N

CLKIN_DMI_P

CLKIN_DMI_N

PERN7

PETP2

PERP2

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(IPU-RSMRST#)

1.8V -> 1.1V

(IPD-PLTRST#)

(IPD-PWROK)

(IPU)

(IPD-PWROK)

(IPU)

(IPD)

VSel strap not functional (VCCVRM = 1.8V)

(IPD)

(IPD-BOOT)

(IPD) (IPD)

(IPU)

(IPD)

(IPD-BOOT)

(IPU)

(IPU/IPD) (IPU/IPD)

(IPD-PWROK)

(IPU-RSMRST#)

Unused clock terminations for FCIM Mode

Controlled by PCIECLKRQ5#

DOES THIS NEED LENGTH MATCH???

If HDA = S0, must also ensure that signal cannot be high in S3.

Connect to ENET_MEDIA_SENSE via 12K R if HDA = 1.5V.

Connect to ENET_MEDIA_SENSE via alias if HDA = 3.3V.

25 69

43 69

6

41 43

38 68

6

37 69

6

37 69

44 69

330K

MF

5%

1/20W

201

1M

MF 201

5% 1/20W

20K

MF

201

5%

1/20W

20K

MF 201

5% 1/20W

37.4

MF 201

1% 1/20W

PLACE_NEAR=U1800.AB10:2.54mm

10K

MF 201

5% 1/20W

PLACE_NEAR=U1800.AC49:2.54mm

90.9

MF

201

1%

1/20W

44 69

16

23 69

23

69

NO STUFF

0

MF

201

5%

1/20W

5%

201

MF

0

NO STUFF

1/20W

201

MF

1K

1%

25 69

25

MF 201

1%

PLACE_NEAR=U1800.AH4:2.54mm

201

1% 1/20W

49.9

MF

PLACE_NEAR=U1800.AF12:2.54mm

23

8

23

6

37 69

6

37 69

16 37

16

44 69

10 66

8

16 68

25 69

16

8

16

34 69

16 36

1/20W

MF5%

201

4.7K

201

10K

MF5%

1/20W

5% MF

10K

201

10K

201

1/20W

5% MF

1/20W

5%

201

MF

10K

5%

1/20W

201

MF

10K

5%

1/20W

MF

10K

201

MF

10K

5%

1/20W

5%

201

MF

10K 10K

1/20W

5%

201

MF

201

10K

MF5%

1/20W

5%

201

MF

10K

201

MF

1/20W

5%

10K

5% MF

10K

1/20W

201

1/20W

MF

201

10K

5%

10K

1/20W

MF

201

16 24

16

1/20W

5%

201

MF

10K 10K

1/20W

5%

201

MF

1/20W

5%

201

MF

33

PLACE_NEAR=U1800.F35:1.27mm

1/20W

MF

33

5%

201

PLACE_NEAR=U1800.K37:1.27mm

1/20W

5% MF33201

PLACE_NEAR=U1800.H35:1.27mm

1/20W

5%

201

MF

33

PLACE_NEAR=U1800.H37:1.27mm

6

40 69

6

40 69

6

40 69

6

40 69

6

41 43 69

6

41 43 69

6

41 43 69

6

41 43 69

1/20W

201

MF

33

5%

1/20W

5% MF33201

1/20W

5%

201

MF

33

1/20W

5%

201

MF

33

6

41 43 69

1/20W

5% MF33201

1/20W

5%

201

MF

10K

1/20W

201

MF

10K

5%

MF

1/20W

5%

10K

201

5%

201

MF

10K

1/20W

5%

201

MF

10K

1/20W

5%

10K

201

MF

1/20W

5%

201

MF

10K

1/20W

5%

201

MF

10K

1/20W

5%

201

MF

10K

OMIT_TABLE

PCH-PPT-MB-SFF-ES1

BGA

QP8D-MM915462

43 69

23 69

16 34

6

40 69

BGA

OMIT_TABLE

PCH-PPT-MB-SFF-ES1

QP8D-MM915462

1.0UF

20%

X5R

0201-MUR

6.3V

1.0UF

20%

6.3V

X5R 0201-MUR

604

1%MF1/20W

PLACE_NEAR=U1800.W49:5.1mm

201

8

69

8

69

8

6

38 66

6

38 66

6

16 38

SYNC_DATE=07/27/2011

PCH SATA/PCIe/CLK/LPC/SPI

SYNC_MASTER=J30_MLB

=PP1V05_S0_PCH_VCCIO_SATA

TP_SATA_C_R2D_CN

TP_SATA_E_D2RP

TP_SATA_E_R2D_CP

HDA_SYNC_R

HDA_RST_R_L

HDA_SDOUT_R

LPC_AD<0>

SML_PCH_1_DATA

SML_PCH_1_CLK

PEGCLKRQB_L_GPIO56

PCH_INTVRMEN_L

PCIE_CLK100M_FW_P

PCIE_CLK100M_FW_N

PCIE_CLK100M_ENET_P

PCIE_CLK100M_ENET_N

NC_PCIE_8_R2D_CN NC_PCIE_8_R2D_CP

FW_CLKREQ_L

PCIE_CLK100M_EXCARD_P

PCIE_CLK100M_EXCARD_N

SSD_CLKREQ_L

TP_PCIE_CLK100M_PEBN

ENET_CLKREQ_L

PCIE_CLK100M_SSD_P

TP_PCIE_CLK100M_PEBP

PEG_CLK100M_N PEG_CLK100M_P

PCIE_CLK100M_TBT_N

ITPXDP_CLK100M_P

PCIE_CLK100M_SSD_N

ITPXDP_CLK100M_N

PEG_CLKREQ_L

AP_CLKREQ_L

PCIE_CLK100M_AP_P

PCIE_CLK100M_AP_N

=PP1V05_S0_PCH

LPC_AD_R<0> LPC_AD_R<1>

NC_PCIE_7_D2RP

PCH_CLKIN_GNDN1

SML_PCH_0_DATA

LPC_AD_R<2>

NC_PCIE_5_R2D_CP

NC_PCIE_5_D2RN NC_PCIE_5_D2RP

PCIE_EXCARD_R2D_C_P

NC_PCIE_6_D2RN NC_PCIE_6_D2RP NC_PCIE_6_R2D_CN

PCH_SPKR

RTC_RESET_L LPC_AD_R<3>

PCH_SPKR

SYSCLK_CLK25M_SB_R

SYSCLK_CLK25M_SB

NC_PCIE_6_R2D_CP

PCH_CLK96M_DOT_P

PCH_CLK96M_DOT_N

DMI_CLK100M_CPU_P

TP_PCH_CLKOUT_DPN

HDA_BIT_CLK

HDA_SYNC

HDA_SDOUT

PCH_SRTCRST_L PCH_INTRUDER_L

PCH_CLKIN_GNDP1

PCIE_CLK100M_PCH_P

PCH_CLK100M_SATA_N

PCH_CLK96M_DOT_P

=PP3V3_S0_PCH

PCIE_CLK100M_PCH_N

PCH_CLK100M_SATA_P

PCH_CLK96M_DOT_N

PCH_CLK14P3M_REFCLK

LPC_AD<3>

LPC_AD<2>

NC_PCIE_8_D2RN NC_PCIE_8_D2RP

NC_PCIE_7_D2RN

NC_PCIE_7_R2D_CP

PCIE_AP_R2D_C_N PCIE_AP_R2D_C_P

USB_EXTB_SEL_XHCI SML_PCH_0_CLK

USB_EXTD_SEL_XHCI

TP_CLINK_DATA TP_CLINK_RESET_L

PEGCLKRQA_L_GPIO47 TP_PCIE_CLK100M_PEGAN TP_PCIE_CLK100M_PEGAP

DMI_CLK100M_CPU_N

TP_PCH_CLKOUT_DPP

PCIE_CLK100M_PCH_N

PCH_CLKIN_GNDN1 PCH_CLKIN_GNDP1

PCH_CLK100M_SATA_P

PCH_CLK100M_SATA_N

=PP1V05_S0_PCH_VCCDIFFCLK

TP_PCH_GPIO64_CLKOUTFLEX0

TP_PCH_GPIO65_CLKOUTFLEX1

TP_PCH_GPIO66_CLKOUTFLEX2

HDA_BIT_CLK_R

=PPVRTC_G3_PCH

RTC_RESET_L

PCH_SRTCRST_L

PCH_INTRUDER_L

PCH_INTVRMEN_L

HDA_BIT_CLK_R

HDA_RST_R_L

SPI_MOSI_R

SPI_MISO

LPC_SERIRQ

PCH_SATALED_L

TP_SATA_F_R2D_CP

TP_SATA_F_D2RN

TP_SATA_E_R2D_CN

TP_SATA_E_D2RN

TP_SATA_D_R2D_CP

TP_SATA_D_R2D_CN

TP_SATA_D_D2RP

TP_SATA_D_D2RN

PCH_SATA3RBIAS

PCH_SATA3COMP

TP_SATA_C_R2D_CP

TP_SATA_C_D2RP

TP_SATA_C_D2RN

SATA_ODD_R2D_C_P

SATA_ODD_R2D_C_N

SATA_ODD_D2R_P

SATA_ODD_D2R_N

SATA_HDD_R2D_C_P

SATA_HDD_R2D_C_N

SATA_HDD_D2R_P

SATA_HDD_D2R_N

XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL

TBT_PWR_EN_PCH

TP_LPC_DREQ0_L

XDP_PCH_TDI

XDP_PCH_TCK

HDA_SDOUT_R

TP_HDA_SDIN1

ENET_MEDIA_SENSE_RDIV

LPC_FRAME_R_L

LPC_AD_R<3>

LPC_AD_R<2>

LPC_AD_R<1>

LPC_AD_R<0>

XDP_PCH_TMS

TP_SPI_CS1_L

HDA_SYNC_R

HDA_SDIN0

TP_HDA_SDIN2

HDA_RST_L

ITPCPU_CLK100M_N

LPC_FRAME_L

PCIE_EXCARD_R2D_C_N

PCIE_FW_R2D_C_P

PCIE_FW_R2D_C_N

PCIE_FW_D2R_N PCIE_FW_D2R_P

PCIE_EXCARD_D2R_N PCIE_EXCARD_D2R_P

PCIE_ENET_D2R_N

PCIE_ENET_R2D_C_P

TP_SATA_F_R2D_CN

TP_SATA_F_D2RP

PCIE_AP_D2R_P

PCIE_AP_D2R_N

PCIE_ENET_R2D_C_N

PCIE_ENET_D2R_P

LPC_AD<1>

JTAG_DPMUXUC_TRST_L

EXCARD_CLKREQ_L

TP_PCIE_CLK100M_PE4N TP_PCIE_CLK100M_PE4P

TBT_CLKREQ_L

PCH_SATAICOMP

NC_PCIE_5_R2D_CN

XDP_DC3_PCH_GPIO19_SATARDRVR_EN

LPC_FRAME_R_L

FW_CLKREQ_L

PCH_SATALED_L

DP_AUXCH_ISOL SATARDRVR_EN

SYSCLK_CLK32K_RTC

NC_PCIE_7_R2D_CN

PCIE_CLK100M_PCH_P

PCH_CLK14P3M_REFCLK

TP_PCH_GPIO67_CLKOUTFLEX3

PCIE_CLK100M_TBT_P

SSD_CLKREQ_L

PCH_CLK33M_PCIIN

SYSCLK_CLK25M_SB_R

PCH_XCLK_RCOMP

TP_CLINK_CLK

SMBUS_PCH_DATA

SMBUS_PCH_CLK

SMBUS_PCH_ALERT_L

ENET_MEDIA_SENSE_RDIV

ITPCPU_CLK100M_P

AP_CLKREQ_L

JTAG_DPMUXUC_TRST_L ENET_CLKREQ_L

PEGCLKRQA_L_GPIO47

TBT_CLKREQ_L

PEG_CLKREQ_L

EXCARD_CLKREQ_L

USB_EXTD_SEL_XHCI

SMBUS_PCH_ALERT_L USB_EXTB_SEL_XHCI

=PP3V3_S0_PCH_GPIO

=PP3V3_SUS_PCH_GPIO

PEGCLKRQB_L_GPIO56

750

1/20W

TP_HDA_SDIN3

23

SPI_CS0_R_L

SPI_CLK_R

XDP_PCH_TDO

69

JTAG_ISP_TMS

R1800

1

2

R1801

1

2

R1802

1

2

R1803

1

2

R1830

1

2

R1820

1

2

R1890

1

2

R1840

12

R1841

12

R1886

1

2

R1832

1

2

R1831

1

2

R1877

12

R1878

12

R1834

12

R1842

12

R1869

12

R1844

12

R1845

12

R1847

12

R1814

21

R1815

12

R1843

12

R1833

12

R1879

12

R1846

12

R1853

12

R1848

12

R1854

12

R1855

12

R1812

12

R1813

12

R1810

12

R1811

12

R1861

12

R1862

12

R1863

12

R1864

12

R1860

12

R1891

12

R1892

12

R1893

12

R1894

12

R1895

12

R1896

12

R1897

12

R1870

12

R1871

12

U1800

A37 A39 C39 C37 K40

H35

K35 M35

F35

D36 B36 C35 A35

K37

H37

K22

C21

M17

U12

M12

M15

H40 F37

F19

A19 C19

M2

AN3 AN1 AU3 AU1

R1

AN6 AN8 AR3 AR1

AD4 AD2 AL3 AL1

AF12 AH4

AF10

AD8 AD6 AG3 AG1

AE3 AE1 AH8 AH6

AC3 AC1 AJ3 AJ1

AB12

AB10

W10

Y4

AD12

AB8

AB6

Y2

W8

N1

A23

U1800

L3 J1 M8

BD17 BF17

M24 K24

BB26 AY26

E51

AK8 AK6

BB24 AY24

AN10 AN12

AR12 AR10

AD48 AD50

AE49 AE51

AD40 AD42

AA49 AA51

Y48 Y50

AB40 AB42

AB44 AB46

W44 W46

AF44 AF46

AF40 AF42

H50

D48

G49

J51

M4

U8

T4

B8

M19

K8

J3

H4

R8

C4

BJ33

BJ35

BH36

BJ37

BJ39

BH40

BJ41

BJ43

BL33

BL35

BK36

BL37

BL39

BK40

BL41

BL43

BB30

BB33

BF33

BD35

AY35

BD37

AY37

AY40

AY30

AY33

BD33

BF35

BB35

BF37

BB37

BB40

J49

H12 F17 F10

H22 K12 A9

C9 D12 C11

AC49

W49 W51

C1802

1

2

C1803

1

2

R1885

12

051-9277

2.8.0

18 OF 109

16 OF 73

7

22

6

16 69

16 25 69

16

8

16

6

23 66

7

22

16

8

16

8

16

16 16

16

16 69

8

16

16 68

7

22

16 68

8

6

16

7

20 22

6

16 69

7

17 20

16

16 69

16

6

16 69

6

16

16 69

6

10 66

6

68

8

16

23 25

8

6

16 38

16 69

6

16

10 66

16 37

16

16 36

16

16 24

7

17 18 19 25 36

7

17 18 19

16

6

25

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

BI

OUT

IN

OUT

IN

OUT

FDI

(3 OF 10)

DMI

SYSTEM POWER

MANAGEMENT

DMI_ZCOMP

DMI3TXN

DMI2TXN

DMI1TXN

DMI0TXN

FDI_LSYNC1

DSWVRMEN

FDI_FSYNC1

FDI_FSYNC0

FDI_RXP5

FDI_RXP4

FDI_RXP3

FDI_RXP2

FDI_RXP1

FDI_RXP0

APWROK

CLKRUN*/GPIO32

DMI0RXN DMI1RXN DMI2RXN

DMI2RXP

DMI3RXN

DMI3RXP

DMI3TXP

DPWROK

DRAMPWROK

FDI_INT

FDI_LSYNC0

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP6 FDI_RXP7

PMSYNCH

PWROK

SLP_A*

SLP_LAN*/GPIO29

SLP_S3*

SLP_S4*

SLP_S5*/GPIO63

SLP_SUS*

SUSACK*

SUSCLK/GPIO62

SUS_STAT*/GPIO61

SYS_PWROK

SYS_RESET*

WAKE*

RI*

BATLOW*/GPIO72

ACPRESENT/GPIO31

PWRBTN*

SUSWARN*/SUSPWRDNACK/GPIO30

RSMRST*

DMI1RXP

DMI0RXP

DMI_IRCOMP

DMI2RBIAS

DMI0TXP DMI1TXP DMI2TXP

(4 OF 10)

LVDS

DIGITAL DISPLAY INTERFACE

CRT

LVDSA_DATA0* LVDSA_DATA1*

LVDSB_DATA3*

LVDSB_DATA2*

CRT_BLUE

CRT_DDC_CLK CRT_DDC_DATA

CRT_GREEN

CRT_HSYNC

CRT_IRTN

CRT_RED

CRT_VSYNC

DAC_IREF

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPB_AUXN DDPB_AUXP

DDPB_HPD

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPC_AUXN DDPC_AUXP

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_HPD

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

DDPD_AUXN DDPD_AUXP

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_HPD

LVDSA_CLK

LVDSA_CLK*

LVDSA_DATA2* LVDSA_DATA3*

LVDSA_DATA0 LVDSA_DATA1

LVDSA_DATA3

LVDSB_CLK

LVDSB_CLK*

LVDSB_DATA0* LVDSB_DATA1*

LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3

LVD_VREFH LVD_VREFL

L_DDC_CLK L_DDC_DATA

SDVO_CTRLCLK

SDVO_CTRLDATA

SDVO_INTN SDVO_INTP

SDVO_STALLN SDVO_STALLP

SDVO_TVCLKINN SDVO_TVCLKINP

L_BKLTEN L_VDD_EN

L_BKLTCTL

LVD_IBG LVD_VBG

LVDSA_DATA2

L_CTRL_CLK L_CTRL_DATA

NC NC NC NC

NC

NC NC

NC

NC NC

NC

NC NC

NC

NC NC

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(IPD-DeepS4/S5)

(IPU)

(IPD-PLTRST#)

(IPD) (IPD)

9

66

9

66

9

66

9

66

9

66

9

66

49.9

1/20W

1%

201

MF

PLACE_NEAR=U1800.BF19:12.7mm

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

1/20W

5%

201

1K

MF

PLACE_NEAR=U1800.R51:2.54mm

750

MF

1% 1/20W

201

PLACE_NEAR=U1800.BK20:2.54mm

390K

MF 201

5% 1/20W

1/20W

5%

201

MF

10K

0

MF

201

5%

1/20W

17 62

1/20W

5%

201

MF

100K

25 41

23 25 41

10 26 66

25

62

17 23 41

41 42 62

42

6

17 37

6

17 41 43

6

25 41 43

42 69

17 41 62

17 26 37 41 49 62

17 26 41 62

10 66

41

8

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

5%

201

1/20W

MF

100K

1/20W

5% MF1K201

1/20W

5%

201

8.2K

MF

1/20W

5%

201

MF

1K

5%

201

MF

100K

1/20W

5%

1/20W

201

MF

100K

1/20W

5%

201

MF

10K

1/20W

5%

201

MF

5% MF

10K

201

1/20W

17 56

OMIT_TABLE

QP8D-MM915462

BGA

PCH-PPT-MB-SFF-ES1 PCH-PPT-MB-SFF-ES1

OMIT_TABLE

QP8D-MM915462

BGA

MF

5%

100K

1/20W

201

PCH DMI/FDI/PM/Graphics

SYNC_MASTER=J30_MLB

SYNC_DATE=07/27/2011

DMI_N2S_P<1>

PM_PWRBTN_L

PCIE_WAKE_L

PM_SLP_SUS_L

PM_SLP_S5_L

PM_SLP_S3_L

FDI_INT

MEM_VDD_SEL_1V5_L

PM_SLP_S4_L

PM_CLKRUN_L

PCH_SUSWARN_L

=PP3V3_SUS_PCH_GPIO

PM_PWRBTN_L

PCH_SUSWARN_L

PCH_DMI_COMP

DMI_S2N_P<0>

DMI_S2N_P<3>

=PP1V05_S0_PCH_VCCIO_PCIE

=PP3V3_SUS_PCH_GPIO

FDI_DATA_N<0>

FDI_DATA_N<2>

TP_SDVO_INTN

TP_DP_IG_C_MLP<0>

TP_DP_IG_C_MLP<1>

TP_DP_IG_C_MLP<2>

TP_DP_IG_B_MLP<0>

TP_DP_IG_B_MLP<1>

LVDS_IG_PANEL_PWR

LVDS_IG_BKL_ON

LVDS_IG_BKL_PWM

TP_SDVO_INTP

DPA_IG_DDC_DATA

TP_SDVO_TVCLKINP

TP_DP_IG_D_MLP<2>

TP_DP_IG_D_MLN<1>

TP_CRT_IG_DDC_DATA

PCH_SUSACK_L

=PP3V3_SUS_PCH_GPIO

=PP3V3_S5_PCH

=PP3V3_S0_PCH_GPIO

TP_CRT_IG_HSYNC

TP_CRT_IG_DDC_CLK

TP_CRT_IG_RED

TP_CRT_IG_BLUE

FDI_DATA_N<5>

FDI_DATA_P<1> FDI_DATA_P<2> FDI_DATA_P<3>

FDI_DATA_N<7>

FDI_DATA_P<4>

FDI_FSYNC<0>

PCH_RI_L

PCH_DMI2RBIAS

DMI_S2N_P<2>

DMI_S2N_N<2>

FDI_DATA_P<0>

PM_DSW_PWRGD

DMI_S2N_P<1>

DMI_N2S_P<0>

PM_RSMRST_L

PM_BATLOW_L

PCIE_WAKE_L

PM_SYSRST_L

PM_PCH_SYS_PWROK

LPC_PWRDWN_L

PCH_SUSACK_L

PM_SLP_SUS_L

PM_SLP_S5_L PM_SLP_S4_L PM_SLP_S3_L

TP_PM_SLP_A_L

PM_PCH_PWROK

PM_SYNC

FDI_DATA_N<6>

FDI_DATA_N<4>

FDI_DATA_N<3>

FDI_DATA_N<1>

PM_MEM_PWRGD

DMI_N2S_P<3>

DMI_N2S_N<3>

DMI_N2S_P<2>

DMI_N2S_N<2>

DMI_N2S_N<1>

DMI_N2S_N<0>

PM_CLKRUN_L

PM_PCH_APWROK

PCH_DSWVRMEN

DMI_S2N_N<0> DMI_S2N_N<1>

DMI_S2N_N<3>

=PPVRTC_G3_PCH

FDI_LSYNC<0> FDI_LSYNC<1>

FDI_FSYNC<1>

FDI_DATA_P<5>

FDI_DATA_P<7>

FDI_DATA_P<6>

PM_CLK32K_SUSCLK_R

MEM_VDD_SEL_1V5_L

TP_SDVO_TVCLKINN

TP_SDVO_STALLP

TP_SDVO_STALLN

DPA_IG_DDC_CLK

TP_DP_IG_D_HPD

TP_DP_IG_D_CTRL_DATA

TP_DP_IG_D_CTRL_CLK

TP_DP_IG_D_AUXP

TP_DP_IG_D_AUXN

TP_DP_IG_D_MLP<3>

TP_DP_IG_D_MLN<3>

TP_DP_IG_D_MLN<2>

TP_DP_IG_D_MLP<1>

TP_DP_IG_D_MLP<0>

TP_DP_IG_D_MLN<0>

DPB_IG_HPD

DPB_IG_DDC_DATA

DPB_IG_DDC_CLK

DPB_IG_AUX_CH_P

DPB_IG_AUX_CH_N

TP_DP_IG_C_MLP<3>

TP_DP_IG_C_MLN<3>

TP_DP_IG_C_MLN<2>

TP_DP_IG_C_MLN<1>

TP_DP_IG_C_MLN<0>

DPA_IG_HPD

DPA_IG_AUX_CH_P

DPA_IG_AUX_CH_N

TP_DP_IG_B_MLP<3>

TP_DP_IG_B_MLN<3>

TP_DP_IG_B_MLP<2>

TP_DP_IG_B_MLN<2>

TP_DP_IG_B_MLN<1>

TP_DP_IG_B_MLN<0>

PCH_DAC_IREF

TP_CRT_IG_VSYNC

TP_CRT_IG_GREEN

SMC_ADAPTER_EN

R1900

1

2

R1951

1

2

R1920

1

2

R1915

1

2

R1905

1

2

R1986

12

R1909

1

2

R1923

21

R1925

12

R1991

12

R1985

12

R1922

21

R1921

21

R1924

21

R1983

1

2

R1982

12

U1800

H19

G3

H10

T2

BL21

BJ21

BD22

BF22

BL23

BJ23

BB22

AY22

BK20

BJ19

BL19

BB19

AY19

BL17

BJ17

BB17

AY17

BD19

BF19

A21

B12

F22

BH12 BK8

BB10

BK12 BH8

BL13 BJ15 BD12 BJ11 AY15 AY12 BJ9 BF10

BJ13 BL15 BF12 BL11 BB15 BB12 BL9 BD10

BB8

K19

M22

F12

B20

C7

A7

D4

K10

F6

A15

G6

F15

D3

C13

M10

L1

D8

U1800

M46

R49 N49

R46

M50

T48

U46

N51

R51

AY48 AY50 AY44 AY46 BB44 BB46 BA49 BA51

AW51 AW49 AY42

BC49 BC51 BD48 BD50 BF46 BF45 BE49 BE51

AU51 AU49

T50 U44

BE46

BG51 BG49 BF42 BD42 BJ47 BL47 BL45 BJ45

AU46 AU44

M48 U42

BK44

L49

M44

R42 M40

L51 K46

M42

AH42 AH40

AG51 AG49

AK46

AK44

AR44

AR46

AN51

AN49

AN46

AN44

AK42

AK40

AH44

AH46

AM48

AM50

AL51

AL49

AJ49

AJ51

AH48

AH50

W42 R44

AT50 AT48

AR51 AR49

AU40 AU42

R1955

1

2

051-9277

2.8.0

19 OF 109

17 OF 73

17 23 41

6

17 37

17 62

17 41 62

17 26 41 62

17 56

17 26 37 41 49 62

6

17 41 43

17

7

16 17 18 19

17

7

16 17 18 19

6

8

6

8

6

17

7

16 17 18 19

7

16 18 19 25 36

6

17

7

16 20

6

8

6

NC

NC NC

NC

NC NC NC

NC

BI

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

BI

IN

(5 OF 10)

USB

PCI

PME*

PLTRSTB*

PIRQA*

TP2

TP5

TP4

TP11

USB3RN4

USB3RN2

CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4

GNT1*/GPIO51 GNT2*/GPIO53 GNT3*/GPIO55

OC0*/GPIO59 OC1*/GPIO40 OC2*/GPIO41 OC3*/GPIO42 OC4*/GPIO43

OC5*/GPIO9 OC6*/GPIO10 OC7*/GPIO14

PIRQB* PIRQC* PIRQD*

PIRQE*/GPIO2 PIRQF*/GPIO3 PIRQG*/GPIO4 PIRQH*/GPIO5

REQ1*/GPIO50 REQ2*/GPIO52 REQ3*/GPIO54

RSVD

TP1

TP3

TP6 TP7 TP8 TP9 TP10

TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20 TP21 TP22 TP23 TP24

TP41 TP42

USB3RN1

USB3RN3

USB3RP1 USB3RP2 USB3RP3 USB3RP4

USB3TN1 USB3TN2 USB3TN3 USB3TN4

USB3TP1 USB3TP2 USB3TP3 USB3TP4

USBP0N USBP0P

USBP10N USBP10P

USBP11N USBP11P

USBP12N USBP12P

USBP1N USBP1P

USBP2N USBP2P

USBP3N USBP3P

USBP4N USBP4P

USBP5N USBP5P

USBP6N USBP6P

USBP7N USBP7P

USBP8N USBP8P

USBP9N USBP9P

USBRBIAS

USBRBIAS*

USBP13P

USBP13N

NC

BI

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Redundant to pull-up on audio page

USB Hub (All LS/FS Devices)

Ext D (XHCI) (Mobiles: Trackpad?)

Redundant to pull-up on audio page

Ext A (XHCI/EHCI)

Ext B (XHCI)

Ext C (XHCI/EHCI)

Unused

Ext D (EHCI)

Ext B (EHCI)

Camera

RSVD: BT (HS)

RSVD: SD

RSVD: WiFi

Unused

(IPD)

(IPU)

(IPU-PCIERST#)

24 68

8

24 68

8

24 68

39 68

40 68

8

201

1/20W

10K

MF5%

1/20W

5%

201

MF

10K

5% MF

201

1/20W

10K

MF

1/20W

5%

201

10K

MF

201

5%

1/20W

NO STUFF

1/20W

MF

10K

201

5%

10K

MF

201

5%

1/20W

10K

MF

201

5%

MF

10K

201

5%

1/20W

201

10K

MF5%

1/20W

NO STUFF

10K

MF

201

5%

1/20W

5%

10K

MF

201

1/20W

18

6

18 40

18 34

6

18 40

1/20W

5%

201

MF

10K

1/20W

5%

201

MF

10K 10K

MF

1/20W

5%

201

1/20W

5%

201

MF

10K

NO STUFF

10K

MF

201

5%

1/20W

10K

MF

201

5%

1/20W

NO STUFF

18 23

23

39 68

23

BGA

PCH-PPT-MB-SFF-ES1

QP8D-MM915462

OMIT_TABLE

39 68

6

40 68

6

40 68

1%

201

MF

1/20W

22.6

PLACE_NEAR=U1800.A33:2.54mm

25 26

25 69

PCH PCI/USB/TP/RSVD

SYNC_DATE=11/10/2011

SYNC_MASTER=J13_MLB_NON_POR

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L

AUD_I2C_INT_L

BLC_I2C_MUX_SEL

BLC_GPIO

PCH_GPIO54

JTAG_GMUX_TMS

XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L

AP_PWR_EN

TP_PCH_STRP_ESI_L PCH_STRP_TOPBLK_SWP_L

XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

TBT_PWR_REQ_L

=PP3V3_S3_PCH_GPIO

USB_EXTD_XHCI_N

USB_EXTD_EHCI_P

XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L

JTAG_GMUX_TMS

PCH_GPIO54

AUD_IP_PERIPHERAL_DET TBT_PWR_REQ_L AUD_I2C_INT_L

USB3_EXTC_TX_P

PCI_INTB_L

BLC_I2C_MUX_SEL

USB_EXTB_EHCI_P

USB_EXTD_EHCI_N

AUD_IP_PERIPHERAL_DET

=PP3V3_S0_PCH_GPIO

TP_USB_WLANP

TP_USB_WLANN

TP_PCH_STRP_BBS1

USB_EXTA_P

USB_EXTA_N

USB_EXTB_XHCI_P

USB_EXTB_XHCI_N

USB_EXTC_N USB_EXTC_P

USB_EXTD_XHCI_P

TP_USB_4N TP_USB_4P TP_USB_SDN

TP_USB_SDP

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L

XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L

XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

XDP_DB2_PCH_GPIO10_AP_PWR_EN

PCH_USB_RBIAS

TP_USB_13N TP_USB_13P

USB_EXTB_EHCI_N

USB_CAMERA_N USB_CAMERA_P

USB_HUB_UP_N USB_HUB_UP_P

TP_USB_12P

TP_USB_BT_HSN TP_USB_BT_HSP

TP_USB_12N

TP_PCH_TP23

USB3_EXTC_RX_N

USB3_EXTB_RX_N

USB3_EXTA_RX_N

USB3_EXTA_RX_P USB3_EXTB_RX_P

USB3_EXTD_RX_P

USB3_EXTC_RX_P

USB3_EXTA_TX_N USB3_EXTB_TX_N USB3_EXTC_TX_N USB3_EXTD_TX_N

USB3_EXTB_TX_P

USB3_EXTA_TX_P

USB3_EXTD_TX_P

PCI_INTC_L

=PP3V3_S0_PCH_GPIO

PCI_INTA_L

PCI_INTD_L

LPC_CLK33M_SMC_R

TP_PCI_CLK33M_OUT2 TP_PCI_CLK33M_OUT3

LPC_CLK33M_LPCPLUS_R

PCH_CLK33M_PCIOUT

TP_PCI_PME_L

PLT_RESET_L

BLC_GPIO

USB3_EXTD_RX_N

=PP3V3_SUS_PCH_GPIO

R2070

1

2

R2067

21

R2068

12

R2061

12

R2062

12

R2033

12

R2060

12

R2030

12

R2018

12

R2016

12

R2017

12

R2014

12

R2031

12

R2010

12

R2011

12

R2012

12

R2013

12

R2054

21

R2069

12

U1800

G51 E49 H48 J43 G45

F42 H42 D44

C17 A17 A13 D16 A11 B16 C23 H15

D49 C48 C47 C45

A47 C41 F45 F40

F7

H2

G46 K44 F46

AU6 AU8

BB6 BC1 BC3 BD2 BD4 BE1 BE3 BE6 BF6 BF7

AW1

BG1 BG3 BH3 BH4 BJ4 BJ5 BJ7 BK6 BL5

AW3 AY2 AY4 AY6 AY8 BA1 BA3

BH24

D20 M30

E3 AM4 AT4 AT2

AD10

B24 D24

AD44

BK24

AD46 BJ48

BL7 W40 K30

BH20 BK16

BH49 BB42

BH16 AN42 AN40 AR40 AR42

BJ25 BJ27 BJ31 BJ29

BL25 BL27 BL31 BL29

BF26 BB28 BF28 BF30

BD26 AY28 BD28 BD30

F24 H24

C31 A31

H33 F33

H30 F30

M33 K33

C25 A25

C27 A27

H28 F28

M26 K26

D28 B28

H26 F26

D32 B32

M28 K28

C29 A29

A33

C33

051-9277

2.8.0

20 OF 109

18 OF 73

18 23

6

18 40

18

18 23

23 37 62

18 23

18 34

7

25

6

18 40

7

16 17 18 19 25 36

68

7

16 17 18 19 25 36

6

7

16 17 19

OUTOUT

BI

IN

NC

IN

OUT

IN

BI

IN

OUT

IN

OUT

BI

IN

OUT

NCTF

CPU/MISC

(6 OF 10)

GPIO

GPIO1 GPIO6

VSS_NCTF

TS_VSS4

TS_VSS3

TS_VSS2

TS_VSS1

THRMTRIP*

STP_PCI*/GPIO34

SATA3GP/GPIO37

SATA2GP/GPIO36

RCIN*

PROCPWRGD

PECI

NC_1

INIT3_3V*

GPIO71

GPIO70

GPIO69

GPIO68

GPIO35

GPIO8

GPIO7

DF_TVS

A20GATE

GPIO24 GPIO27 GPIO28

BMBUSY*/GPIO0

LAN_PHY_PWR_CTRL/GPIO12 GPIO15 SATA4GP/GPIO16 GPIO17 SCLOCK/GPIO22

SLOAD/GPIO38 SDATAOUT0/GPIO39 SDATAOUT1/GPIO48 SATA5GP/GPIO49 GPIO57

D

SG

D

GS

D

SG

OUT

IN

OUT

IN

OUT

NC

08

NC

OUT

NC

08

OUT

NC

IN

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Stuff R2160 or R2574, not both

Must stuff R2197 when R2180 NO STUFFed.

Set to Vcc when High

Set to Vss when Low

DF_TVS:DMI & FDI Term Voltage

(IPD)

(IPU)

(IPU-DeepS4/S5)

THIS SIGNAL IS INTENDED FOR FIRMWARE HUB AND WE ARE NOT USING IT.

(IPU)

(IPD-PLTRST#?)

(IPU-RSMRST#)

(IPD-PLTRST#)

Systems with no chip-down memory should pull all 4 RAMCFG GPIOs high.

(IPU-RSMRST#)

Systems with chip-down memory should add pull-downs on another page and set straps per software.

This has internal pull up and should not pulled low.

NOTE: TDO from CR is Push-Pull CMOS

TBT_PWR_EN goes high for JTAG Programming

NOTE: TMS/TDI from PCH is Open Drain

NOTE: TCK from PCH is Push-Pull CMOS

JTAG Isolation due to glitch in and out of sleep

(TBT_CIO_PLUG_EVENT_ISOL)

SMC_RUNTIME_SCI_L

XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH

TBT_CIO_PLUG_EVENT_ISOL

NO STUFF

10K

TBT_CIO_PLUG_EVENT

JTAG_ISP_TMS

=PP3V3_S0_PCH_STRAPS

74LVC1G08

=PP3V3_TBT_PCH_GPIO

19

XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH

SSM3K15FV

=PP3V3_S0_PCH_GPIO

SSM6N15AFE

JTAG_ISP_TCK

TBT_PWR_EN

CRITICAL

PCH GPIO/MISC/NCTF

X5R-CERM

SYNC_MASTER=J11_MLB

201

=PP3V3_S0_PCH_STRAPS

JTAG_TBT_TCK

SOT891

=PP3V3_S0_PCH_GPIO

1/20W

MF

PCH_RCIN_L

=PP3V3_S5_PCH_GPIO

10K

MF 201

5% 1/20W

1/20W

5%

201

MF

XDP_FC1_PCH_GPIO0

16V

X5R-CERM

10%

0.1UF

0201

1/20W

5%

MF

10K

MF5%

201

16V

10%

0.1UF

0201

74LVC1G08

CRITICAL

SOT891

10K

1/20W

SSM6N15AFE

XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL

ENET_LOW_PWR_PCH

SMC_RUNTIME_SCI_L

201

JTAG_TBT_TMS

=PP3V3_TBT_PCH_GPIO

TBT_GO2SX_BIDIR

10K

5% 1/20W MF 201

CRITICAL

JTAG_ISP_TDO

=PP3V3_TBT_PCH_GPIO

5%

JTAG_ISP_TDI JTAG_TBT_TDI

1/20W

5%

201

MF

10K

SOD-VESM-HF

1/20W

5%

201

MF

10K

SOT563

5%

201

MF

CRITICAL

SOT563

5%

201

MF

10K

1/20W

5%

201

MF

10K

PCH_A20GATE

MLB_RAMCFG0

MF

201

XDP_FC0_PCH_GPIO15

5%

LPCPLUS_GPIO

XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK

XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL

PM_THRMTRIP_L_R

SMC_WAKE_SCI_L

TBT_GO2SX_BIDIR

XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L TBT_SW_RESET_R_L

XDP_DC1_PCH_GPIO35_MXM_GOOD

JTAG_ISP_TDO JTAG_ISP_TDI FW_PWR_EN_PCH

10 23 66

SPIROM_USE_MLB

8

19

23

MF

1/20W

LPCPLUS_GPIO

10 42 66

5%

MF

1/20W

5%

201

MF

10K

RAMCFG2:H

8

23

=PP1V8_S0_PCH_VCC_DFTERM

CPU_PROC_SEL_L

=PP3V3_S0_PCH_GPIO

MLB_RAMCFG1

MLB_RAMCFG2

MLB_RAMCFG3

CPU_PECI

CPU_PWRGD

PM_THRMTRIP_L

PCH_INIT3V3_L

PCH_RCIN_L

PCH_PROCPWRGD

XDP_FC1_PCH_GPIO0 FW_PME_L DPMUX_UC_IRQ

PCH_PECI

PCH_DF_TVS

WOL_EN

FW_PME_L

TBT_SW_RESET_L

TP_PCH_GPIO8

ODD_PWR_EN_L

WOL_EN

RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H

RAMCFG_SLOT

SYNC_DATE=09/16/2011

OMIT_TABLE

PCH-PPT-MB-SFF-ES1

QP8D-MM915462

BGA

19

23

66 42 10

1/20W

5%

201

MF

390

0

MF

201

5%

1/20W

5%

201

MF

43

NO STUFF

1/20W

201

MF

201

1/20W

5% MF

10K

1/20W

5% MF

10K

1/20W

5% MF

23 19

36

1/20W

0

MF

201

23

1/20W

5%

201

MF

10K

5%

201

MF

10K

5%

201

MF5%

5%

1/20W

201

10K 10K

5%

1/20W

MF

201

10K

MF

1/20W

5%

201

1/20W

5% MF

100K

201

1/20W

5% MF

10K

1/20W

5%

201

MF

10K

5%

201

MF

100K

20K

1/20W

5%

201

1/20W

5%

201

MF

2.2K

1/20W

201

MF

1K

19

41 19

8

41 19

RAMCFG0:H

10K

MF 201

5% 1/20W

10K

MF

201

5%

1/20W

RAMCFG1:HRAMCFG3:H

10K

MF

201

5%

1/20W

50 43 19

6

23

19

NO STUFF

1K

201

5%

1/20W

19

43 19

6

23

100K

JTAG_TBT_TDO

1/20W

CRITICAL

ODD_PWR_EN_L

AUD_IPHS_SWITCH_EN_PCH

DPMUX_UC_IRQ

SMC_WAKE_SCI_L

SPIROM_USE_MLB

PCH_A20GATE

FW_PWR_EN_PCH

TBT_SW_RESET_R_L

201

1/20W

=PP3V3_S0_PCH_GPIO

=PP3V3_SUS_PCH_GPIO

10K

NO STUFF

R2130

1

2

R2172

1

2

R2173

1

2

R2174

1

2

R2175

1

2

R2178

12

R2179

1

2

R2111

21

R2195

21

R2191

12

R2192

12

R2193

12

R2194

12

R2184

12

R2197

12

R2190

12

R2196

12

R2185

12

R2160

12

R2112

21

R2180

12

R2198

21

R2116

21

R2150

12

R2155

12

R2170

12

R2140

12

R2156

12

U1800

U3

W1

BC7

B40

K6

B44

K15 C15

G1

W12

K17

C43

K42 A43

A45

D40 A41

H17

R6

C5

U40

AU12

AU10

U6

W6 M6

AA3

AA1

W3

U10

U1

N3

R3

BC9

AK10 AH12 AK12 AH10

A4 A5

BJ51

BL1 BL3 BL4

BL48 BL49 BL51 C3 C49 C51

A48

D1 D51 E1

A49 A51 BH1

BH51

BJ1 BJ3

BJ49

Q2160

6

2

1

Q2162

3

1

2

Q2160

3

5

4

R2162

1

2

R2186

1

2

R2161

1

2

R2199

1

2

R2188

1

2

R2163

1

2

C2113

1

2

U2100

2

1

3

6

4

R2113

1

2

U2101

2

1

3

6

4

C2114

1

2

R2166

1

2

R2167

1

2

051-9277

2.8.0

21 OF 109

19 OF 73

5

16 19

19

18

34

19

43

17 16

7

19

25 23

19

22 20

7

8

10

36 25 19 18 17 16

7

8

19

23 19

42

50 43 19

6

19

8

23 19

41 19

19

6

41 19

19

23

19

34 19

36 25 18 17

7

19

NC

VCC CORE

LVDS

(7 OF 10)

DMI

DFT/SPI

CRTFDI

VCCIO

VCCCORE

VCC3_3

VCCADAC

VCCADMI_VRM

VCCAFDIPLL

VCCAFDI_VRM

VCCALVDS

VCCDFTERM

VCCDMI

VCCIO

VCCSPI

VCCTX_LVDS

VSSALVDS

VSSA_DAC

VCCAPLLEXP

VCCACLK

V_PROC_IO

VCCCLKDMI

VCCRTC

DCPSUSBYP

VCCDSW3_3

VCCAPLLDMI2

DCPRTC

VCCADPLLB

VCCADPLLA

VCCDIFFCLKN

DCPSST

V5REF

V5REF_SUS

VCCAPLL_SATA3

VCCASW

VCCIO

VCCPUSB

VCCSSC

VCCSUS3_3

VCCSUSHDA

VCCVRM

DCPSUS

USB

SATA

PCI/GPIO/LPC

(8 OF 10)

HDA

CLK/MISC

CPURTC

NC

NC NC

NC

NC NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AL24 left as NC per DG

PCH output, for decoupling only

NC-ed per DG

1.44 A Max, 474mA Idle

VCCACLK pin left as NC per DG

PCH output, for decoupling only

55mA Max, 5mA Idle

10 mA Max, 1mA Idle

VCCAPLLDMI2 pin left as NC per DG

QP8D-MM915462

OMIT_TABLE

BGA

PCH-PPT-MB-SFF-ES1PCH-PPT-MB-SFF-ES1

OMIT_TABLE

QP8D-MM915462

BGA

PLACE_NEAR=U1800.N16:2.54mm

X5R-CERM

10%

0.1UF

16V

0201

PLACE_NEAR=U1800.N16:2.54mm

0201

0.1UF

10% 16V X5R-CERM

PLACE_NEAR=U1800.U17:2.54mm

16V

0.1UF

10%

X5R-CERM

0201

PLACE_NEAR=U1800.N16:2.54mm

0201

1UF

20%

6.3V X5R

PLACE_NEAR=U1800.R15:2.54mm

0.1UF

10% 16V

X5R-CERM

0201

PCH POWER

SYNC_MASTER=J11_MLB

SYNC_DATE=09/30/2011

PP3V3_S0_PCH_VCC3_3_CLK_F

=PP3V3_S0_PCH_VCC3_3

=PP1V05_S0_PCH_VCC_CORE

PP3V3_S0_PCH_VCCA_DAC_F

=PP1V05_S0_PCH_VCC_DMI

=PP1V8R1V5_S0_PCH_VCCVRM =PP1V8_S0_PCH_VCC_DFTERM

=PP1V8R1V5_S0_PCH_VCCVRM

=PP3V3_SUS_PCH_VCC_SPI

TP_1V05_S0_PCH_VCCAPLLEXP

=PP1V05_S0_PCH_VCCIO

=PP3V3R1V5_S0_PCH_VCCSUSHDA

=PP1V05_S0_PCH_VCCSSC

=PP3V3_SUS_PCH_VCCSUS_USB

=PP5V_SUS_PCH_V5REFSUS

=PP1V05_S0_PCH_VCCDIFFCLK

PP1V05_S0_PCH_VCCADPLLA_F PP1V05_S0_PCH_VCCADPLLB_F

MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

PPVOUT_G3_PCH_DCPRTC

MIN_LINE_WIDTH=0.2 mm

=PP3V3_S5_PCH_VCCDSW

TP_PPVOUT_PCH_DCPSUSBYP

=PPVRTC_G3_PCH

PP1V05_S0_PCH_VCCCLKDMI_F

=PP1V05_S0_PCH_V_PROC_IO

=PP1V05_S0_PCH_VCCIO

=PP1V05_S0_PCH_VCCASW

=PP1V8R1V5_S0_PCH_VCCVRM

PPVOUT_S0_PCH_DCPSST

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

=PP5V_S0_PCH_V5REF

=PP3V3_SUS_PCH_VCCSUS

U1800

AB19 AC19 AF6 BK28 R40 T39 U37 V37 V39

U51

AU21

AU19

AP13 AP15

AF33 AG33

AP19

AB21 AB23

AG25 AG27 AJ21 AJ23 AJ25 AJ27 AJ29 AJ31 AK29 AK31

AC21

AK33 AM33 AM35

AC23 AE21 AE23 AF21 AF23 AG21 AG23

AJ13 AJ15 AK15 AL13

AM23 AU15 AW16

AP27 AR15 AR23 AR25 AR27 AR29 AT13 AU23 AU25 AU27 AU29 AU35 AW34

AM21

Y19

AF37 AG37 AG39 AJ37

V50

AC33 AE33

U1800

R15 U15

U17

AR33 AU31 AU33 V13

R10

N36

M37

AM17

AC51

BF40 BD40

AM2

AW31

AB27 AB29

U19 U21 V19 V21 V23 V25 Y21 Y23

Y25

Y27

AB31

Y29 Y31

AC27 AC29 AC31 AE27 AE29 AE31

R19

AP39

AC37 AE37 AE39

R12

AA13 AB15 AC13

N18 R23 R25 U23 U25

AC15 AF15 AG13 AG15 AJ17 AK21

U27 U29

N16

AC35

AM27 N27 R27 R29 R33 R35 U33 U35

V31

AC39 AE19 AF17 AW18 AW21

C2232

1

2

C2233

1

2

C2222

1

2

C2231

1

2

C2210

1

2

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22

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22

7

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7

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7

19 22

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20

7

22

7

20 22

7

22 25

7

22

7

22

7

16 22

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7

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16 17

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7

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VSSVSS

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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NOTICE OF PROPRIETARY PROPERTY:

PAGE

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PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

OMIT_TABLE

QP8D-MM915462

PCH-PPT-MB-SFF-ES1

BGA

PCH-PPT-MB-SFF-ES1

OMIT_TABLE

QP8D-MM915462

BGA

SYNC_MASTER=J30_MLB

SYNC_DATE=07/27/2011

PCH GROUNDS

U1800

AA7 AA9

AB25

AP25 AP29 AP31 AP33 AP35 AP37 AP41 AP43 AP45 AP48

AB33

AP50 AR6 AR8 AR17 AR19 AR21 AR31 AR35 AR37 AT7

AB35

AT9 AT11 AT39 AT41 AT43 AT45 AU17 AU37 AV2 AV4

AB37

AV48 AV50 AW7 AW9 AW11 AW13 AW23 AW25 AW27 AW29

AB48

AW36 AW39 AW41 AW43 AW45 AY10 B6 B10 B14 B18

AB50

B22 B26 B30 B34 B38 B42 B46 BA7 BA9 BA11

AC7

BA13 BA16 BA18 BA21 BA23 BA25 BA27 BA29 BA31 BA34

AC9

BA36 BA39 BA41 BA43 BA45 BB2 BB4 BB48 BB50 BC11

AC11

BC13 BC16 BC18 BC21

AC17

AA11

AC25 AC41 AC43 AC45

AE7

AE9 AE11 AE13 AE15 AE17

AA39

AE25 AE35 AE41 AE43 AE45

AF2

AF4

AF8 AF19 AF25

AA41

AF27 AF29 AF31 AF35 AF48 AF50

AG7

AG9 AG11 AG17

AA43

AG19 AG29 AG31 AG35 AG41 AG43 AG45

AH2

AJ7

AJ9

AA45

AJ11 AJ19 AJ33 AJ35 AJ39 AJ41 AJ43 AJ45

AK2

AK4

AB2

AK17 AK19 AK23 AK25 AK27 AK35 AK37 AK48 AK50

AL7

AB4

AL9 AL11 AL39 AL41 AL43 AL45 AM15 AM19 AM25 AM29

AB17

AM31 AM37

AP2 AP4 AP7 AP9 AP11 AP17 AP21 AP23

U1800

BC23 BC25 BC27 BC29 BC31 BC34 BC36 BC39 BC41 BC43 BC45 BD15 BD24

BE7

BE9 BE11 BE13 BE16 BE18 BE21 BE23 BE25 BE27 BE29 BE31 BE34 BE36 BE39 BE41 BE43 BE45

BF2

BF4 BF15 BF24 BF48 BF50

BH6 BH10 BH14 BH18 BH22 BH26 BH28 BH30 BH32 BH34 BH38 BH42 BH44 BH46 BH48 BK10 BK14 BK18 BK22 BK26 BK30 BK32 BK34 BK38 BK42 BK46

D6 D10 D14 D18 D22 D26 D30 D34 D38 D42 D46

F2

F4 F48 F50

G7

G9 G11 G13 G16 G18 G21 G23 G25 G27 G29 G31 G34 G36

G39 G41 G43 J7 J9 J11 J13 J16 J18 J21 J23 J25 J27 J29 J31 J34 J36 J39 J41 J45 K2 K4 K48 K50 L7 L9 L11 L13 L16 L18 L21 L23 L25 L27 L29 L31 L34 L36 L39 L41 L43 L45 N7 N9 N11 N13 N21 N23 N25 N29 N31 N34 N39 N41 N43 N45 P2 P4 P48 P50 R17 R21 R31 R37 T7 T9 T11 T13 T41 T43 T45 U31 U49 V2 V4 V7 V9 V11 V15 V17 V27 V29 V33 V35 V41 V43 V45 V48 Y15 Y17 Y33 Y35 Y37

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Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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PAGE

12

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PAGE TITLE

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DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

68 mA

(PCH Reference for 5V Tolerance on PCI)

(PCH USB 1.05V PWR)

(PCH SUSPEND USB 3.3V PWR)

PCH V5REF_SUS Filter & Follower

NEED PWR CONSTRAINT

<1 MA

PCH V5REF Filter & Follower

1 mA S0-S5

1 mA

PCH VCCIO BYPASS

PCH VCCSUSHDA BYPASS

(PCH HD Audio 3.3V/1.5V PWR)

PCH VCCSUS3_3 BYPASS

PCH VCCCORE BYPASS

(PCH 1.05V CORE PWR)

69 mA

(PCH DPLLA PWR)

PCH VCCADPLLA Filter

PCH VCCADPLLB Filter (PCH DPLLB PWR)

(PCH Reference for 5V Tolerance on USB)

NEED PWR CONSTRAINT

10%

10% 10%

10%

201

10V

PP1V05_S0_PCH_VCCCLKDMI_R

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM VOLTAGE=1.05V

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM VOLTAGE=1.05V MAKE_BASE=TRUE

PP1V05_S0_PCH_VCCCLKDMI_F

PP3V3_S0_PCH_VCCA_DAC_F

MAKE_BASE=TRUE MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

PP1V05_S0_PCH_VCCADPLLB_F

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM VOLTAGE=1.05V

=PP3V3_S0_PCH

MIN_NECK_WIDTH=0.2 MM

PP3V3_S0_PCH_VCC3_3_CLK_F

MIN_LINE_WIDTH=0.4 MM VOLTAGE=3.3V

=PP1V05_S0_PCH_VCCASW

PP3V3_S0_PCH_VCC3_3_CLK_R

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

=PP3V3_S0_PCH_VCC3_3_CLK

=PP3V3_SUS_PCH_VCCSUS_USB

=PP3V3R1V5_S0_PCH_VCCSUSHDA

=PP1V05_S0_PCH_V_PROC_IO

=PP3V3_S0_PCH_VCC3_3

=PP3V3_SUS_PCH_VCCSUS

=PP3V3_S5_PCH_VCCDSW

=PP3V3_SUS_PCH_VCCSUS

=PP1V05_S0_PCH_VCC_DMI

=PP5V_S0_PCH

=PP3V3_S0_PCH_VCCADAC

=PP1V05_S0_PCH_VCCIO

=PP5V_SUS_PCH

=PP3V3_SUS_PCH

=PP1V05_S0_PCH_VCCIO

=PP1V05_S0_PCH_VCCIO_SATA

=PP1V05_S0_PCH_VCCDIFFCLK

=PP3V3_SUS_PCH_VCC_SPI

=PP5V_SUS_PCH_V5REFSUS

MIN_LINE_WIDTH=0.4 MM VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_PCH_VCCADPLLA_F

=PP3V3_S0_PCH_VCC3_3

=PP1V05_S0_PCH_VCCSSC

=PP1V05_S0_PCH_VCC_CORE

PP5V_SUS_PCH_V5REFSUS

MIN_NECK_WIDTH=0.25MM MAKE_BASE=TRUE

VOLTAGE=5V

MIN_LINE_WIDTH=0.3MM

=PP1V8_S0_PCH_VCC_DFTERM

=PP1V05_S0_PCH

=PP3V3_S0_PCH_VCC3_3

=PP5V_S0_PCH_V5REF

MAKE_BASE=TRUE

PP5V_S0_PCH_V5REF

MIN_LINE_WIDTH=0.3MM VOLTAGE=5V

MIN_NECK_WIDTH=0.25MM

=PP3V3_S0_PCH_VCC3_3

=PP1V05_S0_PCH_VCCADPLL

=PP3V3_S0_PCH_VCC3_3

PCH DECOUPLING

SYNC_DATE=10/03/2011

SYNC_MASTER=J11_MLB

0

MF

1/20W

5%

1

5%

MF-LF

402

1/16W

10UH-0.12A-0.36OHM

0603

6.3V

20%

CERM-X5R

10UF

0402-1

PLACE_NEAR=U1800.V37:2.54mm

X5R 402

1UF

6.3V

20%

0201

X5R

1UF

PLACE_NEAR=U1800.AW16:2.54mm

PLACE_NEAR=U1800.AB19:2.54mm

0201

X5R-CERM

0.1UF

16V

PLACE_NEAR=U1800.BD40:2.54MM

0.1UF

0201

16V X5R-CERM

6.3V

PLACE_NEAR=U1800.BD40:2.54MM

0201

X5R

20%

1UF

X5R-CERM

0.1UF

0201

16V

PLACE_NEAR=U1800.BF40:2.54MM

X5R

6.3V

1UF

20%

0201

PLACE_NEAR=U1800.BF40:2.54MM

0.1UF

X5R-CERM 0201

16V

PLACE_NEAR=U1800.T39:2.54mm

0.1UF

X5R-CERM

PLACE_NEAR=U1800.BK28:2.54mm

16V 0201

0201

PLACE_NEAR=U1800.R40:2.54mm

X5R-CERM

16V

0.1UF

PLACE_NEAR=U1800.AF6:2.54mm

0201

X5R-CERM

0.1UF

16V

CERM

20%

0.1UF

PLACE_NEAR=U1800.M37:2.54mm

402

1/20W

5% MF

10

SOT-363

BAT54DW-X-G

PLACE_NEAR=U1800.N36:2.54mm

X5R

1UF

402

100

MF

5%

1/20W

SOT-363

BAT54DW-X-G

0

MF

1/20W

5%

0402-2

10UF

20%

6.3V

CERM-X5R

PLACE_NEAR=U1800.U51:2.54mm PLACE_NEAR=U1800.U51:2.54mm

0.1UF

X5R-CERM

16V

0201

X5R-CERM

16V

0201

0.01UF

PLACE_NEAR=U1800.U51:2.54mm

10UH-0.12A-0.36OHM

0603

CERM-X5R

PLACE_NEAR=U1800.AP39:2.54mm

0402-2

10UF

6.3V

20%

PLACE_NEAR=U1800.AJ17:2.54mm

6.3V

20%

0201

X5R

1UF

6.3V

1UF

20%

0201

X5R

PLACE_NEAR=U1800.U27:2.54mm

PLACE_NEAR=U1800.AC37:2.54mm

6.3V 0201

X5R

1UF

20%

PLACE_NEAR=U1800.AB15:2.54mm

6.3V

20%

0201

X5R

1UF

6.3V

20%

0201

X5R

1UF

PLACE_NEAR=U1800.AC35:2.54mm

PLACE_NEAR=U1800.AG13:2.54mm

6.3V

20%

0201

X5R

1UF

PLACE_NEAR=U1800.R33:2.54mm

1UF

X5R 0201

20%

6.3V

0201

X5R

20%

6.3V

PLACE_NEAR=U1800.AM23:2.54mm

1UF

0201

16V

X5R-CERM

0.1UF

PLACE_NEAR=U1800.R12:2.54mm

X5R 0201

6.3V

1UF

20%

PLACE_NEAR=U1800.Y19:2.54mm

0201

16V

PLACE_NEAR=U1800.R27:2.54mm

0.1UF

X5R-CERM

20%

6.3V X5R 402

4.7UF

PLACE_NEAR=U1800.AM17:2.54mm

X5R-CERM

PLACE_NEAR=U1800.AM17:2.54mm

16V 0201

0.1UF

PLACE_NEAR=U1800.N27:2.54mm

16V 0201

X5R-CERM

0.1UF

PLACE_NEAR=U1800.AM17:2.54mm

0201

16V X5R-CERM

16V 0201

X5R-CERM

0.1UF

PLACE_NEAR=U1800.V31:2.54mm

X5R-CERM 0201

PLACE_NEAR=U1800.AJ13:2.54mm

0.1UF

16V

PLACE_NEAR=U1800.AB21:2.54mm

0201

1UF

X5R

20%

6.3V

PLACE_NEAR=U1800.AB21:2.54mm

1UF

X5R 0201

20%

6.3V

PLACE_NEAR=U1800.AB21:2.54mm

1UF

X5R 0201

20%

6.3V

PLACE_NEAR=U1800.AB21:2.54mm

0402-2

CERM-X5R

6.3V

20%

10UF

1UF

X5R

PLACE_NEAR=U1800.AR25:2.54mm

0201

20%

6.3V 6.3V

PLACE_NEAR=U1800.AU25:2.54mm

X5R 0201

1UF

20%

PLACE_NEAR=U1800.AR29:2.54mm

6.3V

1UF

20%

0201

X5R

PLACE_NEAR=U1800.AU29:2.54mm

6.3V

20%

0201

X5R

1UF

PLACE_NEAR=U1800.AU27:2.54mm

10UF

0402-2

20%

6.3V

CERM-X5R

PLACE_NEAR=U1800.AB27:2.54mm

1UF

X5R

20%

6.3V 0201

PLACE_NEAR=U1800.AB27:2.54mm

X5R

20%

6.3V

1UF

0201

PLACE_NEAR=U1800.AB27:2.54mm

1UF

X5R 0201

20%

6.3V

PLACE_NEAR=U1800.AB27:2.54mm

22UF

20%

6.3V

X5R-CERM1

0603

22UF

PLACE_NEAR=U1800.AB27:2.54mm

20%

0603

X5R-CERM1

6.3V

402

1/16W MF-LF

0

5%

MF-LF

0

402

5%

1/16W

R2460

12

R2465

12

C2420

1

2

C2428

1

2

C2496

1

2

C2456

1

2

C2426

1

2

C2401

1

2

C2463

1

2

C2407

1

2

C2414

1

2

C2429

1

2

C2460

1

2

C2483

1

2

C2482

1

2

C2481

1

2

C2440

1

2

C2441

1

2

C2430

1

2

C2413

1

2

C2417

1

2

C2416

1

2

C2484

1

2

C2442

1

2

C2499

1

2

C2419

1

2

C2476

1

2

C2452

1

2

C2475

1

2

C2444

1

2

C2434

1

2

C2446

1

2

C2469

1

2

C2411

1

2

L2406

12

C2455

1

2

C2451

1

2

C2450

1

2

R2450

12

D2400

1

6

R2405

12

C2439

1

2

D2400

4

3

R2404

12

C2438

1

2

C2423

1

2

C2485

1

2

C2421

1

2

C2424

1

2

C2461

1

2

C2402

1

2

C2466

1

2

C2465

1

2

C2422

1

2

C2418

1

2

C2486

1

2

C2453

1

2

L2451

12

R2451

12

R2415

12

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22 20

7

22 20

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7

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16

7

20 16

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20

22 20

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20

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Apple A1466 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual