Apple A1226 Schematic

ANGLES
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
DATE
APPD
ENG
DATE
APPD
CK
ECN
ZONE
REV
X.XXX
X.XX
XX
DIMENSIONS ARE IN MILLIMETERS
THIRD ANGLE PROJECTION
D
SIZE
APPLICABLE
NOTED AS
MATERIAL/FINISH
NONE
SCALE
DESIGNER
MFG APPD
DESIGN CK
RELEASE
QA APPD
ENG APPD
DRAFTER
METRIC
OF
SHT
DRAWING NUMBER
TITLE
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
Apple Computer Inc.
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
DESCRIPTION OF CHANGE
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
DESCRIPTION
REFERENCE DES
BOM OPTION
QTY
PART NUMBER
CRITICAL
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_HEAD
DRAWING
SCHEM,MLB,MBP15
Schematic / PCB #’s
04/24/2007
051-7225
1
? ??
??
88
A.0.0
TITLE=MLB
ABBREV=DRAWING
Page
Date
(.csa)
Contents Sync
820-2101
1
PCB
CRITICAL
Page Contents
Date
Sync
(.csa)
45
SMC
49
01/17/2007
T9_NOME
1
N/A
1 N/A
Table of Contents
1
051-7225 CRITICAL
SCH
46
SMC Support
50
(MASTER)
(MASTER)
47
LPC+ Debug Connector
51
03/19/2007
M76_MLB
48
SMBus Connections
52
(MASTER)
(MASTER)
49
Current & Voltage Sensing
53
(MASTER)
(MASTER)
50
Current Sensing
54
(MASTER)
(MASTER)
51
Thermal Sensors
55
(MASTER)
(MASTER)
52
Fan Connectors
56
03/19/2007
M76_MLB
53
ALS Support
58
03/19/2007
M76_MLB
54
Sudden Motion Sensor (SMS)
59
03/19/2007
M76_MLB
55
SPI BootROM
61
03/16/2007
T9_NOME
56
PBus-In & Battery Connectors
69
09/09/2006
(M59_SYNC)
57
Power FETs
70
03/19/2007
M76_MLB
58
IMVP6 CPU VCore Regulator
71
01/23/2007
M76_MLB
59
IMVP6 NB Gfx Core Regulator
72
03/19/2007
M76_MLB
60
5V / 3.3V Power Supply
73
03/19/2007
M76_MLB
61
1.25V / 1.05V Power Supply
74
03/12/2007
M76_MLB
62
1.8V DDR2 Supply
75
03/19/2007
M76_MLB
63
1.5V Power Supply
76
03/12/2007
M76_MLB
64
FW PHY Power Supplies
77
03/19/2007
M76_MLB
65
3.425V G3Hot Supply & Power Control
78
(MASTER)
(MASTER)
66
NV G84M PCI-E
80
(MASTER)
(MASTER)
67
NV G84M Core/FB Power
81
(MASTER)
(MASTER)
68
NV G84M Frame Buffer I/F
82
(MASTER)
(MASTER)
69
GDDR3 Frame Buffer A
84
(MASTER)
(MASTER)
70
GDDR3 Frame Buffer B
85
(MASTER)
(MASTER)
71
NV G84M GPIO/MIO/Misc
86
(MASTER)
(MASTER)
72
GPU Straps
87
(MASTER)
(MASTER)
73
NV G84M Video Interfaces
88
(MASTER)
(MASTER)
74
GPU (G84M) Core Supply
89
(MASTER)
(MASTER)
75
LVDS Display Connector
90
(MASTER)
(MASTER)
76
DVI Display Connector
94
(MASTER)
(MASTER)
77
LVDS Interface Mux
95
(MASTER)
(MASTER)
78
Project Specific Connectors
96
08/24/2006
(M59_SYNC)
79
CPU/FSB Constraints
100
01/17/2007
T9_NOME
80
NB Constraints
101
01/17/2007
T9_NOME
81
Memory Constraints
102
01/17/2007
T9_NOME
82
SB Constraints (1 of 2)
103
01/17/2007
T9_NOME
83
SB Constraints (2 of 2)
104
01/17/2007
T9_NOME
84
Clock & SMC Constraints
105
01/17/2007
T9_NOME
85
FireWire Constraints
106
01/17/2007
T9_NOME
86
GPU (G84M) Constraints
107
(MASTER)
(MASTER)
87
Project Specific Constraints
108
(MASTER)
(MASTER)
88
PCB Rule Definitions
109
(MASTER)
(MASTER)
2
(T9_MLB)
2
08/23/2006
System Block Diagram
3
(T9_MLB)
3
08/23/2006
Power Block Diagram
4
N/A
4 N/A
Power Block Diagram
5
N/A
5 N/A
BOM Configuration
6
N/A
6 N/A
Revision History
7
(MASTER)
7
(MASTER)
Functional / ICT Test
8
(MASTER)
8
(MASTER)
Power Aliases
9
(T9_MLB)
9
08/23/2006
Signal Aliases
10
T9_NOME
10
03/16/2007
CPU FSB
11
T9_NOME
11
03/16/2007
CPU Power & Ground
12
M76_MLB
12
03/19/2007
CPU Decoupling & VID
13
T9_NOME
13
12/12/2006
eXtended Debug Port (XDP)
14
T9_NOME
14
03/16/2007
NB CPU Interface
15
T9_NOME
15
03/16/2007
NB PEG / Video Interfaces
16
T9_NOME
16
03/16/2007
NB Misc Interfaces
17
T9_NOME
17
03/16/2007
18
T9_NOME
18
03/16/2007
NB Power 1
19
T9_NOME
19
03/16/2007
20
T9_NOME
20
03/16/2007
21
T9_NOME
21
01/17/2007
M76_MLB
22
03/12/2007
23
T9_NOME
23
03/16/2007
SB Enet, Disk, FSB, LPC
24
T9_NOME
24
03/16/2007
SB PCI, PCIe, DMI, USB
25
T9_NOME
25
03/16/2007
SB Pwr Mgt, GPIO, Clink
26
T9_NOME
26
03/16/2007
SB Power & Ground
27
T9_NOME
27
01/17/2007
SB Decoupling
28
(T9_MLB)
28
08/24/2006
SB Misc
29
T9_NOME
29
03/16/2007
Clock (CK505)
30
(MASTER)
30
08/23/2006
Clock Termination
31
(M59_SYNC)
31
08/24/2006
DDR2 SO-DIMM Connector A
32
(M59_SYNC)
32
08/24/2006
DDR2 SO-DIMM Connector B
33
(T9_NOME)
33
11/14/2006
Memory Active Termination
34
(M59_SYNC)
34
08/24/2006
Left I/O Board Connector
35
T9_NOME
37
03/16/2007
Ethernet (Yukon)
36
T9_NOME
38
03/16/2007
Yukon Power Control
37
M76_MLB
39
03/19/2007
Ethernet Connector
38
M76_MLB
40
03/19/2007
FireWire Link (TSB83AA22)
39
M76_MLB
41
03/19/2007
FireWire PHY (TSB83AA22)
40
M76_MLB
42
03/19/2007
FireWire Port Power
41
M76_MLB
43
03/19/2007
FireWire Ports
42
(MASTER)
44
(MASTER)
PATA Connector
43
M76_MLB
46
03/19/2007
External USB Connector
44
M76_MLB
47
03/19/2007
Left Clutch Barrel Interconnect
NB DDR2 Interfaces
NB Power 2 NB Grounds NB Standard Decoupling NB Graphics Decoupling
22
SCHEM,MLB,MBP15
PCBF,MLB,MBP15
SCHEM,MLB,MBP15
LAST_MODIFIED=Tue Apr 24 17:23:54 2007
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
Pg 15
Pg 17,18,19
Pg 77
Pg 79,81
3.3 V
100 MHz
J4400
Pg 35
DVI-I
MUX
GPIO
Conn
Int Disp
Pg 78
U1000
Pg 10
2.? GHz
CPU
Pg 9
Core ~1.2V
ITP/XDP CONN
J1300/JD000
Pg 28
TERMS Pg 29
UC500
Clocks
Pg 98
CK 505
U2900
Pg 98
Clocks
Pg 13
U1400
PCI-E
Pg 14
J8000
FSB
64-Bit
800/1066? MHz
SDVO
x16 PCI-E
Main Memory
Misc
Parallel
Term
Pg 32
NB-GMCH
Core
DMI
Pg 15
CLnk 0
Pg 15
DDR2 - Dual Channel
1.8V - 64 Bits
J3100 J3200
DIMM
Pg 15/16
TV
Out
RGB
LVDS
Pg 14
x4 DMI
2.5 GHz
J9200
J9200 Source is the LVDS from the PEG based GPU.
MUX
Pg 80
GPIO
J4510/20/30
1.2 V / 1.5 GHz
SATA Conn
Pg 43
UATA Conn
Pg 42
JB200 JB300 JB400
PCI-E Conns
Pg 93/4/5
UB100
6 - x1
2.5 GHz
PCI-E
Pg 92
MUX
DMI
Pg 23
CLnk 0
Pg 24
SPI
Pg 23
6 7 8 951 2 3 4
Core
Pg 25
E-NET
Pg 22
CLnk 1
Pg 24
PCI
Pg 23
AZALIA
USB
Pg 23
Pg 22
DIMM’s
Clk Gen J3100 J3200
U2900 UC500
U6100/50
SPI
Boot ROM
Pg 58
A
B,0 BSA BSB
ADC
Fan
Ser Prt
SMC
U4900
Pg 46
U6000
TPM
Pg 57
J5100
LPC Conn
Pg 48
Fan Conn Pg 53, 54
J6900/50
Pg 66
Power
Temp Sense
Charger
Right Side
GPU
CPU
Linda Fnc
Prt 80, Comm 1, SMC, FWH
J4630
USB
Pg 44
J4710
Camera/IR
Pg 45
J4720
Bluetooth
Pg 45
J4700
Geyser
Pg 45
MDC
Pg ??
U????U6200
Audio Codec
Pg 59
U6300/1
U6400 U6500
U6600/10/20
Line In
Amp
Pg 60
Line Out
Pg 61
Amp 1
Line Out
Amp 2
Pg 62
Speaker
Amps
Pg 63
Conns
Audio
Pg 65
J3400
Pg 33
AirPort
JB500
PCI-E
Conn
U3700
NINEVEH
E-NET
Pg 37
Conn
E-NET
J4630
33 MHz 32-Bit
U4000
TSB82AA2
Pg 38
FW-Link
U4100
TSB81BA3
Pg 39
FW-PHY
J4320 J4330
FireWire
Conn
Pg 41
JB000
PCI
Conn
Pg 91
100 MHz
8-Bit
Ln1 Ln2 Ln3 Ln4 Ln5 Ln6
Pg 22
UATA
PCI-E
Pg 23
SATA-0 SATA-1 SATA-2
SATA
Pg 22
U2300
SB-ICH8
Core 1.05V
Pg 22Pg 24
GPIOsSMB LPC
Pg 24
Pg 51 Pg 52 Pg 52 Pg ??
ReGen
TERMS
J5810/20/90 ALS SENS Pg 55
U5920 Sudden Motion Detect Pg 56
Pg30,31
533/667/800? MHz
1.05 - 1.25V
PEG Connector
Conn
Pg 68-76
Supply
DC/Batt
U5500 U5550 U???
U5572
Power Sense Pg 51, 115-120
J5600/10/50/60, J5720/30/50
Pg 124-130
Pg 12/103
Pg 96
J4600
J6800/1/2/3
J9400
U9120
J9000/10
U9250/60
Approximate System Block Diagram
SYNC_DATE=08/23/2006
System Block Diagram
051-7225
2
88
A.0.0
SYNC_MASTER=(T9_MLB)
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
Power Block Diagram
051-7225
A.0.0
88
3
SYNC_MASTER=(T9_MLB) SYNC_DATE=08/23/2006
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
SYNC_DATE=N/A
SYNC_MASTER=N/A
4
88
A.0.0
051-7225
Power Block Diagram
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
TABLE_BOMGROUP_ITEM
BOM OPTIONS
BOM GROUP
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
DESCRIPTION
REFERENCE DES
BOM OPTION
QTY
PART NUMBER
CRITICAL
DESCRIPTION
REFERENCE DES
BOM OPTION
QTY
PART NUMBER
CRITICAL
BOM OPTIONS
BOM NAME
BOM NUMBER
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
BOM OPTIONS
BOM GROUP
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
Bar Code Labels / EEE #’s
Module Parts
IS
M75 BOM Groups
BOM Variants
337S3464
IC,MDC,SR,E1,PRQ,2.2G,35W,800FSB,4M,BGA
1
U1000 CPU_2_2GHZ
CRITICAL
337S3465
IC,MDC,SR,E1,PRQ,2.4G,35W,800FSB,4M,BGA
CPU_2_4GHZU1000
1
CRITICAL
1
IC,GPU,NV G84M,BGA
338S0388
U8000
CRITICAL
IC,NB,CRESTLINE,GM,C0,PRQ,965PM
338S0432
1
CRITICAL
U1400
IC,ISL9504,SYNC REG CTRL,2PHAS,QFN48,LF
353S1461 ISL9504A
1
U7100
CRITICAL
IC,ISL9504B,2PH IMVP6 REG,PMON,QFN48
ISL9504B353S1651
1
CRITICAL
IC,68 PIN,CK505,LOW POWER CLOCK GENER
SLG8LP537
CRITICAL359S0127
1
IC,SLG2AP101,LW PWR CLCK GEN,CK505,QFN68
SLG2AP101
1
CRITICAL
U2900
359S0130
IC,88E8058,GIGABIT ENET XCVR,64P QFN
CRITICAL
1
U3700
338S0386
IC,SMC,HS8/2116
338S0274 CRITICAL
SMC_BLANK
1
IC,16MBIT 8-PIN SPI SERIAL FLASH,SOIC8
1
335S0384
U6100
BOOTROM_BLANK
CRITICAL
341S2002 CRITICAL
1
BOOTROM_PROG
U6100
IC,EFI ROM,DEVELOPMENT,M75
VRAM_128_SAMSUNG
IC,SGRAM,GDDR3,8Mx32,700MHZ,136 FBGA
4
U8400,U8450,U8500,U8550
333S0404
IC,SGRAM,GDDR3,8Mx32,700MHZ,136 FBGA
VRAM_128_HYNIX
CRITICAL
4
U8400,U8450,U8500,U8550
333S0409
IC,SGRAM,GDDR3,16Mx32,700MHZ,136 FBGA
VRAM_256_HYNIX
U8400,U8450,U8500,U8550
4
CRITICAL333S0401
M75_COMMON1
BOOTROM_PROG,SMC_PROG
M75_PROGPARTS
630-7931
M75_COMMON,EEE_X5D,CPU_2_2GHZ,FB_128_SAMSUNG
152S0276
ALL
152S0476
Inductor alternate
IC,SGRAM,GDDR3,16Mx32,700MHZ,136 FBGA
VRAM_256_SAMSUNG
U8400,U8450,U8500,U8550
4
CRITICAL333S0382
IC,SMC,DEVELOPMENT,M75
U4900
1
SMC_PROG
CRITICAL341S2004
338S0434
IC,SB,ICH8M,B1,PRQ,BGA
CRITICAL
1
U2300
630-7932
M75_COMMON,EEE_X5E,CPU_2_4GHZ,FB_256_SAMSUNG
630-8662
M75_COMMON,EEE_XXT,CPU_2_4GHZ,FB_256_HYNIX
[EEE:X5D]
CRITICAL
EEE_X5D
826-4393
1
ALL
138S0602
Murata alt to Samsung
138S0603
ALL TI alt to National
353S1681 353S1294
ALL
157S0011
E&E alt to TDK/BI-Tech magnetics
157S0030
630-8659
M75_COMMON,EEE_XXS,CPU_2_2GHZ,FB_128_HYNIX
VRAM_256,VRAM_SAMSUNG,VRAM_256_SAMSUNG
VRAM_256,VRAM_HYNIX,VRAM_256_HYNIX
[EEE:X5E]
826-4393
EEE_X5E
CRITICAL
1
1
826-4393 CRITICAL
[EEE:XXT]
EEE_XXT
CRITICAL826-4393
1
[EEE:XXS]
EEE_XXS
VRAM_128,VRAM_HYNIX,VRAM_128_HYNIX
VRAM_128,VRAM_SAMSUNG,VRAM_128_SAMSUNG
M75_COMMON
M75_DEBUG
SMC_DEBUG_NO,XDP,LPCPLUS
SYNC_DATE=N/A
051-7225
A.0.0
88
5
SYNC_MASTER=N/A
BOM Configuration
ALTERNATE,COMMON,M75_COMMON1,M75_COMMON2,M75_DEBUG,M75_PROGPARTS
M75_COMMON2
P1V8S3_1V825,SLG2AP101,SMS_MOT_DIS,YUKON_ULTRA,VGA_TERM_CONN
EXTGPU_RST_HW,ISL9504B,LVDS_SEL_RESUME,ONEWIRE_PU
PCBA,2.4GHZ,256SAM_VRAM,M75,MBP15
PCBA,2.2GHZ,128SAM_VRAM,M75,MBP15
PCBA,2.2GHZ,128HY_VRAM,M75,MBP15 PCBA,2.4GHZ,256HY_VRAM,M75,MBP15
CRITICAL
U4900
U2900
U7100
LBL,P/N LABEL,PCB,28MM X 6 MM
LBL,P/N LABEL,PCB,28MM X 6 MM
LBL,P/N LABEL,PCB,28MM X 6 MM
LBL,P/N LABEL,PCB,28MM X 6 MM
FB_256_HYNIX
FB_256_SAMSUNG
FB_128_HYNIX
FB_128_SAMSUNG
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
04/24/07 -- SMC Support: Changed R5031 to 2.37K, R5032 to 9.09K to meet SIL brightness targets
04/18/07 -- Modules: Updated Intel chipset to PRQ parts
16.3.0: 04/20/07 -- Power FETs: Changed R7097 to 220K to maintain EnergyStar compliance with FET gate pulled to PBUS 04/20/07 -- Power FETs: Changed C7095/C7083 to 16V for proper rating of parts tied to PBUS 04/20/07 -- CPU VCore: Changed C7196 to 16V to eliminate a BOM item
See Perforce change notes for updates before Proto Release 12/22/06 -- Released for Proto (Schem Rev 08, PCB Rev 01)
01/05/07 -- Clock Termination: Removed NO STUFF property from R3067
04/24/07 -- SB Decoupling: Changed L2700 from 155S0152 to 155S0333 for AVL updates
01/19/07 -- Power Sequencing: Changed power rail for U7850 to PP3V3_S5 to eliminate a leakage path
01/23/07 -- BOM: Changed C3860/61 to 22pF from 27 pF based on -R characterization (T9_noME change 41248)
01/24/07 -- Power Aliases: Updated PP3V3_S0 aliases to support above changes
01/25/07 -- Released for EVT (Schem Rev 11, PCB Rev 03)
02/19/07 -- Power Sequencing: NO STUFFed U7885 to remove GPU PGOOD from PWROK chain
02/20/07 -- GPU FB: Changed cal resistors per Nvidia PUN (R8290 to 45.3 ohm and R8291 to 24.9 ohm)
02/19/07 -- Released post-EVT to document what was built (Schem Rev 12)
02/19/07 -- GPU PGOOD: Changed C9595 to 330pF to reduce PGOOD delay on powerup
02/19/07 -- GPU Reset: Changed C2885 to 0.047uF to reduce reset delay on powerup
02/19/07 -- Power Sequencing Rework: Short pins 2 and 4 of U7885 to complete PWROK chain
02/20/07 -- GPU FB: Changed unterminated-mode reference voltage to 40% (R8297 -> 1.02K, R8432/82, R8532/82 -> 2.21K)
02/26/07 -- GPU Vcore: NO STUFFed all PWRCTL related components (feature not to be supported)
02/26/07 -- SB GPIOs: Sync’d page25.csa to T9_MLB to get pullup updates
02/28/07 -- Power Aliases: Moving PP1V8_GPU FET source to PP1V8_S3 rather than PP1V8_S3_ISNS to improve power delivery to GPU (rdar://5021462)
02/28/07 -- NB GFX Core: Changed Vcore controller to ISL6263B (part consolidation effort between Apple/Intersil - rdar://5009109)
03/01/07 -- Thermal Sensors: Updated topology of EMC1033 sensors (removed shorts, changed connector caps to 18pF)
03/01/07 -- LVDS Connector: Changed pin 5 of connector from NC to PP3V3_SW_LCD (in case we add extra cable for power - rdar://5024882)
03/02/07 -- Power/Signal Aliases: Added XW0900 to PP5V_S5 to enable layout improvements
03/06/07 -- FireWire Ports: Changed D4260 to PDS340 for lower height
03/06/07 -- Ethernet Connector: Removed RX shorts on Ethernet MDI lines per EMC request
17.0.0:
01/22/07 -- BOM: Selected P1V8S3_1V825 BOMOPTION to lift voltage at FB memories
01/23/07 -- BOM: Changed FB memories to new Samsung and Hynix APNs (also added new BOMOPTIONs to GPU straps)
01/24/07 -- PATA Conn: Added pass FET Q4430 to allow PCIREQ3 (ODD reset GPIO) to pullup to S0
01/25/07 -- PATA Conn: Replaced PCIREQ pass FET with OD buffer to correct a corner case during PLTRST
01/25/07 -- BOM: Updated gain of PP1V25_ENET current sense amplifier to 165 (R5432 to 165K)
01/25/07 -- Power Aliases: Updated PP5V_S0 aliases to support above changes
01/23/07 -- Released for EVT (Schem Rev 10, PCB Rev 02)
01/22/07 -- BOM: Added BOMOPTIONs for SLG2AP101 (primary) and SLG8LP537 (backup)
01/22/07 -- Clock Termination: Added R3051 for Silego 537/101 compatibility
01/24/07 -- PATA Conn: Changed =PP5V_S0_ODDPWREN to =PP3V3_S0_ODDPWREN for minor power savings
02/26/07 -- Thermal Sensors: Updated topology of EMC1033 filter caps (added C5515 next to IC, moved other caps to connectors - rdar://5025773)
02/28/07 -- Left Clutch IC: Updated both I-PEX connectors to new APN (part update for shell plating)
03/01/07 -- NB GFX Decoupling/Power Aliases: Connected VCCD_CRT of NB to GND per CRT disable guidelines
03/06/07 -- SB GPIOs: Changed R2514 from pulldown to pullup to correct auto power-on issue (Linda card detect GPIO)
01/17/07 -- BOM: Consolidated 3 caps on page 59 from 132S0120 to 132S0131
01/17/07 -- Testpoints: Removed FUNC_TEST from NB_RESET_L and FSB_DPWR_L per PCB request
01/17/07 -- Power FETs: Corrected BOM values for 5V/3.3V S3/S0 FETs
04/03/07 -- GPU FB: Changed FB clock termination to 242 ohms (2x121) per Nvidia PUN
03/30/07 -- SIL: Changed R5031 to 2.21K and R5032 to 9.53K to raise SIL current approx 15% (lightpipe dimmed by 20%)
03/19/07 -- Power Supplies: For 1.8, 3.3 and 5V, increased cap size to 0603/0805 on VBST caps (rdar://5070179)
03/19/07 -- Power Control: Tied all 4 5V/3.3V enables (EN1, EN2, EN3, EN5) together as part of PM_G2_EN
03/20/07 -- GPU Vcore: Updated setpoints for GPU Vcore based upon Nvidia Vmin (i.e. 1.05V,1.05V,1.05V,1.125V) 03/20/07 -- FB: Changed FB VREF caps to 2x0.0047uF as required in Nvidia PUN 02736-001-v07 (which requests 1x0.01uF)
15.0.0:
03/30/07 -- Power Supply: Changed 1.05V power supply current limit to 10A from 8A (R7455 to 5.62k -- rdar://5095642) 04/03/07 -- Power Supply: Changed numerous 10K Rs to 100K for Energy Star compliance (rdar://5102118)
04/03/07 -- Released for DVT (BOM update)
04/17/07 -- Power Sequencing: NO STUFFED U7858 and stuffed R7860 to allow SMC to drive S5 enable pins directly 04/17/07 -- Released for DVT (As-Built)
04/18/07 -- GPU Misc: Added R8735-37 to implement PCI DEVID 0x407 in hardware
16.1.0:
PVT
14.0.0:
01/09/07 -- Temp Sensors: NO STUFFed C5520 (circuit should have only 1 cap)
01/12/07 -- Power Supplies: Minor power supply feedback connection changes from M76
PROTO
DVT
01/19/07 -- Power Sequencing: Added C7859 to create RC delay for 1.5 and 1.05V S0 rails
01/19/07 -- GPU GPIOs: Added 2 TPs on GPIOs to make G-state externally visible
01/22/07 -- LIO Conn: Removed unnecessary aliases as T9 reference design now matches M75 (T9_noME change 40998)
03/01/07 -- NB GFX Decoupling: Added R2260 (0.3 ohm, 0603) to bring ESR of regulator output cap in spec (rdar://5000272)
03/12/07 -- Power Control: Corrected alias connections for 5V/3V3 S5 enable signals
13.1.0: 03/13/07 -- BOM Options: Removed HDCP BOM option from stuffing list (feature removed)
03/06/07 -- FireWire Ports: Changed D4260 to PDS540 for higher current capacity
01/25/07 -- BOM: Updated all Intel APNs to use QS parts
12.1.0:
12.0.0:
12.6.0: 03/06/07 -- Power FETs: Changed Q7080 to RJK0301 which provides much lower Rds(on)
12.4.0:
12.3.0:
01/17/07 -- SMBus: Changed R5260 & R5261 from 4.7K to 3.3K
EVT_SE
11.0.0:
10.2.0:
EVT
9.5.0:
9.2.0:
9.4.0:
9.3.0:
8.1.0:
10.1.0:
9.1.0:
12.2.0:
12.5.0:
9.0.0:
8.2.0:
12.7.0:
02/28/07 -- Power Supplies: Replaced APN 152S0511 with 152S0368 (duplicate APNs for same part - rdar://5009109)
02/21/07 -- Power Sequencing: Removed U7885/C7885 to take GFX_PGOOD out of PWR_OK chain (rdar://4974927)
03/06/07 -- DDR2 Regulator: Changed FB resistors to 0.1% to raise guaranteed lowest output voltage
13.0.0:
10.0.0:
13.3.0:
02/27/07 -- ODD Conn: Changed ODD power FET to FDC606P (from FDC638P) for reduced Rds(on) (rdar://4993378)
02/26/07 -- GPU Vcore: Updated voltage setpoints to 1.000/1.070/1.125V (rdar://5021453)
02/21/07 -- FireWire: Changed to Rev C of TI FireWire MCM (APN: 338S0435)
01/22/07 -- Clocks: Changed U2900 to SLG2AP101 as primary clock chip (T9_noME change 40975)
01/19/07 -- SB GPIOs: Changed SB_GPIO42 to WOW_EN and changed pullup to pulldown (T9_noME change 40787)
01/19/07 -- Clock Termination: Changed R3050 and R3055 to bypass discrete muxes for pending change to SLG2AP101
01/19/07 -- Ethernet Conn: Changed resistor short reference designators from R392x to RX392x
01/19/07 -- SB Decoupling: Removed filtering for PP1V5_S0_SB_VCCGLANPLL to enable PP1V5_S0 corrections at SB
01/18/07 -- ODD Conn: Reconnected ODD power FET gate control circuitry to properly implement soft start (added one cap)
01/18/07 -- IMVP: Updated BOMOPTIONs and values for ISL9504B
01/18/07 -- Clock Termination: Changed series termination on all single ended clocks to 33 ohms
13.4.0:
13.5.0:
03/19/07 -- Power Supplies: For 1.8, 3.3 and 5V, removed VBST 0-ohm series R (rdar://5070179)
03/19/07 -- Power Control: Added U7858 to level shift PM_G2_EN from 3.42V to 5V
03/19/07 -- Thermal Sensors: Updated U5500 power alias to indicate device should be on S3 rail
03/16/07 -- Thermal Sensors: Moved remote sensor U5500 to SMC SMBus "A" and S3 power rail to clear I2C addr clash
03/16/07 -- Yukon Power Control: Crystal caps changed to 18pF (rdar://4946795 and rdar://4945362)
03/16/07 -- NB GFX: LVDS_VREFL/VREFH changed to single pin nets to prevent LVDS glitches per Intel
03/16/07 -- Thermal Sensors: Replaced EMC1033 with second EMC1043 for improved noise filtering
03/14/07 -- Constraints: Constrained WWAN_SIM signals to 50 ohms 03/14/07 -- Thermal Sensors/Aliases: Changed mounting pads of Th2H sensor connector to left clutch chassis gnd
13.2.0:
01/08/07 -- GPU FB: Added VREF support for unterminated memory mode (added FETs and pulldown Rs)
12.8.0:
DVT (cont’d)
03/08/07 -- Thermal Sensors: Added R5515/R5516 in case low pass filter is needed for EMC1033
16.0.0:
04/03/07 -- CPU Vcore: Changed R7117,C7134 and R7115,R7130 for calibration improvements (rdar://5085959)
01/18/07 -- Testpoints: Added NO_TEST property to LVDS_L_DATA_N<1>, _N<2>, _P<2> due to lack of layout space for TP
01/17/07 -- Power Aliases: Deleted alias that accidentally eliminated filtering on PP1V5_S0_SB_VCC1_5_B
01/17/07 -- BOM: Added Hynix BOM configurations
01/17/07 -- Power Sequencing: Added RC delay on PP1V8_S3 switcher enable
01/17/07 -- Sync with T9 noME (6.1.4) to pull in WOL_EN and Wake-on-Wireless support
01/17/07 -- Power Aliases: Moved LCD panel FET to PP3V3_S5 from S0
01/12/07 -- Power Aliases: Moved Ethernet to PP3V3_S3 from S5 (layout improvements)
01/05/07 -- GPU FB: Corrected FB CLK termination (added cap and removed connection to VDDQ)
16.2.0: 04/18/07 -- Power FETs: Changed Q7095 to FDM6296 and pulled up to PBUS for better PP1V25_S0 FET Rds(on)
A.0.0:
04/20/07 -- No changes. Weekly BOM release.
04/24/07 -- Released for PVT
6
88
051-7225
Revision History
SYNC_MASTER=N/A
SYNC_DATE=N/A
A.0.0
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
CPUTHMSNS can not be supported due to layout constraints
Fan Connectors
FUNC_TEST
Thermal Diode Connectors
FUNC_TEST
FUNC_TEST
LPC+ Debug Connector
FUNC_TESTFUNC_TEST
FUNC_TEST FUNC_TEST
FUNC_TEST
FUNC_TEST
FUNC_TEST
FUNC_TEST
FUNC_TEST
NO_TEST
System Validation TPs
NB NO_TESTs
6 TPs, 2 with each of above TP pairs
ICT Test Points
Functional Test Points
Left I/O Power Connector
Battery Digital Connector
Left Clutch Barrel Connector
2 TPs per
Other Func Test Points
Current Sense Calibration
RTC Battery Connector
called out separately in these notes.
NOTE: 10 additional GND test points are
Request for at least 10 GND test points
Left ALS Connector
NO_TEST
CPU FSB NO_TESTs
NO_TEST
GPU NO_TESTs
I550 I551
I552
I553
I554
7
88
A.0.0
051-7225
Functional / ICT Test
SYNC_MASTER=(MASTER)
SYNC_DATE=(MASTER)
TRUE
HSTHMSNS_D_N
TRUE
HSTHMSNS_D_P
TRUE
RSFSTHMSNS_D_P
TRUE
RSFSTHMSNS_D_N
CPUTHMSNS_D2_N
CPUTHMSNS_D2_P
FAN_LT_PWM
TRUE
FAN_LT_TACH
TRUE
TRUE
FAN_RT_PWM
CPU_DPSLP_L
TRUE
CPU_PWRGD
TRUE
=PP3V3_S3_LTALS
TRUE
ALS_GAIN
TRUE
LTALS_OUT
TRUE
DEBUG_RESET_L
TRUE
SMC_TRST_L
TRUE
SMC_TDO
TRUE
SMC_MD1
TRUE
LPC_AD<3>
TRUE
INT_SERIRQ
TRUE
PM_SUS_STAT_L
TRUE
SMC_RESET_L
TRUE
SMC_TCK
TRUE
SMC_TDI
TRUE
PM_SB_PWROK
TRUE
SB_RTC_RST_L
TRUE
PM_STPCPU_L
TRUE
PM_STPPCI_L
TRUE
VR_PWRGD_CLKEN
TRUE
VR_PWRGOOD_DELAY
TRUE
NB_CLK100M_PCIE_N
TRUE
NB_CLK100M_DPLLSS_N
TRUE
NC_NB_NC<1..16>
TRUE
TP_NB_NC<1..16>
SMC_BS_ALRT_L
TRUE
=SMBUS_BATT_SCL
TRUE
PM_CLKRUN_L
TRUE
PM_ENET_EN
TRUE
PM_S4_STATE_L
TRUE
P1V5P1V05S0_PGOOD
TRUE
CPU_DPRSTP_L
TRUE
IMVP6_VID<6..0>
TRUE
NB_CLK96M_DOT_P
TRUE
NB_CLKREQ_L
TRUE
NB_CLK100M_PCIE_P
TRUE
CPU_STPCLK_L
TRUE
SMC_LRESET_L
TRUE
GPU_RESET_L
TRUE
PLT_RST_L
TRUE
=SMBUS_BATT_SDA
TRUE
GND_BATT
TRUE
LPC_AD<0>
TRUE
FWH_INIT_L
TRUE
=PP5V_S0_FAN_LT
TRUE
ISENSE_CAL_EN
TRUE
=PPVCORE_S0_NBGFX_REG
TRUE
=PP5V_S0_ISENSECAL
TRUE
=PPVCORE_GPU_REG
TRUE
USB_CAMERA_N
TRUE
=PP5V_S3_CAMERA
TRUE
USB_CAMERA_P
TRUE
USB_WWAN_N
TRUE
=PP5V_S3_WWAN
TRUE
USB_WWAN_P
TRUE
SMC_ONOFF_L
TRUE
PM_SYSRST_L
TRUE
PM_DPRSLPVR
TRUE
PM_RSMRST_L
TRUE
FSB_CPURST_L
TRUE
IMVP_VR_ON
TRUE
PM_SLP_S3_L
TRUE
IMVP_DPRSLPVR
TRUE
PM_SLP_S5_L
TRUE
=PPBUS_G3H_LIO_CONN
TRUE
PPVBATT_G3_RTC
TRUE
NB_SB_SYNC_L
TRUE
FSB_DPWR_L
FSB_CPUSLP_L
TRUE
PCI_RST_L
TRUE
PM_LAN_ENABLE
TRUE
CPU_DPSLP_L
TRUE
=PP3V3_S5_LPCPLUS
TRUE
=PPVCORE_S0_CPU_REG
TRUE
BOOT_LPC_SPI_L
TRUE
LPC_AD<1>
TRUE
LPC_AD<2>
TRUE
PCI_CLK33M_LPCPLUS
TRUE
SMC_TX_L
TRUE
LPC_FRAME_L
TRUE
LINDACARD_GPIO
TRUE
SMC_NMI
TRUE
TRUE
FAN_RT_TACH
=PP5V_S0_LPCPLUS
TRUE
SMC_TMS
TRUE
SMC_RX_L
TRUE
NB_CLK96M_DOT_N
TRUE
CPU_THERMTRIP_R
TRUE
NB_RESET_L
FSB_CLK_NB_P
TRUE
FSB_CLK_NB_N
TRUE
NB_CLK100M_DPLLSS_P
TRUE
TRUE
FSB_LOCK_L
TRUE
FSB_REQ_L<4..0>
TRUE
FSB_HITM_L
TRUE
FSB_HIT_L
TRUE
FSB_DSTB_L_P<3..0>
TRUE
FSB_DSTB_L_N<3..0>
TRUE
FSB_DRDY_L
TRUE
FSB_DINV_L<3..0>
TRUE
FSB_DBSY_L
TRUE
FSB_D_L<63..0>
TRUE
FSB_BNR_L
TRUE
FSB_BREQ0_L
TRUE
FSB_ADSTB_L<1..0>
TRUE
FSB_ADS_L
TRUE
FSB_A_L<31..3>
TRUE
LVDS_L_DATA_N<2>
TRUE
LVDS_L_DATA_N<1>
TRUE
LVDS_L_DATA_P<2>
GND
TRUE
GND
TRUE
GND
TRUE
GND
TRUE
79
65
79
79
47
58
58
79
79
45
79
47
47
23
23
78
47
47
47
46
47
47
47
28
30
30
28
84
84
56
47
65
23
79
84
79
77
47
74
82
82
78
45
58
14
40
46
79
79
23
58
47
47
84
46
47
47
46
84
84
84
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
86
86
86
87
87
87
10
13
78
53
78
47
47
46
47
45
45
45
46
46
46
25
28
29
29
28
16
30
30
46
56
45
65
45
16
58
29
30
23
45
66
28
56
45
52
49
59
49
49
44
44
44
44
46
28
25
45
13
58
36
79
45
56
25
14
14
28
45
10
47
49
47
45
45
47
45
45
47
47
47
46
45
28
30
30
30
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
77
77
77
51
51
51
51
51
51
52
52
52
7
10
8
45
53
28
45
45
45
23
25
25
45
45
45
9
23
25
25
25
9
16
22
16
45
48
25
36
25
65
10
12
84
16
16
10
28
28
24
48
56
23
47
8
45
8
8
8
24
8
24
44
8
44
45
25
16
25
10
45
25
58
25
8
28
16
10
10
24
25
7
8
8
24
23
23
30
43
23
25
45
52
8
45
43
84
23
16
14
14
22
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
73
73
73
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
Chipset "VCore" Rails
"FW" (FireWire) Rails
"GPU" Rails
3.3V-2.5V Rails 1.8V-0.9V Rails
MAX I = 0.36A
MAX I = ?.??A
"ENET" Rails
Yukon EC will not be supported
5V Rails
"G3Hot" (Always-Present) Rails
SYNC_MASTER=(MASTER)
SYNC_DATE=(MASTER)
8
88
A.0.0
051-7225
Power Aliases
=PP3V3_S3_TOPCASE
=PP3V3_S3_LTALS
=PP3V3_S0_NB_VCCHV
=PPVCORE_GPU_REG
MIN_NECK_WIDTH=0.2 mm
PPVCORE_GPU
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 mm VOLTAGE=1.2V
=PPVCORE_GPU
=PPBUS_G3H_LIO_CONN
=PP5V_S0_ODD
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm
MAKE_BASE=TRUE
VOLTAGE=5V
PP5V_S3
=PP5V_S0_ISENSECAL
=PPVCORE_S0_NBGFX_VSEN
PPVCORE_S0_CPU
MIN_LINE_WIDTH=0.6 mm
MAKE_BASE=TRUE
VOLTAGE=1.25V
MIN_NECK_WIDTH=0.3 mm
=PP3V3_S5_SMC
=PP5V_S5_P1V05S0
=PP5V_S0_P5VS0FET
=PP5V_S0_KBDLED
=PP3V42_G3H_LIDSWITCH
=PPVIN_G3H_P3V42G3H
=PP1V25_S0M_NB_PLL
MIN_LINE_WIDTH=0.4 mm
PP3V3_GPU
MAKE_BASE=TRUE
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2 mm
=PP3V3_GPU_HDCP
=PP3V3_GPU_VCORELOGIC
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm
MAKE_BASE=TRUE
VOLTAGE=1.8V
PP1V8_GPU
=PP1V8_GPU_FBVDDQ
=PP1V8_GPU_FB_VDD
=PP5V_S5_P1V5S0
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE
PP3V3_GPU_TMDS
=PPVCORE_S0_NB_FOLLOW =PPVCORE_S0_SB
=PPVCORE_S0_NBCOREISNS
=PP1V25R1V05_S0_FSB_NB =PP1V25R1V05_S0_NB_VTT
=PP1V05_S0_SB_CPU_IO =PP1V05_S0_SMC_LS
=PP1V05_S0_NB_FOLLOW =PP1V05_S0_NB_PCIE
PP1V05_S0
VOLTAGE=1.05V MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm
=PP3V42_G3H_SMCUSBMUX
=PP3V42_G3H_LIO
=PP3V3_GPU_PWRCTL
=PP3V3_GPU_SMBUS_SMC_0_S0
=PP2V5_GPU_LTC2900
=PP3V3_GPU_VIDEOMUX
=PP3V3_GPU_TMDS
=PP3V3_GPU_VGASYNC
=PP3V3_GPU_DVI =PP3V3_GPU_LVDS_DDC
=PP1V25_S0_NB_VCCDMI
=PP1V25_S0_SB_DMI
=PP3V3_GPU_IFPCD_IOVDD
=PP1V25_GPU_FET
=PP3V3_GPU_TMDSBIAS
=PP1V25_ENET_ISNS
PP1V25_S0
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.25V MAKE_BASE=TRUE
=PP1V2_GPU_PLLVDD
=PP1V8_GPU_IFPX
=PP1V8_GPU_FBIO
=PP1V8_GPU_FB_VDDQ
=PP1V8_GPU_FET
=PP1V2_GPU_PEX_IOVDD =PP1V2_GPU_PEX_PLLXVDD
=PP3V3_S5_SB_VCCSUS3_3
=PP3V3_S5_SB_CLINK1
=PP3V3_GPU_TMDS_FET
=PP1V2_GPU_H_PLLVDD =PP1V2_GPU_VID_PLLVDD
=PP3V3_S5_REG
=PP5V_S3_FET
=PP5V_S3_WWAN
=PP3V3_S5_SB_3V3_VCCSUSHDA
=PP3V3_GPU_VDD33
=PP3V3_GPU_FET
=PPDCIN_G3H_LIO_CONN
=PP3V3_S5_SB_PM =PP3V3_S5_SB_USB =PP3V3_S5_SB
=PP3V3_S5_SB_VCCSUS3_3_USB
=PP3V3_S5_SMBUS_SB_ME
PPVP_FW
VOLTAGE=33V
MIN_NECK_WIDTH=0.3 mm
MIN_LINE_WIDTH=0.6 mm
MAKE_BASE=TRUE
VOLTAGE=1.95V MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 mm
PP1V95_FW
MIN_LINE_WIDTH=0.4 mm
PP3V3_FW
MAKE_BASE=TRUE
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm
=PPBUS_S5_FW_FET
=PPVP_FW_SUMNODE =PPVP_FW_CPS =PPVP_FW_P3V3FW
=PPVP_FW_PORT0
PPVP_FW_PORTA_UF
MAKE_BASE=TRUE
=PPVP_FW_PORT1
PPVP_FW_PORTB_UF
MAKE_BASE=TRUE
=PP3V3_FW_REG
=PP3V3_FW_PHY =PP3V3_FW_LATEVG_ACTIVE
=PPVIN_FW_P1V95FW
=PP3V3_FW_LATEVG
=PP1V95_FW_PHY
=PP1V95_FW_LDO
=PP1V8_FW_PHYOSC
=PP3V3_GPU_MIO =PP3V3_GPU_DAC
=PPBU_S0_P3V3FW
PPBUS_FW_FWPWRSW_F
MAKE_BASE=TRUE
=PP5V_S5_P1V25ENET
=PP5V_S3_RTUSB
=PP5V_S5_P1V25GPUFET
=PP5V_S5_REG
=PP5V_S3_SYSLED =PP5V_S3_CAMERA
=PP5V_S5_P1V8DDRREG
=PP5V_S3_IR
=PP3V3_S5_S5PWRGD
=PP3V3_S5_SB_GPIO
=PP1V2_GPU_PEX_IOVDDQ
=PP1V8_S3_REG
=PP1V8_S3M_MEM_A
=PP1V8_S3_FW
=PP1V8_S3M_MEM_B =PP1V8_S3_ISNS_R
=PP5V_S5_PWRCTL
PP0V9_S3_MEM_VREF
MIN_LINE_WIDTH=0.4 mm VOLTAGE=0.9V
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.9V MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm
PP0V9_S0
=PP1V5_S0_CPU
=PP1V5_S0_REG
=PP1V25_S0_FET
=PP1V25_S0M_NB_VCCA
=PP1V25_S0M_NB_VCC
=PP1V25_S0_NB_PLL =PP1V25_S0_NB_VCC
=PP1V05_S0_REG
=PP1V05_S0M_NB_VCCAXM
=PPVCORE_S0_NB_R
=PP0V9_S3M_MEM_NBVREFA
=PP0V9_S3_VTTR_BUF
=PP0V9_S3M_MEM_NBVREFB =PP0V9_S3M_MEM_DIMMVREFA =PP0V9_S3M_MEM_DIMMVREFB
=PP0V9_S0_VTT_LDO
=PP1V8_S0_FET
=PP1V8_S0_NB_LVDS
PP3V3_ENET
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.4 mm
MAKE_BASE=TRUE
=PP3V3_ENET_PHY
=PP3V3_ENET_FET
=PP3V3_ENET_AVDDLDO
VOLTAGE=1.9V
PP1V9_ENET
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm
MAKE_BASE=TRUE
=PP1V8R2V5_ENET_PHY
VOLTAGE=1.25V
MIN_LINE_WIDTH=0.6 mm
PP1V25_ENET_ISNS
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 mm
=PP1V25_S0_P1V25S0FET =PP1V25_GPU_P1V25GPUFET
PPVCORE_S0_NB_GFX
MIN_LINE_WIDTH=0.5 mm
MAKE_BASE=TRUE
VOLTAGE=1.25V
MIN_NECK_WIDTH=0.25 mm
=PPVCORE_S0_CPU
=PPVCORE_S0_CPU_REG
=PPVCORE_S0_NBGFX_REG
=PP1V2_GPU_FBPLLAVDD =PP1V2_GPU_VCOREPWRCTL
MIN_LINE_WIDTH=0.6 mm VOLTAGE=1.25V
MAKE_BASE=TRUE
PP1V25_GPU
MIN_NECK_WIDTH=0.2 mm
=PP5V_S5_P1V8S0FET
=PP5V_S5_P1V25S0FETXW
=PP5V_S5_GPUVCORE
=PP5V_S5_P1V8GPUFET
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.9V MAKE_BASE=TRUE
PPVCORE_S0_NB_R
=PPVCORE_S0_NB
=PP1V05_S0_CPU
=PP0V9_S0M_MEM_TERM
=PP1V25_ENET_ISNS_R
=PP1V2_ENET_PHY
MIN_LINE_WIDTH=0.6 mm VOLTAGE=1.25V
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 mm
PP1V25_ENET
=PPVOUT_ENET_AVDDLDO
=YUKON_EC_PP2V5_ENET
=PP3V3_S5_LPCPLUS
=PP5V_S5_SB
=PP1V25_ENET_REG
=PP5V_S3_TOPCASE
=PP5V_S3_P5VS3FET
=PP1V5_S0_SB_VCC1_5_A_ATX
=PP1V5_S0_SB_VCCUSBPLL
=PP1V5_S0_LIO
=PP1V5_S0_SB_VCC1_5_A_USB_CORE
=PP3V42_G3H_SB_RTC
=PP3V42_G3H_SMBUS_SMC_BSA
=PP3V3_S3_FW =PP3V3_S3_PCI =PP3V3_S3_SMBUS_SMC_A_S3 =PP3V3_S3_RTALS =PP3V3_S3_SMS
=PP3V3_S3_P1V25ISNS
=PP3V3_S3_SMBUS_SMC_MGMT
=PP3V3_S3_P1V8ISNS
=PP3V3_S0_NB_FOLLOW
=PP3V3_S0_FET
=PP3V3_S0_SB_GPIO =PP3V3_S0_SB_PCI =PP3V3_S0_SB_VCC3_3_IDE =PP3V3_S0_SB_VCC3_3_PCI =PP3V3R1V5_S0_SB_VCCHDA =PP3V3_S0_SB_VCC3_3_DMI =PP3V3_S0_SB_VCC3_3_VCCPCORE =PP3V3_S0_SB_VCCGLAN3_3 =PP3V3_S0_SB_VCC3_3_SATA =PP3V3_S0_SB =PP3V3_S0_SB_PM =PP3V3_S0_RSTBUF =PP3V3_S0_CK505
=PP3V3_S0_SMC
=PP3V3_S0_IDE
=PP3V3_S0_LPCPLUS =PP3V3_S0_SMBUS_SB =PP3V3_S0_SMBUS_SMC_B_S0 =PP3V3_S0_CPUCOREISNS =PP3V3_S0_NBGFXCOREISNS =PP3V3_S0_CPUTHMSNS
=PP3V3_GPU_P3V3GPUFET =PP3V3_S5_PWRCTL
VOLTAGE=3.3V
PP3V3_S5
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm
MAKE_BASE=TRUE
=PPVCORE_S0_NB_GFX
=PP5V_S0_SB
=PP5V_S0_LPCPLUS =PP5V_S0_FAN_LT =PP5V_S0_FAN_RT =PP5V_S0_CPU_IMVP
=PP5V_S0_SB_HPD =PP5V_S0_HDD
=PPBUS_S5_FWPWRSW
=PP5V_S0_DVI_DDC
=PP5V_S0_GFXIMVP6
VOLTAGE=5V
PP5V_S0
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm
MAKE_BASE=TRUE
=PP5V_S0_FET
=PP5V_S0_ODDPWREN =PP5V_S0_PCIREQFIX
=PP3V42_G3H_REG
MAKE_BASE=TRUE
VOLTAGE=1.8V
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.4 mm
PP1V8_S0
=PPVIN_S0_NB_DPLL
=PP1V8_GPU_P1V8GPUFET
VOLTAGE=1.8V
MIN_NECK_WIDTH=0.2 mm MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 mm
PP1V8_S3
=PP3V3_S0_P3V3S0FET
=PP3V3_S0_LCD
=PP3V3_S3_P3V3S3FET
=PP3V3_S5_P1V5P1V05PG
=PP3V3_S5_ROM
MIN_LINE_WIDTH=0.6 mm
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V
PP1V8_S3_ISNS
=PP1V8_S3M_NB_VCC
=PP1V8_S3_ISNS
=PP1V8_S3M_MEM_NB =PP1V8_S0_P1V8S0FET
=PP1V5_S0_NB_TVDAC =PP1V5_S0_SB =PP1V5_S0_SB_VCC1_5_A_ARX
=PP1V5_S0_SB_VCC1_5_A
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 mm
PP1V5_S0
MIN_LINE_WIDTH=0.5 mm VOLTAGE=1.5V
=PP3V3_S3_FET
=PP3V3_S3_P3V3ENETFET
=PP3V3_S3_REMTHMSNS
=PP3V3_S0_NB_VCCA_PEG_BG
MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
PP3V3_S3
MIN_LINE_WIDTH=0.6 mm
MAKE_BASE=TRUE
=PP3V3_S0_GPUTHMSNS =PP3V3_S0_FAN_LT =PP3V3_S0_FAN_RT =PP3V3_S0_IMVP =PP3V3_S0_GFXIMVP6 =PP3V3_S0_NBCOREISNS =PP3V3_S0_ALLSYSPG =PP3V3_S0_DDC_LCD =PP3V3_S0_LVDS_MUX =PP3V3R5V_GPU_GPUISENS =PP3V3_S0_XDP =PP3V3_S0M_CK505 =PP3V3_S0_GPUCLKGATE =PPSPD_S0M_MEM_A =PPSPD_S0M_MEM_B =PP3V3_S0MWOL_SB_CLINK0 =PP3V3_S0MWOL_SB_VCCCL3_3 =PP3V3_S0MWOL_SB_VCCLAN3_3 =PP3V3_S0_PWRCTL
PP3V3_S0
MIN_LINE_WIDTH=0.6 mm VOLTAGE=3.3V
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 mm
PP5V_S5
VOLTAGE=5V MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm
=PPVIN_S5_SMCVREF =PP3V42_G3H_PWRCTL
MIN_NECK_WIDTH=0.2 mm MAKE_BASE=TRUE
VOLTAGE=3.42V
PP3V42_G3H
MIN_LINE_WIDTH=0.3 mm
MIN_LINE_WIDTH=0.4 mm
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 mm VOLTAGE=18.5V
PPDCIN_G3H
=PPBUS_S5_P1V8GPUFET =PPBUS_S5_P1V25S0FET
MIN_NECK_WIDTH=0.2 mm
PPBUS_G3H
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 mm VOLTAGE=12.6V
=PPVIN_S5_CPU_IMVP_VIN
=PPVIN_S5_P5VS5
=PPVIN_S5_CPU_IMVP =PPVIN_S5_P5VP3V3
=PPVIN_S5_P3V3S5 =PPVIN_ENET_P1V25ENET
=PPVIN_S0_GFXIMVP6
=PPVIN_S3_P1V8S3 =PPVIN_S0_P1V5S0
=PPVIN_S0_P1V05S0 =PPVIN_GPU_GPUVCORE
13
21
74
27
49
58
22
12
21
78
19
49
56
49
46
70
27
30
21
26
21
27
70
27
44
27
27
27
41
72
44
87
87
12
21
12
49
59
21
11
47
27
27
27
25
27
27
27
27
27
30
22
47
52
18
27
21
30
27
27
87
78
7
16
7
67
7
42
7
59
45
61
57
53
78
65
21
77
72
74
77
67
69
63
21
26
50
14
19
23
46
21
21
43
34
65
48
77
72
72
76
76
77
19
26
73
57
76
50
65
71
73
68
69
57
66
66
26
25
72
71
71
60
57
7
26
71
57
34
28
24
25
26
48
40
40
39
64
41 40
41 40
64
39
40
64
41
39
64
39
71
73
64 40
61
43
57
60
46
7
62
78
46
25
66
62
31
38
32
50
65
11
63
57
21
21
21
21
61
18
50
16
62
16
31
32
62
57
22
35
36
36
35
57
57
11
7
7
68
74
77
57
9
74
57
18
10
33
50
35
36
35
7
27
61
78
57
26
26
34
26
28
48
38
38
48
53
54
50
48
50
21
57
23
24
26
26
26
26
26
26
26
27
28
28
29
46
42
47
48
48
50
50
51
57
65
87
18
27
7
7
52
58
76
78
40
76
59
65 57
42
42
65
65
22
57
57
75
57
65
55
21
50
16
57
22
27
26
26
87
57
36
51
19
51
52
52
58
59
50
65
75
77
74
13
29
30
31
32
25
26
26
65
65
46
65
57
57
49
58
60
58
60
60
61
59
62
63
61
74
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
TM Hole
(Can’t be PTH)
Tooling
Holes
(Can’t be PTH)
Notches
Edge
Chassis GNDs
Frame Holes
Top CPU TM Notch
Left CPU
Add 2 buried vias to GND
RAM Door (Torx) Holes
TM Hole
Top GPU Right
Bottom Left GPU
TM Hole
Digital Ground
TM Hole
Right CPU
Thermal Module Holes
Board
HOLE-VIA-P5RP25
HOLE-VIA-P5RP25
402
NONE
NONE
SHORT
NONE
OMIT
SHLD-SM-LF
OG-503040
5P75R2P7
5P75R2P7
5P75R2P7
5P75R2P7
3P7R3P2
3P7R3P2
3P7R3P2
3P2R2P7
3P2R2P7
3P2R2P7
HOLE-VIA-P5RP25
HOLE-VIA-P5RP25
SM
Signal Aliases
SYNC_MASTER=(T9_MLB)
9
88
A.0.0
051-7225
SYNC_DATE=08/23/2006
GND_CHASSIS_DVI_BOT
MAKE_BASE=TRUE
VOLTAGE=0V
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm
TP_USB_EXTCN
MAKE_BASE=TRUE
PEG_CLK100M_N
PEG_CLK100M_P
MAKE_BASE=TRUE
PEG_CLK100M_GPU_N
PEG_CLK100M_GPU_P
MAKE_BASE=TRUE
USB_EXTC_P
SMC_SMS_INT
MAKE_BASE=TRUE
=SMC_SMS_INT
MAKE_BASE=TRUE
PM_ALL_NBGFX_PGOOD
GFXIMVP6_PGOOD
VR_PWRGOOD_DELAY
MAKE_BASE=TRUE
=NB_CLINK_MPWROK
=GFX_VR_EN GFX_VID<4..0>
MAKE_BASE=TRUE
GFX_VR_EN
MAKE_BASE=TRUE
GFXIMVP6_VID<4..0>
MEM_A_A<15>
MAKE_BASE=TRUE
TP_MEM_A_A<15>
MEM_B_A<15>
MAKE_BASE=TRUE
TP_MEM_B_A<15>
TP_USB_EXTCP
MAKE_BASE=TRUE
GND_CHASSIS_DVI_TOP
MIN_LINE_WIDTH=0.5 mm
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V
GND_CHASSIS_ENET
MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V
MIN_LINE_WIDTH=0.5 mm
MAKE_BASE=TRUE
MAKE_BASE=TRUE
VOLTAGE=0V
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm
GND_CHASSIS_RTUSB
=GND_CHASSIS_DVI_TOP
=GND_CHASSIS_DVI_BOT
=GND_CHASSIS_FW_PORT1 =GND_CHASSIS_FW_PORT0U
=GND_CHASSIS_ENET
=GND_CHASSIS_FW_PORT0L =GND_CHASSIS_RTUSB
GND_CHASSIS_RAMDOOR_HOLE_1
GND_CHASSIS_LVDS_HOLE
GND_CHASSIS_RIGHT_FAN_HOLE
GND_CHASSIS_RIGHT_FAN_NOTCH
GND_CHASSIS_DIMM_NOTCH
GND_CHASSIS_LIOFLEX_HOLE
GND_CHASSIS_LINDACARD_HOLE
GND_CHASSIS_BATTCONN_HOLE
GND_CHASSIS_DVI_HOLE
GND_CHASSIS_RAMDOOR_HOLE_0
PM_SB_PWROK
MAKE_BASE=TRUE
=SB_CLINK_MPWROK
=PP5V_S5_P1V25S0FET
MIN_LINE_WIDTH=0.1 mm
MAKE_BASE=TRUE
PP5V_S5_P1V25S0FET
MIN_NECK_WIDTH=0.1 mm VOLTAGE=5V
NO_TEST=TRUE
USB_EXTC_N
=PP5V_S5_P1V25S0FETXW
GND_CHASSIS_LEFTCLUTCH
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V MAKE_BASE=TRUE
=GND_CHASSIS_LEFTCLUTCH =GND_CHASSIS_J5590
GND
VOLTAGE=0V
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
ZT0945
1
ZT0950
1
R0910
1
2
SH0925
1 2 3
ZT0970
1
ZT0975
1
ZT0980
1
ZT0985
1
ZT0930
1
ZT0935
1
ZT0940
1
ZT0920
1
ZT0965
1
ZT0955
1
ZT0990
1
ZT0960
1
XW0900
1 2
58 28
28
66
66
82
16
25
82
84
84
30
30
24
54 45
77 59
7
16
16
16
59
59
31
32
76
76
41
41
37
41
43
7
25
57
24
8
44
51
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
IN IN IN
IN
OUT
IN
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
OUT OUT
OUT
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
BI BI BI BI BI
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
BI
BI BI BI
BI BI BI
BI
BI
BI BI
BI BI BI BI BI
BI
OUT
OUT
OUT
OUT
OUT
IN
IN IN IN IN IN
IN IN
IN IN
OUT
IN IN
IN
IN
IN IN
IN
IN
OUT
BI BI BI BI
LOCK*
INIT*
A20M*
A6*
A3* A4*
A14*
A16*
REQ0* REQ1* REQ2* REQ3* REQ4*
BCLK1
BCLK0
THERMTRIP*
THERMDA
PROCHOT*
DBR*
TRST*
TMS
TDO
TDI
TCK
PREQ*
PRDY*
BPM3*
BPM2*
BPM1*
BPM0*
HITM*
HIT*
TRDY*
RS2*
RS1*
RS0*
RESET*
IERR*
BR0*
DBSY*
DRDY*
DEFER*
BNR*
RSVD9
RSVD8
RSVD7
RSVD6
RSVD5
RSVD4
RSVD3
RSVD2
RSVD1
RSVD0
SMI*
LINT1
LINT0
STPCLK*
FERR*
ADSTB1*
A35*
A34*
A33*
A32*
A31*
A30*
A29*
A28*
A19*
A18*
A17*
ADSTB0*
A13*
A12*
BPRI*
A20* A21* A22* A23* A24*
A26* A27*
A9*
A8*
A7*
A11*
A25*
THERMDC
IGNNE*
ADS*
A10*
A15*
A5*
NC
1 OF 4
CONTROL
THERMAL
XDP/ITP SIGNALS
H CLK
RESERVED
ADDR GROUP0ADDR GROUP1
ICH
DINV1*
D31*
D30*
D25*
D11* D12* D13* D14*
DSTBP0* DINV0*
D9*
D8*
D7*
D6*
D19*
D18*
DATBP1*
D0*
D32* D1* D2*
D5*
D16*
D20* D21* D22* D23* D24*
D26* D27* D28* D29*
DSTBN1*
GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6
BSEL0 BSEL1 BSEL2
D33*
D34*
D35*
D36*
D37*
D38*
D39*
D40*
D41*
D42*
D43*
D44*
D45*
D46*
D47*
DSTBN2* DSTBP2*
DINV2*
D48*
D49*
D50*
D51*
D52*
D53*
D54*
D55*
D56*
D57*
D58*
D59*
D60*
D61*
D62*
D63*
DSTBN3* DSTBP3*
DINV3*
COMP0 COMP1 COMP2 COMP3
DPRSTP*
DPSLP*
DPWR*
PWRGOOD
SLP*
PSI*
D17*
D4*
D3*
DSTBN0*
D15*
D10*
2 OF 4
DATA GRP 3 DATA GRP 2
MISC
DATA GRP 0DATA GRP 1
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
NC
LAYOUT NOTE:
MAKE TRACE LENGTH SHORTER THAN 0.5".
COMP0,2 CONNECT WITH ZO=27.4OHM,
MAKE TRACE LENGTH SHORTER THAN 0.5".
COMP1,3 CONNECT WITH ZO=55OHM,
PM_THRMTRIP# SHOULD CONNECT TO ICH AND GMCH WITHOUT T (NO STUB)
0.1" AWAY
PLACE TESTPOINT ON FSB_IERR_L WITH A GND
0.5" MAX LENGTH FOR CPU_GTLREF
REFERENCED TO GND
PLACE C1000 CLOSE TO CPU_TEST4 PIN. MAKE SURE CPU_TEST4 IS
1% 1/16W
54.9
MF-LF 402
68
5% 1/16W
402
MF-LF
1/16W
1%
MF-LF
1K
402
1%
MF-LF
2.0K
1/16W
402
1%
MF-LF
1/16W
54.9
402
27.4
1/16W MF-LF
1%
402
1%
MF-LF
1/16W
54.9
402
1%
MF-LF
1/16W
27.4
402
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
16 23 58 79
7
23 79
7
14 79
7
14 79
28
7
13 23 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
30 79
30 79
30 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
14 79
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
7
14 79
13 79
13 79
13 79
13 79
13 79
13 79
10 13 79
13 28
46 58 79
51
16 23 46 79
23 47 79
7
13 14 79
14 79
14 79
14 79
14 79
10 13 79
10 13 79
10 13 79
10 13 79
51 87
30 84
30 84
23 79
23 79
23 79
23 79
7
23 79
23 79
23 79
0
1/16W MF-LF
5%
NOSTUFF
402
1/16W
5% MF-LF
1K
NOSTUFF
402
1/16W
1%
MF-LF
54.9
402
1%
MF-LF
1/16W
54.9
402
54.9
1/16W MF-LF
1%
402
54.9
1/16W MF-LF
1%
402
14 79
14 79
14 79
14 79
649
1/16W MF-LF
1%
402
1/16W
5%
1K
NOSTUFF
MF-LF
402
X5R
NOSTUFF
0.1uF
10% 16V
402
OMIT
MEROM
FCBGA
OMIT
MEROM
FCBGA
1%
MF-LF
1/16W
54.9
PLACEMENT_NOTE=Place R1024 near ITP connector (if present)
402
SYNC_DATE=03/16/2007
SYNC_MASTER=T9_NOME
88
051-7225
A.0.0
10
CPU FSB
XDP_BPM_L<2>
XDP_BPM_L<5> XDP_TCK
CPU_THERMD_N
=PP1V05_S0_CPU
=PP1V05_S0_CPU
=PP1V05_S0_CPU
=PP1V05_S0_CPU
XDP_TRST_L
XDP_TDI
XDP_TMS
XDP_TDO
XDP_TCK
FSB_A_L<5>
FSB_A_L<15>
FSB_A_L<10>
FSB_ADS_L
CPU_IGNNE_L
FSB_A_L<25>
FSB_A_L<11>
FSB_A_L<7> FSB_A_L<8> FSB_A_L<9>
FSB_A_L<27>
FSB_A_L<26>
FSB_A_L<24>
FSB_A_L<23>
FSB_A_L<22>
FSB_A_L<21>
FSB_A_L<20>
FSB_BPRI_L
FSB_A_L<12> FSB_A_L<13>
FSB_ADSTB_L<0>
FSB_A_L<17> FSB_A_L<18> FSB_A_L<19>
FSB_A_L<28> FSB_A_L<29> FSB_A_L<30> FSB_A_L<31> FSB_A_L<32> FSB_A_L<33> FSB_A_L<34> FSB_A_L<35> FSB_ADSTB_L<1>
CPU_FERR_L
CPU_STPCLK_L CPU_INTR CPU_NMI CPU_SMI_L
TP_CPU_RSVD0 TP_CPU_RSVD1 TP_CPU_RSVD2 TP_CPU_RSVD3 TP_CPU_RSVD4 TP_CPU_RSVD5 TP_CPU_RSVD6 TP_CPU_RSVD7 TP_CPU_RSVD8 TP_CPU_RSVD9
FSB_BNR_L
FSB_DEFER_L FSB_DRDY_L FSB_DBSY_L
FSB_BREQ0_L
CPU_IERR_L
FSB_CPURST_L FSB_RS_L<0> FSB_RS_L<1> FSB_RS_L<2> FSB_TRDY_L
FSB_HIT_L FSB_HITM_L
XDP_BPM_L<0> XDP_BPM_L<1>
XDP_BPM_L<3> XDP_BPM_L<4>
XDP_TDI XDP_TDO XDP_TMS XDP_TRST_L XDP_DBRESET_L
CPU_PROCHOT_L CPU_THERMD_P
PM_THRMTRIP_L
FSB_CLK_CPU_P FSB_CLK_CPU_N
FSB_REQ_L<4>
FSB_REQ_L<3>
FSB_REQ_L<2>
FSB_REQ_L<1>
FSB_REQ_L<0>
FSB_A_L<16>
FSB_A_L<14>
FSB_A_L<4>
FSB_A_L<3>
FSB_A_L<6>
CPU_A20M_L
CPU_INIT_L
FSB_LOCK_L
FSB_D_L<10>
FSB_D_L<15> FSB_DSTB_L_N<0>
FSB_D_L<3> FSB_D_L<4>
FSB_D_L<17>
CPU_PSI_L
FSB_CPUSLP_L
CPU_PWRGD
FSB_DPWR_L
CPU_DPSLP_L
CPU_DPRSTP_L
CPU_COMP<3>
CPU_COMP<2>
CPU_COMP<1>
CPU_COMP<0>
FSB_DINV_L<3>
FSB_DSTB_L_P<3>
FSB_DSTB_L_N<3>
FSB_D_L<63>
FSB_D_L<62>
FSB_D_L<61>
FSB_D_L<60>
FSB_D_L<59>
FSB_D_L<58>
FSB_D_L<57>
FSB_D_L<56>
FSB_D_L<55>
FSB_D_L<54>
FSB_D_L<53>
FSB_D_L<52>
FSB_D_L<51>
FSB_D_L<50>
FSB_D_L<49>
FSB_D_L<48>
FSB_DINV_L<2>
FSB_DSTB_L_P<2>
FSB_DSTB_L_N<2>
FSB_D_L<47>
FSB_D_L<46>
FSB_D_L<45>
FSB_D_L<44>
FSB_D_L<43>
FSB_D_L<42>
FSB_D_L<41>
FSB_D_L<40>
FSB_D_L<39>
FSB_D_L<38>
FSB_D_L<37>
FSB_D_L<36>
FSB_D_L<35>
FSB_D_L<34>
FSB_D_L<33>
CPU_BSEL<2>
CPU_BSEL<1>
CPU_BSEL<0>
TP_CPU_TEST6
CPU_TEST4
TP_CPU_TEST3
CPU_TEST2
CPU_TEST1
CPU_GTLREF
FSB_DSTB_L_N<1>
FSB_D_L<29>
FSB_D_L<28>
FSB_D_L<27>
FSB_D_L<26>
FSB_D_L<24>
FSB_D_L<23>
FSB_D_L<22>
FSB_D_L<21>
FSB_D_L<20>
FSB_D_L<16>
FSB_D_L<5>
FSB_D_L<2>
FSB_D_L<1>
FSB_D_L<32>
FSB_D_L<0>
FSB_DSTB_L_P<1>
FSB_D_L<18> FSB_D_L<19>
FSB_D_L<6> FSB_D_L<7> FSB_D_L<8> FSB_D_L<9>
FSB_DINV_L<0>
FSB_DSTB_L_P<0>
FSB_D_L<14>
FSB_D_L<13>
FSB_D_L<12>
FSB_D_L<11>
FSB_D_L<25>
FSB_D_L<30> FSB_D_L<31>
FSB_DINV_L<1>
TP_CPU_TEST5
R1002
1
2
R1004
1
2
R1005
1
2
R1006
1
2
R1019
R1018
R1017
R1016
R1030
R1007
1
2
R1003
1
2
R1020
R1021
R1022
R1023
R1012
1
2
C1000
1
2
U1000
N3 P5 P2 L2 P4 P1 R1
Y2 U5 R3 W6
A6
U4 Y5 U1 R4 T5 T3 W2 W5 Y4
J4
U2 V4
W3 AA4 AB2 AA3
L5
L4
K5
M3
N2
J1
H1
M1
V1
A22 A21
E2
AD4 AD3 AD1 AC4
G5
F1
C20
E1
H5 F21
A5
G6 E4
D20
C4
B3
C6
B4
H4
B1
AC2 AC1
D21
K3
H2
K2
J3
L1
C1 F3 F4 G3
M4
N5
T2
V3
B2
C3
D2 D22
D3
F6
A3
D5
AC5 AA6 AB3
A24 B25
C7
AB5
G2
AB6
U1000
B22 B23 C21
R26 U26 AA1 Y1
E22 F24
J24 J23 H22 F26 K22 H23
N22 K25 P26 R23
E26
L23 M24 L22 M23 P25 P23 P22 T24 R24 L25
G22
T25 N25
Y22 AB24 V24 V26 V23 T22 U25 U23
F23
Y25 W22 Y23 W24 W25 AA23 AA24 AB25
AE24 AD24
G25
AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21
E25
AC22 AD23 AF22 AC23
E23 K24 G24
M26
H25
N24
U22
AC20
E5 B5 D24
J26
L26
Y26
AE25
H26
AA26
AF24
AD26
AE6
D6 D7
C23 D25 C24
AF26
AF1 A26
R1024
13
13
13
13
12
12
12
12
11
11
11
11
79
79
79
79
79
10
10
10
10
13
13
13
13
13
8
8
8
8
10
10
10
10
10
79
79
79
79
79 79
OUT OUT OUT OUT OUT OUT OUT
OUT
OUT
VCC
VSSSENSE
VCCSENSE
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VCCA
VCCP
VCC
3 OF 4
VSS VSS
4 OF 4
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
TBD A (Deep Sleep LFM)
TBD A (Sleep LFM)
TBD A (Auto-Halt/Stop-Grant LFM)
Current numbers from Merom for Santa Rosa EMTS, doc #22221.
TBD A (LFM)
TBD A (HFM)
TBD A (Auto-Halt/Stop-Grant HFM)
TBD A (Sleep HFM)
TBD A (Deep Sleep HFM)
TBD A (Deeper Sleep) TBD A (Enhanced Deeper Sleep)TBD A (Enhanced Deeper Sleep)
TBD A (Deeper Sleep)
TBD A (Deep Sleep SuperLFM)
TBD A (Deep Sleep HFM)
TBD A (Sleep SuperLFM)
TBD A (Sleep HFM)
TBD A (Auto-Halt/Stop-Grant SuperLFM)
TBD A (Auto-Halt/Stop-Grant HFM)
TBD A (SuperLFM)
18.7 A (LFM)
21.0 A (HFM)
23.0 A (Design Target) 17.0 A (Design Target)
Ultra Low Voltage:Low Voltage:
(CPU INTERNAL PLL POWER 1.5V)
(CPU IO POWER 1.05V)
130 mA
(CPU CORE POWER)
Standard Voltage:
44.0 A (Design Target)
41.0 A (HFM)
16.8 A (Sleep SuperLFM)
16.0 A (Deep Sleep SuperLFM)
4500 mA (before VCC stable) 2500 mA (after VCC stable)
9.4 A (Enhanced Deeper Sleep)
25.5 A (SuperLFM)
30.4 A (LFM)
27.4 A (Auto-Halt/Stop-Grant HFM)
17.0 A (Auto-Halt/Stop-Grant SuperLFM)
27.4 A (Sleep HFM)
25.0 A (Deep Sleep HFM)
11.5 A (Deeper Sleep)
12 79
12 79
12 79
12 79
12 79
12 79
1/16W
1%
100
402
MF-LF
PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.
12 79
58 79
58 79
OMIT
MEROM
FCBGA
OMIT
MEROM
FCBGA
100
1% 1/16W
PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.
402
MF-LF
8811
A.0.0
051-7225
CPU Power & Ground
SYNC_MASTER=T9_NOME
SYNC_DATE=03/16/2007
CPU_VID<2> CPU_VID<3>
CPU_VID<5>
=PPVCORE_S0_CPU
CPU_VCCSENSE_N
CPU_VCCSENSE_P
CPU_VID<0> CPU_VID<1>
=PPVCORE_S0_CPU
CPU_VID<6>
CPU_VID<4>
=PP1V5_S0_CPU
=PP1V05_S0_CPU
R1101
1
2
U1000
A7 A9
B9 B10 B12 B14 B15 B17 B18 B20
C9 C10
A10
C12 C13 C15 C17 C18
D9 D10 D12 D14 D15
A12
D17 D18
E7
E9 E10 E12 E13 E15 E17 E18
A13
E20
F7
F9 F10 F12 F14 F15 F17 F18 F20
A15
AA7 AA9
AA10 AA12 AA13 AA15 AA17 AA18 AA20
AB9
A17
AC10 AB10 AB12 AB14 AB15 AB17 AB18
AB20 AB7 AC7
A18
AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12
A20
AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17
B7
AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20
B26 C26
G21 V6
R21 R6 T21 T6 V21 W21
J6 K6 M6 J21 K21 M21 N21 N6
AF7
AD6 AF5 AE5 AF4 AE3 AF3 AE2
AE7
U1000
A4 A8
B11
W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5
B13
AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8
B16
AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11
B19
AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13
B21
AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16
B24
AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19
C5
AF21 A25 AF25
C8 C11 C14
A11
C16 C19
C2 C22 C25
D1
D4
D8 D11 D13
A14
D16 D19 D23 D26
E3
E6
E8 E11 E14 E16
A16
E19 E21 E24
F5
F8 F11 F13 F16 F19
F2
A19
F22 F25
G4
G1 G23 G26
H3
H6 H21 H24
A23
J2
J5 J22 J25
K1
K4 K23 K26
L3
L6
AF2
L21 L24
M2
M5 M22 M25
N1
N4 N23 N26
B6
P3
P6 P21 P24 R2 R5 R22 R25 T1 T4
B8
T23 T26 U3 U6 U21 U24 V2 V5 V22 V25
R1100
1
2
49
49
13
12
12
12
11
11
12
10
8
8
8
8
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
WF: Consider sharing bulk cap with NB Vtt?
VCCA (CPU AVdd) DECOUPLING
1x 10uF, 1x 0.01uF
VCCP (CPU I/O) DECOUPLING
1x 470uF, 6x 0.1uF 0402
CPU VCORE HF AND BULK DECOUPLING
CPU VCORE VID CONNECTIONS
4x 330uF, 20x 22uF 0805
22UF
20%
6.3V 805
CERM-X5R
470UF
20%
D2T
TANT
2.5V
CRITICAL
22UF
20%
6.3V 805
CERM-X5R
22UF
CERM-X5R 805
6.3V
20%
22UF
CERM-X5R 805
6.3V
20%
22UF
20%
6.3V 805
CERM-X5R
22UF
20%
6.3V 805
CERM-X5R
22UF
20%
6.3V 805
CERM-X5R
6.3V
22UF
20% 805
CERM-X5R
22UF
20%
6.3V 805
CERM-X5R
22UF
CERM-X5R 805
6.3V
20%
22UF
CERM-X5R
20%
805
6.3V
22UF
CERM-X5R 805
6.3V
20%
22UF
CERM-X5R
20%
6.3V 805
20% 805
6.3V
22UF
CERM-X5R
22UF
CERM-X5R
20%
6.3V 805
10V 402
CERM
20%
0.1UF
22UF
20%
6.3V 805
CERM-X5R
22UF
20%
6.3V 805
CERM-X5R
22UF
CERM-X5R 805
6.3V
20%
22UF
CERM-X5R 805
6.3V
20%
10V
0.1UF
402
CERM
20%
10V
0.1UF
402
CERM
20%
10V
0.1UF
402
CERM
20%
10V
0.1UF
402
CERM
20%
10V
0.1UF
402
CERM
20%
22UF
CERM-X5R
20%
805
6.3V
0.01UF
10% 16V
402
CERM
PLACEMENT_NOTE=Place near CPU pin B26.
603
10uF
20%
6.3V X5R
CRITICAL
PLACEMENT_NOTE=Place in CPU center cavity.
D2T
TANT
330UF
2.0V
10%
PLACEMENT_NOTE=Place in CPU center cavity.
D2T
TANT
CRITICAL
330UF
2.0V
10%
PLACEMENT_NOTE=Place in CPU center cavity.
10%
D2T
TANT
CRITICAL
330UF
2.0V
PLACEMENT_NOTE=Place in CPU center cavity.
CRITICAL
D2T
TANT
10%
330UF
2.0V
051-7225
SYNC_DATE=03/19/2007
A.0.0
12 88
SYNC_MASTER=M76_MLB
CPU Decoupling & VID
=PPVCORE_S0_CPU
CPU_VID<0..6>
MAKE_BASE=TRUE
IMVP6_VID<0..6>
=PP1V5_S0_CPU
=PP1V05_S0_CPU
C1208
1
2
C1207
1
2
C1219
1
2
C1218
1
2
C1206
1
2
C1204
1
2
C1216
1
2
C1214
1
2
C1203
1
2
C1202
1
2
C1201
1
2
C1213
1
2
C1212
1
2
C1211
1
2
C1200
1
2
C1210
1
2
C1236
1
2
C1205
1
2
C1209
1
2
C1215
1
2
C1217
1
2
C1237
1
2
C1238
1
2
C1239
1
2
C1240
1
2
C1241
1
2
C1281
1
2
C1280
1
2
C1250
1
2 3
C1251
1
2 3
C1252
1
2 3
C1253
1
2 3
C1235
1
2 3
13
49
79
11
11
79
58
11
10
8
11
7
8
8
IN
BI
BI
OUT
OUT
IN
BI
IN
IN IN
OUT
IN
OUT OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
IN
BI
IN
IN IN
IN
IN
IN IN
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
NB CFG[0] NB CFG[1]
Use with 920-0451 adapter board to support CPU, NB & SB debugging.
Mini-XDP Connector
NOTE: This is not the standard XDP pinout.
(VCC_OBS_CD)
OBSFN_C0
OBSDATA_D3
SB GPIO[8]
NB CFG[8]
NB CFG[3]
NB CFG[7]
NB CFG[6]
NB CFG[5]
NB CFG[4]
NB CFG[2]
SB OC[4]#
(OBSDATA_A2)
SB OC[3]#
PWRGD/HOOK0
TCK0
(OBSDATA_A3)
NC
OBSFN_C1
OBSDATA_C0
OBSDATA_C2
TDO
ITPCLK#/HOOK5
RESET#/HOOK6 DBR#/HOOK7
SB OC[0]#
OBSDATA_C3
SB OC[1]#
SB OC[2]#
SB OC[5]#
SB OC[6]# SB OC[7]#
TCK1
SCL
SDA
OBSDATA_B1
OBSDATA_A1
OBSFN_A1
TRSTn
HOOK3
HOOK2
VCC_OBS_AB
HOOK1
OBSDATA_D1
OBSDATA_D0
OBSDATA_A3
OBSDATA_A2
OBSDATA_B3
OBSDATA_B2
OBSFN_A0
OBSDATA_A0
ITPCLK/HOOK4
Direction of XDP module
on even-numbered side of J1300
Please avoid any obstructions
OBSDATA_C1
XDP_PRESENT#
TMS
TDI
OBSDATA_B0
998-1571
OBSDATA_D2
(OBSDATA_A1)
(OBSDATA_A0)
7
10 23 79
402
MF-LF
1/16W
5%
1K
XDP
15
15
1/16W
XDP
402
MF-LF
1%
54.9
402
16V
10%
0.1uF
X5R
XDP
MF-LF
10K
5%
XDP
1/16W 402
MF-LF
10K
5%
1/16W
XDP
402
402
16V
10%
0.1uF
X5R
XDP
10 28
10 79
10 79
10 79
10 79
10 79
10 79
10 79
7
10 14 79
10 79
10 79
10 79
10 79
30 79 84
30 79 84
24 34
24
24 77
24
24 36
24
24
24 43
1/16W
402
MF-LF
5%
1K
XDP
XDP_CONN
CRITICAL
F-ST-SM
LTH-030-01-G-D-NOPEGS
16 30 79
16 30 79
16
16
16
16
25 45
16
16 30 79
16
eXtended Debug Port (XDP)
SYNC_DATE=12/12/2006
SYNC_MASTER=T9_NOME
13
A.0.0
88
051-7225
=PP1V05_S0_CPU
NB_BSEL<1>
PM_LATRIGGER_L EXTGPU_LVDS_EN
=PP3V3_S0_XDP
XDP_CLK_P
XDP_OBS20
LVDS_CTRL_CLK
LVDS_CTRL_DATA
XDP_TRST_L
XDP_DBRESET_L
USB_EXTA_OC_L SB_GPIO40
XDP_TMS
XDP_TDI
XDP_CPURST_L FSB_CPURST_L
XDP_TDO
XDP_TCK
XDP_BPM_L<3>
TP_XDP_HOOK3
SB_GPIO30 USB_EXTB_OC_L
TP_XDP_HOOK2
WOW_EN
XDP_BPM_L<5>
XDP_BPM_L<2>
XDP_BPM_L<0>
NB_BSEL<0>
NB_CFG<4> NB_CFG<5>
NB_CFG<6> NB_CFG<7>
XDP_PWRGDCPU_PWRGD
SMC_WAKE_SCI_L
NB_BSEL<2> NB_CFG<3>
USB_EXTD_OC_L
NB_CFG<8>
XDP_CLK_N
XDP_BPM_L<1>
XDP_BPM_L<4>
R1399
1 2
R1315
1
2
C1300
1
2
R1331
1
2
R1330
1
2
C1301
1
2
R1303
1 2
J1300
1
10
1112 1314 1516 1718 19
2
20
2122 2324 2526 2728 29
3
30
3132 3334 3536 3738 39
4
40
4142 4344 4546 4748 49
5
50
5152 5354 5556 5758 59
6
60
78 9
12 11 10
8
8
79
BI
BI BI
OUT
OUT
BI
BI
BI
BI BI
BI
BI BI BI BI
BI BI
BI
BI BI
BI BI BI BI
BI BI
OUT
BI
OUT
OUT
OUT
BI BI BI BI BI
BI BI
H_D0*
H_D3*
H_D2*
H_D33* H_D34* H_D35*
H_D1*
H_D4*
H_D10*
H_A4* H_A5* H_A6* H_A7* H_A8*
H_A9* H_A10* H_A11* H_A12* H_A13* H_A14* H_A15* H_A16* H_A17* H_A18* H_A19* H_A20* H_A21* H_A22* H_A23* H_A24* H_A25* H_A26* H_A27* H_A28* H_A29* H_A30* H_A31* H_A32* H_A33* H_A34* H_A35*
H_ADS*
H_ADSTB0* H_ADSTB1*
H_A3*
H_D7* H_D8* H_D9*
H_D11* H_D12* H_D13* H_D14* H_D15* H_D16* H_D17* H_D18* H_D19* H_D20* H_D21* H_D22* H_D23*
H_D25* H_D26* H_D27* H_D28* H_D29* H_D30*
H_D32*
H_D36* H_D37* H_BNR* H_D38*
H_BPRI* H_D39* H_D40*
H_DEFER*
H_D41*
H_DBSY* H_D42* H_D43* H_D44*
H_DPWR* H_D45*
H_DRDY* H_D46* H_HIT* H_D47*
H_HITM* H_D48*
H_LOCK*
H_TRDY*
H_D51* H_D52* H_D53*
H_DINV0*
H_D54*
H_DINV1*
H_D55*
H_DINV2*
H_D56*
H_DINV3*
H_D57* H_D58*
H_DSTBN0*
H_D59*
H_DSTBN1*
H_D60*
H_DSTBN2*
H_D61*
H_DSTBN3*
H_D62* H_D63*
H_DSTBP0* H_DSTBP1*
H_DSTBP2* H_SWING H_RCOMP
H_REQ0* H_SCOMP H_REQ1* H_SCOMP*
H_REQ2*
H_REQ3* H_CPURST*
H_REQ4* H_CPUSLP*
H_RS0* H_RS1*
H_AVREF
H_RS2*
H_DVREF
H_D5* H_D6*
H_D31*
H_BREQ*
H_D24*
H_D49* H_D50*
H_DSTBP3*
HPLL_CLK
HPLL_CLK*
HOST
(1 OF 10)
BI BI BI BI
BI
IN
IN
IN
OUT OUT
BI BI BI BI BI BI BI BI BI BI BI BI BI BI
BI
BI
BI
BI
BI BI BI BI BI
BI
BI BI
BI
BI
BI BI
BI BI
BI
BI
BI
BI
BI BI
BI BI
BI
BI
BI
BI
BI
BI BI
BI BI
BI
BI
BI
BI
BI
BI
BI
BI BI
BI
BI
BI
BI
BI BI
BI
BI
BI
BI
BI
BI
BI
BI BI
BI BI
BI
BI
BI
BI
BI
BI BI
BI BI
BI
BI
BI
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
7
10 79
7
10 79
7
10 79
10 79
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
X5R
0.1uF
10% 16V
402
2.0K
MF-LF
1%
1/16W
402
1K
MF-LF
1%
1/16W
402
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
10 79
7
10 79
10 79
10 79
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
54.9
MF-LF
1% 1/16W
402
24.9
MF-LF
1%
1/16W
402
221
MF-LF
1%
1/16W
402
100
MF-LF
1%
1/16W
402
X5R
0.1uF
10% 16V
402
7
10 79
OMIT
CRESTLINE
FCBGA
10 79
10 79
10 79
10 79
7
10 79
54.9
MF-LF
1%
1/16W
402
7
10 79
7
30 84
7
30 84
7
10 13 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
7
10 79
SYNC_DATE=03/16/2007
NB CPU Interface
051-7225
A.0.0
8814
SYNC_MASTER=T9_NOME
FSB_RS_L<2>
FSB_RS_L<0> FSB_RS_L<1>
FSB_REQ_L<4>
FSB_REQ_L<3>
FSB_REQ_L<2>
FSB_REQ_L<1>
FSB_REQ_L<0>
FSB_DSTB_L_P<3>
FSB_DSTB_L_P<2>
FSB_DSTB_L_P<1>
FSB_DSTB_L_P<0>
FSB_DSTB_L_N<3>
FSB_DSTB_L_N<2>
FSB_DSTB_L_N<1>
FSB_DSTB_L_N<0>
FSB_DINV_L<3>
FSB_DINV_L<2>
FSB_DINV_L<1>
FSB_DINV_L<0>
FSB_LOCK_L FSB_TRDY_L
FSB_HITM_L
FSB_HIT_L
FSB_DRDY_L
FSB_CLK_NB_N
FSB_CLK_NB_P
FSB_DPWR_L
FSB_DBSY_L
FSB_DEFER_L
FSB_BREQ0_L
FSB_BNR_L FSB_BPRI_L
FSB_ADSTB_L<1>
FSB_ADSTB_L<0>
FSB_ADS_L
FSB_A_L<35>
FSB_A_L<34>
FSB_A_L<33>
FSB_A_L<31>
FSB_A_L<30>
FSB_A_L<32>
FSB_A_L<29>
FSB_A_L<28>
FSB_A_L<27>
FSB_A_L<26>
FSB_A_L<25>
FSB_A_L<24>
FSB_A_L<23>
FSB_A_L<22>
FSB_A_L<21>
FSB_A_L<20>
FSB_A_L<19>
FSB_A_L<18>
FSB_A_L<17>
FSB_A_L<16>
FSB_A_L<15>
FSB_A_L<14>
FSB_A_L<13>
FSB_A_L<12>
FSB_A_L<10> FSB_A_L<11>
FSB_A_L<9>
FSB_A_L<8>
FSB_A_L<7>
FSB_A_L<5>
FSB_A_L<4>
FSB_A_L<6>
FSB_A_L<3>
NB_FSB_VREF
NB_FSB_RCOMP
NB_FSB_SWING
FSB_D_L<59>
FSB_D_L<41>
FSB_D_L<38>
FSB_D_L<0>
FSB_D_L<4> FSB_D_L<5>
FSB_D_L<43>
FSB_D_L<12>
FSB_D_L<50>
FSB_D_L<49>
FSB_D_L<24>
FSB_D_L<31>
FSB_D_L<6>
FSB_CPUSLP_L
FSB_CPURST_L
NB_FSB_SCOMP_L
NB_FSB_SCOMP
FSB_D_L<63>
FSB_D_L<62>
FSB_D_L<61>
FSB_D_L<60>
FSB_D_L<58>
FSB_D_L<57>
FSB_D_L<56>
FSB_D_L<55>
FSB_D_L<54>
FSB_D_L<53>
FSB_D_L<52>
FSB_D_L<51>
FSB_D_L<48>
FSB_D_L<46>
FSB_D_L<45>
FSB_D_L<44>
FSB_D_L<42>
FSB_D_L<40>
FSB_D_L<39>
FSB_D_L<37>
FSB_D_L<36>
FSB_D_L<32>
FSB_D_L<30>
FSB_D_L<29>
FSB_D_L<28>
FSB_D_L<27>
FSB_D_L<26>
FSB_D_L<25>
FSB_D_L<23>
FSB_D_L<22>
FSB_D_L<21>
FSB_D_L<20>
FSB_D_L<19>
FSB_D_L<18>
FSB_D_L<17>
FSB_D_L<16>
FSB_D_L<15>
FSB_D_L<14>
FSB_D_L<13>
FSB_D_L<11>
FSB_D_L<9>
FSB_D_L<8>
FSB_D_L<7>
FSB_D_L<10>
FSB_D_L<1>
FSB_D_L<35>
FSB_D_L<34>
FSB_D_L<33>
FSB_D_L<2> FSB_D_L<3>
FSB_D_L<47>
=PP1V25R1V05_S0_FSB_NB
C1425
1
2
R1426
1
2
R1425
1
2
R1420
1
2
R1415
1
2
R1410
1
2
R1411
1
2
C1410
1
2
U1400
G17 C14 K16 B13 L16 J17 B14 K19 P15 R17 B16 H20 L19 D17 M17 N16 J19 B18 E19 B17
J13
B15 E17 C18 A19 B19 N19
B11 C11 M11 C15 F16 L13
G12 H17 G20
B9
C8 E8 F12
B6 E5
E2 G2
M10 N12
N9 H5
P13
K9 M2
W10
Y8 V4
G7
M3 J1 N5 N3 W6 W9 N2 Y7 Y9 P4
M6
W3 N1
AD12
AE3 AD9 AC9
AC7 AC14 AD11 AC11
H7
AB2
AD7
AB1
Y3 AC6 AE2 AC5 AG3 AJ9 AH8
H3
AJ14
AE9
AE11 AH12
AJ5 AH5 AJ6 AE7 AJ7 AJ2
G4
AE5 AJ3 AH2
AH13
F3
N8
H2
C10
D6
K5 L2 AD13 AE13
H8 K7
M7 K3 AD2 AH11
L7 K2 AC2 AJ10
A9
E4 C6 G10
C2
M14 E13 A11 H13 B12
E12 D7 D8
W1
W2
B3
B7
AM5 AM7
R1421
1
2
30
8
IN
IN
OUT
IN
OUT OUT OUT
OUT OUT OUT
OUT
IN
OUT
OUT
BI
L_BKLT_CTRL
L_VDD_EN
PEG_TX15*
PEG_TX14*
PEG_TX13*
PEG_TX12*
PEG_TX11*
PEG_TX10*
PEG_TX9*
PEG_TX8*
PEG_TX7*
PEG_TX6*
PEG_TX5*
PEG_TX4*
PEG_TX3*
PEG_TX2*
PEG_TX1*
PEG_TX0*
PEG_TX15
PEG_TX14
PEG_TX13
PEG_TX12
PEG_TX11
PEG_TX10
PEG_TX9
PEG_TX8
PEG_TX7
PEG_TX6
PEG_TX5
PEG_TX4
PEG_TX3
PEG_TX2
PEG_TX1
PEG_TX0
PEG_RX14
PEG_RX15*
PEG_RX14*
PEG_RX13*
PEG_RX12*
PEG_RX11*
PEG_RX15
PEG_RX13
PEG_RX12
PEG_RX11
PEG_RX10
PEG_RX9
PEG_RX8
PEG_RX7
PEG_RX6
PEG_RX5
PEG_RX4
PEG_RX3
PEG_RX2
PEG_RX1
PEG_RX0
PEG_RX10*
PEG_RX9*
PEG_RX8*
PEG_RX7*
PEG_RX6*
PEG_RX5*
PEG_RX4*
PEG_RX3*
PEG_RX2*
PEG_RX1*
PEG_RX0*
PEG_COMPI PEG_COMPO
CRT_DDC_DATA
L_CTRL_DATA
LVDSB_DATA1 LVDSB_DATA2
LVDSB_DATA0
LVDSB_DATA2*
LVDSB_DATA1*
LVDSB_DATA0*
LVDSA_DATA2
LVDSA_DATA0 LVDSA_DATA1
LVDSB_CLK*
LVDS_VREFL
LVDS_IBG
TVC_RTN
TVA_RTN TVB_RTN
TVC_DAC
TVB_DAC
TVA_DAC
CRT_RED*
CRT_RED
CRT_GREEN*
CRT_GREEN
CRT_BLUE*
CRT_BLUE
CRT_VSYNC
CRT_TVO_IREF
CRT_HSYNC
CRT_DDC_CLK
L_BKLT_EN
L_DDC_CLK
TV_DCONSEL0 TV_DCONSEL1
LVDSA_DATA2*
L_DDC_DATA
LVDSA_DATA1*
LVDSA_DATA0*
LVDSB_CLK
LVDSA_CLK
LVDSA_CLK*
LVDS_VREFH
L_CTRL_CLK
LVDS_VBG
VGA
TV
LVDS
(3 OF 10)
PCI-EXPRESS GRAPHICS
BI
BI
OUT
OUT
IN
IN IN
IN
IN
IN
IN
IN
IN IN IN IN IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT OUT
IN
BI BI
OUT OUT OUT OUT
OUT OUT
IN
OUT
OUT
OUT OUT
OUT
OUT OUT
OUT
OUT OUT
IN
OUT OUT OUT
OUT
OUT
OUT
BI BI
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
recommendation is to float both signals, see Radar #5067636.
a glitch during wake-up on LVDS DATA/CLK pairs. New
Note: SR DG says to tie LVDS_VREFH/L to GND. This causes
If SDVO is used, VCCD_LVDS must remain powered with proper
should connect to GND through 75-ohm resistors.
omit filtering components. Unused DAC outputs
Unused DAC outputs must remain powered, but can
Can leave all signals NC if LVDS is not implemented.
decoupling. Otherwise, tie VCCD_LVDS to GND also.
Tie VCC_TX_LVDS and VCCA_LVDS to GND.
SDVO_FLDSTALL#
SDVO Alternate Function
SDVO_TVCLKIN# SDVO_INT#
SDVO_TVCLKIN SDVO_INT SDVO_FLDSTALL
SDVOB_GREEN
SDVOB_RED
SDVOC_CLKN
SDVOC_BLUE#
SDVOC_GREEN#
SDVOC_RED#
SDVOB_CLKN
SDVOB_BLUE#
SDVOB_GREEN#
SDVOB_RED#
SDVOB_CLKP
SDVOB_BLUE
SDVOC_CLKP
SDVOC_BLUE
SDVOC_GREEN
SDVOC_RED
LVDS Disable
TVDAC rails. VCCA_TVx_DAC and VCCA_DAC_BG can
Component: DACA, DACB & DACC
Composite: DACA only
TV-Out Signal Usage:
Can tie the following rails to GND:
VSYNC and CRT_TVO_IREF to GND.
CRT Disable / TV-Out Enable
TV-Out Disable / CRT Enable Tie TVx_DAC and TVx_RTN to GND. Must power all
Leave GFX_VID<3..0> and GFX_VR_EN as NC.
Tie VCC_AXG and VCC_AXG_NCTF to GND.
Tie VCCA_DPLLA and VCCA_DPLLB to VCC (VCore).
Tie DPLL_REF_CLK and DPLL_REF_SSCLK to GND.
Can also tie CRT_DDC_*, L_CTRL_*, L_DDC_*, SDVO_CTRL_* and TV_DCONSELx to GND.
Follow instructions for LVDS and CRT & TV-Out Disable above.
Internal Graphics Disable
and filtered at all times!
NOTE: Must keep VDDC_TVDAC powered
VCCD_CRT, VCCD_QDAC and VCC_SYNC.
VCCA_CRT_DAC, VCCA_DAC_BG, VCCA_TVx_DAC,
All CRT/TVDAC rails must be powered. All
CRT & TV-Out Disable Tie TVx_DAC, TVx_RTN, R/R#/G/G#/B/B#, HSYNC,
Tie R/R#/G/G#/B/B#, HSYNC and VSYNC to GND.
share filtering with VCCA_CRT_DAC.
S-Video: DACB & DACC only
Tie DPLL_REF_CLK* and DPLL_REF_SSCLK* to VCC (VCore).
rails must be filtered except for VCCA_CRT.
66 80
66 80
402
MF-LF
1/16W
1%
24.9
77
66 80
22
22
22
22
22
22
22
66 80
22
22
22 80
OMIT
CRESTLINE
FCBGA
13
13
22
22
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
66 80
77
77
66 80
77
77
77 80
77 80
77 80
77 80
77 80
77 80
66 80
77 80
77 80
77 80
77 80
77 80
77 80
77 80
77 80
77 80
77 80
66 80
22
22
22
22
22
22
22
22
SYNC_DATE=03/16/2007
15 88
A.0.0
051-7225
NB PEG / Video Interfaces
SYNC_MASTER=T9_NOME
=TV_B_RTN
=TV_B_DAC
LVDS_B_DATA_N<2>
LVDS_B_DATA_N<1>
LVDS_CTRL_DATA
LVDS_CTRL_CLK
TP_LVDS_VBG
PEG_D2R_P<9>
PEG_D2R_P<11>
PEG_D2R_P<10>
PP1V05_S0_NB_VCCPEG
PEG_D2R_N<1>
PEG_D2R_N<6>
TP_LVDS_VREFH
LVDS_A_CLK_N LVDS_A_CLK_P
LVDS_B_CLK_P
LVDS_A_DATA_N<0> LVDS_A_DATA_N<1>
LVDS_DDC_DATA
LVDS_A_DATA_N<2>
TV_DCONSEL<1>
TV_DCONSEL<0>
LVDS_DDC_CLK
LVDS_BKLT_EN
CRT_DDC_CLK
=CRT_HSYNC_R =CRT_TVO_IREF =CRT_VSYNC_R
=CRT_BLUE =CRT_BLUE_L =CRT_GREEN =CRT_GREEN_L =CRT_RED =CRT_RED_L
=TV_A_DAC
=TV_C_DAC
=TV_A_RTN
=TV_C_RTN
LVDS_IBG
TP_LVDS_VREFL
LVDS_B_CLK_N
LVDS_A_DATA_P<1>
LVDS_A_DATA_P<0>
LVDS_A_DATA_P<2>
LVDS_B_DATA_N<0>
LVDS_B_DATA_P<0>
LVDS_B_DATA_P<2>
LVDS_B_DATA_P<1>
CRT_DDC_DATA
PEG_COMP
PEG_D2R_N<0>
PEG_D2R_N<2> PEG_D2R_N<3> PEG_D2R_N<4> PEG_D2R_N<5>
PEG_D2R_N<7> PEG_D2R_N<8> PEG_D2R_N<9> PEG_D2R_N<10>
PEG_D2R_P<0> PEG_D2R_P<1> PEG_D2R_P<2> PEG_D2R_P<3> PEG_D2R_P<4> PEG_D2R_P<5> PEG_D2R_P<6> PEG_D2R_P<7> PEG_D2R_P<8>
PEG_D2R_P<12> PEG_D2R_P<13>
PEG_D2R_P<15>
PEG_D2R_N<11> PEG_D2R_N<12> PEG_D2R_N<13> PEG_D2R_N<14> PEG_D2R_N<15>
PEG_D2R_P<14>
PEG_R2D_C_P<0> PEG_R2D_C_P<1> PEG_R2D_C_P<2> PEG_R2D_C_P<3> PEG_R2D_C_P<4> PEG_R2D_C_P<5> PEG_R2D_C_P<6> PEG_R2D_C_P<7> PEG_R2D_C_P<8> PEG_R2D_C_P<9> PEG_R2D_C_P<10> PEG_R2D_C_P<11> PEG_R2D_C_P<12> PEG_R2D_C_P<13> PEG_R2D_C_P<14> PEG_R2D_C_P<15>
PEG_R2D_C_N<0> PEG_R2D_C_N<1> PEG_R2D_C_N<2> PEG_R2D_C_N<3> PEG_R2D_C_N<4> PEG_R2D_C_N<5> PEG_R2D_C_N<6> PEG_R2D_C_N<7> PEG_R2D_C_N<8> PEG_R2D_C_N<9> PEG_R2D_C_N<10> PEG_R2D_C_N<11> PEG_R2D_C_N<12> PEG_R2D_C_N<13> PEG_R2D_C_N<14> PEG_R2D_C_N<15>
LVDS_VDD_EN
LVDS_BKLT_CTL
R1510
1
2
U1400
H32 G32
K33 G35
K29 J29
F33
F29 E29
C32 E33
J40 H39 E39 E40 C37 D35 K40
L41 L43 N41 N40
C45
D46
G50
G51
E50
E51
F48
F49
E42
D44
E44
G44
A47
B47
A45
B45
N43 M43
J50
J51
L50
L51
AC45
AD44
AC41
AD40
AH47
AG46
AG49
AH49
AH45
AG45
AG42
AG41
M47
N47
U44
T45
T49
T50
T41
U40
W45
Y44
W41
Y40
AB50
AB51
Y48
W49
M45
N45
T38
U39
AD47
AC46
AC50
AC49
AD43
AC42
AG39
AH39
AE50
AE49
AH43
AH44
T46
U47
N50
N51
R51
R50
U43
T42
W42
Y43
Y47
W46
Y39
W38
AC38
AD39
M35 P33
E27
F27
G27
J27
K27
L27
21 19
22
22
IN
IN
CLKREQ*
NC1
NC8
CL_CLK
CL_PWROK
CL_RST*
RSVD6
THERMTRIP*
PM_BM_BUSY*
RSVD4
RSVD3
RSVD7
SM_CKE1
SM_CK0*
SM_CKE0
SM_ODT0
SM_ODT2
SM_RCOMP
SM_RCOMP*
SM_VREF0 SM_VREF1
SM_RCOMP_VOL
SM_CS1*
SM_CS0*
RSVD14
RSVD11
RSVD10
RSVD9
RSVD5
RSVD8
RSVD2
DPLL_REF_CLK*
DPLL_REF_SSCLK
PEG_CLK
DMI_RXN1
DMI_RXN0
DMI_RXN3
DMI_RXN2
DMI_RXP0 DMI_RXP1 DMI_RXP2
DMI_TXN0
DMI_RXP3
DMI_TXN2
DMI_TXN1
DMI_TXP0
DMI_TXN3
DMI_TXP1 DMI_TXP2 DMI_TXP3
PEG_CLK*
RSVD12
CL_DATA
CL_VREF
SDVO_CTRL_CLK
SDVO_CTRL_DATA
ICH_SYNC*
TEST1 TEST2
GFX_VID0 GFX_VID1 GFX_VID2
GFX_VR_EN
GFX_VID3
RSVD20 RSVD21
RSVD24 RSVD25
RSVD27
RSVD34 RSVD35 RSVD36 RSVD37 RSVD38 RSVD39
RSVD41 RSVD42
RSVD40
RSVD43 RSVD44 RSVD45
CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13
CFG16
CFG15
CFG14
CFG17 CFG18 CFG19 CFG20
PM_DPRSTP* PM_EXT_TS0*
PWROK
PM_EXT_TS1*
RSTIN*
DPRSLPVR
NC2
NC4
NC3
NC5
NC7
NC6
NC10
NC9
NC12
NC11
NC13 NC14 NC15 NC16
DPLL_REF_CLK
SM_RCOMP_VOH
SM_ODT3
SM_ODT1
RSVD13
SM_CS2* SM_CS3*
SM_CK3 SM_CK4
SM_CK4*
SM_CKE3
RSVD1
SM_CKE4
DPLL_REF_SSCLK*
SM_CK3*
SM_CK1*
SM_CK1
SM_CK0
SA_MA14
RSVD22 RSVD23
RSVD26
SB_MA14
SM_CK2 SM_CK2* SM_CK5 SM_CK5*
(2 OF 10)
RSVD
DDR MUXING
CLK
CFG
DMI
PM
GRAPHICS VID
ME
MISC
NC
OUT OUT OUT OUT OUT
BI BI
IN
OUT
BI
BI OUT OUT
IN
IN
OUT
OUT OUT
IN IN IN OUT
OUT OUT OUT
BI
OUT
BI
OUT
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT OUT OUT
OUT
OUT
OUT OUT OUT
OUT OUT OUT OUT
IN
IN IN
IN
IN
IN
IN
IN IN IN IN
IN IN
IN
IN
OUT
OUT
OUT
OUT
OUT OUT
OUT
OUT
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
NB CFG<13:12> require ICT access
IPU
IPU
RESERVED
RESERVED
Low = DMIx2
NB_CFG<3>
NB_CFG<8>
IPU
IPU
IPU
IPU
IPU
IPU
IPU IPU IPU IPU IPD
IPD
IPD
Clk used for PEG and DMI
IPU
RESERVED
NB_CFG<6>
High = DMIx4
NB_CFG<7>
RESERVED RESERVED
RESERVED
High = Normal Low = Reversed
NB_CFG<10>
NB_CFG<9>
PCIe Graphics Lane Reversal
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
See Below
See Below
Low = Disabled
High = Enabled
10 = All-Z Mode Enabled
01 = XOR Mode Enabled
Low = Normal
High = Both active
NB_CFG<13:12>
Low = Only SDVO
High = Reversed
11 = Normal Operation
or PCIe x16
00 = RESERVED
NB_CFG<19>
NB_CFG<20>
Concurrent SDVO/PCIe x1
Reversal
DMI Lane
NB_CFG<13>
NB_CFG<12>
NB_CFG<11>
NB_CFG<16>
NB_CFG<14>
NB_CFG<17>
ODT
FSB Dynamic
NB_CFG<15>
NB_CFG<18>
PP1V05_S0M, PP0V9_S3M and PP0V9_S0M. If ME/AMT is not used, short CL_PWROK to PWROK.
PP3V3_S0M, PP3V3_S0MWOL, PP1V8_S3M, PP1V25_S0M,
NOTE: GMCH CL_PWROK input must be PWRGD signal for
DMI x2 Select
NB_CFG<5>
NB_CFG<4>
IPU
IPU
NB CFG<8:0> used for debug access
7
28
8
402
CERM
20%
0.1uF
10V
402
CERM
20%
0.1uF
10V
CRESTLINE
FCBGA
OMIT
9
9
9
9
9
25 83
25 83
9
25 83
22
22
7
29
7
25
402
20K
MF-LF
1/16W
5%
402
0
MF-LF
1/16W
5%
7
25 58 79
32 45
402
10K
MF-LF
5% 1/16W
0.01UF
10% 16V
CERM
402 603
2.2UF
6.3V CERM1
20%
1K
MF-LF
1% 1/16W
402
402
1% 1/16W MF-LF
3.01K
603
6.3V CERM1
2.2UF
20%
0.01UF
10% 16V
CERM
402
1K
402
1/16W
1% MF-LF
402
392
MF-LF
1/16W
1%
402
MF-LF
1/16W
1K
1%
402
20% 10V
CERM
0.1uF
402
5%
3.9K
MF-LF
1/16W
NBCFG_DMI_X2
402
5% 1/16W MF-LF
3.9K
NBCFG_PEG_REVERSE
402
NBCFG_DYN_ODT_DISABLE
3.9K
1/16W
5% MF-LF
402
3.9K
MF-LF
1/16W
5%
NBCFG_DMI_REVERSE
402
5% 1/16W MF-LF
3.9K
NBCFG_SDVO_AND_PCIE
9
31 33 81
32 33 81
13 30 79
13 30 79
13 30 79
13
13
13
13
13 16
25
13
10 23 46 79
31 45
7
10 23 58 79
7 9
28 58
31 81
32 81
32 81
31 81
31 81
32 81
32 81
31 81
31 33 81
31 33 81
32 33 81
31 33 81
32 33 81
31 33 81
32 33 81
32 33 81
31 33 81
31 33 81
32 33 81
32 33 81
MF-LF
1/16W
1%
20
402
1/16W
1%
MF-LF
20
402
8
7
30 84
7
30 84
22
22
22
22
24 80
24 80
24 80
24 80
24 80
24 80
24 80
24 80
24 80
24 80
24 80
24 80
24 80
24 80
24 80
24 80
402
MF-LF
1/16W
5%
10K
051-7225
A.0.0
8816
SYNC_MASTER=T9_NOME
SYNC_DATE=03/16/2007
NB Misc Interfaces
MEM_RCOMP_VOH
=PP1V8_S3M_MEM_NB
MEM_RCOMP
MEM_RCOMP_VOL
=PP0V9_S3M_MEM_NBVREFA
MEM_CKE<3>
MEM_CKE<1>
NB_CFG<4>
TP_NB_RSVD<44>
TP_NB_RSVD<43>
MEM_RCOMP_L
NB_CFG<5>
NB_CFG<9>
NB_CFG<8>
NB_CFG<7>
NB_CFG<6>
NB_CFG<3>
NB_BSEL<1> NB_BSEL<2>
NB_CLINK_VREF
GFX_VID<0>
PP1V25_S0M_NB_VCCAXD
CLINK_NB_CLK
GFX_VID<1>
TP_NB_CFG<17>
=PP3V3_S0_NB_VCCHV
=GFX_VR_EN
GFX_VID<3>
TP_NB_CFG<13>
TP_NB_CFG<11>
=PP3V3_S0_NB_VCCHV
NB_CFG<20>
NB_CFG<19>
=PP3V3_S0_NB_VCCHV
NB_CFG<16>
NB_CFG<9>
PM_EXTTS_L<1>
NB_RESET_L
PM_DPRSLPVR
TP_NB_RSVD<14>
DMI_S2N_N<1>
DMI_S2N_N<3>
TP_NB_RSVD<42>
TP_NB_RSVD<45>
TP_LVDS_B_DATAN3
TP_NB_RSVD<36>
TP_NB_RSVD<35>
DMI_S2N_N<0>
MEM_A_A<14>
TP_LVDS_B_DATAP3
TP_LVDS_A_DATAN3
TP_MEM_CLKP2
TP_NB_RSVD<24>
TP_NB_RSVD<5>
=PP0V9_S3M_MEM_NBVREFB
DMI_S2N_N<2>
DMI_S2N_P<3>
GFX_VID<4>
TP_NB_NC<4>
TP_NB_RSVD<12>
TP_NB_RSVD<6>
MEM_ODT<1>
MEM_ODT<0>
MEM_CS_L<3>
=NB_CLK96M_DOT_N
MEM_ODT<3>
MEM_ODT<2>
MEM_CS_L<2>
PM_THRMTRIP_L
VR_PWRGOOD_DELAY
CPU_DPRSTP_L
PM_BMBUSY_L
TP_MEM_CLKN5
TP_MEM_CLKP5
TP_MEM_CLKN2
NB_SB_SYNC_L
NB_CLKREQ_L
SDVO_CTRLDATA
SDVO_CTRLCLK
CLINK_NB_RESET_L
=NB_CLINK_MPWROK
CLINK_NB_DATA
GFX_VID<2>
DMI_N2S_P<3>
DMI_N2S_P<2>
DMI_N2S_P<1>
DMI_N2S_P<0>
DMI_N2S_N<2> DMI_N2S_N<3>
DMI_N2S_N<1>
DMI_N2S_N<0>
DMI_S2N_P<2>
DMI_S2N_P<1>
DMI_S2N_P<0>
NB_CLK100M_PCIE_N
NB_CLK100M_PCIE_P
=NB_CLK96M_DOT_P
TP_NB_NC<1>
TP_NB_NC<8>
TP_NB_RSVD<4>
TP_NB_RSVD<3>
TP_NB_RSVD<7>
MEM_CLK_N<0>
MEM_CLK_P<1>
MEM_CLK_N<1>
MEM_CKE<0>
MEM_CS_L<1>
MEM_CS_L<0>
TP_NB_RSVD<11>
TP_NB_RSVD<10>
TP_NB_RSVD<9>
TP_NB_RSVD<8>
TP_NB_RSVD<2>
NB_TEST1 NB_TEST2
TP_NB_RSVD<20> TP_NB_RSVD<21> TP_NB_RSVD<22> TP_NB_RSVD<23>
TP_NB_RSVD<41>
TP_NB_CFG<10>
TP_NB_CFG<12>
NB_CFG<16>
TP_NB_CFG<15>
TP_NB_CFG<14>
TP_NB_CFG<18> NB_CFG<19> NB_CFG<20>
PM_EXTTS_L<0>
TP_NB_NC<2> TP_NB_NC<3>
TP_NB_NC<5>
TP_NB_NC<7>
TP_NB_NC<6>
TP_NB_NC<10>
TP_NB_NC<9>
TP_NB_NC<12>
TP_NB_NC<11>
TP_NB_NC<13> TP_NB_NC<14> TP_NB_NC<15> TP_NB_NC<16>
TP_NB_RSVD<13>
MEM_CLK_P<3> MEM_CLK_P<4>
MEM_CLK_N<3> MEM_CLK_N<4>
MEM_CLK_P<0>
TP_NB_RSVD<1>
MEM_CKE<4>
NB_CFG<5>
NB_BSEL<0>
=NB_CLK100M_DPLLSS_N
=NB_CLK100M_DPLLSS_P
TP_NB_RSVD<25> TP_NB_RSVD<26> TP_NB_RSVD<27>
MEM_B_A<14> TP_NB_RSVD<34>
TP_LVDS_A_DATAP3
R1610
1
2
R1611
1
2
R1630
1
2
C1616
1
2
C1615
1
2
U1400
P27 N27
R24 L23 J23 E23 E20 K23 M20 M24 L32 N33
N24
L35
C21 C23 F23 N23 G23 J20 C20
AM49 AK50 AT43 AN49 AM50
G39
AN47 AJ38 AN42 AN46
AM47 AJ39 AN41 AN45
AJ46 AJ41 AM40 AM44
AJ47 AJ42 AM39 AM43
B42 C42 H48 H47
G36
E35 A39 C38 B39 E36
G40
BJ51
E1
A5 C51 B50 A50 A49 BK2
BK51 BK50 BL50 BL49
BL3 BL2 BK1 BJ1
K44 K45
G41 L39 L36 J36
AW49 AV20
P36
AR37 AM36 AL36 AM37
D20
P37
H10 B51
BJ20 BK22 BF19 BH20 BK18 BJ18
R35
BH39 AW20 BK20
C48 D47 B44
N35
C44 A35 B37 B36 B34 C34
AR12 AR13 AM12 AN13
J12
BJ29 BE24
H35 K36
AV29
AW30
BB23
BA23
BF23 BG23
BA25
AW25
AV23
AW23
BC23 BD24
BE29 AY32 BD39 BG37
BG20 BK16 BG16 BE13
BH18 BJ15 BJ14 BE16
BL15 BK14
BK31 BL31
AR49 AW4
A37 R32
N20
R1691
1
2
R1690
1
2
R1631
1
2
C1625
1
2
C1624
1
2
R1624
1
2
R1622
1
2
C1622
1
2
C1623
1
2
R1620
1
2
R1641
1
2
R1640
1
2
C1640
1
2
R1655
1
2
R1659
1
2
R1666
1
2
R1669
1
2
R1670
1
2
21
21
21
21
19
19
19
18
21
16
16
16
16
8
16
83
19
8
8
16
16
8
16
16
7
7
7
16
16
16
7
7
7
7
7
7
7
7
7
7
7
7
7
13
BI
BI BI BI BI BI
OUT
OUT
OUT
OUT
OUT
BI
OUT
OUT
BI BI BI
BI
BI BI BI BI
BI BI
BI BI BI BI BI
BI BI BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI BI BI
BI
BI
BI BI BI BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI BI BI BI BI
BI BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
BI
OUT
OUT OUT
OUT
OUT
OUT
OUT OUT
OUT
OUT
BI
OUT
OUT
OUT
BI
BI
BI BI BI
BI
BI
BI
BI BI BI
BI BI
BI
BI BI
OUT
BI
BI
OUT OUT
OUT OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
OUT
SA_DQ0 SA_DQ1 SA_DQ2
SA_DQ4
SA_DQ6
SA_DQ14
SA_CAS*
SA_BS2
SA_DQ63
SA_DQ62
SA_DQ61
SA_DQ60
SA_DQ59
SA_DQ58
SA_DQ57
SA_DQ56
SA_DQ55
SA_DQ54
SA_DQ53
SA_DQ52
SA_DQ51
SA_DQ50
SA_DQ49
SA_DQ48
SA_DQ47
SA_DQ46
SA_DQ44
SA_DQ43
SA_DQ42
SA_DQ41
SA_DQ40
SA_DQ39
SA_DQ38
SA_DQ37
SA_DQ36
SA_DQ34 SA_DQ35
SA_DQ33
SA_DQ32
SA_DQ31
SA_DQ30
SA_DQ28 SA_DQ29
SA_DQ27
SA_DQ26
SA_DQ25
SA_DQ24
SA_DQ23
SA_DQ22
SA_DQ21
SA_DQ20
SA_DQ19
SA_DQ18
SA_DQ17
SA_DQ16
SA_DQ15
SA_DQ13
SA_DQ11 SA_DQ12
SA_DQ10
SA_DQ9
SA_DQ8
SA_DQ7
SA_DQ5
SA_DQ3
SA_BS1
SA_BS0
SA_DQ45
SA_DM0 SA_DM1
SA_DM3
SA_DM2
SA_DM5
SA_DM4
SA_DM7
SA_DM6
SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7
SA_DQS1*
SA_DQS0*
SA_DQS2*
SA_DQS4*
SA_DQS3*
SA_DQS5* SA_DQS6* SA_DQS7*
SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7
SA_MA9
SA_MA8
SA_MA10 SA_MA11 SA_MA12 SA_MA13
SA_RAS*
SA_RCVEN*
SA_WE*
DDR SYSTEM MEMORY A
(4 OF 10)
SB_DQ2
SB_DQ1
SB_DQ5
SB_DM0
SB_DQ0
SB_DQ4
SB_DQ6 SB_DQ7
SB_CAS*
SB_BS2
SB_BS0 SB_BS1
SB_DQ63
SB_DQ62
SB_DQ59
SB_DQ58
SB_DQ56
SB_DQ55
SB_DQ54
SB_DQ53
SB_DQ52
SB_DQ51
SB_DQ50
SB_DQ49
SB_DQ48
SB_DQ47
SB_DQ45 SB_DQ46
SB_DQ44
SB_DQ43
SB_DQ42
SB_DQ41
SB_DQ40
SB_DQ39
SB_DQ38
SB_DQ37
SB_DQ36
SB_DQ34 SB_DQ35
SB_DQ33
SB_DQ32
SB_DQ31
SB_DQ30
SB_DQ28 SB_DQ29
SB_DQ27
SB_DQ26
SB_DQ25
SB_DQ24
SB_DQ23
SB_DQ22
SB_DQ21
SB_DQ20
SB_DQ19
SB_DQ18
SB_DQ17
SB_DQ16
SB_DQ15
SB_DQ14
SB_DQ13
SB_DQ11 SB_DQ12
SB_DQ10
SB_DQ9
SB_DQ8
SB_DQ3
SB_DQ57
SB_DQ61
SB_DQ60
SB_WE*
SB_RCVEN*
SB_RAS*
SB_MA13
SB_MA12
SB_MA11
SB_MA10
SB_MA8 SB_MA9
SB_MA7
SB_MA6
SB_MA5
SB_MA4
SB_MA3
SB_MA2
SB_MA1
SB_MA0
SB_DQS7*
SB_DQS6*
SB_DQS5*
SB_DQS3* SB_DQS4*
SB_DQS2*
SB_DQS0* SB_DQS1*
SB_DQS7
SB_DQS6
SB_DQS5
SB_DQS4
SB_DQS3
SB_DQS2
SB_DQS1
SB_DQS0
SB_DM6 SB_DM7
SB_DM4 SB_DM5
SB_DM2 SB_DM3
SB_DM1
(5 OF 10)
DDR SYSTEM MEMORY B
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT OUT OUT
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI BI BI BI BI BI BI BI BI BI
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
32 81
32 81
32 81
32 81
32 81
32 81
32 81
32 81
31 81 32 81
32 81
32 81
32 81
32 81
32 81
32 81
32 81
32 81
32 81
31 81
32 81
32 81
32 81
32 81
32 81
32 81
32 81
32 81
32 81
32 81
31 81
32 81
32 81
32 81
32 81
32 81
32 81
32 81
32 81
32 81
32 81
31 81
32 81
32 81
32 81
32 81
32 81
32 81
32 81
32 81
32 81
32 81
31 81
32 81
32 81
32 81
32 81
32 81
32 81
32 81
32 81
32 81
31 81
32 81
32 81
32 81
32 81
32 81
32 81
32 81
32 33 81
32 33 81
32 33 81
31 81
32 33 81
32 33 81
32 33 81
32 33 81
32 33 81
32 33 81
32 33 81
32 33 81
32 33 81
32 33 81
31 81
32 33 81
32 33 81
32 33 81
32 81
32 81
32 81
32 81
32 81
32 81
32 81
31 81
32 81
32 81
32 81
32 81
32 81
32 81
32 81
32 81
32 81
32 81
31 81
32 81
32 81
32 81
32 81
32 81
32 81
32 81
32 33 81
32 33 81
32 33 81
31 81
32 33 81
FCBGA
CRESTLINE
OMIT
FCBGA
CRESTLINE
OMIT
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 33 81
31 33 81
31 33 81
31 81
31 33 81
31 81
31 33 81
31 33 81
31 33 81
31 33 81
31 33 81
31 33 81
31 33 81
31 81
31 33 81
31 33 81
31 33 81
31 33 81
31 33 81
31 33 81
31 33 81
31 33 81
31 33 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
31 81
SYNC_DATE=03/16/2007
SYNC_MASTER=T9_NOME
NB DDR2 Interfaces
051-7225
A.0.0
8817
MEM_A_DQ<63>
MEM_A_DQ<62>
MEM_A_DQ<61>
MEM_A_DQ<60>
MEM_A_DQ<59>
MEM_A_DQ<58>
MEM_A_DQ<57>
MEM_A_DQ<56>
MEM_A_DQ<55>
MEM_A_DQ<54>
MEM_A_DQ<53>
MEM_A_DQ<52>
MEM_A_DQ<51>
MEM_A_DQ<50>
MEM_A_DQ<49>
MEM_A_DQ<48>
MEM_A_DQ<47>
MEM_A_DQ<46>
MEM_A_DQ<45>
MEM_A_DQ<44>
MEM_A_DQ<43>
MEM_A_DQ<42>
MEM_A_DQ<41>
MEM_A_DQ<40>
MEM_A_DQ<39>
MEM_A_DQ<38>
MEM_A_DQ<37>
MEM_A_DQ<36>
MEM_A_DQ<34>
MEM_A_DQ<33>
MEM_A_DQ<32>
MEM_A_DQ<31>
MEM_A_DQ<30>
MEM_A_DQ<29>
MEM_A_DQ<28>
MEM_A_DQ<27>
MEM_A_DQ<26>
MEM_A_DQ<25>
MEM_A_DQ<24>
MEM_A_DQ<23>
MEM_A_DQ<22>
MEM_A_DQ<21>
MEM_A_DQ<20>
MEM_A_DQ<19>
MEM_A_DQ<18>
MEM_A_DQ<17>
MEM_A_DQ<16>
MEM_A_DQ<15>
MEM_A_DQ<14>
MEM_A_DQ<13>
MEM_A_DQ<12>
MEM_A_DQ<11>
MEM_A_DQ<10>
MEM_A_DQ<9>
MEM_A_WE_L
MEM_A_RAS_L
MEM_A_A<13>
MEM_A_A<12>
MEM_A_A<11>
MEM_A_A<10>
MEM_A_A<8> MEM_A_A<9>
MEM_A_A<7>
MEM_A_A<6>
MEM_A_A<5>
MEM_A_A<4>
MEM_A_A<3>
MEM_A_A<2>
MEM_A_A<1>
MEM_A_A<0>
MEM_A_DQS_N<7>
MEM_A_DQS_N<6>
MEM_A_DQS_N<5>
MEM_A_DQS_N<3> MEM_A_DQS_N<4>
MEM_A_DQS_N<2>
MEM_A_DQS_N<0> MEM_A_DQS_N<1>
MEM_A_DQS_P<7>
MEM_A_DQS_P<6>
MEM_A_DQS_P<5>
MEM_A_DQS_P<4>
MEM_A_DQS_P<3>
MEM_A_DQS_P<2>
MEM_A_DQS_P<1>
MEM_A_DQS_P<0>
MEM_A_DM<6> MEM_A_DM<7>
MEM_A_DM<4> MEM_A_DM<5>
MEM_A_DM<2> MEM_A_DM<3>
MEM_A_DM<1>
MEM_A_DM<0>
MEM_A_BS<0> MEM_A_BS<1>
MEM_A_DQ<3>
MEM_A_DQ<5>
MEM_A_DQ<7> MEM_A_DQ<8>
MEM_A_BS<2> MEM_A_CAS_L
MEM_A_DQ<6>
MEM_A_DQ<4>
MEM_A_DQ<2>
MEM_A_DQ<1>
MEM_A_DQ<0>
MEM_B_DQ<63>
MEM_B_DQ<62>
MEM_B_DQ<61>
MEM_B_DQ<60>
MEM_B_DQ<59>
MEM_B_DQ<58>
MEM_B_DQ<57>
MEM_B_DQ<56>
MEM_B_DQ<55>
MEM_B_DQ<54>
MEM_B_DQ<53>
MEM_B_DQ<52>
MEM_B_DQ<51>
MEM_B_DQ<50>
MEM_B_DQ<49>
MEM_B_DQ<48>
MEM_B_DQ<47>
MEM_B_DQ<46>
MEM_B_DQ<45>
MEM_B_DQ<44>
MEM_B_DQ<43>
MEM_B_DQ<42>
MEM_B_DQ<41>
MEM_B_DQ<40>
MEM_B_DQ<38>
MEM_B_DQ<37>
MEM_B_DQ<36>
MEM_B_DQ<35>
MEM_B_DQ<34>
MEM_B_DQ<33>
MEM_B_DQ<32>
MEM_B_DQ<31>
MEM_B_DQ<30>
MEM_B_DQ<29>
MEM_B_DQ<28>
MEM_B_DQ<27>
MEM_B_DQ<26>
MEM_B_DQ<25>
MEM_B_DQ<24>
MEM_B_DQ<23>
MEM_B_DQ<22>
MEM_B_DQ<21>
MEM_B_DQ<20>
MEM_B_DQ<19>
MEM_B_DQ<18>
MEM_B_DQ<17>
MEM_B_DQ<16>
MEM_B_DQ<15>
MEM_B_DQ<14>
MEM_B_DQ<13>
MEM_B_DQ<12>
MEM_B_DQ<11>
MEM_B_DQ<10>
MEM_B_DQ<9>
MEM_B_WE_L
MEM_B_A<13>
MEM_B_RAS_L
MEM_B_A<12>
MEM_B_A<11>
MEM_B_A<10>
MEM_B_A<9>
MEM_B_A<8>
MEM_B_A<7>
MEM_B_A<6>
MEM_B_A<5>
MEM_B_A<4>
MEM_B_A<3>
MEM_B_A<2>
MEM_B_A<1>
MEM_B_A<0>
MEM_B_DQS_N<7>
MEM_B_DQS_N<5> MEM_B_DQS_N<6>
MEM_B_DQS_N<4>
MEM_B_DQS_N<2> MEM_B_DQS_N<3>
MEM_B_DQS_N<0>
MEM_B_DQS_P<7>
MEM_B_DQS_N<1>
MEM_B_DQS_P<5> MEM_B_DQS_P<6>
MEM_B_DQS_P<2> MEM_B_DQS_P<3> MEM_B_DQS_P<4>
MEM_B_DQS_P<0> MEM_B_DQS_P<1>
MEM_B_DM<7>
MEM_B_DM<6>
MEM_B_DM<5>
MEM_B_DM<4>
MEM_B_DM<3>
MEM_B_DQ<8>
MEM_B_DQ<7>
MEM_B_DQ<6>
MEM_B_DQ<5>
MEM_B_DQ<4>
MEM_B_DQ<3>
MEM_B_DQ<2>
MEM_B_DQ<1>
MEM_B_DQ<0>
MEM_B_DM<2>
MEM_B_DM<1>
MEM_B_CAS_L
MEM_B_DM<0>
MEM_B_BS<2>
MEM_B_BS<1>
MEM_B_BS<0>
MEM_B_DQ<39>
TP_MEM_B_RCVEN_LTP_MEM_A_RCVEN_L
MEM_A_DQ<35>
U1400
BB19 BK19 BF29
BL17
AT45 BD44 BD42 AW38 AW13 BG8 AY5 AN6
AR43 AW44
BG47 BJ45 BB47 BG50 BH49 BE45 AW43 BE44 BG42 BE40
BA45
BF44 BH45 BG40 BF40 AR40 AW40 AT39 AW36 AW41 AY41
AY46
AV38 AT38 AV13 AT13 AW11 AV11 AU15 AT11 BA13 BA11
AR41
BE10 BD10
BD8 AY9
BG10
AW9 BD7 BB9 BB5 AY7
AR45
AT5 AT7 AY6 BB7 AR5 AR8 AR9 AN3 AM8
AN10
AT42
AT9 AN9 AM9
AN11
AW47 BB45 BF48
AT46
AT47
BE48
BD47
BB43
BC41
BC37
BA37
BB16
BA16
BH6
BH7
BB2
BC1
AP3
AP2
BJ19 BD20
BC19 BE28 BG30 BJ16
BK27 BH28 BL24 BK28 BJ27 BJ25 BL28 BA28
BE18 AY20
BA19
U1400
AY17 BG18 BG36
BE17
AR50 BD49 BK45 BL39 BH12 BJ7 BF3 AW2
AP49 AR51
BA49 BE50 BA51 AY49 BF50 BF49 BJ50 BJ44 BJ43 BL43
AW50
BK47 BK49 BK43 BK42 BJ41 BL41 BJ37 BJ36 BK41 BJ40
AW51
BL35 BK37 BK13 BE11 BK11 BC11 BC13 BE12 BC12 BG12
AN51
BJ10
BL9 BK5 BL5 BK9
BK10
BJ8 BJ6 BF4 BH5
AN50
BG1 BC2 BK3 BE4 BD3 BJ2 BA3 BB3 AR1 AT3
AV50
AY2 AY3 AU2 AT2
AV49 BA50 BB50
AT50
AU50
BD50
BC50
BK46
BL45
BK39
BK38
BJ12
BK12
BL7
BK7
BE2
BF2
AV2
AV3
BC18 BG28
BG17 BE37 BA39 BG13
BG25 AW17 BF25 BE25 BA29 BC28 AY28 BD37
AV16 AY18
BC17
VCC_SM20
VCC_AXG_NCTF42
VCC_SM9 VCC_SM10
VCC_SM17
VCC_SM16
VCC3
VCC_SM5
VCC_SM8
VCC_AXG_NCTF1 VCC_AXG_NCTF2 VCC_AXG_NCTF3 VCC_AXG_NCTF4 VCC_AXG_NCTF5 VCC_AXG_NCTF6
VCC_AXG_NCTF8
VCC_AXG_NCTF7
VCC_AXG_NCTF10
VCC_AXG_NCTF9
VCC_AXG_NCTF11 VCC_AXG_NCTF12 VCC_AXG_NCTF13 VCC_AXG_NCTF14 VCC_AXG_NCTF15 VCC_AXG_NCTF16
VCC_AXG_NCTF18
VCC_AXG_NCTF17
VCC_AXG_NCTF20
VCC_AXG_NCTF19
VCC_AXG_NCTF21 VCC_AXG_NCTF22
VCC_AXG_NCTF25 VCC_AXG_NCTF26
VCC_AXG_NCTF28
VCC_AXG_NCTF27
VCC_AXG_NCTF29 VCC_AXG_NCTF20 VCC_AXG_NCTF31 VCC_AXG_NCTF32 VCC_AXG_NCTF33 VCC_AXG_NCTF34 VCC_AXG_NCTF35 VCC_AXG_NCTF36
VCC_AXG_NCTF38
VCC_AXG_NCTF37
VCC_AXG_NCTF40
VCC_AXG_NCTF39
VCC_AXG_NCTF41
VCC_AXG_NCTF43 VCC_AXG_NCTF44 VCC_AXG_NCTF45 VCC_AXG_NCTF46
VCC_AXG_NCTF48
VCC_AXG_NCTF47
VCC_AXG_NCTF49 VCC_AXG_NCTF50 VCC_AXG_NCTF51
VCC_AXG_NCTF55
VCC_AXG_NCTF58
VCC_AXG_NCTF57
VCC_AXG_NCTF59
VCC_AXG_NCTF61
VCC_AXG_NCTF60
VCC_AXG_NCTF62 VCC_AXG_NCTF63 VCC_AXG_NCTF64
VCC_AXG_NCTF66
VCC_AXG_NCTF65
VCC_AXG_NCTF67 VCC_AXG_NCTF68 VCC_AXG_NCTF69
VCC_AXG_NCTF71
VCC_AXG_NCTF70
VCC_AXG_NCTF72 VCC_AXG_NCTF73 VCC_AXG_NCTF74
VCC_AXG_NCTF76
VCC_AXG_NCTF75
VCC_AXG_NCTF77 VCC_AXG_NCTF78 VCC_AXG_NCTF79
VCC_AXG_NCTF81
VCC_AXG_NCTF80
VCC_AXG_NCTF82 VCC_AXG_NCTF83
VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7
VCC_AXG_NCTF56
VCC_AXG_NCTF54
VCC_AXG_NCTF53
VCC_AXG_NCTF52
VCC_AXG1 VCC_AXG2 VCC_AXG3 VCC_AXG4 VCC_AXG5 VCC_AXG6 VCC_AXG7 VCC_AXG8 VCC_AXG9 VCC_AXG10 VCC_AXG11 VCC_AXG12 VCC_AXG13 VCC_AXG14 VCC_AXG15 VCC_AXG16 VCC_AXG17 VCC_AXG18 VCC_AXG19 VCC_AXG20 VCC_AXG21 VCC_AXG22 VCC_AXG23 VCC_AXG24 VCC_AXG25 VCC_AXG26 VCC_AXG27 VCC_AXG28 VCC_AXG29 VCC_AXG30 VCC_AXG31 VCC_AXG32 VCC_AXG33 VCC_AXG34
VCC_SM1 VCC_SM2 VCC_SM3 VCC_SM4
VCC_SM6 VCC_SM7
VCC_SM11 VCC_SM12 VCC_SM13 VCC_SM14 VCC_SM15
VCC_SM18 VCC_SM19
VCC_SM21 VCC_SM22 VCC_SM23
VCC_SM26 VCC_SM27 VCC_SM28 VCC_SM29 VCC_SM30 VCC_SM31 VCC_SM32 VCC_SM33 VCC_SM34 VCC_SM35 VCC_SM36
VCC_SM25
VCC_SM24
VCC1 VCC2
VCC7 VCC8 VCC9 VCC10 VCC11 VCC12
VCC13
VCC_AXG_NCTF24
VCC_AXG_NCTF23
VCC6
VCC5 VCC4
VCC GFX
VCC SM
VCC SM LF
(6 OF 10)
VCC CORE
POWER
VCC GFX NCTF
VCC_NCTF49
VCC_NCTF15
VCC_NCTF2
VCC_NCTF10
VCC_AXM7
VCC_AXM5
VCC_AXM4
VCC_AXM3
VCC_AXM2
VCC_AXM1
VSS_SCB6
VSS_SCB5
VSS_SCB4
VSS_SCB3
VSS_SCB2
VSS_SCB1
VCC_NCTF11 VCC_NCTF12 VCC_NCTF13 VCC_NCTF14
VSS_NCTF21
VSS_NCTF20
VSS_NCTF19
VSS_NCTF18
VSS_NCTF17
VSS_NCTF16
VSS_NCTF15
VSS_NCTF14
VSS_NCTF12
VSS_NCTF11
VSS_NCTF13
VSS_NCTF10
VSS_NCTF9
VSS_NCTF8
VSS_NCTF7
VSS_NCTF6
VSS_NCTF5
VSS_NCTF4
VSS_NCTF3
VSS_NCTF2
VSS_NCTF1
VCC_NCTF22
VCC_NCTF27
VCC_NCTF50
VCC_NCTF47 VCC_NCTF48
VCC_NCTF44
VCC_NCTF43
VCC_NCTF39 VCC_NCTF40
VCC_NCTF38
VCC_NCTF37
VCC_NCTF34 VCC_NCTF35
VCC_NCTF33
VCC_NCTF32
VCC_NCTF31
VCC_NCTF29
VCC_NCTF28
VCC_NCTF26
VCC_NCTF24 VCC_NCTF25
VCC_NCTF23
VCC_NCTF21
VCC_NCTF18 VCC_NCTF19
VCC_NCTF16 VCC_NCTF17
VCC_NCTF3 VCC_NCTF4
VCC_NCTF41 VCC_NCTF42
VCC_NCTF45 VCC_NCTF46
VCC_AXM6
VCC_AXM_NCTF1 VCC_AXM_NCTF2 VCC_AXM_NCTF3 VCC_AXM_NCTF4 VCC_AXM_NCTF5 VCC_AXM_NCTF6 VCC_AXM_NCTF7 VCC_AXM_NCTF8 VCC_AXM_NCTF9 VCC_AXM_NCTF10 VCC_AXM_NCTF11 VCC_AXM_NCTF12 VCC_AXM_NCTF13 VCC_AXM_NCTF14 VCC_AXM_NCTF15 VCC_AXM_NCTF16 VCC_AXM_NCTF17 VCC_AXM_NCTF18 VCC_AXM_NCTF19
VCC_NCTF8
VCC_NCTF20
VCC_NCTF1
VCC_NCTF5 VCC_NCTF6 VCC_NCTF7
VCC_NCTF36
VCC_NCTF30
VCC_NCTF9
VCC AXM NCTF
VCC NCTF
VSS SCBVCC AXM
VSS NCTF
(7 OF 10)
POWER
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
Current numbers from Crestline EDS, doc #21749.
NCTF balls are Not Critical To Function
These connections can break without
impacting part performance.
5 mA (standby)
7700 mA (Int Graphics)
1310 mA (Ext Graphics) 1573 mA (Int Graphics)
540 mA
3300 mA (2 ch, 667MHz) 2700 mA (2 ch, 533MHz) 1700 mA (1 ch, 667MHz) 1395 mA (1 ch, 533MHz)
FCBGA
CRESTLINE
OMIT
FCBGA
CRESTLINE
OMIT
20%
CERM
10V
0.1uF
402
20%
CERM
10V
0.1uF
402
20%
6.3V
0.22UF
X5R 402
20%
6.3V
0.22UF
X5R 402
6.3V
1uF
CERM
10%
402
CERM-X5R
6.3V
0.47UF
10%
402
6.3V
1uF
CERM
10%
402
SYNC_MASTER=T9_NOME
SYNC_DATE=03/16/2007
NB Power 1
051-7225
A.0.0
8818
=PP1V8_S3M_MEM_NB
=PPVCORE_S0_NB_GFX
=PPVCORE_S0_NB
=PPVCORE_S0_NB_GFX
NB_VCCSM_LF6
NB_VCCSM_LF4
NB_VCCSM_LF3
NB_VCCSM_LF2
NB_VCCSM_LF1
=PP1V05_S0M_NB_VCCAXM
=PPVCORE_S0_NB
NB_VCCSM_LF7
NB_VCCSM_LF5
=PP1V05_S0M_NB_VCCAXM
U1400
AT35
AH31 AH29 AF32
R30
AT34 AH28
AC31
AC32
AK32 AJ31 AJ28 AH32
R20
AB21 AB24 AB29 AC20 AC21 AC23 AC24 AC26 AC28 AC29
T14
AD20 AD23 AD24 AD28 AF21 AF26 AA31 AH20 AH21 AH23
W13
AH24 AH26 AD31 AJ20 AN14
W14
Y12 AA20 AA23 AA26 AA28
T17
U17 U19 U20 U21 U23 U26 V16 V17 V19 V20
T18
V21 V23 V24 Y15 Y16 Y17 Y19 Y20 Y21 Y23
T19
Y24 Y26 Y28 Y29 AA16 AA17 AB16 AB19 AC16 AC17
T21
AC19 AD15 AD16 AD17 AF16 AF19 AH15 AH16 AH17 AH19
T22
AJ16 AJ17 AJ19 AK16 AK19 AL16 AL17 AL19 AL20 AL21
T23
AL23 AM15 AM16 AM19 AM20 AM21 AM23 AP15 AP16 AP17
T25
AP19 AP20 AP21 AP23 AP24 AR20 AR21 AR23 AR24 AR26
U15
V26 V28 V29 Y31
U16
AU32
BA35 BB33 BC32 BC33 BC35 BD32 BD35 BE32 BE33 BE35
AU33
BF33 BF34 BG32 BG33 BG35 BH32 BH34 BH35 BJ32 BJ33
AU35
BJ34 BK32 BK33 BK34 BK35 BL33 AU30
AV33 AW33 AW35 AY35 BA32 BA33
AW45 BC39 BE39 BD17 BD4 AW8 AT6
U1400
AT33 AT31 AK29 AK24 AK23 AJ26 AJ23
AL24
AP29 AP31 AP32 AP33 AL29 AL31 AL32 AR31 AR32 AR33
AL26 AL28 AM26 AM28 AM29 AM31 AM32 AM33
AB33
AF36 AH33 AH35 AH36 AH37 AJ33 AJ35 AK33 AK35 AK36
AB36
AK37 AD33 AJ36 AM35 AL33 AL35 AA33 AA35 AA36 AP35
AB37
AP36 AR35 AR36
Y32 Y33 Y35 Y36 Y37 T30 T34
AC33
T35 U29 U31 U32 U33 U35 U36 V32 V33 V36
AC35
V37
AC36 AD35 AD36 AF33
T27
AD19 AD37 AF17 AF35 AK17 AM17 AM24 AP26 AP28 AR15
T37
AR19 AR28
U24 U28 V31 V35 AA19 AB17 AB35
A3 B2 C1 BL1 BL51 A51
C1806
1
2
C1807
1
2
C1804
1
2
C1805
1
2
C1802
1
2
C1803
1
2
C1801
1
2
22
22
21
22 21
22
21
21
21
16
18 18
18
18
18
18
8
8 8
8
8
8
8
VCCA_CRT_DAC1
VTT7 VTT8
VCC_AXD_NCTF
VCCD_CRT
VCC_RXR_DMI1 VCC_RXR_DMI2
VTT1
VCCA_SM_CK2 VCC_TX_LVDS
VCC_HV2
VCC_PEG1 VCC_PEG2 VCC_PEG3
VCC_AXF2
VCC_AXD1 VCC_AXD2
VSSA_LVDS
VCCA_SM5
VCCA_PEG_PLL
VCCA_MPLL
VCCA_HPLL VTT16
VTT17
VTT15
VCCD_LVDS2
VCCD_LVDS1
VCCD_PEG_PLL
VCCD_HPLL
VCCD_QDAC
VCCD_TVDAC
VCCA_TVC_DAC1 VCCA_TVC_DAC2
VCCA_TVB_DAC2
VCCA_TVB_DAC1
VCCA_TVA_DAC2
VCCA_TVA_DAC1
VCCA_SM_CK1
VCCA_SM2
VCCA_SM1
VCCA_SM_NCTF2
VCCA_SM_NCTF1
VCCA_SM11
VCCA_SM10
VCCA_SM9
VCCA_SM8
VCCA_SM7
VCCA_SM4
VCCA_SM3
VSSA_PEG_BG
VCCA_PEG_BG
VCCA_LVDS
VCCA_DPLLB
VCCA_DPLLA
VSSA_DAC_BG
VCCA_DAC_BG
VCC_AXF3
VCC_HV1
VCC_PEG5
VTTLF1
VTTLF3
VTTLF2
VCC_PEG4
VCC_SM_CK3
VCC_SM_CK2
VCC_SM_CK1
VCC_SM_CK4
VCC_DMI
VCC_AXF1
VTT22
VCC_AXD6
VCC_AXD5
VCC_AXD4
VCC_AXD3
VTT19
VTT2
VTT6
VTT5
VTT11
VTT10
VTT9
VTT13
VTT12
VTT14
VTT18
VTT21
VTT20
VTT3 VTT4
VCCA_CRT_DAC2
VCC_SYNC
CRT
AXD
PEG
HV
AXF
VTTLF
VTT
SM CK
DMI
TV/CRT
D
LVDS
A SMA CK
CRT A LVDS
A PEG
PLL
(8 OF 10)
POWER
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
100 mA
100 mA
100 mA
200 mA
5 mA
50 mA
100 mA
10 mA
40 mA
40 mA
40 mA
60 mA
250 mA
150 mA
5 mA
S0 or S3M is acceptable
S0 or S3M is acceptable
TBD mA @ 1067MHz FSB (1.25V)
150 mA
770 mA @ 667MHz FSB (1.05V)
1260 mA
260 mA
0.4 mA
80 mA
30 mA
60 mA
100 mA
35 mA
850 mA @ 800MHz FSB (1.05V)
495 mA
515 mA
Current numbers from Crestline EDS, doc #21749.
640 mA (667MHz DDR) 550 mA (533MHz DDR)
6.3V 402
CERM-X5R
10%
0.47UF
402
CERM-X5R
6.3V
10%
0.47UF
402
CERM-X5R
6.3V
10%
0.47UF
CRESTLINE
FCBGA
OMIT
SYNC_MASTER=T9_NOME
SYNC_DATE=03/16/2007
NB Power 2
19 88
A.0.0
051-7225
=PP3V3_S0_NB_VCCA_PEG_BG
PP1V25_S0M_NB_VCCA_SM
PP1V8_S3M_NB_VCCSMCK
PP1V25_S0_NB_PEGPLL
PP1V25_S0M_NB_VCCA_SM_CK
=PP3V3_S0_NB_VCCSYNC
PP3V3_S0_NB_VCCA_CRTDAC
PP1V8_S0_NB_VCCTXLVDS
=PP1V25R1V05_S0_NB_VTT
PP3V3_S0_NB_VCCA_TVDACB
PP1V25_S0_NB_VCCA_DPLLB
PP3V3_S0_NB_VCCA_TVDACC
PP1V25_S0M_NB_VCCAXD
PP1V25_S0_NB_VCCAXF
PP1V05_S0_NB_VCCRXRDMI
=PP3V3_S0_NB_VCCHV
PP1V05_S0_NB_VCCPEG
PP1V8_S0_NB_VCCTXLVDS
=GND_NB_VSSA_PEG_BG
=GND_NB_VSSA_DAC_BG
=PP1V25_S0_NB_VCCDMI
NB_VTTLF_CAP3
NB_VTTLF_CAP1
PP1V25_S0M_NB_VCCA_MPLL
PP3V3_S0_NB_VCCA_DAC_BG
=GND_NB_VSSA_LVDS
=PP1V25_S0M_NB_VCCD_HPLL
PP1V5_S0_NB_VCCD_QDAC
PP1V5_S0_NB_VCCD_TVDAC
=PP1V5_S0_NB_VCCD_CRT
PP3V3_S0_NB_VCCA_TVDACA
PP1V25_S0M_NB_VCCA_HPLL
PP1V25_S0_NB_VCCA_DPLLA
=PP1V8_S0_NB_VCCD_LVDS
NB_VTTLF_CAP2
U1400
AT23 AU28 AU24 AT29 AT25 AT30
AR29
B23 B21 A21
AJ50
C40 B40
AD51 W50 W51 V49 V50
AH50 AH51
BK24 BK23 BJ24 BJ23
J32
A43
A33 B33
A30
B49
H49
AL2
A41
AM2
K50
U51
AW18
AT18 AT17
AV19 AU19 AU18 AU17
AT22 AT21 AT19
BC29 BB29
AR17 AR16
C25 B25 C27 B27 B28 A28
M32
AN2
J41 H42
U48
N28
L29
B32
B41
K49
U13
U1 T13 T11 T10 T9 T7 T6 T5 T3 T2
U12
R3 R2 R1
U11 U9 U8 U7 U5 U3 U2
A7 F2 AH1
C1911
1
2
C1913
1
2
C1912
1
2
21
21
22
21
21
16
21
22
21
8
21
21
21
21
22
22
19
8
22
22
22
16
21
21
8
15
19
21
22
8
21
22
22
21
22
22
22
22
21
22
22
VSS198VSS99
VSS197VSS98
VSS196VSS97
VSS195VSS96
VSS194VSS95
VSS193VSS94
VSS192VSS93
VSS191VSS92
VSS190VSS91
VSS189VSS90
VSS188VSS89
VSS187VSS88
VSS186VSS87
VSS185VSS86
VSS184VSS85
VSS183VSS84
VSS182VSS83
VSS181VSS82
VSS180VSS81
VSS179VSS80
VSS178VSS79
VSS177VSS78
VSS176VSS77
VSS175VSS76
VSS174VSS75
VSS173VSS74
VSS172VSS73
VSS171VSS72
VSS170VSS71
VSS169VSS70
VSS168VSS69
VSS167VSS68
VSS166VSS67
VSS165VSS66
VSS164VSS65
VSS163VSS64
VSS162VSS63
VSS161VSS62
VSS160VSS61
VSS159VSS60
VSS158VSS59
VSS157VSS58
VSS156VSS57
VSS155VSS56
VSS154VSS55
VSS153VSS54
VSS152VSS53
VSS151VSS52
VSS150VSS51
VSS149VSS50
VSS148VSS49
VSS147VSS48
VSS146VSS47
VSS145VSS46
VSS144VSS45
VSS143VSS44
VSS142VSS43
VSS141VSS42
VSS140VSS41
VSS139VSS40
VSS138VSS39
VSS137VSS38
VSS136VSS37
VSS135VSS36
VSS134VSS35
VSS133VSS34
VSS132VSS33
VSS131VSS32
VSS130VSS31
VSS129VSS30
VSS128VSS29
VSS127VSS28
VSS126VSS27
VSS125VSS26
VSS124VSS25
VSS123VSS24
VSS122VSS23
VSS121VSS22
VSS120VSS21
VSS119VSS20
VSS118VSS19
VSS117
VSS116VSS17
VSS115VSS16
VSS114VSS15
VSS113VSS14
VSS112VSS13
VSS111VSS12
VSS110VSS11
VSS109VSS10
VSS108
VSS9
VSS107VSS8
VSS106VSS7
VSS105VSS6
VSS104VSS5
VSS103VSS4
VSS102
VSS101
VSS100
VSS1
VSS18
VSS2 VSS3
VSS
(9 OF 10)
VSS202
VSS289 VSS290 VSS291 VSS292
VSS295
VSS199 VSS287 VSS200 VSS288 VSS201
VSS203 VSS204
VSS293 VSS294
VSS208 VSS296 VSS209 VSS297 VSS210 VSS298 VSS211 VSS299 VSS212 VSS300 VSS213 VSS301 VSS214 VSS215 VSS216 VSS302 VSS217 VSS218 VSS219 VSS303 VSS220 VSS221 VSS222 VSS304 VSS223 VSS224 VSS225 VSS305 VSS226 VSS227 VSS228 VSS229 VSS306 VSS230 VSS307 VSS231 VSS308 VSS232 VSS309 VSS233 VSS310 VSS234 VSS311 VSS235 VSS312 VSS236 VSS313 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243
VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285 VSS286
VSS207
VSS206
VSS205
(10 OF 10)
VSS
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
TDE_SENSE
TDE_FORCE
TDB_FORCE
alias these nets directly to GND.
Mainly for investigation. If not used,
NOTE: TDB = _N
TDB_SENSE
Crestline Thermal Diode Pins
NOTE: TDE = _P
CRESTLINE
OMIT
FCBGA
CRESTLINE
OMIT
FCBGA
SYNC_DATE=03/16/2007
SYNC_MASTER=T9_NOME
NB Grounds
20 88
A.0.0
051-7225
=NB_TDE_SENSE
=NB_TDE_FORCE
=NB_TDB_FORCE
=NB_TDB_SENSE
U1400
A13
AB26
AW24 AW29 AW32 AW5 AW7 AY10 AY24 AY37 AY42 AY43
AB28 AY45
AY47 AY50 B10 B20 B24 B29 B30 B35 B38
AB31
B43 B46 B5 B8 BA1 BA17 BA18 BA2 BA24 BB12
AC10
BB25 BB40 BB44 BB49 BB8 BC16 BC24 BC25 BC36 BC40
AC13
BC51 BD13 BD2 BD28 BD45 BD48 BD5 BE1 BE19 BE23
AC3
BE30 BE42 BE51 BE8 BF12 BF16 BF36 BG19 BG2 BG24
AC39
BG29 BG39 BG48 BG5 BG51 BH17 BH30 BH44 BH46 BH8
AC43
BJ11 BJ13 BJ38 BJ4 BJ42 BJ46 BK15 BK17 BK25 BK29
AC47
BK36 BK40 BK44 BK6 BK8 BL11 BL13 BL19 BL22 BL37
AD1
BL47 C12 C16 C19 C28 C29 C33 C36 C41
A15
AD21 AD26 AD29
AD3 AD41 AD45 AD49
AD5 AD50
AD8
A17
AE10 AE14
AE6 AF20 AF23 AF24 AF31
AG2 AG38 AG43
A24
AG47 AG50
AH3 AH40 AH41
AH7
AH9 AJ11 AJ13 AJ21
AA21
AJ24 AJ29 AJ32 AJ43 AJ45 AJ49 AK20 AK21 AK26 AK28
AA24
AK31 AK51
AL1 AM11 AM13
AM3
AM4 AM41 AM45
AN1
AA29
AN38 AN39 AN43
AN5
AN7
AP4 AP48 AP50 AR11
AR2
AB20
AR39 AR44 AR47
AR7 AT10 AT14 AT41 AT49
AU1 AU23
AB23
AU29
AU3 AU36 AU49 AU51 AV39 AV48
AW1 AW12 AW16
U1400
C46 C50
C7 D13 D24
D3 D32 D39 D45 D49 E10 E16 E24 E28 E32 E47 F19 F36
F4 F40 F50
G1 G13 G16 G19 G24 G28 G29 G33 G42 G45 G48
G8 H24 H28
H4 H45 J11 J16
J2 J24 J28 J33 J35 J39
K12 K47
K8
L1 L17 L20 L24 L28
L3 L33 L49 M28 M42 M46 M49
M5 M50
M9 N11 N14 N17 N29 N32 N36 N39 N44 N49
N7 P19
P2 P23
P3 P50 R49 T39 T43 T47 U41 U45 U50
V2
V3
W11 W39 W43 W47 W5 W7 Y13 Y2 Y41 Y45 Y49 Y5 Y50 Y11 P29
T29
T31
T33
R28
AA32 AB32 AD32 AF28 AF29 AT27 AV25 H50
51
51
51
51
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
and DDR2 taps." (C2135)
Placeholder for 3.9nH, 1A, 32mOhm
GMCH Memory I/O Rail
GMCH FSB I/O Rail
850 mA (800MHz FSB)
Current numbers from Crestline EDS, doc #21749.
260 mA
1520 mA 1260 mA
495 mA495 mA
550 mA (533MHz DDR2)
640 mA (667MHz DDR2)
35 mA
0.4 mA
515 mA515 mA
585 mA (533MHz DDR2)
675 mA (667MHz DDR2)
770 mA (667MHz FSB)
3300 mA (2ch 667MHz) 2700 mA (2ch 533MHz) 1700 mA (1ch 667MHz) 1395 mA (1ch 533MHz) 5 mA (standby)
Layout Note: Route to caps, then GND
NOTE: This follower is redundant if VCORE is always 1.05V.
100 mA
100 mA
200 mA 200 mA
GMCH ME Core Power
on opposite side.
be close to MCH
Layout Note:
on opposite side.
be close to MCH
450 mA
150 mA
50 mA
250 mA
100 mA
10uF caps should
Placeholder for 2.2nH, 1.4A, 17mOhm
Layout Note: Place L and C close to MCH
WF: "Place where LVDS
Layout Note: 10uF caps should
Placeholder for 5.6nH, 0.9A, 45mOhm max
100 mA
540 mA
WF: Matanzas has 2-pin 270uF bulk cap
1310mA (Ext Graphics)
1573mA (Int Graphics)
GMCH Core Power
0.47UF
CERM-X5R
10% 402
6.3V
PLACEMENT_NOTE=Place close to U1400
6.3V
20%
PLACEMENT_NOTE=Place close to U1400
2.2uF
603
CERM1
4.7uF
603
PLACEMENT_NOTE=Place close to U1400
CERM
20%
6.3V
10V
0.1uF
402
CERM
20%
10V
0.1uF
402
CERM
20%
CRITICAL
D2T
20%
470UF
TANT
2.5V
10V
PLACEMENT_NOTE=Place in GMCH cavity
0.1uF
402
CERM
20%
0.22uF
402
20%
6.3V X5R
402
20%
6.3V X5R
0.22uF
22UF
CERM-X5R
20%
6.3V
805-3
CERM
PLACEMENT_NOTE=Place in GMCH cavity
10V
0.1uF
402
20%
PLACEMENT_NOTE=Place in GMCH cavity
10V
0.1uF
402
CERM
20%
4.7uF
603
PLACEMENT_NOTE=Place close to U1400
CERM
20%
6.3V
22UF
805-3
6.3V
20% CERM-X5R
PLACEMENT_NOTE=Place close to U1400
22UF
805-3
6.3V
20% CERM-X5R
PLACEMENT_NOTE=Place close to U1400
0.1uF
20% CERM
402
10V
0.51
MF-LF
1/16W
1%
402
10V
0.1uF
402
CERM
20%
402
1.1
1% 1/16W MF-LF
0805
FERR-220-OHM
10uF
20%
6.3V X5R 603
10V
0.1uF
402
CERM
20%
PLACEMENT_NOTE=Place C2180 by U1400.AN2
10V
0.1uF
402
CERM
20%
CRITICAL
D3L
POLY
6.3V
20%
330uF
CRITICAL
D3L
POLY
6.3V
20%
330uF
20%
603
10uF
6.3V X5R
CRITICAL
CASE-B2
2.5V
220UF
20%
POLY
91NH
1210
10V 402
CERM
20%
0.1uF
402
MF-LF
1%
1/16W
1.1
0805
1.0UH-220MA-0.12-OHM
603
10uF
20%
6.3V X5R
22UF
805-3
6.3V
20%
CERM-X5R
10V
0.1uF
402
CERM
20%
X5R
10V
10%
402
1uF
603
X5R
6.3V
20%
10uF
603
5%
MF-LF
1/10W
0
X5R
10V
10%
1uF
402
5% 1/10W MF-LF
0
603
NO STUFF
0603
FERR-120-OHM-0.2A
22UF
805-3
6.3V
20%
CERM-X5R
NO STUFF
CERM-X5R
22uF
20%
6.3V
805-3
4.7UF
6.3V
20% CERM
603
CRITICAL
D3L
POLY
6.3V
20%
330uF
X5R
1uF
402
10% 10V
0
5% 1/10W MF-LF
603
22UF
CERM-X5R
20%
6.3V
805-3
0
603
MF-LF
1/10W
5%
CERM
20%
402
0.1uF
10V
1/16W
1%
MF-LF
10
402
BAT54E3
SOT23
10
MF-LF
1%
1/16W
402
BAT54E3
SOT23
22UF
NO STUFF
6.3V
805-3
20%
CERM-X5R
NO STUFF
6.3V
20%
2.2uF
603
CERM1
0603
FERR-120-OHM-0.2A
PLACEMENT_NOTE=Place in GMCH cavity
10V
0.1uF
402
CERM
20%
603
10uF
20%
6.3V X5R
0.22uF
PLACEMENT_NOTE=Place in GMCH cavity
402
20%
6.3V X5R
0.22uF
PLACEMENT_NOTE=Place in GMCH cavity
402
20%
6.3V X5R
10V
PLACEMENT_NOTE=Place C2184 by U1400.AM2
0.1uF
402
CERM
20%
PLACEMENT_NOTE=Place C2182 by U1400.AL2
10V
0.1uF
402
CERM
20%
22UF
20%
6.3V
CERM-X5R
805-3
0603
FERR-120-OHM-0.2A
22UF
20%
6.3V
CERM-X5R
805-3
22UF
805-3
6.3V
20%
PLACEMENT_NOTE=Place in GMCH cavity
CERM-X5R
NB Standard Decoupling
SYNC_MASTER=T9_NOME
88
051-7225
A.0.0
21
SYNC_DATE=01/17/2007
=PP1V05_S0M_NB_VCCAXM
=PP1V25R1V05_S0_NB_VTT
PP1V8_S3M_NB_VCCSMCK
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.8V
=PP1V8_S3M_NB_VCC
=PP1V25_S0M_NB_VCC
MIN_NECK_WIDTH=0.2 MM
PP1V25_S0_NB_PEGPLL_RC
MIN_LINE_WIDTH=0.25 MM VOLTAGE=1.25V
PP1V25_S0M_NB_VCCA_SM
MIN_LINE_WIDTH=0.4 MM VOLTAGE=1.25V
MIN_NECK_WIDTH=0.2 MM
PP1V25_S0_NB_PEGPLL
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.25V
=PP1V25_S0_NB_PLL
VOLTAGE=1.25V
PP1V25_S0M_NB_VCCAXD
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM
=PP1V05_S0_NB_PCIE
PP1V25_S0_NB_VCCAXF
MIN_LINE_WIDTH=0.4 MM VOLTAGE=1.25V
MIN_NECK_WIDTH=0.2 MM
=PP1V25_S0_NB_VCC
=PP1V05_S0_NB_FOLLOW
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.25 MM
PP1V8_S3M_NB_VCCSMCK_RC
VOLTAGE=1.8V
=PP3V3_S0_NB_VCCA_PEG_BG
=PPVCORE_S0_NB_FOLLOW
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM
PP3V3_S0_NBCORE_FOLLOW_R
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.4 MM VOLTAGE=3.3V
PP3V3_S0_NB1V05_FOLLOW_R
=PP3V3_S0_NB_FOLLOW
=PP1V25_S0M_NB_VCCD_HPLL
MIN_LINE_WIDTH=0.3 MM VOLTAGE=1.25V
MIN_NECK_WIDTH=0.2 MM
PP1V25_S0M_NB_MPLL_RC
=PP1V25_S0_NB_VCCDMI
=PP1V25_S0M_NB_PLL
MIN_LINE_WIDTH=0.3 MM VOLTAGE=1.25V
MIN_NECK_WIDTH=0.2 MM
PP1V25_S0M_NB_VCCA_MPLL
=PPVCORE_S0_NB
=PP3V3_S0_NB_VCCHV
=GND_NB_VSSA_PEG_BG
PP1V25_S0M_NB_VCCA_HPLL
MIN_LINE_WIDTH=0.25 MM VOLTAGE=1.25V
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.5 MM
PP1V05_S0_NB_VCCRXRDMI
MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V
PP1V25_S0M_NB_VCCA_SM_CK
MIN_LINE_WIDTH=0.4 MM VOLTAGE=1.25V
MIN_NECK_WIDTH=0.2 MM
=PP1V8_S3M_MEM_NB
=PP1V25_S0M_NB_VCCA
MAKE_BASE=TRUE
PP1V05_S0_NB_VCCPEG
MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V
MIN_LINE_WIDTH=0.5 MM
L2181
1 2
C2104
1
2
C2177
1
2
C2103
1
2
C2102
1
2
C2184
1
2
C2182
1
2
C2181
1
2
L2183
1 2
C2183
1
2
C2101
1
2
C2124
1
2
C2123
1
2
C2121
1
2
C2161
1
2
C2165
1
2
C2100
1
2 3
C2113
1
2
C2112
1
2
C2111
1
2
C2110
1
2
C2114
1
2
C2115
1
2
C2122
1
2
C2131
1
2
C2132
1
2
C2135
1
2
R2183
1
2
C2191
1
2
R2190
1
2
L2190
1 2
C2190
1
2
C2192
1
2
C2180
1
2
C2130
1
2
C2120
1
2
C2174
1
2
C2173
1
2
L2173
1 2
C2197
1
2
R2195
1
2
L2195
1 2
C2195
1
2
C2196
1
2
C2160
1
2
C2171
1
2
C2170
1
2
R2170
1 2
C2151
1
2
R2150
1 2
L2150
1 2
C2142
1
2
C2141
1
2
C2143
1
2
C2140
1
2
C2144
1
2
R2141
1 2
C2145
1
2
R2145
1 2
C2148
1
2
R2186
1 2
D2186
1 3
R2185
1 2
D2185
1 3
C2150
1
2
C2146
1
2
22
19
18
18
19
19
19 19
18
16
16
19
8
8
19
8
8
19
19
8
16
8
19
8
8
8
8
8
19
8
8
19
8
8
19
19
19
19
8
8
15
IN
OUT
EN
NR/FB
IN
GND
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
GMCH Graphics Core Power
VCCD_TVDAC also powers internal thermal sensors.
7700 mA
Vout = 1.25V (Factory Programmed)
Layout Note: Route to cap, then GND
65 mA
Crestline LVDS Support
260 mA 110 mA
150 mA
Current numbers from Crestline EDS Addendum, doc #20127.
60 mA
Layout Note:
within 6.35 mm of NB edge
These 2 caps should be
100 mA
100 mA
(1.7V - 5.5V) 100 mA
NOTE: This filter is required even if using only external graphics.
2.37K
1% 1/16W MF-LF
402
15 80
1UF
10%
402
CERM
6.3V
CRITICAL
SOT23-5
TPS731125
10% 16V
402
CERM
0.01UF
1/10W
0.300
603
FF
5%
NO STUFF
402
5%
4.7
MF-LF
1/16W
NO STUFF
20% CERM
402
0.1uF
10V
1/16W
5%
4.7
402
MF-LF
0.1uF
20% CERM
402
10V
X5R
6.3V
20%
10UF
603
CERM
50V
10% 402
0.001UF0.001UF
CERM
50V
10% 402
22000pF-1000mA
16V
NFM18
20% CERM
402
10V
0.1uF
1210
1.0UH-0.5A
CASE-D3L
CRITICAL
POLY
6.3V
20%
220UF
0.1uF
20% CERM
402
10V
PLACEMENT_NOTE=Place in GMCH cavity
20%
0.1uF
10V
PLACEMENT_NOTE=Place in GMCH cavity
402
CERM
402
10%
PLACEMENT_NOTE=Place in GMCH cavity
6.3V CERM-X5R
0.47UF
20%
6.3V X5R
PLACEMENT_NOTE=Place in GMCH cavity
10uF
603
CRITICAL
6.3V
20%
PLACEMENT_NOTE=Place in GMCH cavity
22UF
CERM-X5R 805-3
2.5V D2T
470UF
20%
TANT
CRITICAL
20%
2.5V D2T
TANT
470UF
CRITICAL
1UF
10% 402
CERM
6.3V
6.3V CERM
10%
1UF
PLACEMENT_NOTE=Place in GMCH cavity
402
SYNC_DATE=03/12/2007
NB Graphics Decoupling
051-7225
A.0.0
8822
SYNC_MASTER=M76_MLB
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_LVDS_VREFH
TP_LVDS_VREFL
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_LVDS_VREFL
TP_LVDS_VREFH
NB_CLK100M_DPLLSS_N
=PP1V5_S0_NB_TVDAC
=CRT_BLUE =CRT_BLUE_L
=CRT_GREEN =CRT_GREEN_L
=CRT_HSYNC_R
=CRT_RED =CRT_RED_L
=CRT_TVO_IREF
=CRT_VSYNC_R
=GND_NB_VSSA_DAC_BG
=NB_CLK96M_DOT_P
=PP1V5_S0_NB_VCCD_CRT
=PP3V3_S0_NB_VCCSYNC
=TV_A_DAC =TV_A_RTN =TV_B_DAC =TV_B_RTN =TV_C_DAC =TV_C_RTN
CRT_DDC_CLK CRT_DDC_DATA
PP1V5_S0_NB_VCCD_QDAC
PP3V3_S0_NB_VCCA_CRTDAC
PP3V3_S0_NB_VCCA_DAC_BG
PP3V3_S0_NB_VCCA_TVDACA PP3V3_S0_NB_VCCA_TVDACB PP3V3_S0_NB_VCCA_TVDACC
SDVO_CTRLCLK SDVO_CTRLDATA TV_DCONSEL<0> TV_DCONSEL<1>
=PPVIN_S0_NB_DPLL
MIN_NECK_WIDTH=0.2 MM
GND_DPLL_ESR
MIN_LINE_WIDTH=0.4 MM VOLTAGE=0V
MIN_LINE_WIDTH=0.4 MM VOLTAGE=1.25V
MIN_NECK_WIDTH=0.2 MM
PP1V25_S0_NB_DPLL
P1V25S0NBDPLL_NR
MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.25V
MIN_LINE_WIDTH=0.3 MM
PP1V25_S0_NB_VCCA_DPLLB
VOLTAGE=1.5V
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.3 MM
PP1V5_S0_NB_VCCD_TVDAC
PP1V25_S0_NB_VCCA_DPLLA
MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.25V
=PP1V8_S0_NB_LVDS
LVDS_IBG
=PPVCORE_S0_NB
=NB_CLK96M_DOT_N
=NB_CLK100M_DPLLSS_P =NB_CLK100M_DPLLSS_N
PP1V8_S0_NB_VCCTXLVDS
MIN_LINE_WIDTH=0.2 MM VOLTAGE=1.8V
MIN_NECK_WIDTH=0.2 MM
=GND_NB_VSSA_LVDS
=PP1V8_S0_NB_VCCD_LVDS
NB_CLK100M_DPLLSS_P
=PPVCORE_S0_NB_GFX
R2261
1 2
C2261
1
2
R2262
1 2
C2262
1
2
C2260
1
2
C2223
1
2
C2221
1
2
C2201
2
1 3
C2200
1
2
L2220
1 2
C2220
1
2
C2217
1
2
C2216
1
2
C2215
1
2
C2213
1
2
C2212
1
2
C2211
1
2 3
C2210
1
2 3
C2226
1
2
C2214
1
2
R2299
1
2
C2265
1
2
U2265
3
2
1
4
5
C2266
1
2
R2260
1
2
84
21
84
30
18
30
18
15
15
7
8
15
15
15
15
15
15
15
15
15
19
16
19
19
15
15
15
15
15
15
15
15
19
19
19
19
19
19
16
16
15
15
8
19
19
19
8
8
16
16
16
19
19
19
7
8
SATA0RXP
SATA0RXN
SATALED*
RTCRST*
HDA_BIT_CLK
DDREQ
RTCX1 RTCX2
DCS1* DCS3*
IDEIRQ
DDACK*
IORDY
DIOR* DIOW*
DD11 DD12
DD4
DD2
DD14
DD0
DD15
DD1
DD13
DD5
DD10
DD8
DD3
DD9
LDRQ0*
FWH2/LAD2 FWH3/LAD3
FWH1/LAD1
LDRQ1*/GPIO23
FWH0/LAD0
FWH4/LFRAME*
HDA_SDIN0
HDA_SYNC
SATA1TXN SATA1TXP
HDA_SDIN1 HDA_SDIN2
RCIN*
SATA0TXP
SATA0TXN
CPUPWRGD/GPIO49
SMI*
A20M*
SATA1RXP
SATA1RXN
SATARBIAS
SATARBIAS*
IGNNE*
DPRSTP*
INTVRMEN
A20GATE
SATA2RXN SATA2RXP
THRMTRIP*
DPSLP*
INIT*
HDA_RST*
HDA_SDOUT
HDA_DOCK_EN*/GPIO33
SATA2TXN SATA2TXP
FERR*
NMI
HDA_SDIN3
INTR
SATA_CLKP
SATA_CLKN
DA2
DD6
STPCLK*
TP8
DA0 DA1
HDA_DOCK_RST*/GPIO34
INTRUDER*
LAN_TXD0
LAN100_SLP
LAN_RSTSYNC
LAN_RXD0 LAN_RXD1 LAN_RXD2
DD7
LAN_TXD2
LAN_TXD1
GLAN_COMPI GLAN_COMPO
GLAN_CLK
LAN/GLANIHDA
CPU
RTC
LPC
(1 OF 6)
SATA
IDE
OUT
IN
IN
IN
BI
BI BI
BI
BI
OUT
OUT
IN
IN
OUT
OUT
IN IN OUT OUT
IN IN
OUT
OUT
IN IN
IN IN
OUT OUT
IN
OUT
OUT OUT OUT
IN IN IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT OUT OUT
OUT
OUT OUT
OUT
OUT OUT
IN
IN
OUT OUT
OUT
OUT
OUT
OUT
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
NOTE: ALL IDE PINS HAVE INTERNAL 33-OHM SERIES R’S
INT PU
INT PU
INT PU
INT PD
INT PD INT PD INT PD INT PD
INT PD
INT PU INT PD
INTEGRATED PD
INTEGRATED PD
INTEGRATED PDs
ACZ_SYNC
HDA_SDOUT
HDA_SDIN[0-2]
HDA_RST#
HDA_BIT_CLK
24.000MHZ CLOCK W/INTERNAL WEAK PD
HDA
INT PD
INT PU
INT PU
INT PU
ICH8M
BGA
OMIT
28
28
7
28
28
7
45 47
7
45 47
7
45 47
7
45 47
28 65
7
45 47
10 79
NO STUFF
2.2K
5% 1/16W MF-LF
402
1/16W MF-LF
24.9
1%
402
1/16W 402
MF-LF
332K
1%
78 82
78 82
78 82
78 82
42 82
42 82
42 82
42 82
42 82
42 82
42 82
42 82
30 84
30 84
42
42
7
10 16 58 79
7
10 79
10 79
7
10 13 79
42 82
42 82
42 82
42 82
42 82
42 82
42 82
42 82
42 82
42 82
42 82
42 82
42 82
42 82
42 82
42 82
42 82
42 82
42 82
42 82
42 82
42 82
42 82
42 82
42 82
7
10 79
10 79
10 79
10 79
10 47 79
10 79
1/16W
5%
402
MF-LF
10K
10 16 46 79
402
24.9
1/16W MF-LF
1%
PLACEMENT_NOTE=Place R2308 within 50mm of U2300
34 82
MF-LF
402
332K
1%
1/16W
402
MF-LF
1/16W
5%
8.2K
34 82
34 82
34 82
34 82
8.2K
5% 1/16W MF-LF
402
54.9
402
MF-LF
1/16W
1%
PLACEMENT_NOTE=Place R2309 within 50mm of R2308 (NO STUB)
54.9
402
MF-LF
1/16W
1%
5%
1/16W MF-LF33402
402
33
MF-LF1/16W
5%
4025%
MF-LF
33
1/16W
33
402
MF-LF1/16W
5%
5%
10K
MF-LF 402
1/16W
42 82
42 82
SB Enet, Disk, FSB, LPC
SYNC_DATE=03/16/2007
SYNC_MASTER=T9_NOME
051-7225
8823
A.0.0
LAN_ENERGY_DET
=PP3V3_S0_SB_GPIO
PP1V5_S0_SB_VCC1_5_B
GLAN_COMP
PP3V3_G3_SB_RTC
HDA_DOCK_EN_L
SB_INTVRMEN SB_LAN100_SLP
SB_SM_INTRUDER_L
SB_RTC_RST_L
SB_RTC_X2
SB_RTC_X1
TP_LAN_R2D<2>
LPC_AD<2>
LPC_AD<0> LPC_AD<1>
LPC_AD<3> LPC_FRAME_L
EXTGPU_PWR_EN
PM_THRMTRIP_L
CPU_THERMTRIP_R
CPU_A20M_L
CPU_DPSLP_L
CPU_DPRSTP_L
CPU_PWRGD
CPU_IGNNE_L CPU_INIT_L
CPU_INTR
CPU_NMI CPU_SMI_L
CPU_STPCLK_L
IDE_PDD<0>
IDE_PDD<2>
IDE_PDD<1>
IDE_PDD<3> IDE_PDD<4> IDE_PDD<5>
IDE_PDD<7>
IDE_PDD<6>
IDE_PDD<8>
IDE_PDD<10>
IDE_PDD<9>
IDE_PDD<12>
IDE_PDD<11>
IDE_PDD<13>
IDE_PDD<15>
IDE_PDD<14>
IDE_PDA<0> IDE_PDA<1> IDE_PDA<2>
IDE_PDCS3_L
IDE_PDCS1_L
IDE_PDIOW_L
IDE_PDIOR_L
IDE_PDDACK_L IDE_IRQ14 IDE_PDIORDY IDE_PDDREQ
=PP1V05_S0_SB_CPU_IO
=PP3V3_S0_SB_GPIO
CPU_FERR_L
SB_A20GATE
TP_LPC_DRQ0_L
SB_RCIN_L
TP_SB_TP8
TP_LAN_D2R<2>
SATA_A_D2R_P
TP_SB_SATALED_L
SATA_A_R2D_C_P
SATA_A_R2D_C_N
SATA_B_D2R_P
SATA_B_D2R_N
TP_HDA_DOCK_RST_L
TP_LAN_R2D<0>
TP_LAN_RSTSYNC TP_LAN_D2R<0>
TP_LAN_R2D<1>
SATA_B_R2D_C_N SATA_B_R2D_C_P
SATA_C_D2R_P
SATA_C_D2R_N
SATA_C_R2D_C_N SATA_C_R2D_C_P
SB_CLK100M_SATA_P
SB_CLK100M_SATA_N
SATA_RBIAS_P
SATA_RBIAS_N
HDA_BIT_CLK_R HDA_SYNC_R
HDA_RST_L_R
HDA_SDOUT_R
HDA_SYNC
HDA_BIT_CLK
HDA_RST_L
HDA_SDOUT
SATA_A_D2R_N
TP_HDA_SDIN1
TP_ENET_GLAN_CLK
TP_LAN_D2R<1>
HDA_SDIN0
TP_HDA_SDIN3
TP_HDA_SDIN2
U2300
AF13 AG26
AG29
AA4 AA1 AB3
Y6 Y5
V1 U2
T4 V6 V5 U1 V2 U6
V3 T1 V4 T5 AB2 T6 T3 R2
Y2
W5
W4 W3
AF26 AE26
AD24
E5 F5 G8 F6
C4
B24
D25 C25
AH21
AJ16
AE10 AG14
AE14
AJ17 AH17 AH15 AD13
AE13
AJ15
Y3
AF27
AE24 AC20
AD22
AF25
Y1
AD21
D22
C21 B21 C22
D21 E20 C20
G9 E6
AD23
AH14
AF23
AG25 AF24
AF6 AF5 AH5 AH6
AG3 AG4 AJ4 AJ3
AF2 AF1 AE4 AE3
AB7 AC6
AF10
AG2
AG1
AG28
AA24
AE27
AA23
R2304
1
2
R2302
1
2
R2301
1
2
R2306
1
2
R2308
1 2
R2300
1
2
R2303
1
2
R2310
1
2
R2305
1
2
R2309
1
2
R2313
1 2
R2314
1 2
R2315
1 2
R2316
1 2
R2311
1
2
25
27
28
27
25
23
26
27
26
23
8
24
83
26
7
8
8
82
82
82
82
SPI_CS1*
PETN1
PERP1
OC4*/GPIO43 OC5*/GPIO29 OC6*/GPIO30 OC7*/GPIO31 OC8* OC9*
SPI_MOSI
OC0* OC1*/GPIO40 OC2*/GPIO41 OC3*/GPIO42
PERN5
DMI1RXN DMI1RXP DMI1TXN DMI1TXP
DMI0RXN DMI0RXP DMI0TXN DMI0TXP
DMI_CLKN DMI_CLKP
PETP1
USBP9N USBP9P
PERN2
USBP7N USBP7P USBP8N USBP8P
PETN2
USBP6N USBP6P
PERP3
USBP4N USBP4P USBP5N USBP5P
PETN3
PETP3
USBP3N USBP3P
PERN4 PERP4
USBP1N USBP1P USBP2N USBP2P
PETN4 PETP4
USBP0N USBP0P
PERP5
SPI_MISO
USBRBIAS
USBRBIAS*
PETP5
PERN6/GLAN_RXN PERP6/GLAN_RXP PETN6/GLAN_TXN PETP6/GLAN_TXP
SPI_CLK SPI_CS0*
DMI3RXN DMI3RXP DMI3TXN DMI3TXP
DMI2RXN DMI2RXP DMI2TXN DMI2TXP
DMI_IRCOMP
DMI_ZCOMP
PERN1
PERP2
PETP2
PERN3
PETN5
PCI_EXPRESS
DIRECT MEDIA INTERFACE
SPI
USB
(2 OF 6)
IN
IN OUT OUT
IN
IN OUT OUT
IN
IN OUT OUT
IN
IN OUT OUT
IN
IN
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
IN
IN OUT OUT
IN
IN OUT OUT
BI BI
BI
BI
AD4 AD5
AD9
PIRQF*/GPIO3
PIRQE*/GPIO2
AD13
PME*
PCIRST*
GNT2*/GPIO53
C/BE2*
PIRQG*/GPIO4
SERR*
PIRQA*
AD1
REQ1*/GPIO50
C/BE3*
AD11
C/BE1*
AD25 AD26
AD0
AD2
DEVSEL*
AD18
AD21
PAR
GNT0*
AD7
GNT1*/GPIO51
C/BE0*
STOP*
AD20
AD16
GNT3*/GPIO55
TRDY*
IRDY*
AD22
PIRQC*
REQ2*/GPIO52
AD19
PCICLK
PLOCK*
AD15
PIRQB*
PIRQH*/GPIO5
PLTRST*
AD3
AD6
AD8
FRAME*
AD14
AD12
AD10
REQ3*/GPIO54
PIRQD*
AD17
PERR*
REQ0*
AD31
AD27 AD28
AD30
AD29
AD24
AD23
(3 OF 6)
INTERRUPT I/F
PCI
BI
BI
BI BI BI
BI
BI
BI BI BI
BI
BI
BI BI BI
BI
BI
BI BI BI
BI
BI
BI BI BI
BI
BI
BI BI BI
BI
BI
BI
BI
BI
BI
IN
IN
IN
BI
BI
BI
BI
BI BI
OUT
BI BI BI
BI
BI
BI
BI
OUT
IN
BI BI
IN
IN
IN IN IN
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
NOTE: USBP[0-9]P/N have internal 15K pull-downs.
IR
Bluetooth
External D / WWAN
External A
Geyser Trackpad/Keyboard
External B
ExpressCard
AirPort (PCIe Mini-Card)
Camera
External C
INT PD
INT PD
INT PD
INT PD
INT PD
INT PD
INT PD
EHCI0
INT PD
INT PD INT PD INT PD INT PD INT PD
INT PD
INT PD
INT PD
INT PD
INT PU
INT PU
INT PU
INT PU
EHCI1
INT PD
INT PD
INT PD
Spares
ExpressCard
FireWire
(AirPort)
Ethernet
(x2-capable, pull HDA_SYNC high for x2)
SPI_CS1# HAS INT PU (NOMINAL=20K, SIMULATION=15K-35K)
GNT0# HAS INT PU; ENABLED ONLY WHEN PCIRST#=0 AND PWROK=H
1
GNT0#
0
NOTE:
SPI
PCIe Mini Card
Yukon-PCIE Nineveh-GLCI
LPC
I/F
SB BOOT BIOS SELECT
selects SPI ROM by default.
R2415 pull-down on GNT0#
Provide a pull-down on this GPIO if not used.
INT PU
INT PU
INT PU
INT PU
INT PU
FireWire INT*
rises, or PCIe ports 5 & 6 will be disabled.
If used, ensure GNT2# is not low when PWROK
enabled only when PCIRST# = 0 and PWROK = 1
NOTE: GNT[0-3]# have internal 20K pull-ups
MF-LF
5%
10K
402
1/16W
1/16W MF-LF 402
10K
5%
10K
402
5% 1/16W MF-LF
10K
1/16W 402
MF-LF
5%
MF-LF 402
5%
10K
1/16W
402
5% 1/16W MF-LF
10K
402
1/16W
10K
MF-LF
5%
10K
MF-LF 402
1/16W
5%
BGA
ICH8M
OMIT
16 80
16 80
16 80
16 80
16 80
16 80
16 80
16 80
16 80
16 80
16 80
16 80
16 80
16 80
16 80
16 80
30 84
30 84
1% 402
MF-LF1/16W
24.9
43 82
43 82
34 82
34 82
44 82
44 82
7
44 82
7
44 82
78 82
78 82
78 82
78 82
78 82
78 82
34 82
34 82
34 82
34 82
9
82
9
82
22.6
MF-LF
402
1%
1/16W
34 83
34 83
34 83
34 83
35 83
35 83
35 83
35 83
55 82
55 82
55 82
55 82
ICH8M
BGA
OMIT
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
24 83
24 83
24 83
24 38 83
24 83
24 38 83
24 83
38 83
38 83
38 83
38 83
24 38 83
38 83
7
28
24 38 83
24 38 83
24 83
24 38 83
24 38 83
24 38 83
24 38 83
7
28 77
30 84
24 83
5%
402
MF-LF
1/16W
10K
402
1/16W
5%
MF-LF
10K
402
5% 1/16W MF-LF
1K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
24 83
8.2K
13 43
13
13 34
34 46
24 42
76
38 83
42 82
13
7
47
13 77
8.2K
13
13 36
13
SYNC_DATE=03/16/2007
051-7225
8824
A.0.0
SYNC_MASTER=T9_NOME
SB PCI, PCIe, DMI, USB
WOW_EN
INT_PIRQD_L
INT_PIRQC_L
INT_PIRQA_L INT_PIRQB_L
PCI_AD<31>
PCI_AD<30>
PCI_AD<29>
PCI_AD<28>
PCI_AD<27>
PCI_AD<26>
PCI_AD<25>
PCI_AD<23> PCI_AD<24>
PCI_AD<22>
PCI_AD<21>
PCI_AD<20>
PCI_AD<19>
PCI_AD<17> PCI_AD<18>
PCI_AD<16>
PCI_AD<15>
PCI_AD<14>
PCI_AD<12> PCI_AD<13>
PCI_AD<11>
PCI_AD<10>
PCI_AD<9>
PCI_AD<7> PCI_AD<8>
PCI_AD<6>
PCI_AD<5>
PCI_AD<4>
PCI_AD<3>
PCI_AD<1> PCI_AD<2>
PCI_AD<0>
ODD_PWR_EN_L
DVI_HOTPLUG_DET
INT_PIRQE_L INT_PIRQF_L
PLT_RST_L PCI_CLK33M_SB
PCI_TRDY_L PCI_FRAME_L
PCI_STOP_L
PCI_SERR_L
PCI_LOCK_L
PCI_DEVSEL_L PCI_PERR_L
PCI_RST_L
PCI_PAR
PCI_IRDY_L
PCI_C_BE_L<3>
PCI_C_BE_L<1>
PCI_C_BE_L<0>
PCI_C_BE_L<2>
ODD_RST_5VTOL_L
PCI_REQ2_L
PCI_FW_REQ_L
TP_SB_GPIO55
TP_SB_GPIO51
PCI_REQ1_L
TP_SB_GPIO53
TP_PCI_PME_L
BOOT_LPC_SPI_L
PCI_FW_GNT_L
MAKE_BASE=TRUE
=PP3V3_S5_SB_USB
SB_GPIO40
USB_EXTA_OC_L
EXTGPU_LVDS_EN
USB_EXTC_OC_L
SB_GPIO30
TP_PCIE_A_R2D_C_P
PCI_REQ1_L
PCI_TRDY_L
INT_PIRQE_L
INT_PIRQD_L
INT_PIRQB_L
INT_PIRQA_L
PCI_REQ2_L
PCI_STOP_L
PCI_IRDY_L
PCI_FRAME_L
PCI_FW_REQ_L
PCI_LOCK_L
INT_PIRQF_L
INT_PIRQC_L
ODD_PWR_EN_L
PCI_SERR_L PCI_DEVSEL_L PCI_PERR_L
=PP3V3_S0_SB_PCI
PP1V5_S0_SB_VCC1_5_B
USB_RBIAS
DMI_IRCOMP_R
TP_SPI_CE_R_L<1>
TP_PCIE_A_R2D_C_N
TP_PCIE_A_D2R_P
PM_LATRIGGER_L
USB_EXTB_OC_L EXCARD_OC_L
SPI_SI_R
USB_EXTD_OC_L
PCIE_MINI_D2R_N
TP_PCIE_B_D2R_N
TP_PCIE_B_R2D_C_N
TP_PCIE_EXCARD_D2R_P TP_PCIE_EXCARD_R2D_C_N TP_PCIE_EXCARD_R2D_C_P
TP_PCIE_FW_D2R_N TP_PCIE_FW_D2R_P TP_PCIE_FW_R2D_C_N TP_PCIE_FW_R2D_C_P
PCIE_MINI_D2R_P
SPI_SO
PCIE_MINI_R2D_C_P
PCIE_ENET_D2R_N PCIE_ENET_D2R_P PCIE_ENET_R2D_C_N PCIE_ENET_R2D_C_P
SPI_SCLK_R SPI_CE_R_L<0>
TP_PCIE_A_D2R_N
TP_PCIE_B_D2R_P
TP_PCIE_B_R2D_C_P
TP_PCIE_EXCARD_D2R_N
PCIE_MINI_R2D_C_N
USB_EXTC_P
USB_EXCARD_P USB_EXTC_N
USB_EXCARD_N
USB_EXTB_P
USB_EXTB_N
USB_BT_P
USB_TPAD_P USB_BT_N
USB_TPAD_N
USB_IR_P
USB_IR_N
USB_CAMERA_N USB_CAMERA_P
USB_EXTD_P
USB_EXTD_N
USB_MINI_P
USB_MINI_N
USB_EXTA_P
USB_EXTA_N
SB_CLK100M_DMI_P
SB_CLK100M_DMI_N
DMI_S2N_P<3>
DMI_S2N_N<3>
DMI_N2S_P<3>
DMI_N2S_N<3>
DMI_S2N_P<2>
DMI_S2N_N<2>
DMI_N2S_P<2>
DMI_N2S_N<2>
DMI_S2N_P<1>
DMI_S2N_N<1>
DMI_N2S_P<1>
DMI_N2S_N<1>
DMI_S2N_P<0>
DMI_S2N_N<0>
DMI_N2S_P<0>
DMI_N2S_N<0>
R2408
1
2
R2407
1
2
R2400
1
2
R2409
1
2
R2401
1
2
R2402
1
2
R2404
1
2
R2403
1
2
U2300
V27 V26 U29 U28
Y27 Y26 W29 W28
AB26 AB25 AA29 AA28
AD27 AD26 AC29 AC28
T26 T25
Y24
Y23
AJ19 AG16 AG15 AE15 AF15 AG17 AD12 AJ18 AD14 AH18
P27
M27
K27
H27
F27
D27
P26
M26
K26
H26
F26
D26
N29
L29
J29
G29
E29
C29
N28
L28
J28
G28
E28
C28
C23 B23 E22
F21
D23
G3 G2 H5 H4 H2 H1 J3 J2 K5 K4 K2 K1 L3 L2 M5 M4 M2 M1 N3 N2
F3
F2
R2413
1 2
R2414
1 2
U2300
D20 E19
A12 E16 A14 G16 A15
B6
C11
A9 D11 B12
D19
C12 D10
C7 F13 E11 E13 E12
D8
A6
E8
A20
D6
A3
D17 A21 A19 C19 A18 B16 C17
E15 F16 E17
D16
A17
D7
C18
F18
C10
C8 D9
B10
G6
A7
F9
B5
C5 A10
F8 G11 F12 B3
B7
AG24
G7
A4
E18
B19
A11
F10 C16 C9
R2405
1
2
R2406
2
1
R2415
1
2
R2423
1 2
R2424
1 2
R2425
1 2
R2426
1 2
R2427
1 2
R2428
1 2
R2430
1 2
R2429
1 2
R2432
1 2
R2431
1 2
R2433
1 2
R2437
1 2
R2439
1 2
R2438
1 2
R2436
1 2
R2440
1 2
R2441
1 2
R2442
1 2
83
83
83
83
83
83
83
83
83
27
83
38
83
38
83
83
83
38
38
38
38
83
83
83
42
38
38
38
26
8
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
8
23
82
34
34
34
34
OUT OUT
BI
IN
BI
IN IN
SMBALERT*/GPIO11
STP_PCI*/GPIO15
BMBUSY*/GPIO0
SYS_RESET*
SUS_STAT*/LPCPD*
THRM*
SMLINK0
GPIO12
SPKR
SDATAOUT1/GPIO48
SLP_S5*
GPIO20
GPIO8
WAKE*
CL_CLK1
BATLOW*
PWROK
SLOAD/GPIO38
SATA2GP/GPIO36
SERIRQ
RI*
CL_DATA1
SLP_S4*
EC_ME_ALERT/GPIO14
TACH0/GPIO17
CLK14
SCLOCK/GPIO22
SATA3GP/GPIO37
SATACLKREQ*/GPIO35
STP_CPU*/GPIO25
WOL_EN/GPIO9
LINKALERT*
SLP_S3*
RSMRST*
TACH3/GPIO7
CLKRUN*/GPIO32
GPIO18
LAN_RST*
CL_VREF1
S4_STATE*/GPIO26
TACH1/GPIO1 TACH2/GPIO6
SATA1GP/GPIO19
SDATAOUT0/GPIO39
SATA0GP/GPIO21
MCH_SYNC*
DPRSLPVR/GPIO16
VRMPWRGD
TP3
TP7
CL_RST*
ME_EC_ALERT/GPIO10
SLP_M*
MEM_LED/GPIO24
PWRBTN*
SUSCLK
CL_VREF0
CK_PWRGD
CLPWROK
CL_DATA0
CL_CLK0
CLK48
SMBCLK SMBDATA
SMLINK1
MISC
SYS GPIO
SMB
CLOCKS
POWER MGT
CONTROLLER LINK
GPIO
SATA
GPIO
(4 OF 6)
IN IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
BI BI
OUT
IN
IN
IN
IN
IN
OUT
OUT
IN
BI
BI
OUT
BI
BI
BI
IN
IN
OUT OUT
OUT
IN
OUT
OUT
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
If ME/AMT is not used, short CLPWROK to PWROK.
PP3V3_S0M, PP3V3_S0MWOL, PP1V8_S3M, PP1V25_S0M,
have been up for at least 1ms.
PM_LAN_ENABLE must remain deasseted until VccCL3_3, VccLAN3_3 and VccLAN1_05
INT PU
NOTE: ICH CLPWROK input must be PWRGD signal for
INT PD
INT PD
INT PU
Test access required
AT BOOT/RESET FOR STRAPPING FUNCTION
NOTE: DPRSLPVR HAS INT 20K PD ENABLED
INT PU
for XOR chain testing.
PP1V05_S0M, PP0V9_S3M and PP0V9_S0M.
See note below
7
29 30
7
29 30
7
45 47
34 35
7
45 47
45
13 45
5% 1/16W MF-LF 402
10K
402
0
5% 1/16W MF-LF
ARB_ONLY
MF-LF
1/16W
5%
10K
402
MF-LF
1/16W
5%
0
402
NOSTUFF
5%
10K
MF-LF
402
1/16W
402
10K
5% MF-LF
1/16W
1K
5% 1/16W MF-LF 402
402
8.2K
5% 1/16W MF-LF
402
5%
10K
1/16W MF-LF
402
1/16W
8.2K
5%
MF-LF
OMIT
BGA
ICH8M
30 84
30 84
46
7
36 40 45 65
402
1/16W
5%
1K
NO_REBOOT_MODE
MF-LF
7
45 46
7
16 58 79
7 9
28
25 45
7
45
45
48 82
48 82
7
45 46 47
7
28 45
16
7
28
25 38
7
16
7
45 65
29
9
16 83
16 83
402
3.24K
1% 1/16W MF-LF
402
453
1% 1/16W MF-LF
402
16V
10%
0.1uF
X5R
402
1/16W
1% MF-LF
4.53K
1% 1/16W MF-LF 402
32.4K
402
16V
10% X5R
0.1uF
16 83
25
100K
1/16W
402
MF-LF
5%
48 82
48 82
25
1/16W
10K
MF-LF
1%
402
5%
MF-LF
1/16W
8.2K
402
MF-LF
10K
1/16W
1%
402
10K
MF-LF
1/16W
5%
402
7
25 47
25
25 28
29
MF-LF
1/16W
5%
10K
402
402
MF-LF
1/16W
10K
5%
MF-LF
402
1/16W
5%
10K
402
MF-LF
1/16W
5%
8.2K
1/16W
8.2K
5% MF-LF
402
7
45
1%
MF-LF
1/16W
10K
402
1%
MF-LF
1/16W
10K
402
10K
MF-LF
402
5%
1/16W
402
1/16W
5%
MF-LF
10K
1/16W MF-LF
10K
402
5%
77
5% 1/16W MF-LF
10K
402
100K
402
5% 1/16W MF-LF
10K
1/16W MF-LF
1%
402
10K
1/16W MF-LF
1%
402
MF-LF
1/16W
5%
100K
402
MF-LF
10K
1/16W
1%
402
10K
1/16W MF-LF
1%
402
A.0.0
25 88
051-7225
SYNC_MASTER=T9_NOME
SYNC_DATE=03/16/2007
SB Pwr Mgt, GPIO, Clink
=PP3V3_S5_SB_GPIO
=PP3V3_S0_SB_GPIO
ARB_DETECT_L
TP_PM_SLP_M_L
CLINK_NB_CLK
SB_GPIO14_CL2
SB_CLINK_VREF1
SB_SCLOCK
SB_GPIO18
PM_STPCPU_L
PM_LAN_ENABLE PM_RSMRST_L CLK_PWRGD
PCI_PME_FW_L
=PP3V3_S5_SB
SATA_B_PWR_EN_L
SB_SPKR
SMC_WAKE_SCI_L
TP_SB_TP3
SB_SLOAD
SB_SATA_CLKREQ_L
FWH_MFG_MODE
SATA_B_PWR_EN_L
TP_SB_GPIO20
EXTGPU_RST_L
LAN_PHYPC
SMC_RUNTIME_SCI_L
SB_GPIO6
TP_SB_TP7 PCI_PME_FW_L
PM_CLKRUN_L PCIE_WAKE_L
INT_SERIRQ
PM_THRM_L
SATA_B_DET_L
TP_CLINK_WLAN_DATA
SB_GPIO10_CL1
WOL_EN
PM_SLP_S3_L
SB_CLK14P3M_TIMER
VR_PWRGD_CLKEN
PM_SUS_STAT_L
NB_SB_SYNC_L
LINDACARD_GPIO
PM_BMBUSY_L
CLINK_NB_DATA
TP_CLINK_WLAN_CLK
PM_BATLOW_L
PM_S4_STATE_L PM_SB_PWROK
PM_SLP_S5_L
TP_PM_SLP_S4_L
PM_SYSRST_L
SMB_ME_DATA
SMB_DATA
=PP3V3_S0MWOL_SB_CLINK0
SB_GPIO14_CL2
LAN_PHYPC
SB_GPIO10_CL1
PM_BATLOW_L
PM_RI_L
PM_DPRSLPVR
SMB_CLK
SMB_ME_CLK
PM_PWRBTN_L
TP_CLINK_WLAN_RESET_L
SUS_CLK_SB
SB_CLK48M_USBCTLR
=PP3V3_S5_SB_CLINK1
CLINK_NB_RESET_L
PM_RI_L
=SB_CLINK_MPWROK
PM_STPPCI_L
RSVD_EXTGPU_LVDS_EN
SB_CRT_TVOUT_MUX_L
SB_GPIO36
SB_CLINK_VREF0
=PP3V3_S5_SB
LINDACARD_GPIO
FWH_MFG_MODE
ARB_DETECT_L
SB_GPIO6
=PP3V3_S0_SB_GPIO
EXTGPU_RST_L
SB_SDATAOUT<0> SB_SDATAOUT<1>
R2510
1
2
R2515
1
2
R2516
1
2
R2511
1
2
R2512
1
2
R2502
1
2
R2504
1
2
R2500
1
2
R2507
1
2
R2506
1
2
R2505
1
2
U2300
AE21
AG12
E1
F23 AE18
F22 AF19
AJ23
D24 AH23
AG9 G5
AH11
E3
AJ14
AF22
AC19
AH12 AE11
AE16
AH20
AG21
AJ13 AJ24
AJ27
C2
AE23
AH25 AD16
AF17
AG27
AH27
AJ12 AJ10 AF11 AG11
AG13
AG10
AJ11 AD10
AF12
AF9
AJ25
AG23 AF21 AD18
AG22
AJ26 AD19
AC17 AE19
AD9
AG18
AE20
F4 D3
AD15
AG8
AJ8 AJ9 AH9
AC13
AJ21
AJ22
AJ20
AE17
AG19
R2526
1
2
R2527
1
2
C2500
1
2
R2529
1
2
R2528
1
2
C2501
1
2
R2523
1
2
R2536
1 2
R2544
1 2
R2545
1 2
R2525
1
2
R2534
2
1
R2552
1
2
R2550
1
2
R2553
1
2
R2551
1
2
R2598
1 2
R2546
1 2
R2532
2
1
R2533
2
1
R2535
2
1
R2547
2
1
R2524
1
2
R2530
1 2
R2531
1 2
R2514
2
1
R2596
1 2
R2597
1 2
25
27
27
47
25
23
38
25
45
25
25
23
28
8
8
25
83
25
8
25
25
25
25
25
36
8
25
25
25
25
25
8
83
8
7
25
25
25
8
25
VSS
VSS_NCTF
VSS
(5 OF 6)
VCC1_5_B
V5REF_SUS
VCCDMIPLL
VCC_DMI
VCC3_3
VCC1_05
V5REF
VCCCL1_5
VCCGLANPLL
VCC3_3
VCC1_5_A
VCC3_3
VCCHDA
VCCSUS1_5
VCCSUS3_3
V_CPU_IO
VCC3_3
VCCSUSHDA
VCC1_5_A
VCC3_3
VCCSATAPLL
VCCGLAN3_3
VCCSUS3_3
VCCLAN3_3
VCCCL1_05
VCCSUS1_05
VCCSUS1_5
VCCSUS3_3
VCCA3GP
VCCGLAN1_5
VCCCL3_3
VCCLAN1_05
VCC1_5_A24
VCC1_5_A
VCCRTC
VCC1_5_A
VCCUSBPLL
VCC1_5_A
VCC1_5_A
VCC1_5_A
GLAN POWER
USB CORE
ATX ARX
(6 OF 6)
VCCPSUS
IDE
COREVCCP CORE
PCI
VCCPUSB
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
6 uA S0-G3
1 mA
1 mA S0-S5
657 mA
Current numbers from ICH8M Max Power Estimates Rev 2.0, doc #610194.
Current figures provided assume 1.5V.
depending on VIO of HD Audio interface.
VccHDA and VccSusHDA can be 1.5V or 3.3V
NOTE:
1130 mA
23 mA
50 mA
1 mA
(VCC3_3 total)
442 mA
117 mA S0,
11 mA S0,
44 mA S3-S5
1 mA S3-S5
(VCCSUS3_3 total)
32 mA
1080 mA
47 mA
(VCC1_5_A total)
63 mA M1 & WOL
19 mA S0,
10 mA
23 mA 80 mA
1 mA
51 mA M1 & WOL
19 mA S0,
1uF
6.3V CERM
10%
402 402
CERM
10V
20%
0.1uF
ICH8M
BGA
OMIT
BGA
ICH8M
OMIT
SYNC_MASTER=T9_NOME
051-7225
8826
A.0.0
SYNC_DATE=03/16/2007
SB Power & Ground
=PP3V3_S0_SB_VCC3_3_PCI
=PP1V5_S0_SB_VCCUSBPLL
PP3V3_G3_SB_RTC
TP_VCCLAN1_05_INTERNAL_REG1 TP_VCCLAN1_05_INTERNAL_REG2
TP_VCCSUS1_05_INTERNAL_REG2
TP_VCCSUS1_5_INTERNAL_REG2
TP_VCCSUS1_05_INTERNAL_REG1
TP_VCCCL1_05_INTERNAL_REG
=PP3V3_S0_SB_VCCGLAN3_3
PP1V5_S0_SB_VCCSATAPLL
=PP3V3_S0_SB_VCC3_3_DMI
=PP3V3_S5_SB_3V3_VCCSUSHDA
=PP3V3_S0_SB_VCC3_3_SATA
TP_VCCSUS1_5_INTERNAL_REG1
=PP3V3R1V5_S0_SB_VCCHDA
PP1V5_S0_SB_VCCGLANPLL
PP1V5_S0_SB_VCCDMIPLL
PP5V_S5_SB_V5REF_SUS
=PP1V5_S0_SB_VCCGLAN1_5
=PP3V3_S0MWOL_SB_VCCCL3_3
=PP1V5_S0_SB_VCC1_5_A_USB_CORE
=PP1V5_S0_SB_VCC1_5_A
=PP3V3_S0MWOL_SB_VCCLAN3_3
=PP3V3_S5_SB_VCCSUS3_3_USB
=PP3V3_S5_SB_VCCSUS3_3
=PP1V5_S0_SB_VCC1_5_A_ATX
=PP1V5_S0_SB_VCC1_5_A_ARX
=PP1V25_S0_SB_DMI
=PPVCORE_S0_SB
VCCCL1_5V
PP5V_S0_SB_V5REF
PP1V5_S0_SB_VCC1_5_B
=PP3V3_S0_SB_VCC3_3_IDE
=PP3V3_S0_SB_VCC3_3_VCCPCORE
=PP1V05_S0_SB_CPU_IO
U2300
A23
A5
AC26
L13 L15 L26 L27 L4 L5 M12 M13 M14 M15
AC27
M16 M17 M23 M28 M29 M3 N1 N11 N12 N13
AD17
N14 N15 N16 N17 N18 N26 N27 N4 N5 N6
AD20
P12 P13 P14 P15 P16 P17 P23 P28 P29 R11
AD28
R12 R13 R14 R15 R16 R17 R18 R28 R4 T12
AD29
T13 T14 T15 T16 T17 T2 U12 U13 U14 U15
AD3
U16 U17 U23 U26 U27 U3 U5 V13 V15 V28
AD4
V29 W2 W26 W27 Y28 Y29 Y4 AB4 AB23 AB5
AD6
AB6 AD5 U4 W24
AE1
AA2
AE12
AE2
AE22
AD1
AE25
AE5 AE6
AE9 AF14 AF16
AA7
AF18
AF3
AF4
AG5
AG6 AH10 AH13 AH16 AH19
AH2
A25
AF28 AH22 AH24 AH26
AH3
AH4
AH8
AJ5
B11
B14
AB1
B17
B2 B20 B22
B8 C24 C26 C27
C6 D12
AB24
D15 D18
D2
D4 E21 E24
E4
E9 F15 E23
AC11
F28 F29
F7
G1
E2 G10 G13 G19 G23 G25
AC14
G26 G27 H25 H28 H29
H3
H6
J1 J25 J26
AC25
J27
J4
J5 K23 K28 K29
K3
K6
K7 L1
A1 A2
B1 B29
A28 A29 AH1 AH29 AJ1 AJ2 AJ28 AJ29
U2300
A16
T7
G4
AC23 AC24
A13 B13
L14 L16 L17 L18 M11 M18 P11 P18 T11 T18
C13
U18 V17 V14 V11 U11 V18 V16 V12
C14 D14 E14 F14 G14 L11 L12
AE7 AF7
AC10
AC9
AA5 AA6
G12 G17
H7
AC7 AD7
F1
AG7
L6 L7 M6 M7
W23
AH7 AJ7
AC1 AC2 AC3 AC4 AC5
AA25 AA26
E27 F24 F25 G24 H23 H24 J23 J24 K24 K25
AA27
L23 L24 L25 M24 M25 N23 N24 N25 P24 P25
AB27
R24 R25 R26 R27 T23 T24 T27 T28 T29 U24
AB28
W25 V24 U25 Y25 V25 V23
AB29
D28 D29 E25 E26
AF29
AD2
W6 W7 Y7
A8 B15 B18 B4 B9 C15 D13
AC8
D5 E10 E7 F11
AD8 AE8 AF8
AA3 U7 V7 W1
AE28 AE29
G22
A22
F20 G21
R29
B27 A27 B28 B26 A26
B25
A24
AC12
F17 G18
F19 G20
AD25
AJ6
J6 AF20
AC16
J7
C3
AC18
P1 P2 P3 P4 P5 R1 R3 R5 R6
AC21 AC22 AG20 AH28
P6 P7 C1 N7
AD11
D1
C2600
1
2
C2601
1
2
28
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
24
27
23
8
8
23
8
27
8
8
8
8
27
27
27
27
8
8
8
8
8
8
8
8
8
8
27
23
8
8
8
NCNC
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
REFERENCE DESIGNATOR(S)
BOM OPTION
TABLE_5_HEAD
QTY
DESCRIPTION
PART#
TABLE_5_ITEM
PLACE C2736 NEAR PIN B27..A26
PLACE CAPS < 2.54MM OF SB ON SECONDARY OR 3.56MM ON PRIMARY NEAR PIN AJ6
38 mA S0 / 114 mA M1 & WOL
(ICH INTEL HDA SUSPEND 3.3V/1.5V PWR)
ICH VCCSUSHDA BYPASS
1 mA S3-S5
11 mA S0 /
32 mA (@ 1.5V)
(@ 1.5V)
ICH USB/VCCSUS3_3 BYPASS
0.6 uA G3
Current numbers from ICH8M Max Power Estimates Rev 2.0, doc #610194.
(ICH IO,LOGIC 1.5V PWR)
ICH VCCSUS3_3 BYPASS
117 mA S0 /
44 mA S3-S5
442 mA
(VCCSUS3_3 Total)
PLACEMENT NOTE:
P6..R6
PLACEMENT NOTE: PLACE CAPS NEAR PIN AD25 OF SB
(ICH SUSPEND 3.3V PWR)
PLACE CAPS NEAR PINS AC18..AH28
PLACE CAP NEAR PINS
PLACEMENT NOTE:
(ICH SUSPEND USB 3.3V PWR)
ICH VCCRTC BYPASS (ICH RTC 3.3V PWR)
1080 mA
(VCC1_5_A Total)
657 mA
80 mA
ICH VCC1_5_B BYPASS
47 mA
33 mA
(ICH SATA PLL PWR)
ICH VCCSATAPLL Filter
23 mA
(ICH DMI PLL PWR)
ICH VCCDMIPLL Filter
33 mA
47 mA
23 mA
PLACEMENT NOTE: PLACE CAPS < 2.54MM OF SB ON SECONDARY SIDE OR 3.56MM ON PRIMARY
OR 3.56MM ON PRIMARY NEAR PIN A24
PLACE CAPS < 2.54MM OF SB ON SECONDARY
837 mA
PLACEMENT NOTE:
PLACEMENT NOTE:
PLACEMENT NOTE:
1 mA
ICH V5REF Filter & Follower
1 mA
PLACE C2703 < 2.54MM OF PIN A16..T7 OF SB
ON SECONDARY SIDE OR 3.56MM ON PRIMARY
1 mA S0-S5
1 mA S0-S5
(VCC3_3 Total)
3.56MM ON PRIMARY NEAR PINS AA3...Y7
PLACE < 2.54MM OF SB ON SECONDARY OR
PLACEMENT NOTE: PLACE < 2.54MM OF SB ON SECONDARY OR 3.56MM ON PRIMARY NEAR PIN AD2
PLACEMENT NOTE:
PLACEMENT NOTE:
PLACE < 2.54MM OF SB ON SECONDARY OR 3.56MM ON PRIMARY NEAR PIN AD11
PLACE < 2.54MM OF SB ON SECONDARY OR 3.56MM ON PRIMARY NEAR PIN AC12
PLACEMENT NOTE:
NEAR PINS A8 ... F11
DISTRIBUTE IN PCI SECTION OF SB
OR 3.56MM ON PRIMARY NEAR PIN AF29
PLACE CAP < 2.54MM OF SB ON SECONDARY
PLACEMENT NOTE:
PLACEMENT NOTE:
ICH VCCHDA BYPASS (ICH INTEL HDA CORE 3.3V/1.5V PWR)
ICH PCI/VCC3_3 BYPASS (ICH PCI I/O 3.3V PWR)
(ICH IDE I/O 3.3V PWR)
ICH IDE/VCC3_3 BYPASS
(ICH LAN I/F BUFFER 3.3V PWR)
ICH VCC_PAUX/VCCLAN3_3 BYPASS
PLACE CAP UNDER SB NEAR PINS F19 AND G20
PLACEMENT NOTE:
PLACEMENT NOTE: PLACE CAPS AT EDGE OF SB
ICH V_CPU_IO BYPASS (ICH CPU I/O 1.05V PWR)
50 mA
1 mA
1130 mA
ICH CORE/VCC1_05 BYPASS (ICH CORE 1.05V PWR)
10 mA
3.56MM ON PRIMARY NEAR PIN AC1..AC5
PLACEMENT NOTE:
PLACEMENT NOTE:
PLACE NEAR PINS AC23,AC24 OF SB
OR 3.56MM ON PRIMARY NEAR PIN AE29
PLACE < 2.54MM OF SB ON SECONDARY
PLACEMENT NOTE:
(ICH USB PLL 1.5V PWR)
ICH VCCUSBPLL BYPASS
PLACE C2715 NEAR PIN D1 OF SB
3.56MM ON PRIMARY NEAR PINS F1..M7
ICH USB CORE/VCC1_5_A BYPASS
PLACE < 2.54MM OF SB ON SECONDARY OR
(ICH USB CORE 1.5V PWR)
PLACEMENT NOTE: PLACE < 2.54MM OF SB ON SECONDARY OR
PLACEMENT NOTE:
PLACEMENT NOTE:
3.56MM ON PRIMARY NEAR PINS AE7..AJ7
PLACE < 2.54MM OF SB ON SECONDARY OR
ICH VCC1_5_A/ATX BYPASS (ICH LOGIC&IO[ATX] 1.5V PWR)
(ICH LOGIC&IO[ARX] 1.5V PWR)
ICH VCC1_5_A/ARX BYPASS
ICH V5REF_SUS Filter & Follower
(ICH GLAN PLL PWR)
PLACEMENT NOTE: PLACE C2704 < 2.54MM OF PIN G4 OF SB
(ICH Reference for 5V Tolerance on Core Well Inputs)
ON SECONDARY SIDE OR 3.56MM ON PRIMARY
(ICH Reference for 5V Tolerance on Resume Well Inputs)
ICH VCCGLANPLL Filter
PLACEMENT NOTE:
ON SECONDARY SIDE OR 3.56MM ON PRIMARY
PLACE C2700 & C2705-07 < 2.54MM OF SB
DISTRIBUTED BETWEEN AA25..V23
PLACEMENT NOTE:
220UF
2.5V POLY
20%
CASE-B2
CRITICAL
X5R 402
16V
10%
0.1UF
1
1/10W MF-LF
5%
603
4.7UF
6.3V
20%
CERM
603
0.1UF
10% 16V
402
X5R
SOT-363
BAT54DW
SOT-363
BAT54DW
1210
1.0UH-0.5A
X5R
6.3V
20%
10UF
603
X5R 402
16V
10%
0.1UF
1UF
10% 402
CERM
6.3V
2.2uF
603
CERM1
20%
6.3V
6.3V
20% CERM
603
4.7uF
4.7uF
CERM 603
20%
6.3V
X5R 402
16V
10%
0.1UF
0.1UF
10% 16V
402
X5R
10UH-100MA
0805
0.1UF
10% 16V
402
X5R
6.3V
22UF
805-3
20% CERM-X5R
X5R 402
16V
10%
0.1UF
402
5%
MF-LF
1/16W
0
100
MF-LF
1/16W
5%
402
10
MF-LF
1/16W
5%
402
0.1UF
10% 16V
402
X5R
OMIT
SM
FERR-330-OHM
805-3
6.3V
20%
22UF
CERM-X5R
22UF
805-3
CERM-X5R
6.3V
20%
6.3V
20% CERM1
2.2UF
603
402
CERM
16V
0.01UF
10%
603
10UF
20%
6.3V X5R
6.3V CERM 402
1UF
10%
6.3V CERM 402
10%
1UF
X5R 402
16V
10%
0.1UF
X5R 402
16V
10%
0.1UF
0.1UF
10% 16V
402
X5R
X5R 402
16V
10%
0.1UF
0.1UF
10% 16V
402
X5R
X5R 402
16V
10%
0.1UF
X5R 402
16V
10%
0.1UF
X5R 402
16V
10%
0.1UF
X5R 402
16V
10%
0.1UF
0.1UF
10% 16V
402
X5R
0.1UF
10% 16V
402
X5R
0.1UF
10% 16V
402
X5RX5R
402
16V
10%
0.1UF
155S0333
1
FLTR,EMI BEAD,330 OHM,1.5A,0805,SMD
L2700
SYNC_MASTER=T9_NOME
SB Decoupling
SYNC_DATE=01/17/2007
27 88
A.0.0
051-7225
=PP5V_S5_SB
PP1V5_S0_SB_VCCGLANPLL
=PP1V5_S0_SB
=PP1V5_S0_SB_VCC1_5_A_ATX
=PP1V5_S0_SB_VCC1_5_A_ARX
=PP1V5_S0_SB_VCC1_5_A_USB_CORE
=PP1V5_S0_SB_VCCUSBPLL
=PP1V25_S0_SB_DMI
=PPVCORE_S0_SB
=PP1V05_S0_SB_CPU_IO
=PP3V3_S0MWOL_SB_VCCLAN3_3 =PP3V3_S0MWOL_SB_VCCCL3_3
=PP3V3_S0_SB_VCC3_3_IDE
=PP3V3_S0_SB_VCC3_3_SATA
=PP3V3_S0_SB_VCC3_3_DMI
=PP3V3R1V5_S0_SB_VCCHDA
=PP3V3_S5_SB_3V3_VCCSUSHDA
=PP3V3_S0_SB_VCC3_3_PCI
=PP3V3_S5_SB
MIN_LINE_WIDTH=0.3MM
PP5V_S5_SB_V5REF_SUS
MIN_NECK_WIDTH=0.25MM VOLTAGE=5V
=PP5V_S0_SB
=PP3V3_S0_SB
VOLTAGE=5V
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.3MM
PP5V_S0_SB_V5REF
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM VOLTAGE=1.5V
PP1V5_S0_SB_VCCDMIPLL_F
PP1V5_S0_SB_VCCSATAPLL_F
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM VOLTAGE=1.5V
PP1V5_S0_SB_VCCDMIPLL
VOLTAGE=1.5V
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM
VOLTAGE=1.5V
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM
PP1V5_S0_SB_VCCSATAPLL
=PP1V5_S0_SB_VCCGLAN1_5
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.5 mm
MAKE_BASE=TRUE
VOLTAGE=1.5V
PP1V5_S0_SB_VCC1_5_B
=PP3V3_S5_SB_VCCSUS3_3_USB
PP3V3_G3_SB_RTC
=PP3V3_S5_SB_VCCSUS3_3
C2700
1
2
R2700
1 2
C2703
1
2
C2704
1
2
L2700
1 2
C2705 C2706 C2707
C2701
1
2
C2708
1
2
C2717
C2714
1
2
C2715
1
2
C2718
1
2
C2719
1
2
C2721
1
2
C2723
1
2
C2725
1
2
C2726
1
2
C2727
1
2
C2728
1
2
C2729
1
2
C2730
1
2
C2734
1
2
C2731
1
2
C2712
1
2
C2724
1
2
C2722
1
2
D2702
1
6
5
D2702
4
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