Apple A1226 Schematic

ANGLES

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

DATE

APPD

ENG

DATE

APPD

CK

ECN

ZONE

REV

DO NOT SCALE DRAWING

X.XXX

X.XX

XX

DIMENSIONS ARE IN MILLIMETERS

THIRD ANGLE PROJECTION

D

SIZE

APPLICABLE

NOTED AS

MATERIAL/FINISH

NONE

SCALE

DESIGNER

MFG APPD

DESIGN CK

RELEASE

QA APPD

ENG APPD

DRAFTER

METRIC

OF

SHT

DRAWING NUMBER

TITLE

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

Apple Computer Inc.

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

DESCRIPTION OF CHANGE

TABLE_TABLEOFCONTENTS_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_HEAD

DRAWING

SCHEM,MLB,MBP15

Schematic / PCB #’s

04/24/2007

051-7225

1

? ??

??

88

A.0.0

TITLE=MLB

ABBREV=DRAWING

Page

Date

(.csa)

Contents Sync

820-2101

1

PCB

CRITICAL

Page Contents

Date

Sync

(.csa)

45

SMC

49

01/17/2007

T9_NOME

1

N/A

1 N/A

Table of Contents

1

051-7225 CRITICAL

SCH

46

SMC Support

50

(MASTER)

47

LPC+ Debug Connector

51

03/19/2007

M76_MLB

48

SMBus Connections

52

(MASTER)

49

Current & Voltage Sensing

53

(MASTER)

50

Current Sensing

54

(MASTER)

51

Thermal Sensors

55

(MASTER)

52

Fan Connectors

56

03/19/2007

M76_MLB

53

ALS Support

58

03/19/2007

M76_MLB

54

Sudden Motion Sensor (SMS)

59

03/19/2007

M76_MLB

55

SPI BootROM

61

03/16/2007

T9_NOME

56

PBus-In & Battery Connectors

69

09/09/2006

(M59_SYNC)

57

Power FETs

70

03/19/2007

M76_MLB

58

IMVP6 CPU VCore Regulator

71

01/23/2007

M76_MLB

59

IMVP6 NB Gfx Core Regulator

72

03/19/2007

M76_MLB

60

5V / 3.3V Power Supply

73

03/19/2007

M76_MLB

61

1.25V / 1.05V Power Supply

74

03/12/2007

M76_MLB

62

1.8V DDR2 Supply

75

03/19/2007

M76_MLB

63

1.5V Power Supply

76

03/12/2007

M76_MLB

64

FW PHY Power Supplies

77

03/19/2007

M76_MLB

65

3.425V G3Hot Supply & Power Control

78

(MASTER)

66

NV G84M PCI-E

80

(MASTER)

67

NV G84M Core/FB Power

81

(MASTER)

68

NV G84M Frame Buffer I/F

82

(MASTER)

69

GDDR3 Frame Buffer A

84

(MASTER)

70

GDDR3 Frame Buffer B

85

(MASTER)

71

NV G84M GPIO/MIO/Misc

86

(MASTER)

72

GPU Straps

87

(MASTER)

73

NV G84M Video Interfaces

88

(MASTER)

74

GPU (G84M) Core Supply

89

(MASTER)

75

LVDS Display Connector

90

(MASTER)

76

DVI Display Connector

94

(MASTER)

77

LVDS Interface Mux

95

(MASTER)

78

Project Specific Connectors

96

08/24/2006

(M59_SYNC)

79

CPU/FSB Constraints

100

01/17/2007

T9_NOME

80

NB Constraints

101

01/17/2007

T9_NOME

81

Memory Constraints

102

01/17/2007

T9_NOME

82

SB Constraints (1 of 2)

103

01/17/2007

T9_NOME

83

SB Constraints (2 of 2)

104

01/17/2007

T9_NOME

84

Clock & SMC Constraints

105

01/17/2007

T9_NOME

85

FireWire Constraints

106

01/17/2007

T9_NOME

86

GPU (G84M) Constraints

107

(MASTER)

87

Project Specific Constraints

108

(MASTER)

88

PCB Rule Definitions

109

(MASTER)

2

(T9_MLB)

2

08/23/2006

System Block Diagram

3

(T9_MLB)

3

08/23/2006

Power Block Diagram

4

N/A

4 N/A

Power Block Diagram

5

N/A

5 N/A

BOM Configuration

6

N/A

6 N/A

Revision History

7

(MASTER)

7

(MASTER)

Functional / ICT Test

8

(MASTER)

8

(MASTER)

Power Aliases

9

(T9_MLB)

9

08/23/2006

Signal Aliases

10

T9_NOME

10

03/16/2007

CPU FSB

11

T9_NOME

11

03/16/2007

CPU Power & Ground

12

M76_MLB

12

03/19/2007

CPU Decoupling & VID

13

T9_NOME

13

12/12/2006

eXtended Debug Port (XDP)

14

T9_NOME

14

03/16/2007

NB CPU Interface

15

T9_NOME

15

03/16/2007

NB PEG / Video Interfaces

16

T9_NOME

16

03/16/2007

NB Misc Interfaces

17

T9_NOME

17

03/16/2007

18

T9_NOME

18

03/16/2007

NB Power 1

19

T9_NOME

19

03/16/2007

20

T9_NOME

20

03/16/2007

21

T9_NOME

21

01/17/2007

M76_MLB

22

03/12/2007

23

T9_NOME

23

03/16/2007

SB Enet, Disk, FSB, LPC

24

T9_NOME

24

03/16/2007

SB PCI, PCIe, DMI, USB

25

T9_NOME

25

03/16/2007

SB Pwr Mgt, GPIO, Clink

26

T9_NOME

26

03/16/2007

SB Power & Ground

27

T9_NOME

27

01/17/2007

SB Decoupling

28

(T9_MLB)

28

08/24/2006

SB Misc

29

T9_NOME

29

03/16/2007

Clock (CK505)

30

(MASTER)

30

08/23/2006

Clock Termination

31

(M59_SYNC)

31

08/24/2006

DDR2 SO-DIMM Connector A

32

(M59_SYNC)

32

08/24/2006

DDR2 SO-DIMM Connector B

33

(T9_NOME)

33

11/14/2006

Memory Active Termination

34

(M59_SYNC)

34

08/24/2006

Left I/O Board Connector

35

T9_NOME

37

03/16/2007

Ethernet (Yukon)

36

T9_NOME

38

03/16/2007

Yukon Power Control

37

M76_MLB

39

03/19/2007

Ethernet Connector

38

M76_MLB

40

03/19/2007

FireWire Link (TSB83AA22)

39

M76_MLB

41

03/19/2007

FireWire PHY (TSB83AA22)

40

M76_MLB

42

03/19/2007

FireWire Port Power

41

M76_MLB

43

03/19/2007

FireWire Ports

42

(MASTER)

44

(MASTER)

PATA Connector

43

M76_MLB

46

03/19/2007

External USB Connector

44

M76_MLB

47

03/19/2007

Left Clutch Barrel Interconnect

NB DDR2 Interfaces

NB Power 2 NB Grounds NB Standard Decoupling NB Graphics Decoupling

22

SCHEM,MLB,MBP15

PCBF,MLB,MBP15

SCHEM,MLB,MBP15

LAST_MODIFIED=Tue Apr 24 17:23:54 2007

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Pg 15

Pg 17,18,19

Pg 77

Pg 79,81

3.3 V

100 MHz

J4400

Pg 35

DVI-I

MUX

GPIO

Conn

Int Disp

Pg 78

U1000

Pg 10

2.? GHz

CPU

Pg 9

Core ~1.2V

ITP/XDP CONN

J1300/JD000

Pg 28

TERMS Pg 29

UC500

Clocks

Pg 98

CK 505

U2900

Pg 98

Clocks

Pg 13

U1400

PCI-E

Pg 14

J8000

FSB

64-Bit

800/1066? MHz

SDVO

x16 PCI-E

Main Memory

Misc

Parallel

Term

Pg 32

NB-GMCH

Core

DMI

Pg 15

CLnk 0

Pg 15

DDR2 - Dual Channel

1.8V - 64 Bits

J3100 J3200

DIMM

Pg 15/16

TV

Out

RGB

LVDS

Pg 14

x4 DMI

2.5 GHz

J9200

J9200 Source is the LVDS from the PEG based GPU.

MUX

Pg 80

GPIO

J4510/20/30

1.2 V / 1.5 GHz

SATA Conn

Pg 43

UATA Conn

Pg 42

JB200 JB300 JB400

PCI-E Conns

Pg 93/4/5

UB100

6 - x1

2.5 GHz

PCI-E

Pg 92

MUX

DMI

Pg 23

CLnk 0

Pg 24

SPI

Pg 23

6 7 8 951 2 3 4

Core

Pg 25

E-NET

Pg 22

CLnk 1

Pg 24

PCI

Pg 23

AZALIA

USB

Pg 23

Pg 22

DIMM’s

Clk Gen J3100 J3200

U2900 UC500

U6100/50

SPI

Boot ROM

Pg 58

A

B,0 BSA BSB

ADC

Fan

Ser Prt

SMC

U4900

Pg 46

U6000

TPM

Pg 57

J5100

LPC Conn

Pg 48

Fan Conn Pg 53, 54

J6900/50

Pg 66

Power

Temp Sense

Charger

Right Side

GPU

CPU

Linda Fnc

Prt 80, Comm 1, SMC, FWH

J4630

USB

Connectors

Pg 44

J4710

Camera/IR

Pg 45

J4720

Bluetooth

Pg 45

J4700

Trackpad/Keyboard

Geyser

Pg 45

MDC

Pg ??

U????U6200

Audio Codec

Pg 59

U6300/1

U6400 U6500

U6600/10/20

Line In

Amp

Pg 60

Line Out

Pg 61

Amp 1

Line Out

Amp 2

Pg 62

Speaker

Amps

Pg 63

Conns

Audio

Pg 65

J3400

Pg 33

Mini PCI-E

AirPort

JB500

PCI-E

Conn

U3700

NINEVEH

E-NET

Pg 37

Conn

E-NET

J4630

33 MHz 32-Bit

U4000

TSB82AA2

Pg 38

FW-Link

U4100

TSB81BA3

Pg 39

FW-PHY

J4320 J4330

FireWire

Conn

Pg 41

JB000

PCI

Conn

Pg 91

100 MHz

8-Bit

Ln1 Ln2 Ln3 Ln4 Ln5 Ln6

Pg 22

UATA

PCI-E

Pg 23

SATA-0 SATA-1 SATA-2

SATA

Pg 22

U2300

SB-ICH8

Core 1.05V

Pg 22Pg 24

GPIOsSMB LPC

Pg 24

Pg 51 Pg 52 Pg 52 Pg ??

ReGen

TERMS

J5810/20/90 ALS SENS Pg 55

U5920 Sudden Motion Detect Pg 56

Pg30,31

533/667/800? MHz

1.05 - 1.25V

PEG Connector

Conn

Pg 68-76

Supply

DC/Batt

U5500 U5550 U???

U5572

Power Sense Pg 51, 115-120

J5600/10/50/60, J5720/30/50

Pg 124-130

Pg 12/103

Pg 96

J4600

J6800/1/2/3

J9400

U9120

J9000/10

U9250/60

Approximate System Block Diagram

SYNC_DATE=08/23/2006

System Block Diagram

051-7225

2

88

A.0.0

SYNC_MASTER=(T9_MLB)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Power Block Diagram

051-7225

A.0.0

88

3

SYNC_MASTER=(T9_MLB) SYNC_DATE=08/23/2006

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

SYNC_DATE=N/A

SYNC_MASTER=N/A

4

88

A.0.0

051-7225

Power Block Diagram

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

Bar Code Labels / EEE #’s

Module Parts

IS

M75 BOM Groups

BOM Variants

337S3464

IC,MDC,SR,E1,PRQ,2.2G,35W,800FSB,4M,BGA

1

U1000 CPU_2_2GHZ

CRITICAL

337S3465

IC,MDC,SR,E1,PRQ,2.4G,35W,800FSB,4M,BGA

CPU_2_4GHZU1000

1

CRITICAL

1

IC,GPU,NV G84M,BGA

338S0388

U8000

CRITICAL

IC,NB,CRESTLINE,GM,C0,PRQ,965PM

338S0432

1

CRITICAL

U1400

IC,ISL9504,SYNC REG CTRL,2PHAS,QFN48,LF

353S1461 ISL9504A

1

U7100

CRITICAL

IC,ISL9504B,2PH IMVP6 REG,PMON,QFN48

ISL9504B353S1651

1

CRITICAL

IC,68 PIN,CK505,LOW POWER CLOCK GENER

SLG8LP537

CRITICAL359S0127

1

IC,SLG2AP101,LW PWR CLCK GEN,CK505,QFN68

SLG2AP101

1

CRITICAL

U2900

359S0130

IC,88E8058,GIGABIT ENET XCVR,64P QFN

CRITICAL

1

U3700

338S0386

IC,SMC,HS8/2116

338S0274 CRITICAL

SMC_BLANK

1

IC,16MBIT 8-PIN SPI SERIAL FLASH,SOIC8

1

335S0384

U6100

BOOTROM_BLANK

CRITICAL

341S2002 CRITICAL

1

BOOTROM_PROG

U6100

IC,EFI ROM,DEVELOPMENT,M75

VRAM_128_SAMSUNG

IC,SGRAM,GDDR3,8Mx32,700MHZ,136 FBGA

4

U8400,U8450,U8500,U8550

333S0404

IC,SGRAM,GDDR3,8Mx32,700MHZ,136 FBGA

VRAM_128_HYNIX

CRITICAL

4

U8400,U8450,U8500,U8550

333S0409

IC,SGRAM,GDDR3,16Mx32,700MHZ,136 FBGA

VRAM_256_HYNIX

U8400,U8450,U8500,U8550

4

CRITICAL333S0401

M75_COMMON1

BOOTROM_PROG,SMC_PROG

M75_PROGPARTS

630-7931

M75_COMMON,EEE_X5D,CPU_2_2GHZ,FB_128_SAMSUNG

152S0276

ALL

152S0476

Inductor alternate

IC,SGRAM,GDDR3,16Mx32,700MHZ,136 FBGA

VRAM_256_SAMSUNG

U8400,U8450,U8500,U8550

4

CRITICAL333S0382

IC,SMC,DEVELOPMENT,M75

U4900

1

SMC_PROG

CRITICAL341S2004

338S0434

IC,SB,ICH8M,B1,PRQ,BGA

CRITICAL

1

U2300

630-7932

M75_COMMON,EEE_X5E,CPU_2_4GHZ,FB_256_SAMSUNG

630-8662

M75_COMMON,EEE_XXT,CPU_2_4GHZ,FB_256_HYNIX

[EEE:X5D]

CRITICAL

EEE_X5D

826-4393

1

ALL

138S0602

Murata alt to Samsung

138S0603

ALL TI alt to National

353S1681 353S1294

ALL

157S0011

E&E alt to TDK/BI-Tech magnetics

157S0030

630-8659

M75_COMMON,EEE_XXS,CPU_2_2GHZ,FB_128_HYNIX

VRAM_256,VRAM_SAMSUNG,VRAM_256_SAMSUNG

VRAM_256,VRAM_HYNIX,VRAM_256_HYNIX

[EEE:X5E]

826-4393

EEE_X5E

CRITICAL

1

826-4393 CRITICAL

[EEE:XXT]

EEE_XXT

CRITICAL826-4393

1

[EEE:XXS]

EEE_XXS

VRAM_128,VRAM_HYNIX,VRAM_128_HYNIX

VRAM_128,VRAM_SAMSUNG,VRAM_128_SAMSUNG

M75_COMMON

M75_DEBUG

SMC_DEBUG_NO,XDP,LPCPLUS

SYNC_DATE=N/A

051-7225

A.0.0

88

5

SYNC_MASTER=N/A

BOM Configuration

ALTERNATE,COMMON,M75_COMMON1,M75_COMMON2,M75_DEBUG,M75_PROGPARTS

M75_COMMON2

P1V8S3_1V825,SLG2AP101,SMS_MOT_DIS,YUKON_ULTRA,VGA_TERM_CONN

EXTGPU_RST_HW,ISL9504B,LVDS_SEL_RESUME,ONEWIRE_PU

PCBA,2.4GHZ,256SAM_VRAM,M75,MBP15

PCBA,2.2GHZ,128SAM_VRAM,M75,MBP15

PCBA,2.2GHZ,128HY_VRAM,M75,MBP15 PCBA,2.4GHZ,256HY_VRAM,M75,MBP15

CRITICAL

U4900

U2900

U7100

LBL,P/N LABEL,PCB,28MM X 6 MM

FB_256_HYNIX

FB_256_SAMSUNG

FB_128_HYNIX

FB_128_SAMSUNG

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

04/24/07 -- SMC Support: Changed R5031 to 2.37K, R5032 to 9.09K to meet SIL brightness targets

04/18/07 -- Modules: Updated Intel chipset to PRQ parts

16.3.0: 04/20/07 -- Power FETs: Changed R7097 to 220K to maintain EnergyStar compliance with FET gate pulled to PBUS 04/20/07 -- Power FETs: Changed C7095/C7083 to 16V for proper rating of parts tied to PBUS 04/20/07 -- CPU VCore: Changed C7196 to 16V to eliminate a BOM item

See Perforce change notes for updates before Proto Release 12/22/06 -- Released for Proto (Schem Rev 08, PCB Rev 01)

01/05/07 -- Clock Termination: Removed NO STUFF property from R3067

04/24/07 -- SB Decoupling: Changed L2700 from 155S0152 to 155S0333 for AVL updates

01/19/07 -- Power Sequencing: Changed power rail for U7850 to PP3V3_S5 to eliminate a leakage path

01/23/07 -- BOM: Changed C3860/61 to 22pF from 27 pF based on -R characterization (T9_noME change 41248)

01/24/07 -- Power Aliases: Updated PP3V3_S0 aliases to support above changes

01/25/07 -- Released for EVT (Schem Rev 11, PCB Rev 03)

02/19/07 -- Power Sequencing: NO STUFFed U7885 to remove GPU PGOOD from PWROK chain

02/20/07 -- GPU FB: Changed cal resistors per Nvidia PUN (R8290 to 45.3 ohm and R8291 to 24.9 ohm)

02/19/07 -- Released post-EVT to document what was built (Schem Rev 12)

02/19/07 -- GPU PGOOD: Changed C9595 to 330pF to reduce PGOOD delay on powerup

02/19/07 -- GPU Reset: Changed C2885 to 0.047uF to reduce reset delay on powerup

02/19/07 -- Power Sequencing Rework: Short pins 2 and 4 of U7885 to complete PWROK chain

02/20/07 -- GPU FB: Changed unterminated-mode reference voltage to 40% (R8297 -> 1.02K, R8432/82, R8532/82 -> 2.21K)

02/26/07 -- GPU Vcore: NO STUFFed all PWRCTL related components (feature not to be supported)

02/26/07 -- SB GPIOs: Sync’d page25.csa to T9_MLB to get pullup updates

02/28/07 -- Power Aliases: Moving PP1V8_GPU FET source to PP1V8_S3 rather than PP1V8_S3_ISNS to improve power delivery to GPU (rdar://5021462)

02/28/07 -- NB GFX Core: Changed Vcore controller to ISL6263B (part consolidation effort between Apple/Intersil - rdar://5009109)

03/01/07 -- Thermal Sensors: Updated topology of EMC1033 sensors (removed shorts, changed connector caps to 18pF)

03/01/07 -- LVDS Connector: Changed pin 5 of connector from NC to PP3V3_SW_LCD (in case we add extra cable for power - rdar://5024882)

03/02/07 -- Power/Signal Aliases: Added XW0900 to PP5V_S5 to enable layout improvements

03/06/07 -- FireWire Ports: Changed D4260 to PDS340 for lower height

03/06/07 -- Ethernet Connector: Removed RX shorts on Ethernet MDI lines per EMC request

17.0.0:

01/22/07 -- BOM: Selected P1V8S3_1V825 BOMOPTION to lift voltage at FB memories

01/23/07 -- BOM: Changed FB memories to new Samsung and Hynix APNs (also added new BOMOPTIONs to GPU straps)

01/24/07 -- PATA Conn: Added pass FET Q4430 to allow PCIREQ3 (ODD reset GPIO) to pullup to S0

01/25/07 -- PATA Conn: Replaced PCIREQ pass FET with OD buffer to correct a corner case during PLTRST

01/25/07 -- BOM: Updated gain of PP1V25_ENET current sense amplifier to 165 (R5432 to 165K)

01/25/07 -- Power Aliases: Updated PP5V_S0 aliases to support above changes

01/23/07 -- Released for EVT (Schem Rev 10, PCB Rev 02)

01/22/07 -- BOM: Added BOMOPTIONs for SLG2AP101 (primary) and SLG8LP537 (backup)

01/22/07 -- Clock Termination: Added R3051 for Silego 537/101 compatibility

01/24/07 -- PATA Conn: Changed =PP5V_S0_ODDPWREN to =PP3V3_S0_ODDPWREN for minor power savings

02/26/07 -- Thermal Sensors: Updated topology of EMC1033 filter caps (added C5515 next to IC, moved other caps to connectors - rdar://5025773)

02/28/07 -- Left Clutch IC: Updated both I-PEX connectors to new APN (part update for shell plating)

03/01/07 -- NB GFX Decoupling/Power Aliases: Connected VCCD_CRT of NB to GND per CRT disable guidelines

03/06/07 -- SB GPIOs: Changed R2514 from pulldown to pullup to correct auto power-on issue (Linda card detect GPIO)

01/17/07 -- BOM: Consolidated 3 caps on page 59 from 132S0120 to 132S0131

01/17/07 -- Testpoints: Removed FUNC_TEST from NB_RESET_L and FSB_DPWR_L per PCB request

01/17/07 -- Power FETs: Corrected BOM values for 5V/3.3V S3/S0 FETs

04/03/07 -- GPU FB: Changed FB clock termination to 242 ohms (2x121) per Nvidia PUN

03/30/07 -- SIL: Changed R5031 to 2.21K and R5032 to 9.53K to raise SIL current approx 15% (lightpipe dimmed by 20%)

03/19/07 -- Power Supplies: For 1.8, 3.3 and 5V, increased cap size to 0603/0805 on VBST caps (rdar://5070179)

03/19/07 -- Power Control: Tied all 4 5V/3.3V enables (EN1, EN2, EN3, EN5) together as part of PM_G2_EN

03/20/07 -- GPU Vcore: Updated setpoints for GPU Vcore based upon Nvidia Vmin (i.e. 1.05V,1.05V,1.05V,1.125V) 03/20/07 -- FB: Changed FB VREF caps to 2x0.0047uF as required in Nvidia PUN 02736-001-v07 (which requests 1x0.01uF)

15.0.0:

03/30/07 -- Power Supply: Changed 1.05V power supply current limit to 10A from 8A (R7455 to 5.62k -- rdar://5095642) 04/03/07 -- Power Supply: Changed numerous 10K Rs to 100K for Energy Star compliance (rdar://5102118)

04/03/07 -- Released for DVT (BOM update)

04/17/07 -- Power Sequencing: NO STUFFED U7858 and stuffed R7860 to allow SMC to drive S5 enable pins directly 04/17/07 -- Released for DVT (As-Built)

04/18/07 -- GPU Misc: Added R8735-37 to implement PCI DEVID 0x407 in hardware

16.1.0:

PVT

14.0.0:

01/09/07 -- Temp Sensors: NO STUFFed C5520 (circuit should have only 1 cap)

01/12/07 -- Power Supplies: Minor power supply feedback connection changes from M76

PROTO

DVT

01/19/07 -- Power Sequencing: Added C7859 to create RC delay for 1.5 and 1.05V S0 rails

01/19/07 -- GPU GPIOs: Added 2 TPs on GPIOs to make G-state externally visible

01/22/07 -- LIO Conn: Removed unnecessary aliases as T9 reference design now matches M75 (T9_noME change 40998)

03/01/07 -- NB GFX Decoupling: Added R2260 (0.3 ohm, 0603) to bring ESR of regulator output cap in spec (rdar://5000272)

03/12/07 -- Power Control: Corrected alias connections for 5V/3V3 S5 enable signals

13.1.0: 03/13/07 -- BOM Options: Removed HDCP BOM option from stuffing list (feature removed)

03/06/07 -- FireWire Ports: Changed D4260 to PDS540 for higher current capacity

01/25/07 -- BOM: Updated all Intel APNs to use QS parts

12.1.0:

12.0.0:

12.6.0: 03/06/07 -- Power FETs: Changed Q7080 to RJK0301 which provides much lower Rds(on)

12.4.0:

12.3.0:

01/17/07 -- SMBus: Changed R5260 & R5261 from 4.7K to 3.3K

EVT_SE

11.0.0:

10.2.0:

EVT

9.5.0:

9.2.0:

9.4.0:

9.3.0:

8.1.0:

10.1.0:

9.1.0:

12.2.0:

12.5.0:

9.0.0:

8.2.0:

12.7.0:

02/28/07 -- Power Supplies: Replaced APN 152S0511 with 152S0368 (duplicate APNs for same part - rdar://5009109)

02/21/07 -- Power Sequencing: Removed U7885/C7885 to take GFX_PGOOD out of PWR_OK chain (rdar://4974927)

03/06/07 -- DDR2 Regulator: Changed FB resistors to 0.1% to raise guaranteed lowest output voltage

13.0.0:

10.0.0:

13.3.0:

02/27/07 -- ODD Conn: Changed ODD power FET to FDC606P (from FDC638P) for reduced Rds(on) (rdar://4993378)

02/26/07 -- GPU Vcore: Updated voltage setpoints to 1.000/1.070/1.125V (rdar://5021453)

02/21/07 -- FireWire: Changed to Rev C of TI FireWire MCM (APN: 338S0435)

01/22/07 -- Clocks: Changed U2900 to SLG2AP101 as primary clock chip (T9_noME change 40975)

01/19/07 -- SB GPIOs: Changed SB_GPIO42 to WOW_EN and changed pullup to pulldown (T9_noME change 40787)

01/19/07 -- Clock Termination: Changed R3050 and R3055 to bypass discrete muxes for pending change to SLG2AP101

01/19/07 -- Ethernet Conn: Changed resistor short reference designators from R392x to RX392x

01/19/07 -- SB Decoupling: Removed filtering for PP1V5_S0_SB_VCCGLANPLL to enable PP1V5_S0 corrections at SB

01/18/07 -- ODD Conn: Reconnected ODD power FET gate control circuitry to properly implement soft start (added one cap)

01/18/07 -- IMVP: Updated BOMOPTIONs and values for ISL9504B

01/18/07 -- Clock Termination: Changed series termination on all single ended clocks to 33 ohms

13.4.0:

13.5.0:

03/19/07 -- Power Supplies: For 1.8, 3.3 and 5V, removed VBST 0-ohm series R (rdar://5070179)

03/19/07 -- Power Control: Added U7858 to level shift PM_G2_EN from 3.42V to 5V

03/19/07 -- Thermal Sensors: Updated U5500 power alias to indicate device should be on S3 rail

03/16/07 -- Thermal Sensors: Moved remote sensor U5500 to SMC SMBus "A" and S3 power rail to clear I2C addr clash

03/16/07 -- Yukon Power Control: Crystal caps changed to 18pF (rdar://4946795 and rdar://4945362)

03/16/07 -- NB GFX: LVDS_VREFL/VREFH changed to single pin nets to prevent LVDS glitches per Intel

03/16/07 -- Thermal Sensors: Replaced EMC1033 with second EMC1043 for improved noise filtering

03/14/07 -- Constraints: Constrained WWAN_SIM signals to 50 ohms 03/14/07 -- Thermal Sensors/Aliases: Changed mounting pads of Th2H sensor connector to left clutch chassis gnd

13.2.0:

01/08/07 -- GPU FB: Added VREF support for unterminated memory mode (added FETs and pulldown Rs)

12.8.0:

DVT (cont’d)

03/08/07 -- Thermal Sensors: Added R5515/R5516 in case low pass filter is needed for EMC1033

16.0.0:

04/03/07 -- CPU Vcore: Changed R7117,C7134 and R7115,R7130 for calibration improvements (rdar://5085959)

01/18/07 -- Testpoints: Added NO_TEST property to LVDS_L_DATA_N<1>, _N<2>, _P<2> due to lack of layout space for TP

01/17/07 -- Power Aliases: Deleted alias that accidentally eliminated filtering on PP1V5_S0_SB_VCC1_5_B

01/17/07 -- BOM: Added Hynix BOM configurations

01/17/07 -- Power Sequencing: Added RC delay on PP1V8_S3 switcher enable

01/17/07 -- Sync with T9 noME (6.1.4) to pull in WOL_EN and Wake-on-Wireless support

01/17/07 -- Power Aliases: Moved LCD panel FET to PP3V3_S5 from S0

01/12/07 -- Power Aliases: Moved Ethernet to PP3V3_S3 from S5 (layout improvements)

01/05/07 -- GPU FB: Corrected FB CLK termination (added cap and removed connection to VDDQ)

16.2.0: 04/18/07 -- Power FETs: Changed Q7095 to FDM6296 and pulled up to PBUS for better PP1V25_S0 FET Rds(on)

A.0.0:

04/20/07 -- No changes. Weekly BOM release.

04/24/07 -- Released for PVT

6

88

051-7225

Revision History

SYNC_MASTER=N/A

SYNC_DATE=N/A

A.0.0

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

CPUTHMSNS can not be supported due to layout constraints

Fan Connectors

FUNC_TEST

Thermal Diode Connectors

FUNC_TEST

LPC+ Debug Connector

FUNC_TESTFUNC_TEST

FUNC_TEST FUNC_TEST

FUNC_TEST

NO_TEST

System Validation TPs

NB NO_TESTs

6 TPs, 2 with each of above TP pairs

ICT Test Points

Functional Test Points

Left I/O Power Connector

Battery Digital Connector

Left Clutch Barrel Connector

2 TPs per

Other Func Test Points

Current Sense Calibration

RTC Battery Connector

called out separately in these notes.

NOTE: 10 additional GND test points are

Request for at least 10 GND test points

Left ALS Connector

NO_TEST

CPU FSB NO_TESTs

NO_TEST

GPU NO_TESTs

I550 I551

I552

I553

I554

7

88

A.0.0

051-7225

Functional / ICT Test

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

TRUE

HSTHMSNS_D_N

TRUE

HSTHMSNS_D_P

TRUE

RSFSTHMSNS_D_P

TRUE

RSFSTHMSNS_D_N

CPUTHMSNS_D2_N

CPUTHMSNS_D2_P

FAN_LT_PWM

TRUE

FAN_LT_TACH

TRUE

FAN_RT_PWM

CPU_DPSLP_L

TRUE

CPU_PWRGD

TRUE

=PP3V3_S3_LTALS

TRUE

ALS_GAIN

TRUE

LTALS_OUT

TRUE

DEBUG_RESET_L

TRUE

SMC_TRST_L

TRUE

SMC_TDO

TRUE

SMC_MD1

TRUE

LPC_AD<3>

TRUE

INT_SERIRQ

TRUE

PM_SUS_STAT_L

TRUE

SMC_RESET_L

TRUE

SMC_TCK

TRUE

SMC_TDI

TRUE

PM_SB_PWROK

TRUE

SB_RTC_RST_L

TRUE

PM_STPCPU_L

TRUE

PM_STPPCI_L

TRUE

VR_PWRGD_CLKEN

TRUE

VR_PWRGOOD_DELAY

TRUE

NB_CLK100M_PCIE_N

TRUE

NB_CLK100M_DPLLSS_N

TRUE

NC_NB_NC<1..16>

TRUE

TP_NB_NC<1..16>

SMC_BS_ALRT_L

TRUE

=SMBUS_BATT_SCL

TRUE

PM_CLKRUN_L

TRUE

PM_ENET_EN

TRUE

PM_S4_STATE_L

TRUE

P1V5P1V05S0_PGOOD

TRUE

CPU_DPRSTP_L

TRUE

IMVP6_VID<6..0>

TRUE

NB_CLK96M_DOT_P

TRUE

NB_CLKREQ_L

TRUE

NB_CLK100M_PCIE_P

TRUE

CPU_STPCLK_L

TRUE

SMC_LRESET_L

TRUE

GPU_RESET_L

TRUE

PLT_RST_L

TRUE

=SMBUS_BATT_SDA

TRUE

GND_BATT

TRUE

LPC_AD<0>

TRUE

FWH_INIT_L

TRUE

=PP5V_S0_FAN_LT

TRUE

ISENSE_CAL_EN

TRUE

=PPVCORE_S0_NBGFX_REG

TRUE

=PP5V_S0_ISENSECAL

TRUE

=PPVCORE_GPU_REG

TRUE

USB_CAMERA_N

TRUE

=PP5V_S3_CAMERA

TRUE

USB_CAMERA_P

TRUE

USB_WWAN_N

TRUE

=PP5V_S3_WWAN

TRUE

USB_WWAN_P

TRUE

SMC_ONOFF_L

TRUE

PM_SYSRST_L

TRUE

PM_DPRSLPVR

TRUE

PM_RSMRST_L

TRUE

FSB_CPURST_L

TRUE

IMVP_VR_ON

TRUE

PM_SLP_S3_L

TRUE

IMVP_DPRSLPVR

TRUE

PM_SLP_S5_L

TRUE

=PPBUS_G3H_LIO_CONN

TRUE

PPVBATT_G3_RTC

TRUE

NB_SB_SYNC_L

TRUE

FSB_DPWR_L

FSB_CPUSLP_L

TRUE

PCI_RST_L

TRUE

PM_LAN_ENABLE

TRUE

CPU_DPSLP_L

TRUE

=PP3V3_S5_LPCPLUS

TRUE

=PPVCORE_S0_CPU_REG

TRUE

BOOT_LPC_SPI_L

TRUE

LPC_AD<1>

TRUE

LPC_AD<2>

TRUE

PCI_CLK33M_LPCPLUS

TRUE

SMC_TX_L

TRUE

LPC_FRAME_L

TRUE

LINDACARD_GPIO

TRUE

SMC_NMI

TRUE

FAN_RT_TACH

=PP5V_S0_LPCPLUS

TRUE

SMC_TMS

TRUE

SMC_RX_L

TRUE

NB_CLK96M_DOT_N

TRUE

CPU_THERMTRIP_R

TRUE

NB_RESET_L

FSB_CLK_NB_P

TRUE

FSB_CLK_NB_N

TRUE

NB_CLK100M_DPLLSS_P

TRUE

FSB_LOCK_L

TRUE

FSB_REQ_L<4..0>

TRUE

FSB_HITM_L

TRUE

FSB_HIT_L

TRUE

FSB_DSTB_L_P<3..0>

TRUE

FSB_DSTB_L_N<3..0>

TRUE

FSB_DRDY_L

TRUE

FSB_DINV_L<3..0>

TRUE

FSB_DBSY_L

TRUE

FSB_D_L<63..0>

TRUE

FSB_BNR_L

TRUE

FSB_BREQ0_L

TRUE

FSB_ADSTB_L<1..0>

TRUE

FSB_ADS_L

TRUE

FSB_A_L<31..3>

TRUE

LVDS_L_DATA_N<2>

TRUE

LVDS_L_DATA_N<1>

TRUE

LVDS_L_DATA_P<2>

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

79

65

79

47

58

79

45

79

47

23

78

47

46

47

28

30

28

84

56

47

65

23

79

84

79

77

47

74

82

78

45

58

14

40

46

79

23

58

47

84

46

47

46

84

79

86

87

10

13

78

53

78

47

46

47

45

46

25

28

29

28

16

30

46

56

45

65

45

16

58

29

30

23

45

66

28

56

45

52

49

59

49

44

46

28

25

45

13

58

36

79

45

56

25

14

28

45

10

47

49

47

45

47

45

47

46

45

28

30

14

77

51

52

7

10

8

45

53

28

45

23

25

45

9

23

25

9

16

22

16

45

48

25

36

25

65

10

12

84

16

10

28

24

48

56

23

47

8

45

8

24

8

24

44

8

44

45

25

16

25

10

45

25

58

25

8

28

16

10

24

25

7

8

24

23

30

43

23

25

45

52

8

45

43

84

23

16

14

22

10

73

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Chipset "VCore" Rails

"FW" (FireWire) Rails

"GPU" Rails

3.3V-2.5V Rails 1.8V-0.9V Rails

MAX I = 0.36A

MAX I = ?.??A

"ENET" Rails

Yukon EC will not be supported

5V Rails

"G3Hot" (Always-Present) Rails

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

8

88

A.0.0

051-7225

Power Aliases

=PP3V3_S3_TOPCASE

=PP3V3_S3_LTALS

=PP3V3_S0_NB_VCCHV

=PPVCORE_GPU_REG

MIN_NECK_WIDTH=0.2 mm

PPVCORE_GPU

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm VOLTAGE=1.2V

=PPVCORE_GPU

=PPBUS_G3H_LIO_CONN

=PP5V_S0_ODD

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

VOLTAGE=5V

PP5V_S3

=PP5V_S0_ISENSECAL

=PPVCORE_S0_NBGFX_VSEN

PPVCORE_S0_CPU

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

VOLTAGE=1.25V

MIN_NECK_WIDTH=0.3 mm

=PP3V3_S5_SMC

=PP5V_S5_P1V05S0

=PP5V_S0_P5VS0FET

=PP5V_S0_KBDLED

=PP3V42_G3H_LIDSWITCH

=PPVIN_G3H_P3V42G3H

=PP1V25_S0M_NB_PLL

MIN_LINE_WIDTH=0.4 mm

PP3V3_GPU

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

=PP3V3_GPU_HDCP

=PP3V3_GPU_VCORELOGIC

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

VOLTAGE=1.8V

PP1V8_GPU

=PP1V8_GPU_FBVDDQ

=PP1V8_GPU_FB_VDD

=PP5V_S5_P1V5S0

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE

PP3V3_GPU_TMDS

=PPVCORE_S0_NB_FOLLOW =PPVCORE_S0_SB

=PPVCORE_S0_NBCOREISNS

=PP1V25R1V05_S0_FSB_NB =PP1V25R1V05_S0_NB_VTT

=PP1V05_S0_SB_CPU_IO =PP1V05_S0_SMC_LS

=PP1V05_S0_NB_FOLLOW =PP1V05_S0_NB_PCIE

PP1V05_S0

VOLTAGE=1.05V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

=PP3V42_G3H_SMCUSBMUX

=PP3V42_G3H_LIO

=PP3V3_GPU_PWRCTL

=PP3V3_GPU_SMBUS_SMC_0_S0

=PP2V5_GPU_LTC2900

=PP3V3_GPU_VIDEOMUX

=PP3V3_GPU_TMDS

=PP3V3_GPU_VGASYNC

=PP3V3_GPU_DVI =PP3V3_GPU_LVDS_DDC

=PP1V25_S0_NB_VCCDMI

=PP1V25_S0_SB_DMI

=PP3V3_GPU_IFPCD_IOVDD

=PP1V25_GPU_FET

=PP3V3_GPU_TMDSBIAS

=PP1V25_ENET_ISNS

PP1V25_S0

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.25V MAKE_BASE=TRUE

=PP1V2_GPU_PLLVDD

=PP1V8_GPU_IFPX

=PP1V8_GPU_FBIO

=PP1V8_GPU_FB_VDDQ

=PP1V8_GPU_FET

=PP1V2_GPU_PEX_IOVDD =PP1V2_GPU_PEX_PLLXVDD

=PP3V3_S5_SB_VCCSUS3_3

=PP3V3_S5_SB_CLINK1

=PP3V3_GPU_TMDS_FET

=PP1V2_GPU_H_PLLVDD =PP1V2_GPU_VID_PLLVDD

=PP3V3_S5_REG

=PP5V_S3_FET

=PP5V_S3_WWAN

=PP3V3_S5_SB_3V3_VCCSUSHDA

=PP3V3_GPU_VDD33

=PP3V3_GPU_FET

=PPDCIN_G3H_LIO_CONN

=PP3V3_S5_SB_PM =PP3V3_S5_SB_USB =PP3V3_S5_SB

=PP3V3_S5_SB_VCCSUS3_3_USB

=PP3V3_S5_SMBUS_SB_ME

PPVP_FW

VOLTAGE=33V

MIN_NECK_WIDTH=0.3 mm

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

VOLTAGE=1.95V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

PP1V95_FW

MIN_LINE_WIDTH=0.4 mm

PP3V3_FW

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm

=PPBUS_S5_FW_FET

=PPVP_FW_SUMNODE =PPVP_FW_CPS =PPVP_FW_P3V3FW

=PPVP_FW_PORT0

PPVP_FW_PORTA_UF

MAKE_BASE=TRUE

=PPVP_FW_PORT1

PPVP_FW_PORTB_UF

MAKE_BASE=TRUE

=PP3V3_FW_REG

=PP3V3_FW_PHY =PP3V3_FW_LATEVG_ACTIVE

=PPVIN_FW_P1V95FW

=PP3V3_FW_LATEVG

=PP1V95_FW_PHY

=PP1V95_FW_LDO

=PP1V8_FW_PHYOSC

=PP3V3_GPU_MIO =PP3V3_GPU_DAC

=PPBU_S0_P3V3FW

PPBUS_FW_FWPWRSW_F

MAKE_BASE=TRUE

=PP5V_S5_P1V25ENET

=PP5V_S3_RTUSB

=PP5V_S5_P1V25GPUFET

=PP5V_S5_REG

=PP5V_S3_SYSLED =PP5V_S3_CAMERA

=PP5V_S5_P1V8DDRREG

=PP5V_S3_IR

=PP3V3_S5_S5PWRGD

=PP3V3_S5_SB_GPIO

=PP1V2_GPU_PEX_IOVDDQ

=PP1V8_S3_REG

=PP1V8_S3M_MEM_A

=PP1V8_S3_FW

=PP1V8_S3M_MEM_B =PP1V8_S3_ISNS_R

=PP5V_S5_PWRCTL

PP0V9_S3_MEM_VREF

MIN_LINE_WIDTH=0.4 mm VOLTAGE=0.9V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=0.9V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm

PP0V9_S0

=PP1V5_S0_CPU

=PP1V5_S0_REG

=PP1V25_S0_FET

=PP1V25_S0M_NB_VCCA

=PP1V25_S0M_NB_VCC

=PP1V25_S0_NB_PLL =PP1V25_S0_NB_VCC

=PP1V05_S0_REG

=PP1V05_S0M_NB_VCCAXM

=PPVCORE_S0_NB_R

=PP0V9_S3M_MEM_NBVREFA

=PP0V9_S3_VTTR_BUF

=PP0V9_S3M_MEM_NBVREFB =PP0V9_S3M_MEM_DIMMVREFA =PP0V9_S3M_MEM_DIMMVREFB

=PP0V9_S0_VTT_LDO

=PP1V8_S0_FET

=PP1V8_S0_NB_LVDS

PP3V3_ENET

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

MAKE_BASE=TRUE

=PP3V3_ENET_PHY

=PP3V3_ENET_FET

=PP3V3_ENET_AVDDLDO

VOLTAGE=1.9V

PP1V9_ENET

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

=PP1V8R2V5_ENET_PHY

VOLTAGE=1.25V

MIN_LINE_WIDTH=0.6 mm

PP1V25_ENET_ISNS

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

=PP1V25_S0_P1V25S0FET =PP1V25_GPU_P1V25GPUFET

PPVCORE_S0_NB_GFX

MIN_LINE_WIDTH=0.5 mm

MAKE_BASE=TRUE

VOLTAGE=1.25V

MIN_NECK_WIDTH=0.25 mm

=PPVCORE_S0_CPU

=PPVCORE_S0_CPU_REG

=PPVCORE_S0_NBGFX_REG

=PP1V2_GPU_FBPLLAVDD =PP1V2_GPU_VCOREPWRCTL

MIN_LINE_WIDTH=0.6 mm VOLTAGE=1.25V

MAKE_BASE=TRUE

PP1V25_GPU

MIN_NECK_WIDTH=0.2 mm

=PP5V_S5_P1V8S0FET

=PP5V_S5_P1V25S0FETXW

=PP5V_S5_GPUVCORE

=PP5V_S5_P1V8GPUFET

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.9V MAKE_BASE=TRUE

PPVCORE_S0_NB_R

=PPVCORE_S0_NB

=PP1V05_S0_CPU

=PP0V9_S0M_MEM_TERM

=PP1V25_ENET_ISNS_R

=PP1V2_ENET_PHY

MIN_LINE_WIDTH=0.6 mm VOLTAGE=1.25V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

PP1V25_ENET

=PPVOUT_ENET_AVDDLDO

=YUKON_EC_PP2V5_ENET

=PP3V3_S5_LPCPLUS

=PP5V_S5_SB

=PP1V25_ENET_REG

=PP5V_S3_TOPCASE

=PP5V_S3_P5VS3FET

=PP1V5_S0_SB_VCC1_5_A_ATX

=PP1V5_S0_SB_VCCUSBPLL

=PP1V5_S0_LIO

=PP1V5_S0_SB_VCC1_5_A_USB_CORE

=PP3V42_G3H_SB_RTC

=PP3V42_G3H_SMBUS_SMC_BSA

=PP3V3_S3_FW =PP3V3_S3_PCI =PP3V3_S3_SMBUS_SMC_A_S3 =PP3V3_S3_RTALS =PP3V3_S3_SMS

=PP3V3_S3_P1V25ISNS

=PP3V3_S3_SMBUS_SMC_MGMT

=PP3V3_S3_P1V8ISNS

=PP3V3_S0_NB_FOLLOW

=PP3V3_S0_FET

=PP3V3_S0_SB_GPIO =PP3V3_S0_SB_PCI =PP3V3_S0_SB_VCC3_3_IDE =PP3V3_S0_SB_VCC3_3_PCI =PP3V3R1V5_S0_SB_VCCHDA =PP3V3_S0_SB_VCC3_3_DMI =PP3V3_S0_SB_VCC3_3_VCCPCORE =PP3V3_S0_SB_VCCGLAN3_3 =PP3V3_S0_SB_VCC3_3_SATA =PP3V3_S0_SB =PP3V3_S0_SB_PM =PP3V3_S0_RSTBUF =PP3V3_S0_CK505

=PP3V3_S0_SMC

=PP3V3_S0_IDE

=PP3V3_S0_LPCPLUS =PP3V3_S0_SMBUS_SB =PP3V3_S0_SMBUS_SMC_B_S0 =PP3V3_S0_CPUCOREISNS =PP3V3_S0_NBGFXCOREISNS =PP3V3_S0_CPUTHMSNS

=PP3V3_GPU_P3V3GPUFET =PP3V3_S5_PWRCTL

VOLTAGE=3.3V

PP3V3_S5

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

=PPVCORE_S0_NB_GFX

=PP5V_S0_SB

=PP5V_S0_LPCPLUS =PP5V_S0_FAN_LT =PP5V_S0_FAN_RT =PP5V_S0_CPU_IMVP

=PP5V_S0_SB_HPD =PP5V_S0_HDD

=PPBUS_S5_FWPWRSW

=PP5V_S0_DVI_DDC

=PP5V_S0_GFXIMVP6

VOLTAGE=5V

PP5V_S0

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

=PP5V_S0_FET

=PP5V_S0_ODDPWREN =PP5V_S0_PCIREQFIX

=PP3V42_G3H_REG

MAKE_BASE=TRUE

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

PP1V8_S0

=PPVIN_S0_NB_DPLL

=PP1V8_GPU_P1V8GPUFET

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 mm MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm

PP1V8_S3

=PP3V3_S0_P3V3S0FET

=PP3V3_S0_LCD

=PP3V3_S3_P3V3S3FET

=PP3V3_S5_P1V5P1V05PG

=PP3V3_S5_ROM

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V

PP1V8_S3_ISNS

=PP1V8_S3M_NB_VCC

=PP1V8_S3_ISNS

=PP1V8_S3M_MEM_NB =PP1V8_S0_P1V8S0FET

=PP1V5_S0_NB_TVDAC =PP1V5_S0_SB =PP1V5_S0_SB_VCC1_5_A_ARX

=PP1V5_S0_SB_VCC1_5_A

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

PP1V5_S0

MIN_LINE_WIDTH=0.5 mm VOLTAGE=1.5V

=PP3V3_S3_FET

=PP3V3_S3_P3V3ENETFET

=PP3V3_S3_REMTHMSNS

=PP3V3_S0_NB_VCCA_PEG_BG

MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

PP3V3_S3

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

=PP3V3_S0_GPUTHMSNS =PP3V3_S0_FAN_LT =PP3V3_S0_FAN_RT =PP3V3_S0_IMVP =PP3V3_S0_GFXIMVP6 =PP3V3_S0_NBCOREISNS =PP3V3_S0_ALLSYSPG =PP3V3_S0_DDC_LCD =PP3V3_S0_LVDS_MUX =PP3V3R5V_GPU_GPUISENS =PP3V3_S0_XDP =PP3V3_S0M_CK505 =PP3V3_S0_GPUCLKGATE =PPSPD_S0M_MEM_A =PPSPD_S0M_MEM_B =PP3V3_S0MWOL_SB_CLINK0 =PP3V3_S0MWOL_SB_VCCCL3_3 =PP3V3_S0MWOL_SB_VCCLAN3_3 =PP3V3_S0_PWRCTL

PP3V3_S0

MIN_LINE_WIDTH=0.6 mm VOLTAGE=3.3V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

PP5V_S5

VOLTAGE=5V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

=PPVIN_S5_SMCVREF =PP3V42_G3H_PWRCTL

MIN_NECK_WIDTH=0.2 mm MAKE_BASE=TRUE

VOLTAGE=3.42V

PP3V42_G3H

MIN_LINE_WIDTH=0.3 mm

MIN_LINE_WIDTH=0.4 mm

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm VOLTAGE=18.5V

PPDCIN_G3H

=PPBUS_S5_P1V8GPUFET =PPBUS_S5_P1V25S0FET

MIN_NECK_WIDTH=0.2 mm

PPBUS_G3H

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm VOLTAGE=12.6V

=PPVIN_S5_CPU_IMVP_VIN

=PPVIN_S5_P5VS5

=PPVIN_S5_CPU_IMVP =PPVIN_S5_P5VP3V3

=PPVIN_S5_P3V3S5 =PPVIN_ENET_P1V25ENET

=PPVIN_S0_GFXIMVP6

=PPVIN_S3_P1V8S3 =PPVIN_S0_P1V5S0

=PPVIN_S0_P1V05S0 =PPVIN_GPU_GPUVCORE

13

21

74

27

49

58

22

12

21

78

19

49

56

49

46

70

27

30

21

26

21

27

70

27

44

27

41

72

44

87

12

21

12

49

59

21

11

47

27

25

27

30

22

47

52

18

27

21

30

27

87

78

7

16

7

67

7

42

7

59

45

61

57

53

78

65

21

77

72

74

77

67

69

63

21

26

50

14

19

23

46

21

43

34

65

48

77

72

76

77

19

26

73

57

76

50

65

71

73

68

69

57

66

26

25

72

71

60

57

7

26

71

57

34

28

24

25

26

48

40

39

64

41 40

64

39

40

64

41

39

64

39

71

73

64 40

61

43

57

60

46

7

62

78

46

25

66

62

31

38

32

50

65

11

63

57

21

61

18

50

16

62

16

31

32

62

57

22

35

36

35

57

11

7

68

74

77

57

9

74

57

18

10

33

50

35

36

35

7

27

61

78

57

26

34

26

28

48

38

48

53

54

50

48

50

21

57

23

24

26

27

28

29

46

42

47

48

50

51

57

65

87

18

27

7

52

58

76

78

40

76

59

65 57

42

65

22

57

75

57

65

55

21

50

16

57

22

27

26

87

57

36

51

19

51

52

58

59

50

65

75

77

74

13

29

30

31

32

25

26

65

46

65

57

49

58

60

58

60

61

59

62

63

61

74

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

TM Hole

(Can’t be PTH)

Tooling

Holes

(Can’t be PTH)

Notches

Edge

Chassis GNDs

Frame Holes

Top CPU TM Notch

Left CPU

Add 2 buried vias to GND

RAM Door (Torx) Holes

TM Hole

Top GPU Right

Bottom Left GPU

TM Hole

Digital Ground

TM Hole

Right CPU

Thermal Module Holes

Board

HOLE-VIA-P5RP25

402

NONE

SHORT

NONE

OMIT

SHLD-SM-LF

OG-503040

5P75R2P7

3P7R3P2

3P2R2P7

HOLE-VIA-P5RP25

SM

Signal Aliases

SYNC_MASTER=(T9_MLB)

9

88

A.0.0

051-7225

SYNC_DATE=08/23/2006

GND_CHASSIS_DVI_BOT

MAKE_BASE=TRUE

VOLTAGE=0V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

TP_USB_EXTCN

MAKE_BASE=TRUE

PEG_CLK100M_N

PEG_CLK100M_P

MAKE_BASE=TRUE

PEG_CLK100M_GPU_N

PEG_CLK100M_GPU_P

MAKE_BASE=TRUE

USB_EXTC_P

SMC_SMS_INT

MAKE_BASE=TRUE

=SMC_SMS_INT

MAKE_BASE=TRUE

PM_ALL_NBGFX_PGOOD

GFXIMVP6_PGOOD

VR_PWRGOOD_DELAY

MAKE_BASE=TRUE

=NB_CLINK_MPWROK

=GFX_VR_EN GFX_VID<4..0>

MAKE_BASE=TRUE

GFX_VR_EN

MAKE_BASE=TRUE

GFXIMVP6_VID<4..0>

MEM_A_A<15>

MAKE_BASE=TRUE

TP_MEM_A_A<15>

MEM_B_A<15>

MAKE_BASE=TRUE

TP_MEM_B_A<15>

TP_USB_EXTCP

MAKE_BASE=TRUE

GND_CHASSIS_DVI_TOP

MIN_LINE_WIDTH=0.5 mm

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V

GND_CHASSIS_ENET

MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V

MIN_LINE_WIDTH=0.5 mm

MAKE_BASE=TRUE

VOLTAGE=0V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

GND_CHASSIS_RTUSB

=GND_CHASSIS_DVI_TOP

=GND_CHASSIS_DVI_BOT

=GND_CHASSIS_FW_PORT1 =GND_CHASSIS_FW_PORT0U

=GND_CHASSIS_ENET

=GND_CHASSIS_FW_PORT0L =GND_CHASSIS_RTUSB

GND_CHASSIS_RAMDOOR_HOLE_1

GND_CHASSIS_LVDS_HOLE

GND_CHASSIS_RIGHT_FAN_HOLE

GND_CHASSIS_RIGHT_FAN_NOTCH

GND_CHASSIS_DIMM_NOTCH

GND_CHASSIS_LIOFLEX_HOLE

GND_CHASSIS_LINDACARD_HOLE

GND_CHASSIS_BATTCONN_HOLE

GND_CHASSIS_DVI_HOLE

GND_CHASSIS_RAMDOOR_HOLE_0

PM_SB_PWROK

MAKE_BASE=TRUE

=SB_CLINK_MPWROK

=PP5V_S5_P1V25S0FET

MIN_LINE_WIDTH=0.1 mm

MAKE_BASE=TRUE

PP5V_S5_P1V25S0FET

MIN_NECK_WIDTH=0.1 mm VOLTAGE=5V

NO_TEST=TRUE

USB_EXTC_N

=PP5V_S5_P1V25S0FETXW

GND_CHASSIS_LEFTCLUTCH

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V MAKE_BASE=TRUE

=GND_CHASSIS_LEFTCLUTCH =GND_CHASSIS_J5590

GND

VOLTAGE=0V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

ZT0945

1

ZT0950

1

R0910

1

2

SH0925

1 2 3

ZT0970

1

ZT0975

1

ZT0980

1

ZT0985

1

ZT0930

1

ZT0935

1

ZT0940

1

ZT0920

1

ZT0965

1

ZT0955

1

ZT0990

1

ZT0960

1

XW0900

1 2

58 28

28

66

82

16

25

82

84

30

24

54 45

77 59

7

16

59

31

32

76

41

37

41

43

7

25

57

24

8

44

51

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

IN IN IN

IN

OUT

IN

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

OUT OUT

OUT

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI

BI BI BI

BI

BI BI

BI BI BI BI BI

BI

OUT

IN

IN IN IN IN IN

IN IN

OUT

IN IN

IN

IN IN

IN

OUT

BI BI BI BI

LOCK*

INIT*

A20M*

A6*

A3* A4*

A14*

A16*

REQ0* REQ1* REQ2* REQ3* REQ4*

BCLK1

BCLK0

THERMTRIP*

THERMDA

PROCHOT*

DBR*

TRST*

TMS

TDO

TDI

TCK

PREQ*

PRDY*

BPM3*

BPM2*

BPM1*

BPM0*

HITM*

HIT*

TRDY*

RS2*

RS1*

RS0*

RESET*

IERR*

BR0*

DBSY*

DRDY*

DEFER*

BNR*

RSVD9

RSVD8

RSVD7

RSVD6

RSVD5

RSVD4

RSVD3

RSVD2

RSVD1

RSVD0

SMI*

LINT1

LINT0

STPCLK*

FERR*

ADSTB1*

A35*

A34*

A33*

A32*

A31*

A30*

A29*

A28*

A19*

A18*

A17*

ADSTB0*

A13*

A12*

BPRI*

A20* A21* A22* A23* A24*

A26* A27*

A9*

A8*

A7*

A11*

A25*

THERMDC

IGNNE*

ADS*

A10*

A15*

A5*

NC

1 OF 4

CONTROL

THERMAL

XDP/ITP SIGNALS

H CLK

RESERVED

ADDR GROUP0ADDR GROUP1

ICH

DINV1*

D31*

D30*

D25*

D11* D12* D13* D14*

DSTBP0* DINV0*

D9*

D8*

D7*

D6*

D19*

D18*

DATBP1*

D0*

D32* D1* D2*

D5*

D16*

D20* D21* D22* D23* D24*

D26* D27* D28* D29*

DSTBN1*

GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6

BSEL0 BSEL1 BSEL2

D33*

D34*

D35*

D36*

D37*

D38*

D39*

D40*

D41*

D42*

D43*

D44*

D45*

D46*

D47*

DSTBN2* DSTBP2*

DINV2*

D48*

D49*

D50*

D51*

D52*

D53*

D54*

D55*

D56*

D57*

D58*

D59*

D60*

D61*

D62*

D63*

DSTBN3* DSTBP3*

DINV3*

COMP0 COMP1 COMP2 COMP3

DPRSTP*

DPSLP*

DPWR*

PWRGOOD

SLP*

PSI*

D17*

D4*

D3*

DSTBN0*

D15*

D10*

2 OF 4

DATA GRP 3 DATA GRP 2

MISC

DATA GRP 0DATA GRP 1

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NC

LAYOUT NOTE:

MAKE TRACE LENGTH SHORTER THAN 0.5".

COMP0,2 CONNECT WITH ZO=27.4OHM,

MAKE TRACE LENGTH SHORTER THAN 0.5".

COMP1,3 CONNECT WITH ZO=55OHM,

PM_THRMTRIP# SHOULD CONNECT TO ICH AND GMCH WITHOUT T (NO STUB)

0.1" AWAY

PLACE TESTPOINT ON FSB_IERR_L WITH A GND

0.5" MAX LENGTH FOR CPU_GTLREF

REFERENCED TO GND

PLACE C1000 CLOSE TO CPU_TEST4 PIN. MAKE SURE CPU_TEST4 IS

1% 1/16W

54.9

MF-LF 402

68

5% 1/16W

402

MF-LF

1/16W

1%

MF-LF

1K

402

1%

MF-LF

2.0K

1/16W

402

1%

MF-LF

1/16W

54.9

402

27.4

1/16W MF-LF

1%

402

1%

MF-LF

1/16W

54.9

402

1%

MF-LF

1/16W

27.4

402

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

16 23 58 79

7

23 79

7

14 79

7

14 79

28

7

13 23 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

30 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

13 79

10 13 79

13 28

46 58 79

51

16 23 46 79

23 47 79

7

13 14 79

14 79

10 13 79

51 87

30 84

23 79

7

23 79

0

1/16W MF-LF

5%

NOSTUFF

402

1/16W

5% MF-LF

1K

NOSTUFF

402

1/16W

1%

MF-LF

54.9

402

1%

MF-LF

1/16W

54.9

402

54.9

1/16W MF-LF

1%

402

54.9

1/16W MF-LF

1%

402

14 79

649

1/16W MF-LF

1%

402

1/16W

5%

1K

NOSTUFF

MF-LF

402

X5R

NOSTUFF

0.1uF

10% 16V

402

OMIT

MEROM

FCBGA

OMIT

MEROM

FCBGA

1%

MF-LF

1/16W

54.9

PLACEMENT_NOTE=Place R1024 near ITP connector (if present)

402

SYNC_DATE=03/16/2007

SYNC_MASTER=T9_NOME

88

051-7225

A.0.0

10

CPU FSB

XDP_BPM_L<2>

XDP_BPM_L<5> XDP_TCK

CPU_THERMD_N

=PP1V05_S0_CPU

XDP_TRST_L

XDP_TDI

XDP_TMS

XDP_TDO

XDP_TCK

FSB_A_L<5>

FSB_A_L<15>

FSB_A_L<10>

FSB_ADS_L

CPU_IGNNE_L

FSB_A_L<25>

FSB_A_L<11>

FSB_A_L<7> FSB_A_L<8> FSB_A_L<9>

FSB_A_L<27>

FSB_A_L<26>

FSB_A_L<24>

FSB_A_L<23>

FSB_A_L<22>

FSB_A_L<21>

FSB_A_L<20>

FSB_BPRI_L

FSB_A_L<12> FSB_A_L<13>

FSB_ADSTB_L<0>

FSB_A_L<17> FSB_A_L<18> FSB_A_L<19>

FSB_A_L<28> FSB_A_L<29> FSB_A_L<30> FSB_A_L<31> FSB_A_L<32> FSB_A_L<33> FSB_A_L<34> FSB_A_L<35> FSB_ADSTB_L<1>

CPU_FERR_L

CPU_STPCLK_L CPU_INTR CPU_NMI CPU_SMI_L

TP_CPU_RSVD0 TP_CPU_RSVD1 TP_CPU_RSVD2 TP_CPU_RSVD3 TP_CPU_RSVD4 TP_CPU_RSVD5 TP_CPU_RSVD6 TP_CPU_RSVD7 TP_CPU_RSVD8 TP_CPU_RSVD9

FSB_BNR_L

FSB_DEFER_L FSB_DRDY_L FSB_DBSY_L

FSB_BREQ0_L

CPU_IERR_L

FSB_CPURST_L FSB_RS_L<0> FSB_RS_L<1> FSB_RS_L<2> FSB_TRDY_L

FSB_HIT_L FSB_HITM_L

XDP_BPM_L<0> XDP_BPM_L<1>

XDP_BPM_L<3> XDP_BPM_L<4>

XDP_TDI XDP_TDO XDP_TMS XDP_TRST_L XDP_DBRESET_L

CPU_PROCHOT_L CPU_THERMD_P

PM_THRMTRIP_L

FSB_CLK_CPU_P FSB_CLK_CPU_N

FSB_REQ_L<4>

FSB_REQ_L<3>

FSB_REQ_L<2>

FSB_REQ_L<1>

FSB_REQ_L<0>

FSB_A_L<16>

FSB_A_L<14>

FSB_A_L<4>

FSB_A_L<3>

FSB_A_L<6>

CPU_A20M_L

CPU_INIT_L

FSB_LOCK_L

FSB_D_L<10>

FSB_D_L<15> FSB_DSTB_L_N<0>

FSB_D_L<3> FSB_D_L<4>

FSB_D_L<17>

CPU_PSI_L

FSB_CPUSLP_L

CPU_PWRGD

FSB_DPWR_L

CPU_DPSLP_L

CPU_DPRSTP_L

CPU_COMP<3>

CPU_COMP<2>

CPU_COMP<1>

CPU_COMP<0>

FSB_DINV_L<3>

FSB_DSTB_L_P<3>

FSB_DSTB_L_N<3>

FSB_D_L<63>

FSB_D_L<62>

FSB_D_L<61>

FSB_D_L<60>

FSB_D_L<59>

FSB_D_L<58>

FSB_D_L<57>

FSB_D_L<56>

FSB_D_L<55>

FSB_D_L<54>

FSB_D_L<53>

FSB_D_L<52>

FSB_D_L<51>

FSB_D_L<50>

FSB_D_L<49>

FSB_D_L<48>

FSB_DINV_L<2>

FSB_DSTB_L_P<2>

FSB_DSTB_L_N<2>

FSB_D_L<47>

FSB_D_L<46>

FSB_D_L<45>

FSB_D_L<44>

FSB_D_L<43>

FSB_D_L<42>

FSB_D_L<41>

FSB_D_L<40>

FSB_D_L<39>

FSB_D_L<38>

FSB_D_L<37>

FSB_D_L<36>

FSB_D_L<35>

FSB_D_L<34>

FSB_D_L<33>

CPU_BSEL<2>

CPU_BSEL<1>

CPU_BSEL<0>

TP_CPU_TEST6

CPU_TEST4

TP_CPU_TEST3

CPU_TEST2

CPU_TEST1

CPU_GTLREF

FSB_DSTB_L_N<1>

FSB_D_L<29>

FSB_D_L<28>

FSB_D_L<27>

FSB_D_L<26>

FSB_D_L<24>

FSB_D_L<23>

FSB_D_L<22>

FSB_D_L<21>

FSB_D_L<20>

FSB_D_L<16>

FSB_D_L<5>

FSB_D_L<2>

FSB_D_L<1>

FSB_D_L<32>

FSB_D_L<0>

FSB_DSTB_L_P<1>

FSB_D_L<18> FSB_D_L<19>

FSB_D_L<6> FSB_D_L<7> FSB_D_L<8> FSB_D_L<9>

FSB_DINV_L<0>

FSB_DSTB_L_P<0>

FSB_D_L<14>

FSB_D_L<13>

FSB_D_L<12>

FSB_D_L<11>

FSB_D_L<25>

FSB_D_L<30> FSB_D_L<31>

FSB_DINV_L<1>

TP_CPU_TEST5

R1002

1

2

R1004

1

2

R1005

1

2

R1006

1

2

R1019

R1018

R1017

R1016

R1030

R1007

1

2

R1003

1

2

R1020

R1021

R1022

R1023

R1012

1

2

C1000

1

2

U1000

N3 P5 P2 L2 P4 P1 R1

Y2 U5 R3 W6

A6

U4 Y5 U1 R4 T5 T3 W2 W5 Y4

J4

U2 V4

W3 AA4 AB2 AA3

L5

L4

K5

M3

N2

J1

H1

M1

V1

A22 A21

E2

AD4 AD3 AD1 AC4

G5

F1

C20

E1

H5 F21

A5

G6 E4

D20

C4

B3

C6

B4

H4

B1

AC2 AC1

D21

K3

H2

K2

J3

L1

C1 F3 F4 G3

M4

N5

T2

V3

B2

C3

D2 D22

D3

F6

A3

D5

AC5 AA6 AB3

A24 B25

C7

AB5

G2

AB6

U1000

B22 B23 C21

R26 U26 AA1 Y1

E22 F24

J24 J23 H22 F26 K22 H23

N22 K25 P26 R23

E26

L23 M24 L22 M23 P25 P23 P22 T24 R24 L25

G22

T25 N25

Y22 AB24 V24 V26 V23 T22 U25 U23

F23

Y25 W22 Y23 W24 W25 AA23 AA24 AB25

AE24 AD24

G25

AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21

E25

AC22 AD23 AF22 AC23

E23 K24 G24

M26

H25

N24

U22

AC20

E5 B5 D24

J26

L26

Y26

AE25

H26

AA26

AF24

AD26

AE6

D6 D7

C23 D25 C24

AF26

AF1 A26

R1024

13

12

11

79

10

13

8

10

79

79 79

OUT OUT OUT OUT OUT OUT OUT

OUT

VCC

VSSSENSE

VCCSENSE

VID6

VID5

VID4

VID3

VID2

VID1

VID0

VCCA

VCCP

VCC

3 OF 4

VSS VSS

4 OF 4

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

TBD A (Deep Sleep LFM)

TBD A (Sleep LFM)

TBD A (Auto-Halt/Stop-Grant LFM)

Current numbers from Merom for Santa Rosa EMTS, doc #22221.

TBD A (LFM)

TBD A (HFM)

TBD A (Auto-Halt/Stop-Grant HFM)

TBD A (Sleep HFM)

TBD A (Deep Sleep HFM)

TBD A (Deeper Sleep) TBD A (Enhanced Deeper Sleep)TBD A (Enhanced Deeper Sleep)

TBD A (Deeper Sleep)

TBD A (Deep Sleep SuperLFM)

TBD A (Deep Sleep HFM)

TBD A (Sleep SuperLFM)

TBD A (Sleep HFM)

TBD A (Auto-Halt/Stop-Grant SuperLFM)

TBD A (Auto-Halt/Stop-Grant HFM)

TBD A (SuperLFM)

18.7 A (LFM)

21.0 A (HFM)

23.0 A (Design Target) 17.0 A (Design Target)

Ultra Low Voltage:Low Voltage:

(CPU INTERNAL PLL POWER 1.5V)

(CPU IO POWER 1.05V)

130 mA

(CPU CORE POWER)

Standard Voltage:

44.0 A (Design Target)

41.0 A (HFM)

16.8 A (Sleep SuperLFM)

16.0 A (Deep Sleep SuperLFM)

4500 mA (before VCC stable) 2500 mA (after VCC stable)

9.4 A (Enhanced Deeper Sleep)

25.5 A (SuperLFM)

30.4 A (LFM)

27.4 A (Auto-Halt/Stop-Grant HFM)

17.0 A (Auto-Halt/Stop-Grant SuperLFM)

27.4 A (Sleep HFM)

25.0 A (Deep Sleep HFM)

11.5 A (Deeper Sleep)

12 79

1/16W

1%

100

402

MF-LF

PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.

12 79

58 79

OMIT

MEROM

FCBGA

OMIT

MEROM

FCBGA

100

1% 1/16W

PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.

402

MF-LF

8811

A.0.0

051-7225

CPU Power & Ground

SYNC_MASTER=T9_NOME

SYNC_DATE=03/16/2007

CPU_VID<2> CPU_VID<3>

CPU_VID<5>

=PPVCORE_S0_CPU

CPU_VCCSENSE_N

CPU_VCCSENSE_P

CPU_VID<0> CPU_VID<1>

=PPVCORE_S0_CPU

CPU_VID<6>

CPU_VID<4>

=PP1V5_S0_CPU

=PP1V05_S0_CPU

R1101

1

2

U1000

A7 A9

B9 B10 B12 B14 B15 B17 B18 B20

C9 C10

A10

C12 C13 C15 C17 C18

D9 D10 D12 D14 D15

A12

D17 D18

E7

E9 E10 E12 E13 E15 E17 E18

A13

E20

F7

F9 F10 F12 F14 F15 F17 F18 F20

A15

AA7 AA9

AA10 AA12 AA13 AA15 AA17 AA18 AA20

AB9

A17

AC10 AB10 AB12 AB14 AB15 AB17 AB18

AB20 AB7 AC7

A18

AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12

A20

AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17

B7

AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20

B26 C26

G21 V6

R21 R6 T21 T6 V21 W21

J6 K6 M6 J21 K21 M21 N21 N6

AF7

AD6 AF5 AE5 AF4 AE3 AF3 AE2

AE7

U1000

A4 A8

B11

W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5

B13

AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8

B16

AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11

B19

AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13

B21

AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16

B24

AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19

C5

AF21 A25 AF25

C8 C11 C14

A11

C16 C19

C2 C22 C25

D1

D4

D8 D11 D13

A14

D16 D19 D23 D26

E3

E6

E8 E11 E14 E16

A16

E19 E21 E24

F5

F8 F11 F13 F16 F19

F2

A19

F22 F25

G4

G1 G23 G26

H3

H6 H21 H24

A23

J2

J5 J22 J25

K1

K4 K23 K26

L3

L6

AF2

L21 L24

M2

M5 M22 M25

N1

N4 N23 N26

B6

P3

P6 P21 P24 R2 R5 R22 R25 T1 T4

B8

T23 T26 U3 U6 U21 U24 V2 V5 V22 V25

R1100

1

2

49

13

12

11

12

10

8

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

WF: Consider sharing bulk cap with NB Vtt?

VCCA (CPU AVdd) DECOUPLING

1x 10uF, 1x 0.01uF

VCCP (CPU I/O) DECOUPLING

1x 470uF, 6x 0.1uF 0402

CPU VCORE HF AND BULK DECOUPLING

CPU VCORE VID CONNECTIONS

4x 330uF, 20x 22uF 0805

22UF

20%

6.3V 805

CERM-X5R

470UF

20%

D2T

TANT

2.5V

CRITICAL

22UF

20%

6.3V 805

CERM-X5R

22UF

CERM-X5R 805

6.3V

20%

22UF

CERM-X5R 805

6.3V

20%

22UF

20%

6.3V 805

CERM-X5R

22UF

20%

6.3V 805

CERM-X5R

22UF

20%

6.3V 805

CERM-X5R

6.3V

22UF

20% 805

CERM-X5R

22UF

20%

6.3V 805

CERM-X5R

22UF

CERM-X5R 805

6.3V

20%

22UF

CERM-X5R

20%

805

6.3V

22UF

CERM-X5R 805

6.3V

20%

22UF

CERM-X5R

20%

6.3V 805

20% 805

6.3V

22UF

CERM-X5R

22UF

CERM-X5R

20%

6.3V 805

10V 402

CERM

20%

0.1UF

22UF

20%

6.3V 805

CERM-X5R

22UF

20%

6.3V 805

CERM-X5R

22UF

CERM-X5R 805

6.3V

20%

22UF

CERM-X5R 805

6.3V

20%

10V

0.1UF

402

CERM

20%

10V

0.1UF

402

CERM

20%

10V

0.1UF

402

CERM

20%

10V

0.1UF

402

CERM

20%

10V

0.1UF

402

CERM

20%

22UF

CERM-X5R

20%

805

6.3V

0.01UF

10% 16V

402

CERM

PLACEMENT_NOTE=Place near CPU pin B26.

603

10uF

20%

6.3V X5R

CRITICAL

PLACEMENT_NOTE=Place in CPU center cavity.

D2T

TANT

330UF

2.0V

10%

PLACEMENT_NOTE=Place in CPU center cavity.

D2T

TANT

CRITICAL

330UF

2.0V

10%

PLACEMENT_NOTE=Place in CPU center cavity.

10%

D2T

TANT

CRITICAL

330UF

2.0V

PLACEMENT_NOTE=Place in CPU center cavity.

CRITICAL

D2T

TANT

10%

330UF

2.0V

051-7225

SYNC_DATE=03/19/2007

A.0.0

12 88

SYNC_MASTER=M76_MLB

CPU Decoupling & VID

=PPVCORE_S0_CPU

CPU_VID<0..6>

MAKE_BASE=TRUE

IMVP6_VID<0..6>

=PP1V5_S0_CPU

=PP1V05_S0_CPU

C1208

1

2

C1207

1

2

C1219

1

2

C1218

1

2

C1206

1

2

C1204

1

2

C1216

1

2

C1214

1

2

C1203

1

2

C1202

1

2

C1201

1

2

C1213

1

2

C1212

1

2

C1211

1

2

C1200

1

2

C1210

1

2

C1236

1

2

C1205

1

2

C1209

1

2

C1215

1

2

C1217

1

2

C1237

1

2

C1238

1

2

C1239

1

2

C1240

1

2

C1241

1

2

C1281

1

2

C1280

1

2

C1250

1

2 3

C1251

1

2 3

C1252

1

2 3

C1253

1

2 3

C1235

1

2 3

13

49

79

11

79

58

11

10

8

11

7

8

IN

BI

OUT

IN

BI

IN

IN IN

OUT

IN

OUT OUT

OUT

IN

BI

IN

BI

IN

IN IN

IN

IN IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NB CFG[0] NB CFG[1]

Use with 920-0451 adapter board to support CPU, NB & SB debugging.

Mini-XDP Connector

NOTE: This is not the standard XDP pinout.

(VCC_OBS_CD)

OBSFN_C0

OBSDATA_D3

SB GPIO[8]

NB CFG[8]

NB CFG[3]

NB CFG[7]

NB CFG[6]

NB CFG[5]

NB CFG[4]

NB CFG[2]

SB OC[4]#

(OBSDATA_A2)

SB OC[3]#

PWRGD/HOOK0

TCK0

(OBSDATA_A3)

NC

OBSFN_C1

OBSDATA_C0

OBSDATA_C2

TDO

ITPCLK#/HOOK5

RESET#/HOOK6 DBR#/HOOK7

SB OC[0]#

OBSDATA_C3

SB OC[1]#

SB OC[2]#

SB OC[5]#

SB OC[6]# SB OC[7]#

TCK1

SCL

SDA

OBSDATA_B1

OBSDATA_A1

OBSFN_A1

TRSTn

HOOK3

HOOK2

VCC_OBS_AB

HOOK1

OBSDATA_D1

OBSDATA_D0

OBSDATA_A3

OBSDATA_A2

OBSDATA_B3

OBSDATA_B2

OBSFN_A0

OBSDATA_A0

ITPCLK/HOOK4

Direction of XDP module

on even-numbered side of J1300

Please avoid any obstructions

OBSDATA_C1

XDP_PRESENT#

TMS

TDI

OBSDATA_B0

998-1571

OBSDATA_D2

(OBSDATA_A1)

(OBSDATA_A0)

7

10 23 79

402

MF-LF

1/16W

5%

1K

XDP

15

1/16W

XDP

402

MF-LF

1%

54.9

402

16V

10%

0.1uF

X5R

XDP

MF-LF

10K

5%

XDP

1/16W 402

MF-LF

10K

5%

1/16W

XDP

402

16V

10%

0.1uF

X5R

XDP

10 28

10 79

7

10 14 79

10 79

30 79 84

24 34

24

24 77

24

24 36

24

24 43

1/16W

402

MF-LF

5%

1K

XDP

XDP_CONN

CRITICAL

F-ST-SM

LTH-030-01-G-D-NOPEGS

16 30 79

16

25 45

16

16 30 79

16

eXtended Debug Port (XDP)

SYNC_DATE=12/12/2006

SYNC_MASTER=T9_NOME

13

A.0.0

88

051-7225

=PP1V05_S0_CPU

NB_BSEL<1>

PM_LATRIGGER_L EXTGPU_LVDS_EN

=PP3V3_S0_XDP

XDP_CLK_P

XDP_OBS20

LVDS_CTRL_CLK

LVDS_CTRL_DATA

XDP_TRST_L

XDP_DBRESET_L

USB_EXTA_OC_L SB_GPIO40

XDP_TMS

XDP_TDI

XDP_CPURST_L FSB_CPURST_L

XDP_TDO

XDP_TCK

XDP_BPM_L<3>

TP_XDP_HOOK3

SB_GPIO30 USB_EXTB_OC_L

TP_XDP_HOOK2

WOW_EN

XDP_BPM_L<5>

XDP_BPM_L<2>

XDP_BPM_L<0>

NB_BSEL<0>

NB_CFG<4> NB_CFG<5>

NB_CFG<6> NB_CFG<7>

XDP_PWRGDCPU_PWRGD

SMC_WAKE_SCI_L

NB_BSEL<2> NB_CFG<3>

USB_EXTD_OC_L

NB_CFG<8>

XDP_CLK_N

XDP_BPM_L<1>

XDP_BPM_L<4>

R1399

1 2

R1315

1

2

C1300

1

2

R1331

1

2

R1330

1

2

C1301

1

2

R1303

1 2

J1300

1

10

1112 1314 1516 1718 19

2

20

2122 2324 2526 2728 29

3

30

3132 3334 3536 3738 39

4

40

4142 4344 4546 4748 49

5

50

5152 5354 5556 5758 59

6

60

78 9

12 11 10

8

79

BI

BI BI

OUT

BI

BI BI

BI

BI BI BI BI

BI BI

BI

BI BI

BI BI BI BI

BI BI

OUT

BI

OUT

BI BI BI BI BI

BI BI

H_D0*

H_D3*

H_D2*

H_D33* H_D34* H_D35*

H_D1*

H_D4*

H_D10*

H_A4* H_A5* H_A6* H_A7* H_A8*

H_A9* H_A10* H_A11* H_A12* H_A13* H_A14* H_A15* H_A16* H_A17* H_A18* H_A19* H_A20* H_A21* H_A22* H_A23* H_A24* H_A25* H_A26* H_A27* H_A28* H_A29* H_A30* H_A31* H_A32* H_A33* H_A34* H_A35*

H_ADS*

H_ADSTB0* H_ADSTB1*

H_A3*

H_D7* H_D8* H_D9*

H_D11* H_D12* H_D13* H_D14* H_D15* H_D16* H_D17* H_D18* H_D19* H_D20* H_D21* H_D22* H_D23*

H_D25* H_D26* H_D27* H_D28* H_D29* H_D30*

H_D32*

H_D36* H_D37* H_BNR* H_D38*

H_BPRI* H_D39* H_D40*

H_DEFER*

H_D41*

H_DBSY* H_D42* H_D43* H_D44*

H_DPWR* H_D45*

H_DRDY* H_D46* H_HIT* H_D47*

H_HITM* H_D48*

H_LOCK*

H_TRDY*

H_D51* H_D52* H_D53*

H_DINV0*

H_D54*

H_DINV1*

H_D55*

H_DINV2*

H_D56*

H_DINV3*

H_D57* H_D58*

H_DSTBN0*

H_D59*

H_DSTBN1*

H_D60*

H_DSTBN2*

H_D61*

H_DSTBN3*

H_D62* H_D63*

H_DSTBP0* H_DSTBP1*

H_DSTBP2* H_SWING H_RCOMP

H_REQ0* H_SCOMP H_REQ1* H_SCOMP*

H_REQ2*

H_REQ3* H_CPURST*

H_REQ4* H_CPUSLP*

H_RS0* H_RS1*

H_AVREF

H_RS2*

H_DVREF

H_D5* H_D6*

H_D31*

H_BREQ*

H_D24*

H_D49* H_D50*

H_DSTBP3*

HPLL_CLK

HPLL_CLK*

HOST

(1 OF 10)

BI BI BI BI

BI

IN

OUT OUT

BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI

BI BI BI BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

X5R

0.1uF

10% 16V

402

2.0K

MF-LF

1%

1/16W

402

1K

MF-LF

1%

1/16W

402

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

54.9

MF-LF

1% 1/16W

402

24.9

MF-LF

1%

1/16W

402

221

MF-LF

1%

1/16W

402

100

MF-LF

1%

1/16W

402

X5R

0.1uF

10% 16V

402

7

10 79

OMIT

CRESTLINE

FCBGA

10 79

7

10 79

54.9

MF-LF

1%

1/16W

402

7

10 79

7

30 84

7

30 84

7

10 13 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

SYNC_DATE=03/16/2007

NB CPU Interface

051-7225

A.0.0

8814

SYNC_MASTER=T9_NOME

FSB_RS_L<2>

FSB_RS_L<0> FSB_RS_L<1>

FSB_REQ_L<4>

FSB_REQ_L<3>

FSB_REQ_L<2>

FSB_REQ_L<1>

FSB_REQ_L<0>

FSB_DSTB_L_P<3>

FSB_DSTB_L_P<2>

FSB_DSTB_L_P<1>

FSB_DSTB_L_P<0>

FSB_DSTB_L_N<3>

FSB_DSTB_L_N<2>

FSB_DSTB_L_N<1>

FSB_DSTB_L_N<0>

FSB_DINV_L<3>

FSB_DINV_L<2>

FSB_DINV_L<1>

FSB_DINV_L<0>

FSB_LOCK_L FSB_TRDY_L

FSB_HITM_L

FSB_HIT_L

FSB_DRDY_L

FSB_CLK_NB_N

FSB_CLK_NB_P

FSB_DPWR_L

FSB_DBSY_L

FSB_DEFER_L

FSB_BREQ0_L

FSB_BNR_L FSB_BPRI_L

FSB_ADSTB_L<1>

FSB_ADSTB_L<0>

FSB_ADS_L

FSB_A_L<35>

FSB_A_L<34>

FSB_A_L<33>

FSB_A_L<31>

FSB_A_L<30>

FSB_A_L<32>

FSB_A_L<29>

FSB_A_L<28>

FSB_A_L<27>

FSB_A_L<26>

FSB_A_L<25>

FSB_A_L<24>

FSB_A_L<23>

FSB_A_L<22>

FSB_A_L<21>

FSB_A_L<20>

FSB_A_L<19>

FSB_A_L<18>

FSB_A_L<17>

FSB_A_L<16>

FSB_A_L<15>

FSB_A_L<14>

FSB_A_L<13>

FSB_A_L<12>

FSB_A_L<10> FSB_A_L<11>

FSB_A_L<9>

FSB_A_L<8>

FSB_A_L<7>

FSB_A_L<5>

FSB_A_L<4>

FSB_A_L<6>

FSB_A_L<3>

NB_FSB_VREF

NB_FSB_RCOMP

NB_FSB_SWING

FSB_D_L<59>

FSB_D_L<41>

FSB_D_L<38>

FSB_D_L<0>

FSB_D_L<4> FSB_D_L<5>

FSB_D_L<43>

FSB_D_L<12>

FSB_D_L<50>

FSB_D_L<49>

FSB_D_L<24>

FSB_D_L<31>

FSB_D_L<6>

FSB_CPUSLP_L

FSB_CPURST_L

NB_FSB_SCOMP_L

NB_FSB_SCOMP

FSB_D_L<63>

FSB_D_L<62>

FSB_D_L<61>

FSB_D_L<60>

FSB_D_L<58>

FSB_D_L<57>

FSB_D_L<56>

FSB_D_L<55>

FSB_D_L<54>

FSB_D_L<53>

FSB_D_L<52>

FSB_D_L<51>

FSB_D_L<48>

FSB_D_L<46>

FSB_D_L<45>

FSB_D_L<44>

FSB_D_L<42>

FSB_D_L<40>

FSB_D_L<39>

FSB_D_L<37>

FSB_D_L<36>

FSB_D_L<32>

FSB_D_L<30>

FSB_D_L<29>

FSB_D_L<28>

FSB_D_L<27>

FSB_D_L<26>

FSB_D_L<25>

FSB_D_L<23>

FSB_D_L<22>

FSB_D_L<21>

FSB_D_L<20>

FSB_D_L<19>

FSB_D_L<18>

FSB_D_L<17>

FSB_D_L<16>

FSB_D_L<15>

FSB_D_L<14>

FSB_D_L<13>

FSB_D_L<11>

FSB_D_L<9>

FSB_D_L<8>

FSB_D_L<7>

FSB_D_L<10>

FSB_D_L<1>

FSB_D_L<35>

FSB_D_L<34>

FSB_D_L<33>

FSB_D_L<2> FSB_D_L<3>

FSB_D_L<47>

=PP1V25R1V05_S0_FSB_NB

C1425

1

2

R1426

1

2

R1425

1

2

R1420

1

2

R1415

1

2

R1410

1

2

R1411

1

2

C1410

1

2

U1400

G17 C14 K16 B13 L16 J17 B14 K19 P15 R17 B16 H20 L19 D17 M17 N16 J19 B18 E19 B17

J13

B15 E17 C18 A19 B19 N19

B11 C11 M11 C15 F16 L13

G12 H17 G20

B9

C8 E8 F12

B6 E5

E2 G2

M10 N12

N9 H5

P13

K9 M2

W10

Y8 V4

G7

M3 J1 N5 N3 W6 W9 N2 Y7 Y9 P4

M6

W3 N1

AD12

AE3 AD9 AC9

AC7 AC14 AD11 AC11

H7

AB2

AD7

AB1

Y3 AC6 AE2 AC5 AG3 AJ9 AH8

H3

AJ14

AE9

AE11 AH12

AJ5 AH5 AJ6 AE7 AJ7 AJ2

G4

AE5 AJ3 AH2

AH13

F3

N8

H2

C10

D6

K5 L2 AD13 AE13

H8 K7

M7 K3 AD2 AH11

L7 K2 AC2 AJ10

A9

E4 C6 G10

C2

M14 E13 A11 H13 B12

E12 D7 D8

W1

W2

B3

B7

AM5 AM7

R1421

1

2

30

8

IN

OUT

IN

OUT OUT OUT

OUT

IN

OUT

BI

L_BKLT_CTRL

L_VDD_EN

PEG_TX15*

PEG_TX14*

PEG_TX13*

PEG_TX12*

PEG_TX11*

PEG_TX10*

PEG_TX9*

PEG_TX8*

PEG_TX7*

PEG_TX6*

PEG_TX5*

PEG_TX4*

PEG_TX3*

PEG_TX2*

PEG_TX1*

PEG_TX0*

PEG_TX15

PEG_TX14

PEG_TX13

PEG_TX12

PEG_TX11

PEG_TX10

PEG_TX9

PEG_TX8

PEG_TX7

PEG_TX6

PEG_TX5

PEG_TX4

PEG_TX3

PEG_TX2

PEG_TX1

PEG_TX0

PEG_RX14

PEG_RX15*

PEG_RX14*

PEG_RX13*

PEG_RX12*

PEG_RX11*

PEG_RX15

PEG_RX13

PEG_RX12

PEG_RX11

PEG_RX10

PEG_RX9

PEG_RX8

PEG_RX7

PEG_RX6

PEG_RX5

PEG_RX4

PEG_RX3

PEG_RX2

PEG_RX1

PEG_RX0

PEG_RX10*

PEG_RX9*

PEG_RX8*

PEG_RX7*

PEG_RX6*

PEG_RX5*

PEG_RX4*

PEG_RX3*

PEG_RX2*

PEG_RX1*

PEG_RX0*

PEG_COMPI PEG_COMPO

CRT_DDC_DATA

L_CTRL_DATA

LVDSB_DATA1 LVDSB_DATA2

LVDSB_DATA0

LVDSB_DATA2*

LVDSB_DATA1*

LVDSB_DATA0*

LVDSA_DATA2

LVDSA_DATA0 LVDSA_DATA1

LVDSB_CLK*

LVDS_VREFL

LVDS_IBG

TVC_RTN

TVA_RTN TVB_RTN

TVC_DAC

TVB_DAC

TVA_DAC

CRT_RED*

CRT_RED

CRT_GREEN*

CRT_GREEN

CRT_BLUE*

CRT_BLUE

CRT_VSYNC

CRT_TVO_IREF

CRT_HSYNC

CRT_DDC_CLK

L_BKLT_EN

L_DDC_CLK

TV_DCONSEL0 TV_DCONSEL1

LVDSA_DATA2*

L_DDC_DATA

LVDSA_DATA1*

LVDSA_DATA0*

LVDSB_CLK

LVDSA_CLK

LVDSA_CLK*

LVDS_VREFH

L_CTRL_CLK

LVDS_VBG

VGA

TV

LVDS

(3 OF 10)

PCI-EXPRESS GRAPHICS

BI

OUT

IN

IN IN

IN

IN IN IN IN IN

IN

OUT

IN

OUT

IN

OUT

IN

OUT

OUT OUT

IN

BI BI

OUT OUT OUT OUT

OUT OUT

IN

OUT

OUT OUT

OUT

OUT OUT

OUT

OUT OUT

IN

OUT OUT OUT

OUT

BI BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

recommendation is to float both signals, see Radar #5067636.

a glitch during wake-up on LVDS DATA/CLK pairs. New

Note: SR DG says to tie LVDS_VREFH/L to GND. This causes

If SDVO is used, VCCD_LVDS must remain powered with proper

should connect to GND through 75-ohm resistors.

omit filtering components. Unused DAC outputs

Unused DAC outputs must remain powered, but can

Can leave all signals NC if LVDS is not implemented.

decoupling. Otherwise, tie VCCD_LVDS to GND also.

Tie VCC_TX_LVDS and VCCA_LVDS to GND.

SDVO_FLDSTALL#

SDVO Alternate Function

SDVO_TVCLKIN# SDVO_INT#

SDVO_TVCLKIN SDVO_INT SDVO_FLDSTALL

SDVOB_GREEN

SDVOB_RED

SDVOC_CLKN

SDVOC_BLUE#

SDVOC_GREEN#

SDVOC_RED#

SDVOB_CLKN

SDVOB_BLUE#

SDVOB_GREEN#

SDVOB_RED#

SDVOB_CLKP

SDVOB_BLUE

SDVOC_CLKP

SDVOC_BLUE

SDVOC_GREEN

SDVOC_RED

LVDS Disable

TVDAC rails. VCCA_TVx_DAC and VCCA_DAC_BG can

Component: DACA, DACB & DACC

Composite: DACA only

TV-Out Signal Usage:

Can tie the following rails to GND:

VSYNC and CRT_TVO_IREF to GND.

CRT Disable / TV-Out Enable

TV-Out Disable / CRT Enable Tie TVx_DAC and TVx_RTN to GND. Must power all

Leave GFX_VID<3..0> and GFX_VR_EN as NC.

Tie VCC_AXG and VCC_AXG_NCTF to GND.

Tie VCCA_DPLLA and VCCA_DPLLB to VCC (VCore).

Tie DPLL_REF_CLK and DPLL_REF_SSCLK to GND.

Can also tie CRT_DDC_*, L_CTRL_*, L_DDC_*, SDVO_CTRL_* and TV_DCONSELx to GND.

Follow instructions for LVDS and CRT & TV-Out Disable above.

Internal Graphics Disable

and filtered at all times!

NOTE: Must keep VDDC_TVDAC powered

VCCD_CRT, VCCD_QDAC and VCC_SYNC.

VCCA_CRT_DAC, VCCA_DAC_BG, VCCA_TVx_DAC,

All CRT/TVDAC rails must be powered. All

CRT & TV-Out Disable Tie TVx_DAC, TVx_RTN, R/R#/G/G#/B/B#, HSYNC,

Tie R/R#/G/G#/B/B#, HSYNC and VSYNC to GND.

share filtering with VCCA_CRT_DAC.

S-Video: DACB & DACC only

Tie DPLL_REF_CLK* and DPLL_REF_SSCLK* to VCC (VCore).

rails must be filtered except for VCCA_CRT.

66 80

402

MF-LF

1/16W

1%

24.9

77

66 80

22

66 80

22

22 80

OMIT

CRESTLINE

FCBGA

13

22

66 80

77

66 80

77

77 80

66 80

77 80

66 80

22

SYNC_DATE=03/16/2007

15 88

A.0.0

051-7225

NB PEG / Video Interfaces

SYNC_MASTER=T9_NOME

=TV_B_RTN

=TV_B_DAC

LVDS_B_DATA_N<2>

LVDS_B_DATA_N<1>

LVDS_CTRL_DATA

LVDS_CTRL_CLK

TP_LVDS_VBG

PEG_D2R_P<9>

PEG_D2R_P<11>

PEG_D2R_P<10>

PP1V05_S0_NB_VCCPEG

PEG_D2R_N<1>

PEG_D2R_N<6>

TP_LVDS_VREFH

LVDS_A_CLK_N LVDS_A_CLK_P

LVDS_B_CLK_P

LVDS_A_DATA_N<0> LVDS_A_DATA_N<1>

LVDS_DDC_DATA

LVDS_A_DATA_N<2>

TV_DCONSEL<1>

TV_DCONSEL<0>

LVDS_DDC_CLK

LVDS_BKLT_EN

CRT_DDC_CLK

=CRT_HSYNC_R =CRT_TVO_IREF =CRT_VSYNC_R

=CRT_BLUE =CRT_BLUE_L =CRT_GREEN =CRT_GREEN_L =CRT_RED =CRT_RED_L

=TV_A_DAC

=TV_C_DAC

=TV_A_RTN

=TV_C_RTN

LVDS_IBG

TP_LVDS_VREFL

LVDS_B_CLK_N

LVDS_A_DATA_P<1>

LVDS_A_DATA_P<0>

LVDS_A_DATA_P<2>

LVDS_B_DATA_N<0>

LVDS_B_DATA_P<0>

LVDS_B_DATA_P<2>

LVDS_B_DATA_P<1>

CRT_DDC_DATA

PEG_COMP

PEG_D2R_N<0>

PEG_D2R_N<2> PEG_D2R_N<3> PEG_D2R_N<4> PEG_D2R_N<5>

PEG_D2R_N<7> PEG_D2R_N<8> PEG_D2R_N<9> PEG_D2R_N<10>

PEG_D2R_P<0> PEG_D2R_P<1> PEG_D2R_P<2> PEG_D2R_P<3> PEG_D2R_P<4> PEG_D2R_P<5> PEG_D2R_P<6> PEG_D2R_P<7> PEG_D2R_P<8>

PEG_D2R_P<12> PEG_D2R_P<13>

PEG_D2R_P<15>

PEG_D2R_N<11> PEG_D2R_N<12> PEG_D2R_N<13> PEG_D2R_N<14> PEG_D2R_N<15>

PEG_D2R_P<14>

PEG_R2D_C_P<0> PEG_R2D_C_P<1> PEG_R2D_C_P<2> PEG_R2D_C_P<3> PEG_R2D_C_P<4> PEG_R2D_C_P<5> PEG_R2D_C_P<6> PEG_R2D_C_P<7> PEG_R2D_C_P<8> PEG_R2D_C_P<9> PEG_R2D_C_P<10> PEG_R2D_C_P<11> PEG_R2D_C_P<12> PEG_R2D_C_P<13> PEG_R2D_C_P<14> PEG_R2D_C_P<15>

PEG_R2D_C_N<0> PEG_R2D_C_N<1> PEG_R2D_C_N<2> PEG_R2D_C_N<3> PEG_R2D_C_N<4> PEG_R2D_C_N<5> PEG_R2D_C_N<6> PEG_R2D_C_N<7> PEG_R2D_C_N<8> PEG_R2D_C_N<9> PEG_R2D_C_N<10> PEG_R2D_C_N<11> PEG_R2D_C_N<12> PEG_R2D_C_N<13> PEG_R2D_C_N<14> PEG_R2D_C_N<15>

LVDS_VDD_EN

LVDS_BKLT_CTL

R1510

1

2

U1400

H32 G32

K33 G35

K29 J29

F33

F29 E29

C32 E33

J40 H39 E39 E40 C37 D35 K40

L41 L43 N41 N40

C45

D46

G50

G51

E50

E51

F48

F49

E42

D44

E44

G44

A47

B47

A45

B45

N43 M43

J50

J51

L50

L51

AC45

AD44

AC41

AD40

AH47

AG46

AG49

AH49

AH45

AG45

AG42

AG41

M47

N47

U44

T45

T49

T50

T41

U40

W45

Y44

W41

Y40

AB50

AB51

Y48

W49

M45

N45

T38

U39

AD47

AC46

AC50

AC49

AD43

AC42

AG39

AH39

AE50

AE49

AH43

AH44

T46

U47

N50

N51

R51

R50

U43

T42

W42

Y43

Y47

W46

Y39

W38

AC38

AD39

M35 P33

E27

F27

G27

J27

K27

L27

21 19

22

IN

CLKREQ*

NC1

NC8

CL_CLK

CL_PWROK

CL_RST*

RSVD6

THERMTRIP*

PM_BM_BUSY*

RSVD4

RSVD3

RSVD7

SM_CKE1

SM_CK0*

SM_CKE0

SM_ODT0

SM_ODT2

SM_RCOMP

SM_RCOMP*

SM_VREF0 SM_VREF1

SM_RCOMP_VOL

SM_CS1*

SM_CS0*

RSVD14

RSVD11

RSVD10

RSVD9

RSVD5

RSVD8

RSVD2

DPLL_REF_CLK*

DPLL_REF_SSCLK

PEG_CLK

DMI_RXN1

DMI_RXN0

DMI_RXN3

DMI_RXN2

DMI_RXP0 DMI_RXP1 DMI_RXP2

DMI_TXN0

DMI_RXP3

DMI_TXN2

DMI_TXN1

DMI_TXP0

DMI_TXN3

DMI_TXP1 DMI_TXP2 DMI_TXP3

PEG_CLK*

RSVD12

CL_DATA

CL_VREF

SDVO_CTRL_CLK

SDVO_CTRL_DATA

ICH_SYNC*

TEST1 TEST2

GFX_VID0 GFX_VID1 GFX_VID2

GFX_VR_EN

GFX_VID3

RSVD20 RSVD21

RSVD24 RSVD25

RSVD27

RSVD34 RSVD35 RSVD36 RSVD37 RSVD38 RSVD39

RSVD41 RSVD42

RSVD40

RSVD43 RSVD44 RSVD45

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13

CFG16

CFG15

CFG14

CFG17 CFG18 CFG19 CFG20

PM_DPRSTP* PM_EXT_TS0*

PWROK

PM_EXT_TS1*

RSTIN*

DPRSLPVR

NC2

NC4

NC3

NC5

NC7

NC6

NC10

NC9

NC12

NC11

NC13 NC14 NC15 NC16

DPLL_REF_CLK

SM_RCOMP_VOH

SM_ODT3

SM_ODT1

RSVD13

SM_CS2* SM_CS3*

SM_CK3 SM_CK4

SM_CK4*

SM_CKE3

RSVD1

SM_CKE4

DPLL_REF_SSCLK*

SM_CK3*

SM_CK1*

SM_CK1

SM_CK0

SA_MA14

RSVD22 RSVD23

RSVD26

SB_MA14

SM_CK2 SM_CK2* SM_CK5 SM_CK5*

(2 OF 10)

RSVD

DDR MUXING

CLK

CFG

DMI

PM

GRAPHICS VID

ME

MISC

NC

OUT OUT OUT OUT OUT

BI BI

IN

OUT

BI

BI OUT OUT

IN

OUT

OUT OUT

IN IN IN OUT

OUT OUT OUT

BI

OUT

BI

OUT

IN

OUT

OUT OUT OUT

OUT

OUT OUT OUT

OUT OUT OUT OUT

IN

IN IN

IN

IN IN IN IN

IN IN

IN

OUT

OUT OUT

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NB CFG<13:12> require ICT access

IPU

RESERVED

Low = DMIx2

NB_CFG<3>

NB_CFG<8>

IPU

IPU IPU IPU IPU IPD

IPD

Clk used for PEG and DMI

IPU

RESERVED

NB_CFG<6>

High = DMIx4

NB_CFG<7>

RESERVED RESERVED

RESERVED

High = Normal Low = Reversed

NB_CFG<10>

NB_CFG<9>

PCIe Graphics Lane Reversal

RESERVED

See Below

Low = Disabled

High = Enabled

10 = All-Z Mode Enabled

01 = XOR Mode Enabled

Low = Normal

High = Both active

NB_CFG<13:12>

Low = Only SDVO

High = Reversed

11 = Normal Operation

or PCIe x16

00 = RESERVED

NB_CFG<19>

NB_CFG<20>

Concurrent SDVO/PCIe x1

Reversal

DMI Lane

NB_CFG<13>

NB_CFG<12>

NB_CFG<11>

NB_CFG<16>

NB_CFG<14>

NB_CFG<17>

ODT

FSB Dynamic

NB_CFG<15>

NB_CFG<18>

PP1V05_S0M, PP0V9_S3M and PP0V9_S0M. If ME/AMT is not used, short CL_PWROK to PWROK.

PP3V3_S0M, PP3V3_S0MWOL, PP1V8_S3M, PP1V25_S0M,

NOTE: GMCH CL_PWROK input must be PWRGD signal for

DMI x2 Select

NB_CFG<5>

NB_CFG<4>

IPU

NB CFG<8:0> used for debug access

7

28

8

402

CERM

20%

0.1uF

10V

402

CERM

20%

0.1uF

10V

CRESTLINE

FCBGA

OMIT

9

25 83

9

25 83

22

7

29

7

25

402

20K

MF-LF

1/16W

5%

402

0

MF-LF

1/16W

5%

7

25 58 79

32 45

402

10K

MF-LF

5% 1/16W

0.01UF

10% 16V

CERM

402 603

2.2UF

6.3V CERM1

20%

1K

MF-LF

1% 1/16W

402

1% 1/16W MF-LF

3.01K

603

6.3V CERM1

2.2UF

20%

0.01UF

10% 16V

CERM

402

1K

402

1/16W

1% MF-LF

402

392

MF-LF

1/16W

1%

402

MF-LF

1/16W

1K

1%

402

20% 10V

CERM

0.1uF

402

5%

3.9K

MF-LF

1/16W

NBCFG_DMI_X2

402

5% 1/16W MF-LF

3.9K

NBCFG_PEG_REVERSE

402

NBCFG_DYN_ODT_DISABLE

3.9K

1/16W

5% MF-LF

402

3.9K

MF-LF

1/16W

5%

NBCFG_DMI_REVERSE

402

5% 1/16W MF-LF

3.9K

NBCFG_SDVO_AND_PCIE

9

31 33 81

32 33 81

13 30 79

13

13 16

25

13

10 23 46 79

31 45

7

10 23 58 79

7 9

28 58

31 81

32 81

31 81

32 81

31 81

31 33 81

32 33 81

31 33 81

32 33 81

31 33 81

32 33 81

31 33 81

32 33 81

MF-LF

1/16W

1%

20

402

1/16W

1%

MF-LF

20

402

8

7

30 84

7

30 84

22

24 80

402

MF-LF

1/16W

5%

10K

051-7225

A.0.0

8816

SYNC_MASTER=T9_NOME

SYNC_DATE=03/16/2007

NB Misc Interfaces

MEM_RCOMP_VOH

=PP1V8_S3M_MEM_NB

MEM_RCOMP

MEM_RCOMP_VOL

=PP0V9_S3M_MEM_NBVREFA

MEM_CKE<3>

MEM_CKE<1>

NB_CFG<4>

TP_NB_RSVD<44>

TP_NB_RSVD<43>

MEM_RCOMP_L

NB_CFG<5>

NB_CFG<9>

NB_CFG<8>

NB_CFG<7>

NB_CFG<6>

NB_CFG<3>

NB_BSEL<1> NB_BSEL<2>

NB_CLINK_VREF

GFX_VID<0>

PP1V25_S0M_NB_VCCAXD

CLINK_NB_CLK

GFX_VID<1>

TP_NB_CFG<17>

=PP3V3_S0_NB_VCCHV

=GFX_VR_EN

GFX_VID<3>

TP_NB_CFG<13>

TP_NB_CFG<11>

=PP3V3_S0_NB_VCCHV

NB_CFG<20>

NB_CFG<19>

=PP3V3_S0_NB_VCCHV

NB_CFG<16>

NB_CFG<9>

PM_EXTTS_L<1>

NB_RESET_L

PM_DPRSLPVR

TP_NB_RSVD<14>

DMI_S2N_N<1>

DMI_S2N_N<3>

TP_NB_RSVD<42>

TP_NB_RSVD<45>

TP_LVDS_B_DATAN3

TP_NB_RSVD<36>

TP_NB_RSVD<35>

DMI_S2N_N<0>

MEM_A_A<14>

TP_LVDS_B_DATAP3

TP_LVDS_A_DATAN3

TP_MEM_CLKP2

TP_NB_RSVD<24>

TP_NB_RSVD<5>

=PP0V9_S3M_MEM_NBVREFB

DMI_S2N_N<2>

DMI_S2N_P<3>

GFX_VID<4>

TP_NB_NC<4>

TP_NB_RSVD<12>

TP_NB_RSVD<6>

MEM_ODT<1>

MEM_ODT<0>

MEM_CS_L<3>

=NB_CLK96M_DOT_N

MEM_ODT<3>

MEM_ODT<2>

MEM_CS_L<2>

PM_THRMTRIP_L

VR_PWRGOOD_DELAY

CPU_DPRSTP_L

PM_BMBUSY_L

TP_MEM_CLKN5

TP_MEM_CLKP5

TP_MEM_CLKN2

NB_SB_SYNC_L

NB_CLKREQ_L

SDVO_CTRLDATA

SDVO_CTRLCLK

CLINK_NB_RESET_L

=NB_CLINK_MPWROK

CLINK_NB_DATA

GFX_VID<2>

DMI_N2S_P<3>

DMI_N2S_P<2>

DMI_N2S_P<1>

DMI_N2S_P<0>

DMI_N2S_N<2> DMI_N2S_N<3>

DMI_N2S_N<1>

DMI_N2S_N<0>

DMI_S2N_P<2>

DMI_S2N_P<1>

DMI_S2N_P<0>

NB_CLK100M_PCIE_N

NB_CLK100M_PCIE_P

=NB_CLK96M_DOT_P

TP_NB_NC<1>

TP_NB_NC<8>

TP_NB_RSVD<4>

TP_NB_RSVD<3>

TP_NB_RSVD<7>

MEM_CLK_N<0>

MEM_CLK_P<1>

MEM_CLK_N<1>

MEM_CKE<0>

MEM_CS_L<1>

MEM_CS_L<0>

TP_NB_RSVD<11>

TP_NB_RSVD<10>

TP_NB_RSVD<9>

TP_NB_RSVD<8>

TP_NB_RSVD<2>

NB_TEST1 NB_TEST2

TP_NB_RSVD<20> TP_NB_RSVD<21> TP_NB_RSVD<22> TP_NB_RSVD<23>

TP_NB_RSVD<41>

TP_NB_CFG<10>

TP_NB_CFG<12>

NB_CFG<16>

TP_NB_CFG<15>

TP_NB_CFG<14>

TP_NB_CFG<18> NB_CFG<19> NB_CFG<20>

PM_EXTTS_L<0>

TP_NB_NC<2> TP_NB_NC<3>

TP_NB_NC<5>

TP_NB_NC<7>

TP_NB_NC<6>

TP_NB_NC<10>

TP_NB_NC<9>

TP_NB_NC<12>

TP_NB_NC<11>

TP_NB_NC<13> TP_NB_NC<14> TP_NB_NC<15> TP_NB_NC<16>

TP_NB_RSVD<13>

MEM_CLK_P<3> MEM_CLK_P<4>

MEM_CLK_N<3> MEM_CLK_N<4>

MEM_CLK_P<0>

TP_NB_RSVD<1>

MEM_CKE<4>

NB_CFG<5>

NB_BSEL<0>

=NB_CLK100M_DPLLSS_N

=NB_CLK100M_DPLLSS_P

TP_NB_RSVD<25> TP_NB_RSVD<26> TP_NB_RSVD<27>

MEM_B_A<14> TP_NB_RSVD<34>

TP_LVDS_A_DATAP3

R1610

1

2

R1611

1

2

R1630

1

2

C1616

1

2

C1615

1

2

U1400

P27 N27

R24 L23 J23 E23 E20 K23 M20 M24 L32 N33

N24

L35

C21 C23 F23 N23 G23 J20 C20

AM49 AK50 AT43 AN49 AM50

G39

AN47 AJ38 AN42 AN46

AM47 AJ39 AN41 AN45

AJ46 AJ41 AM40 AM44

AJ47 AJ42 AM39 AM43

B42 C42 H48 H47

G36

E35 A39 C38 B39 E36

G40

BJ51

E1

A5 C51 B50 A50 A49 BK2

BK51 BK50 BL50 BL49

BL3 BL2 BK1 BJ1

K44 K45

G41 L39 L36 J36

AW49 AV20

P36

AR37 AM36 AL36 AM37

D20

P37

H10 B51

BJ20 BK22 BF19 BH20 BK18 BJ18

R35

BH39 AW20 BK20

C48 D47 B44

N35

C44 A35 B37 B36 B34 C34

AR12 AR13 AM12 AN13

J12

BJ29 BE24

H35 K36

AV29

AW30

BB23

BA23

BF23 BG23

BA25

AW25

AV23

AW23

BC23 BD24

BE29 AY32 BD39 BG37

BG20 BK16 BG16 BE13

BH18 BJ15 BJ14 BE16

BL15 BK14

BK31 BL31

AR49 AW4

A37 R32

N20

R1691

1

2

R1690

1

2

R1631

1

2

C1625

1

2

C1624

1

2

R1624

1

2

R1622

1

2

C1622

1

2

C1623

1

2

R1620

1

2

R1641

1

2

R1640

1

2

C1640

1

2

R1655

1

2

R1659

1

2

R1666

1

2

R1669

1

2

R1670

1

2

21

19

18

21

16

8

16

83

19

8

16

8

16

7

16

7

13

BI

BI BI BI BI BI

OUT

BI

OUT

BI BI BI

BI

BI BI BI BI

BI BI

BI BI BI BI BI

BI BI BI

BI

BI BI BI

BI

BI BI BI BI

BI

BI BI BI BI BI

BI BI

BI

OUT

BI

OUT

OUT OUT

OUT

OUT OUT

OUT

BI

OUT

BI

BI BI BI

BI

BI BI BI

BI BI

BI

BI BI

OUT

BI

OUT OUT

OUT

BI

OUT

SA_DQ0 SA_DQ1 SA_DQ2

SA_DQ4

SA_DQ6

SA_DQ14

SA_CAS*

SA_BS2

SA_DQ63

SA_DQ62

SA_DQ61

SA_DQ60

SA_DQ59

SA_DQ58

SA_DQ57

SA_DQ56

SA_DQ55

SA_DQ54

SA_DQ53

SA_DQ52

SA_DQ51

SA_DQ50

SA_DQ49

SA_DQ48

SA_DQ47

SA_DQ46

SA_DQ44

SA_DQ43

SA_DQ42

SA_DQ41

SA_DQ40

SA_DQ39

SA_DQ38

SA_DQ37

SA_DQ36

SA_DQ34 SA_DQ35

SA_DQ33

SA_DQ32

SA_DQ31

SA_DQ30

SA_DQ28 SA_DQ29

SA_DQ27

SA_DQ26

SA_DQ25

SA_DQ24

SA_DQ23

SA_DQ22

SA_DQ21

SA_DQ20

SA_DQ19

SA_DQ18

SA_DQ17

SA_DQ16

SA_DQ15

SA_DQ13

SA_DQ11 SA_DQ12

SA_DQ10

SA_DQ9

SA_DQ8

SA_DQ7

SA_DQ5

SA_DQ3

SA_BS1

SA_BS0

SA_DQ45

SA_DM0 SA_DM1

SA_DM3

SA_DM2

SA_DM5

SA_DM4

SA_DM7

SA_DM6

SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7

SA_DQS1*

SA_DQS0*

SA_DQS2*

SA_DQS4*

SA_DQS3*

SA_DQS5* SA_DQS6* SA_DQS7*

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7

SA_MA9

SA_MA8

SA_MA10 SA_MA11 SA_MA12 SA_MA13

SA_RAS*

SA_RCVEN*

SA_WE*

DDR SYSTEM MEMORY A

(4 OF 10)

SB_DQ2

SB_DQ1

SB_DQ5

SB_DM0

SB_DQ0

SB_DQ4

SB_DQ6 SB_DQ7

SB_CAS*

SB_BS2

SB_BS0 SB_BS1

SB_DQ63

SB_DQ62

SB_DQ59

SB_DQ58

SB_DQ56

SB_DQ55

SB_DQ54

SB_DQ53

SB_DQ52

SB_DQ51

SB_DQ50

SB_DQ49

SB_DQ48

SB_DQ47

SB_DQ45 SB_DQ46

SB_DQ44

SB_DQ43

SB_DQ42

SB_DQ41

SB_DQ40

SB_DQ39

SB_DQ38

SB_DQ37

SB_DQ36

SB_DQ34 SB_DQ35

SB_DQ33

SB_DQ32

SB_DQ31

SB_DQ30

SB_DQ28 SB_DQ29

SB_DQ27

SB_DQ26

SB_DQ25

SB_DQ24

SB_DQ23

SB_DQ22

SB_DQ21

SB_DQ20

SB_DQ19

SB_DQ18

SB_DQ17

SB_DQ16

SB_DQ15

SB_DQ14

SB_DQ13

SB_DQ11 SB_DQ12

SB_DQ10

SB_DQ9

SB_DQ8

SB_DQ3

SB_DQ57

SB_DQ61

SB_DQ60

SB_WE*

SB_RCVEN*

SB_RAS*

SB_MA13

SB_MA12

SB_MA11

SB_MA10

SB_MA8 SB_MA9

SB_MA7

SB_MA6

SB_MA5

SB_MA4

SB_MA3

SB_MA2

SB_MA1

SB_MA0

SB_DQS7*

SB_DQS6*

SB_DQS5*

SB_DQS3* SB_DQS4*

SB_DQS2*

SB_DQS0* SB_DQS1*

SB_DQS7

SB_DQS6

SB_DQS5

SB_DQS4

SB_DQS3

SB_DQS2

SB_DQS1

SB_DQS0

SB_DM6 SB_DM7

SB_DM4 SB_DM5

SB_DM2 SB_DM3

SB_DM1

(5 OF 10)

DDR SYSTEM MEMORY B

BI

OUT OUT OUT

BI

OUT

BI

OUT

BI

BI BI BI BI BI BI BI BI BI BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

31 81

32 81

31 81 32 81

32 81

31 81

32 81

31 81

32 81

31 81

32 81

31 81

32 81

31 81

32 81

32 33 81

31 81

32 33 81

31 81

32 33 81

32 81

31 81

32 81

31 81

32 81

32 33 81

31 81

32 33 81

FCBGA

CRESTLINE

OMIT

FCBGA

CRESTLINE

OMIT

31 81

31 33 81

31 81

31 33 81

31 81

31 33 81

31 81

31 33 81

31 81

SYNC_DATE=03/16/2007

SYNC_MASTER=T9_NOME

NB DDR2 Interfaces

051-7225

A.0.0

8817

MEM_A_DQ<63>

MEM_A_DQ<62>

MEM_A_DQ<61>

MEM_A_DQ<60>

MEM_A_DQ<59>

MEM_A_DQ<58>

MEM_A_DQ<57>

MEM_A_DQ<56>

MEM_A_DQ<55>

MEM_A_DQ<54>

MEM_A_DQ<53>

MEM_A_DQ<52>

MEM_A_DQ<51>

MEM_A_DQ<50>

MEM_A_DQ<49>

MEM_A_DQ<48>

MEM_A_DQ<47>

MEM_A_DQ<46>

MEM_A_DQ<45>

MEM_A_DQ<44>

MEM_A_DQ<43>

MEM_A_DQ<42>

MEM_A_DQ<41>

MEM_A_DQ<40>

MEM_A_DQ<39>

MEM_A_DQ<38>

MEM_A_DQ<37>

MEM_A_DQ<36>

MEM_A_DQ<34>

MEM_A_DQ<33>

MEM_A_DQ<32>

MEM_A_DQ<31>

MEM_A_DQ<30>

MEM_A_DQ<29>

MEM_A_DQ<28>

MEM_A_DQ<27>

MEM_A_DQ<26>

MEM_A_DQ<25>

MEM_A_DQ<24>

MEM_A_DQ<23>

MEM_A_DQ<22>

MEM_A_DQ<21>

MEM_A_DQ<20>

MEM_A_DQ<19>

MEM_A_DQ<18>

MEM_A_DQ<17>

MEM_A_DQ<16>

MEM_A_DQ<15>

MEM_A_DQ<14>

MEM_A_DQ<13>

MEM_A_DQ<12>

MEM_A_DQ<11>

MEM_A_DQ<10>

MEM_A_DQ<9>

MEM_A_WE_L

MEM_A_RAS_L

MEM_A_A<13>

MEM_A_A<12>

MEM_A_A<11>

MEM_A_A<10>

MEM_A_A<8> MEM_A_A<9>

MEM_A_A<7>

MEM_A_A<6>

MEM_A_A<5>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_A<2>

MEM_A_A<1>

MEM_A_A<0>

MEM_A_DQS_N<7>

MEM_A_DQS_N<6>

MEM_A_DQS_N<5>

MEM_A_DQS_N<3> MEM_A_DQS_N<4>

MEM_A_DQS_N<2>

MEM_A_DQS_N<0> MEM_A_DQS_N<1>

MEM_A_DQS_P<7>

MEM_A_DQS_P<6>

MEM_A_DQS_P<5>

MEM_A_DQS_P<4>

MEM_A_DQS_P<3>

MEM_A_DQS_P<2>

MEM_A_DQS_P<1>

MEM_A_DQS_P<0>

MEM_A_DM<6> MEM_A_DM<7>

MEM_A_DM<4> MEM_A_DM<5>

MEM_A_DM<2> MEM_A_DM<3>

MEM_A_DM<1>

MEM_A_DM<0>

MEM_A_BS<0> MEM_A_BS<1>

MEM_A_DQ<3>

MEM_A_DQ<5>

MEM_A_DQ<7> MEM_A_DQ<8>

MEM_A_BS<2> MEM_A_CAS_L

MEM_A_DQ<6>

MEM_A_DQ<4>

MEM_A_DQ<2>

MEM_A_DQ<1>

MEM_A_DQ<0>

MEM_B_DQ<63>

MEM_B_DQ<62>

MEM_B_DQ<61>

MEM_B_DQ<60>

MEM_B_DQ<59>

MEM_B_DQ<58>

MEM_B_DQ<57>

MEM_B_DQ<56>

MEM_B_DQ<55>

MEM_B_DQ<54>

MEM_B_DQ<53>

MEM_B_DQ<52>

MEM_B_DQ<51>

MEM_B_DQ<50>

MEM_B_DQ<49>

MEM_B_DQ<48>

MEM_B_DQ<47>

MEM_B_DQ<46>

MEM_B_DQ<45>

MEM_B_DQ<44>

MEM_B_DQ<43>

MEM_B_DQ<42>

MEM_B_DQ<41>

MEM_B_DQ<40>

MEM_B_DQ<38>

MEM_B_DQ<37>

MEM_B_DQ<36>

MEM_B_DQ<35>

MEM_B_DQ<34>

MEM_B_DQ<33>

MEM_B_DQ<32>

MEM_B_DQ<31>

MEM_B_DQ<30>

MEM_B_DQ<29>

MEM_B_DQ<28>

MEM_B_DQ<27>

MEM_B_DQ<26>

MEM_B_DQ<25>

MEM_B_DQ<24>

MEM_B_DQ<23>

MEM_B_DQ<22>

MEM_B_DQ<21>

MEM_B_DQ<20>

MEM_B_DQ<19>

MEM_B_DQ<18>

MEM_B_DQ<17>

MEM_B_DQ<16>

MEM_B_DQ<15>

MEM_B_DQ<14>

MEM_B_DQ<13>

MEM_B_DQ<12>

MEM_B_DQ<11>

MEM_B_DQ<10>

MEM_B_DQ<9>

MEM_B_WE_L

MEM_B_A<13>

MEM_B_RAS_L

MEM_B_A<12>

MEM_B_A<11>

MEM_B_A<10>

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<7>

MEM_B_A<6>

MEM_B_A<5>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_A<2>

MEM_B_A<1>

MEM_B_A<0>

MEM_B_DQS_N<7>

MEM_B_DQS_N<5> MEM_B_DQS_N<6>

MEM_B_DQS_N<4>

MEM_B_DQS_N<2> MEM_B_DQS_N<3>

MEM_B_DQS_N<0>

MEM_B_DQS_P<7>

MEM_B_DQS_N<1>

MEM_B_DQS_P<5> MEM_B_DQS_P<6>

MEM_B_DQS_P<2> MEM_B_DQS_P<3> MEM_B_DQS_P<4>

MEM_B_DQS_P<0> MEM_B_DQS_P<1>

MEM_B_DM<7>

MEM_B_DM<6>

MEM_B_DM<5>

MEM_B_DM<4>

MEM_B_DM<3>

MEM_B_DQ<8>

MEM_B_DQ<7>

MEM_B_DQ<6>

MEM_B_DQ<5>

MEM_B_DQ<4>

MEM_B_DQ<3>

MEM_B_DQ<2>

MEM_B_DQ<1>

MEM_B_DQ<0>

MEM_B_DM<2>

MEM_B_DM<1>

MEM_B_CAS_L

MEM_B_DM<0>

MEM_B_BS<2>

MEM_B_BS<1>

MEM_B_BS<0>

MEM_B_DQ<39>

TP_MEM_B_RCVEN_LTP_MEM_A_RCVEN_L

MEM_A_DQ<35>

U1400

BB19 BK19 BF29

BL17

AT45 BD44 BD42 AW38 AW13 BG8 AY5 AN6

AR43 AW44

BG47 BJ45 BB47 BG50 BH49 BE45 AW43 BE44 BG42 BE40

BA45

BF44 BH45 BG40 BF40 AR40 AW40 AT39 AW36 AW41 AY41

AY46

AV38 AT38 AV13 AT13 AW11 AV11 AU15 AT11 BA13 BA11

AR41

BE10 BD10

BD8 AY9

BG10

AW9 BD7 BB9 BB5 AY7

AR45

AT5 AT7 AY6 BB7 AR5 AR8 AR9 AN3 AM8

AN10

AT42

AT9 AN9 AM9

AN11

AW47 BB45 BF48

AT46

AT47

BE48

BD47

BB43

BC41

BC37

BA37

BB16

BA16

BH6

BH7

BB2

BC1

AP3

AP2

BJ19 BD20

BC19 BE28 BG30 BJ16

BK27 BH28 BL24 BK28 BJ27 BJ25 BL28 BA28

BE18 AY20

BA19

U1400

AY17 BG18 BG36

BE17

AR50 BD49 BK45 BL39 BH12 BJ7 BF3 AW2

AP49 AR51

BA49 BE50 BA51 AY49 BF50 BF49 BJ50 BJ44 BJ43 BL43

AW50

BK47 BK49 BK43 BK42 BJ41 BL41 BJ37 BJ36 BK41 BJ40

AW51

BL35 BK37 BK13 BE11 BK11 BC11 BC13 BE12 BC12 BG12

AN51

BJ10

BL9 BK5 BL5 BK9

BK10

BJ8 BJ6 BF4 BH5

AN50

BG1 BC2 BK3 BE4 BD3 BJ2 BA3 BB3 AR1 AT3

AV50

AY2 AY3 AU2 AT2

AV49 BA50 BB50

AT50

AU50

BD50

BC50

BK46

BL45

BK39

BK38

BJ12

BK12

BL7

BK7

BE2

BF2

AV2

AV3

BC18 BG28

BG17 BE37 BA39 BG13

BG25 AW17 BF25 BE25 BA29 BC28 AY28 BD37

AV16 AY18

BC17

VCC_SM20

VCC_AXG_NCTF42

VCC_SM9 VCC_SM10

VCC_SM17

VCC_SM16

VCC3

VCC_SM5

VCC_SM8

VCC_AXG_NCTF1 VCC_AXG_NCTF2 VCC_AXG_NCTF3 VCC_AXG_NCTF4 VCC_AXG_NCTF5 VCC_AXG_NCTF6

VCC_AXG_NCTF8

VCC_AXG_NCTF7

VCC_AXG_NCTF10

VCC_AXG_NCTF9

VCC_AXG_NCTF11 VCC_AXG_NCTF12 VCC_AXG_NCTF13 VCC_AXG_NCTF14 VCC_AXG_NCTF15 VCC_AXG_NCTF16

VCC_AXG_NCTF18

VCC_AXG_NCTF17

VCC_AXG_NCTF20

VCC_AXG_NCTF19

VCC_AXG_NCTF21 VCC_AXG_NCTF22

VCC_AXG_NCTF25 VCC_AXG_NCTF26

VCC_AXG_NCTF28

VCC_AXG_NCTF27

VCC_AXG_NCTF29 VCC_AXG_NCTF20 VCC_AXG_NCTF31 VCC_AXG_NCTF32 VCC_AXG_NCTF33 VCC_AXG_NCTF34 VCC_AXG_NCTF35 VCC_AXG_NCTF36

VCC_AXG_NCTF38

VCC_AXG_NCTF37

VCC_AXG_NCTF40

VCC_AXG_NCTF39

VCC_AXG_NCTF41

VCC_AXG_NCTF43 VCC_AXG_NCTF44 VCC_AXG_NCTF45 VCC_AXG_NCTF46

VCC_AXG_NCTF48

VCC_AXG_NCTF47

VCC_AXG_NCTF49 VCC_AXG_NCTF50 VCC_AXG_NCTF51

VCC_AXG_NCTF55

VCC_AXG_NCTF58

VCC_AXG_NCTF57

VCC_AXG_NCTF59

VCC_AXG_NCTF61

VCC_AXG_NCTF60

VCC_AXG_NCTF62 VCC_AXG_NCTF63 VCC_AXG_NCTF64

VCC_AXG_NCTF66

VCC_AXG_NCTF65

VCC_AXG_NCTF67 VCC_AXG_NCTF68 VCC_AXG_NCTF69

VCC_AXG_NCTF71

VCC_AXG_NCTF70

VCC_AXG_NCTF72 VCC_AXG_NCTF73 VCC_AXG_NCTF74

VCC_AXG_NCTF76

VCC_AXG_NCTF75

VCC_AXG_NCTF77 VCC_AXG_NCTF78 VCC_AXG_NCTF79

VCC_AXG_NCTF81

VCC_AXG_NCTF80

VCC_AXG_NCTF82 VCC_AXG_NCTF83

VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7

VCC_AXG_NCTF56

VCC_AXG_NCTF54

VCC_AXG_NCTF53

VCC_AXG_NCTF52

VCC_AXG1 VCC_AXG2 VCC_AXG3 VCC_AXG4 VCC_AXG5 VCC_AXG6 VCC_AXG7 VCC_AXG8 VCC_AXG9 VCC_AXG10 VCC_AXG11 VCC_AXG12 VCC_AXG13 VCC_AXG14 VCC_AXG15 VCC_AXG16 VCC_AXG17 VCC_AXG18 VCC_AXG19 VCC_AXG20 VCC_AXG21 VCC_AXG22 VCC_AXG23 VCC_AXG24 VCC_AXG25 VCC_AXG26 VCC_AXG27 VCC_AXG28 VCC_AXG29 VCC_AXG30 VCC_AXG31 VCC_AXG32 VCC_AXG33 VCC_AXG34

VCC_SM1 VCC_SM2 VCC_SM3 VCC_SM4

VCC_SM6 VCC_SM7

VCC_SM11 VCC_SM12 VCC_SM13 VCC_SM14 VCC_SM15

VCC_SM18 VCC_SM19

VCC_SM21 VCC_SM22 VCC_SM23

VCC_SM26 VCC_SM27 VCC_SM28 VCC_SM29 VCC_SM30 VCC_SM31 VCC_SM32 VCC_SM33 VCC_SM34 VCC_SM35 VCC_SM36

VCC_SM25

VCC_SM24

VCC1 VCC2

VCC7 VCC8 VCC9 VCC10 VCC11 VCC12

VCC13

VCC_AXG_NCTF24

VCC_AXG_NCTF23

VCC6

VCC5 VCC4

VCC GFX

VCC SM

VCC SM LF

(6 OF 10)

VCC CORE

POWER

VCC GFX NCTF

VCC_NCTF49

VCC_NCTF15

VCC_NCTF2

VCC_NCTF10

VCC_AXM7

VCC_AXM5

VCC_AXM4

VCC_AXM3

VCC_AXM2

VCC_AXM1

VSS_SCB6

VSS_SCB5

VSS_SCB4

VSS_SCB3

VSS_SCB2

VSS_SCB1

VCC_NCTF11 VCC_NCTF12 VCC_NCTF13 VCC_NCTF14

VSS_NCTF21

VSS_NCTF20

VSS_NCTF19

VSS_NCTF18

VSS_NCTF17

VSS_NCTF16

VSS_NCTF15

VSS_NCTF14

VSS_NCTF12

VSS_NCTF11

VSS_NCTF13

VSS_NCTF10

VSS_NCTF9

VSS_NCTF8

VSS_NCTF7

VSS_NCTF6

VSS_NCTF5

VSS_NCTF4

VSS_NCTF3

VSS_NCTF2

VSS_NCTF1

VCC_NCTF22

VCC_NCTF27

VCC_NCTF50

VCC_NCTF47 VCC_NCTF48

VCC_NCTF44

VCC_NCTF43

VCC_NCTF39 VCC_NCTF40

VCC_NCTF38

VCC_NCTF37

VCC_NCTF34 VCC_NCTF35

VCC_NCTF33

VCC_NCTF32

VCC_NCTF31

VCC_NCTF29

VCC_NCTF28

VCC_NCTF26

VCC_NCTF24 VCC_NCTF25

VCC_NCTF23

VCC_NCTF21

VCC_NCTF18 VCC_NCTF19

VCC_NCTF16 VCC_NCTF17

VCC_NCTF3 VCC_NCTF4

VCC_NCTF41 VCC_NCTF42

VCC_NCTF45 VCC_NCTF46

VCC_AXM6

VCC_AXM_NCTF1 VCC_AXM_NCTF2 VCC_AXM_NCTF3 VCC_AXM_NCTF4 VCC_AXM_NCTF5 VCC_AXM_NCTF6 VCC_AXM_NCTF7 VCC_AXM_NCTF8 VCC_AXM_NCTF9 VCC_AXM_NCTF10 VCC_AXM_NCTF11 VCC_AXM_NCTF12 VCC_AXM_NCTF13 VCC_AXM_NCTF14 VCC_AXM_NCTF15 VCC_AXM_NCTF16 VCC_AXM_NCTF17 VCC_AXM_NCTF18 VCC_AXM_NCTF19

VCC_NCTF8

VCC_NCTF20

VCC_NCTF1

VCC_NCTF5 VCC_NCTF6 VCC_NCTF7

VCC_NCTF36

VCC_NCTF30

VCC_NCTF9

VCC AXM NCTF

VCC NCTF

VSS SCBVCC AXM

VSS NCTF

(7 OF 10)

POWER

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Current numbers from Crestline EDS, doc #21749.

NCTF balls are Not Critical To Function

These connections can break without

impacting part performance.

5 mA (standby)

7700 mA (Int Graphics)

1310 mA (Ext Graphics) 1573 mA (Int Graphics)

540 mA

3300 mA (2 ch, 667MHz) 2700 mA (2 ch, 533MHz) 1700 mA (1 ch, 667MHz) 1395 mA (1 ch, 533MHz)

FCBGA

CRESTLINE

OMIT

FCBGA

CRESTLINE

OMIT

20%

CERM

10V

0.1uF

402

20%

CERM

10V

0.1uF

402

20%

6.3V

0.22UF

X5R 402

20%

6.3V

0.22UF

X5R 402

6.3V

1uF

CERM

10%

402

CERM-X5R

6.3V

0.47UF

10%

402

6.3V

1uF

CERM

10%

402

SYNC_MASTER=T9_NOME

SYNC_DATE=03/16/2007

NB Power 1

051-7225

A.0.0

8818

=PP1V8_S3M_MEM_NB

=PPVCORE_S0_NB_GFX

=PPVCORE_S0_NB

=PPVCORE_S0_NB_GFX

NB_VCCSM_LF6

NB_VCCSM_LF4

NB_VCCSM_LF3

NB_VCCSM_LF2

NB_VCCSM_LF1

=PP1V05_S0M_NB_VCCAXM

=PPVCORE_S0_NB

NB_VCCSM_LF7

NB_VCCSM_LF5

=PP1V05_S0M_NB_VCCAXM

U1400

AT35

AH31 AH29 AF32

R30

AT34 AH28

AC31

AC32

AK32 AJ31 AJ28 AH32

R20

AB21 AB24 AB29 AC20 AC21 AC23 AC24 AC26 AC28 AC29

T14

AD20 AD23 AD24 AD28 AF21 AF26 AA31 AH20 AH21 AH23

W13

AH24 AH26 AD31 AJ20 AN14

W14

Y12 AA20 AA23 AA26 AA28

T17

U17 U19 U20 U21 U23 U26 V16 V17 V19 V20

T18

V21 V23 V24 Y15 Y16 Y17 Y19 Y20 Y21 Y23

T19

Y24 Y26 Y28 Y29 AA16 AA17 AB16 AB19 AC16 AC17

T21

AC19 AD15 AD16 AD17 AF16 AF19 AH15 AH16 AH17 AH19

T22

AJ16 AJ17 AJ19 AK16 AK19 AL16 AL17 AL19 AL20 AL21

T23

AL23 AM15 AM16 AM19 AM20 AM21 AM23 AP15 AP16 AP17

T25

AP19 AP20 AP21 AP23 AP24 AR20 AR21 AR23 AR24 AR26

U15

V26 V28 V29 Y31

U16

AU32

BA35 BB33 BC32 BC33 BC35 BD32 BD35 BE32 BE33 BE35

AU33

BF33 BF34 BG32 BG33 BG35 BH32 BH34 BH35 BJ32 BJ33

AU35

BJ34 BK32 BK33 BK34 BK35 BL33 AU30

AV33 AW33 AW35 AY35 BA32 BA33

AW45 BC39 BE39 BD17 BD4 AW8 AT6

U1400

AT33 AT31 AK29 AK24 AK23 AJ26 AJ23

AL24

AP29 AP31 AP32 AP33 AL29 AL31 AL32 AR31 AR32 AR33

AL26 AL28 AM26 AM28 AM29 AM31 AM32 AM33

AB33

AF36 AH33 AH35 AH36 AH37 AJ33 AJ35 AK33 AK35 AK36

AB36

AK37 AD33 AJ36 AM35 AL33 AL35 AA33 AA35 AA36 AP35

AB37

AP36 AR35 AR36

Y32 Y33 Y35 Y36 Y37 T30 T34

AC33

T35 U29 U31 U32 U33 U35 U36 V32 V33 V36

AC35

V37

AC36 AD35 AD36 AF33

T27

AD19 AD37 AF17 AF35 AK17 AM17 AM24 AP26 AP28 AR15

T37

AR19 AR28

U24 U28 V31 V35 AA19 AB17 AB35

A3 B2 C1 BL1 BL51 A51

C1806

1

2

C1807

1

2

C1804

1

2

C1805

1

2

C1802

1

2

C1803

1

2

C1801

1

2

22

21

22 21

22

21

16

18 18

18

8

8 8

8

VCCA_CRT_DAC1

VTT7 VTT8

VCC_AXD_NCTF

VCCD_CRT

VCC_RXR_DMI1 VCC_RXR_DMI2

VTT1

VCCA_SM_CK2 VCC_TX_LVDS

VCC_HV2

VCC_PEG1 VCC_PEG2 VCC_PEG3

VCC_AXF2

VCC_AXD1 VCC_AXD2

VSSA_LVDS

VCCA_SM5

VCCA_PEG_PLL

VCCA_MPLL

VCCA_HPLL VTT16

VTT17

VTT15

VCCD_LVDS2

VCCD_LVDS1

VCCD_PEG_PLL

VCCD_HPLL

VCCD_QDAC

VCCD_TVDAC

VCCA_TVC_DAC1 VCCA_TVC_DAC2

VCCA_TVB_DAC2

VCCA_TVB_DAC1

VCCA_TVA_DAC2

VCCA_TVA_DAC1

VCCA_SM_CK1

VCCA_SM2

VCCA_SM1

VCCA_SM_NCTF2

VCCA_SM_NCTF1

VCCA_SM11

VCCA_SM10

VCCA_SM9

VCCA_SM8

VCCA_SM7

VCCA_SM4

VCCA_SM3

VSSA_PEG_BG

VCCA_PEG_BG

VCCA_LVDS

VCCA_DPLLB

VCCA_DPLLA

VSSA_DAC_BG

VCCA_DAC_BG

VCC_AXF3

VCC_HV1

VCC_PEG5

VTTLF1

VTTLF3

VTTLF2

VCC_PEG4

VCC_SM_CK3

VCC_SM_CK2

VCC_SM_CK1

VCC_SM_CK4

VCC_DMI

VCC_AXF1

VTT22

VCC_AXD6

VCC_AXD5

VCC_AXD4

VCC_AXD3

VTT19

VTT2

VTT6

VTT5

VTT11

VTT10

VTT9

VTT13

VTT12

VTT14

VTT18

VTT21

VTT20

VTT3 VTT4

VCCA_CRT_DAC2

VCC_SYNC

CRT

AXD

PEG

HV

AXF

VTTLF

VTT

SM CK

DMI

TV/CRT

D

LVDS

A SMA CK

CRT A LVDS

A PEG

PLL

(8 OF 10)

POWER

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

100 mA

200 mA

5 mA

50 mA

100 mA

10 mA

40 mA

60 mA

250 mA

150 mA

5 mA

S0 or S3M is acceptable

TBD mA @ 1067MHz FSB (1.25V)

150 mA

770 mA @ 667MHz FSB (1.05V)

1260 mA

260 mA

0.4 mA

80 mA

30 mA

60 mA

100 mA

35 mA

850 mA @ 800MHz FSB (1.05V)

495 mA

515 mA

Current numbers from Crestline EDS, doc #21749.

640 mA (667MHz DDR) 550 mA (533MHz DDR)

6.3V 402

CERM-X5R

10%

0.47UF

402

CERM-X5R

6.3V

10%

0.47UF

402

CERM-X5R

6.3V

10%

0.47UF

CRESTLINE

FCBGA

OMIT

SYNC_MASTER=T9_NOME

SYNC_DATE=03/16/2007

NB Power 2

19 88

A.0.0

051-7225

=PP3V3_S0_NB_VCCA_PEG_BG

PP1V25_S0M_NB_VCCA_SM

PP1V8_S3M_NB_VCCSMCK

PP1V25_S0_NB_PEGPLL

PP1V25_S0M_NB_VCCA_SM_CK

=PP3V3_S0_NB_VCCSYNC

PP3V3_S0_NB_VCCA_CRTDAC

PP1V8_S0_NB_VCCTXLVDS

=PP1V25R1V05_S0_NB_VTT

PP3V3_S0_NB_VCCA_TVDACB

PP1V25_S0_NB_VCCA_DPLLB

PP3V3_S0_NB_VCCA_TVDACC

PP1V25_S0M_NB_VCCAXD

PP1V25_S0_NB_VCCAXF

PP1V05_S0_NB_VCCRXRDMI

=PP3V3_S0_NB_VCCHV

PP1V05_S0_NB_VCCPEG

PP1V8_S0_NB_VCCTXLVDS

=GND_NB_VSSA_PEG_BG

=GND_NB_VSSA_DAC_BG

=PP1V25_S0_NB_VCCDMI

NB_VTTLF_CAP3

NB_VTTLF_CAP1

PP1V25_S0M_NB_VCCA_MPLL

PP3V3_S0_NB_VCCA_DAC_BG

=GND_NB_VSSA_LVDS

=PP1V25_S0M_NB_VCCD_HPLL

PP1V5_S0_NB_VCCD_QDAC

PP1V5_S0_NB_VCCD_TVDAC

=PP1V5_S0_NB_VCCD_CRT

PP3V3_S0_NB_VCCA_TVDACA

PP1V25_S0M_NB_VCCA_HPLL

PP1V25_S0_NB_VCCA_DPLLA

=PP1V8_S0_NB_VCCD_LVDS

NB_VTTLF_CAP2

U1400

AT23 AU28 AU24 AT29 AT25 AT30

AR29

B23 B21 A21

AJ50

C40 B40

AD51 W50 W51 V49 V50

AH50 AH51

BK24 BK23 BJ24 BJ23

J32

A43

A33 B33

A30

B49

H49

AL2

A41

AM2

K50

U51

AW18

AT18 AT17

AV19 AU19 AU18 AU17

AT22 AT21 AT19

BC29 BB29

AR17 AR16

C25 B25 C27 B27 B28 A28

M32

AN2

J41 H42

U48

N28

L29

B32

B41

K49

U13

U1 T13 T11 T10 T9 T7 T6 T5 T3 T2

U12

R3 R2 R1

U11 U9 U8 U7 U5 U3 U2

A7 F2 AH1

C1911

1

2

C1913

1

2

C1912

1

2

21

22

21

16

21

22

21

8

21

22

19

8

22

16

21

8

15

19

21

22

8

21

22

21

22

21

22

VSS198VSS99

VSS197VSS98

VSS196VSS97

VSS195VSS96

VSS194VSS95

VSS193VSS94

VSS192VSS93

VSS191VSS92

VSS190VSS91

VSS189VSS90

VSS188VSS89

VSS187VSS88

VSS186VSS87

VSS185VSS86

VSS184VSS85

VSS183VSS84

VSS182VSS83

VSS181VSS82

VSS180VSS81

VSS179VSS80

VSS178VSS79

VSS177VSS78

VSS176VSS77

VSS175VSS76

VSS174VSS75

VSS173VSS74

VSS172VSS73

VSS171VSS72

VSS170VSS71

VSS169VSS70

VSS168VSS69

VSS167VSS68

VSS166VSS67

VSS165VSS66

VSS164VSS65

VSS163VSS64

VSS162VSS63

VSS161VSS62

VSS160VSS61

VSS159VSS60

VSS158VSS59

VSS157VSS58

VSS156VSS57

VSS155VSS56

VSS154VSS55

VSS153VSS54

VSS152VSS53

VSS151VSS52

VSS150VSS51

VSS149VSS50

VSS148VSS49

VSS147VSS48

VSS146VSS47

VSS145VSS46

VSS144VSS45

VSS143VSS44

VSS142VSS43

VSS141VSS42

VSS140VSS41

VSS139VSS40

VSS138VSS39

VSS137VSS38

VSS136VSS37

VSS135VSS36

VSS134VSS35

VSS133VSS34

VSS132VSS33

VSS131VSS32

VSS130VSS31

VSS129VSS30

VSS128VSS29

VSS127VSS28

VSS126VSS27

VSS125VSS26

VSS124VSS25

VSS123VSS24

VSS122VSS23

VSS121VSS22

VSS120VSS21

VSS119VSS20

VSS118VSS19

VSS117

VSS116VSS17

VSS115VSS16

VSS114VSS15

VSS113VSS14

VSS112VSS13

VSS111VSS12

VSS110VSS11

VSS109VSS10

VSS108

VSS9

VSS107VSS8

VSS106VSS7

VSS105VSS6

VSS104VSS5

VSS103VSS4

VSS102

VSS101

VSS100

VSS1

VSS18

VSS2 VSS3

VSS

(9 OF 10)

VSS202

VSS289 VSS290 VSS291 VSS292

VSS295

VSS199 VSS287 VSS200 VSS288 VSS201

VSS203 VSS204

VSS293 VSS294

VSS208 VSS296 VSS209 VSS297 VSS210 VSS298 VSS211 VSS299 VSS212 VSS300 VSS213 VSS301 VSS214 VSS215 VSS216 VSS302 VSS217 VSS218 VSS219 VSS303 VSS220 VSS221 VSS222 VSS304 VSS223 VSS224 VSS225 VSS305 VSS226 VSS227 VSS228 VSS229 VSS306 VSS230 VSS307 VSS231 VSS308 VSS232 VSS309 VSS233 VSS310 VSS234 VSS311 VSS235 VSS312 VSS236 VSS313 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243

VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285 VSS286

VSS207

VSS206

VSS205

(10 OF 10)

VSS

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

TDE_SENSE

TDE_FORCE

TDB_FORCE

alias these nets directly to GND.

Mainly for investigation. If not used,

NOTE: TDB = _N

TDB_SENSE

Crestline Thermal Diode Pins

NOTE: TDE = _P

CRESTLINE

OMIT

FCBGA

CRESTLINE

OMIT

FCBGA

SYNC_DATE=03/16/2007

SYNC_MASTER=T9_NOME

NB Grounds

20 88

A.0.0

051-7225

=NB_TDE_SENSE

=NB_TDE_FORCE

=NB_TDB_FORCE

=NB_TDB_SENSE

U1400

A13

AB26

AW24 AW29 AW32 AW5 AW7 AY10 AY24 AY37 AY42 AY43

AB28 AY45

AY47 AY50 B10 B20 B24 B29 B30 B35 B38

AB31

B43 B46 B5 B8 BA1 BA17 BA18 BA2 BA24 BB12

AC10

BB25 BB40 BB44 BB49 BB8 BC16 BC24 BC25 BC36 BC40

AC13

BC51 BD13 BD2 BD28 BD45 BD48 BD5 BE1 BE19 BE23

AC3

BE30 BE42 BE51 BE8 BF12 BF16 BF36 BG19 BG2 BG24

AC39

BG29 BG39 BG48 BG5 BG51 BH17 BH30 BH44 BH46 BH8

AC43

BJ11 BJ13 BJ38 BJ4 BJ42 BJ46 BK15 BK17 BK25 BK29

AC47

BK36 BK40 BK44 BK6 BK8 BL11 BL13 BL19 BL22 BL37

AD1

BL47 C12 C16 C19 C28 C29 C33 C36 C41

A15

AD21 AD26 AD29

AD3 AD41 AD45 AD49

AD5 AD50

AD8

A17

AE10 AE14

AE6 AF20 AF23 AF24 AF31

AG2 AG38 AG43

A24

AG47 AG50

AH3 AH40 AH41

AH7

AH9 AJ11 AJ13 AJ21

AA21

AJ24 AJ29 AJ32 AJ43 AJ45 AJ49 AK20 AK21 AK26 AK28

AA24

AK31 AK51

AL1 AM11 AM13

AM3

AM4 AM41 AM45

AN1

AA29

AN38 AN39 AN43

AN5

AN7

AP4 AP48 AP50 AR11

AR2

AB20

AR39 AR44 AR47

AR7 AT10 AT14 AT41 AT49

AU1 AU23

AB23

AU29

AU3 AU36 AU49 AU51 AV39 AV48

AW1 AW12 AW16

U1400

C46 C50

C7 D13 D24

D3 D32 D39 D45 D49 E10 E16 E24 E28 E32 E47 F19 F36

F4 F40 F50

G1 G13 G16 G19 G24 G28 G29 G33 G42 G45 G48

G8 H24 H28

H4 H45 J11 J16

J2 J24 J28 J33 J35 J39

K12 K47

K8

L1 L17 L20 L24 L28

L3 L33 L49 M28 M42 M46 M49

M5 M50

M9 N11 N14 N17 N29 N32 N36 N39 N44 N49

N7 P19

P2 P23

P3 P50 R49 T39 T43 T47 U41 U45 U50

V2

V3

W11 W39 W43 W47 W5 W7 Y13 Y2 Y41 Y45 Y49 Y5 Y50 Y11 P29

T29

T31

T33

R28

AA32 AB32 AD32 AF28 AF29 AT27 AV25 H50

51

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

and DDR2 taps." (C2135)

Placeholder for 3.9nH, 1A, 32mOhm

GMCH Memory I/O Rail

GMCH FSB I/O Rail

850 mA (800MHz FSB)

Current numbers from Crestline EDS, doc #21749.

260 mA

1520 mA 1260 mA

495 mA495 mA

550 mA (533MHz DDR2)

640 mA (667MHz DDR2)

35 mA

0.4 mA

515 mA515 mA

585 mA (533MHz DDR2)

675 mA (667MHz DDR2)

770 mA (667MHz FSB)

3300 mA (2ch 667MHz) 2700 mA (2ch 533MHz) 1700 mA (1ch 667MHz) 1395 mA (1ch 533MHz) 5 mA (standby)

Layout Note: Route to caps, then GND

NOTE: This follower is redundant if VCORE is always 1.05V.

100 mA

200 mA 200 mA

GMCH ME Core Power

on opposite side.

be close to MCH

Layout Note:

on opposite side.

be close to MCH

450 mA

150 mA

50 mA

250 mA

100 mA

10uF caps should

Placeholder for 2.2nH, 1.4A, 17mOhm

Layout Note: Place L and C close to MCH

WF: "Place where LVDS

Layout Note: 10uF caps should

Placeholder for 5.6nH, 0.9A, 45mOhm max

100 mA

540 mA

WF: Matanzas has 2-pin 270uF bulk cap

1310mA (Ext Graphics)

1573mA (Int Graphics)

GMCH Core Power

0.47UF

CERM-X5R

10% 402

6.3V

PLACEMENT_NOTE=Place close to U1400

6.3V

20%

PLACEMENT_NOTE=Place close to U1400

2.2uF

603

CERM1

4.7uF

603

PLACEMENT_NOTE=Place close to U1400

CERM

20%

6.3V

10V

0.1uF

402

CERM

20%

10V

0.1uF

402

CERM

20%

CRITICAL

D2T

20%

470UF

TANT

2.5V

10V

PLACEMENT_NOTE=Place in GMCH cavity

0.1uF

402

CERM

20%

0.22uF

402

20%

6.3V X5R

402

20%

6.3V X5R

0.22uF

22UF

CERM-X5R

20%

6.3V

805-3

CERM

PLACEMENT_NOTE=Place in GMCH cavity

10V

0.1uF

402

20%

PLACEMENT_NOTE=Place in GMCH cavity

10V

0.1uF

402

CERM

20%

4.7uF

603

PLACEMENT_NOTE=Place close to U1400

CERM

20%

6.3V

22UF

805-3

6.3V

20% CERM-X5R

PLACEMENT_NOTE=Place close to U1400

22UF

805-3

6.3V

20% CERM-X5R

PLACEMENT_NOTE=Place close to U1400

0.1uF

20% CERM

402

10V

0.51

MF-LF

1/16W

1%

402

10V

0.1uF

402

CERM

20%

402

1.1

1% 1/16W MF-LF

0805

FERR-220-OHM

10uF

20%

6.3V X5R 603

10V

0.1uF

402

CERM

20%

PLACEMENT_NOTE=Place C2180 by U1400.AN2

10V

0.1uF

402

CERM

20%

CRITICAL

D3L

POLY

6.3V

20%

330uF

CRITICAL

D3L

POLY

6.3V

20%

330uF

20%

603

10uF

6.3V X5R

CRITICAL

CASE-B2

2.5V

220UF

20%

POLY

91NH

1210

10V 402

CERM

20%

0.1uF

402

MF-LF

1%

1/16W

1.1

0805

1.0UH-220MA-0.12-OHM

603

10uF

20%

6.3V X5R

22UF

805-3

6.3V

20%

CERM-X5R

10V

0.1uF

402

CERM

20%

X5R

10V

10%

402

1uF

603

X5R

6.3V

20%

10uF

603

5%

MF-LF

1/10W

0

X5R

10V

10%

1uF

402

5% 1/10W MF-LF

0

603

NO STUFF

0603

FERR-120-OHM-0.2A

22UF

805-3

6.3V

20%

CERM-X5R

NO STUFF

CERM-X5R

22uF

20%

6.3V

805-3

4.7UF

6.3V

20% CERM

603

CRITICAL

D3L

POLY

6.3V

20%

330uF

X5R

1uF

402

10% 10V

0

5% 1/10W MF-LF

603

22UF

CERM-X5R

20%

6.3V

805-3

0

603

MF-LF

1/10W

5%

CERM

20%

402

0.1uF

10V

1/16W

1%

MF-LF

10

402

BAT54E3

SOT23

10

MF-LF

1%

1/16W

402

BAT54E3

SOT23

22UF

NO STUFF

6.3V

805-3

20%

CERM-X5R

NO STUFF

6.3V

20%

2.2uF

603

CERM1

0603

FERR-120-OHM-0.2A

PLACEMENT_NOTE=Place in GMCH cavity

10V

0.1uF

402

CERM

20%

603

10uF

20%

6.3V X5R

0.22uF

PLACEMENT_NOTE=Place in GMCH cavity

402

20%

6.3V X5R

0.22uF

PLACEMENT_NOTE=Place in GMCH cavity

402

20%

6.3V X5R

10V

PLACEMENT_NOTE=Place C2184 by U1400.AM2

0.1uF

402

CERM

20%

PLACEMENT_NOTE=Place C2182 by U1400.AL2

10V

0.1uF

402

CERM

20%

22UF

20%

6.3V

CERM-X5R

805-3

0603

FERR-120-OHM-0.2A

22UF

20%

6.3V

CERM-X5R

805-3

22UF

805-3

6.3V

20%

PLACEMENT_NOTE=Place in GMCH cavity

CERM-X5R

NB Standard Decoupling

SYNC_MASTER=T9_NOME

88

051-7225

A.0.0

21

SYNC_DATE=01/17/2007

=PP1V05_S0M_NB_VCCAXM

=PP1V25R1V05_S0_NB_VTT

PP1V8_S3M_NB_VCCSMCK

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.8V

=PP1V8_S3M_NB_VCC

=PP1V25_S0M_NB_VCC

MIN_NECK_WIDTH=0.2 MM

PP1V25_S0_NB_PEGPLL_RC

MIN_LINE_WIDTH=0.25 MM VOLTAGE=1.25V

PP1V25_S0M_NB_VCCA_SM

MIN_LINE_WIDTH=0.4 MM VOLTAGE=1.25V

MIN_NECK_WIDTH=0.2 MM

PP1V25_S0_NB_PEGPLL

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.25V

=PP1V25_S0_NB_PLL

VOLTAGE=1.25V

PP1V25_S0M_NB_VCCAXD

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

=PP1V05_S0_NB_PCIE

PP1V25_S0_NB_VCCAXF

MIN_LINE_WIDTH=0.4 MM VOLTAGE=1.25V

MIN_NECK_WIDTH=0.2 MM

=PP1V25_S0_NB_VCC

=PP1V05_S0_NB_FOLLOW

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

PP1V8_S3M_NB_VCCSMCK_RC

VOLTAGE=1.8V

=PP3V3_S0_NB_VCCA_PEG_BG

=PPVCORE_S0_NB_FOLLOW

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP3V3_S0_NBCORE_FOLLOW_R

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM VOLTAGE=3.3V

PP3V3_S0_NB1V05_FOLLOW_R

=PP3V3_S0_NB_FOLLOW

=PP1V25_S0M_NB_VCCD_HPLL

MIN_LINE_WIDTH=0.3 MM VOLTAGE=1.25V

MIN_NECK_WIDTH=0.2 MM

PP1V25_S0M_NB_MPLL_RC

=PP1V25_S0_NB_VCCDMI

=PP1V25_S0M_NB_PLL

MIN_LINE_WIDTH=0.3 MM VOLTAGE=1.25V

MIN_NECK_WIDTH=0.2 MM

PP1V25_S0M_NB_VCCA_MPLL

=PPVCORE_S0_NB

=PP3V3_S0_NB_VCCHV

=GND_NB_VSSA_PEG_BG

PP1V25_S0M_NB_VCCA_HPLL

MIN_LINE_WIDTH=0.25 MM VOLTAGE=1.25V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

PP1V05_S0_NB_VCCRXRDMI

MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

PP1V25_S0M_NB_VCCA_SM_CK

MIN_LINE_WIDTH=0.4 MM VOLTAGE=1.25V

MIN_NECK_WIDTH=0.2 MM

=PP1V8_S3M_MEM_NB

=PP1V25_S0M_NB_VCCA

MAKE_BASE=TRUE

PP1V05_S0_NB_VCCPEG

MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

MIN_LINE_WIDTH=0.5 MM

L2181

1 2

C2104

1

2

C2177

1

2

C2103

1

2

C2102

1

2

C2184

1

2

C2182

1

2

C2181

1

2

L2183

1 2

C2183

1

2

C2101

1

2

C2124

1

2

C2123

1

2

C2121

1

2

C2161

1

2

C2165

1

2

C2100

1

2 3

C2113

1

2

C2112

1

2

C2111

1

2

C2110

1

2

C2114

1

2

C2115

1

2

C2122

1

2

C2131

1

2

C2132

1

2

C2135

1

2

R2183

1

2

C2191

1

2

R2190

1

2

L2190

1 2

C2190

1

2

C2192

1

2

C2180

1

2

C2130

1

2

C2120

1

2

C2174

1

2

C2173

1

2

L2173

1 2

C2197

1

2

R2195

1

2

L2195

1 2

C2195

1

2

C2196

1

2

C2160

1

2

C2171

1

2

C2170

1

2

R2170

1 2

C2151

1

2

R2150

1 2

L2150

1 2

C2142

1

2

C2141

1

2

C2143

1

2

C2140

1

2

C2144

1

2

R2141

1 2

C2145

1

2

R2145

1 2

C2148

1

2

R2186

1 2

D2186

1 3

R2185

1 2

D2185

1 3

C2150

1

2

C2146

1

2

22

19

18

19

19 19

18

16

19

8

19

8

19

8

16

8

19

8

19

8

19

8

19

8

15

IN

OUT

EN

NR/FB

IN

GND

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

GMCH Graphics Core Power

VCCD_TVDAC also powers internal thermal sensors.

7700 mA

Vout = 1.25V (Factory Programmed)

Layout Note: Route to cap, then GND

65 mA

Crestline LVDS Support

260 mA 110 mA

150 mA

Current numbers from Crestline EDS Addendum, doc #20127.

60 mA

Layout Note:

within 6.35 mm of NB edge

These 2 caps should be

100 mA

(1.7V - 5.5V) 100 mA

NOTE: This filter is required even if using only external graphics.

2.37K

1% 1/16W MF-LF

402

15 80

1UF

10%

402

CERM

6.3V

CRITICAL

SOT23-5

TPS731125

10% 16V

402

CERM

0.01UF

1/10W

0.300

603

FF

5%

NO STUFF

402

5%

4.7

MF-LF

1/16W

NO STUFF

20% CERM

402

0.1uF

10V

1/16W

5%

4.7

402

MF-LF

0.1uF

20% CERM

402

10V

X5R

6.3V

20%

10UF

603

CERM

50V

10% 402

0.001UF0.001UF

CERM

50V

10% 402

22000pF-1000mA

16V

NFM18

20% CERM

402

10V

0.1uF

1210

1.0UH-0.5A

CASE-D3L

CRITICAL

POLY

6.3V

20%

220UF

0.1uF

20% CERM

402

10V

PLACEMENT_NOTE=Place in GMCH cavity

20%

0.1uF

10V

PLACEMENT_NOTE=Place in GMCH cavity

402

CERM

402

10%

PLACEMENT_NOTE=Place in GMCH cavity

6.3V CERM-X5R

0.47UF

20%

6.3V X5R

PLACEMENT_NOTE=Place in GMCH cavity

10uF

603

CRITICAL

6.3V

20%

PLACEMENT_NOTE=Place in GMCH cavity

22UF

CERM-X5R 805-3

2.5V D2T

470UF

20%

TANT

CRITICAL

20%

2.5V D2T

TANT

470UF

CRITICAL

1UF

10% 402

CERM

6.3V

6.3V CERM

10%

1UF

PLACEMENT_NOTE=Place in GMCH cavity

402

SYNC_DATE=03/12/2007

NB Graphics Decoupling

051-7225

A.0.0

8822

SYNC_MASTER=M76_MLB

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_VREFH

TP_LVDS_VREFL

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_VREFL

TP_LVDS_VREFH

NB_CLK100M_DPLLSS_N

=PP1V5_S0_NB_TVDAC

=CRT_BLUE =CRT_BLUE_L

=CRT_GREEN =CRT_GREEN_L

=CRT_HSYNC_R

=CRT_RED =CRT_RED_L

=CRT_TVO_IREF

=CRT_VSYNC_R

=GND_NB_VSSA_DAC_BG

=NB_CLK96M_DOT_P

=PP1V5_S0_NB_VCCD_CRT

=PP3V3_S0_NB_VCCSYNC

=TV_A_DAC =TV_A_RTN =TV_B_DAC =TV_B_RTN =TV_C_DAC =TV_C_RTN

CRT_DDC_CLK CRT_DDC_DATA

PP1V5_S0_NB_VCCD_QDAC

PP3V3_S0_NB_VCCA_CRTDAC

PP3V3_S0_NB_VCCA_DAC_BG

PP3V3_S0_NB_VCCA_TVDACA PP3V3_S0_NB_VCCA_TVDACB PP3V3_S0_NB_VCCA_TVDACC

SDVO_CTRLCLK SDVO_CTRLDATA TV_DCONSEL<0> TV_DCONSEL<1>

=PPVIN_S0_NB_DPLL

MIN_NECK_WIDTH=0.2 MM

GND_DPLL_ESR

MIN_LINE_WIDTH=0.4 MM VOLTAGE=0V

MIN_LINE_WIDTH=0.4 MM VOLTAGE=1.25V

MIN_NECK_WIDTH=0.2 MM

PP1V25_S0_NB_DPLL

P1V25S0NBDPLL_NR

MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.25V

MIN_LINE_WIDTH=0.3 MM

PP1V25_S0_NB_VCCA_DPLLB

VOLTAGE=1.5V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.3 MM

PP1V5_S0_NB_VCCD_TVDAC

PP1V25_S0_NB_VCCA_DPLLA

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.25V

=PP1V8_S0_NB_LVDS

LVDS_IBG

=PPVCORE_S0_NB

=NB_CLK96M_DOT_N

=NB_CLK100M_DPLLSS_P =NB_CLK100M_DPLLSS_N

PP1V8_S0_NB_VCCTXLVDS

MIN_LINE_WIDTH=0.2 MM VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 MM

=GND_NB_VSSA_LVDS

=PP1V8_S0_NB_VCCD_LVDS

NB_CLK100M_DPLLSS_P

=PPVCORE_S0_NB_GFX

R2261

1 2

C2261

1

2

R2262

1 2

C2262

1

2

C2260

1

2

C2223

1

2

C2221

1

2

C2201

2

1 3

C2200

1

2

L2220

1 2

C2220

1

2

C2217

1

2

C2216

1

2

C2215

1

2

C2213

1

2

C2212

1

2

C2211

1

2 3

C2210

1

2 3

C2226

1

2

C2214

1

2

R2299

1

2

C2265

1

2

U2265

3

2

1

4

5

C2266

1

2

R2260

1

2

84

21

84

30

18

30

18

15

7

8

15

19

16

19

15

19

16

15

8

19

8

16

19

7

8

SATA0RXP

SATA0RXN

SATALED*

RTCRST*

HDA_BIT_CLK

DDREQ

RTCX1 RTCX2

DCS1* DCS3*

IDEIRQ

DDACK*

IORDY

DIOR* DIOW*

DD11 DD12

DD4

DD2

DD14

DD0

DD15

DD1

DD13

DD5

DD10

DD8

DD3

DD9

LDRQ0*

FWH2/LAD2 FWH3/LAD3

FWH1/LAD1

LDRQ1*/GPIO23

FWH0/LAD0

FWH4/LFRAME*

HDA_SDIN0

HDA_SYNC

SATA1TXN SATA1TXP

HDA_SDIN1 HDA_SDIN2

RCIN*

SATA0TXP

SATA0TXN

CPUPWRGD/GPIO49

SMI*

A20M*

SATA1RXP

SATA1RXN

SATARBIAS

SATARBIAS*

IGNNE*

DPRSTP*

INTVRMEN

A20GATE

SATA2RXN SATA2RXP

THRMTRIP*

DPSLP*

INIT*

HDA_RST*

HDA_SDOUT

HDA_DOCK_EN*/GPIO33

SATA2TXN SATA2TXP

FERR*

NMI

HDA_SDIN3

INTR

SATA_CLKP

SATA_CLKN

DA2

DD6

STPCLK*

TP8

DA0 DA1

HDA_DOCK_RST*/GPIO34

INTRUDER*

LAN_TXD0

LAN100_SLP

LAN_RSTSYNC

LAN_RXD0 LAN_RXD1 LAN_RXD2

DD7

LAN_TXD2

LAN_TXD1

GLAN_DOCK*/GPIO13

GLAN_COMPI GLAN_COMPO

GLAN_CLK

LAN/GLANIHDA

CPU

RTC

LPC

(1 OF 6)

SATA

IDE

OUT

IN

BI

BI BI

BI

OUT

IN

OUT

IN IN OUT OUT

IN IN

OUT

IN IN

OUT OUT

IN

OUT

OUT OUT OUT

IN IN IN

BI

OUT OUT OUT

OUT

OUT OUT

OUT

OUT OUT

IN

OUT OUT

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NOTE: ALL IDE PINS HAVE INTERNAL 33-OHM SERIES R’S

INT PU

INT PD

INT PD INT PD INT PD INT PD

INT PD

INT PU INT PD

INTEGRATED PD

INTEGRATED PDs

ACZ_SYNC

HDA_SDOUT

HDA_SDIN[0-2]

HDA_RST#

HDA_BIT_CLK

24.000MHZ CLOCK W/INTERNAL WEAK PD

HDA

INT PD

INT PU

ICH8M

BGA

OMIT

28

7

28

7

45 47

7

45 47

7

45 47

7

45 47

28 65

7

45 47

10 79

NO STUFF

2.2K

5% 1/16W MF-LF

402

1/16W MF-LF

24.9

1%

402

1/16W 402

MF-LF

332K

1%

78 82

42 82

30 84

42

7

10 16 58 79

7

10 79

7

10 13 79

42 82

7

10 79

10 47 79

10 79

1/16W

5%

402

MF-LF

10K

10 16 46 79

402

24.9

1/16W MF-LF

1%

PLACEMENT_NOTE=Place R2308 within 50mm of U2300

34 82

MF-LF

402

332K

1%

1/16W

402

MF-LF

1/16W

5%

8.2K

34 82

8.2K

5% 1/16W MF-LF

402

54.9

402

MF-LF

1/16W

1%

PLACEMENT_NOTE=Place R2309 within 50mm of R2308 (NO STUB)

54.9

402

MF-LF

1/16W

1%

5%

1/16W MF-LF33402

402

33

MF-LF1/16W

5%

4025%

MF-LF

33

1/16W

33

402

MF-LF1/16W

5%

10K

MF-LF 402

1/16W

42 82

SB Enet, Disk, FSB, LPC

SYNC_DATE=03/16/2007

SYNC_MASTER=T9_NOME

051-7225

8823

A.0.0

LAN_ENERGY_DET

=PP3V3_S0_SB_GPIO

PP1V5_S0_SB_VCC1_5_B

GLAN_COMP

PP3V3_G3_SB_RTC

HDA_DOCK_EN_L

SB_INTVRMEN SB_LAN100_SLP

SB_SM_INTRUDER_L

SB_RTC_RST_L

SB_RTC_X2

SB_RTC_X1

TP_LAN_R2D<2>

LPC_AD<2>

LPC_AD<0> LPC_AD<1>

LPC_AD<3> LPC_FRAME_L

EXTGPU_PWR_EN

PM_THRMTRIP_L

CPU_THERMTRIP_R

CPU_A20M_L

CPU_DPSLP_L

CPU_DPRSTP_L

CPU_PWRGD

CPU_IGNNE_L CPU_INIT_L

CPU_INTR

CPU_NMI CPU_SMI_L

CPU_STPCLK_L

IDE_PDD<0>

IDE_PDD<2>

IDE_PDD<1>

IDE_PDD<3> IDE_PDD<4> IDE_PDD<5>

IDE_PDD<7>

IDE_PDD<6>

IDE_PDD<8>

IDE_PDD<10>

IDE_PDD<9>

IDE_PDD<12>

IDE_PDD<11>

IDE_PDD<13>

IDE_PDD<15>

IDE_PDD<14>

IDE_PDA<0> IDE_PDA<1> IDE_PDA<2>

IDE_PDCS3_L

IDE_PDCS1_L

IDE_PDIOW_L

IDE_PDIOR_L

IDE_PDDACK_L IDE_IRQ14 IDE_PDIORDY IDE_PDDREQ

=PP1V05_S0_SB_CPU_IO

=PP3V3_S0_SB_GPIO

CPU_FERR_L

SB_A20GATE

TP_LPC_DRQ0_L

SB_RCIN_L

TP_SB_TP8

TP_LAN_D2R<2>

SATA_A_D2R_P

TP_SB_SATALED_L

SATA_A_R2D_C_P

SATA_A_R2D_C_N

SATA_B_D2R_P

SATA_B_D2R_N

TP_HDA_DOCK_RST_L

TP_LAN_R2D<0>

TP_LAN_RSTSYNC TP_LAN_D2R<0>

TP_LAN_R2D<1>

SATA_B_R2D_C_N SATA_B_R2D_C_P

SATA_C_D2R_P

SATA_C_D2R_N

SATA_C_R2D_C_N SATA_C_R2D_C_P

SB_CLK100M_SATA_P

SB_CLK100M_SATA_N

SATA_RBIAS_P

SATA_RBIAS_N

HDA_BIT_CLK_R HDA_SYNC_R

HDA_RST_L_R

HDA_SDOUT_R

HDA_SYNC

HDA_BIT_CLK

HDA_RST_L

HDA_SDOUT

SATA_A_D2R_N

TP_HDA_SDIN1

TP_ENET_GLAN_CLK

TP_LAN_D2R<1>

HDA_SDIN0

TP_HDA_SDIN3

TP_HDA_SDIN2

U2300

AF13 AG26

AG29

AA4 AA1 AB3

Y6 Y5

V1 U2

T4 V6 V5 U1 V2 U6

V3 T1 V4 T5 AB2 T6 T3 R2

Y2

W5

W4 W3

AF26 AE26

AD24

E5 F5 G8 F6

C4

B24

D25 C25

AH21

AJ16

AE10 AG14

AE14

AJ17 AH17 AH15 AD13

AE13

AJ15

Y3

AF27

AE24 AC20

AD22

AF25

Y1

AD21

D22

C21 B21 C22

D21 E20 C20

G9 E6

AD23

AH14

AF23

AG25 AF24

AF6 AF5 AH5 AH6

AG3 AG4 AJ4 AJ3

AF2 AF1 AE4 AE3

AB7 AC6

AF10

AG2

AG1

AG28

AA24

AE27

AA23

R2304

1

2

R2302

1

2

R2301

1

2

R2306

1

2

R2308

1 2

R2300

1

2

R2303

1

2

R2310

1

2

R2305

1

2

R2309

1

2

R2313

1 2

R2314

1 2

R2315

1 2

R2316

1 2

R2311

1

2

25

27

28

27

25

23

26

27

26

23

8

24

83

26

7

8

82

SPI_CS1*

PETN1

PERP1

OC4*/GPIO43 OC5*/GPIO29 OC6*/GPIO30 OC7*/GPIO31 OC8* OC9*

SPI_MOSI

OC0* OC1*/GPIO40 OC2*/GPIO41 OC3*/GPIO42

PERN5

DMI1RXN DMI1RXP DMI1TXN DMI1TXP

DMI0RXN DMI0RXP DMI0TXN DMI0TXP

DMI_CLKN DMI_CLKP

PETP1

USBP9N USBP9P

PERN2

USBP7N USBP7P USBP8N USBP8P

PETN2

USBP6N USBP6P

PERP3

USBP4N USBP4P USBP5N USBP5P

PETN3

PETP3

USBP3N USBP3P

PERN4 PERP4

USBP1N USBP1P USBP2N USBP2P

PETN4 PETP4

USBP0N USBP0P

PERP5

SPI_MISO

USBRBIAS

USBRBIAS*

PETP5

PERN6/GLAN_RXN PERP6/GLAN_RXP PETN6/GLAN_TXN PETP6/GLAN_TXP

SPI_CLK SPI_CS0*

DMI3RXN DMI3RXP DMI3TXN DMI3TXP

DMI2RXN DMI2RXP DMI2TXN DMI2TXP

DMI_IRCOMP

DMI_ZCOMP

PERN1

PERP2

PETP2

PERN3

PETN5

PCI_EXPRESS

DIRECT MEDIA INTERFACE

SPI

USB

(2 OF 6)

IN

IN OUT OUT

IN

IN OUT OUT

IN

IN OUT OUT

IN

IN OUT OUT

IN

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

IN

IN OUT OUT

IN

IN OUT OUT

BI BI

BI

AD4 AD5

AD9

PIRQF*/GPIO3

PIRQE*/GPIO2

AD13

PME*

PCIRST*

GNT2*/GPIO53

C/BE2*

PIRQG*/GPIO4

SERR*

PIRQA*

AD1

REQ1*/GPIO50

C/BE3*

AD11

C/BE1*

AD25 AD26

AD0

AD2

DEVSEL*

AD18

AD21

PAR

GNT0*

AD7

GNT1*/GPIO51

C/BE0*

STOP*

AD20

AD16

GNT3*/GPIO55

TRDY*

IRDY*

AD22

PIRQC*

REQ2*/GPIO52

AD19

PCICLK

PLOCK*

AD15

PIRQB*

PIRQH*/GPIO5

PLTRST*

AD3

AD6

AD8

FRAME*

AD14

AD12

AD10

REQ3*/GPIO54

PIRQD*

AD17

PERR*

REQ0*

AD31

AD27 AD28

AD30

AD29

AD24

AD23

(3 OF 6)

INTERRUPT I/F

PCI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

IN

BI

BI BI

OUT

BI BI BI

BI

OUT

IN

BI BI

IN

IN IN IN

OUT

IN

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NOTE: USBP[0-9]P/N have internal 15K pull-downs.

IR

Bluetooth

External D / WWAN

External A

Geyser Trackpad/Keyboard

External B

ExpressCard

AirPort (PCIe Mini-Card)

Camera

External C

INT PD

EHCI0

INT PD

INT PD INT PD INT PD INT PD INT PD

INT PD

INT PU

EHCI1

INT PD

Spares

ExpressCard

FireWire

(AirPort)

Ethernet

(x2-capable, pull HDA_SYNC high for x2)

SPI_CS1# HAS INT PU (NOMINAL=20K, SIMULATION=15K-35K)

GNT0# HAS INT PU; ENABLED ONLY WHEN PCIRST#=0 AND PWROK=H

1

GNT0#

0

NOTE:

SPI

PCIe Mini Card

Yukon-PCIE Nineveh-GLCI

LPC

I/F

SB BOOT BIOS SELECT

selects SPI ROM by default.

R2415 pull-down on GNT0#

Provide a pull-down on this GPIO if not used.

INT PU

FireWire INT*

rises, or PCIe ports 5 & 6 will be disabled.

If used, ensure GNT2# is not low when PWROK

enabled only when PCIRST# = 0 and PWROK = 1

NOTE: GNT[0-3]# have internal 20K pull-ups

MF-LF

5%

10K

402

1/16W

1/16W MF-LF 402

10K

5%

10K

402

5% 1/16W MF-LF

10K

1/16W 402

MF-LF

5%

MF-LF 402

5%

10K

1/16W

402

5% 1/16W MF-LF

10K

402

1/16W

10K

MF-LF

5%

10K

MF-LF 402

1/16W

5%

BGA

ICH8M

OMIT

16 80

30 84

1% 402

MF-LF1/16W

24.9

43 82

34 82

44 82

7

44 82

7

44 82

78 82

34 82

9

82

9

82

22.6

MF-LF

402

1%

1/16W

34 83

35 83

55 82

ICH8M

BGA

OMIT

38 83

24 83

24 38 83

24 83

24 38 83

24 83

38 83

24 38 83

38 83

7

28

24 38 83

24 83

24 38 83

7

28 77

30 84

24 83

5%

402

MF-LF

1/16W

10K

402

1/16W

5%

MF-LF

10K

402

5% 1/16W MF-LF

1K

8.2K

24 83

8.2K

13 43

13

13 34

34 46

24 42

76

38 83

42 82

13

7

47

13 77

8.2K

13

13 36

13

SYNC_DATE=03/16/2007

051-7225

8824

A.0.0

SYNC_MASTER=T9_NOME

SB PCI, PCIe, DMI, USB

WOW_EN

INT_PIRQD_L

INT_PIRQC_L

INT_PIRQA_L INT_PIRQB_L

PCI_AD<31>

PCI_AD<30>

PCI_AD<29>

PCI_AD<28>

PCI_AD<27>

PCI_AD<26>

PCI_AD<25>

PCI_AD<23> PCI_AD<24>

PCI_AD<22>

PCI_AD<21>

PCI_AD<20>

PCI_AD<19>

PCI_AD<17> PCI_AD<18>

PCI_AD<16>

PCI_AD<15>

PCI_AD<14>

PCI_AD<12> PCI_AD<13>

PCI_AD<11>

PCI_AD<10>

PCI_AD<9>

PCI_AD<7> PCI_AD<8>

PCI_AD<6>

PCI_AD<5>

PCI_AD<4>

PCI_AD<3>

PCI_AD<1> PCI_AD<2>

PCI_AD<0>

ODD_PWR_EN_L

DVI_HOTPLUG_DET

INT_PIRQE_L INT_PIRQF_L

PLT_RST_L PCI_CLK33M_SB

PCI_TRDY_L PCI_FRAME_L

PCI_STOP_L

PCI_SERR_L

PCI_LOCK_L

PCI_DEVSEL_L PCI_PERR_L

PCI_RST_L

PCI_PAR

PCI_IRDY_L

PCI_C_BE_L<3>

PCI_C_BE_L<1>

PCI_C_BE_L<0>

PCI_C_BE_L<2>

ODD_RST_5VTOL_L

PCI_REQ2_L

PCI_FW_REQ_L

TP_SB_GPIO55

TP_SB_GPIO51

PCI_REQ1_L

TP_SB_GPIO53

TP_PCI_PME_L

BOOT_LPC_SPI_L

PCI_FW_GNT_L

MAKE_BASE=TRUE

=PP3V3_S5_SB_USB

SB_GPIO40

USB_EXTA_OC_L

EXTGPU_LVDS_EN

USB_EXTC_OC_L

SB_GPIO30

TP_PCIE_A_R2D_C_P

PCI_REQ1_L

PCI_TRDY_L

INT_PIRQE_L

INT_PIRQD_L

INT_PIRQB_L

INT_PIRQA_L

PCI_REQ2_L

PCI_STOP_L

PCI_IRDY_L

PCI_FRAME_L

PCI_FW_REQ_L

PCI_LOCK_L

INT_PIRQF_L

INT_PIRQC_L

ODD_PWR_EN_L

PCI_SERR_L PCI_DEVSEL_L PCI_PERR_L

=PP3V3_S0_SB_PCI

PP1V5_S0_SB_VCC1_5_B

USB_RBIAS

DMI_IRCOMP_R

TP_SPI_CE_R_L<1>

TP_PCIE_A_R2D_C_N

TP_PCIE_A_D2R_P

PM_LATRIGGER_L

USB_EXTB_OC_L EXCARD_OC_L

SPI_SI_R

USB_EXTD_OC_L

PCIE_MINI_D2R_N

TP_PCIE_B_D2R_N

TP_PCIE_B_R2D_C_N

TP_PCIE_EXCARD_D2R_P TP_PCIE_EXCARD_R2D_C_N TP_PCIE_EXCARD_R2D_C_P

TP_PCIE_FW_D2R_N TP_PCIE_FW_D2R_P TP_PCIE_FW_R2D_C_N TP_PCIE_FW_R2D_C_P

PCIE_MINI_D2R_P

SPI_SO

PCIE_MINI_R2D_C_P

PCIE_ENET_D2R_N PCIE_ENET_D2R_P PCIE_ENET_R2D_C_N PCIE_ENET_R2D_C_P

SPI_SCLK_R SPI_CE_R_L<0>

TP_PCIE_A_D2R_N

TP_PCIE_B_D2R_P

TP_PCIE_B_R2D_C_P

TP_PCIE_EXCARD_D2R_N

PCIE_MINI_R2D_C_N

USB_EXTC_P

USB_EXCARD_P USB_EXTC_N

USB_EXCARD_N

USB_EXTB_P

USB_EXTB_N

USB_BT_P

USB_TPAD_P USB_BT_N

USB_TPAD_N

USB_IR_P

USB_IR_N

USB_CAMERA_N USB_CAMERA_P

USB_EXTD_P

USB_EXTD_N

USB_MINI_P

USB_MINI_N

USB_EXTA_P

USB_EXTA_N

SB_CLK100M_DMI_P

SB_CLK100M_DMI_N

DMI_S2N_P<3>

DMI_S2N_N<3>

DMI_N2S_P<3>

DMI_N2S_N<3>

DMI_S2N_P<2>

DMI_S2N_N<2>

DMI_N2S_P<2>

DMI_N2S_N<2>

DMI_S2N_P<1>

DMI_S2N_N<1>

DMI_N2S_P<1>

DMI_N2S_N<1>

DMI_S2N_P<0>

DMI_S2N_N<0>

DMI_N2S_P<0>

DMI_N2S_N<0>

R2408

1

2

R2407

1

2

R2400

1

2

R2409

1

2

R2401

1

2

R2402

1

2

R2404

1

2

R2403

1

2

U2300

V27 V26 U29 U28

Y27 Y26 W29 W28

AB26 AB25 AA29 AA28

AD27 AD26 AC29 AC28

T26 T25

Y24

Y23

AJ19 AG16 AG15 AE15 AF15 AG17 AD12 AJ18 AD14 AH18

P27

M27

K27

H27

F27

D27

P26

M26

K26

H26

F26

D26

N29

L29

J29

G29

E29

C29

N28

L28

J28

G28

E28

C28

C23 B23 E22

F21

D23

G3 G2 H5 H4 H2 H1 J3 J2 K5 K4 K2 K1 L3 L2 M5 M4 M2 M1 N3 N2

F3

F2

R2413

1 2

R2414

1 2

U2300

D20 E19

A12 E16 A14 G16 A15

B6

C11

A9 D11 B12

D19

C12 D10

C7 F13 E11 E13 E12

D8

A6

E8

A20

D6

A3

D17 A21 A19 C19 A18 B16 C17

E15 F16 E17

D16

A17

D7

C18

F18

C10

C8 D9

B10

G6

A7

F9

B5

C5 A10

F8 G11 F12 B3

B7

AG24

G7

A4

E18

B19

A11

F10 C16 C9

R2405

1

2

R2406

2

1

R2415

1

2

R2423

1 2

R2424

1 2

R2425

1 2

R2426

1 2

R2427

1 2

R2428

1 2

R2430

1 2

R2429

1 2

R2432

1 2

R2431

1 2

R2433

1 2

R2437

1 2

R2439

1 2

R2438

1 2

R2436

1 2

R2440

1 2

R2441

1 2

R2442

1 2

83

27

83

38

83

38

83

38

83

42

38

26

8

24

8

23

82

34

OUT OUT

BI

IN

BI

IN IN

SMBALERT*/GPIO11

STP_PCI*/GPIO15

BMBUSY*/GPIO0

SYS_RESET*

SUS_STAT*/LPCPD*

QRT_STATE0/GPIO27

THRM*

SMLINK0

GPIO12

SPKR

SDATAOUT1/GPIO48

QRT_STATE1/GPIO28

SLP_S5*

GPIO20

GPIO8

WAKE*

CL_CLK1

BATLOW*

PWROK

SLOAD/GPIO38

SATA2GP/GPIO36

SERIRQ

RI*

CL_DATA1

SLP_S4*

EC_ME_ALERT/GPIO14

TACH0/GPIO17

CLK14

SCLOCK/GPIO22

SATA3GP/GPIO37

SATACLKREQ*/GPIO35

STP_CPU*/GPIO25

WOL_EN/GPIO9

LINKALERT*

SLP_S3*

RSMRST*

TACH3/GPIO7

CLKRUN*/GPIO32

GPIO18

LAN_RST*

CL_VREF1

S4_STATE*/GPIO26

TACH1/GPIO1 TACH2/GPIO6

SATA1GP/GPIO19

SDATAOUT0/GPIO39

SATA0GP/GPIO21

MCH_SYNC*

DPRSLPVR/GPIO16

VRMPWRGD

TP3

TP7

CL_RST*

ME_EC_ALERT/GPIO10

SLP_M*

MEM_LED/GPIO24

PWRBTN*

SUSCLK

CL_VREF0

CK_PWRGD

CLPWROK

CL_DATA0

CL_CLK0

CLK48

SMBCLK SMBDATA

SMLINK1

MISC

SYS GPIO

SMB

CLOCKS

POWER MGT

CONTROLLER LINK

GPIO

SATA

GPIO

(4 OF 6)

IN IN

OUT

IN

BI BI

OUT

IN

OUT

IN

BI

OUT

BI

IN

OUT OUT

OUT

IN

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

If ME/AMT is not used, short CLPWROK to PWROK.

PP3V3_S0M, PP3V3_S0MWOL, PP1V8_S3M, PP1V25_S0M,

have been up for at least 1ms.

PM_LAN_ENABLE must remain deasseted until VccCL3_3, VccLAN3_3 and VccLAN1_05

INT PU

NOTE: ICH CLPWROK input must be PWRGD signal for

INT PD

INT PU

Test access required

AT BOOT/RESET FOR STRAPPING FUNCTION

NOTE: DPRSLPVR HAS INT 20K PD ENABLED

INT PU

for XOR chain testing.

PP1V05_S0M, PP0V9_S3M and PP0V9_S0M.

See note below

7

29 30

7

29 30

7

45 47

34 35

7

45 47

45

13 45

5% 1/16W MF-LF 402

10K

402

0

5% 1/16W MF-LF

ARB_ONLY

MF-LF

1/16W

5%

10K

402

MF-LF

1/16W

5%

0

402

NOSTUFF

5%

10K

MF-LF

402

1/16W

402

10K

5% MF-LF

1/16W

1K

5% 1/16W MF-LF 402

402

8.2K

5% 1/16W MF-LF

402

5%

10K

1/16W MF-LF

402

1/16W

8.2K

5%

MF-LF

OMIT

BGA

ICH8M

30 84

46

7

36 40 45 65

402

1/16W

5%

1K

NO_REBOOT_MODE

MF-LF

7

45 46

7

16 58 79

7 9

28

25 45

7

45

48 82

7

45 46 47

7

28 45

16

7

28

25 38

7

16

7

45 65

29

9

16 83

402

3.24K

1% 1/16W MF-LF

402

453

1% 1/16W MF-LF

402

16V

10%

0.1uF

X5R

402

1/16W

1% MF-LF

4.53K

1% 1/16W MF-LF 402

32.4K

402

16V

10% X5R

0.1uF

16 83

25

100K

1/16W

402

MF-LF

5%

48 82

25

1/16W

10K

MF-LF

1%

402

5%

MF-LF

1/16W

8.2K

402

MF-LF

10K

1/16W

1%

402

10K

MF-LF

1/16W

5%

402

7

25 47

25

25 28

29

MF-LF

1/16W

5%

10K

402

MF-LF

1/16W

10K

5%

MF-LF

402

1/16W

5%

10K

402

MF-LF

1/16W

5%

8.2K

1/16W

8.2K

5% MF-LF

402

7

45

1%

MF-LF

1/16W

10K

402

1%

MF-LF

1/16W

10K

402

10K

MF-LF

402

5%

1/16W

402

1/16W

5%

MF-LF

10K

1/16W MF-LF

10K

402

5%

77

5% 1/16W MF-LF

10K

402

100K

402

5% 1/16W MF-LF

10K

1/16W MF-LF

1%

402

10K

1/16W MF-LF

1%

402

MF-LF

1/16W

5%

100K

402

MF-LF

10K

1/16W

1%

402

10K

1/16W MF-LF

1%

402

A.0.0

25 88

051-7225

SYNC_MASTER=T9_NOME

SYNC_DATE=03/16/2007

SB Pwr Mgt, GPIO, Clink

=PP3V3_S5_SB_GPIO

=PP3V3_S0_SB_GPIO

ARB_DETECT_L

TP_PM_SLP_M_L

CLINK_NB_CLK

SB_GPIO14_CL2

SB_CLINK_VREF1

SB_SCLOCK

SB_GPIO18

PM_STPCPU_L

PM_LAN_ENABLE PM_RSMRST_L CLK_PWRGD

PCI_PME_FW_L

=PP3V3_S5_SB

SATA_B_PWR_EN_L

SB_SPKR

SMC_WAKE_SCI_L

TP_SB_TP3

SB_SLOAD

SB_SATA_CLKREQ_L

FWH_MFG_MODE

SATA_B_PWR_EN_L

TP_SB_GPIO20

EXTGPU_RST_L

LAN_PHYPC

SMC_RUNTIME_SCI_L

SB_GPIO6

TP_SB_TP7 PCI_PME_FW_L

PM_CLKRUN_L PCIE_WAKE_L

INT_SERIRQ

PM_THRM_L

SATA_B_DET_L

TP_CLINK_WLAN_DATA

SB_GPIO10_CL1

WOL_EN

PM_SLP_S3_L

SB_CLK14P3M_TIMER

VR_PWRGD_CLKEN

PM_SUS_STAT_L

NB_SB_SYNC_L

LINDACARD_GPIO

PM_BMBUSY_L

CLINK_NB_DATA

TP_CLINK_WLAN_CLK

PM_BATLOW_L

PM_S4_STATE_L PM_SB_PWROK

PM_SLP_S5_L

TP_PM_SLP_S4_L

PM_SYSRST_L

SMB_ME_DATA

SMB_DATA

=PP3V3_S0MWOL_SB_CLINK0

SB_GPIO14_CL2

LAN_PHYPC

SB_GPIO10_CL1

PM_BATLOW_L

PM_RI_L

PM_DPRSLPVR

SMB_CLK

SMB_ME_CLK

PM_PWRBTN_L

TP_CLINK_WLAN_RESET_L

SUS_CLK_SB

SB_CLK48M_USBCTLR

=PP3V3_S5_SB_CLINK1

CLINK_NB_RESET_L

PM_RI_L

=SB_CLINK_MPWROK

PM_STPPCI_L

RSVD_EXTGPU_LVDS_EN

SB_CRT_TVOUT_MUX_L

SB_GPIO36

SB_CLINK_VREF0

=PP3V3_S5_SB

LINDACARD_GPIO

FWH_MFG_MODE

ARB_DETECT_L

SB_GPIO6

=PP3V3_S0_SB_GPIO

EXTGPU_RST_L

SB_SDATAOUT<0> SB_SDATAOUT<1>

R2510

1

2

R2515

1

2

R2516

1

2

R2511

1

2

R2512

1

2

R2502

1

2

R2504

1

2

R2500

1

2

R2507

1

2

R2506

1

2

R2505

1

2

U2300

AE21

AG12

E1

F23 AE18

F22 AF19

AJ23

D24 AH23

AG9 G5

AH11

E3

AJ14

AF22

AC19

AH12 AE11

AE16

AH20

AG21

AJ13 AJ24

AJ27

C2

AE23

AH25 AD16

AF17

AG27

AH27

AJ12 AJ10 AF11 AG11

AG13

AG10

AJ11 AD10

AF12

AF9

AJ25

AG23 AF21 AD18

AG22

AJ26 AD19

AC17 AE19

AD9

AG18

AE20

F4 D3

AD15

AG8

AJ8 AJ9 AH9

AC13

AJ21

AJ22

AJ20

AE17

AG19

R2526

1

2

R2527

1

2

C2500

1

2

R2529

1

2

R2528

1

2

C2501

1

2

R2523

1

2

R2536

1 2

R2544

1 2

R2545

1 2

R2525

1

2

R2534

2

1

R2552

1

2

R2550

1

2

R2553

1

2

R2551

1

2

R2598

1 2

R2546

1 2

R2532

2

1

R2533

2

1

R2535

2

1

R2547

2

1

R2524

1

2

R2530

1 2

R2531

1 2

R2514

2

1

R2596

1 2

R2597

1 2

25

27

47

25

23

38

25

45

25

23

28

8

25

83

25

8

25

36

8

25

8

83

8

7

25

8

25

VSS

VSS_NCTF

VSS

(5 OF 6)

VCC1_5_B

V5REF_SUS

VCCDMIPLL

VCC_DMI

VCC3_3

VCC1_05

V5REF

VCCCL1_5

VCCGLANPLL

VCC3_3

VCC1_5_A

VCC3_3

VCCHDA

VCCSUS1_5

VCCSUS3_3

V_CPU_IO

VCC3_3

VCCSUSHDA

VCC1_5_A

VCC3_3

VCCSATAPLL

VCCGLAN3_3

VCCSUS3_3

VCCLAN3_3

VCCCL1_05

VCCSUS1_05

VCCSUS1_5

VCCSUS3_3

VCCA3GP

VCCGLAN1_5

VCCCL3_3

VCCLAN1_05

VCC1_5_A24

VCC1_5_A

VCCRTC

VCC1_5_A

VCCUSBPLL

VCC1_5_A

GLAN POWER

USB CORE

ATX ARX

(6 OF 6)

VCCPSUS

IDE

COREVCCP CORE

PCI

VCCPUSB

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

6 uA S0-G3

1 mA

1 mA S0-S5

657 mA

Current numbers from ICH8M Max Power Estimates Rev 2.0, doc #610194.

Current figures provided assume 1.5V.

depending on VIO of HD Audio interface.

VccHDA and VccSusHDA can be 1.5V or 3.3V

NOTE:

1130 mA

23 mA

50 mA

1 mA

(VCC3_3 total)

442 mA

117 mA S0,

11 mA S0,

44 mA S3-S5

1 mA S3-S5

(VCCSUS3_3 total)

32 mA

1080 mA

47 mA

(VCC1_5_A total)

63 mA M1 & WOL

19 mA S0,

10 mA

23 mA 80 mA

1 mA

51 mA M1 & WOL

19 mA S0,

1uF

6.3V CERM

10%

402 402

CERM

10V

20%

0.1uF

ICH8M

BGA

OMIT

BGA

ICH8M

OMIT

SYNC_MASTER=T9_NOME

051-7225

8826

A.0.0

SYNC_DATE=03/16/2007

SB Power & Ground

=PP3V3_S0_SB_VCC3_3_PCI

=PP1V5_S0_SB_VCCUSBPLL

PP3V3_G3_SB_RTC

TP_VCCLAN1_05_INTERNAL_REG1 TP_VCCLAN1_05_INTERNAL_REG2

TP_VCCSUS1_05_INTERNAL_REG2

TP_VCCSUS1_5_INTERNAL_REG2

TP_VCCSUS1_05_INTERNAL_REG1

TP_VCCCL1_05_INTERNAL_REG

=PP3V3_S0_SB_VCCGLAN3_3

PP1V5_S0_SB_VCCSATAPLL

=PP3V3_S0_SB_VCC3_3_DMI

=PP3V3_S5_SB_3V3_VCCSUSHDA

=PP3V3_S0_SB_VCC3_3_SATA

TP_VCCSUS1_5_INTERNAL_REG1

=PP3V3R1V5_S0_SB_VCCHDA

PP1V5_S0_SB_VCCGLANPLL

PP1V5_S0_SB_VCCDMIPLL

PP5V_S5_SB_V5REF_SUS

=PP1V5_S0_SB_VCCGLAN1_5

=PP3V3_S0MWOL_SB_VCCCL3_3

=PP1V5_S0_SB_VCC1_5_A_USB_CORE

=PP1V5_S0_SB_VCC1_5_A

=PP3V3_S0MWOL_SB_VCCLAN3_3

=PP3V3_S5_SB_VCCSUS3_3_USB

=PP3V3_S5_SB_VCCSUS3_3

=PP1V5_S0_SB_VCC1_5_A_ATX

=PP1V5_S0_SB_VCC1_5_A_ARX

=PP1V25_S0_SB_DMI

=PPVCORE_S0_SB

VCCCL1_5V

PP5V_S0_SB_V5REF

PP1V5_S0_SB_VCC1_5_B

=PP3V3_S0_SB_VCC3_3_IDE

=PP3V3_S0_SB_VCC3_3_VCCPCORE

=PP1V05_S0_SB_CPU_IO

U2300

A23

A5

AC26

L13 L15 L26 L27 L4 L5 M12 M13 M14 M15

AC27

M16 M17 M23 M28 M29 M3 N1 N11 N12 N13

AD17

N14 N15 N16 N17 N18 N26 N27 N4 N5 N6

AD20

P12 P13 P14 P15 P16 P17 P23 P28 P29 R11

AD28

R12 R13 R14 R15 R16 R17 R18 R28 R4 T12

AD29

T13 T14 T15 T16 T17 T2 U12 U13 U14 U15

AD3

U16 U17 U23 U26 U27 U3 U5 V13 V15 V28

AD4

V29 W2 W26 W27 Y28 Y29 Y4 AB4 AB23 AB5

AD6

AB6 AD5 U4 W24

AE1

AA2

AE12

AE2

AE22

AD1

AE25

AE5 AE6

AE9 AF14 AF16

AA7

AF18

AF3

AF4

AG5

AG6 AH10 AH13 AH16 AH19

AH2

A25

AF28 AH22 AH24 AH26

AH3

AH4

AH8

AJ5

B11

B14

AB1

B17

B2 B20 B22

B8 C24 C26 C27

C6 D12

AB24

D15 D18

D2

D4 E21 E24

E4

E9 F15 E23

AC11

F28 F29

F7

G1

E2 G10 G13 G19 G23 G25

AC14

G26 G27 H25 H28 H29

H3

H6

J1 J25 J26

AC25

J27

J4

J5 K23 K28 K29

K3

K6

K7 L1

A1 A2

B1 B29

A28 A29 AH1 AH29 AJ1 AJ2 AJ28 AJ29

U2300

A16

T7

G4

AC23 AC24

A13 B13

L14 L16 L17 L18 M11 M18 P11 P18 T11 T18

C13

U18 V17 V14 V11 U11 V18 V16 V12

C14 D14 E14 F14 G14 L11 L12

AE7 AF7

AC10

AC9

AA5 AA6

G12 G17

H7

AC7 AD7

F1

AG7

L6 L7 M6 M7

W23

AH7 AJ7

AC1 AC2 AC3 AC4 AC5

AA25 AA26

E27 F24 F25 G24 H23 H24 J23 J24 K24 K25

AA27

L23 L24 L25 M24 M25 N23 N24 N25 P24 P25

AB27

R24 R25 R26 R27 T23 T24 T27 T28 T29 U24

AB28

W25 V24 U25 Y25 V25 V23

AB29

D28 D29 E25 E26

AF29

AD2

W6 W7 Y7

A8 B15 B18 B4 B9 C15 D13

AC8

D5 E10 E7 F11

AD8 AE8 AF8

AA3 U7 V7 W1

AE28 AE29

G22

A22

F20 G21

R29

B27 A27 B28 B26 A26

B25

A24

AC12

F17 G18

F19 G20

AD25

AJ6

J6 AF20

AC16

J7

C3

AC18

P1 P2 P3 P4 P5 R1 R3 R5 R6

AC21 AC22 AG20 AH28

P6 P7 C1 N7

AD11

D1

C2600

1

2

C2601

1

2

28

27

24

27

23

8

23

8

27

8

27

8

27

23

8

NCNC

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

REFERENCE DESIGNATOR(S)

BOM OPTION

TABLE_5_HEAD

QTY

DESCRIPTION

PART#

TABLE_5_ITEM

PLACE C2736 NEAR PIN B27..A26

PLACE CAPS < 2.54MM OF SB ON SECONDARY OR 3.56MM ON PRIMARY NEAR PIN AJ6

38 mA S0 / 114 mA M1 & WOL

(ICH INTEL HDA SUSPEND 3.3V/1.5V PWR)

ICH VCCSUSHDA BYPASS

1 mA S3-S5

11 mA S0 /

32 mA (@ 1.5V)

(@ 1.5V)

ICH USB/VCCSUS3_3 BYPASS

0.6 uA G3

Current numbers from ICH8M Max Power Estimates Rev 2.0, doc #610194.

(ICH IO,LOGIC 1.5V PWR)

ICH VCCSUS3_3 BYPASS

117 mA S0 /

44 mA S3-S5

442 mA

(VCCSUS3_3 Total)

PLACEMENT NOTE:

P6..R6

PLACEMENT NOTE: PLACE CAPS NEAR PIN AD25 OF SB

(ICH SUSPEND 3.3V PWR)

PLACE CAPS NEAR PINS AC18..AH28

PLACE CAP NEAR PINS

PLACEMENT NOTE:

(ICH SUSPEND USB 3.3V PWR)

ICH VCCRTC BYPASS (ICH RTC 3.3V PWR)

1080 mA

(VCC1_5_A Total)

657 mA

80 mA

ICH VCC1_5_B BYPASS

47 mA

33 mA

(ICH SATA PLL PWR)

ICH VCCSATAPLL Filter

23 mA

(ICH DMI PLL PWR)

ICH VCCDMIPLL Filter

33 mA

47 mA

23 mA

PLACEMENT NOTE: PLACE CAPS < 2.54MM OF SB ON SECONDARY SIDE OR 3.56MM ON PRIMARY

OR 3.56MM ON PRIMARY NEAR PIN A24

PLACE CAPS < 2.54MM OF SB ON SECONDARY

837 mA

PLACEMENT NOTE:

1 mA

ICH V5REF Filter & Follower

1 mA

PLACE C2703 < 2.54MM OF PIN A16..T7 OF SB

ON SECONDARY SIDE OR 3.56MM ON PRIMARY

1 mA S0-S5

(VCC3_3 Total)

3.56MM ON PRIMARY NEAR PINS AA3...Y7

PLACE < 2.54MM OF SB ON SECONDARY OR

PLACEMENT NOTE: PLACE < 2.54MM OF SB ON SECONDARY OR 3.56MM ON PRIMARY NEAR PIN AD2

PLACEMENT NOTE:

PLACE < 2.54MM OF SB ON SECONDARY OR 3.56MM ON PRIMARY NEAR PIN AD11

PLACE < 2.54MM OF SB ON SECONDARY OR 3.56MM ON PRIMARY NEAR PIN AC12

PLACEMENT NOTE:

NEAR PINS A8 ... F11

DISTRIBUTE IN PCI SECTION OF SB

OR 3.56MM ON PRIMARY NEAR PIN AF29

PLACE CAP < 2.54MM OF SB ON SECONDARY

PLACEMENT NOTE:

ICH VCCHDA BYPASS (ICH INTEL HDA CORE 3.3V/1.5V PWR)

ICH PCI/VCC3_3 BYPASS (ICH PCI I/O 3.3V PWR)

(ICH IDE I/O 3.3V PWR)

ICH IDE/VCC3_3 BYPASS

(ICH LAN I/F BUFFER 3.3V PWR)

ICH VCC_PAUX/VCCLAN3_3 BYPASS

PLACE CAP UNDER SB NEAR PINS F19 AND G20

PLACEMENT NOTE:

PLACEMENT NOTE: PLACE CAPS AT EDGE OF SB

ICH V_CPU_IO BYPASS (ICH CPU I/O 1.05V PWR)

50 mA

1 mA

1130 mA

ICH CORE/VCC1_05 BYPASS (ICH CORE 1.05V PWR)

10 mA

3.56MM ON PRIMARY NEAR PIN AC1..AC5

PLACEMENT NOTE:

PLACE NEAR PINS AC23,AC24 OF SB

OR 3.56MM ON PRIMARY NEAR PIN AE29

PLACE < 2.54MM OF SB ON SECONDARY

PLACEMENT NOTE:

(ICH USB PLL 1.5V PWR)

ICH VCCUSBPLL BYPASS

PLACE C2715 NEAR PIN D1 OF SB

3.56MM ON PRIMARY NEAR PINS F1..M7

ICH USB CORE/VCC1_5_A BYPASS

PLACE < 2.54MM OF SB ON SECONDARY OR

(ICH USB CORE 1.5V PWR)

PLACEMENT NOTE: PLACE < 2.54MM OF SB ON SECONDARY OR

PLACEMENT NOTE:

3.56MM ON PRIMARY NEAR PINS AE7..AJ7

PLACE < 2.54MM OF SB ON SECONDARY OR

ICH VCC1_5_A/ATX BYPASS (ICH LOGIC&IO[ATX] 1.5V PWR)

(ICH LOGIC&IO[ARX] 1.5V PWR)

ICH VCC1_5_A/ARX BYPASS

ICH V5REF_SUS Filter & Follower

(ICH GLAN PLL PWR)

PLACEMENT NOTE: PLACE C2704 < 2.54MM OF PIN G4 OF SB

(ICH Reference for 5V Tolerance on Core Well Inputs)

ON SECONDARY SIDE OR 3.56MM ON PRIMARY

(ICH Reference for 5V Tolerance on Resume Well Inputs)

ICH VCCGLANPLL Filter

PLACEMENT NOTE:

ON SECONDARY SIDE OR 3.56MM ON PRIMARY

PLACE C2700 & C2705-07 < 2.54MM OF SB

DISTRIBUTED BETWEEN AA25..V23

PLACEMENT NOTE:

220UF

2.5V POLY

20%

CASE-B2

CRITICAL

X5R 402

16V

10%

0.1UF

1

1/10W MF-LF

5%

603

4.7UF

6.3V

20%

CERM

603

0.1UF

10% 16V

402

X5R

SOT-363

BAT54DW

SOT-363

BAT54DW

1210

1.0UH-0.5A

X5R

6.3V

20%

10UF

603

X5R 402

16V

10%

0.1UF

1UF

10% 402

CERM

6.3V

2.2uF

603

CERM1

20%

6.3V

20% CERM

603

4.7uF

CERM 603

20%

6.3V

X5R 402

16V

10%

0.1UF

10% 16V

402

X5R

10UH-100MA

0805

0.1UF

10% 16V

402

X5R

6.3V

22UF

805-3

20% CERM-X5R

X5R 402

16V

10%

0.1UF

402

5%

MF-LF

1/16W

0

100

MF-LF

1/16W

5%

402

10

MF-LF

1/16W

5%

402

0.1UF

10% 16V

402

X5R

OMIT

SM

FERR-330-OHM

805-3

6.3V

20%

22UF

CERM-X5R

22UF

805-3

CERM-X5R

6.3V

20%

6.3V

20% CERM1

2.2UF

603

402

CERM

16V

0.01UF

10%

603

10UF

20%

6.3V X5R

6.3V CERM 402

1UF

10%

6.3V CERM 402

10%

1UF

X5R 402

16V

10%

0.1UF

X5R 402

16V

10%

0.1UF

10% 16V

402

X5R

X5R 402

16V

10%

0.1UF

10% 16V

402

X5R

X5R 402

16V

10%

0.1UF

X5R 402

16V

10%

0.1UF

X5R 402

16V

10%

0.1UF

X5R 402

16V

10%

0.1UF

10% 16V

402

X5R

0.1UF

10% 16V

402

X5R

0.1UF

10% 16V

402

X5RX5R

402

16V

10%

0.1UF

155S0333

1

FLTR,EMI BEAD,330 OHM,1.5A,0805,SMD

L2700

SYNC_MASTER=T9_NOME

SB Decoupling

SYNC_DATE=01/17/2007

27 88

A.0.0

051-7225

=PP5V_S5_SB

PP1V5_S0_SB_VCCGLANPLL

=PP1V5_S0_SB

=PP1V5_S0_SB_VCC1_5_A_ATX

=PP1V5_S0_SB_VCC1_5_A_ARX

=PP1V5_S0_SB_VCC1_5_A_USB_CORE

=PP1V5_S0_SB_VCCUSBPLL

=PP1V25_S0_SB_DMI

=PPVCORE_S0_SB

=PP1V05_S0_SB_CPU_IO

=PP3V3_S0MWOL_SB_VCCLAN3_3 =PP3V3_S0MWOL_SB_VCCCL3_3

=PP3V3_S0_SB_VCC3_3_IDE

=PP3V3_S0_SB_VCC3_3_SATA

=PP3V3_S0_SB_VCC3_3_DMI

=PP3V3R1V5_S0_SB_VCCHDA

=PP3V3_S5_SB_3V3_VCCSUSHDA

=PP3V3_S0_SB_VCC3_3_PCI

=PP3V3_S5_SB

MIN_LINE_WIDTH=0.3MM

PP5V_S5_SB_V5REF_SUS

MIN_NECK_WIDTH=0.25MM VOLTAGE=5V

=PP5V_S0_SB

=PP3V3_S0_SB

VOLTAGE=5V

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.3MM

PP5V_S0_SB_V5REF

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM VOLTAGE=1.5V

PP1V5_S0_SB_VCCDMIPLL_F

PP1V5_S0_SB_VCCSATAPLL_F

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM VOLTAGE=1.5V

PP1V5_S0_SB_VCCDMIPLL

VOLTAGE=1.5V

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM

VOLTAGE=1.5V

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM

PP1V5_S0_SB_VCCSATAPLL

=PP1V5_S0_SB_VCCGLAN1_5

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

MAKE_BASE=TRUE

VOLTAGE=1.5V

PP1V5_S0_SB_VCC1_5_B

=PP3V3_S5_SB_VCCSUS3_3_USB

PP3V3_G3_SB_RTC

=PP3V3_S5_SB_VCCSUS3_3

C2700

1

2

R2700

1 2

C2703

1

2

C2704

1

2

L2700

1 2

C2705 C2706 C2707

C2701

1

2

C2708

1

2

C2717

C2714

1

2

C2715

1

2

C2718

1

2

C2719

1

2

C2721

1

2

C2723

1

2

C2725

1

2

C2726

1

2

C2727

1

2

C2728

1

2

C2729

1

2

C2730

1

2

C2734

1

2

C2731

1

2

C2712

1

2

C2724

1

2

C2722

1

2

D2702

1

6

5

D2702

4

3

2

L2703

1 2

C2735

1

2

C2711

1

2

C2732

1

2

C2736

1

2

C2733

1

2

C2741

1

2

C2738

1

2

L2702

1 2

C2737

1

2

C2739

1

2

C2702

1

2

R2735

1 2

R2702

2

1

R2701

2

1

26

28

26

23

26

25

24

26

8

26

8

26

8

26

23

8

23

8

OUT

IN

OUT

IN

NCNC

IN

OUT

IN

OUT OUT

OUT

IN

OUT

IN

A

B

Y

132

A

B

Y

132

IN

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

into isolated signals due to sharp reset edge and isolating FET Cgs.

that would otherwise be injected

of the system. RC prevents glitch

certain GPU signals from the rest

Coin-Cell Connector

518S0487

CPU VCore ForcePSI

SB RTC Crystal

NC

This part is never stuffed, it provides a set of pads on the board to short or

RTC Power Sources

w/ 1K pullup on PM_ALL_GPU_PGOOD)

GPU_IOENABLE_RC is used to isolate

NC

Unbuffered

NC

to solder a reset button.

Platform Reset Connections

NC

Muxed GFX GPU Reset Support

VRMPWRGD Inverter

System Reset "Button"

reset while chip is still powered and clocks are still running.

This ensures that GPU is put into

ON POWER DOWN:

PCI Reset Connections

PWROK Circuit

fault protection for RTC battery.

NOTE: R2800 and D2805 form the double-

(RC should reach schmitt trigger

run before GPU is released from reset

This delay ensures that GPU clocks

ON POWER UP:

threshold at approx .8 ms nominal

1/16W

5%

MF-LF

20K

402

23

CERM

20% 10V

0.1UF

402

6.3V CERM

1UF

10%

402

10 13

MF-LF

1/16W

1M

402

5%

7

25 45

10K

MF-LF

5%

402

1/16W

5%

402

1/16W MF-LF

1K

CERM

5%

50V 402

12pF

5%

50V

12pF

402

CERM

32.768K

SM-2

CRITICAL

0

MF-LF

5%

1/16W

402

1/16W MF-LF

10M

5%

402

7

24 77

1K

1/16W

5%

MF-LF

ITP&XDP

402

SOT-363

BAT54DW

402

1/16W MF-LF

100

5%

1/16W

5%

0

MF-LF

402

MF-LF

402

5%

1/16W

100

MF-LF

5%

1/16W

402

10V

20%

CERM

0.1UF

402

7 9

16 58

45 46 65

7 9

25

10V

20%

CERM

0.1UF

402

MF-LF

402

1/16W

5%

0

7

16

7

47

7

45

34

7

66

SC70

MC74VHC1G08

SC70

MC74VHC1G08

SC70-5

MC74VHC1G00

MF-LF

OMIT

5%

0

1/10W 603

SILK_PART=SYS RST

38

402

0

5% 1/16W MF-LF

38

402

1/16W

5%

MF-LF

100

7

24

77

76

58 10

58

7

25

402

1/16W

5% MF-LF

10K

5%

402

1/16W MF-LF

CRITICAL

BM02B-ACHKS-GAN-TF-LF-SN-M

M-RT-SM

1/16W

402

1K

MF-LF

5%

0.001UF

402

CERM

10% 50V

5%

402

MF-LF

0

1/16W

35

30 77

0.1UF

402

CERM

10V

20%

5%

1/16W

10K

MF-LF

402

16V

0.047UF

10% CERM

402

1/16W MF-LF

402

1%

24.3K

CRITICAL

74LVC2G132

US8

CRITICAL

US8

74LVC2G132

25

23 65

EXTGPU_RST_HW

5%

MF-LF

402

1/16W

0

EXTGPU_RST_SW

1/16W MF-LF

5%

402

0

7

23

10%

1UF

6.3V 402

CERM

SYNC_DATE=08/24/2006

28

051-7225

A.0.0

88

SYNC_MASTER=(T9_MLB)

SB Misc

=PP3V3_S0_RSTBUF

EXTGPU_RST_QUAL_L

PCI_RST_L

RST_L_AND_GPU_PGOOD

EXTGPU_PWR_EN

EXTGPU_RST_L

PM_SB_PWROK

ENET_RESET_L

LCDBKLT_PLT_RST_L

PLT_RST_L

MAKE_BASE=TRUE

DEBUG_RESET_L

=PP3V3_S5_SB_PM

PCI_FW_RST_L

=GPU_HPD_ENABLE

=GPU_DDC_ENABLE

GPU_RESET_L

=PP3V3_S0_SB_PM

SB_RTC_X2

VR_PWRGOOD_DELAY

=PP3V3_S0_SB_PM

PPVBATT_G3_RTC

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

=PP3V42_G3H_SB_RTC

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.3 mm

PPVBATT_G3_RTC_R

MIN_NECK_WIDTH=0.2 mm

PM_SYSRST_L

XDP_DBRESET_L

SB_RTC_X1

LIO_PLT_RST_L

NB_RESET_L

FW_PLT_RST_L

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm VOLTAGE=3.3V

PP3V3_G3_SB_RTC

SB_RTC_RST_L

SB_SM_INTRUDER_L

SMC_LRESET_L

PM_ALL_GPU_PGOOD

VR_PWRGD_CLKEN_L

GPU_PGOOD_RC

RST_L_AND_GPU_PGOOD_L

=PP3V3_S0_RSTBUF

ALL_SYS_PWRGD

VR_PWRGD_CLKEN

SB_RTC_X1_R

IMVP6_PSI_L

MAKE_BASE=TRUE

CPU_PSI_L

GPU_IOENABLE_RC

MAKE_BASE=TRUE

GPU_RESET_R_L

C2805

1

2

R2806

1 2

C2806

1

2

R2805

1

2

R2800

2 1

C2830

1

2

R2825

1

2

C2810

1 2

C2811

1 2

Y2810

2 4

1 3

R2810

1 2

R2811

1

2

R2826

1 2

D2805

1

4

6

3

5

2

R2862

1 2

R2863

1 2

R2864

1 2

R2860

1 2

C2840

1

2

C2880

1

2

R2881

1 2

U2880

3

2

1

4

5

U2840

3

2

1

4

5

U2830

3

2

1

4

5

R2820

1

2

R2861

1 2

R2890

1 2

R2840

1

2

R2841

1

2

J2800

3

4

1 2

R2882

1 2

C2882

1

2

R2865

1 2

C2883

12

R2885

1 2

C2885

1

2

R2886

1

2

U2883

5

6

4

8

3

U2883

1

2

4

8

7

R2887

1 2

R2880

1 2

27

28

28 28

26

28

8

23

8

7

8

23

8

IN IN

OUT OUT

OUT

IN

OUT

OUT OUT OUT OUT

IN

BI

OUT

IN

BI

OUT

IN

OUT

IN

OUT

OUT OUT

IN

VSS_PCI

CLKREQ_7*

CLKREQ_8*

GPU_STOP*

REF_0/FS_C/TEST_SEL

48M/FS_A

DOT_96/27M

DOT_96*/27M_SS

SRC_8*

SRC_8

PCI_5/FCT_SEL

PCIF_0/ITP_EN

VDD_PCI

VDD_48

THRM_PAD

SRC_4*

CLKREQ_3*

SRC_3

SRC_0/LCD_CLK

SRC_0*/LCD_CLK*

CPU_1_MCH*

CPU_1_MCH

CPU_ITP*/SRC_10*

CPU_ITP/SRC_10

VSS_SRC

VSS_REF

VSS_CPU

VSS_48

SDA

PCIF_1

PCI_4

PCI_3

PCI_2

PCI_1

VSS_A

XTAL_OUT

CLKREQ_6*

CLKREQ_5*

CLKREQ_4*

CLKREQ_1*

SCL

CPU_0

SRC_1

SRC_2*

SRC_2

SRC_4

SRC_5*

SRC_5

SRC_7*

SRC_7

SRC_6*

SRC_6

VDD_REF

CPU_0*

SRC_3*

CPU_STOP*

PCI_STOP*

XTAL_IN

VDD_A

FS_B/TEST_MODE

VDD_CPU

SRC_1*

CKPWRGD/PD*

VDD_SRC

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

FW PCI 33MHz

(INT PD*)

(INT PU*)

0 1

FCT_SEL

27M

DOT_96+

PIN 6

27M w/SS

DOT_96-

PIN 7

PIN 10

LCD_CLK+

SRC_0+ SRC_0-

PIN 11

LCD_CLK-

(For Internal Graphics) (For External Graphics)

TP or GPU PGOOD

(INT PU*)

GMCH Display PLL A 96MHz (Int GFX)

NOTE: Pin 40 was PGMODE on SLG8LP537. Do not pull low

ICH PCI 33MHz

(INT PU*)

Spare 100MHz

From ICH

ICH SIO/LPC/REF 14.318MHz

ICH USB/Audio 48MHz

(Or 27MHz Spread & Non-Spread for Ext GFX)

PCIe Mini Card (AirPort) 100MHz

GMCH DMI/PCIe 100MHz

Spare 33MHz

Linda/LPC+ 33MHz

ExpressCard / Spare 100MHz

SMC LPC 33MHz

GMCH Display PLL B 100MHz (Int GFX)

From ICH

ICH DMI/PCIe 100MHz

ICH SATA 100MHz

GPU PCIe 100MHz (Ext GFX)

ITP/XDP Host Clock (FSB/4)

GMCH Host Clock (FSB/4)

One 0.1uF per power pin (place at pin).

CPU Host Clock (FSB/4)

CPU MHz

133.3

1

0

200.0

0

0 1

RSVD

(400.0)

100.0

(333.3)

166.6

1

0

1

0 0

00

0 1

0

1

0

1

One 10uF cap per rail.

FS_C FS_B FS_A

(266.6)

NEED TO CHECK CAP VALUE

on SLG8LP537 or device is set to CK410M mode.

Yukon PCIe 100MHz

(*) CLKREQ# internal pull-ups/downs only on SLG2AP101, not SLG8LP537.

(INT PU*)

NOTE: Pin 53 was REF_1 on SLG8LP537.

10UF

X5R 603

20%

6.3V

FERR-120-OHM-1.5A

0402

0.1UF

X5R 402

10% 16V

0.1UF

X5R 402

10% 16V

0.1UF

X5R 402

10% 16V

0.1UF

X5R 402

10% 16V

7

25 30

7

25 30

30 84

25

30 84

18pF

5% 50V CERM 402402

18pF

CERM

5%

50V

30 84

48

10UF

X5R 603

20%

6.3V

0.1UF

X5R 402

10% 16V

30 84

30

30 84

0.1UF

X5R 402

10% 16V

0.1UF

X5R 402

10% 16V

0.1UF

X5R 402

10% 16V

0.1UF

X5R 402

10% 16V

1UF

CERM 402

10%

6.3V

10UF

X5R 603

20%

6.3V

0.1UF

X5R 402

10% 16V

FERR-120-OHM-1.5A

0402

1UF

CERM

402

10%

6.3V

2.2

MF-LF

402

5%

1/16W

1

MF-LF

402

5%

1/16W

10UF

X5R 603

20%

6.3V

5%

1/16W

2.2

MF-LF

402

30 84

30

XDP

10K

MF-LF

402

5%

1/16W

30 84

25

30 84

7

16

CRITICAL

14.31818

5X3.2-SM

10UF

X5R 603

20%

6.3V

FERR-120-OHM-1.5A

0402

QFN

SLG2AP101

OMIT

30

Clock (CK505)

SYNC_MASTER=T9_NOME

SYNC_DATE=03/16/2007

A.0.0

8829

051-7225

CK505_SRC6_N

CK505_SRC8_N

CK505_CLKREQ8_L

CK505_SRC8_P

CK505_SRC3_P

CK505_CLKREQ6_L CK505_SRC7_N

CK505_SRC7_P CK505_CLKREQ7_L

CK505_DOT96_27M_P

TP_GPU_STOP_L

CLK_PWRGD

CK505_SRC6_P

=PP3V3_S0M_CK505

CK505_PCIF0_CLK_ITPEN

CK505_PCI5_CLK_FCTSEL

CK505_XTAL_OUT

CK505_SRC5_N

PP3V3_S0M_CK505_VDDA_R

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.5mm MIN_NECK_WIDTH=0.2mm

=PP3V3_S0M_CK505

=PP3V3_S0_CK505

CK505_REF0_FSC

CK505_48M_FSA

CK505_DOT96_27M_N

PP3V3_S0M_CK505_VDD48

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.5mm MIN_NECK_WIDTH=0.2mm

CK505_SRC4_N

CK505_CLKREQ3_L

CK505_LVDS_P

CK505_LVDS_N

CK505_CPU1_N CK505_CPU1_P

CK505_CPU2_ITP_SRC10_N CK505_CPU2_ITP_SRC10_P

=SMBUS_CK505_SDA

CK505_PCIF1_CLK

CK505_PCI4_CLK

CK505_PCI3_CLK

CK505_PCI2_CLK

CK505_PCI1_CLK

NB_CLKREQ_L

SB_SATA_CLKREQ_L

CK505_CLKREQ1_L

CK505_CPU0_P

CK505_SRC1_P

CK505_SRC1_N

CK505_SRC2_N CK505_SRC2_P

CK505_SRC4_P

PP3V3_S0M_CK505_VDD_CPU_SRC

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.5mm MIN_NECK_WIDTH=0.2mm

PP3V3_S0M_CK505_VDD_REF

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.5mm MIN_NECK_WIDTH=0.2mm

PP3V3_S0M_CK505_VDD_PCI

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.5mm MIN_NECK_WIDTH=0.2mm

CK505_CPU0_N

CK505_SRC3_N

PM_STPCPU_L

PM_STPPCI_L

CK505_FSB_TEST_MODE

CK505_XTAL_IN

MIN_LINE_WIDTH=0.5mm

PP3V3_S0M_CK505_VDDA

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2mm

=SMBUS_CK505_SCL

CK505_SRC5_P

C2910

1

2

C2912

1

2

L2902

1 2

C2913

1

2

C2915

1

2

C2909

1

2

C2990

1

2

C2989

1

2

C2907

1

2

C2908

1

2

C2906

1

2

C2905

1

2

C2904

1

2

C2903

1

2

C2911

1

2

C2901

1

2

C2902

1

2

L2901

1 2

C2900

1

2

R2901

1 2

R2902

1 2

C2914

1

2

R2900

1 2

R2903

1

2

Y2901

1 2

C2916

1

2

L2903

1 2

U2900

4

2

9

59

20

60

25

40

34

45

44

42

41

37

36

55

6

7

8

53

57 58 63 64 65

56

68

1

54

47 48

10

11

13

14

15

16

18

19

21

22

23

24

26

27

29

30

33

32

69

33843616749121728

35

5

39

46

62 66

52

31

51 50

30

29

30

8

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

BI

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

BI

OUT

IN

OUT

BI

OUT

IN

OUT

IN

OUT

G

D

S

IN

VER 1

VCC

A

1

0

B1

GND

B0

SEL

VER 1

VCC

A

1

0

B1

GND

B0

SEL

IN

OUT

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

FS_A, FS_B, FS_C (Host clock freq select)

(ICH8M DMI 100MHZ)

CK505 Configuration Straps

FCT_SEL (GFX clock select)

(TO MCH FS_A)

(ExpressCard 100MHz)

(ICH8M SATA 100MHZ)

0

(FROM CPU FS_B)

(FROM CPU FS_A)

(FROM CPU FS_C)

(TO ICH8M 14.318MHZ)

(TO/FROM CK505)

(TO MCH FS_B)

(TO CK505)

(TO MCH FS_C)

(TO/FROM CK505)

1 1

1

0

1

0 1

0

0 0

0 10

0

1

0

0 1

RSVD1

FS_C FS_B FS_A

(400.0)

(333.3)

(266.6)

133.3

100.0

166.6

200.0

CPU MHz

NO STUFF R3082, R3086 & R3090 for manual CPU clk frequency.

SLG8LP536 and CY28545-5)

(TO ICH8M USB 48MHZ)

(CPU HOST 167/200MHZ)

(GMCH HOST 167/200MHZ)

(GPU PCIe 100MHz)

(ENET 100MHZ)

(Ext GFX 27MHz)

(Ext GFX Spread 27MHz)

(ICH8M PCI 33MHZ)

(FIREWIRE PCI 33MHZ)

(SMC PCI 33MHZ)

(Int Gfx LVDS 100MHz)

(Note: HOST/SRC/GFX clock termination removed. Silego SL8GLP536 or equiv. support only)

CLKREQ Controls

(GMCH PEG/DMI 100MHZ)

(Reserved for TPM PCI 33MHZ) (Spare 33MHZ)

CLK Termination

(WIRELESS PCIe MINI 100MHZ)

(Only 100-200MHz supported by

(LINDA/LPC+ LPC 33MHZ)

(FW 100MHz)

(ITP HOST 167/200MHZ)

Unused Clocks

CLKREQ# pins. Support for SL8GLP537 or equiv. only.

Silego SLG2AP101 has internal pull-ups on all

GPU Clock Gating

NB and SATA CLKREQs are not remappable (and thus are not shown here).

29 84

7

16 84

7

16 84

29 84

29 84 35 84

35 84

24 84

29 84

38 84

45 84

24 84

34 84

34 84 29 84

29 84

7

47 84 29 84

24 84

402

10K

MF-LF

1/16W

5%

1/16W

5%

402

MF-LF

1K

MF-LF

402

5%

1/16W

29

29 84

23 84

29 84

MF-LF

1K

402

5%

1/16W

NO STUFF

1/16W

5%

MF-LF

0

402

10 79

1/16W

5%

402

MF-LF

0

MF-LF

1K

402

NO STUFF

1/16W

5%

34 84

29 84

7

14 84

29 84

9

66

9

66

7

14 84

29 84

10 84

25 84

33

1/16W

5%

402

MF-LF

29 84

10 84

MF-LF

1/16W

5%

402

1K

13 16 79

1K

5%

1/16W

402

MF-LF

13 16 79

10 79

1/16W

5%

402

MF-LF

0

MF-LF

402

5%

1/16W

1K

NO STUFF

1/16W

5%

402

MF-LF

1K

13 79 84

1K

1/16W

5%

402

MF-LF

13 16 79

25 84

33

402

1/16W

5%

MF-LF

29 84

13 79 84

33

MF-LF

5%

1/16W

402

MF-LF

402

5%

1/16W

33

7

22 84

7

22 84

29 84

33

402

1/16W

5%

MF-LF

402

MF-LF

1/16W

5%

33

402

1/16W

5%

MF-LF

33

5% 1/16W MF-LF

402

10K

MF-LF

1/16W

5%

402

MF-LF

402

2.2K

5%

1/16W

402

5%

MF-LF

1/16W

10K

NO STUFF

402

5%

MF-LF

1/16W

10K

34

7

25 29

7

25 29

29 84

29

72 86

SLG8LP537

SOT-363

2N7002DW-X-F

28 30 77

SLG8LP537

SC70

NC7SB3157P6X

SC70

GPU_SS_EXT

402

10V

0.1UF

20%

CERM

GPU_SS_EXT

0.1UF

402

CERM

10V

20%

SLG8LP537

28 30 77

35

1/16W MF-LF

402

5%

0

SLG2AP101

0

5%

402

MF-LF

1/16W

SLG2AP101

29

5% 1/16W MF-LF

402

0

SLG2AP101

29 84

SYNC_MASTER=(MASTER)

051-7225

30 88

A.0.0

SYNC_DATE=08/23/2006

Clock Termination

TP_GPU_STOP_L

GPU_STOP_L

MAKE_BASE=TRUE

PM_ALL_GPU_PGOOD

=ENET_CLKREQ_L

MAKE_BASE=TRUE

ENET_CLKREQ_L

TP_CK505_CLKREQ7_L

MAKE_BASE=TRUE

CK505_CLKREQ7_L

EXCARD_CLKREQ_L

MAKE_BASE=TRUE

MINI_CLKREQ_L

MAKE_BASE=TRUE

CK505_CLKREQ6_L

CK505_CLKREQ3_L

CK505_CLKREQ8_L

GPU_CLK27M_SS

=PP3V3_S0_GPUCLKGATE

GPU_CLK27M

GPU_CLK27M_SS_GATED

GPU_CLK27M_GATED

PM_ALL_GPU_PGOOD

MAKE_BASE=TRUE

PEG_CLKREQ_L

CK505_SRC8_P CK505_SRC8_N

CK505_DOT96_27M_P

CK505_DOT96_27M_N

PCI_CLK33M_LPCPLUS

CK505_LVDS_P CK505_LVDS_N

MAKE_BASE=TRUE

NB_CLK100M_DPLLSS_N

MAKE_BASE=TRUE

NB_CLK100M_DPLLSS_P

CK505_SRC1_P

CK505_SRC3_P

CK505_CLKREQ1_L

PCIE_CLK100M_MINI_P

MAKE_BASE=TRUE

PCIE_CLK100M_MINI_N

MAKE_BASE=TRUE

NB_CLK100M_PCIE_N

MAKE_BASE=TRUE

FSB_CLK_CPU_P

=PP1V25R1V05_S0_FSB_NB

MAKE_BASE=TRUE

NB_CLK100M_PCIE_P

=PP3V3_S0M_CK505

MAKE_BASE=TRUE

PCIE_CLK100M_EXCARD_N

CK505_PCI4_CLK

CK505_PCI2_CLK

MAKE_BASE=TRUE

TP_CK505_PCI4_CLK

TP_CK505_PCI2_CLK

MAKE_BASE=TRUE

PM_STPCPU_L

PM_STPPCI_L

CK505_CLK27M_SS

MAKE_BASE=TRUE

TP_PCIE_CLK100M_SRC7P

CK505_SRC4_N

=PP1V25R1V05_S0_FSB_NB

CK505_CPU2_ITP_SRC10_N

PCIE_CLK100M_ENET_P

MAKE_BASE=TRUE

PCIE_CLK100M_ENET_N

MAKE_BASE=TRUE

TP_PCIE_CLK100M_SRC7N

MAKE_BASE=TRUE

CK505_SRC7_N

CK505_SRC7_P

CK505_SRC6_P CK505_SRC6_N

SB_CLK100M_SATA_P

MAKE_BASE=TRUE

SB_CLK100M_SATA_N

CK505_SRC5_P CK505_SRC5_N

CK505_SRC4_P

CK505_SRC3_N

MAKE_BASE=TRUE

SB_CLK100M_DMI_N

MAKE_BASE=TRUE

SB_CLK100M_DMI_P

CK505_SRC2_N

MAKE_BASE=TRUE

PEG_CLK100M_GPU_N

MAKE_BASE=TRUE

PEG_CLK100M_GPU_P

CK505_CPU2_ITP_SRC10_P

MAKE_BASE=TRUE

XDP_CLK_N

MAKE_BASE=TRUE

XDP_CLK_P

MAKE_BASE=TRUE

FSB_CLK_NB_N

MAKE_BASE=TRUE

FSB_CLK_NB_PCK505_CPU1_P

CK505_CPU1_N

CK505_CPU0_P CK505_CPU0_N

MAKE_BASE=TRUE

FSB_CLK_CPU_N

GPU_CLK27M_SS

PCI_CLK33M_SMC

PCI_CLK33M_SB

PCI_CLK33M_FW

CK505_PCI3_CLK

GPU_CLK27M

CK505_PCIF0_CLK_ITPEN

CK505_PCI1_CLK

NB_BSEL<2>

NB_BSEL<1>

CK505_48M_FSA

NB_BSEL<0>

SB_CLK14P3M_TIMER

CK505_REF0_FSC

CPU_BSEL<2>

CPU_BSEL<1>

CPU_BSEL<0>

SB_CLK48M_USBCTLR

CK505_FSC

CK505_FSB_TEST_MODE

=PP1V25R1V05_S0_FSB_NB

CK505_CLK27M

MAKE_BASE=TRUE

CK505_PCIF1_CLK

MAKE_BASE=TRUE

PCIE_CLK100M_EXCARD_P

CK505_SRC2_P

CK505_SRC1_N

=PP3V3_S0_CK505

CK505_PCI5_CLK_FCTSEL

CK505_FSA

R3067

1

2

R3083

1

2

R3084

1

2

R3080

1

2

R3082

1 2

R3086

1 2

R3087

1

2

R3032

1 2

R3081

1 2

R3085

1 2

R3090

1 2

R3088

1

2

R3091

1

2

R3089

1 2

R3034

1 2

R3024

1 2

R3025

1 2

R3026

1 2

R3027

1 2

R3028

1 2

R3030

1 2

R3035

2

1

R3033

2

1

R3046

1 2

R3047

1 2

Q3050

6

2

1

U3050

43

1

2

6

5

U3055

43

1

2

6

5

C3055

1 2

C3050

1 2

R3050

1

2

R3055

1

2

R3051

1

2

30

86

14

29

14

86

14

29

30

8

30

8

30

84

8

84

VSS7

VSS12

VSS9

KEY

DQ57

DQ51

DQS6

DQ43

DQ42

DQ40

DQ34

DQ1

DQ0

VSS1

DQS0* DQS0 VSS6 DQ2 DQ3

DQ8 DQ9 VSS10 DQS1* DQS1

DQ10 DQ11 VSS14

VSS16 DQ16 DQ17 VSS18 DQS2* DQS2 VSS21 DQ18 DQ19 VSS23 DQ24 DQ25 VSS25 DM3 NC1 VSS27 DQ26 DQ27 VSS29 CKE0 VDD0 NC2 BA2 VDD2 A12 A9 A8 VDD4 A5 A3 A1 VDD6 A10/AP BA0 WE* VDD8 CAS* NC/S1* VDD10 NC/ODT1 VSS31 DQ32 DQ33 VSS33 DQS4* DQS4 VSS36

DQ35 VSS38

DQ41 VSS40 DM5 VSS41

VSS43 DQ48 DQ49 VSS45 NC_TEST VSS47 DQS6*

VSS49 DQ50

VSS51 DQ56

VSS53 DM7 VSS55 DQ58 DQ59 VSS57 SDA SCL VDDSPD

DM6

DQ55

DQ61

DQ46 DQ47

DQ12

DM1

DM0

DQ7

DQ13

VSS11

CK0

CK0*

VSS13

DQ14 DQ15

VSS15

VSS17

DQ20 DQ21

VSS19

NC0 DM2

VSS22

DQ22 DQ23

VSS24

DQ28

DQ29 VSS26 DQS3*

DQS3 VSS28

DQ30

DQ31 VSS30

NC/CKE1

VDD1

NC/A15 NC/A14

VDD3

A11

A7 A6

VDD5

A4 A2 A0

VDD7

BA1

RAS*

S0* VDD9 ODT0

NC/A13

VDD11

NC3

VSS32

DQ36 DQ37

VSS34

DM4

VSS35

DQ38 DQ39

VSS37

DQ44 DQ45

VSS39 DQS5*

DQS5

VSS42

VSS44

DQ52 DQ53

VSS46

CK1 CK1*

VSS48

VSS50

DQ54

VSS52

DQ60

VSS54 DQS7*

DQS7

VSS56

DQ62 DQ63

VSS58

SA0

SA1

DQ5 VSS2

VREF

VSS4

VSS8

VSS0

DQ4

VSS5

DQ6

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Page Notes

Power aliases required by this page:

- =PP0V9_S3M_MEM_DIMMVREFA

- =PP1V8_S3M_MEM_A

- =I2C_SODIMMA_SCL

(NONE)

BOM options provided by this page:

- =I2C_SODIMMA_SDA

- =PPSPD_S0M_MEM_A (2.5V - 3.3V)

NC

ADDR=0xA0(WR)/0xA1(RD)

(For return current)

NC

516-0140

NC

DDR2 Bypass Caps

"Factory" (thru-hole) slot

NC

Signal aliases required by this page:

402

6.3V CERM

1UF

10%

402

6.3V CERM

1UF

10%

10UF

X5R 603

20%

6.3V

402

6.3V CERM

1UF

10%

10UF

X5R 603

20%

6.3V

402

6.3V CERM

1UF

10%

402

10%

6.3V CERM

1UF

402

10%

6.3V CERM

1UF

402

6.3V CERM

1UF

10%

402

6.3V CERM

1UF

10%

402

10%

6.3V CERM

1UF

402

10%

6.3V CERM

1UF

402

6.3V CERM

1UF

10%

402

6.3V CERM

1UF

10%

0.1uF

CERM 402

20% 10V

2.2uF

20%

603

CERM1

6.3V

F-RT-TH1

DDR2-SODIMM-DUAL

CRITICAL

SYNC_DATE=08/24/2006

SYNC_MASTER=(M59_SYNC)

DDR2 SO-DIMM Connector A

051-7225

A.0.0

8831

MEM_A_DM<7>

MEM_A_DQS_N<6>

MEM_A_DQ<22> MEM_A_DQ<19>

=PP1V8_S3M_MEM_A

MEM_A_A<14>

MEM_A_A<15>

MEM_CKE<1>

MEM_A_DM<3>

MEM_A_A<6>

=I2C_SODIMMA_SCL

MEM_A_DQS_N<4>

MEM_A_A<0>

MEM_A_BS<1>

MEM_A_DQ<14>

MEM_A_DM<1>

MEM_A_DQ<2>

MEM_A_DQ<13>

MEM_A_DQS_N<1> MEM_A_DQS_P<1>

MEM_A_DQ<10> MEM_A_DQ<11>

MEM_A_DQ<7> MEM_A_DQ<0>

MEM_A_DQS_N<0> MEM_A_DQS_P<0>

MEM_A_DQ<4>

MEM_A_DQ<17> MEM_A_DQ<21>

MEM_A_DQS_N<2> MEM_A_DQS_P<2>

MEM_A_DQ<23> MEM_A_DQ<16>

MEM_A_DQ<31> MEM_A_DQ<27>

MEM_A_DQ<30> MEM_A_DQ<28>

MEM_CKE<0>

=PP1V8_S3M_MEM_A

MEM_A_BS<2>

MEM_A_A<12> MEM_A_A<9> MEM_A_A<8>

MEM_A_A<5> MEM_A_A<3> MEM_A_A<1>

MEM_A_A<10> MEM_A_BS<0> MEM_A_WE_L

MEM_A_CAS_L MEM_CS_L<1>

MEM_ODT<1>

MEM_A_DQ<36> MEM_A_DQ<38>

MEM_A_DQS_P<4>

MEM_A_DQ<37> MEM_A_DQ<34>

MEM_A_DQ<56> MEM_A_DQ<59>

MEM_A_DQ<54>

MEM_A_DQS_P<6>

MEM_A_DQ<48> MEM_A_DQ<53>

MEM_A_DQ<43> MEM_A_DQ<42>

MEM_A_DM<5>

MEM_A_DQ<46> MEM_A_DQ<41>

=I2C_SODIMMA_SDA

=PPSPD_S0M_MEM_A

MEM_A_RAS_L MEM_CS_L<0>

MEM_ODT<0> MEM_A_A<13>

MEM_A_DQ<39>

MEM_A_DM<4>

MEM_A_DQ<33> MEM_A_DQ<32>

MEM_A_DQ<63> MEM_A_DQ<62>

MEM_A_DQS_N<7> MEM_A_DQS_P<7>

MEM_A_DQ<57> MEM_A_DQ<61>

MEM_A_DQ<55> MEM_A_DQ<50>

MEM_CLK_P<1> MEM_CLK_N<1>

MEM_A_DM<6>

MEM_A_DQ<49> MEM_A_DQ<52>

MEM_A_DQ<45> MEM_A_DQ<40>

MEM_A_DQS_N<5> MEM_A_DQS_P<5>

MEM_A_DQ<44> MEM_A_DQ<47>

MEM_A_DQ<35>

MEM_A_DQ<8> MEM_A_DQ<12>

MEM_A_DQ<3>

MEM_A_DM<0>

MEM_CLK_P<0> MEM_CLK_N<0>

MEM_A_DQ<1> MEM_A_DQ<5>

MEM_A_DQ<18> MEM_A_DQ<20>

PM_EXTTS_L<0> MEM_A_DM<2>

MEM_A_DQ<26> MEM_A_DQ<24>

MEM_A_DQS_N<3> MEM_A_DQS_P<3>

MEM_A_DQ<25> MEM_A_DQ<29>

MEM_A_A<11> MEM_A_A<7>

MEM_A_A<4> MEM_A_A<2>

MEM_A_DQ<9> MEM_A_DQ<15>

MEM_A_DQ<6>

=PP0V9_S3M_MEM_DIMMVREFA

=PP1V8_S3M_MEM_A

MEM_A_DQ<51>

MEM_A_DQ<60>

MEM_A_DQ<58>

C3113

1

2

C3112

1

2

C3109

1

2

C3111

1

2

C3108

1

2

C3110

1

2

C3119

1

2

C3118

1

2

C3117

1

2

C3116

1

2

C3121

1

2

C3120

1

2

C3115

1

2

C3114

1

2

C3100

1

2

C3101

1

2

J3100

102B

105B

90B89B

101B

100B

99B

98B97B

94B

92B

93B

91B

107B

106B

85B

113B

30B 32B

164B 166B

79B

10B

26B

52B

67B

130B

147B

170B

185B

5B

35B 37B

20B 22B

36B 38B

43B 45B

55B 57B

7B

44B 46B

56B 58B

61B 63B

73B 75B

62B 64B

17B

74B 76B

123B 125B

135B 137B

124B 126B

134B 136B

19B

141B 143B

151B 153B

140B 142B

152B 154B

157B 159B

4B

173B 175B

158B 160B

174B 176B

179B 181B

189B 191B

6B

180B 182B

192B 194B

14B 16B

23B 25B

13B

11B

31B

29B

51B

49B

70B

68B

131B

129B

148B

146B

169B

167B

188B

186B

201

202

116B

86B

84B

80B

119B

115B

50B

69B

83B

120B

163B

114B

108B 110B

198B 200B

197B

195B

81B

117B 118B

82B

87B 88B

95B 96B

103B 104B

111B 112B

199B

1B 2B

27B 28B

33B 34B

39B 40B

41B 42B

47B 48B

3B

53B 54B

59B 60B

65B 66B

71B 72B

77B

8B

78B

121B 122B

127B 128B

132B

133B

138B

139B

144B

145B

149B 150B

155B 156B

161B 162B

165B

168B

171B

9B

172B

177B 178B

183B 184B

187B

190B

193B

196B

12B

15B

18B

21B

24B

109B

87

81

87

81

87

81

31

33

81

33

81

33

81

33

31

33

81

33

81

45

81

33

81

31

81

17

8

16

9

16

17

48

17

16

8

17

16

17

48

8

17

16

17

16

17

16

17

16

17

8

17

VSS2

DQS0*

DQ5

VSS0

DQ4

VSS5

DQ6

VSS29

DM0

VSS7

DM1

DQ7

VDD1

DQ30

DQ23

VSS22

NC/ODT1

RAS*

SA1

SA0

VSS58

DQ63

DQ62

VSS56

DQS7

DQS7*

VSS54

DQ60

VSS52

DQ54

VSS50

VSS48

CK1*

CK1

VSS46

DQ53

DQ52

VSS44

VSS42

DQS5

DQS5*

VSS39

DQ45

DQ44

VSS37

DQ39

DQ38

VSS35

DM4

VSS34

DQ37

DQ36

VSS32

NC3

VDD11

NC/A13

ODT0

VDD9

S0*

BA1

VDD7

A0

A2

A4

VDD5

A6

A7

A11

VDD3

NC/A14

NC/A15

NC/CKE1

VSS30

DQ31

DQS3

DQ29

DQ28

VSS24

DQ22

DM2

NC0

VSS19

DQ21

DQ20

VSS17

VSS15

DQ15

DQ14

VSS13

CK0*

CK0

VSS11

DQ13

DQ12

DQ47

DQ46

DQ61

DQ55

DM6

VDDSPD

SCL

SDA

VSS57

DQ59

DQ58

VSS55

DM7

VSS53

DQ56

VSS51

DQ50

VSS49

DQS6*

VSS47

NC_TEST

VSS45

DQ49

DQ48

VSS43

VSS41

DM5

VSS40

DQ41

VSS38

DQ35

VSS36

DQS4

DQS4*

VSS33

DQ33

DQ32

VSS31

VDD10

NC/S1*

CAS*

VDD8

WE*

BA0

A10/AP

VDD6

A1

A3

A5

VDD4

A8

A9

A12

VDD2

BA2

NC2

VDD0

CKE0

DQ27

DQ26

VSS27

NC1

DM3

DQ25

DQ24

VSS23

DQ19

DQ18

VSS21

DQS2

DQS2*

VSS18

DQ17

DQ16

VSS16

VSS14

DQ11

DQ10

VSS12

DQS1

DQS1*

DQ9

DQ8

VSS8

DQ3

DQ2

VSS6

DQS0

VREF

DQ34

DQ40

DQ42 DQ43

DQS6

DQ51

DQ57

KEY

VSS9

DQ1 VSS4

DQ0

VSS1

DQS3*

VSS26

VSS28

VSS25

VSS10

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

- =PP1V8_S3M_MEM_B

- =PPSPD_S0M_MEM_B (2.5V - 3.3V)

- =PP0V9_S3M_MEM_DIMMVREFB

- =I2C_SODIMMB_SDA

- =I2C_SODIMMB_SCL

(NONE)

BOM options provided by this page:

NC

(For return current)

DDR2 Bypass Caps

516S0471

"Expansion" (surface-mount) slot

Signal aliases required by this page:

Power aliases required by this page:

Page Notes

ADDR=0xA4(WR)/0xA5(RD)

Resistor prevents pwr-gnd short

402

CERM

1UF

10%

6.3V

402

CERM

1UF

10%

6.3V

20% 603

X5R

10UF

10V

0.1uF

CERM 402

20%

603

20%

6.3V

X5R

10UF

402

CERM

1UF

10%

6.3V

10V

0.1uF

CERM 402

20%

10V

0.1uF

CERM 402

20%

0.1uF

CERM 402

20%

10V

402

CERM

1UF

10%

6.3V

10V

0.1uF

CERM 402

20%

0.1uF

10V

CERM 402

20%

402

CERM

1UF

10%

6.3V

402

CERM

1UF

10%

6.3V

1/16W 402

MF-LF

5%

10K

0.1uF

CERM 402

20% 10V

2.2uF

20%

603

CERM1

6.3V

DDR2-SODIMM-DUAL

CRITICAL

F-RT-SM-M9

8832

051-7225

A.0.0

SYNC_MASTER=(M59_SYNC)

SYNC_DATE=08/24/2006

DDR2 SO-DIMM Connector B

MEM_B_CAS_L

MEM_B_DQ<33>

MEM_B_DQS_N<4>

MEM_B_DM<6>

MEM_B_DQ<49>

MEM_B_DQ<44>

MEM_B_A<10>

MEM_CS_L<3>

MEM_ODT<3>

MEM_B_DQ<34>

MEM_B_DQ<36>

MEM_CLK_P<3> MEM_CLK_N<3>

MEM_B_DQ<52>

MEM_B_DQ<46>

SODIMM_B_SA1

=PPSPD_S0M_MEM_B

MEM_B_DQ<43>

=PPSPD_S0M_MEM_B

MEM_B_A<7>

MEM_B_A<4>

MEM_B_DQS_P<1>

MEM_B_DQ<12>

MEM_B_DQ<6>

MEM_B_DQS_N<1>

MEM_B_DQ<29>

MEM_B_DQ<31>

MEM_B_DQS_P<3>

MEM_B_DQ<58>

PM_EXTTS_L<1>

MEM_B_DQ<41>

MEM_B_DQS_P<5>

MEM_B_DQS_N<5>

MEM_B_DQ<53>

MEM_B_DQ<54>

MEM_B_DQ<63>

MEM_B_DQS_P<7>

MEM_B_DQS_N<7>

MEM_B_DQ<59>

MEM_B_DQ<56>

MEM_B_DQ<39>

MEM_B_DQ<38>

MEM_B_DM<4>

MEM_B_DQ<37>

MEM_B_DQ<32>

MEM_B_A<13>

=PP1V8_S3M_MEM_B

MEM_CS_L<2>

MEM_B_A<2>

MEM_B_A<6>

MEM_B_A<14>

MEM_B_A<15>

MEM_B_DQ<17>

MEM_B_DQ<5>

MEM_CLK_N<4>

MEM_CLK_P<4>

MEM_B_DM<0>

MEM_B_DM<1>

MEM_B_DQ<9>

=I2C_SODIMMB_SCL

=I2C_SODIMMB_SDA

MEM_B_DQ<45>

MEM_B_DQ<42>

MEM_B_DM<5>

MEM_B_DQ<47>

MEM_B_DQ<40>

MEM_B_DQ<55>

MEM_B_DQ<50>

MEM_B_DQS_P<6>

MEM_B_DQS_N<6>

MEM_B_DQ<51>

MEM_B_DQ<48>

MEM_B_DQ<62>

MEM_B_DQ<61>

MEM_B_DM<7>

MEM_B_DQ<60>

MEM_B_DQ<57>

MEM_B_DQ<35>

MEM_B_DQS_P<4>

MEM_B_DQ<4>

MEM_B_WE_L

MEM_B_BS<0>

MEM_B_A<1>

MEM_B_A<3>

MEM_B_A<5>

MEM_B_A<8>

MEM_B_A<9>

MEM_B_A<12>

MEM_B_BS<2>

MEM_CKE<3>

MEM_B_DQ<25>

MEM_B_DQ<27>

MEM_B_DM<3>

MEM_B_DQ<24>

MEM_B_DQ<20>

MEM_B_DQS_P<2>

MEM_B_DQS_N<2>

MEM_B_DQ<19>

MEM_B_DQ<21>

MEM_B_DQ<1>

MEM_B_DQS_P<0>

MEM_B_DQS_N<0>

MEM_B_DQ<2>

MEM_B_DQ<7>

MEM_B_DQ<13>

MEM_B_DQ<10>

MEM_B_DQ<15>

MEM_CKE<4>

MEM_B_BS<1>

MEM_B_DQ<0>

MEM_B_DQ<18>

MEM_B_DM<2>

MEM_B_DQ<16>

MEM_B_DQ<26> MEM_B_DQ<28>

MEM_B_DQ<30>

MEM_B_A<11>

MEM_B_A<0>

MEM_B_RAS_L

MEM_ODT<2>

MEM_B_DQ<22>

MEM_B_DQS_N<3>

MEM_B_DQ<11>

MEM_B_DQ<14>

MEM_B_DQ<3>

MEM_B_DQ<8>

=PP1V8_S3M_MEM_B

MEM_B_DQ<23>

=PP0V9_S3M_MEM_DIMMVREFB

=PP1V8_S3M_MEM_B

C3213

1

2

C3212

1

2

C3209

1

2

C3211

1

2

C3208

1

2

C3210

1

2

C3219

1

2

C3218

1

2

C3217

1

2

C3216

1

2

C3221

1

2

C3220

1

2

C3215

1

2

C3214

1

2

R3200

1

2

C3200

1

2

C3201

1

2

J3200

102A

105A

90A89A

101A

100A

99A

98A97A

94A

92A

93A

91A

107A

106A

85A

113A

30A 32A

164A 166A

79A

10A

26A

52A

67A

130A

147A

170A

185A

5A

35A 37A

20A 22A

36A 38A

43A 45A

55A 57A

7A

44A 46A

56A 58A

61A 63A

73A 75A

62A 64A

17A

74A 76A

123A 125A

135A 137A

124A 126A

134A 136A

19A

141A 143A

151A 153A

140A 142A

152A 154A

157A 159A

4A

173A 175A

158A 160A

174A 176A

179A 181A

189A 191A

6A

180A 182A

192A 194A

14A 16A

23A 25A

13A

11A

31A

29A

51A

49A

70A

68A

131A

129A

148A

146A

169A

167A

188A

186A

201

202

203

204

116A

86A

84A

80A

119A

115A

50A

69A

83A

120A

163A

114A

108A 110A

198A 200A

197A

195A

81A

117A 118A

82A

87A 88A

95A 96A

103A 104A

111A 112A

199A

1A 2A

27A 28A

33A 34A

39A 40A

41A 42A

47A 48A

3A

53A 54A

59A 60A

65A 66A

71A 72A

77A

8A

78A

121A 122A

127A 128A

132A

133A

138A

139A

144A

145A

149A 150A

155A 156A

161A 162A

165A

168A

171A

9A

172A

177A 178A

183A 184A

187A

190A

193A

196A

12A

15A

18A

21A

24A

109A

81

87

81

81 81

81

87

33

81

33

81

32

81

32

33

81 81

81

45

81

33

32

33

81

33

81

33

81

33

81

32

81

32

17

16

17

16

17

8

17

8

17

17 17

17

16

17

8

16

17

16

9

17

16

17

48

17

16

17

16

17

16

17

8

17

8

IN

IN IN

IN

IN IN

IN

IN IN

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Ensure CS_L and ODT resistors are close to SO-DIMM connector

One cap for each side of every RPAK, one cap for every two discrete resistors

CERM

20% 10V

0.1uF

402

CERM

20% 10V

0.1uF

402

CERM

20% 10V

0.1uF

402

CERM

20% 10V

0.1uF

402

CERM

20% 10V

0.1uF

402

CERM

20% 10V

0.1uF

402

CERM

20% 10V

0.1uF

402

CERM

20% 10V

0.1uF

402

20% 10V CERM

0.1uF

402

CERM

20% 10V

0.1uF

402

17 32 81

16 32 81

SM-LF1/16W

5%

56

SM-LF1/16W

5%

56

17 31 81

17 32 81

17 31 81

16 32 81

16 31 81

16 32 81

16 31 81

17 32 81

17 31 81

16 31 81

17 31 81

17 32 81

16 32 81

17 32 81

17 31 81

17 32 81

16 32 81

17 32 81

56

5%

1/16W MF-LF

402

16 31 81

SM-LF1/16W

5%

56 56

5%

1/16W SM-LF

SM-LF1/16W

5%

56

SM-LF1/16W

5%

56

1/16W

5%

56

SM-LF

SM-LF1/16W

5%

56

1/16W

5%

56

SM-LF

56

5%

1/16W SM-LF

1/16W

5%

56

SM-LF

SM-LF1/16W

5%

56

SM-LF

56

5%

1/16W

56

5%

1/16W SM-LF

SM-LF

56

5%

1/16W

SM-LF1/16W

5%

56

SM-LF1/16W

5%

56

SM-LF1/16W

5%

56

1/16W

5%

56

SM-LF

56

5%

1/16W SM-LF

56

5%

1/16W SM-LF

SM-LF1/16W

5%

56

5%

1/16W SM-LF

SM-LF1/16W

5%

56

5%

1/16W SM-LF

SM-LF

56

5%

1/16W

56

5%

1/16W SM-LF

SM-LF

56

5%

1/16W

SM-LF1/16W

5%

56

SM-LF

56

5%

1/16W

56

5%

1/16W SM-LF

1/16W

5%

56

SM-LF

56

5%

1/16W SM-LF

1/16W

5%

56

SM-LF

56

5%

1/16W SM-LF

SM-LF

56

5%

1/16W

56

5%

1/16W SM-LF

1/16W

5%

56

SM-LF

56

5%

1/16W SM-LF

SM-LF

56

5%

1/16W

SM-LF1/16W

5%

56

1/16W

5%

56

SM-LF

SM-LF1/16W

5%

56

1/16W

5%

56

SM-LF

56

5%

1/16W SM-LF

1/16W

5%

56

SM-LF

56

5%

1/16W SM-LF

1/16W

5%

56

SM-LF

56

5%

1/16W SM-LF

1/16W

5%

56

SM-LF

SM-LF1/16W

5%

56

SM-LF

56

5%

1/16W

MF-LF1/16W

5%

56

402

16 32 81

10V

20% CERM

0.1uF

402

17 31 81

16 31 81

17 31 81

16 32 81

CERM

20% 10V

0.1uF

402

CERM

20% 10V

0.1uF

402

CERM

20% 10V

0.1uF

402

CERM

20% 10V

0.1uF

402

CERM

20% 10V

0.1uF

402

CERM

20% 10V

0.1uF

402

CERM

20% 10V

0.1uF

10V

20% CERM

0.1uF

402

CERM

20% 10V

0.1uF

402

CERM

20% 10V

0.1uF

402

CERM

20% 10V

0.1uF

402

CERM

20% 10V

0.1uF

402

CERM

20% 10V

0.1uF

402

CERM

20% 10V

0.1uF

402

CERM

20% 10V

0.1uF

402

CERM

20% 10V

0.1uF

402

SYNC_DATE=11/14/2006

SYNC_MASTER=(T9_NOME)

Memory Active Termination

051-7225

A.0.0

8833

MEM_A_A<10>

=PP0V9_S0M_MEM_TERM

MEM_B_A<10>

MEM_A_A<3>

MEM_B_A<3>

MEM_ODT<3>

MEM_B_WE_L

MEM_B_CAS_L

MEM_B_A<13>

MEM_ODT<2>

MEM_CS_L<2>

MEM_B_BS<2>

MEM_B_A<14>

MEM_A_A<9>

MEM_A_A<4>

MEM_A_A<0>

MEM_ODT<0>

MEM_CKE<1>

MEM_CKE<0>

MEM_B_A<6>

MEM_B_A<8> MEM_B_A<9>

MEM_B_A<0>

MEM_B_BS<1>

MEM_B_A<11>

MEM_A_BS<1>

MEM_B_BS<0>

MEM_CS_L<1>

MEM_A_CAS_L

MEM_B_RAS_L

MEM_B_A<7>

MEM_CKE<4>

MEM_A_A<13>

MEM_A_WE_L

MEM_A_RAS_L

MEM_CS_L<3>

MEM_CS_L<0>

MEM_A_BS<0>

MEM_A_A<12>

MEM_A_A<5>

MEM_A_A<2>

MEM_A_A<1>

MEM_B_A<5>

MEM_A_A<8>

MEM_A_A<14>

MEM_ODT<1>

MEM_CKE<3>

MEM_B_A<2>

MEM_B_A<1>

MEM_B_A<12>

MEM_B_A<4>

MEM_A_BS<2>

MEM_A_A<11>

MEM_A_A<7>

MEM_A_A<6>

C3348

1

2

C3346

1

2

C3336

1

2

C3334

1

2

C3332

1

2

C3330

1

2

C3312

1

2

C3310

1

2

C3307

1

2

C3305

1

2

C3302

1

2

C3300

1

2

C3344

1

2

C3342

1

2

C3340

1

2

C3338

1

2

C3352

1

2

C3356

1

2

C3354

1

2

C3350

1

2

C3360

1

2

C3364

1

2

C3368

1

2

C3366

1

2

C3362

1

2

C3358

1

2

RP3358

2 7

RP3300

3 6

R3370

1 2

RP3346

4 5

RP3330

1 8

RP3342

2 7

RP3330

3 6

RP3330

4 5

RP3330

2 7

RP3342

4 5

RP3342

3 6

RP3342

1 8

RP3358

4 5

RP3346

3 6

RP3358

3 6

RP3346

1 8

RP3346

2 7

RP3358

1 8

RP3366

4 5

RP3366

1 8

RP3366

2 7

RP3350

1 8

RP3334

4 5

RP3338

2 7

RP3354

3 6

RP3354

4 5

RP3310

1 8

RP3310

4 5

RP3310

2 7

RP3362

3 6

RP3350

4 5

RP3350

2 7

RP3354

2 7

RP3350

3 6

RP3354

1 8

RP3338

4 5

RP3338

3 6

RP3338

1 8

RP3334

2 7

RP3334

1 8

RP3334

3 6

RP3300

4 5

RP3305

2 7

RP3366

3 6

RP3300

2 7

RP3310

3 6

RP3362

2 7

RP3305

4 5

RP3305

1 8

RP3305

3 6

RP3300

1 8

RP3362

1 8

RP3362

4 5

R3371

1 2

C3370

1

2

8

IN

IN IN

IN

BI

BI IN IN

OUT OUT IN

OUT OUT OUT

IN

IN IN

IN

OUT OUT

OUT IN

IN

OUT

BI IN

BI BI

IN BI

IN IN

OUT OUT

IN IN

IN

OUT IN

IN OUT

BI BI

IN

OUT OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NC

516S0348

(Input from LIO) (Output to LIO)

(Output to LIO)

Place caps close to SB

Left I/O Board Connector

Pull-up on LIO, FETs to GND on MLB

24

77

QT500806-L121-9F

CRITICAL

M-ST-SM

46

36

45 46

36 40 45 46

45 46

30

28

24 46

13 24

49

45

45 46

65

45 46

49

65

45

25 35

48

24 82

48

30 84

24 83

30 84

23 82

24 82

10% 16V X5R 402

0.1uF

10% X5R

402

16V

0.1uF

10% 16V X5R 402

402

X5R

0.1uF

10% 16V

24 83

24

SYNC_DATE=08/24/2006

SYNC_MASTER=(M59_SYNC)

Left I/O Board Connector

051-7225

A.0.0

8834

PM_WLAN_EN_L

USB_MINI_N

SMC_ENRGYSTR_LDO_EN

MAKE_BASE=TRUE

PCIE_EXCARD_D2R_N

PCIE_MINI_R2D_N

USB_EXTB_N

=PP1V5_S0_LIO

HDA_SDOUT

LIO_S3_EN

SMC_EXCARD_PWR_EN

USB_MINI_P

TP_PCIE_EXCARD_R2D_C_P

TP_PCIE_EXCARD_R2D_C_N

MAKE_BASE=TRUE

PCIE_EXCARD_R2D_C_P

PCIE_EXCARD_R2D_C_N

MAKE_BASE=TRUE

TP_PCIE_EXCARD_D2R_N TP_PCIE_EXCARD_D2R_P

PCIE_MINI_R2D_C_P

PCIE_MINI_R2D_C_N

LIO_DCIN_ISENSE

LIO_S0_EN_L

SMC_BC_ACOK

SMC_EXCARD_CP

SMC_BATT_TRICKLE_EN_L

SMC_BATT_ISET

SMC_SYS_ISET

LIO_BATT_ISENSE

USB_EXTB_OC_L

EXCARD_OC_L

=PPDCIN_G3H_LIO_CONN

=PP3V42_G3H_LIO

LIO_PLT_RST_L

MINI_CLKREQ_L

EXCARD_CLKREQ_L

LCDBKLT_PWREN

LCDBKLT_PWM_UNBUF

SMC_BATT_CHG_EN

SMC_ADAPTER_EN

SYS_ONEWIRE

PCIE_EXCARD_R2D_P

PCIE_EXCARD_R2D_N

MAKE_BASE=TRUE

PCIE_EXCARD_D2R_P

PCIE_CLK100M_EXCARD_P

PCIE_CLK100M_EXCARD_N

PCIE_MINI_R2D_P

PCIE_MINI_D2R_P

PCIE_MINI_D2R_N

PCIE_CLK100M_MINI_P

PCIE_CLK100M_MINI_N

=SMBUS_LIO_SB_SDA

=SMBUS_LIO_SB_SCL

USB_EXTB_P

USB_EXCARD_P

USB_EXCARD_N

=SMBUS_LIO_SMC_SCL

=SMBUS_LIO_SMC_SDA

PCIE_WAKE_L

HDA_SDIN0

HDA_BIT_CLK

HDA_SYNC

HDA_RST_L

C3411

1 2

C3410

1 2

C3421

1 2

C3420

1 2

J3400

1

10

1112 1314 1516 1718 19

2

20

2122 2324 2526 2728 29

3

30

3132 3334 3536 3738 39

4

40

4142 4344 4546 4748 49

5

50

5152 5354 5556 5758 59

6

60

6162 6364 6566 6768 69

7

70

7172 7374 7576 7778 79

8

80

81

8283

84

9

83

87

8

83

8

87

83

87

BI BI

OUT

IN

OUT

IN IN

THRML_PAD

VDDO_TTL1

VMAIN_AVLBL

SWITCH_VAUX

VAUX_AVLBL

LED_DUPLEX*

RSVD_43

RSVD_29

RSVD_25

RSVD_24

NC_64

CTRL12

NC_57

NC_52

NC_51

NC_32

RSET

SWITCH_VCC

AVDDH

AVDD0

AVDD3

VDDO_TTL3

LOM_DISABLE*

VDD0

VDD1

VDD3

VDD4

TX_P

CTRL18

TESTMODE

VDD2

VDD5

VDD7

CLKREQ*

WAKE*

PERST*

MDIP0

MDIP1 MDIN1

MDIP2 MDIN2

MDIP3

XTALI

MDIN3

XTALO

REFCLKP REFCLKN

RX_N

RX_P

SPI_DO

SPI_CLK

SPI_CS

VPD_DATA

VPD_CLK

TX_N

MDIN0

AVDD1

LED_LINK1000*

VDD6

VDDO_TTL2

VDDO_TTL0

LED_ACT*

LED_LINK10/100*

AVDD2

SPI_DI

ANALOG

PCI EXPRESS

SPI

LED

TWSI

MEDIA

MAIN CLK

TEST/RSVD

IN

OUT OUT

E2

WC*

NC0

NC1

VCC

VSS

SCL

SDA

IN OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

No link: 130 mA 10 Mbps: 130 mA

1000 Mbps: 290 mA

(IPU)

and magnetics. Can also use BCP69T1 connected to CTRL18 pin 4 for internal VR.

- =ENET_VMAIN_AVLBL (See note by pin)

NOTE: See bottom of page for

Yukon Ultra schematic support.

instructions for dual Yukon EC /

YUKON_EC - Selects Yukon EC RSET value.

To support Yukon EC and Ultra on the same board:

- =PP1V8R2V5_ENET_PHY

Signal aliases required by this page:

- =ENET_CLKREQ_L (NC/TP for Yukon EC)

BOM options provided by this page:

YUKON_ULTRA - Selects Yukon Ultra RSET.

(EC:2.5V)

Yukon Ultra: Alias to GND

Yukon EC: Alias to PP1V8R2V5_ENET_PHY_AVDD, add 1x 0.1uF & 1x 0.001uF caps

No link: 82 mA

1000 Mbps: 218 mA

100 Mbps: 126 mA

10 Mbps: 108 mA

Yukon EC (2.5V)

1000 Mbps: 150 mA

100 Mbps: 40 mA

No link: 0 mA 10 Mbps: 30 mA

Yukon Ultra (1.8V)

10 Mbps: 4 mA 100 Mbps: 4 mA

1000 Mbps: 80 mA

Must be high in S0 state (can use PP3V3_S0 as input)

- =YUKON_EC_PP2V5_ENET

Yukon Ultra

1000 Mbps: 426 mA

100 Mbps: 203 mA

No link: 171 mA

Yukon EC

100 Mbps: 150 mA

Yukon EC

VPD ROM

NC

1000 Mbps: 4 mA

No link: 4 mA

10 Mbps: 179 mA

Yukon Ultra

100 Mbps: 70 mA

EC:NO CONNECT

EC:AVDD 2.5V

NC NC NC

NC

EC:CTRL25

(IPU)

(IPD)

NC

(2.5V / GND)

(2.5V / 1.8V)

(EC / Ultra)

- =PP1V2_ENET_PHY

- =PP3V3_ENET_PHY

Power aliases required by this page:

Page Notes

Yukon EC: Pin 42 should be NC (or TP) net.

- Use 0-ohm resistors or variable supply to provide 1.8V or 2.5V to =PP1V8R2V5_ENET_PHY

- Use YUKON_EC and YUKON_ULTRA BOMOPTIONs to select stuffed part

- Connect =ENET_CLKREQ_L to clock generator via 0-ohm resistor (BOMOPTION: YUKON_ULTRA)

- Alias =YUKON_EC_PP2V5_ENET to PP1V8R2V5_ENET_PHY_AVDD, add 1x 0.1uF and 1x 0.001uF caps

10 Mbps: 70 mA

No link: 60 mA

49.9

MF-LF

1% 1/16W

402

SIGNAL_MODEL=EMPTY

1/16W

49.9

MF-LF

1%

402

SIGNAL_MODEL=EMPTY

37 83

24 83

402

0.001UF

50V CERM

10%

402

0.001UF

50V CERM

10%

402

0.001UF

50V CERM

10%

402

0.001UF

50V CERM

10%

49.9

MF-LF

1%

402

SIGNAL_MODEL=EMPTY

1/16W 1/16W

49.9

MF-LF

1%

402

SIGNAL_MODEL=EMPTY

1/16W

49.9

MF-LF

1%

402

SIGNAL_MODEL=EMPTY

1/16W

49.9

MF-LF

1%

402

SIGNAL_MODEL=EMPTY

1/16W

49.9

MF-LF

1%

402

SIGNAL_MODEL=EMPTY

49.9

MF-LF

1% 1/16W

402

SIGNAL_MODEL=EMPTY

16V 402X5R10%

0.1uF

402X5R16V10%

0.1uF

402X5R

0.1uF

10% 16V

PLACEMENT_NOTE=Place C3730 close to southbridge.

0.1uF

10% 16V X5R 402

PLACEMENT_NOTE=Place C3731 close to southbridge.

24 83

28

25 34

30

30 84

QFN

OMIT

CRITICAL

88E8058

65

1% 1/16W MF-LF 402

4.99K

YUKON_ULTRA

603

4.7UF

20%

6.3V CERM

10% 402

0.001UF

CERM

50V

X5R

10% 16V

402

0.1UF

X5R

10% 16V

0.1UF

402

0.1UF

402

16V

10% X5R

CERM

50V

0.001UF

10%

402

X5R

10% 16V

402

0.1UF

X5R

10% 16V

402

0.1UF0.1UF

402

16V

10% X5R

CERM

4.7UF

603

20%

6.3V

10%

402

0.001UF

50V CERM

402

16V

10% X5R

0.1UF

402

16V

10% X5R

0.1UF0.1UF

402

16V

10% X5R

0.1UF

402

16V

10% X5RX5R

10% 16V

402

0.1UF

CERM

6.3V

20%

4.7UF

603

CERM

50V

0.001UF

402

10%

CERM

50V

0.001UF

402

10%

CERM

50V

0.001UF

402

10%

CRITICAL

OMIT

M24C08

SO8

0.1UF

402

16V

10% X5R

1/16W MF-LF

402

5%

4.7K

1/16W MF-LF 402

5%

4.7K

1/16W MF-LF

402

4.7K

5%

0402

FERR-120-OHM-1.5A

36

R3760

RES,4.87K,1%,1/16W,0402,LF

YUKON_EC1114S0285

U3780

IC,EEPROM,SERIAL IIC,8KBIT,SO8

341S1797 YUKON_EC1 CRITICAL

IC,FLASH,88E8058 ETHERNET VPD,IIC,SO8

341S2060

YUKON_ULTRA

U37801 CRITICAL

IC,88E8058,GIGABIT ENET XCVR,64P QFN

YUKON_ULTRA

CRITICALU3700338S0386 1

CRITICAL

IC,88E8053,GIGABIT ENET XCVR,64P QFN

338S0270 U37001 YUKON_EC

SYNC_DATE=03/16/2007

SYNC_MASTER=T9_NOME

35

Ethernet (Yukon)

88

A.0.0

051-7225

ENET_MDI_P<3> ENET_MDI_N<3>

ENET_CLK25M_XTALO

ENET_CLK25M_XTALI

=PP3V3_ENET_PHY

ENET_RESET_L

ENET_MDI_P<0>

PCIE_WAKE_L

PCIE_CLK100M_ENET_N =ENET_CLKREQ_L

ENET_MDI_N<0>

ENET_MDI_N<1>

PCIE_CLK100M_ENET_P

ENET_MDI_P<1>

ENET_MDI_N<2>

ENET_MDI_P<2>

PCIE_ENET_D2R_C_P

YUKON_VPD_CLK

ENET_MDI3ENET_MDI2ENET_MDI1ENET_MDI0

ENET_LOM_DIS_L

YUKON_RSET

=ENET_VMAIN_AVLBL

TP_YUKON_CTRL12

TP_YUKON_CTRL18

PCIE_ENET_D2R_C_N

PCIE_ENET_R2D_N

PCIE_ENET_D2R_P

PCIE_ENET_D2R_N

PCIE_ENET_R2D_C_P

PCIE_ENET_R2D_C_N

YUKON_VPD_DATA

PCIE_ENET_R2D_P

=PP1V2_ENET_PHY

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

PP1V8R2V5_ENET_PHY_AVDD

=PP1V8R2V5_ENET_PHY

=YUKON_EC_PP2V5_ENET

R3740

1

2

R3741

1

2

C3740

1

2

C3742

1

2

C3744

1

2

C3746

1

2

R3742

1

2

R3743

1

2

R3747

1

2

R3746

1

2

R3745

1

2

R3744

1

2

C3735

1 2

C3736

1 2

C3730

1 2

C3731

1 2

U3700

192223

28

8

42

3

4

59

63

62

60

10

18

21

27

31

17

20

26

30

3251525764

5

56

55

16

24 25 29 43

53

54

37 36

35

34

9

11

46

65

50

49

12

271333394448

58

14045

61

47

38 41

6

15 14

R3765

1

2

C3720

1

2

C3724

1

2

C3723

1

2

C3722

1

2

C3721

1

2

C3714

1

2

C3713

1

2

C3712

1

2

C3711

1

2

C3710

1

2

C3715

1

2

C3705

1

2

C3704

1

2

C3703

1

2

C3702

1

2

C3701

1

2

C3700

1

2

C3708

1

2

C3707

1

2

C3706

1

2

U3780

3

1

2

6

5

8

4

7

C3780

1

2

R3780

1

2

R3781

1

2

R3760

1

2

L3720

1 2

8

83

8

37

8

OUT

THRM_PAD

NC

IN1

EN

IN2

OUT1 OUT2

NR/FB

GND

IN

OUT

G

D

S

IN

G

D

S

G

D

S

IN

OUT

G

DS

G

D

S

G

D

S

G

D

S

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

"ENET" = "S0" || ("S3" && "AC" && "WOL_EN")

NOTE: S3 term is guaranteed by source of R3800 & Q3810, MUST BE S3 RAIL.

EC: Vout = 2.510V

Yukon Ultra requires 1.9V on its magnetics to pass compliance tests

Yukon AVDDL LDO

WLAN Enable Generation

"WLAN" = "S0" || ("S3" && "AC" && "WOW_EN")

NOTE: S3 term is guaranteed by FET & pull-up source, MUST BE S3 RAIL.

Ultra: Vout = 1.912V

(PM_SLP_S3_L)

3.3V ENET FET

NC

500 mA max output (U3850 limit)

Vout = 1.2246V * (1 + Ra / Rb)

NC

1.9V for Yukon Ultra, 2.5V for Yukon EC

ENET Enable Generation

(AC_EN_L)

Yukon Crystal

NC

7

65

LREG_TPS79501DRB

SON

CRITICAL

1UF

6.3V CERM

402

10%

402

CERM

6.3V

1UF

YUKON_ULTRA

402

MF-LF

1/16W

1%

16.9K

402

1/16W

1%

30.1K

MF-LF

33PF

402

CERM

50V

5%

CRITICAL

25.0000M

SM-3.2X2.5MM

18PF

5% 50V

402

CERM

18PF

402

50V

5%

CERM

35

SOT-363

2N7002DW-X-F

34 40 45 46

10V

0.22UF

CERM

10%

402

2N7002DW-X-F

SOT-363 SOT-363

2N7002DW-X-F

13 24

34

402

100K

MF-LF

5%

1/16W

402

1/16W

5%

MF-LF

10K

CERM

0.01UF

402

16V

10%

NTR4101P

SOT-23

0.033UF

X5R 402

16V

10%

MF-LF

402

10K

1/16W

5%

2N7002DW-X-F

SOT-363

2N7002DW-X-F

SOT-363

2N7002DW-X-F

7

25 40 45 65

25

114S0363

RES,31.6K,1%,1/16W,402,LF

YUKON_ECR38551

Yukon Power Control

051-7225

A.0.0

8836

SYNC_MASTER=T9_NOME

SYNC_DATE=03/16/2007

PM_ENET_EN_L

WOL_EN

PM_SLP_S3_L

AC_EN_L

=PP3V3_ENET_AVDDLDO

ENET_CLK25M_XTALI ENET_CLK25M_XTALO

PM_ENET_EN

SMC_ADAPTER_EN

WOW_EN

ENETAVDDL_FB

=PPVOUT_ENET_AVDDLDO

P3V3ENET_SS

=PP3V3_ENET_FET

=PP3V3_S3_P3V3ENETFET

PM_WLAN_EN_L

R3810

1 2

R3811

1

2

C3810

12

Q3810

3

1

2

C3811

1

2

R3800

1

2

Q3801

3

5

4

Q3800

3

5

4

Q3801

6

2

1

U3850

8

6

1 2

7

5

3 4

9

C3850

1

2

C3851

1

2

R3855

1

2

R3856

1

2

C3855

1

2

Y3860

24

13

C3861

1

2

C3860

1

2

Q3800

6

2

1

C3800

1

2

Q3805

3

5

4

Q3805

6

2

1

8 8

SYM_VER2

NC2

NC3

NC4

LINE

SIDE

CHIP

SIDE

NC1

SYM_VER2

NC2

NC3

NC4

LINE

SIDE

CHIP

SIDE

NC1

BI

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

Place one cap at each pin of transformer

- =GND_CHASSIS_ENET

New Series Rs required for European Telecom Compliance

Place close to connector

(NONE)

514-0277

Short shielded RJ-45

BOM options provided by this page:

Signal aliases required by this page:

Power aliases required by this page:

Page Notes

mirrored on opposite

Transformers should be sides of the board

OMIT

NONE

SHORT

NONE NONE

402

10%

6.3V

1uF

CERM 402

1uF

10% CERM

402

6.3V

MF-LF 402

1/16W

5%

7575

MF-LF 402

5% 1/16W1/16W

5%

402

MF-LF

75

1/16W MF-LF

5%

402

75

6.3V 402

1uF

10% CERM

1uF

CERM

6.3V

10% 402

1000BT-824-00275

CRITICAL

XFR-SM

OMIT

CRITICAL

XFR-SM

1000BT-824-00275

35 83

9

F-RT-TH-RJ45

JM36113-P2054-7F

CRITICAL

OMIT

NONE

SHORT

NONE NONE

402

OMIT

NONE

SHORT

NONE NONE

402

OMIT

NONE

SHORT

NONE NONE

402

CRITICAL

10% 2KV

CERM

1000PF

1206

157S0030

2

XFMR,ISO,HALF-PORT,1000T,16P,SMD,2MM

T3900,T3901

CRITICAL

Ethernet Connector

88

051-7225

37

A.0.0

SYNC_MASTER=M76_MLB

SYNC_DATE=03/19/2007

ENET_MDI_N<3>

ENET_MDI_P<3>

ENET_MDI_N<2>

ENET_MDI_P<2>

ENET_MDI_N<1>

ENET_MDI_P<1>

ENET_MDI_N<0>

ENET_MDI_P<0>

=GND_CHASSIS_ENET

ENET_CTAP0

ENET_CTAP3

ENET_CTAP1

ENET_CTAP2

ENETCONN_P<1>

ENETCONN_N<0>

ENETCONN_P<0>

ENETCONN_N<1>

ENETCONN_P<3>

ENETCONN_N<2>

ENETCONN_P<2>

ENETCONN_N<3>

ENET_CTAP_COMMON

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

PP1V8R2V5_ENET_PHY_AVDD

RX3910

1 2

C3903

1

2

C3902

1

2

R3903

1

2

R3902

1

2

R3901

1

2

R3900

1

2

C3901

1

2

C3900

1

2

T3900

1

10

11

14

15

16

2

3

6

7

8 9

4 5 12

13

T3901

1

10

11

14

15

16

2

3

6

7

8 9

4 5 12

13

J3900

9

10

11

12

1 2 3 4 5 6 7 8

RX3911

1 2

RX3991

1 2

RX3990

1 2

C3904

1 2

87

35

BI

BI BI BI BI

BI

BI BI

BI BI BI

OUT OUT

IN

OUT

BI

OUT

IN IN

BI

OUT

SDA

SCL

PCI_AD19

PCI_AD18

PCI_AD17

PCI_AD16

PCI_AD15

PCI_AD14

PCI_AD13

PCI_AD12

PCI_AD11

PCI_AD10

PCI_AD31

PCI_AD30

PCI_AD28 PCI_AD29

PCI_AD27

PCI_AD25 PCI_AD26

PCI_AD24

PCI_AD23

PCI_AD21

PCI_AD20

PCI_AD9

PCI_AD8

PCI_AD7

PCI_AD6

PCI_AD5

PCI_AD4

PCI_AD3

PCI_AD2

PCI_PAR

PCI_CLK PCI_IDSEL

GND

PCI_AD1

PCI_AD0

VCC

MFUNC

G_RST_L

REG18_1

REG18_0

REG_EN_L

PHY_PINT

PHY_PCLK

PHY_LREQ

PHY_LPS

PHY_LINKON

PHY_LCLK

PHY_D7

PHY_D6

PHY_D5

PHY_D4

PHY_D3

PHY_D1-D1

PHY_D2

PHY_D0-D0

PHY_CTL1-CTL1

PHY_CTL0-CTL0

PCI_ACK64_L

PCI_TRDY_L

PCI_STOP_L

PCI_SERR_L

PCI_RST_L

PCI_REQ64_L

PCI_REQ_L

PCI_PME_L

PCI_PERR_L

PCI_IRDY_L

PCI_INTA_L

PCI_GNT_L

PCI_FRAME_L

PCI_DEVSEL_L

VCCP

PCI_AD22

PCI_C_BE2_L

PCI_C_BE0_L

PCI_C_BE3_L

PCI_C_BE1_L

G

D

S

IN

G

D

S

IN

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(FW_G_RST_L)

Might use

a GPIO

MFUNC as

G_RST* assertion min 2ms

(OK if VCCP and VCC are

It must not be taken high

aliased to the same rail)

G_RST* is clamped to VCCP

when there’s no power on VCCP

24 83

25

24 83

30 84

24 83

28

10%

402

X5R

10V

1uF

10%

1uF

X5R 402

10V

10%

1uF

X5R 402

10V

1uF

10% X5R

402

10V

402

X5R

10%

1uF

10V

402

X5R

10V

1uF

10%

1uF

402

10V X5R

10%

4.7K

5% 1/16W MF-LF 402

4.7K

5%

402

MF-LF

1/16W

24 83

39

5% 1/16W MF-LF

402

220

5% 1/16W MF-LF

402

1K

402

MF-LF

1/16W

5%

220

39 85

402

MF-LF

1/16W

5%

10K

BGA

(2 OF 2)

CRITICAL

TSB83AA22CZAJ

2N7002DW-X-F

SOT-363

39

SOT-363

2N7002DW-X-F

5% 1/16W MF-LF 402

100K

402

MF-LF

1/16W

5%

10K

45

28

22

5% 1/16W MF-LF

402

0.1uF

X5R 402

10% 16V

0.1uF

10% 16V X5R 402

24 83

FireWire Link (TSB83AA22)

051-7225

A.0.0

8838

SYNC_MASTER=M76_MLB

SYNC_DATE=03/19/2007

CLKFW_LINK_PCLK

FW_LLC_PP1V8LDO_EN_L

PCI_REQ64_L

PCI_IRDY_L PCI_PERR_L

PCI_DEVSEL_L

PCI_FW_REQ_L

FW_SCL FW_SDA

FW_MFUNC

PCI_AD<19>

FW_PCI_IDSEL

PCI_AD<18>

PCI_AD<17>

PCI_AD<16>

PCI_AD<15>

PCI_AD<14>

PCI_AD<13>

PCI_AD<12>

PCI_AD<11>

PCI_AD<10>

PCI_AD<31>

PCI_AD<30>

PCI_AD<28> PCI_AD<29>

PCI_AD<27>

PCI_AD<25> PCI_AD<26>

PCI_AD<24>

PCI_AD<23>

PCI_AD<21>

PCI_AD<20>

PCI_AD<9>

PCI_AD<8>

PCI_AD<7>

PCI_AD<6>

PCI_AD<5>

PCI_AD<4>

PCI_AD<3>

PCI_AD<2>

PCI_CLK33M_FW

PCI_AD<1>

PCI_AD<0>

FW_PINT

FW_LREQ

FW_LPS

FW_LINKON

CLKFW_PHY_LCLK

FW_DATA<7>

FW_DATA<6>

FW_DATA<5>

FW_DATA<3>

TP_FW_DATA<1>

FW_DATA<2>

TP_FW_DATA<0>

TP_FW_CTL<1>

TP_FW_CTL<0>

PCI_STOP_L

PCI_SERR_L

PCI_FW_RST_L

PCI_PME_FW_L

PCI_C_BE_L<0>

PCI_C_BE_L<3>

PCI_AD<22>

PCI_C_BE_L<2>

PCI_C_BE_L<1>

PCI_PAR

FW_DATA<4>

=PP1V8_S3_FW

FW_PLT_RST_L

=PP3V3_S3_FW

FW_G_RST_L

SMC_RSTGATE_L

PLT_GATED_RST

PCI_TRDY_L

PCI_ACK64_L

PCI_FRAME_L PCI_FW_GNT_L INT_PIRQD_L

=PP3V3_S3_FW

=PP3V3_S3_PCI

U4000

E4

C7

C8

F7F8F9

F10

G6G7G8

G9

G10

H6D6H7H8H9

H10

J8

J9

J10

K10

D7E6E7E8E9

E10

F6

A1

N12

L12 N11

N6 M6 M7 K9 K8 M5 K3 N1 L4 M2

M11

M1 L1 J4 H3 H4 J3 H2 G3 H1 F1

N10

F2 G4

M10 K12

M9 N9 L8 M8

N8 M3 K5 K2

D3

N2 L3 E3

L2

B3 K4

N3

L6 F4

J13

F3

D1 L7 L5 J5

F13 F12

E13 E12

C13 B9 B10 C11 B12 A11 B7 B4 A2 D4 B6 A3

G11 G12

C2

C3 C4

D5D8D9E5F5

H11J6J7

J11

E11

F11

R4000

1

2

C4010

1

2

C4011

1

2

C4008

1

2

C4009

1

2

C4004

1

2

C4003

1

2

C4002

1

2

C4001

1

2

C4000

1

2

R4002

1

2

R4001

1

2

R4090

1

2

R4080

1

2

R4091

1

2

R4010

1

2

Q4070

3

5

4

Q4070

6

2

1

R4070

1

2

R4071

1

2

38

8

SE

SM

RESET

D7

D5 D6

D4

D3

D2

CPS

PD

BMODE

PC2

PC0 PC1

LREQ

LPS

DS1 LCLK

DS0

XI

R1

R0

TESTM TESTW

TPBIAS0 TPBIAS1

TPB1N

TPB1P

TPB0N

TPB0P

TPA1N

TPA1P

TPA0P TPA0N

PINT

PCLK

AVDD_3P3

DVDD_3P3

DVDD_CORE

PLLVDD_3P3

PLLVDD_CORE

PLLGND

LKON_DS2

CNA

BI BI

OUT

OUT OUT

OUT

TRI-ST/NC

VCC

GND

IN

OUT

BI BI BI BI BI BI

BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

1MA (MAX) BUS HOLDERS

NC

(IPU)

NC

pull-up provides

C4150 with internal

PHY power-up reset.

Lo: Beta Mode enable (1394b).

Hi: Data-Strobe only (1394a).

DSx Straps:

Multi-port Portable systems are Power Class 4 (’100’). Implement 1K pull-up or pull-down on port page.

Strap via alias on port page.

Single-port / Desktop systems are Power Class 0 (’000’).

Power Class:

as 3rd FireWire port is not pinned out.

No need for DS2 pull-down on TSB83AA22A,

R4160 provides isolation between R4161 and unpowered LLC.

0.22uF

X5R 402

20%

6.3V

402

MF-LF

1/16W

5%

390K

CRITICAL

(1 OF 2)

BGA

TSB83AA22CZAJ

16V

20%

402

CERM

0.01uF

10V

10%

402

X5R

1uF

X5R 402

10% 10V

41 85

38 85

41

10V

10%

402

X5R

1uF 1uF

10V

10%

402

X5R

10V

10%

402

X5R

1uF

10V

10%

402

X5R

1uF

10% 10V

402

X5R

1uF 1uF

10V

10%

402

X5R

1uF

10V

10%

402

X5R

SM

98P3040MHZ

CRITICAL

38 85

38

5%

1/16W

402

MF-LF

1K

402

5%

MF-LF

1/16W

1K

10V

10% 402

X5R

1uF

10V

10% 402

X5R

1uF

6.3V

10% 603

CERM1

2.2uF

41

402

MF-LF

1/16W

5%

10K

402

MF-LF

1/16W

5%

4.7

1/16W

5%

402

MF-LF

1

1/16W

5%

402

MF-LF

1

MF-LF

402

5%

1/16W

5%

402

MF-LF

470

1/16W

1% MF-LF

6.34K

402

5% 1/16W MF-LF

402

1K

38

22

MF-LF

402

5%

1/16W

6.3V

20% 402

X5R

0.22uF

1/16W

5%

402

MF-LF

1K1K

MF-LF 402

5% 1/16W 1/16W

5%

402

MF-LF

1K

FireWire PHY (TSB83AA22)

SYNC_DATE=03/19/2007

051-7225

A.0.0

8839

SYNC_MASTER=M76_MLB

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm

PP3V3_FW_PHY_PLLVDD

PP3V3_FW_PHY_AVDD

MIN_NECK_WIDTH=0.22 mm

MIN_LINE_WIDTH=0.38 mm VOLTAGE=3.3V

=PP1V95_FW_PHY

PP1V95_FW_PHY_PLLVDD

MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.22 mm VOLTAGE=1.95V

FW_1_TPA_P

FW_0_TPB_P

FW_LREQ

=FWPHY_DS1

FWPHY_RESET_L

FW_LPS

FWPHY_CLK98P304M_R

PP1V8_FW_PHYOSC_R

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.25 mm VOLTAGE=1.8V

=PP1V8_FW_PHYOSC

FWPHY_CLK98P304

FW_0_TPB_N

=FWPHY_PC0

FW_LINKON_R

=FWPHY_DS0

FW_DATA<3> FW_DATA<4> FW_DATA<5> FW_DATA<6> FW_DATA<7>

FW_DATA<2>

CLKFW_PHY_LCLK

FW_0_TPA_N

FWPHY_BMODE

FWPHY_CPS

FW_LINKON

FWPHY_TESTW

FWPHY_DS1

FWPHY_DS0

=PPVP_FW_CPS

FWPHY_R1

FW_1_TPB_P FW_1_TPB_N

FW_1_TPA_N

FW_0_TPA_P

FW_PINT

FWPHY_TESTM

CLKFW_LINK_PCLK

FW_1_TPBIAS

VOLTAGE=1.86V

=PP3V3_FW_PHY

FW_0_TPBIAS

VOLTAGE=1.86V

FWPHY_R0

R4180

1 2

C4180

1

2

R4191

1

2

R4140

1

2

R4190

1

2

C4150

1

2

R4155

1

2

U4000

D10

D11G5H5

L9

M12

A5

D13

C9 C10 C12 B13 B11

A6

B8

D12

H12

J12K7K6C5C6

G13

L13

N13

K13

N4

M4

N5

H13

K11

M13

A10

A7

A8

A12 A13

L10

A4

B5

L11 N7

E2

E1

J1

J2

B1

C1

G1

G2

D2 K1

A9

C4110

1

2

C4102

1

2

C4121

1

2

C4101

1

2

C4103

1

2

C4104

1

2

C4111

1

2

C4112

1

2

C4113

1

2

C4114

1

2

G4180

2

3 1

4

R4145

12

R4142

12

C4131

1

2

C4130

1

2

C4135

1

2

R4156

1

2

R4186

1

2

R4100

1 2

R4135

1 2

R4120

1 2

R4161

1

2

R4162

1

2

R4160

1 2

41

8

41

8

41

8

V-

V+

S

G

D

S

G

D

GND

SENSEB

OUTA

FAULTB_L

FAULTA_L

ONB

INB

ONA

ONQ1

INA

GATE1A

GATE2A

SENSEA

GATE1B

GATE2B

OUTB

G

D

S

G

D

S

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

NC

Late-VG Event Detection

NC

0.020 ohm => 2.4A

Current Limits

is running or on AC.

Enables port power when machine

FWLATEVG_3V_REF Hysteresis:

2.95V when port power is on

2.81V on late Vg event and port power is off

0.033 ohm => 1.5A

0.030 ohm => 1.66A (Ideal)

0.025 ohm => 2A

as +1 if over the limit (at any point during the period)

MAX5944 current limiter trips if integrator (counter) reaches 16. A new sample (taken every 125 us) is weighted

and -1/128 if under the limit. As a result, the device tends to trip easily on devices that produce periodic current spikes. Current limit has been set higher to compensate.

- =PPBUS_S5_FWPWRSW (system supply for bus power)

- =PP3V3_FW_LATEVG_ACTIVE

(NONE)

- FW_PORT_FAULT_PU

Current Limit/Active Late-VG Protection

FireWire Port Power Switch

BOM options provided by this page:

Signal aliases required by this page:

- =PPVP_FW_SUMNODE (power passthru summation node)

Power aliases required by this page:

Page Notes

2.0M

1/16W

5%

402

MF-LF

10V

10%

603

CERM-X5R

0.33UF

0.1UF

CERM 402

20% 10V

200K

MF-LF

402

1%

1/16W

SM-LF

LMC7211

1/16W

5%

402

MF-LF

10K

402

100pF

CERM

5%

50V

MF-LF

1/16W

1%

402

10K

80.6K

MF-LF 402

1% 1/16W

MBR0540XXG

SOD-123

SOT23-3

SI2318DS

CRITICAL

SI2318DS

SOT23-3

CRITICAL

35V

1uF

10%

805

X7R

CRITICALCRITICAL

1uF

X7R 805

10% 35V

CRITICAL

805

MF

1%

0.25W

0.020

CRITICAL

MAX5944

SOIC

MF

1%

0.020

805

0.25W

CRITICAL

100K

402

5% 1/16W MF-LF

FW_PORT_FAULT_PU

SOI-LF

CRITICAL

NDS9407

16V

20%

402

CERM

0.01uF

402

470K

1/16W

5% MF-LF

2N7002DW-X-F

SOT-363

402

1/16W MF-LF

330K

5%

2N7002DW-X-F

SOT-363

34 36 45 46

7

25 36 45 65

MINISMDC

CRITICAL

1.5A-24V

OMIT

CRITICAL

PDS340XF

PWRDI5

CRITICAL

D4260

DIODE,SCHOTTKY,40V,5A,POWERDI 5,LF

1

371S0466

A.0.0

051-7225

40 88

FireWire Port Power

SYNC_MASTER=M76_MLB

SYNC_DATE=03/19/2007

=PP3V3_FW_LATEVG_ACTIVE

FW_PORTPWR_DISABLE_L

MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V

MIN_LINE_WIDTH=0.5 mm

PPBUS_FW_FWPWRSW_D

=PPBUS_S5_FW_FET

VOLTAGE=33V

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

PPVP_FW_PORTA_ISENSE

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V

PPBUS_FW_FWPWRSW_F

=PPBUS_S5_FWPWRSW

FWPWR_EN_L_DIV

PP2V4_FW_LATEVG

LATEVG_EVENT_L

P2V4_FWLATEVG_RC

FWPWR_EN_L

SMC_ADAPTER_EN

PM_SLP_S3_L

FW_PORT_FAULT_L

=PPVP_FW_SUMNODE

FW_PORTA_PWRCTRL

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=33V

PPVP_FW_PORTB_ISENSE

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=33V

PPVP_FW_PORTA_UF

FWLATEGV_3V_REF

FW_PORTB_PWRCTRL

PPVP_FW_PORTB_UF

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=33V

R4219

1

2

C4219

1

2

C4210

1

2

R4210

1 2

U4210

4

3

1

5

2

R4211

1

2

C4211

1

2

R4212

1

2

R4213

1

2

D4219

12

Q4220

3

1

2

Q4225

3

1

2

C4225

1

2

C4220

1

2

R4220

1 2

U4220

3

11

15

7

14

6

12

1

9

2

10

4

13

5

16

8

R4225

1 2

R4229

1

2

Q4260

5

6

7

8

4

1

2

3

C4260

1

2

R4260

1

2

Q4261

6

2

1

R4261

1

2

Q4261

3

5

4

F4260

1 2

D4260

1

2

3

8

41

8

TPO#

TPI

TPO

TPI#

VGND

VP

SYM_VER-2

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

FW spec calls out 0.33uF

TI PHYs require 1uF even though

Place close to FireWire PHY

ESD and late-VG rail for snap-back diodes (Common to all ports)

and should be biased to 2.4V for margin

to at least 2.1V for FW signal integrity

R4390 should be 390 Ohms max for a 3.3V rail

(NONE)

- =GND_CHASSIS_FW_EMI_R

- =PPVP_FW_PORT0

appropriate connectors and/or to

assumed that FireWire PHY page will

to apply to entire TPA/TPB XNets.

FireWire Design Guide (FWDG 0.6, 5/14/03)

1394b implementation based on Apple

Termination

- Port "0" Data-Strobe only (1394A)

- 2-port Portable Power Class (4)

Configures PHY for:

- Port "1" Bilingual (1394B)

PP2V4_FWLATEVG needs to be biased

Late-VG Protection Power

Page Notes

- =PPVP_FW_PORT1

- =PP3V3_FW_LATEVG

- =GND_CHASSIS_FW_PORT0U

- =GND_CHASSIS_FW_PORT1

properly terminate unused signals. BOM options provided by this page:

NOTE: FireWire TPA/TPB pairs are NOT constrained on this page. It is

provide the appropriate constraints

FireWire PHY Config Straps

Signal aliases required by this page:

NOTE: This page is expected to contain the necessary aliases to map the

(TPB-)

Cable Power

TPBTPB<R>

TPATPA<R> TPA+

TPB+ VP

VG

NC

BILINGUAL

between them (to avoid ground offset issue)

(FW_PORT1_BREF)

BREF should be hard-connected to logic

detection currents per 1394b V1.33

local grounds per 1394b spec

beta-only device, there is no DC path

"Snapback" & "Late VG" Protection

1394A

Note: Trace PPVP_FW_PORT0 must handle up to 5A

(TPB+)

(TPA+) (TPA-)

PORT 0

514-0255

(GND_FW_PORT0_VG)

(PPFW_PORT0_VP)

INPUT

OUTPUT

PORT 1

(GND_FW_PORT1_VG)

Note: Trace PPVP_FW_PORT1 must handle up to 5A

(PPVP_FW_PORT1)

Cable Power

ground for speed signaling and connection

When a bilingual device is connected to a

AREF needs to be isolated from all

514S0133

Power aliases required by this page:

- =GND_CHASSIS_FW_PORT0L

(NONE)

FireWire TPA/TPB pairs to their

"Snapback" & "Late VG" Protection

6.3V

10% 402

CERM

1uF

56.2

MF-LF

402

1%

1/16W

56.2

MF-LF 402

1% 1/16W

SIGNAL_MODEL=EMPTY

56.2

MF-LF

402

1%

1/16W

SIGNAL_MODEL=EMPTY

56.2

MF-LF 402

1% 1/16W

1/16W

1%

402

MF-LF

4.99K

25V

5%

402

CERM

220pF

SM

FERR-250-OHM

CRITICAL

0.001uF

50V

20%

402

CERM

SOT-363

BAV99DW-X-F

F-RT-TH-LF

1394A

CRITICAL

0.01uF

20% 603

CERM

50V

SOT-363

BAV99DW-X-F

X7R

50V

0.01uF

10%

402

SOT-363

BAV99DW-X-F

X7R 402

10% 50V

0.01uF

X7R 402

10% 50V

SOT-363

BAV99DW-X-F

50V

10%

402

X7R

0.01uF

56.2

MF-LF

402

1%

1/16W

1%

402

MF-LF

4.99K

56.2

MF-LF 402

1% 1/16W

25V

5%

402

CERM

220pF

56.2

MF-LF

402

1%

1/16W

6.3V

10% 402

CERM

1uF

56.2

402

MF-LF

1% 1/16W

NO STUFF

16V

20% 402

CERM

0.01uF

50V

10%

603-1

X7R

0.1uF

PLACEMENT_NOTE=Place C4319 close to connector pin 5.

MF-LF 402

5% 1/16W

1M

0.001uF

50V

20% 402

CERM

SM

CRITICAL

FERR-250-OHM

0.01uF

50V

20% 603

CERM

OMIT

NONE

SHORT

NONE NONE

402

0.01uF

50V

10%

402

X7R

BAV99DW-X-F

SOT-363

10% 50V

0.01uF

402

X7R

BAV99DW-X-F

SOT-363

BAV99DW-X-F

SOT-363

BAV99DW-X-F

SOT-363

0.01uF

50V

10%

402

X7R

50V

10% X7R

402

0.01uF

1/16W

1%

402

MF-LF

332

SOT23

MMBZ5227B

CRITICAL

F-RT-SM1

1394B-UG31903

90-OHM-100MA

1210-4SM1

CRITICAL

1210-4SM1

90-OHM-100MA

18NH-250MA

CRITICAL

0402

CRITICAL

18NH-250MA

0402

SIGNAL_MODEL=EMPTY

18NH-250MA

CRITICAL

0402

CRITICAL

18NH-250MA

SIGNAL_MODEL=EMPTY

0402

OMIT

NONE

SHORT

NONE NONE

402

OMIT

NONE

SHORT

NONE NONE

402

OMIT

NONE

SHORT

NONE NONE

402

OMIT

NONE

SHORT

NONE NONE

402

OMIT

NONE

SHORT

NONE NONE

402

OMIT

NONE

SHORT

NONE NONE

402

OMIT

NONE

SHORT

NONE NONE

402

051-7225

A.0.0

41 88

SYNC_DATE=03/19/2007

SYNC_MASTER=M76_MLB

FireWire Ports

=FWPHY_DS1

FW_B_TPB_L_P

FW_PORT1_TPB_N

FW_PORT1_TPB_P

=GND_CHASSIS_FW_PORT1

FW_PORT1_TPA_N

FW_PORT1_AREF

FW_PORT1_TPA_P

PP2V4_FW_LATEVG

=GND_CHASSIS_FW_PORT1

PPVP_FW_PORT1

VOLTAGE=33V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

=GND_CHASSIS_FW_PORT0U

FW_PORT0_TPB_P

PP2V4_FW_LATEVG

FW_PORT0_TPA_P

VOLTAGE=33V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PPVP_FW_PORT0

=GND_CHASSIS_FW_PORT0L

FW_PORT0_TPB_N

=PPVP_FW_PORT0

FW_PORT0_TPA_FL_P

FW_PORT0_TPA_N

=PPVP_FW_PORT1

FW_PORT0_TPB_FL_P

FW_PORT0_TPA_FL_N

FW_PORT0_TPB_FL_N

VOLTAGE=2.4V

MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm

PP2V4_FW_LATEVG

FW_1_TPBIAS

FW_B_TPA_L_P

FW_0_TPA_P FW_0_TPA_N

FW_1_TPA_N

FW_0_TPBIAS

FW_0_TPB_P

=FWPHY_PC0 =FWPHY_DS0

=PP3V3_FW_PHY

FW_B_TPA_L_N

=PP3V3_FW_LATEVG

MAKE_BASE=TRUE

FW_PORT1_TPB_N

FW_PORT1_TPA_N

MAKE_BASE=TRUE

FW_PORT1_TPB_P

MAKE_BASE=TRUE

FW_PORT1_TPA_P

MAKE_BASE=TRUE

FW_PORT0_TPB_P

MAKE_BASE=TRUE

FW_PORT0_TPB_N

MAKE_BASE=TRUE

FW_PORT0_TPA_N

MAKE_BASE=TRUE

FW_PORT0_TPA_P

FW_PORT0_TPB_C

FW_0_TPB_N

FW_PORT1_TPB_C

FW_1_TPB_N

FW_1_TPB_P

FW_1_TPA_P

FW_B_TPB_L_N

C4350

1

2

R4351

1

2

R4350

1

2

R4353

1

2

R4352

1

2

R4354

1

2

C4354

1

2

L4300

1 2

C4304

1

2

DP4300

4

5

3

J4300

7 8 9 10

4

3

6

5

2

1

C4305

1

2

DP4301

4

5

3

C4301

1

2

DP4300

1

2

6

C4300

1

2

C4303

1

2

DP4301

1

2

6

C4302

1

2

R4363

1

2

R4364

1

2

R4362

1

2

C4364

1

2

R4361

1

2

C4360

1

2

R4360

1

2

C4317

1

2

C4319

1

2

R4319

1

2

C4314

1

2

L4310

1 2

C4315

1

2

CX4304

1

2

C4310

1

2

DP4310

1

2

6

C4311

1

2

DP4310

4

5

3

DP4311

1

2

6

DP4311

4

5

3

C4313

1

2

C4312

1

2

R4390

1 2

D4390

1

3

J4310

1

10

11

2

3

4

5

6

7

8

9

FL4300

1

2 3

4

FL4301

1

2 3

4

L4360

1 2

L4361

1 2

L4362

1 2

L4363

1 2

CX4305

1

2

CX4306

1

2

CX4307

1

2

CX4302

1

2

CX4303

1

2

CX4300

1

2

CX4301

1

2

41

85

39

85

39

41

40

9

41

40

41

9

41

8

87

41

8

87

40

39

8

41

39

BI BI

IN

OUT

G

D

S

G

D

S

IN

Y

B

A

SGD

IN

BI

IN

OUT

BI BI BI BI

IN

OUT

IN

OUT IN

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

100K pull-up to 5V)

516S0335

(ODD has internal

(UATA_STOP)

IDE (ODD) Connector

(SB has internal pulldown 5.7k-23.5k) (UATA_DSTROBE)

Unused SATA Ports

(UATA_HSTROBE)

NC

Indicates disk presence

(UATA_CS1*)

from ball of SB

Place within 12.7mm

Placement note

(UATA_CS0*)

23

23 82

2N7002DW-X-F

SOT-363

2N7002DW-X-F

SOT-363

1/16W

5%

402

MF-LF

100K

24

CRITICAL

M-ST-SM1-LF

10K

1/16W

402

MF-LF

5%

402

5%

MF-LF

1/16W

47K

10% 10V

0.068UF

CERM

402

24 82

1/16W

5%

402

MF-LF

100K

SC70

MC74VHC1G09

FDC606P

SOT-6

CRITICAL

23 82

402

MF-LF

1/16W

24.9

1%

23 82

402

4.7K

MF-LF

5% 1/16W

6.2K

MF-LF 402

5% 1/16W

45

33K

5% 1/16W MF-LF

402

23 82

23 82 23 82

23 82

402

10% 16V

CERM

0.01UF

23 82

PATA Connector

051-7225

A.0.0

42 88

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

VOLTAGE=5V

MIN_NECK_WIDTH=0.4 mm

MIN_LINE_WIDTH=0.6 mm

PP5V_ODD

=PP5V_S0_ODD

P5VODD_SS

=PP5V_S0_ODDPWREN

P5VODD_EN_L

ODD_PWR_EN_L

IDE_IRQ14

IDE_PDD<2>

IDE_PDDREQ IDE_PDIORDY

SMC_ODD_DETECT

IDE_PDD<14>

IDE_PDD<12>

IDE_PDD<11>

MAKE_BASE=TRUE

SATA_RBIAS

MAKE_BASE=TRUE

TP_SATA_C_D2RN

MAKE_BASE=TRUE

TP_SATA_B_D2RP

MAKE_BASE=TRUE

TP_SATA_B_D2RN

MAKE_BASE=TRUE

TP_SATA_B_R2DN

MAKE_BASE=TRUE

TP_SATA_C_D2RP

TP_SATA_C_R2DN

MAKE_BASE=TRUE

TP_SATA_C_R2DP

MAKE_BASE=TRUE

TP_SATA_B_R2DP

SATA_RBIAS_P SATA_RBIAS_N

SATA_B_R2D_C_P SATA_B_R2D_C_N

SATA_C_R2D_C_P SATA_C_R2D_C_N

SATA_B_D2R_P SATA_B_D2R_N

SATA_C_D2R_P SATA_C_D2R_N

=PP3V3_S0_IDE

IDE_PDCS3_L

IDE_PDD<7> IDE_PDD<6> IDE_PDD<5>

IDE_PDD<1>

IDE_PDD<0> IDE_PDIOW_L IDE_PDIOR_L IDE_PDDACK_L

IDE_PDA<1> IDE_PDCS1_L IDE_PDA<2>

IDE_PDD<8> IDE_PDD<9> IDE_PDD<10>

IDE_PDD<13>

IDE_PDD<15>

IDE_PDA<0>

IDE_PDD<4> IDE_PDD<3>

ODD_RST_BUF_L

ODD_PWR_EN

ODD_RST_5VTOL_L

=PP5V_S0_PCIREQFIX

ODD_RST_BUF_L

R4460

1

2

R4402

1

2

R4403

1

2

R4410

1

2

C4421

1 2

Q4421

3

5

4

Q4421

6

2

1

R4422

1

2

J4400

1

10 11 12 13 14 15 16 17 18 19

2

20 21 22 23 24 25 26

27

28

29

3

30

31

32

33

34

35

36

37

38

39

4

40

41

42

43

44

45

46

47

48

49

5

50

6 7 8 9

R4420

1

2

R4421

12

C4422

1

2

R4430

1

2

U4430

3

2

1

4

5

Q4420

1 2 5 6

3

4

8

82

8

42

8

42

OUT

VBUS

D-

D+

GND

IN

OUT

EN

OC*

GND

THRML

PAD

VDD

THRM_PAD

GND

0I0 Y0

SEL

1I1

1I0

0I1

Y1

BI

SYM_VER-1

IN OUT

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

USB/SMC Debug Mux

SEL=1 Choose USB

SEL=0 Choose SMC

If power source is S3, can tie EN to IN.

514S0115

Place L4600 and L4605 across moat

Right USB Port

Port Power Switch

CRITICAL

0603

FERR-220-OHM-2A

POLY B2

20%

6.3V

100UF

CRITICAL

6.3V

805-1

20%

10uF

CERM

10uF

CERM

805-1

20%

6.3V

0.1UF

CERM 402

20% 10V

16V

20% 402

CERM

0.01uF

OMIT

NONE

SHORT

NONE NONE

402

13 24

UAR2X

F-RT-SM-USB-RGT1

CRITICAL

SC-75

RCLAMP0502B

RTUSB_ESD

TPS2051

MSOP

CRITICAL

PI3USB10

TDFN

CRITICAL

SMC_DEBUG_YES

SIGNAL_MODEL=USB_MUX

24 82

SMC_DEBUG_YES

CERM

402

20% 10V

0.1UF 10K

MF-LF 402

5% 1/16W

1210-4SM1

90-OHM-100MA

CRITICAL

7

45 46 47

7

45 46 47

45

65

SMC_DEBUG_NO

1/16W MF-LF

0

5%

402

1/16W MF-LF

5%

402

0

SMC_DEBUG_NO

OMIT

NONE

SHORT

NONE NONE

402

OMIT

NONE

SHORT

NONE NONE

402

OMIT

NONE

SHORT

NONE NONE

402

43 88

A.0.0

SYNC_MASTER=M76_MLB

SYNC_DATE=03/19/2007

External USB Connector

051-7225

PP5V_S3_RTUSB_ILIM

MIN_NECK_WIDTH=0.5 mm

MIN_LINE_WIDTH=0.5 mm VOLTAGE=5V

=GND_CHASSIS_RTUSB

USB2_RT_N

USB2_EXTA_MUXED_P

USB2_RT_P

=USB_EXTA_EN

MIN_LINE_WIDTH=0.5 mm

PP5V_S3_RTUSB_F

MIN_NECK_WIDTH=0.5 mm VOLTAGE=5V

USB_DEBUGPRT_EN_L

SMC_RX_L

SMC_TX_L

USB2_EXTA_MUXED_N

USB_EXTA_N USB_EXTA_P

=PP3V42_G3H_SMCUSBMUX

=PP5V_S3_RTUSB

USB_EXTA_OC_L

L4605

1 2

C4696

1

2

C4695

1

2

C4690

1

2

C4691

1

2

C4605

1

2

CX4601

1

2

J4600

1 2 3 4

5 6

7 8

D4600

3

12

U4690

4

1

2

3

5

8

7

6

9

U4650

12

10

11

9

157

6

13

2

8

3 4

C4650

1

2

R4650

1

2

L4600

1

2 3

4

R4651

1 2

R4652

1 2

CX4600

1

2

CX4603

1

2

CX4602

1

2

9

87

87 87

87

8

SYM_VER-1

BI

SYM_VER-1

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Keep close to FL4735 to keep return current loop small

SIM Interconnect

NC

WWAN Ground WWAN Ground

WWAN Ground

NC

WWAN USB D+

WWAN Power

WWAN TwinAx Shield 2

WWAN Ground

NC

WWAN_SIM_CLOCK

WWAN_SIM_VCC

WWAN_SIM_RESET

WWAN_SIM_DATA

WWAN Power

514S0171

Camera Power

WWAN USB D-

Camera USB D+

Camera Ground

WWAN Power

Camera TwinAx Shield

Connector shield

Camera Power

Camera Ground

Camera USB D-

514S0172

Keep close to FL4745 to keep return current loop small

Left Clutch Barrel Interconnect

50V 402

X7R

10%

0.01UF

0603

FERR-220-OHM-2A

CRITICAL

OMIT

20%

402

CERM

50V

0.001uF

NO STUFF

OMIT

CRITICAL

FERR-220-OHM-2A

0603

CRITICAL

FERR-220-OHM-2A

0603

F-RT-SM

20347-125E-12

CRITICAL

1210-4SM1

CRITICAL

90-OHM-100MA

24 82

50V

10%

0.01UF

402

X7R

0603

CRITICAL

FERR-220-OHM-2A

50V

20% 402

CERM

0.001uF

NOSTUFF

7

24 82

SIM_CONN

F-RT-SM

20347-110E-12

CRITICAL

NO STUFF CRITICAL

0402

FERR-120-OHM-1.5A

7 24 82

1210-4SM1

90-OHM-100MA

CRITICAL

SYNC_DATE=03/19/2007

SYNC_MASTER=M76_MLB

Left Clutch Barrel Interconnect

051-7225

A.0.0

8844

RES,MF,1/10W,0OHM,5,0603,SM,LF

CRITICAL

L4731,L4741

113S0022

2

=GND_CHASSIS_LEFTCLUTCH

USB_CAMERA_P

=PP5V_S3_WWAN

MAKE_BASE=TRUE

USB_WWAN_P

USB_WWAN_F_N

USB_CAMERA_N

PP5V_S3_WWAN_F

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V

=GND_CHASSIS_LEFTCLUTCH

USB_CAMERA_F_N

WWAN_SIM_CLOCK PPVCC_WWAN_SIM

USB_WWAN_F_P

WWAN_SIM_RESET WWAN_SIM_DATA

PP5V_S3_CAMERA_F

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V

USB_CAMERA_F_P

=PP5V_S3_CAMERA

USB_EXTD_P

MAKE_BASE=TRUE

USB_WWAN_N USB_EXTD_N

PPVCC_WWAN_SIM

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.25 mm VOLTAGE=3.3V

WWAN_SIM_RESET

WWAN_SIM_CLOCK

WWAN_SIM_DATA

C4730

1

2

FL4735

1

2 3

4

L4731

1 2

C4731

1

2

L4741

1 2

L4730

1 2

J4731

1

10 11 12 13 14 15 16 17 18 19

2

20 21 22 23 24 25

26 27 28 29

3

30

31

32

4 5 6 7 8 9

FL4745

1

2 3

4

C4740

1

2

L4740

1 2

C4741

1

2

J4732

1

10

11 12

13

14

2 3 4 5 6 7 8 9

L4764

1 2

44

8

44

87

8

87

9

7

87

9

87

44

87

44

87

7

44

IN

OUT

IN

OUT

IN IN IN IN IN IN IN IN

IN

OUT

IN

OUT

P16

P51

P50

P42/SDA1

P97/IRQ15*/SDA0

P95/IRQ14*

P94/IRQ13*

P93/IRQ12*

P92/IRQ0*

P91/IRQ1*

P86/IRQ5*/SCK1/SCL1

P83/LPCPD*

P82/CLKRUN*

P80/PME*

P35/LRESET*

P34/LFRAME*

P10

P12 P13 P14 P15

P17

P31/LAD1

P30/LAD0

P32/LAD2 P33/LAD3

P36/LCLK P37/SERIRQ

P44/TMO1

P77/AN7

P76/AN6

P81/GA20

P96/EXCL

P11

P47/PWX1/PWM1

P45 P46/PWX0/PWM0

P40/TMIO

P43/TMI1/EXSCK1

P27

P26

P25

P24

P23

P22

P21

P20

P41/TMO0

P52/SCL0

P60/KIN0* P61/KIN1* P62/KIN2* P63/KIN3* P64/KIN4*

P65/KIN5* P66/IRQ6*/KIN6* P67/IRQ7*/KIN7*

P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5

P84/IRQ3*/TXD1 P85/IRQ4*/RXD1

P90/IRQ2*

(1 OF 4)

PA2/KIN10*/PS2AC PA3/KIN11*/PS2AD

PA5/KIN13*/PS2BD

PA4/KIN12*/PS2BC

PB2 PB3 PB4

PE0

PG6/EXIRQ14*/EXSDAB

PG5/EXIRQ13*/EXSCLA

PH1/EXIRQ7*

PH0/EXIRQ6*

PG7/EXIRQ15*/EXSCLB

PG4/EXIRQ12*/EXSDAA

PH3/EXEXCL

PH2/FWE

PB5

PF4/PWM4

PF2/IRQ10*/TMOY

PG2/EXIRQ10*/SDA2

PG0/EXIRQ8*/TMIX

PF7/PWM7

PC3/TIOCD0/TCLKB/WUE11*

PH5

PB7

PB6

PH4

PF5/PWM5 PF6/PWM6

PG1/EXIRQ9*/TMIY

PA6/KIN14*/PS2CC PA7/KIN15*/PS2CD

PD0/AN8 PD1/AN9 PD2/AN10 PD3/AN11 PD4/AN12 PD5/AN13 PD6/AN14 PD7/AN15

PF0/IRQ8*/PWM2 PF1/IRQ9*/PWM3

PB0/LSMI* PB1/LSCI

PC0/TIOCA0/WUE8* PC1/TIOCB0/WUE9* PC2/TIOCC0/TCLKA/WUE10*

PC4/TIOCA1/WUE12* PC5/TIOCB1/TCLKC/WUE13* PC6/TIOCA2/WUE14* PC7/TIOCB2/TCLKD/WUE15*

PG3/EXIRQ11*/SCL2

PF3/IRQ11*/TMOX

PA1/KIN9*/PA2DD

PA0/KIN8*/PA2DC

PE1*/ETCK PE2*/ETDI PE3*/ETDO PE4*/ETMS

(2 OF 4)

VCL

AVREF

VCC

AVCC

XTAL EXTAL

AVCC

VCC

MD1 MD2

NMI

RES*

ETRST*

AVREF

AVSS

VSS

(3 OF 4)

NC22

NC21

NC20

NC19

NC18

NC17

NC16

NC15

NC14

NC13

NC12

NC9

NC6

NC11

NC10

NC8

NC7

NC5

NC4

NC3

NC2

NC1

NC0

(4 OF 4)

OUT OUT

BI

IN

OUT

BI

OUT

IN

OUT

IN

OUT OUT OUT OUT

IN

IN IN

IN

IN IN

IN

OUT

IN

OUT OUT OUT OUT

BI BI BI BI BI BI

OUT OUT

OUT

IN

OUT

IN

OUT OUT

BI

OUT

IN

OUT

IN

BI BI BI BI

IN IN IN

OUT

BI

IN IN IN IN

BI

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(OC)

(DEBUG_SW_1) (DEBUG_SW_2)

(OC)

(OC) (OC)

(OC)

pins designed as outputs can be left floating,

NOTE: Unused pins have "SMC_Pxx" names. Unused

those designated as inputs require pull-ups.

(DEBUG_SW_3)

NC

NC NC

NC

NC NCNC

NC

NC NC NC

NC

NC NC NC NC NC

NOTE: SMS Interrupt can be active high or low, rename net accordingly. If SMS interrupt is not used, pull up to SMC rail.

805-3

6.3V

20%

22UF

CERM-X5R

7

25 46 47

7

46 47

7

46 78

6.3V 402

10%

PLACEMENT_NOTE=Place C4907 close to U4900 pin F1

0.47UF

CERM-X5R

20% 402

0.1UF

10V CERM

20%

402

0.1UF

10V

CERM

PLACEMENT_NOTE=Place C4920 close to U4900 pins N14,N15

PLACEMENT_NOTE=Place R4999 close to U4900 pins N14,N15

402

4.7

1/16W

5%

MF-LF

20% 402

0.1UF

10V CERM

SM

25

7

58

20% 402

0.1UF

10V CERM

7

25

46

28 46 65

38

20% 402

0.1UF

10V CERM

49

7

46 56

34 46

7

43 45 46 47

7

43 45 46 47

34 36 40 46

65

BGA

SMC_H8S2116

OMIT

SMC_H8S2116

OMIT

BGA

SMC_H8S2116

OMIT

BGA

SMC_H8S2116

OMIT

34 46

48

402

10K

MF-LF

5%

1/16W

7

47

7

47

MF-LF 402

10K

5% 1/16W

402

1/16W

5% MF-LF

10K

402

NO STUFF

0

MF-LF

5% 1/16W

402

10K

MF-LF

5% 1/16W

43

34 46

16 32

25

7

49

42

34 46

34

25

46

52

46

52

54

49

54

53

49

7

46 47

46

7

46 47

7

46 47

7

46 47

46 78

34

46

34

46

48

46

7

53 78

54

49

7

43 45 46 47

7

43 45 46 47

46

9

46

7

25 47

16 31

7

25 28

7

47

13 25

7

25 47

7

25

46

7

23 47

7

23 47

7

23 47

7

23 47

7

23 47

7

28

30 84

53

48

7

25 36 40 65

7

25 65

7

25 46

46

48

46

SYNC_DATE=01/17/2007

SYNC_MASTER=T9_NOME

SMC

45 88

A.0.0

051-7225

SMC_P64

SMC_P63

SMC_P62

SMC_ADAPTER_EN

SMC_GPU_ISENSE

SMC_P14

SMC_P67

PM_LAN_PWRGD

SMC_GFX_THROTTLE_L

SMC_P45

SMC_P43

SMC_SYS_LED

SMB_MGMT_CLK

SMC_WAKE_SCI_L SMC_P81

SMC_TX_L

SMC_DCIN_ISENSE SMC_PBUS_VSENSE SMC_BATT_ISENSE SMC_NB_1V25_ISENSE

PM_SLP_S5_L

SMC_PG0

SMC_ONOFF_L

SMC_RX_L

PM_SUS_STAT_L

PM_CLKRUN_L

SMC_GPU_VSENSE

PP3V3_S5_AVREF_SMC

SMC_TCK

SMC_PF0 SMC_PF1 SMC_LID

SMB_BSA_CLK

SMC_TMS

SMC_TDO

SMC_BATT_VSET SMC_SYS_ISET

PM_SLP_S3_L

PM_PWRBTN_L

SMC_PROCHOT_3_3_L

=SMC_SMS_INT

SMB_A_S3_CLK

SMC_FAN_2_TACH

SMS_Y_AXIS SMS_Z_AXIS SMC_ANALOG_ID

SMC_FAN_1_CTL

IMVP_VR_ON

SMC_P20 SMC_P21

PM_RSMRST_L

ALS_RIGHT

ALS_LEFT

SMC_NB_1V8_ISENSE

SMC_NB_CORE_ISENSE

SMS_X_AXIS

SMC_FAN_3_TACH

SMC_FAN_0_CTL

PM_EXTTS_L<1>

USB_DEBUGPRT_EN_L

SMC_P46

SMC_P44

INT_SERIRQ

SMB_0_S0_CLK

SMC_RX_L

SMC_TX_L

SMC_SYS_KBDLED

SMB_MGMT_DATA

PCI_CLK33M_SMC

SMC_LRESET_L

LPC_FRAME_L

LPC_AD<3>

LPC_AD<2>

LPC_AD<1>

LPC_AD<0>

SMC_BATT_CHG_EN

SMC_BATT_TRICKLE_EN_L

ALL_SYS_PWRGD

SMC_RSTGATE_L

RSMRST_PWRGD

SMC_P27

SMC_P26

SMC_P23

SMC_KBC_MDE

SMC_TRST_L

SMC_NMI

SMC_VCL

PM_EXTTS_L<0>

SMC_PA0 SMC_PA1

=PP3V3_S5_SMC

SMC_MD1

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.25 MM VOLTAGE=3.3V

PP3V3_S5_SMC_AVCC

GND_SMC_AVSS

SMC_RESET_L SMC_XTAL

SMC_EXTAL

SMC_PM_G2_EN

SMC_CPU_ISENSE SMC_CPU_VSENSE

SMC_BC_ACOK SMC_BS_ALRT_L

PM_S4_STATE_L

SMC_SUS_CLK SMB_0_S0_DATA

SMC_CASE_OPEN

SMC_TDI

SMB_BSA_DATA

SMB_A_S3_DATA

SMB_B_S0_DATA

SMC_PROCHOT

SMB_B_S0_CLK

SMC_THRMTRIP

ALS_GAIN

SMC_FWE

SMS_ONOFF_L

PM_BATLOW_L

SYS_ONEWIRE

SMC_PB0

SMC_EXCARD_PWR_EN

SMC_EXCARD_CP

SMC_RUNTIME_SCI_L SMC_ODD_DETECT ISENSE_CAL_EN

SMC_EXCARD_OC_L SMC_GFX_OVERTEMP_L

SMC_FAN_2_CTL SMC_FAN_3_CTL SMC_FAN_0_TACH SMC_FAN_1_TACH

SMC_SYS_VSET

SMC_BATT_ISET

PM_SYSRST_L

SMC_PF3

SMC_PH4

SMC_P22

PM_LAN_ENABLE

C4902

1

2

C4903

1

2

C4904

1

2

C4905

1

2

C4906

1

2

C4907

1

2

C4920

1

2

R4999

1 2

XW4900

1

2

U4900

B12 C13 A15 B14 B15 C14 D12 C15

D13 D14 D15 E12 E14 E15 E13 F14

D9 C9 A9 B9 D8 C8 A8 D7

A5 B5 D5 C3 B1 C2 D3 C1

G1 G4 F2

L13 L14 L15 K12 K13 K14 J12 J13

N12 R13 P13 R14 P14 R15 N13 P15

C7 A7 B7 D6 C6 A6 B6

K4 J2 J1 J3 J4 H2 H1 G2

U4900

R3 P3 R2 N3 R1 N2 M4 N1

B10 A10 D10 A11 B11 C11 A12 D11

G14 G15 G13 G12 H14 H15 H13 H12

M11 P11 R11 N11 P10 R10 N10 M10

M3 M2 M1 L4 L2

M7 P6 R6 N6 M6 R5 P5 N5

P9 R9 N9 P8 R8 M8 P7 R7

E1 F3 K2 C4 D4 B3

U4900

N14

N15

M14

M15

P12 R12

L1

B2

E2 K1

F4

E3

P2P1J15A1F1

D1P4R4

F12

F13

B13

A13

A4B4D2

A2

U4900

G3 H3

K15 J14

F15 A14 C12 C10 C5 A3 B8 E4

K3

H4 M9 N8

L3 N4 M5

N7 M12 M13 L12

R4909

1

2

R4901

1

2

R4902

1

2

R4903

1

2

R4998

1

2

53

46

49

46

8

46

46 46

46

G

D

S

IN

OUT

GND

NC

CD

GND

OUT

VDD

OUT

IN

OUT

IN

OUT

IN

BI

OUT

IN

G

D

S

G

D

S

OUT

IN

OUT

IN

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

SMC AVREF Supply

LAN PWRGD Circuit

SMC FSB to 3.3V Level Shifting

TO CPU

TO SMC

NC

TPS51120 PGOOD threshold 87-93% (4.35 - 4.65V)

TPS51120 PGOOD threshold 87-93% (2.87 - 3.07V)

System (Sleep) LED Circuit

Debug Power "Button"

Reports when 5V S5 and 3.3V S5 are in regulation

S5 Rail PWRGD Circuit

SMC Crystal Circuit

SMC Reset "Button" / Brownout Detect

CERM

20%

402

0.1uF

10V

2N7002DW-X-F

SOT-363

0.47UF

402

CERM-X5R

6.3V

10%

CERM 402

16V

10%

0.01UF

10uF

603

X5R

20%

6.3V

SOT23-3

REF3133

CRITICAL

0

1/16W

5%

402

MF-LF

402

MF-LF

5%

1/16W

10K

402

1/16W5%MF-LF

100K

402

1/16W MF-LF

5%

10K

MF-LF

5%

1/16W

10K

402

100K

5%

MF-LF1/16W

402

2.0K

MF-LF

5%

1/16W

402

ONEWIRE_PU

MF-LF

5%

1/16W

100K

402

MF-LF

5%

1/16W

10K

402

10K

1/16W5%MF-LF

402

10K

5%

1/16W MF-LF

402

10K

1/16W5%MF-LF

402

10K

1/16W5%MF-LF

402

10K

1/16W5%MF-LF

402

1/16W MF-LF

5% 402

10K

1/16W5%MF-LF

402

10K

5%

470K

402

MF-LF1/16W

10K

1/16W

5% 402

MF-LF

20.00MHZ

5X3.2-SM

CRITICAL

SOT23-5

RN5VD30A-F

100K

402

MF-LF

5%

1/16W

5%

100K

402

MF-LF1/16W

7

45 47

MF-LF

5%

1/16W

10K

402

MF-LF

5%

1/16W

10K

45

10 16 23 79

78

603

MF-LF

0

1/10W

OMIT

603

5% MF-LF

0

1/10W

OMIT

MF-LF 402

5% 1/16W

100K

60 45

402

0.0022UF

10% 50V CERM

60

MMDT3904XF

SOT-363-LF

MF-LF

1/16W

5%

402

3.3K

MMDT3904XF

SOT-363-LF

3.3K

1/16W

5%

MF-LF

402

470

402

MF-LF

1/16W

5%

10 58 79

45

SOT-363

2N7002DW-X-F

100K

1/16W5%MF-LF

402

100K

5%

MF-LF1/16W

402

100K

MF-LF

5%

1/16W

402

SOT23-LF

2N7002

402

MF-LF

5%

1/16W

10K

402

MF-LF

5%

1/16W

10K

5%

402

NO STUFF

100K

1/16W MF-LF

5%

402

0

45 28 45 65

34

1/16W

5% MF-LF

1K

402

7

45 46 78

2N3906

SOT23-LF

402

5% MF-LF

100

1/16W

1%

402

MF-LF

1/16W

45

9.09K

1%

1/16W

402

MF-LF

5%

CERM

5%

15pF

402

CERM

50V

10%

0.01UF

16V

CERM

402

SYNC_DATE=(MASTER)

051-7225

A.0.0

8846

SYNC_MASTER=(MASTER)

SMC Support

ALL

Intersil ISL60002-33

353S1381 353S1278

SMC_P45

SUS_CLK_SB

MAKE_BASE=TRUE

SMC_P81 SMC_PF0 SMC_PF1

SMC_EXCARD_OC_L

=PP3V3_S5_SMC

SMC_PH4

SMC_BATT_TRICKLE_EN_L

SMC_ADAPTER_EN

SMC_EXTAL

=PP3V3_S0_SMC

SMC_P67

SMC_PG0

SMC_THRMTRIP

PM_THRMTRIP_L

SMC_PROCHOT

CPU_PROCHOT_L_R

CPU_PROCHOT_L

CPU_PROCHOT_BUF

=PP1V05_S0_SMC_LS

SMC_P44

TP_SMC_P44

MAKE_BASE=TRUE

SMC_P43

TP_SMC_P43

MAKE_BASE=TRUE

SMC_P27

MAKE_BASE=TRUE

TP_SMC_P27

SMC_P26

MAKE_BASE=TRUE

TP_SMC_P26

SMC_P23

MAKE_BASE=TRUE

TP_SMC_P23

SMC_P22

TP_SMC_P22

MAKE_BASE=TRUE

SMC_P21

MAKE_BASE=TRUE

TP_SMC_P21

SMC_GFX_THROTTLE_L

MAKE_BASE=TRUE

TP_SMC_GFX_THROTTLE_L

SMC_GFX_OVERTEMP_L

MAKE_BASE=TRUE

TP_SMC_GFX_OVERTEMP_L

SMC_FAN_3_CTL

MAKE_BASE=TRUE

TP_SMC_FAN_3_CTL

SMC_FAN_3_TACH

MAKE_BASE=TRUE

TP_SMC_FAN_3_TACH

SMC_FAN_2_TACH

MAKE_BASE=TRUE

TP_SMC_FAN_2_TACH

SMC_FAN_2_CTL

MAKE_BASE=TRUE

TP_SMC_FAN_2_CTL

SMC_XTAL

SYS_LED_ILIM

=PP5V_S3_SYSLED

SYS_LED_ANODE

SYS_LED_L_VDIV

SMC_RESET_L

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm

PP3V3_S5_AVREF_SMC

VOLTAGE=3.3V

PM_SUS_STAT_L

SMC_EXCARD_CP

SMC_BC_ACOK

PM_SLP_S5_L

=P3V3S5_PGOOD

=P5VS5_PGOOD

RSMRST_PWRGD

MAKE_BASE=TRUE

EXCARD_OC_L

SMC_SYS_LED

SYS_LED_L

SMC_CASE_OPEN

SMC_PA0 SMC_PA1 SMC_PB0

SMC_ONOFF_L

SMC_TX_L

SMC_FWE

SMC_LID

SMC_RX_L

SYS_ONEWIRE SMC_BS_ALRT_L

SMC_TDO

SMC_TMS

SMC_TDI SMC_TCK

SMC_PF3

TP_SMC_BATT_VSET

MAKE_BASE=TRUE

SMC_BATT_VSET

MAKE_BASE=TRUE

TP_SMC_SYS_VSET

SMC_SYS_VSET

SMC_P20

TP_SMC_P20

MAKE_BASE=TRUE

TP_SMC_P14

SMC_P14

=PP3V3_S0_SMC

SMC_PROCHOT_3_3_L

=PP3V3_S5_SMC

=PPVIN_S5_SMCVREF

ALL_SYS_PWRGD

SMC_ONOFF_L

SMC_SUS_CLK

PM_LAN_PWRGD

MAKE_BASE=TRUE

TP_SMC_P62

SMC_P62

MAKE_BASE=TRUE

TP_SMC_P46

SMC_P46

MAKE_BASE=TRUE

TP_SMC_P64

SMC_P64

TP_SMC_P63

MAKE_BASE=TRUE

SMC_P63

TP_SMC_P81

MAKE_BASE=TRUE

TP_SMC_PF0

MAKE_BASE=TRUE

TP_SMC_PF1

SMC_ENRGYSTR_LDO_EN

MAKE_BASE=TRUE

SMC_BATT_CHG_EN

=PP3V3_S5_S5PWRGD

VOLTAGE=0V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

GND_SMC_AVSS

15pF

50V 402

SMC_MANUAL_RST_L

2.37K

5%

C5000

1

2

R5000

1

2

C5001

1

2

Q5030

1

3

2

R5030

1

2

R5031

1

2

R5032

1

2

C5010

1 2

C5011

1 2

Q5059

6

2

1

C5020

1

2

C5026

1

2

C5025

1

2

VR5020

3

1 2

R5095

1 2

R5070

1 2

R5071

1 2

R5072

1 2

R5073

1 2

R5074

1 2

R5075

1 2

R5076

1 2

R5077

1 2

R5078

1 2

R5079

1 2

R5080

1 2

R5083

1 2

R5084

1 2

R5085

1 2

R5086

1 2

R5087

1 2

R5088

1 2

Y5010

1

2

U5000

5

3

4

1

2

R5089

1 2

R5090

1 2

R5082

1 2

R5081

1 2

R5001

1

2

R5015

1

2

R5045

1

2

C5045

1

2

Q5060

5

3

4

R5061

1

2

Q5060

2

6

1

R5062

1 2

R5060

1

2

Q5059

3

5

4

R5091

1 2

R5093

1 2

R5092

1 2

Q5032

3

1

2

R5096

1 2

R5094

1 2

R5097

1

2

R5098

1 2

45

47

78

47

46

40

45

46

45

56

47

46

53

45

36

46

25

45

25

34

45

43

78

43

45

46 45

45

49

45

25

45

8

45

34

45

8

45

8

45

8

45

7

34

7

24

45

7

45

7

34

7

45

8 8

8

45

34

8

45

BI

IN

OUT OUT OUT

OUT

IN

BI

OUT OUT OUT

OUT

IN

OUT

IN

OUT

BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

FWH_INIT_L Generation

LPC+ Connector

516S0394

7

23 45

7

25 45

7

30 84

7

25 45 46

7

25 45

7

24

7

45 46

7

45

7

45

7

28

7

23 45

7

23 45

7

23 45

7

45 46

7

45 46

7

45

7

25

LPCPLUS

SOT-363-LF

MMDT3904XF

SOT-363-LF

PLACEMENT_NOTE=Place Q5190 close to R5190

LPCPLUS

402

5% 1/16W MF-LF

LPCPLUS

330

1.3K

402

MF-LF

1/16W

5%

LPCPLUS

PLACEMENT_NOTE=Place R5190 to minimize CPU_INIT_L stub

1/16W

5%

MF-LF

402

330

LPCPLUS

10 23 79

7

43 45 46

7

43 45 46

7

45 46

7

45 46

QT500306-L021-9F

M-ST-SM

LPCPLUS

CRITICAL

7

23 45

SYNC_MASTER=M76_MLB

A.0.0

8847

051-7225

LPC+ Debug Connector

SYNC_DATE=03/19/2007

=PP3V3_S5_LPCPLUS =PP5V_S0_LPCPLUS

LPC_AD<0> LPC_AD<1>

LPC_FRAME_L PM_CLKRUN_L BOOT_LPC_SPI_L SMC_TMS

CPU_INIT_LS3V3

FWH_INIT_L PCI_CLK33M_LPCPLUS

LPC_AD<2> LPC_AD<3>

INT_SERIRQ PM_SUS_STAT_L SMC_TDI SMC_TCK SMC_RESET_L SMC_NMI SMC_RX_L

LINDACARD_GPIO

DEBUG_RESET_L SMC_TRST_L SMC_TDO SMC_MD1 SMC_TX_L

CPU_INIT_L

=PP3V3_S0_LPCPLUS

CPU_INIT_R_L

Q5190

5

3

4

Q5190

2

6

1

R5192

1

2

R5191

1

2

R5190

1 2

J5100

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

31

32

33

34

4

5

6

7

8

9

8 8 7

7

8

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Left I/O SMBus Connections: LIO - TMP106

(Write: 0x92 Read: 0x93)

M35B - TMP106

(Write: 0x90 Read: 0x91)

J3400

Left I/O Board

(See Table)

SMC "Battery A" SMBus Connections

MLB/J9600 -- Flex/TMP105 (Write: 0x92 Read: 0x93)

CPU Temp

KXPS5-2050: U5900

ICH8-M SMBus Connections

Clock Chip

SLG8LP537V: U2900

(Write: 0xD2 Read: 0xD3)

SMC

U4900

(Write: 0x9E Read: 0x9F)

(Write: 0x98 Read: 0x99)

GPU Temp (Ext)

(Write: 0xA4 Read: 0xA5)

G84M: U8000

GPU Temp (Int)

(Write: 0xA0 Read: 0xA1)

(MASTER)

SMC

U4900

SO-DIMM "B"

J3200

J3100

SMC "A" SMBus Connections

NOTE: SMC RMT bus remains powered and may be active in S3 state

(MASTER)

SMC "0" SMBus Connections

SMC

U4900

SMC

(MASTER)

U4900

SMC

TMP401: U5550

Top-Case

(MASTER)

U2300

ICH8-M

The bus formerly known as "Battery B"

SO-DIMM "A"

U4900

(MASTER)

J6950

Battery

(Write: 0x16 Read: 0x17)

SMC "Management" SMBus Connections

(Write: 0x30 Read: 0x31)

SMS

(MASTER)

J3400

Left I/O

(See Table)

ICH8-M ME SMBus Connections

Left I/O SMBus Connections:

(Address determined by ARP)

ICH8-M

(MASTER?)

U2300

ExpressCard Slot

Remote Temps

SMC "B" SMBus Connections

EMC1043-5: U5570

(Write: 0x98 Read: 0x99)

EMC1043-5: U5500

4.7K

402

MF-LF

5%

1/16W

4.7K

402

MF-LF

1/16W

5%

1/16W

5%

402

MF-LF

4.7K

402

MF-LF

1/16W

4.7K

5%

402

MF-LF

1/16W

5%

4.7K

MF-LF

402

5%

1/16W

4.7K

3.3K

402

MF-LF

1/16W

5%

3.3K

402

1/16W MF-LF

5%

4.7K

MF-LF 402

1/16W

5%

4.7K

1/16W

5%

402

MF-LFMF-LF

4.7K

1/16W 402

5%

1/16W

402

5%

MF-LF

4.7K

402

5% MF-LF

1/16W

10K

MF-LF

1/16W

402

5%

10K

SMBus Connections

A.0.0

48 88

051-7225

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

SMBUS_SMC_A_S3_SDA

MAKE_BASE=TRUE

SMBUS_SMC_A_S3_SCL

MAKE_BASE=TRUE

=SMBUS_REMTHMSNS_SDA

=SMBUS_REMTHMSNS_SCL

SMB_ME_CLK SMB_ME_DATA

MAKE_BASE=TRUE

SMBUS_SB_ME_SDA

SMBUS_SB_ME_SCL

MAKE_BASE=TRUE

=SMBUS_LIO_SB_SDA

=SMBUS_LIO_SB_SCL

=PP3V3_S5_SMBUS_SB_ME

SMBUS_SB_SDA

MAKE_BASE=TRUE

SMBUS_SB_SCL

MAKE_BASE=TRUE

=PP3V3_GPU_SMBUS_SMC_0_S0

=PP3V3_S3_SMBUS_SMC_MGMT

=SMBUS_BATT_SDA

=SMBUS_BATT_SCL

SMB_MGMT_DATA

SMB_MGMT_CLK

=SMBUS_GPUTHMSNS_SDA

=I2C_TOPCASE_SCL =I2C_TOPCASE_SDA

SMBUS_SMC_BSA_SDA

MAKE_BASE=TRUE

SMBUS_SMC_BSA_SCL

SMB_BSA_DATA

SMB_BSA_CLK

=PP3V42_G3H_SMBUS_SMC_BSA

SMB_DATA

=SMBUS_CK505_SCL

=PP3V3_S3_SMBUS_SMC_A_S3

SMB_A_S3_DATA

SMB_A_S3_CLK

=SMBUS_CK505_SDA

=I2C_SODIMMA_SCL =I2C_SODIMMA_SDA

=I2C_SODIMMB_SCL

=PP3V3_S0_SMBUS_SMC_B_S0

=I2C_CPUTHMSNS_SCL =I2C_CPUTHMSNS_SDA

SMB_B_S0_CLK SMB_B_S0_DATA

=GPU_I2CS_SDA

=I2C_SODIMMB_SDA

=GPU_I2CS_SCL

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SCL

=SMBUS_GPUTHMSNS_SCL

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SDA

SMB_0_S0_DATA

SMB_0_S0_CLK

=I2C_SMS_SDA

=I2C_SMS_SCL

SMBUS_SMC_MGMT_SDA

MAKE_BASE=TRUE

SMBUS_SMC_MGMT_SCL

=PP3V3_S0_SMBUS_SB

SMB_CLK

MAKE_BASE=TRUE

SMBUS_SMC_B_S0_SCL

MAKE_BASE=TRUE

SMBUS_SMC_B_S0_SDA

=SMBUS_LIO_SMC_SDA

=SMBUS_LIO_SMC_SCL

R5200

1

2

R5201

1

2

R5280

1

2

R5281

1

2

R5291

1

2

R5290

1

2

R5261

1

2

R5260

1

2

R5271

1

2

R5270

1

2

R5251

1

2

R5250

1

2

R5231

1

2

R5230

1

2

82

56

82

84

51

25

34

8

7

45

51

78

84

45

8

25

29

8

45

29

31

32

8

51

45

73

32

73

84 51

84

45

54

84

8

25

84

34

IN

OUT

N-CHN

S

D

G

P-CHN

G

D

S

D

S

G

IN

D

S

G

ININ

IN

OUT

IN

OUT

IN

OUT

IN IN

OUT

OUTOUT

OUT

IN

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Enables PBUS VSense divider when high.

S0/GPU 1.25V Current Sense Filter

Place RC close to SMCPlace RC close to SMC

NB 1.8V Current Sense Filter

PBUS Voltage Sense & Filter

Place RC close to SMC

Rthevanin = 4573 ohms

Place RC close to SMC

Battery (PBUS) Current Sense Filter

Place RC close to SMC

DCIN Current Sense Filter

Place RC close to SMC

CPU Current Sense Filter

Place RC close to SMC

Switches in fixed load on power supplies to calibrate current sense circuits

Current Sense Calibration Circuit

Place RC close to SMC

GPU Current Sense Filter

Place RC close to SMC

NB Core Current Sense Filter

GPU Voltage Sense / Filter

CPU Voltage Sense / Filter

Place RC close to SMC

Place short near U8000 center

Place short near U1000 center

NB GFX Current Sense Filter

7

45

100K

5% 1/16W MF-LF

402

100K

402

MF-LF

1/16W

5%

45

402

MF-LF

1/16W

1%

27.4K

20% X5R

402

0.22UF

6.3V

1% 1/16W MF-LF

402

5.49K

SC70-6

FDG6332C_NL

SC70-6

FDG6332C_NL

FDM6296

CRITICAL

MICROFET3X3

ISL9504B

1/16W

1%

MF-LF

402

4.53K

58 65

1206

MF-LF

1/4W

1%

1.00

MICROFET3X3

FDM6296

CRITICAL

50 50

100K

402

MF-LF

1/16W

5%

SN74AHCT1G125DCKRE4

SC70-5

1/16W MF-LF

5%

402

1K

0.1UF

20% 10V

CERM

402

1%

MF-LF

402

4.53K

1/16W

50

6.3V

0.22UF

402

X5R

20%

45

0.22UF

20%

6.3V X5R 402

1/16W

1%

MF-LF

402

4.53K

45

1/16W

4.53K

402

MF-LF

1%

20% X5R

402

0.22UF

6.3V

50 45

402

20% X5R

6.3V

0.22UF

402

1% 1/16W MF-LF

4.53K

74

45

402

6.3V

0.22UF

X5R

20%

1/16W

4.53K

402

MF-LF

1%

34 34

4.53K

402

MF-LF

1/16W

1%

6.3V

0.22UF

402

X5R

20%

45

6.3V

0.22UF

402

X5R

20%

4.53K

402

MF-LF

1%

1/16W

45

0.22UF

20%

6.3V 402

X5R

402

MF-LF

1%

1/16W

4.53K

45

0.22UF

402

20% X5R

6.3V

1/16W

1%

MF-LF

4.53K

402

ISL9504A

50

SM

45

402

1%

4.53K

MF-LF

1/16W

402

X5R

6.3V

20%

0.22UF

SM

1206

MF-LF

1/4W

1%

1.00

49 88

A.0.0

051-7225

Current & Voltage Sensing

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

ISENSE_CAL_EN_LS5V

MIN_LINE_WIDTH=0.50 mm MIN_NECK_WIDTH=0.20 mm

GPUCORE_ISENSE_CAL

=PPVCORE_GPU_REG

SMC_NBGFXCORE_ISENSE

MAKE_BASE=TRUE

SMC_ANALOG_ID

NBGFXCORE_IOUT

NBCORE_IOUT

SMC_NBGFXCORE_ISENSE

GND_SMC_AVSS

SMC_NB_CORE_ISENSE

GND_SMC_AVSS

P1V8_S3_IOUT

=PPVCORE_S0_CPU

GPUVCORE_IOUT

=PPVCORE_S0_CPU_REG

GND_SMC_AVSS

SMC_GPU_ISENSE

LIO_DCIN_ISENSE

SMC_NB_1V8_ISENSE

SMC_DCIN_ISENSE

GND_SMC_AVSS

GND_SMC_AVSS GND_SMC_AVSS

CPUVCORE_ISENSE_CAL

MIN_LINE_WIDTH=0.50 mm MIN_NECK_WIDTH=0.20 mm

SMC_BATT_ISENSE

GND_SMC_AVSS

LIO_BATT_ISENSE

GND_SMC_AVSS

=PPVCORE_GPU_REG

SMC_CPU_VSENSE

CPUVSENSE_IN

SMC_GPU_VSENSE

GPUVSENSE_IN

PPBUS_G3H

GND_SMC_AVSS

MIN_LINE_WIDTH=0.20 mm MIN_NECK_WIDTH=0.20 mm VOLTAGE=18.5V

PPBUS_G3H_VSENSE

GND_SMC_AVSS

P1V25_S0GPU_IOUT

SMC_NB_1V25_ISENSE

SMC_PBUS_VSENSE

PBUSVSENS_EN_DIV

=PBUSVSENS_EN

PBUSVSENS_EN_L

CPUVCORE_IOUT

SMC_CPU_ISENSE

IMVP6_IMON

=PP5V_S0_ISENSECAL

ISENSE_CAL_EN_LS5V_R

ISENSE_CAL_EN

C5359

1

2

R5359

1 2

R5370

1 2

C5370

1

2

C5375

1

2

R5375

1 2

C5380

1

2

R5380

1 2

R5390

1 2

C5390

1

2

C5340

1

2

R5340

1 2

C5335

1

2

R5335

1 2

C5330

1

2

R5330

1 2

XW5359

1 2

R5309

1 2

C5309

1

2

XW5309

1 2

R5320

1

2

R5327

1

2

R5315

1

2

R5385

1

2

C5385

1

2

R5386

1

2

Q5315

6

2

1

Q5315

3

5

4

Q5320

5

4

1 2 3

R5331

1 2

R5322

1

2

Q5322

5

4

1 2 3

R5316

1

2

U5327

2

3 1

5

4

R5328

12

C5327

1 2

R5365

1 2

C5365

1

2

74

53

53 53 53

53

74

53

49

12

58

49

49 49 49

49

8

46

11

8

46

46 46 46

46

8

46

8

7

49

45

8

7

45

45 45 45

45

7

8

45

65

7

OUT

R1-

R1+

R2

V-

V+

+

IN

OUT

R1-

R1+

R2

V-

V+

+

OUT

IN

OUT

R1-

R1+

R2

V-

V+

+

OUT

R1-

R1+

R2

V-

V+

+

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Gain = 100:1

Gain = 165:1

2.0K

1% 1/16W MF-LF 402

SM

402

1%

MF-LF

1/16W

10

0.1UF

402

X5R

16V

10%

49

50V

10% 402

CERM

0.001UF

100K

MF-LF

1/16W

1%

402

MSOP

INA326EA-250

CRITICAL

2.0K

1% 1/16W

402

MF-LF

59

MF-LF

1%

1/4W 1206

0.002

CRITICAL

CERM

402

10% 50V

470PF

1M

MF-LF

402

1%

1/16W

0.1UF

CERM 402

20% 10V

MF-LF

1%

402

1/16W

40.2K

NO STUFF

0.1UF

402

CERM

20% 10V

LMV2011MF

SOT23-5

CRITICAL

1M

MF-LF

402

1%

1/16W

CERM

402

10% 50V

470PF

MF-LF

1%

40.2K

402

1/16W

0.1UF

20% 10V

NO STUFF

CERM

402

49

10

1/16W MF-LF

1%

402

10% 16V X5R 402

0.1UF

0.001UF

CERM

402

10% 50V

CRITICAL

INA326EA-250

MSOP

402

100K

1% 1/16W MF-LF

805-3

CERM-X5R

6.3V

20%

22UF

805-3

CERM-X5R

6.3V

20%

22UF

2.0K

MF-LF 402

1% 1/16W

CRITICAL

0.002

1206

1/4W

1%

MF-LF

49

58

10

1/16W MF-LF

1%

402

49

0.001UF

CERM

402

10% 50V

CRITICAL

1206

1%

MF-LF

1/4W

0.002

10% 16V X5R 402

0.1UF

165K

MF-LF

1/16W

1%

402

805-3

CERM-X5R

6.3V

20%

22UF

INA326EA-250

MSOP

CRITICAL

805-3

CERM-X5R

6.3V

20%

22UF

2.0K

MF-LF 402

1/16W

1%

1/16W

402

1%

10

MF-LF

49

0.001UF

50V

CERM

402

10%

10% 16V X5R 402

0.1UF

805-3

6.3V

20%

22UF

CERM-X5R

805-3

6.3V

20%

22UF

CERM-X5R

CRITICAL

INA326EA-250

MSOP

100K

402

1% 1/16W MF-LF

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

Current Sensing

50 88

A.0.0

051-7225

=PP3V3_S0_NBGFXCOREISNS

P1V8ISNS_R1_N

P1V8ISNS_N

=PP3V3_S0_CPUCOREISNS

CPUVCORE_IOUT

CPUCOREISNS_P

IMVP6_DROOP

P1V25ISNS_R1_N

MIN_LINE_WIDTH=0.25mm VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2mm

PP3V3_S3_P1V25ISNS_VCC

P1V25ISNS_R2

P1V25_S0GPU_IOUT

=PP3V3_S3_P1V25ISNS

P1V25ISNS_N

=PP1V25_ENET_ISNS

=PP1V25_ENET_ISNS_R

P1V8ISNS_R1_P

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.25mm MIN_NECK_WIDTH=0.2mm

PP3V3_S3_P1V8ISNS_VCC

P1V8ISNS_R2

NBCOREISNS_R1_N

NBCOREISNS_R1_P

NBCOREISNS_P

NBCOREISNS_N

=PPVCORE_S0_NBCOREISNS

NBCOREISNS_R2

=PP3V3_S0_NBCOREISNS

P1V8_S3_IOUT

NBGFXISNS_R1_P

MIN_NECK_WIDTH=0.2mm VOLTAGE=3.3V

MIN_LINE_WIDTH=0.25mm

PP3V3_S0_NBGFXISNS_VCC

NBGFXISNS_R2

NBGFXISNS_R1_N

NBGFXCORE_IOUT

GFXIMVP6_PHASE_VSUM

GFXIMVP6_VO

P1V25ISNS_R1_P

P1V25ISNS_P

MIN_LINE_WIDTH=0.25mm VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2mm

PP3V3_S0_NBCOREISNS_VCC

=PPVCORE_S0_NB_R

=PP3V3_S3_P1V8ISNS

NBCORE_IOUT

P1V8ISNS_P

CPUCOREISNS_N

IMVP6_VO

=PP1V8_S3_ISNS_R

=PP1V8_S3_ISNS

C5400

1 2

R5400

1 2

C5401

1

2

R5402

1 2

C5403

1

2

U5400

3

4

1

5

2

R5404

1 2

C5405

12

R5403

1 2

C5404

1

2

R5420

1 2

C5420

1

2

C5422

1

2

U5420

3

2

6

1

8

5

4

7

R5422

1

2

C5426

1

2

C5425

1

2

R5421

1

2

R5425

1 2

R5430

1 2

C5432

1

2

R5435

1 2

C5430

1

2

R5432

1

2

C5436

1

2

U5430

3

2

6

1

8

5

4

7

C5435

1

2

R5431

1

2

R5440

1 2

C5442

1

2

C5440

1

2

C5446

1

2

C5445

1

2

U5440

3

2

6

1

8

5

4

7

R5442

1

2

R5441

1

2

XW5425

1

2

XW5426

1

2

XW5445

1

2

XW5446

1

2

XW5435

1

2

XW5436

1

2

R5410

1 2

C5410

1

2

C5412

1

2

R5412

1

2

U5410

3

2

6

1

8

5

4

7

R5411

1

2

R5445

1 2

8

8 8

87

8

87

8

87

8 8

BI BI BI BI

GND

VDD

SDATA

SCLK

THM*

ALERT*/

D+ D-

THM2*

BI

OUT

IN

VDD

SMDATA

SMCLK

GND

DP1 DN1

DP2 DN2

VDD

SMDATA

SMCLK

GND

DP1 DN1

DP2 DN2

BI BI

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Placement note:

518S0487

(TC0P)

(Th0H)

Placement note:

Place U5550 near GPU

(Th1H)

(TG0P)

CPU T-Diode Thermal Sensor

(Reserved for CPU heatpipe sensor)

NB Thermal Diodes Not Used

(TG0T)

(Th2H)

518S0487

Place on left side of fan cutout

connectors as possible

Keep 2 caps as close to

Placement note:

GPU Die Thermal Sensor

(TC0D)

518S0487

Placement note:

GPU/Heat Pipe & Bottom Case Skin Thermal Sensor

Place near GPU

(TG0H)

Keep 2 caps as close to IC pins as possible

Placement note:

20

10V

20% 402

CERM

0.1uF

402

1/16W

5%

MF-LF

47

5%

18PF

50V CERM 402

NO STUFF

50V 402

CERM

18PF

5%

NO STUFF

M-RT-SM

CRITICAL

BM02B-ACHKS-GAN-TF-LF-SN-M

CRITICAL

M-RT-SM

402

1/16W MF-LF

5%

10K

GPU_TMP401GPU_TMP401

1/16W

10K

5%

402

MF-LF

0.1UF

X5R 402

10% 16V

GPU_TMP401

50V CERM 402

10%

0.001UF

GPU_TMP401

402

MF-LF

1/16W

1%

499

GPU_TMP401

499

1% 1/16W MF-LF

402

GPU_TMP401

CRITICAL

TMP401

MSOP

GPU_TMP401

M-RT-SM

BM02B-ACHKS-GAN-TF-LF-SN-M

CRITICAL

48

72 87

72

402

0.0022uF

CERM

50V

10%

MSOP

EMC1043-5

CRITICAL

10% 50V

CERM

0.0022uF

402

MSOP

EMC1043-5

CRITICAL

48

10V

0.1uF

20% CERM

402

MF-LF

5%

1/16W

47

402

0.0022uF

10% 50V

CERM

402

470PF

10% 50V

CERM

402

10 87

10

SYNC_DATE=(MASTER)

Thermal Sensors

51 88

A.0.0

051-7225

SYNC_MASTER=(MASTER)

=SMBUS_REMTHMSNS_SDA

=SMBUS_REMTHMSNS_SCL

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

PP3V3_S3_REMTHMSNS_R

HSTHMSNS_D_P

HSTHMSNS_D_N

RSFSTHMSNS_D_N

RSFSTHMSNS_D_P

=GND_CHASSIS_J5590

CPUTHMSNS_D2_N

=PP3V3_S0_GPUTHMSNS

GPU_TDIODE_P

GPUTHMSNS_D_N

GPU_TDIODE_N

GPUTHMSNS_D_P

=PP3V3_S0_CPUTHMSNS

GPUTHMSNS_THM_L

GPUTHMSNS_ALERT_L

CPUTHMSNS_D2_P

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

PP3V3_S0_CPUTHMSNS_R

CPU_THERMD_P

CPU_THERMD_N

=I2C_CPUTHMSNS_SDA

=I2C_CPUTHMSNS_SCL

=PP3V3_S3_REMTHMSNS

=SMBUS_GPUTHMSNS_SDA

=SMBUS_GPUTHMSNS_SCL

=NB_TDE_SENSE =NB_TDE_FORCE

=NB_TDB_SENSE

=NB_TDB_FORCE

U5570

2

4

1

3

5

8 7

6

C5570

1

2

R5570

1 2

C5590

1

2

C5580

1

2

C5500

1

2

R5500

1 2

C5510

1

2

C5520

1

2

J5510

3

4

1 2

J5520

3

4

1 2

R5552

1

2

R5551

1

2

C5550

1

2

C5560

1

2

R5560

1 2

R5561

1 2

U5550

6

3

2

5

8 7

4

1

J5590

3

4

1 2

C5511

1

2

U5500

2

4

1

3

5

8 7

6

C5521

1

2

87

7

9

7

8

87

8

7

8

G

S D

G

S D

IN

OUT OUT

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

518S0369

Left Fan

Right Fan

518S0369

MF-LF

5%

402

47K

1/16W

47K

402

MF-LF

5%

1/16W

5%

47K

MF-LF

402

5% 1/16W MF-LF

47K

402

100K

1/16W

5%

MF-LF

402

SOT-363

2N7002DW-X-F

1/16W

402

MF-LF

5%

100K

2N7002DW-X-F

SOT-363

M-RT-SM

SM04B-ACH

CRITICAL

M-RT-SM

SM04B-ACH

CRITICAL

45

45 45

45

SYNC_DATE=03/19/2007

SYNC_MASTER=M76_MLB

52 88

051-7225

A.0.0

Fan Connectors

=PP5V_S0_FAN_LT

FAN_LT_TACH

FAN_LT_PWM

=PP3V3_S0_FAN_RT

FAN_RT_TACH

=PP5V_S0_FAN_RT

FAN_RT_PWM

=PP3V3_S0_FAN_LT

SMC_FAN_0_TACH

SMC_FAN_0_CTL

SMC_FAN_1_TACH

SMC_FAN_1_CTL

R5650

1

2

R5655

1 2

R5660

1

2

R5665

1 2

R5651

1

2

Q5660

3

5

4

R5661

1

2

Q5660

6

2

1

J5650

5

6

1 2 3 4

J5660

5

6

1 2 3 4

8 7

7

8

7

8

7

8

V+

V-

G

D

S

IN

OUT

IN

OUT

IN

THRML

CAP

SW

LED

VIN

CTRL

PAD

GND

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

WF: This circuit does not use return, can tie cathode to GND on topcase flex

Left ALS Filter

Left ALS circuit has 1K series-R

Keyboard LED Driver

RTALS_OP_IN and RTALS_OP_COMP need to be matched

Right ALS Circuit

MAX4236EUTT

SOT23-6-LF

CRITICAL

CERM

402

20% 10V

0.1UF

120K

MF-LF 402

5% 1/16W

0.22UF

X5R 402

20%

6.3V

15.0K

MF-LF 402

1% 1/16W

1K

MF-LF

402

1%

1/16W

MF-LF

402

1%

1/16W

1K

BS520EOF

TH

CRITICAL

5.1M

MF-LF

402

5%

1/16W

0.01UF

CERM

20% 16V

402

2N7002

SOT23-LF

7

45 78

45

4.53K

MF-LF

402

1%

1/16W

0.22UF

X5R

20%

6.3V 402

45

6.3V

20%

402

X5R

0.22UF

1/16W

1%

402

MF-LF

3.48K

7

78

CRITICAL

10UH-0.58A

DE2812C-SM

10V

1UF

20%

603

CERM

MF-LF

5%

1/16W

10K

402

45

402

1/16W

10

1% MF-LF

78

X5R

1UF

25V

10% 603

78

CRITICAL

LT3491

DFN

ALS Support

53 88

051-7225

A.0.0

SYNC_MASTER=M76_MLB

SYNC_DATE=03/19/2007

KBDLED_RETURN

SMC_SYS_KBDLED

KBDLED_ANODE

ALS_LEFT

GND_SMC_AVSS

RTALS_GAIN_L

RTALS_PHOTODIODE

RTALS_OP_IN

GND_SMC_AVSS

ALS_RIGHT

ALS_RT_OUT

=PP3V3_S3_RTALS

RTALS_OP_COMP

ALS_GAIN

LTALS_OUT

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.3 MM

KBDLED_SW

=PP5V_S0_KBDLED

KBDLED_CAP

U5805

3

4

1

5

6

2

C5805

1

2

R5806

1

2

C5806

1

2

R5807

1

2

R5808

1

2

R5801

1 2

PD5800

1

2

R5800

1

2

C5800

1

2

Q5808

3

1

2

R5810

1 2

C5810

1

2

C5830

1

2

R5830

1 2

L5850

1 2

C5850

1

2

R5852

1

2

R5855

1

2

C5855

1

2

U5850

4

6

2

5

3

7

1

53

49

46

45

8

CS*

SCL/SCLK

ADDR/SDI

MOT_ENABLE

ENABLE

VDD

X Y Z

FF/MOT

SDA/SDO

GND

IN

OUT OUT OUT

OUT

BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

APN:338S0354

Desired orientation when

+Z (up)

ADDR low => 0x30, 0x31 ADDR high => 0x32, 0x33

I2C addresses:

Alias SCL/SDA to GND if using analog outputs only

+X

1

+Z (dn)

Package Top

1

+X

+Y +Y

Desired orientation when placed on board top-side:

Top-through View

placed on board bottom-side:

0.1uF

CERM 402

20% 10V

402

X5R

16V

10%

0.033UF

402

X5R

16V

10%

0.033UF

CRITICAL

LGA

KXPS5-2050

10K

MF-LF

402

5%

1/16W

45

1/16W

5%

402

MF-LF

0

SMS_MOT_EN

0

5% 1/16W MF-LF 402

SMS_MOT_DIS

5%

1/16W

MF-LF

402

100K

9

48

402

0.033UF

16V

10% X5R

54 88

A.0.0

051-7225

Sudden Motion Sensor (SMS)

SYNC_MASTER=M76_MLB

SYNC_DATE=03/19/2007

SMS_ONOFF_L

SMS_Z_AXIS

SMS_MOT_EN

SMC_SMS_INT

=PP3V3_S3_SMS

=I2C_SMS_SCL

SMS_Y_AXIS

=I2C_SMS_SDA

SMS_X_AXIS

C5901

1

2

C5900

1

2

C5902

1

2

C5903

1

2

U5900

3

2

6

11

10

12

5

4

11314

7 8 9

R5900

1

2

R5901

1

2

R5902

1

2

R5903

1

2

8

SO

VDD

CE*

SCK

VSS

HOLD*

SI

WP*

OUT

IN

IN IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

CERM

20% 10V

0.1UF

402

1/16W

5%

3.3K

MF-LF

402

1/16W

5%

MF-LF

3.3K

PLACEMENT_NOTE=Place R6114 within 12.7mm of U6100

15

MF-LF

5%

1/16W

402

OMIT

SST25VF016B

SOI

16MBIT

CRITICAL

24 82

MF-LF

5%

1/16W

15

402

PLACEMENT_NOTE=Place R6190 within 12.7mm of U2300

402

MF-LF

5%

1/16W

15

PLACEMENT_NOTE=Place R6191 within 12.7mm of U2300

24 82

PLACEMENT_NOTE=Place R6193 within 12.7mm of U2300

MF-LF

5%

1/16W

15

402

24 82

SYNC_MASTER=T9_NOME

SYNC_DATE=03/16/2007

051-7225

A.0.0

8855

SPI BootROM

=PP3V3_S5_ROM

SPI_SI_R

SPI_SO

SPI_HOLD_L

SPI_A_SI_R

SPI_WP_L

SPI_A_SO_R

SPI_SCLK

SPI_CE_L<0>

SPI_SCLK_R

SPI_CE_R_L<0>

C6100

1

2

R6101

1

2

R6100

1

2

R6114

1 2

U6100

1

7

6

5

2

8

4

3

R6190

1 2

R6191

1 2

R6193

1 2

8

82

OUT

BI BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

518S0369

518S0458

Left I/O Power Connector

Battery Connector (Digital Signals)

7

45 46

7

48

7

48

87438-0663

M-RT-SM

CRITICAL

M-RT-SM

SM04B-ACH

CRITICAL

402

8V-100PF

NO STUFF

402

8V-100PF

NO STUFF

8V-100PF

402

NO STUFF

8V-100PF

402

NO STUFF

5% 1/16W MF-LF 402

10

PBus-In & Battery Connectors

A.0.0

8856

051-7225

SYNC_MASTER=(M59_SYNC)

SYNC_DATE=09/09/2006

=PPBUS_G3H_LIO_CONN

MIN_NECK_WIDTH=0.2 mm

GND_BATT

MIN_LINE_WIDTH=0.4 mm VOLTAGE=0V

=SMBUS_BATT_SDA SMC_BS_ALRT_L

=SMBUS_BATT_SCL

R6950

1

2

J6900

1 2 3 4 5 6

J6950

5

6

1 2 3 4

DZ6951

1

2

DZ6950

1

2

DZ6963

1

2

DZ6962

1

2

8 7

7

D

SG

D

SG

D

SG

D

SG

D

SG

D

SG

D

SG

G

D

S

G

D

S

G

D

S

G

D

S

G

D

S

D

S

G

D

S

G

D

S

G

IN

D

SG

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

3.3V S0 FET

1.25V S0 FET

5V S3 FET

1.8V S0 FET

3.3V GPU FET

1.8V GPU FET

PBUS used for lower Rds(on)

1.25V GPU FET

5V S0 FET

3.3V S3 FET

SOT563

SSM6N15FE

SOT563

SSM6N15FE

SOT563

SSM6N15FE

SOT563

SSM6N15FE

SOT563

SSM6N15FE

SOT563

SSM6N15FE

SOT-363

2N7002DW-X-F

SOT-363

2N7002DW-X-F

SOT-363

2N7002DW-X-F

SOT-363

SOT23-LF

2N7002

TSSOP

IRF7707PBF

CRITICAL

SM-LF

CRITICAL

FDC638P

FDC637AN

SOT23

CRITICAL

SM-LF

FDC638P

CRITICAL

SM-LF

FDC638P

CRITICAL

SM-LF

FDC638P

CRITICAL

FDC637AN

SOT23

CRITICAL

RJK0301DPB

LFPAK

CRITICAL

MICROFET3X3

FDM6296

6.3V

0.15UF

10%

402

CERM-X5R

65

499

402

1%

MF-LF

1/16W

0.15UF

6.3V CERM-X5R

10%

402

100K

MF-LF

402

1/16W

5%

15.0K

402

MF-LF

1/16W

1%

16V

10% X5R

402

0.1UF

69.8K

402

1/16W MF-LF

1%

1/16W MF-LF

499

1%

402

65

10%

402

CERM

0.01UF

16V

402

X5R

10V

10%

1UF

100K

5% 1/16W MF-LF

402

MF-LF

1/16W

5%

10K

65

402

10% CERM-X5R

6.3V

0.15UF

402

1%

499

1/16W MF-LF

499

402

1%

MF-LF

1/16W

0.15UF

402

10% CERM-X5R

6.3V

MF-LF

402

100K

1/16W

5%

1/16W MF-LF

402

100K

5%

CERM

402

20%

0.1UF

10V

15.0K

402

MF-LF

1/16W

1%

402

69.8K

1% 1/16W MF-LF

220K

5%

MF-LF

1/16W

402

1%

MF-LF

402

1/16W

15.0K

16V

10% X5R

0.1UF

402

10V

0.1UF

20%

CERM

402

69.8K

1% 1/16W MF-LF

402

65

402

CERM

0.068UF

10V

10%

402

CERM

0.01UF

16V

MF-LF

1/16W

1%

69.8K

402

1/16W

402

MF-LF

5%

10K

1/16W MF-LF

402

5%

47K

65

10%

402

CERM

0.01UF

16V

402

10%

0.033UF

X5R

16V

100K

5% 1/16W MF-LF

402

MF-LF

1/16W

5%

10K

65

CERM

402

16V

0.01UF

10%

402

10V

10%

0.068UF

CERM

402

MF-LF

1/16W

5%

47K

10K

5% 1/16W MF-LF

402

1% 1/16W MF-LF

402

15.0K

65

16V

0.01UF

CERM

402

10%

402

X5R

10%

0.033UF

16V

402

MF-LF

1/16W

5%

100K

10K

5% 1/16W MF-LF

402

65

SOT563

SSM6N15FE

88

051-7225

57

A.0.0

Power FETs

SYNC_DATE=03/19/2007

SYNC_MASTER=M76_MLB

=PP1V25_S0_P1V25S0FET

=PP5V_S5_P1V25S0FET

=PPBUS_S5_P1V25S0FET

P5VS3_EN_L

P1V8GPU_SS

=PP1V8_GPU_P1V8GPUFET

P3V3S3_SS

=PP3V3_S3_FET

P3V3GPU_SS

=PP3V3_GPU_P3V3GPUFET

=PP3V3_GPU_FET

=PP3V3_S0_P3V3S0FET

=PP3V3_S0_FET

=P5VS0_EN

P5VS3_SS

=PP5V_S0_P5VS0FET

P5VS0_SS

=P3V3GPU_EN

P3V3GPU_EN_L

=P3V3S0_EN

P3V3S0_EN_L

P5VS0_EN_L

=P3V3S3_EN

P3V3S3_EN_L

=P5VS3_EN

P1V8GPU_EN_L_RC

P1V8GPU_EN_L

=P1V25GPU_EN

P1V25GPU_EN_L

=P1V25S0_EN

P1V25S0_EN_L

P1V25S0_EN_L_RC

=PP5V_S5_P1V8GPUFET

P1V25GPU_SS_RC

P3V3S0_SS

=PP1V25_GPU_FET

P1V25GPU_SS

P1V25GPU_EN_L_RC

=P1V8GPU_EN

=PP1V25_GPU_P1V25GPUFET

=PP5V_S5_P1V25GPUFET

=P1V8S0_EN

=PP1V8_S0_P1V8S0FET

=PP1V8_S0_FET

P1V8S0_SS

P1V8S0_EN_L_RC

=PP5V_S5_P1V8S0FET

P1V8S0_EN_L

P1V8S0_SS_RC

=PP5V_S3_P5VS3FET

=PP5V_S3_FET

=PP1V8_GPU_FET

P1V8GPU_SS_RC

=PPBUS_S5_P1V8GPUFET

=PP5V_S0_FET

=PP3V3_S3_P3V3S3FET

P1V25S0_SS

=PP1V25_S0_FET

P1V25S0_SS_RC

C7090

1

2

R7093

1 2

R7092

1 2

C7093

1 2

R7091

1

2

R7090

1 2

R7083

1 2

C7080

1

2

R7082

1 2

R7080

1 2

C7083

1 2

R7081

1

2

C7070

1 2

C7071

1

2

R7070

1 2

R7072

1

2

C7050

1

2

R7053

1 2

R7098

1 2

C7096

1

2

R7052

1 2

C7053

1 2

R7050

1 2

R7051

1

2

R7097

1 2

R7096

1 2

C7095

1 2

R7095

1

2

C7001

1

2

C7000

1 2

R7002

1

2

R7000

1 2

C7010

1 2

C7011

1

2

R7010

1 2

R7012

1

2

C7020

1 2

C7021

1

2

R7020

1 2

R7022

1

2

C7030

1 2

C7031

1

2

R7030

1 2

R7032

1

2

Q7091

6

2

1

Q7091

3

5

4

Q7081

3

5

4

Q7081

6

2

1

Q7051

3

5

4

Q7051

6

2

1

Q7096

3

5

4

Q7096

6

2

1

Q7002

6

2

1

Q7012

6

2

1

Q7002

3

5

4

Q7012

3

5

4

Q7072

3

1

2

Q7020

1 5 8

4

2 3 6 7

Q7000

1

2

5

6

3

4

Q7090

1 2 5 6

3

4

Q7070

1

2

5

6

3

4

Q7030

1

2

5

6

3

4

Q7010

1

2

5

6

3

4

Q7050

1 2 5 6

3

4

Q7080

5

4

1 2 3

Q7095

5

4

1 2 3

8

9

8

IN

OUT

IN

OUT

IN

OUT OUT

IN

OUT

VID0

DPRSTP*

NC

VW

COMP

FB

FB2

RBIAS

VR_TT* NTC

VR_ON PGOOD

PSI*

RTN

VSEN

DFB

DROOP

VO

OCSET

VSUM

ISEN2

VID1

VID3 VID2

VID4

VID5

VID6

PGND2

VIN VDD

PVCC

LGATE2

PHASE2

UGATE2

ISEN1

PGND1

LGATE1

UGATE1

PHASE1

BOOT1 BOOT2

3V3

VDIFF

SOFT

DPRSLPVR

TPAD

GND

CLK_EN*

IMON

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(GND_IMVP6_SGND)

(IMVP6_FB)

(GND_IMVP6_SGND)

(IMVP6_NTC)

Place R7126 in hot spot of reg circuit.

These caps are for Q7102

(IMVP6_VW)

(IMVP6_COMP)

(GND)

(IMVP6_VO)

(IMVP6_ISEN2)

(IMVP6_ISEN1)

(IMVP6_PHASE2)

1

0

1

0 1

0

1 0

0

1

PSI*

1-Phase

Operation

2-Phase

1-Phase

CCM

DCM

Mode

CCM

These caps are for Q7100

(IMVP6_PHASE1)

44A MAX CURRENT

(PGD_IN) (ISL9504A)

(IMVP6_VSUM)

DPRSTP*

DPRSLPVR

LAYOUT NOTE:

CERM

NO STUFF

0.0022UF

10% 50V

402

10K

1/16W MF-LF

1%

402

10%

0.22UF

10V

CERM

SM

20%

0.22UF

25V 603

X5R

7

10 16 23 79

7

16 25 79

28

7

45

7 9

16 28

SM

10K

1/16W MF-LF

1%

402

10%

0.22UF

10V

CERM

NO STUFF

CERM 402

50V

10%

0.0022UF

20%

603

X5R

25V

0.22UF

MF-LF

1%

402

10

1/16W

10

402

1/16W MF-LF

1%

X5R

10%

1UF

10V 402

1/16W MF-LF

402

10

1%

16V 402

10%

0.1uF

X5R

499

1/16W

402

1%

MF-LF

402

ISL9504B

CERM

50V

10%

0.001UF

ISL9504B

402

MF-LF

1/16W

1%

6.81K

CERM

6.3V

20% 603

4.7uF

CERM

402

16V

0.01uF

10%

ISL9504B

402

1% 1/16W MF-LF

1K

ISL9504B

402

MF-LF

1/16W

1%

1K

ISL9504B

402

50V

220PF

X7R-CERM

10%

ISL9504B

402

1/16W MF-LF

1%

97.6K

402

MF-LF

1/16W

5%

1

MF-LF

1/16W

5%

1

402

CERM

402

50V

10%

NO STUFF

0.001uF

402

1/16W MF-LF

1%

3.74K

CERM

50V 402

5%

180pF

MF-LF

1% 1/16W

402

1K

402

MF-LF

1%

1/16W

1.18K

402

1/16W MF-LF

1%

9.09K

0.22UF

10%

402

6.3V

CERM-X5R

10% 402

CER

56NF

10V

402

0

1/16W MF-LF

5%

CERM

10%

402

16V

0.01uF

SIGNAL_MODEL=EMPTY

CERM 402

16V

0.01uF

10%

NO STUFF

5%

1/16W

402

MF-LF

0

CERM

402

16V

0.01uF

10%

0.22UF

6.3V

20%

402

X5R

SM

3.65K

MF-LF 603

1% 1/10W

3.65K

1/10W 603

MF-LF

1%

CRITICAL

FDUE1030D-SM

0.36UH-27A

CRITICAL

FDUE1030D-SM

0.36UH-27A

16V

10% 402

X5R

0.1UF

7

12 79

7

12 79

7

12 79

7

12 79

7

12 79

7

12 79

7

12 79

CERM

50V

10%

0.001UF

402

ISL9504B

CERM 402

50V

10%

470PF

ISL9504B

402

MF-LF

1%

1/16W

255

402

16V

10%

0.015UF

X7R

13.3K

1/16W

1% MF-LF

402

25V

10% X5R

603

1UF

CRITICAL

0603-LF

10KOHM-5%

1/16W 402

MF-LF

1%

147K

1/16W

402

1%

MF-LF

4.02K

MF-LF 402

1/16W

5%

2.0K

SM

50 58

11 79

CRITICAL

402

470K

402

5%

MF-LF

0

1/16W

10 46 79

NO STUFF

402

5% MF-LF

68

1/16W

OMIT

QFN

ISL9504BCRZ

LFPAK

RJK0305DPB

CRITICAL

LFPAK

RJK0301DPB

CRITICAL

LFPAK

RJK0305DPB

CRITICAL

RJK0301DPB

CRITICAL

LFPAK

RJK0301DPB

CRITICAL

RJK0301DPB

LFPAK

CRITICAL

POLY

20%

CRITICAL

25V

22UF

CASE-D2-LF CASE-D2-LF

20%

POLY

CRITICAL

25V

22UF22UF

20%

CRITICAL

POLY

25V

CASE-D2-LF

1UF

603

X5R

10% 25V

49 65

I848I849

IMVP6 CPU VCore Regulator

051-7225

A.0.0

58 88

SYNC_MASTER=M76_MLB

SYNC_DATE=01/23/2007

=PP5V_S0_CPU_IMVP

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V

PP5V_S0_IMVP6_VDD

IMVP6_VSUM

=PPVIN_S5_CPU_IMVP

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

IMVP6_VSEN_P

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

IMVP6_VSEN_N

IMVP6_ISEN2

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.2 MM

IMVP6_ISEN1

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

IMVP6_UGATE1

MIN_NECK_WIDTH=0.2 MM

MIN_NECK_WIDTH=0.25 MMMIN_LINE_WIDTH=0.25 MM

IMVP6_VSUM1

IMVP6_COMP

MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MM

IMVP6_VW

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

IMVP6_VW

IMVP6_LGATE1

IMVP6_BOOT1 IMVP6_BOOT2

IMVP6_UGATE1 IMVP6_PHASE1

IMVP6_ISEN1

IMVP6_UGATE2

IMVP6_LGATE2

IMVP6_ISEN2

IMVP6_OCSET

IMVP6_VSEN_P

IMVP_DPRSLPVR

IMVP6_DFB

IMVP6_DROOP

MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MM

IMVP6_OCSET

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

IMVP6_DROOP

IMVP6_FB

MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MM

IMVP6_VO

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

IMVP6_DFB

MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MM

IMVP6_SOFT

MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MM

IMVP6_RBIAS

MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MM

IMVP6_VDIFF IMVP6_FB2

MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MM

MIN_LINE_WIDTH=1.5 MM

IMVP6_PHASE1

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

IMVP6_BOOT1

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.25 MM

IMVP6_LGATE1

MIN_NECK_WIDTH=0.25 MM

IMVP6_VO1

MIN_LINE_WIDTH=0.25 MM

IMVP6_VID<6>

IMVP6_VO2

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM

IMVP6_VSUM2

IMVP6_VO1

IMVP6_VO2

IMVP6_VO_R

IMVP6_VDIFF_RC

IMVP6_COMP_RC

IMVP6_VSUM1

=PPVCORE_S0_CPU_REG

IMVP6_VSUM2

CPU_VCCSENSE_N

CPU_VCCSENSE_P

VR_PWRGD_CLKEN_L

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.5 MM

IMVP6_LGATE2

MIN_LINE_WIDTH=0.5 MM

IMVP6_UGATE2

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

IMVP6_BOOT2

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=1.5 MM

IMVP6_PHASE2

MIN_NECK_WIDTH=0.2 MM

IMVP6_PSI_L

IMVP6_NTC_R

PM_DPRSLPVR

IMVP6_VID<3>

IMVP6_VID<4>

IMVP6_VID<1>

IMVP6_IMON

IMVP6_VID<2>

IMVP6_VID<0>

IMVP_VR_ON VR_PWRGOOD_DELAY

CPU_PROCHOT_L

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.2 MM

PPVIN_S5_IMVP6_VIN

MIN_LINE_WIDTH=0.25 MM

IMVP6_COMP

IMVP6_VID<5>

CPU_DPRSTP_L

IMVP6_NTC

=PP3V3_S0_IMVP

PP3V3_S0_IMVP6_3V3

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

IMVP6_FB

IMVP6_RBIAS

IMVP6_SOFT

IMVP6_PHASE2

IMVP6_VDIFF

IMVP6_FB2

IMVP6_VR_TT_L

VOLTAGE=0V

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.50 MM

GND_IMVP6_SGND

=PPVIN_S5_CPU_IMVP_VIN

IMVP6_VO

IMVP6_VSEN_N

C7100

1

2

R7100

1 2

C7103

1 2

XW7104

12

C7115

1

2

XW7102

12

R7105

1 2

C7104

1 2

C7102

1

2

C7127

1

2

R7120

1 2

R7112

1 2

C7126

1

2

R7121

1 2

C7130

1

2

R7119

1 2

C7107

1

2

R7110

1

2

C7135

1

2

C7110

1

2

R7113

1

2

R7109

1

2

C7113

1

2

R7114

1

2

R7104

1

2

R7107

1

2

C7116

1

2

R7117

1 2

C7129

1

2

R7118

1

2

R7130

1

2

R7115

1

2

C7128

1

2

C7134

1

2

R7122

1 2

C7131

1

2

C7132

1

2

R7123

1 2

C7133

1

2

C7121

1

2

XW7100

1 2

R7101

1

2

R7106

1

2

L7100

1 2

L7101

1 2

C7196

1

2

C7106

1

2

C7114

1

2

R7111

1

2

C7105

1

2

R7116

1

2

C7109

1

2

R7131

1

2

R7108

1

2

R7127

1

2

R7197

1

2

XW7103

1 2

XW7101

1 2

R7126

1

2

R7198

1 2

R7199

1

2

U7100

48

36 26

47

10

17

45

46

16

11

12

21

3

24

23

32

30

25

6

8

33

29

1

34

28

2

31

4

15

7

49

35

27

22

13

37

38

39

40

41

42

43

20

18

44

5

14

19

9

Q7100

5

4

1 2 3

Q7103

5

4

1 2 3

Q7102

5

4

1 2 3

Q7105

5

4

1 2 3

Q7104

5

4

1 2 3

Q7101

5

4

1 2 3

C7117

1

2

C7153

1

2

C7155

1

2

C7154

1

2

49

79 79

79

58

8

79

8

58 58

58

58 58

58

7

58

50

58

50

58

58 58

58

7

58

8

58

8

58

OUT

IN IN

IN

S

D

G

OUT OUT

OCSET

VO

DFB

COMP

VSUM

DROOP

RTN

VDIFF

PGND

VSS

THRM_PAD

VSEN

FDE

AF_EN

VID4

SOFT

FB

VW

VR_ON

VID3

VID2

PGOOD VID0

LGATE

UGATE

PHASE

BOOT

RBIAS

VIN

PVCC

VID1

VDD

IMON

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(GFXIMVP6_AGND)

(VO/PHASE_VSUM offpage flags for current sensing)

VO=Sense-, PHASE_VSUM=Sense+

(GFXIMVP6_PHASE_VSUM)

(GFXIMVP6_VO)

(GND) (NB VID0) (NB VID1)

ENTER DIODE-EMULATION-MODE IN ALL STATES

NOTE: Intel recommendation to stuff 30K pull-up and 100K pull-down on VR_EN per Crestline Issue #306022.

(NB VID2) (NB VID3)

(GFXIMVP6_VO)

ENABLED WHEN GFXIMVP6_AF_EN = 1

WHEN GFXIMVP6_FDE = 1

(GFXIMVP6_AF_EN) (GFXIMVP6_FDE)

Vout according to VID 10A max output (Q7250 limit)

IN RENDER SUSPEND STATE, AUDIO FILTER

402

1/16W

1%

MF-LF

150K

CERM

402

16V

0.01uF

10%

0

MF-LF

5%

1/16W

402

0.22uF

10V

CERM

402

10%

402

1/16W

1%

MF-LF

6.98K

CERM 402

50V

10%

0.001UF

CERM 402

10% 50V

470pF

NO STUFF

CERM

402

50V

10%

0.001UF

CERM 402

0.0033UF

50V

10%

330pF

50V

10%

402

CERM

0.1uF

10% 16V

402

X5R

750

1/16W

1%

MF-LF

402

SM

1K

5% 1/16W

402

MF-LF

402

1/16W

5%

MF-LF

0

PLACEMENT_NOTE=Place R7220 at NB

402

1/16W

5%

MF-LF

0

402

PLACEMENT_NOTE=Place R7221 at NB

1/16W

5%

MF-LF

0

0.001UF

CERM 402

50V

10%

402

1/16W

5%

MF-LF

1K

1/16W

402

1%

MF-LF

10

X5R 402

10% 10V

1uF

10V

10%

402

X5R

10%

0.01uF

16V 402

CERM

680pF

50V

10% 402

CERM

402

MF-LF

NO STUFF

5%

1/16W

10K

MF-LF

402

1/16W

5%

20K

NO STUFF

402

1/16W

5%

MF-LF

10K

NO STUFF

402

1/16W

5%

10K

MF-LF

402

1/16W

5% MF-LF

10K

SM SM

5%

1/16W

402

MF-LF

1

X5R 603

10UF

6.3V

20%

X5R

20%

6.3V 603

10UF

15.0K

MF-LF

1%

1/16W

402

1/16W MF-LF

1%

402

3.01K

0.47UH-26A

IHLP2525CZ-SM

CRITICAL

POLY

CASE-D2-LF

20%

22UF

25V

603

1UF

X5R

25V

10%

603

1UF

10% X5R

25V

402

1/16W

1% MF-LF

158K

CERM 402

50V

5%

120PF

402

1/16W

1% MF-LF

2.21K

402

1/16W

1% MF-LF

3.65K

0

402

1/16W

5% MF-LF

NO STUFF

402

10% 50V

820PF

CERM

402

10% 50V

680PF

9

59

9

59

9

59

9

59

9

59

22K

MF-LF

402

1/16W

5%

402

1/16W MF-LF

22K

5%

22K

MF-LF

402

1/16W

5%

402

1/16W

5%

100K

MF-LF

402

1/16W

5%

30K

MF-LF

402

1/16W

5%

22K

MF-LF

9

59

SI7114DN

PWRPK-1212-8

CRITICAL

SI7108DNS

CRITICAL

PWRPK-1212-8

CRITICAL

TANT D2T

10%

330UF

2.0V

1%

MF-LF

1/4W

0.002

1206

402-1

CERM

5%

68PF

50V

50

QFN

ISL6263B

CRITICAL

SYNC_DATE=03/19/2007

A.0.0

051-7225

SYNC_MASTER=M76_MLB

8859

IMVP6 NB Gfx Core Regulator

GFXIMVP6_VID<0>

=PPVCORE_S0_NBGFX_REG

PPVCORE_S0_NBGFXSENSE_R

MIN_LINE_WIDTH=0.6MM VOLTAGE=1.0V

MIN_NECK_WIDTH=0.3MM

=PP5V_S0_GFXIMVP6

MIN_NECK_WIDTH=0.3MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_VDIFF_RC

MIN_NECK_WIDTH=0.3MM

GFXIMVP6_COMP_RC

MIN_LINE_WIDTH=0.3MM

MIN_NECK_WIDTH=0.3MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_VDIFF

=PPVCORE_S0_NBGFX_VSEN

GFXIMVP6_BOOT_RC

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.3MM

=PP3V3_S0_GFXIMVP6

=PPVIN_S0_GFXIMVP6

GFXIMVP6_VID<1> GFXIMVP6_VID<2>

GFXIMVP6_VID<4> GFX_VR_EN

GFXIMVP6_VID<3>

MIN_NECK_WIDTH=0.3MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_PHASE_VSUM

=PP3V3_S0_GFXIMVP6

GFXIMVP6_IMON

PP5V_S0_GFXIMVP6_VDD

MIN_LINE_WIDTH=0.3MM VOLTAGE=5V

MIN_NECK_WIDTH=0.2MM

GFXIMVP6_VID<1>

MIN_NECK_WIDTH=0.2MM

PP5V_S0_GFXIMVP6_PVCC

MIN_LINE_WIDTH=0.3MM VOLTAGE=5V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_VIN

GFXIMVP6_RBIAS

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_BOOT

MIN_NECK_WIDTH=0.2MM

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.6MM

GFXIMVP6_PHASE

MIN_NECK_WIDTH=0.2MM

GFXIMVP6_UGATE

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.3MM

GFXIMVP6_LGATE

GFXIMVP6_PGOOD

GFXIMVP6_VID<2> GFXIMVP6_VID<3>

GFX_VR_EN

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_VW

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_FB

MIN_NECK_WIDTH=0.2MM

GFXIMVP6_SOFT

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

GFXIMVP6_VID<4>

GFXIMVP6_AF_EN GFXIMVP6_FDE

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_VSEN_P

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

GND_GFXIMVP6_AGND

VOLTAGE=0V

GFXIMVP6_VDIFF_R

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_VSEN_N

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_DROOP

MIN_NECK_WIDTH=0.2MM

GFXIMVP6_VSUM

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_COMP

MIN_NECK_WIDTH=0.2MM

GFXIMVP6_DFB

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

GFXIMVP6_VO

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

GFXIMVP6_OCSET

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

R7202

2 1

C7203

12

R7251

1 2

C7256

1

2

R7222

1

2

C7222

1

2

C7233

1

2

C7221

1

2

C7220

1

2

C7271

1 2

C7272

1

2

R7277

1 2

XW7200

1 2

R7271

1

2

R7232

1 2

R7220

1 2

R7221

1 2

C7223

1

2

R7250

1

2

R7200

1 2

C7200

1

2

C7201

1

2

C7202

1

2

C7251

1

2

R7204

1

2

R7203

2 1

R7205

1

2

R7206

1

2

R7207

1

2

XW7201

1

2

XW7202

1

2

R7208

1 2

C7266

1

2

C7265

1

2

R7270

1 2

R7272

2

1

L7200

1 2

C7252

C7253

1

2

C7254

1

2

R7230

1

2

C7232

1

2

R7233

1

2

R7231

1

2

R7201

2

1

C7230

12

C7231

1 2

R7291

1

2

R7292

1

2

R7294

1

2

R7296

1

2

R7295

1

2

R7293

1

2

Q7250

5

4

1 2 3

Q7251

5

4

1 2 3

C7260

1

23

R7260

1 2

C7273

1

2

U7200

30

17

5

11

10

6

32

28

21

3

20

31

19

22

1

9

2

33

18

16

7

23 24 25 26 27

14

12

29

8

15

13

4

59

8

59

9

7

8

9

87

GND

THRML_PAD

SKIPSEL TONSEL

V5FILT

VIN

VREG5

VREG3

VREF2

EN5 EN3

VBST2

DRVH2

LL2

CS2

DRVL2

VO2

PGND2

COMP2

VFB2

PGOOD2

EN2

DRVH1

LL1

DRVL1

CS1

VO1

PGND1

VFB1 COMP1

PGOOD1

EN1

VBST1

SYM (3 OF 3)

IN

OUT OUT

IN

S

D

G

S

D

G

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

8A max output

5V Fixed

3.3V Fixed

Vout = 5.0V

(L7320 limit)

5.5A max output

When both are low TPS51120 VIN current drops from 100-150uA to 10-20uA.

NOTE: EN5 can float or tie to VIN for automatic 5V LDO enable EN3 can float or tie to VREG5 for automatic 3.3V LDO enable

(L7360 limit)

Vout = 3.3V

(Available for system use)

TPS51120 LDO/Buffer outputs

50uA max load when EN5 & EN3 high

100mA max load when EN5 high

10% X5R

603

25V

1UF

CRITICAL

IHLP

4.7UH

25V

10% X5R

603

1UF

X7R

603-1

10%

0.1UF

50V

X5R 603

10UF

6.3V

20%

0.1UF

X7R 603-1

10% 50V

D3L

330UF

20%

CRITICAL

POLY

6.3V

805-2

10UF

10V

CERM

20%

805-2

10UF

10V

20% CERM

SM

6.3V

150UF

CASE-B2

CRITICAL

POLY

20%

POLY

20% 25V

22UF

CASE-D2-LF

CRITICAL

10% X5R

603

1UF

25V

CRITICAL

20%

POLY

22UF

25V

CASE-D2-LF

2.2UH-14A

IHLP2525CZ-SM

CRITICAL

LLP

TPS51120

4.22K

1/16W 402

MF-LF

1%

3.57K

MF-LF

402

1/16W

1%

6.3V

20%

10UF

X5R 603

10UF

20%

6.3V X5R 603

1/16W 402

4.7

5% MF-LF

402

10% 10V X5R

1UF

65

46

65

402

CERM

50V

20%

0.001UF

CRITICAL

PWRPK-1212-8

SI7114DN

CRITICAL

PWRPK-1212-8

SI7108DNS

PWRPK-1212-8

CRITICAL

SI7114DN

CRITICAL

SI7108DNS

PWRPK-1212-8

PLACEMENT_NOTE=Place XW7360 next to C7390.

SM

PLACEMENT_NOTE=Place XW7320 next to C7350.

SM

SM SM

5V / 3.3V Power Supply

SYNC_DATE=03/19/2007

SYNC_MASTER=M76_MLB

051-7225

A.0.0

8860

MIN_NECK_WIDTH=0.2 mm

GND_P5VP3V3_SGND

MIN_LINE_WIDTH=0.6 mm VOLTAGE=0V

=P5VS5_EN =P5VS5_PGOOD =P3V3S5_PGOOD

=P5VP3V3_EN3 =P5VP3V3_EN5

=P3V3S5_EN

GND_P3V3S5_PGND

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

VOLTAGE=0V

MIN_NECK_WIDTH=0.20 mm

PP5V_S5_P5VP3V3_LDO

VOLTAGE=5V

MIN_LINE_WIDTH=0.25 mm

=PPVIN_S5_P3V3S5

P3V3S5_LL

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

P3V3S5_DRVL

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

P3V3S5_DRVH

MIN_LINE_WIDTH=0.6 mmGATE_NODE=TRUE MIN_NECK_WIDTH=0.2 mm

=PPVIN_S5_P5VP3V3

P3V3S5_CS

=PP5V_S5_REG

=PP3V3_S5_REG

P3V3S5_VO

P5VS5_DRVL

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUE

GND_P5VS5_PGND

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V

P5VS5_VO

P5VS5_DRVH

GATE_NODE=TRUEMIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP5V_S5_P5VP3V3_V5FILT

VOLTAGE=5V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

P3V3S5_VBST

P5VP3V3_VREG3

PP2V0_S5_P5VP3V3_BUF

VOLTAGE=2V

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.20 mm

P5VS5_CS

SWITCH_NODE=TRUE

P5VS5_LL

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

=PPVIN_S5_P5VS5

P5VS5_VBST

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

C7300

1

2

L7360

1 2

C7341

1

2

C7364

1

2

C7390

1

2

C7324

1

2

C7352

1

2

C7350

1

2

C7351

1

2

XW7300

1 2

C7392

1

2

C7340

1

2

C7381

1

2

C7380

1

2

L7320

1 2

U7300

2 7

23 18

27

14

25 16

29 12

10

9

5

26 15

24 17

30 11

32

33

31

20

28 13

3 6

22

1 8

4

19

21

R7325

1

2

R7365

1

2

C7303

1

2

C7305

1

2

R7306

1

2

C7306

1

2

C7302

1

2

Q7360

5

4

1 2 3

Q7365

5

4

1 2 3

Q7320

5

4

123

Q7325

5

4

123

XW7360

1

2

XW7320

1

2

XW7325

1 2

XW7365

1 2

8

8 8

8

OUT

IN

THRM_PAD

VFB

TRIP

VOUT

EN_PSV

GND

PGND

V5DRV

V5FILT

DRVL

DRVH

LL

TON

VBST

PGOOD

SYM (2 OF 2)

S

D

G

OUT

IN

THRM_PAD

VFB

TRIP

VOUT

EN_PSV

GND

PGND

V5DRV

V5FILT

DRVL

DRVH

LL

TON

VBST

PGOOD

SYM (2 OF 2)

S

D

G

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

<Ra>

Vout = 0.75V * (1 + Ra / Rb)

(P1V25ENET_VFB)

Vout = 1.051V 10A max output (L7460? limit)

8A max output

<Rb>

Vout = 0.75V * (1 + Ra / Rb)

<Rb>

(L7410? limit)

(GND)

(P1V25ENET_TON)

Vout = 1.2496V

(P1V05S0_VFB)

<Ra>

(P1V05S0_TON)

1% MF-LF

402

1/16W

6.81K

65

402

1/16W

1%

MF-LF

200

SM

TPS51117RGY_QFN14

CRITICAL

QFN

16V

2.2UF

10%

603

X5R

0

5%

1/16W

402

MF-LF

1UF

10V

10% X5R

402

SI7108DNS

CRITICAL

PWRPK-1212-8

20%

402

CERM

0.1UF

10V

SI7114DN

PWRPK-1212-8

CRITICAL

IHLP2525CZ-SM

CRITICAL

2.2UH-14A

200K

1%

402

MF-LF

1/16W

CRITICAL

POLY

20% 25V

22UF

CASE-D2-LF

603

10%

1UF

25V X5R

12.1K

1% 1/16W MF-LF

402

1/16W

8.06K

1% MF-LF

402

50V

100PF

NO STUFF

CERM 402

5%

PLACEMENT_NOTE=Place XW7430 close to C7415.

SM

X5R 603

10UF

20%

6.3V

5.62K

MF-LF

1%

402

1/16W

65

402

1/16W MF-LF

1%

200

SM

CRITICAL

QFN

TPS51117RGY_QFN14

X5R 603

10%

2.2UF

16V

0

5%

1/16W

402

MF-LF

10% 10V X5R 402

1UF

CRITICAL

SI7108DNS

PWRPK-1212-8

20%

402

CERM

0.1UF

10V

CRITICAL

SI7114DN

PWRPK-1212-8

1.0UH-22A

CRITICAL

IHLP2525CZ-SM

402

200K

1% MF-LF

1/16W

CRITICAL

POLY

20% 25V

22UF

CASE-D2-LF

10%

603

1UF

25V X5R

14.0K

1% 1/16W MF-LF

402

5.62K

1/16W

1%

402

MF-LF

CERM 402

50V

5%

NO STUFF 100PF

PLACEMENT_NOTE=Place XW7480 close to C7465.

SM

10UF

6.3V 603

20% X5R

CRITICAL

2.0V

330UF

20%

CASE-B2

POLY

2.0V

330UF

D2T

TANT

CRITICAL

10%

SM

88

SYNC_DATE=03/12/2007

61

A.0.0

051-7225

SYNC_MASTER=M76_MLB

1.25V / 1.05V Power Supply

P1V05S0_TRIP

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V

GND_P1V05S0_SGND

=PP1V05_S0_REG P1V05S0_VFB

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V

GND_P1V25ENET_SGND

P1V25ENET_VFB

P1V05S0_BOOT_R

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm

=PP1V05_S0_REG

=PP5V_S5_P1V25ENET

PP5V_S5_P1V25ENET_V5FILT

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V

P1V25ENET_TRIP

=PP5V_S5_P1V05S0

=P1V05S0_PGOOD

MIN_LINE_WIDTH=0.25 mm

P1V05S0_VBST

MIN_NECK_WIDTH=0.2 mm

P1V05S0_TON

P1V05S0_DRVH

MIN_LINE_WIDTH=0.6 mmGATE_NODE=TRUE MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

P1V25ENET_LL

MIN_NECK_WIDTH=0.2 mm

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.6 mmGATE_NODE=TRUE

P1V25ENET_DRVL

MIN_NECK_WIDTH=0.2 mm

=PPVIN_ENET_P1V25ENET

=PPVIN_S0_P1V05S0

=P1V25ENET_EN =P1V25ENET_PGOOD

MIN_LINE_WIDTH=0.6 mm

P1V25ENET_PGND

VOLTAGE=0V

MIN_NECK_WIDTH=0.2 mm

P1V05S0_PGND

MIN_LINE_WIDTH=0.6 mm VOLTAGE=0V

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=5V

PP5V_S5_P1V05S0_V5FILT

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

P1V05S0_LL

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

PP1V05_S0_VDDQSNS

P1V05S0_DRVL

MIN_LINE_WIDTH=0.6 mmGATE_NODE=TRUE MIN_NECK_WIDTH=0.2 mm

=P1V05S0_EN

PP1V25_ENET_VDDQSNS

=PP1V25_ENET_REG

P1V25ENET_BOOT_R

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

P1V25ENET_DRVH

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

GATE_NODE=TRUE

MIN_LINE_WIDTH=0.25 mm

P1V25ENET_VBST

MIN_NECK_WIDTH=0.2 mm

P1V25ENET_TON

R7405

1

2

R7401

1 2

XW7400

1

2

U7400

13

9

1

7

12

8

6

15

2

11

10

4

14

5

3

C7401

1

2

R7420

1

2

C7400

1

2

Q7411

5

4

1 2 3

C7420

1

2

Q7410

5

4

1 2 3

L7410

1 2

R7421

1

2

C7440

1

2

C7445

1

2

R7431

1

2

R7430

1

2

C7430

1

2

XW7430

1

2

C7415

1

2

R7455

1

2

R7451

1 2

XW7450

1

2

U7450

13

9

1

7

12

8

6

15

2

11

10

4

14

5

3

C7451

1

2

R7470

1

2

C7450

1

2

Q7461

5

4

1 2 3

C7470

1

2

Q7460

5

4

1 2 3

L7460

1 2

R7471

1

2

C7490

1

2

C7495

1

2

R7481

1

2

R7480

1

2

C7480

1

2

XW7480

1

2

C7465

1

2

C7410

C7460

1

23

XW7401

1

2

XW7451

1

2

61

8

MODE

VDDQSNS

COMP

NC0 NC1

VTTSNS

VTT

VTTREF

PGOOD

S3 S5

VTTGND

THRM_PAD

GND

CS_GND

PGND

CS

LL

DRVL

DRVH

VDDQSET

VBST

VLDOINV5FILT

V5IN

SYM (2 OF 2)

IN IN

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

VDDQ PGOOD

Vout = 1.80V or 1.825V 18A max output (L7530 limit)

Place at pin 23

VDDQ/VTTREF Enable

Vout = VTTREF

(P1V8S3_LL)

(P1V8S3_VDDQSNS)

Place next to

VTT Enable

NC NC

10mA max load Vout = VDDQSNS/2

C7545

(P1V8S3_FB)

<Rb>

<Ra>

Vout = 0.75V * (1 + Ra / Rb)

(P1V8S3_CSGND)

(P1V8S3_DRVL)

(P1V8S3_DRVH)

0.1UF

X7R-CERM

805

10% 50V

P1V8S3_1V825

0.1%

21.5K

1/16W 402

MF-LF

0.1% MF-LF

1/16W

15.0K

402

330UF

CASE-C2

2.5V POLY

20%

CRITICAL

20%

CASE-C2

POLY

2.5V

330UF

CRITICAL

25V X5R

1UF

603

10%

100PF

5%

CERM

50V 402

NO STUFF

CRITICAL

QFN

TPS51116

402

1UF

10V

10% X5R

1/16W

4.7

5%

MF-LF

402

CRITICAL

20%

6.3V

22UF

CERM-X5R

805-3

CRITICAL

20%

6.3V

22UF

CERM-X5R 805-3

SM

16V X5R 402

10%

0.033UF

65

805-2

10UF

CERM

20% 10V

65

MF-LF

402

1%

1/16W

6.81K

65

POLY

CASE-D2-LF

20% 25V

22UF

CRITICAL

25V

CASE-D2-LF

POLY

22UF

20%

CRITICAL

RJK0305DPB

LFPAK

CRITICAL

RJK0303DPB

LFPAK

CRITICAL

1.0UH-20A

CRITICAL

IHLP4040DZ11-SM

X5R 603

20%

10UF

6.3V

LFPAK

RJK0303DPB

CRITICAL

SM

10UF

20%

603

X5R

6.3V

SM

MF-LF

5%

603

1/10W

1

R7520

1

CRITICAL P1V8S3_1V8103S0192

RES,MTL FILM,21K,0.1,0402,SM,LF

SYNC_MASTER=M76_MLB

1.8V DDR2 Supply

051-7225

62 88

A.0.0

SYNC_DATE=03/19/2007

P1V8S3_VBST

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

SWITCH_NODE=TRUE

P1V8S3_LL

VOLTAGE=5V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP5V_S5_P1V8DDRREG_V5FILT

P1V8S3_CSGND

P1V8S3_FB

GATE_NODE=TRUE

P1V8S3_DRVH

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

GATE_NODE=TRUE

P1V8S3_DRVL

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

VOLTAGE=1.8V

P1V8S3_VDDQSNS

VOLTAGE=0V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

GND_P1V8DDRREG_SGND

=PP1V8_S3_REG

DDRREG_VTTSNS

=PP1V8_S3_REG

P1V8S3_CS

=PP0V9_S0_VTT_LDO

=P1V8S3_PGOOD

=P1V8S3_EN

=P0V9S0_EN

=PPVIN_S3_P1V8S3

GATE_NODE=TRUE MIN_LINE_WIDTH=0.6 mm

P1V8S3_DRVH_R

MIN_NECK_WIDTH=0.2 mm

=PP0V9_S3_VTTR_BUF

=PP5V_S5_P1V8DDRREG

C7525

R7520

1

2

R7521

1

2

C7540

1

2

C7541

1

2

C7532

1

2

C7520

1

2

U7500

6

16

17

21

19

3

20

4

7

12

18

13

10 11

25

14

15

22

9

8

23

24

1

5

2

C7505

1

2

R7505

1 2

C7561

1

2

C7560

1

2

XW7560

1 2

XW7535

1 2

C7550

1

2

C7500

1

2

R7510

1

2

C7530

1

2

C7531

1

2

Q7530

5

4

1 2 3

Q7535

5

4

1 2 3

L7530

1 2

C7545

1

2

Q7536

5

4

1 2 3

XW7545

1

2

C7501

1

2

XW7500

1

2

R7526

1 2

62

62 8 8

8

IN

OUT

THRM_PAD

VFB

TRIP

VOUT

EN_PSV

GND

PGND

V5DRV

V5FILT

DRVL

DRVH

LL

TON

VBST

PGOOD

SYM (2 OF 2)

S

D

G

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

<Ra>

<Rb>

(P1V5S0_VFB)

Vout = 0.75V * (1 + Ra / Rb)

(P1V5S0_TON)

(GND)

(L7620 limit)

8A max output

Vout = 1.50V

NO STUFF

100PF

50V 402

5% CERM

1/16W MF-LF

402

5%

0

10V

0.1UF

CERM

402

20%

CASE-D2-LF

22UF

25V

20%

POLY

CRITICAL

2.5V

330UF

CASE-D2E-LF

20% POLY

65

10% 10V

1UF

X5R 402

200

1/16W MF-LF

402

1%

16V

2.2UF

10% 603

X5R

1/16W MF-LF 402

1%

200K

QFN

TPS51117RGY_QFN14

CRITICAL

X5R

25V

1UF

10%

603

PWRPK-1212-8

SI7114DN

CRITICAL

SI7108DNS

PWRPK-1212-8

CRITICAL

SM

PLACEMENT_NOTE=Place XW7620 close to L7620.

SM

6.04K

MF-LF

1%

402

1/16W

603

X5R

10UF

20%

6.3V

1/16W

1%

10K

402

MF-LF

1/16W MF-LF

402

10K

1%

1.0UH-22A

IHLP2525CZ-SM

CRITICAL

A.0.0

051-7225

63 88

SYNC_MASTER=M76_MLB

SYNC_DATE=03/12/2007

1.5V Power Supply

PP1V5_S0_VDDQSNS

=PP1V5_S0_REG

P1V5S0_TRIP

=PP1V5_S0_REG

VOLTAGE=0V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

GND_P1V5S0_SGND

VOLTAGE=5V

MIN_LINE_WIDTH=0.6 mm

PP5V_S5_P1V5S0_V5FILT

MIN_NECK_WIDTH=0.2 mm

=P1V5S0_PGOOD

=PPVIN_S0_P1V5S0

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

SWITCH_NODE=TRUE

P1V5S0_LL

=P1V5S0_EN

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm

P1V5S0_BOOT_R

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mmGATE_NODE=TRUE

P1V5S0_DRVH

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.25 mm

P1V5S0_VBST

P1V5S0_TON

=PP5V_S5_P1V5S0

P1V5S0_VFB

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

P1V5S0_DRVL

C7630

1

2

R7610

1

2

R7611

1

2

C7601

1

2

R7605

1

2

L7620

1 2

C7610

1

2

R7615

1

2

C7615

1

2

C7620

1

2

C7632

1

2

C7600

1

2

R7601

1 2

R7619

1

2

U7600

13

9

1

7

12

8

6

15

2

11

10

4

14

5

3

C7621

1

2

Q7620

5

4

1 2 3

Q7625

5

4

1 2 3

XW7620

1

2

XW7600

1 2

63

63 8 8

8

OUT

IN

NR

NC

THRML

EN

GND

PAD

FB

BIAS

SW

SHDN*

NC

VIN

BOOST

GND

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(Switcher limit)

<Ra>

NC

<Rb>

Vout = 3.316V

Vout = 1.25V * (1 + Ra / Rb)

3.3V FW PHY Supply

NC

Backup power in case of FW bus VP short to keep PHY powered.

1.95V FW PHY Supply

200mA max output

2.2uF

X5R 402

20% 4V

0.01uF

CERM

402

10% 16V

1uF

CERM

402

10%

6.3V

CRITICAL

TPS799195

SON

324K

1% 1/16W MF-LF 402

196K

MF-LF 402

1% 1/16W

22pF

CERM

402

5%

50V

0.22uF

6.3V X5R

20%

402

4.7UF

1206

10%

X7R-CERM

50V

LT3470

TSOT23-8

CRITICAL

SC-59

SMD20E40C-X-F

CRITICAL

CDPH4D19F-SM

33uH

805-3

CERM-X5R

22UF

20%

6.3V

CRITICAL

64 88

A.0.0

051-7225

SYNC_DATE=03/19/2007

FW PHY Power Supplies

SYNC_MASTER=M76_MLB

=PP1V95_FW_LDO

P1V95FW_NR

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE

P3V3FW_SW

PPVIN_FW_P3V3FW

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

VOLTAGE=33V

=PPVP_FW_P3V3FW

=PPVIN_FW_P1V95FW

=PPBU_S0_P3V3FW

P3V3FW_BOOST

P3V3FW_FB

=PP3V3_FW_REG

C7722

1

2

C7721

1

2

C7720

1

2

U7720

4

3

6

5

2

1

7

R7710

1

2

R7711

1

2

C7710

1

2

C7705

1

2

C7700

1

2

U7700

7

6

8

4

2

1 5

3

D7700

1

2

3

L7700

1 2

C7701

1

2

8

FB

BIAS

SW

SHDN*

NC

VIN

BOOST

GND

OUT OUT OUT

OUT

OUT OUT

OUT

OUT OUT

OUT

OUT OUT

OUT

OUT OUT

OUT

IN

OUT

OUT OUT

IN

OUT

VPG

V2

V4

V3

VREF RST*

CRT

THRM_PAD

GND

PBR*

V1

OUT OUT

G

D

S

OUT

G

D

S

Y

B

A

Y

B

A

IN

G

D

S

OUT

G

D

S

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Power Control Signals

Other S0 Rails PWRGD Circuit

NOTE: 0.9V/2.5V is not checked!

(PM_S4_STATE_L)

Need to ensure that

first via RC control

before 99ms SMC timer expires.

not be necessary to stuff if GPU

200mA max output (Switcher limit)

LTC2900 typical threshold is 93.5% (4.675V, 3.086V, 1.685V, 1.120V)

PP1V2_GPU needs to ramp

Fast wake glitch filter. Should

TPS51117 PGOOD threshold 92.5-97.5% (0.98 - 1.02V)

TPS51117 PGOOD threshold 92.5-97.5% (1.36 - 1.46V)

G84M GPU requires rails to come

1) 1.2V

Trst = 216ms

Trst = 4.6ms/nF

NC

Does not include GFX rails

3.425V "G3Hot" Supply

<Ra>

Unused PGOOD Signals

Vout = 1.25V * (1 + Ra / Rb)

NC

<Rb>

Vout = 3.425

1 0 0 0

1 1

0

1

1 0

Battery Off (G3Hot)

Sleep (S3) Soft-Off (S5)

State

Supply needs to guarantee 3.31V delivered to SMC VRef generator

Run (S0)

SMC_PM_G2_ENABLE

PM_SLP_S4_L PM_SLP_S3_L

1.5V / 1.05V PWRGD Circuit

Reports when 1.5V S0 and 1.05V S0 are in regulation

To CPU IMVP6

GPU core voltage.

supplies and PGOOD revalidate

R7853 acts as pull-up for open-drain GPIO.

(EXTGPU_PWR_EN)

4) 1.8V

3) Vcore

2) 3.3V

up in the following order:

(PM_SLP_S3_L)

SB GPIO has ability to force all GPU rails off

VIDs are changing

deassert while GPU

TPS51117 PGOOD does not

(PM_ENET_EN)

LT3470

TSOT23-8

CRITICAL

25V

10%

1206-1

X5R

10UF

805-3

CERM-X5R

22UF

20%

6.3V

1/16W

1%

402

MF-LF

200K

1/16W MF-LF

5%

402

100K

57

57 61

35

62

49

63

34

57

62

MC74VHC1G08

SC70

43

34

60

57

0.1UF

CERM 402

20% 10V

7

36

23 28

49 58

CERM 402

10% 16V

0.047UF

NO STUFF

61

60

63

60

ISL9504A

0

1/16W

5%

402

MF-LF

10V

20%

CERM

402

0.1UF

93.1K

MF-LF 402

1/16W

1%

9.53K

1/16W 402

MF-LF

1%

LTC2900

DFN

CRITICAL

16V

0.047UF

10% 402

CERM

MF-LF

1% 1/16W

100K

402

MF-LF 402

1% 1/16W

124K

402

CERM

10V

20%

0.1UF 10K

5%

402

MF-LF

1/16W

0.1UF

20% 402

10V

CERM

402

CERM

20% 10V

0.1uF

57

SOT-363

2N7002DW-X-F

72 74

2N7002DW-X-F

SOT-363

MF-LF

1/16W

5%

402

100K

MF-LF

1/16W

5%

402

10K

SC70

MC74VHC1G09

5%

402

1/16W MF-LF

10K

1/16W MF-LF

5%

402

CERM-X5R 402

10%

0.47UF

6.3V

NO STUFF

CERM

402

10% 16V

0.047UF

SC70

MC74VHC1G09

NO STUFF

0

402

5%

MF-LF

1/16W

61

100K

402

1/16W MF-LF

5%

10K

1/16W

5%

MF-LF

402

2N7002DW-X-F

SOT-363

28 45 46

1/16W

1%

402

MF-LF

348K

CDPH4D19F-SM

33uH

CRITICAL

SOT-363

2N7002DW-X-F

74

50V

5%

402

CERM

22pF

1/16W

402

5%

MF-LF

100K

7

25 36 40 45

1/16W

5%

402

MF-LF

10K

7

25 45

5%

1/16W

402

MF-LF

100K

45

6.3V

20%

402

X5R

0.22uF

10K

MF-LF

402

5%

1/16W

3.425V G3Hot Supply & Power Control

051-7225

8865

A.0.0

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

=P5VP3V3_EN3

=P5VP3V3_EN5

=P5VS5_EN =P3V3S5_EN

S0PGOOD_PWROK

=PP3V42_G3H_REG

MAKE_BASE=TRUE

EXTGPU_PWR_EN

MAKE_BASE=TRUE

PM_S4_STATE_L

P1V8S3_EN

MAKE_BASE=TRUE

LIO_S3_EN

=USB_EXTA_EN

=P1V8S3_EN

MAKE_BASE=TRUE

PM_ENET_EN

MAKE_BASE=TRUE

PM_SLP_S3_L

=P1V8S0_EN

LIO_S0_EN_L

=PP3V3_S0_PWRCTL

=P5VS0_EN =P3V3S0_EN

=PP5V_S5_PWRCTL

=GPUVCORE_PGOOD

=ENET_VMAIN_AVLBL

=P1V25S0_EN

=PBUSVSENS_EN

=P1V05S0_EN

=P1V5S0_EN

=PP3V3_GPU_PWRCTL

PVCOREGPU_EN_L

MAKE_BASE=TRUE

PM_GPUP1V8FET_EN

=P1V8GPU_EN

PM_GPUVCORE_EN

MAKE_BASE=TRUE

=GPUVCORE_EN

S0PGOOD_P1V2_DIV

S0PGOOD_VREF

PP3V3_S0

=PP3V3_S0_ALLSYSPG

=PP3V3_S5_P1V5P1V05PG

=P5VS3_EN

=PPVIN_G3H_P3V42G3H

P3V42G3H5_BOOST

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

P3V42G3H_SW

P3V42G3H_FB

=P1V25ENET_PGOOD

=P3V3S3_EN

=P1V8S3_PGOOD

=P3V3ENET_EN

ALL_SYS_PWRGD

MAKE_BASE=TRUE

TP_P1V25ENET_PGOOD TP_P1V8S3_PGOOD

MAKE_BASE=TRUE

PP1V25_S0

PP5V_S0

S0PGOOD_VPG

S0PGOOD_CRT

IMVP6_IMON

P1V5P1V05S0_PGOOD

MAKE_BASE=TRUE

=P1V5S0_PGOOD

=P1V05S0_PGOOD

=P1V25GPU_EN

=P0V9S0_EN

PP1V8_S0

=PVCOREGPU_EN =P3V3GPU_EN

=P1V25ENET_EN

=PM_SLP_S3_DELAY_L

=PP3V3_S5_PWRCTL

PM_SLP_S3_DELAY_L

MAKE_BASE=TRUE

PM_SLP_S3_LS5V

MAKE_BASE=TRUE

PM_G2_EN

MAKE_BASE=TRUE

SMC_PM_G2_EN

=PP3V42_G3H_PWRCTL

R7810

1

2

L7810

1 2

C7810

1

2

C7805

1

2

U7800

7

6

8

4

2

1 5

3

C7800

1

2

C7815

1

2

R7811

1

2

R7865

1

2

U7880

3

2

1

4

5

C7880

1

2

R7851

1

2

R7850

1

2

Q7850

6

2

1

Q7850

3

5

4

R7856

1

2

R7857

1

2

R7858

1

2

R7853

1

2

C7853

1

2

R7866

1

2

C7873

1

2

R7871

1

2

R7870

1

2

U7870

3

6

5

4

11

2

10

1

9

7

8

C7875

1

2

R7874

1

2

R7873

1

2

C7872

12

R7875

1

2

C7871

1

2

C7870

1

2

Q7851

3

5

4

Q7851

6

2

1

R7852

1

2

R7854

1

2

U7850

3

2

1

4

5

R7859

1

2

R7855

1 2

C7855

1

2

C7859

1

2

U7858

3

2

1

4

5

R7860

12

87

8

8 8

8

61

62

8

7

8

OUT

PEX_TX0

PEX_TX0_L

PEX_RX4

PEX_RX0

PEX_TX1PEX_RX1

PEX_RX2 PEX_TX2

PEX_RX3 PEX_TX3

PEX_TX4

PEX_TX5PEX_RX5

PEX_TX6PEX_RX6

PEX_RX7 PEX_TX7

PEX_TX8PEX_RX8

PEX_TX9PEX_RX9

PEX_TX10PEX_RX10

PEX_TX11PEX_RX11

PEX_TX12PEX_RX12

PEX_TX13PEX_RX13

PEX_TX14PEX_RX14

PEX_TX15PEX_RX15

PEX_TSTCLK_OUT

PEX_REFCLK

PEX_TX1_L

PEX_TX2_L

PEX_TX3_L

PEX_TX4_L

PEX_TX5_L

PEX_TX6_L

PEX_TX7_L

PEX_TX8_L

PEX_TX9_L

PEX_TX10_L

PEX_TX11_L

PEX_TX12_L

PEX_TX13_L

PEX_TX14_L

PEX_TX15_L

PEX_TSTCLK_OUT_L

PEX_RST_L

PEX_REFCLK_L

PEX_RX15_L

PEX_RX14_L

PEX_RX13_L

PEX_RX12_L

PEX_RX11_L

PEX_RX10_L

PEX_RX9_L

PEX_RX8_L

PEX_RX7_L

PEX_RX6_L

PEX_RX5_L

PEX_RX4_L

PEX_RX3_L

PEX_RX2_L

PEX_RX1_L

PEX_RX0_L

PCI-EXPRESS BUS INTERFACE

NC

PEX_IOVDD_1 PEX_IOVDD_2 PEX_IOVDD_3 PEX_IOVDD_4 PEX_IOVDD_5 PEX_IOVDD_6

PEX_IOVDDQ_1 PEX_IOVDDQ_2 PEX_IOVDDQ_3 PEX_IOVDDQ_4 PEX_IOVDDQ_5 PEX_IOVDDQ_6 PEX_IOVDDQ_7 PEX_IOVDDQ_8

PEX_IOVDDQ_9 PEX_IOVDDQ_10 PEX_IOVDDQ_11

PEX_PLLAVDD PEX_PLLDVDD

PEX_PLLGND

IN

IN IN

IN

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

- =PP1V2_GPU_PEX_PLLXVDD

- =PP1V2_GPU_PEX_IOVDD Signal aliases required by this page:

1500mA

20mA

180mA

(NONE)

Page Notes

250mA

PEX 1.2V Current = 2A

BOM options provided by this page:

- =PP1V2_GPU_PEX_IOVDDQ

Power aliases required by this page:

15 80

10% 16V

0.1uF

402X5R

40210% 16V X5R

0.1uF

15 80

X5R10% 16V 402

0.1uF

10% 16V X5R

0.1uF

402

15 80

10% 16V X5R

0.1uF

402

0.1uF

10% 16V X5R 402

15 80

10% 16V X5R

0.1uF

402

10% 16V X5R

0.1uF

402

15 80

10% 16V X5R

0.1uF

402

10% 16V X5R

0.1uF

402

15 80

0.1uF

X5R16V10% 402

15 80

10% 16V X5R

0.1uF

402

10% 16V X5R

0.1uF

402

15 80

10% 16V X5R

0.1uF

402

10% 16V X5R

0.1uF

402

15 80

10% 16V X5R

0.1uF

402

402X5R16V

0.1uF

10%

10% 16V X5R

0.1uF

402

15 80

10% 16V X5R

0.1uF

402

10% 16V X5R

0.1uF

402

15 80

10% 16V X5R

0.1uF

402

10% 16V X5R

0.1uF

402

15 80

402

0.1uF

X5R16V10%

15 80

10% 16V X5R

0.1uF

402

10% 16V X5R 402

0.1uF

15 80

10% 16V X5R

0.1uF

402

10% 16V X5R

0.1uF

402

15 80

10% 16V X5R

0.1uF

402

0.1uF

402X5R16V10%

10% 16V X5R 402

0.1uF

402

0.1uF

X5R16V10%

402

0.1uF

X5R16V10%

402

0.1uF

10% X5R16V

OMIT

(1 OF 8)

BGA

NB8P-GS-W-A2

OMIT

(2 OF 8)

BGA

NB8P-GS-W-A2

CERM

4.7UF

603

20%

6.3V

CERM 402

1UF

10%

6.3V 402

CERM

20%

0.1UF

10V

0.1uF

X5R16V10% 402

20% CERM

402

0.1UF

10V

CERM

4.7UF

20%

6.3V 603 603

6.3V

20%

4.7UF

CERM

20%

805

6.3V

22UF

CERM-X5R

0.1uF

402X5R16V10%

1UF

6.3V

10%

402

CERM

22UF

6.3V 805

20% CERM-X5R

CERM

6.3V

20%

603

4.7UF

CERM

10%

6.3V

1UF

402

6.3V

10%

1UF

402

CERM

10V

0.1UF

20% CERM

402

CERM

20% 10V

0.1UF

402

0.1UF

20% 10V

402

CERM

16V 402

0.1uF

X5R10%

603

6.3V

20%

4.7UF

CERMCERM

402

10V

20%

0.1UF

603

6.3V

20%

4.7UF

CERM

10NH-600MA

0603

10NH-600MA

0603

402

0.1uF

X5R16V10%

402

0.1uF

X5R16V10%

402

0.1uF

X5R16V10%

402

0.1uF

X5R16V10%

402

0.1uF

X5R16V10%

0.1uF

402X5R16V10%

402

0.1uF

X5R16V10%

402

0.1uF

X5R16V10%

402

0.1uF

X5R16V10%

402

0.1uF

X5R16V10%

402

0.1uF

X5R16V10%

16V 402

0.1uF

X5R10%

402

0.1uF

X5R16V10%

0.1uF

402X5R16V10%

402

0.1uF

X5R16V10%

402

0.1uF

X5R16V10%

402

0.1uF

X5R16V10%

402

0.1uF

X5R16V10%

10% 402

0.1uF

X5R16V

402

0.1uF

X5R16V10%

16V 402X5R10%

0.1uF

402

0.1uF

X5R16V10%

15 80

9

30

9

30

7

28

402

0.1uF

X5R16V10%

402

0.1uF

X5R16V10%

15 80

10% 16V X5R

0.1uF

402

0.1uF

10% 16V X5R 402

15 80

10% 16V X5R

0.1uF

402

10% 16V X5R

0.1uF

402

15 80

NV G84M PCI-E

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

66 88

A.0.0

051-7225

=PP1V2_GPU_PEX_IOVDD

=PP1V2_GPU_PEX_IOVDDQ

PP1V2_GPU_PEX_PLLAVDD_F

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.2V

MIN_LINE_WIDTH=0.25 mm VOLTAGE=1.2V

MIN_NECK_WIDTH=0.25 mm

PP1V2_GPU_PEX_PLLDVDD_F

PEG_R2D_N<10>

PEG_R2D_P<11> PEG_R2D_N<11>

PEG_D2R_C_P<13>

PEG_R2D_C_N<11>

PEG_R2D_N<13>

PEG_D2R_C_N<13>

PEG_R2D_C_P<12>

PEG_R2D_C_N<12>

PEG_CLK100M_GPU_N

TP_GPU_PEXTSTCLK_P

PEG_D2R_C_N<15>

PEG_D2R_C_P<15>

GPU_RESET_L

PEG_CLK100M_GPU_P

PEG_R2D_C_N<14>

PEG_R2D_C_P<15>

PEG_R2D_P<15>

PEG_R2D_C_N<13>

PEG_R2D_C_P<14>

PEG_R2D_C_P<13>

PEG_R2D_C_P<11>

PEG_R2D_C_P<10>

PEG_R2D_C_N<10>

PEG_R2D_C_P<9>

PEG_R2D_C_N<9>

PEG_R2D_C_P<8>

PEG_R2D_C_N<8>

PEG_R2D_C_N<7>

PEG_R2D_C_N<6>

PEG_R2D_C_N<5>

PEG_R2D_C_P<6>

PEG_R2D_P<14>

PEG_R2D_P<13>

PEG_R2D_P<12>

PEG_R2D_P<10>

PEG_R2D_P<9>

PEG_R2D_P<8>

PEG_R2D_P<7>

PEG_R2D_P<6>

PEG_R2D_C_N<4>

PEG_R2D_C_P<5>

PEG_R2D_C_N<3>

PEG_R2D_C_P<4>

PEG_R2D_C_P<3>

PEG_R2D_C_P<2>

PEG_R2D_C_N<2>

PEG_R2D_C_P<1>

PEG_R2D_C_N<1>

PEG_R2D_C_P<0>

PEG_R2D_C_N<0>

PEG_R2D_P<5>

PEG_R2D_P<4>

PEG_R2D_P<3>

PEG_R2D_P<2>

PEG_R2D_P<1>

PEG_R2D_P<0>

PEG_R2D_N<14>

PEG_R2D_N<15>

PEG_R2D_N<12>

PEG_R2D_N<5>

PEG_R2D_N<9>

PEG_R2D_N<8>

PEG_R2D_N<7>

PEG_R2D_N<4>

PEG_R2D_N<1>

PEG_R2D_N<2>

PEG_R2D_N<3>

PEG_R2D_N<0>

PEG_D2R_C_N<14>

PEG_D2R_C_N<12>

PEG_D2R_C_N<10>

PEG_D2R_C_N<9>

PEG_D2R_C_N<7>

PEG_D2R_C_N<6>

PEG_D2R_C_N<5>

PEG_D2R_C_N<4>

PEG_D2R_C_N<3>

PEG_D2R_C_N<2>

PEG_D2R_C_N<1>

PEG_D2R_C_P<12>

PEG_D2R_C_P<11>

PEG_D2R_C_P<10>

PEG_D2R_C_P<9>

PEG_D2R_C_P<8>

PEG_D2R_C_P<6>

PEG_D2R_C_P<5>

PEG_D2R_C_P<4>

PEG_D2R_C_P<3>

PEG_D2R_C_P<2>

PEG_D2R_C_P<1>

PEG_D2R_C_N<0>

PEG_D2R_C_P<0>

PEG_D2R_N<13>

PEG_D2R_N<15>

PEG_D2R_N<14>

PEG_D2R_P<15>

PEG_D2R_P<14>

PEG_D2R_P<12>

PEG_D2R_P<11>

PEG_D2R_N<11>

PEG_D2R_N<10>

PEG_D2R_N<9>

PEG_D2R_P<8>

PEG_D2R_N<7>

PEG_D2R_P<7>

PEG_D2R_P<6>

PEG_D2R_P<5>

PEG_D2R_P<4>

PEG_D2R_N<4>

PEG_D2R_P<3>

PEG_D2R_N<3>

PEG_D2R_P<2>

PEG_D2R_N<2>

PEG_D2R_P<1>

PEG_D2R_N<0>

PEG_D2R_P<0>

PEG_D2R_N<12>

PEG_D2R_N<1>

PEG_D2R_C_P<7>

PEG_D2R_N<6>

PEG_D2R_P<13>

PEG_D2R_P<10>

PEG_D2R_P<9>

PEG_D2R_N<8>

PEG_D2R_C_P<14>

PEG_D2R_N<5>

PEG_D2R_C_N<11>

PEG_D2R_C_N<8>

PEG_R2D_N<6>

PEG_R2D_C_P<7>

PEG_R2D_C_N<15>

=PP1V2_GPU_PEX_PLLXVDD

TP_GPU_PEXTSTCLK_N

C8020

1 2

C8021

1 2

C8050

1 2

C8051

1 2

C8048

1 2

C8049

1 2

C8046

1 2

C8047

1 2

C8044

1 2

C8045

1 2

C8042

1 2

C8043

1 2

C8040

1 2

C8041

1 2

C8038

1 2

C8039

1 2

C8036

1 2

C8037

1 2

C8034

1 2

C8035

1 2

C8032

1 2

C8033

1 2

C8030

1 2

C8031

1 2

C8028

1 2

C8029

1 2

C8026

1 2

C8027

1 2

C8024

1 2

C8025

1 2

C8022

1 2

C8023

1 2

C8055

1 2

C8056

1 2

C8085

1 2

C8086

1 2

C8083

1 2

C8084

1 2

C8081

1 2

C8082

1 2

C8079

1 2

C8080

1 2

C8077

1 2

C8078

1 2

C8075

1 2

C8076

1 2

C8073

1 2

C8074

1 2

C8071

1 2

C8072

1 2

C8069

1 2

C8070

1 2

C8067

1 2

C8068

1 2

C8065

1 2

C8066

1 2

C8063

1 2

C8064

1 2

C8061

1 2

C8062

1 2

C8059

1 2

C8060

1 2

C8057

1 2

C8058

1 2

U8000

AH14 AJ14

AH15

AK13 AK14

AM14 AM15

AL23 AL24

AM24 AM25

AK25 AK26

AL26 AL27

AM27 AM28

AL28 AL29

AL15 AL16

AK16 AK17

AL17 AL18

AM18 AM19

AK19 AK20

AL20 AL21

AM21 AM22

AK22 AK23

AM12 AM11

AJ15 AK15

AH16 AG16

AG23 AH23

AK24 AJ24

AJ25 AH25

AH26 AG26

AK27 AJ27

AJ28 AH27

AG17 AH17

AG18 AH18

AK18 AJ18

AJ19 AH19

AG20 AH20

AG21 AH21

AK21 AJ21

AJ22 AH22

U8000

A26

M5 U6 V1 V3 V4 V5 V6 W1 W3 W4

A28

W5 Y5

Y6 AC26 AD26 AE26 AG12 AH13 AH31 AH32

B32

AM8 AM9

D1

D31 D32

F1

F6

G8

AD23 AF23 AF24 AF25 AG24 AG25

AC16

AF21 AF22

AC17 AC21 AC22 AE18 AE21 AE22 AF12 AF18

AF15 AE15 AE16

C8001

1

2

C8003

1

2

C8004

1

2

C8005

1

2

C8016

1

2

C8015

1

2

C8000

1

2

C8002

1

2

C8006

1

2

C8007

1

2

C8008

1

2

C8009

1

2

C8010

1

2

C8011

1

2

C8017

1

2

C8013

1

2

C8014

1

2

C8012

1

2

L8015

1 2

L8012

1 2

8

80

80 80

80

80 80

80

8

FBVTT

FBVDDQ

GND_SENSE

VDD_SENSE

VDD_LP

VDD

FBVDD

GND

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

???A @ ???/???MHz Core/Mem Clk for VDD

- =PPVCORE_GPU

- =PP1V8_GPU_FBVDDQ

(NONE) BOM options provided by this page:

(NONE)

Signal aliases required by this page:

Power aliases required by this page:

Page Notes

???A @ ???MHz 1.8V GDDR3

NC

NC NC NC NC

NC

CERM

6.3V

1UF

10%

402

CERM

6.3V

1UF

10%

402

OMIT

(7 OF 8)

BGA

NB8P-GS-W-A2

OMIT

BGA

(8 OF 8)

NB8P-GS-W-A2

CERM

6.3V

1UF

10%

402

0.1UF

20% 10V

402

CERM

20% CERM

402

0.1UF

10V

20% 10V

402

CERM

0.1UF

10V

0.1UF

20% CERM

402

10V

0.1UF

20%

402

CERM

20% 10V CERM

0.1UF

402

20%

402

CERM

0.1UF

10V

20% 10V CERM 402

0.1UF

20% 10V

402

CERM

0.1UF

10V

0.1UF

CERM 402

20%

20% 10V CERM 402

0.1UF

20% 10V

402

CERM

0.1UF

20% 10V CERM 402

0.1UF

20% 10V

402

CERM

0.1UF

10V CERM

0.1UF

20%

402

CERM-X5R

10%

6.3V

0.47UF

402

0.47UF

6.3V

10%

CERM-X5R

CERM

402

10V

20%

0.1UF

4.7UF

603

20%

6.3V CERM

CERM

402

10V

20%

0.1UF

CERM

402

0.1UF

20% 10V

CERM

402

0.1UF

20% 10V

4.7UF

603

20%

6.3V CERM

CERM

402

10V

20%

0.1UF

402

CERM

0.1UF

20% 10V

CERM

402

0.1UF

20% 10V

CERM

402

10V

20%

0.1UF

402

CERM

20%

10V CERM 402

20% 10V

0.1UF

402

CERM

20% 10V

0.1UF

402

CERM

10V

0.1UF

20%

CERM 402

20% 10V

0.1UF

402

CERM-X5R

10%

6.3V

0.47UF

402

0.47UF

6.3V

10%

CERM-X5R

10%

6.3V

0.47UF

402

CERM-X5R

10%

6.3V

0.47UF

402

CERM-X5R

10%

6.3V

0.47UF

402

CERM-X5R

10%

6.3V

0.47UF

402

SYNC_DATE=(MASTER)

A.0.0

051-7225

8867

NV G84M Core/FB Power

SYNC_MASTER=(MASTER)

TP_GPU_GND_SENSE

TP_GPU_VDD_SENSE

=PPVCORE_GPU

=PP1V8_GPU_FBVDDQ

C8101

1

2

C8100

1

2

U8000

A12

A9 AA32 AD32 AG32 AK32 C32 F32 J32 M32 R32

A18 A21 A24 A27 A3 A30 A6

AA25

G22 H11 H12 H15 H18 H21 H22 L25 L26 M25

AA26

M26 R25 R26 V25 V26

AB25 AB26 G11 G12 G15 G18 G21

AA23

K12 K21 K22 K24 K9 L23 M23 T25 U25

AB23 H16 H17 J10 J23 J24 J9 K11

M21

K16

P16 P17 P19 R16 R17 T13 T14 T15 T18 T19

K17

U13 U14 U15 U18 U19 V16 V17 W13 W14 W16

N13

W17 W19 Y13 Y14 Y16 Y17 Y19 Y20

N14 N16 N17 N19 P13 P14

P20 T20 T23 U20 U23 W20

N20

U8000

AE17

AG11

J16 J17 J2 J31 K10 K23 K29 K4 L27 L6

AB27

M12 M2 M31 N15 N18 N29 N4 P15 P18 P27

AB6

P6 R13 R14 R15 R18 R19 R2 R20 R31 T16

AC10

T17 T24 T29 T4 U16 U17 U24 U29 U8 V13

AC23

V14 V15 V18 V19 V2 V20 V31 W15 W18 W27

AC29

W6 Y15 Y18 Y29 Y4

AC4 AD16 AD17

AD2

AE27

AD31 AA12

AA2 AA21 AA31 AG13 AG14 AG15 AG19

AG2

AE6

AG22 AG31

AG8 AH24 AJ10 AJ13 AJ16 AJ17 AJ20 AJ23

AF11

AJ26 AJ29

AJ4

AJ7

AK2 AK28 AK31 AL10 AL11 AL14

AF26

AL19 AL22 AL25

AL3

AL6

AL9 AM10 AM13 AM16 AM17

AF29

AM20 AM23 AM26 AM29

B12

B15

B18

B21

B24

B27

AF4

B3

B30

B6 B9

C2 C31 D10 D13

D16 D17

AF7

D20 D23 D26 D29 D4 D7 F11 F14 F19 F2

AG10

F22 F25 F31 F8 G26 G29 G4 G7 H27 H6

C8102

1

2

C8107

1

2

C8112

1

2

C8117

1

2

C8106

1

2

C8105

1

2

C8110

1

2

C8111

1

2

C8116

1

2

C8115

1

2

C8104

1

2

C8109

1

2

C8114

1

2

C8113

1

2

C8108

1

2

C8103

1

2

C8160

1

2

C8166

1

2

C8159

1

2

C8151

1

2

C8158

1

2

C8165

1

2

C8164

1

2

C8150

1

2

C8157

1

2

C8163

1

2

C8162

1

2

C8156

1

2

C8122

1

2

C8121

1

2

C8120

1

2

C8119

1

2

C8118

1

2

C8161

1

2

C8167

1

2

C8169

1

2

C8168

1

2

C8171

1

2

C8170

1

2

8

BI

OUT

OUT OUT

OUT

OUT OUT

OUT

OUT OUT

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

OUT

FBAD20

FBAD22

FBAD1 FBAD2

FBAD18

FBAD0

FBAD3

FBAD5 FBAD6 FBAD7 FBAD8 FBAD9 FBAD10 FBAD11 FBAD12 FBAD13 FBAD14 FBAD15 FBAD16 FBAD17

FBAD19

FBAD21

FBAD23 FBAD24 FBAD25 FBAD26 FBAD27

FBAD29 FBAD30

FBAD32 FBAD33 FBAD34 FBAD35 FBAD36 FBAD37 FBAD38 FBAD39 FBAD40 FBAD41 FBAD42 FBAD43 FBAD44 FBAD45 FBAD46 FBAD47 FBAD48 FBAD49 FBAD50 FBAD51 FBAD52 FBAD53 FBAD54 FBAD55 FBAD56 FBAD57 FBAD58 FBAD59 FBAD60 FBAD61 FBAD62 FBAD63

FBA_PLLAVDD FBA_PLLGND

FBAD31

FBCAL_PD_VDDQ

FBCAL_PU_GND

FBAD28

FBAD4

FBADQS_WP0 FBADQS_WP1

FBADQS_WP3

FBADQS_WP2

FBADQS_WP6

FBADQS_WP5

FBADQS_WP4

FBADQS_WP7

FBA_DEBUG

FBADQS_RN2

FBADQS_RN1

FBADQS_RN0

FBADQS_RN4

FBADQS_RN3

FBADQS_RN5

FBADQS_RN7

FBADQS_RN6

FBA_CLK0

FBA_CLK0_L

FBA_CLK1_L

FBA_CLK1

FBADQM1

FBADQM0

FBADQM3

FBADQM2

FBADQM6

FBADQM5

FBADQM4

FBADQM7

FBA_CMD0

FBA_CMD2

FBA_CMD1

FBA_CMD5

FBA_CMD3 FBA_CMD4

FBA_CMD7

FBA_CMD6

FBA_CMD8

FBA_CMD10

FBA_CMD9

FBA_CMD13

FBA_CMD12

FBA_CMD11

FBA_CMD15

FBA_CMD14

FBA_CMD18

FBA_CMD17

FBA_CMD16

FBA_CMD20

FBA_CMD19

FBA_CMD23

FBA_CMD22

FBA_CMD21

FBA_CMD25

FBA_CMD24

FBA_CMD28

FBA_CMD26 FBA_CMD27

READ STROBE

WRITE STROBE

MEMORY INTERFACE A

OUT

OUT OUT

OUT

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

OUT OUT

OUT OUT OUT

OUT OUT OUT OUT OUT OUT OUT OUT OUT

OUT

FB_VREF

FBCAL_TERM_GND

FBC_PLLGND

FBC_PLLAVDD

FBCD63

FBCD62

FBCD61

FBCD60

FBCD59

FBCD58

FBCD57

FBCD56

FBCD55

FBCD53

FBCD51

FBCD50

FBCD49

FBCD48

FBCD47

FBCD46

FBCD45

FBCD44

FBCD43

FBCD41

FBCD40

FBCD39

FBCD38

FBCD37

FBCD36

FBCD35

FBCD34

FBCD33

FBCD32

FBCD31

FBCD30

FBCD29

FBCD28

FBCD27

FBCD26

FBCD25

FBCD24

FBCD23

FBCD22

FBCD21

FBCD20

FBCD19

FBCD18

FBCD17

FBCD16

FBCD15

FBCD11

FBCD9

FBCD8

FBCD7

FBCD6

FBCD5

FBCD4

FBCD3

FBCD2

FBCD1

FBCD10

FBCD42

FBCD0

FBCD54

FBCD52

FBCD13

FBCD12

FBCD14

FBCDQS_RN0 FBCDQS_RN1 FBCDQS_RN2 FBCDQS_RN3 FBCDQS_RN4 FBCDQS_RN5 FBCDQS_RN6 FBCDQS_RN7

FBCDQS_WP1 FBCDQS_WP2

FBCDQS_WP0

FBCDQS_WP4

FBCDQS_WP3

FBCDQS_WP6 FBCDQS_WP7

FBCDQS_WP5

FBC_DEBUG

FBCDQM7

FBC_CLK1

FBC_CLK0

FBC_CLK0_L

FBC_CLK1_L

FBCDQM0 FBCDQM1 FBCDQM2 FBCDQM3 FBCDQM4 FBCDQM5 FBCDQM6

FBC_CMD4

FBC_CMD3

FBC_CMD6

FBC_CMD5

FBC_CMD9

FBC_CMD8

FBC_CMD7

FBC_CMD11

FBC_CMD10

FBC_CMD14

FBC_CMD13

FBC_CMD12

FBC_CMD16

FBC_CMD15

FBC_CMD19

FBC_CMD18

FBC_CMD17

FBC_CMD21

FBC_CMD20

FBC_CMD22

FBC_CMD24

FBC_CMD23

FBC_CMD27

FBC_CMD26

FBC_CMD25

FBC_CMD28

FBC_CMD1

FBC_CMD0

FBC_CMD2

MEMORY INTERFACE B

WRITE STROBE

READ STROBE

OUT

BI BI BI BI BI BI BI BI

IN IN IN IN IN IN

IN

OUT

OUT OUT OUT OUT

OUT

BI

IN IN IN IN IN IN IN IN

OUT OUT OUT

OUT

OUT OUT OUT

G

D

S

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NC

Page Notes

- =PP1V2_GPU_FBPLLAVDD

(NONE)

- =PP1V8_GPU_FBIO

Power aliases required by this page:

Signal aliases required by this page:

BOM options provided by this page:

69 86

72

69 86

70 86

69 86

(3 OF 8)

OMIT

BGA

NB8P-GS-W-A2

20%

0.1UF

10V CERM 402

69 86

72

69 86

70 86

72

70 86

72

5% 1/16W MF-LF 402

10K

70 86

5% 1/16W MF-LF 402

10K

40.2

402

1%

MF-LF

1/16W

1%

MF-LF

402

1/16W

24.9

OMIT

(4 OF 8)

BGA

NB8P-GS-W-A2

16V

0.1uF

10% X5R

402

1.07K

MF-LF

402

1/16W

1%

0402

FERR-220-OHM

402

1%

MF-LF

1/16W

45.3

4.7UF

20%

603

CERM

6.3V

402

5% 1/16W MF-LF

10K

5% 1/16W MF-LF 402

10K

69 86

70 86

2N7002DW-X-F

SOT-363

402

MF-LF

1/16W

1%

2.49K

402

MF-LF

1/16W

1%

1.02K

69 70 72

SYNC_MASTER=(MASTER)

NV G84M Frame Buffer I/F

SYNC_DATE=(MASTER)

68 88

051-7225

A.0.0

FB_VREF_UNTERM

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

GPU_FB_VREF_UNTERM_L

GPU_FB_VREF

=PP1V8_GPU_FBIO

FB_B_WDQS<7>

FB_B_DQ<32>

FB_B_DQ<31>

TP_FBC_CMD28

TP_FBC_CMD27

FB_B_WDQS<6>

FB_B_WDQS<1> FB_B_WDQS<2>

FB_B_WDQS<4>

FB_B_WDQS<3>

FB_B_WDQS<5>

FB_B_RDQS<5> FB_B_RDQS<6> FB_B_RDQS<7>

FB_B_WDQS<0>

FB_B_RDQS<0> FB_B_RDQS<1> FB_B_RDQS<2> FB_B_RDQS<3> FB_B_RDQS<4>

FB_B_DQM_L<4>

FB_B_DQM_L<7>

FB_B_DQM_L<6>

FB_B_DQM_L<5>

FB_B_DQM_L<3>

FB_B_CLK_N<1>

FB_B_DQM_L<2>

FB_B_DQM_L<1>

FB_B_DQM_L<0>

FB_B_CLK_N<0>

FB_B_CLK_P<0>

FB_B_CLK_P<1>

TP_FBC_DEBUG

=PP1V8_GPU_FBIO

FB_A_DQ<35>

FB_A_CLK_N<1>

FB_A_CLK_P<1>

TP_FBA_CMD28

TP_FBA_CMD27

FB_A_CLK_N<0>

FB_A_CLK_P<0>

FB_A_WDQS<7>

FB_A_WDQS<6>

FB_A_WDQS<5>

FB_A_WDQS<4>

FB_A_WDQS<3>

FB_A_WDQS<2>

FB_A_WDQS<1>

FB_A_WDQS<0>

FB_A_RDQS<7>

FB_A_RDQS<6>

FB_A_RDQS<5>

FB_A_RDQS<4>

FB_A_RDQS<3>

FB_A_RDQS<2>

FB_A_RDQS<1>

FB_A_RDQS<0>

FB_A_DQM_L<7>

FB_A_DQM_L<6>

FB_A_DQM_L<5>

FB_A_DQM_L<4>

FB_A_DQM_L<3>

FB_A_DQM_L<2>

FB_A_DQM_L<1>

FB_A_DQM_L<0>

FBCAL_PU_GND

TP_FBA_DEBUG

FBCAL_PD_VDDQ

FB_A_CKE

FB_A_DQ<5>

FB_A_BA<2> FB_A_CS0_L

FB_A_DQ<2>

FB_A_DQ<1>

FB_B_DQ<63>FB_A_DQ<63>

FB_A_DQ<54> FB_A_DQ<55> FB_A_DQ<56> FB_A_DQ<57> FB_A_DQ<58> FB_A_DQ<59> FB_A_DQ<60> FB_A_DQ<61> FB_A_DQ<62>

FB_A_DQ<44> FB_A_DQ<45> FB_A_DQ<46> FB_A_DQ<47> FB_A_DQ<48> FB_A_DQ<49> FB_A_DQ<50> FB_A_DQ<51> FB_A_DQ<52> FB_A_DQ<53>

FB_A_DQ<34>

FB_A_DQ<36> FB_A_DQ<37> FB_A_DQ<38> FB_A_DQ<39> FB_A_DQ<40> FB_A_DQ<41> FB_A_DQ<42> FB_A_DQ<43>

FB_A_DQ<33>

FB_A_DQ<25> FB_A_DQ<26>

FB_A_DQ<28> FB_A_DQ<29> FB_A_DQ<30> FB_A_DQ<31> FB_A_DQ<32>

FB_A_DQ<13> FB_A_DQ<14> FB_A_DQ<15> FB_A_DQ<16> FB_A_DQ<17> FB_A_DQ<18> FB_A_DQ<19> FB_A_DQ<20> FB_A_DQ<21>

FB_A_DQ<4>

FB_A_DQ<7> FB_A_DQ<8>

FB_A_DQ<10> FB_A_DQ<11> FB_A_DQ<12>

FB_A_DQ<0>

FB_B_DQ<62>

FB_B_DQ<56>

FB_B_DQ<52>

FB_B_DQ<60>

FB_B_DQ<14>

FB_B_DQ<12> FB_B_DQ<13>

FB_B_DQ<54>

FB_B_UMA<2> FB_B_UMA<4>

FB_B_BA<2>

FB_B_DQ<0>

FB_B_BA<1>

FB_B_DQ<42>

FB_B_LMA<4>

FB_B_DQ<10>

FB_B_DQ<1> FB_B_DQ<2> FB_B_DQ<3> FB_B_DQ<4> FB_B_DQ<5> FB_B_DQ<6> FB_B_DQ<7> FB_B_DQ<8> FB_B_DQ<9>

FB_B_DQ<11>

FB_B_DQ<15> FB_B_DQ<16>

FB_B_DQ<19>

FB_B_DQ<22> FB_B_DQ<23> FB_B_DQ<24> FB_B_DQ<25> FB_B_DQ<26> FB_B_DQ<27> FB_B_DQ<28> FB_B_DQ<29> FB_B_DQ<30>

FB_B_DQ<33> FB_B_DQ<34> FB_B_DQ<35> FB_B_DQ<36> FB_B_DQ<37> FB_B_DQ<38> FB_B_DQ<39> FB_B_DQ<40> FB_B_DQ<41>

FB_B_DQ<44> FB_B_DQ<45> FB_B_DQ<46>

FB_B_DQ<49> FB_B_DQ<50>

FB_B_DQ<57> FB_B_DQ<58> FB_B_DQ<59>

FB_B_DQ<61>

FB_B_RAS_L FB_B_LMA<5>

FB_B_MA<11> FB_B_CAS_L FB_B_WE_L

FB_B_UMA<5> TP_FB_B_MA12

FB_B_MA<7> FB_B_MA<10>

FB_B_MA<6> FB_B_LMA<2> FB_B_MA<8> FB_B_LMA<3> FB_B_MA<1> TP_FB_B_MA13

FB_A_MA<9>

FB_A_LMA<2>

TP_FB_A_MA13

FB_A_MA<0>

FB_A_MA<11>

FB_A_UMA<3>

FB_A_RAS_L FB_A_LMA<5> FB_A_BA<1>

FB_B_DQ<17> FB_B_DQ<18>

FB_B_DQ<20> FB_B_DQ<21>

FB_A_UMA<4>

FB_B_BA<0>

FB_B_UMA<3>

FB_B_CS0_L

FB_A_UMA<2>

FB_B_DQ<43>

FB_B_DQ<51>

FB_B_DQ<55>

FB_A_LMA<4>

FB_A_MA<10>

FB_A_MA<7>

FB_A_UMA<5>

FB_A_WE_L

FB_A_DRAM_RST

FB_A_CAS_L

FB_A_BA<0>

TP_FB_A_MA12

FBCAL_TERM_GND

FB_B_DQ<53>

FB_A_LMA<3>

FB_A_MA<8>

FB_A_MA<1>

FB_A_MA<6>

FB_B_DQ<47> FB_B_DQ<48>

FB_B_MA<9>

FB_B_MA<0>

FB_B_CKE

FB_B_DRAM_RST

FB_A_DQ<22>

FB_A_DQ<24>

FB_A_DQ<27>

FB_A_DQ<23>

FB_A_DQ<9>

FB_A_DQ<6>

FB_A_DQ<3>

VOLTAGE=1.2V

PP1V2_GPU_FBA_PLL_F

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm

=PP1V2_GPU_FBPLLAVDD

U8000

P28 R28 Y27 AA27

P32 U27

T31 U32 W29 W30 T27 V28 V30 U31 R27 V29

P31

T30 W28 R29 R30 P29 U28 Y32 Y30 V32

U30 Y31 W32 W31 T32 V27 T28

AC27

G25 G24

N27 M27

N30 N32 L31 L30 J30 L32 H30 K30 H31 F30

N28

H32 E31 D30 E30 H28 H29 E29 J27 F27 E27

L29

E28

F28 AD29 AE29 AD28 AC28 AB29 AA30

Y28 AB30

K27

AM30 AF30 AJ31 AJ30 AJ32 AK29 AM31 AL30 AE32 AE30

K28

AE31 AD30 AC31 AC32 AB32 AB31 AG27 AF28 AH28 AG28

J29

AG29 AD27 AF27 AE28

J28

P30

N31

M29 M30 G30 F29 AA29 AK30 AC30 AG30

M28 K32 G31 G27 AA28 AL31 AF31 AH29

L28 K31 G32 G28 AB28 AL32 AF32 AH30

K26 H26

C8201

1

2

R8200

1

2

R8250

1

2

R8292

12

R8291

1

2

U8000

E32

E13 F13 F18 E17

C13 A16

C15 B16 F17 C19 D15 C17 A17 C16 D14 F16

A13

C14 C18 E14 B13 E15 F15 A20 C20 A15

B17 B20 A19 B19 B14 E16 A14

F12

G10

G9

J26

B7 A7

D12

D9 E12 D11

E8

D8

E7

F7

D6

D5

C7

D3

E4

C3

B4 C10 B10

C8 A10 C11 C12

A2

A11 B11 B28 C27 C26 B26 C30 B31 C29 A31

B2

D28 D27 F26 D24 E23 E26 E24 F23 B23 A23

C4

C25 C23 A22 C22 C21 B22 E22 D22 D21 E21

A5

E18 D19 D18 E19

B5

F9 F10

A4 E11 F5 C9 C28 F24 C24 E20

C6 E9 E6 A8 B29 E25 A25 F21

C5 E10 E5 B8 A29 D25 B25 F20

C8296

1

2

R8295

1

2

L8200

1 2

R8290

12

C8200

1

2

R8201

1

2

R8251

1

2

Q8295

3

5

4

R8296

1

2

R8297

1

2

68

8

72

8

72

8

DQ1

DQ0

DQ2 DQ3

DQ5 DQ6

DQ4

DQ8

DQ7

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21

DQ24

DQ23

DQ22

DQ25 DQ26 DQ27

DQ29

DQ28

DQ30 DQ31

RDQS3

RDQS2

RDQS1

RDQS0

SEN RESET

MF

ZQ

RAS*

CAS*

WE*

CS*

CK*

A9

A6 A7

A3 A4

A2

A0 A1

CK

WDQS2

WDQS1

WDQS0

WDQS3

BA0

BA2

BA1

RFU1 RFU2

DM3

DM2

DM1

DM0

A5

A11

A8/AP

A10

CKE

MFHIGH

(1 OF 2)

VSS0 VSS1 VSS2

VSS5

VSS3 VSS4

VSS7

VSS6

VSSA0 VSSA1

VSSQ0 VSSQ1 VSSQ2 VSSQ3

VSSQ5 VSSQ6

VSSQ4

VSSQ7 VSSQ8

VSSQ9 VSSQ10 VSSQ11 VSSQ12 VSSQ13 VSSQ14

VSSQ16

VSSQ15

VSSQ17 VSSQ18 VSSQ19VDDQ19

VDDQ20 VDDQ21

VREF1

VREF0

VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15

VDDQ18

VDDQ16 VDDQ17

VDDQ9

VDDA1

VDDQ0 VDDQ1 VDDQ2

VDDQ5

VDDQ3 VDDQ4

VDDQ6 VDDQ7 VDDQ8

VDD0 VDD1 VDD2

VDD5

VDD3 VDD4

VDD6 VDD7

VDDA0

(2 OF 2)

IN

BI

IN

OUT OUT OUT OUT

IN

IN IN

IN

OUT

OUT OUT

OUT

IN

IN IN

IN

IN IN

IN

DQ1

DQ0

DQ2 DQ3

DQ5 DQ6

DQ4

DQ8

DQ7

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21

DQ24

DQ23

DQ22

DQ25 DQ26 DQ27

DQ29

DQ28

DQ30 DQ31

RDQS3

RDQS2

RDQS1

RDQS0

SEN RESET

MF

ZQ

RAS*

CAS*

WE*

CS*

CK*

A9

A6 A7

A3 A4

A2

A0 A1

CK

WDQS2

WDQS1

WDQS0

WDQS3

BA0

BA2

BA1

RFU1 RFU2

DM3

DM2

DM1

DM0

A5

A11

A8/AP

A10

CKE

MFHIGH

(1 OF 2)

VSS0 VSS1 VSS2

VSS5

VSS3 VSS4

VSS7

VSS6

VSSA0 VSSA1

VSSQ0 VSSQ1 VSSQ2 VSSQ3

VSSQ5 VSSQ6

VSSQ4

VSSQ7 VSSQ8

VSSQ9 VSSQ10 VSSQ11 VSSQ12 VSSQ13 VSSQ14

VSSQ16

VSSQ15

VSSQ17 VSSQ18 VSSQ19VDDQ19

VDDQ20 VDDQ21

VREF1

VREF0

VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15

VDDQ18

VDDQ16 VDDQ17

VDDQ9

VDDA1

VDDQ0 VDDQ1 VDDQ2

VDDQ5

VDDQ3 VDDQ4

VDDQ6 VDDQ7 VDDQ8

VDD0 VDD1 VDD2

VDD5

VDD3 VDD4

VDD6 VDD7

VDDA0

(2 OF 2)

BI BI BI BI

BI BI BI BI BI

BI

BI BI BI BI

BI

IN IN

BI

IN IN

G

D

S

G

D

S

IN IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

BOM options provided by this page:

Signal aliases required by this page:

Power aliases required by this page:

Page Notes

Connect to designated pin, then GND

NC NC

- =PP1V8_S0_FB_VDDQ

- =PP1V8_S0_FB_VDD

(NONE)

U8400.J1

U8400.J12

U8400.J1

U8400.J12

NC

Connect to designated pin, then GND

2.37K

MF-LF

402

1%

1/16W

5.49K

MF-LF

1%

1/16W

402

16V

10%

402

X5R

0.1uF0.1uF

16V

10%

402

X5R

16V

10%

402

X5R

0.1uF

16V

10% X5R

0.1uF

402

0.1uF

X5R

10% 16V

402

0.1uF

402

10% 16V X5R X5R

402

10% 16V

0.1uF

16V

10% 402

X5R

0.1uF 0.1uF

16V

10% 402

X5R

16MX32-GDDR3-500MHZ

K4J52324QC-BC20

FBGA

OMIT

CRITICAL

FBGA

K4J52324QC-BC20

16MX32-GDDR3-500MHZ

CRITICAL

OMIT

100

1/16W

5%

402

MF-LF

1/16W

1%

402

MF-LF

243

121

1/16W

1%

402

MF-LF

1/16W

1%

402

MF-LF

121

402

10%

0.0047uF

25V CERM

402

X5R

10% 16V

0.1uF

16V

10%

402

X5R

0.1uF

10% 16V

402

X5R

0.1uF

5%

1K

MF-LF

402

1/16W

1/16W 402

MF-LF

1%

121

1%

121

MF-LF

402

1/16W

1/16W 402

121

1% MF-LF

1%

121

MF-LF

402

1/16W

68 86

68 69 86

68 86

68 69 86

68 86

68 69 86

68 86

68 69 86

68 86

68 69 86

68 86

68 69 86

68 86

68 69 86

68 86

68 69 86

MF-LF

402

1/16W

1K

5% 1%

121

MF-LF

402

1/16W

10%

0.1uF

X5R 402

16V

0.1uF

X5R 402

10% 16V

243

MF-LF

402

1%

1/16W

100

MF-LF 402

5% 1/16W

OMIT

16MX32-GDDR3-500MHZ

K4J52324QC-BC20

FBGA

CRITICAL

1/16W 402

MF-LF

121

1%

MF-LF 402

1% 1/16W

121

1%

121

MF-LF

402

1/16W

1% MF-LF

402

1/16W

121

MF-LF

402

1%

1/16W

121

0.1uF

X5R 402

10% 16V

0.1uF

X5R 402

10% 16V

0.1uF

X5R 402

10% 16V

FBGA

K4J52324QC-BC20

16MX32-GDDR3-500MHZ

OMIT

CRITICAL

0.1uF

X5R 402

10% 16V

X5R

0.1uF

402

10% 16V

402

0.1uF

X5R

10% 16V

0.1uF

X5R 402

10% 16V

0.1uF

X5R 402

10% 16V

0.1uF

X5R 402

10% 16V

0.1uF

X5R 402

10% 16V

68 86

6.3V

20%

805

CERM-X5R

22UF

805

6.3V

20%

CERM-X5R

22UF

805

6.3V

20%

CERM-X5R

22UF

6.3V

20%

805

CERM

0.01UF

402

10% 16V

CERM

0.01UF

402

10% 16V

402

MF-LF

1%

1/16W

2.21K

2N7002DW-X-F

SOT-363

10% 402

0.0047uF

25V CERM

SOT-363

2N7002DW-X-F

CERM

25V

0.0047uF

10% 402

402

MF-LF

1%

1/16W

2.21K

1/16W

1%

402

MF-LF

2.37K

402

1/16W

1%

MF-LF

5.49K

68 69 70 72

CERM

25V

0.0047uF

402

10%

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

GDDR3 Frame Buffer A

69

A.0.0

051-7225

88

FB_A0_MF

FB_A_LMA<5>

FB_A_MA<0>

=PP1V8_GPU_FB_VDD

FB_A_RDQS<6> FB_A_RDQS<4>

=PP1V8_GPU_FB_VDDQ

FB_A1_VREF_UNTERM_L

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

FB_A_UMA<4>

FB_A_UMA<2>

FB_A_CLK_P<1>

FB_A1_MF

FB_A_LMA<4>

FB_A_CLK_P<0>

FB_A_LMA<2>

FB_A_MA<6>

FB_A_BA<2>

FB_A_DQ<28>

FB_A_DQ<0>

FB_A_MA<11>

FB_A_CS0_L

FB_A_CAS_L FB_A_RAS_L

FB_A1_ZQ

FB_A_MA<8>

FB_A_MA<11>

FB_A_RDQS<2>

FB_A_MA<10>

FB_A_MA<8>

FB_A_DQM_L<7> FB_A_DQM_L<5> FB_A_DQM_L<6> FB_A_DQM_L<4>

FB_A_BA<1>

FB_A_BA<0>

FB_A_WDQS<4>

FB_A_WDQS<7> FB_A_WDQS<5> FB_A_WDQS<6>

FB_A_MA<1>

FB_A_MA<7>

FB_A_MA<6>

FB_A_MA<9>

FB_A_DRAM_RST

FB_A1_SEN

FB_A_RDQS<7> FB_A_RDQS<5>

FB_A_DQ<38>

FB_A_DQ<39>

FB_A_DQ<37>

FB_A_DQ<35>

FB_A_DQ<33>

FB_A_DQ<54>

FB_A_DQ<34>

FB_A_DQ<48>

FB_A_DQ<50>

FB_A_DQ<43>

FB_A_DQ<41>

FB_A_DQ<44>

FB_A_DQ<61>

FB_A_DQ<59>

FB_A_DQ<62>

FB_A_MA<10>

FB_A_DQM_L<0>

FB_A_DQM_L<2> FB_A_DQM_L<3>

FB_A_BA<1>

FB_A_DQ<30>

FB_A_DQ<29>

FB_A_DQ<31> FB_A_DQ<26>

FB_A_DQ<24>

FB_A_DQ<27>

FB_A_DQ<22> FB_A_DQ<23> FB_A_DQ<25>

FB_A_DQ<19>

FB_A_DQ<21>

FB_A_DQ<20>

FB_A_DQ<16>

FB_A_DQ<18>

FB_A_DQ<17>

FB_A_DQ<13>

FB_A_DQ<14>

FB_A_DQ<15>

FB_A_DQ<12>

FB_A_DQ<11>

FB_A_DQ<10>

FB_A_DQ<9>

FB_A_DQ<6> FB_A_DQ<8>

FB_A_DQ<5>

FB_A_DQ<3>

FB_A_DQ<7>

FB_A_DQ<2>

FB_A_DQ<1> FB_A_DQ<4>

FB_A_BA<2>

FB_A_DQM_L<1>

FB_A_RDQS<3>

FB_A_RDQS<1>

FB_A_RDQS<0>

FB_A_DQ<56> FB_A_DQ<58>

FB_A_DQ<57> FB_A_DQ<63> FB_A_DQ<60>

FB_A_DQ<40> FB_A_DQ<47> FB_A_DQ<46> FB_A_DQ<45> FB_A_DQ<42>

FB_A_RAS_L

FB_A_CKE

FB_A_WE_L

FB_A_CKE

FB_A_CLK_N<1>

FB_A_UMA<5>

=PP1V8_GPU_FB_VDD

FB_A0_SEN

FB_A_BA<0>

FB_A_WDQS<3>

FB_A_WDQS<2>

FB_A_WDQS<1>

FB_A_WDQS<0>

FB_A_CAS_L

FB_A_WE_L

FB_A_CS0_L

FB_A_DQ<52> FB_A_DQ<51> FB_A_DQ<55> FB_A_DQ<49>

FB_A_DQ<53>

FB_A_DQ<36>

FB_A_DQ<32>

FB_A_DRAM_RST

FB_A0_ZQ

FB_A_CLK_N<0>

FB_A_MA<9>

FB_A_MA<7>

FB_A_LMA<3>

FB_A_MA<1>

=PP1V8_GPU_FB_VDDQ

FB_A_CLK0_TERM

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm

FB_A0_VREF_UNTERM_L

FB_VREF_UNTERM

FB_A_CLK1_TERM

FB_VREF_UNTERM

FB_A_UMA<3>

FB_A_MA<0>

FB_A0_VREF

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm

FB_A1_VREF

C8431

1

2

R8430

1

2

R8431

1

2

C8403

1

2

C8402

1

2

C8404

1

2

C8401

1

2

C8422

1

2

C8423

1

2

C8424

1

2

C8425

1

2

C8426

1

2

U8400

K9

H11

K11

L9

K10

M9 K4 H2 K3 L4 K2 M4

G9 G4 H3

F9

J11 J10

H9

F4

E3 E10 N10 N3

B2 B3

C11 C10 E11 F10 F11 G10 M11 L10 N11 M10

C2

R11 R10 T11 T10 M2 L3 N2 M3 R2 R3

C3

T2 T3

E2 F3 F2 G3 B11 B10

A9

H10

D3 D10 P10

P3

V9

J2

J3

V4

D2 D11 P11

P2

H4

A4

U8400

A2

A11

F1

F12

M1

M12

V2

V11

K1

K12

A1

A12

J4 J9 N1 N4 N9

N12

R1 R4 R9

R12

C1

V1

V12

C4 C9

C12

E1 E4 E9

E12

H1

H12

A3 A10 G1 G12 L1 L12 V3 V10

J1 J12

B1 B4

L2 L11 P1 P4 P9 P12 T1 T4 T9 T12

B9 B12 D1 D4 D9 D12 G2 G11

R8449

1

2

R8448

1

2

R8445

1

2

R8446

1

2

C8433

1

2

C8421

1

2

C8415

1

2

C8410

1

2

R8440

1

2

R8447

1

2

R8444

1

2

R8443

1

2

R8442

1

2

R8490

1

2

R8492

1

2

C8471

1

2

C8472

1

2

R8498

1

2

R8499

1

2

U8450

K9

H11

K11

L9

K10

M9 K4 H2 K3 L4 K2 M4

G9 G4 H3

F9

J11 J10

H9

F4

E3 E10 N10 N3

B2 B3

C11 C10 E11 F10 F11 G10 M11 L10 N11 M10

C2

R11 R10 T11 T10 M2 L3 N2 M3 R2 R3

C3

T2 T3

E2 F3 F2 G3 B11 B10

A9

H10

D3 D10 P10

P3

V9

J2

J3

V4

D2 D11 P11

P2

H4

A4

R8493

1

2

R8495

1

2

R8494

1

2

R8497

1

2

R8496

1

2

C8473

1

2

C8474

1

2

C8475

1

2

U8450

A2

A11

F1

F12

M1

M12

V2

V11

K1

K12

A1

A12

J4 J9 N1 N4 N9

N12

R1 R4 R9

R12

C1

V1

V12

C4 C9

C12

E1 E4 E9

E12

H1

H12

A3 A10 G1 G12 L1 L12 V3 V10

J1 J12

B1 B4

L2 L11 P1 P4 P9 P12 T1 T4 T9 T12

B9 B12 D1 D4 D9 D12 G2 G11

C8476

1

2

C8451

1

2

C8452

1

2

C8460

1

2

C8453

1

2

C8465

1

2

C8454

1

2

C8400

1

2

C8420

1

2

C8450

1

2

C8470

1

2

C8446

1

2

C8496

1

2

R8432

1

2

Q8400

3

5

4

C8483

1

2

Q8400

6

2

1

C8481

1

2

R8482

1

2

R8480

1

2

R8481

1

2

70

69

8

DQ1

DQ0

DQ2 DQ3

DQ5 DQ6

DQ4

DQ8

DQ7

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21

DQ24

DQ23

DQ22

DQ25 DQ26 DQ27

DQ29

DQ28

DQ30 DQ31

RDQS3

RDQS2

RDQS1

RDQS0

SEN RESET

MF

ZQ

RAS*

CAS*

WE*

CS*

CK*

A9

A6 A7

A3 A4

A2

A0 A1

CK

WDQS2

WDQS1

WDQS0

WDQS3

BA0

BA2

BA1

RFU1 RFU2

DM3

DM2

DM1

DM0

A5

A11

A8/AP

A10

CKE

MFHIGH

(1 OF 2)

VSS0 VSS1 VSS2

VSS5

VSS3 VSS4

VSS7

VSS6

VSSA0 VSSA1

VSSQ0 VSSQ1 VSSQ2 VSSQ3

VSSQ5 VSSQ6

VSSQ4

VSSQ7 VSSQ8

VSSQ9 VSSQ10 VSSQ11 VSSQ12 VSSQ13 VSSQ14

VSSQ16

VSSQ15

VSSQ17 VSSQ18 VSSQ19VDDQ19

VDDQ20 VDDQ21

VREF1

VREF0

VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15

VDDQ18

VDDQ16 VDDQ17

VDDQ9

VDDA1

VDDQ0 VDDQ1 VDDQ2

VDDQ5

VDDQ3 VDDQ4

VDDQ6 VDDQ7 VDDQ8

VDD0 VDD1 VDD2

VDD5

VDD3 VDD4

VDD6 VDD7

VDDA0

(2 OF 2)

IN

BI

IN

OUT OUT OUT OUT

IN

IN IN

IN

OUT

OUT OUT

OUT

IN

IN IN

IN

IN IN

IN

DQ1

DQ0

DQ2 DQ3

DQ5 DQ6

DQ4

DQ8

DQ7

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21

DQ24

DQ23

DQ22

DQ25 DQ26 DQ27

DQ29

DQ28

DQ30 DQ31

RDQS3

RDQS2

RDQS1

RDQS0

SEN RESET

MF

ZQ

RAS*

CAS*

WE*

CS*

CK*

A9

A6 A7

A3 A4

A2

A0 A1

CK

WDQS2

WDQS1

WDQS0

WDQS3

BA0

BA2

BA1

RFU1 RFU2

DM3

DM2

DM1

DM0

A5

A11

A8/AP

A10

CKE

MFHIGH

(1 OF 2)

VSS0 VSS1 VSS2

VSS5

VSS3 VSS4

VSS7

VSS6

VSSA0 VSSA1

VSSQ0 VSSQ1 VSSQ2 VSSQ3

VSSQ5 VSSQ6

VSSQ4

VSSQ7 VSSQ8

VSSQ9 VSSQ10 VSSQ11 VSSQ12 VSSQ13 VSSQ14

VSSQ16

VSSQ15

VSSQ17 VSSQ18 VSSQ19VDDQ19

VDDQ20 VDDQ21

VREF1

VREF0

VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15

VDDQ18

VDDQ16 VDDQ17

VDDQ9

VDDA1

VDDQ0 VDDQ1 VDDQ2

VDDQ5

VDDQ3 VDDQ4

VDDQ6 VDDQ7 VDDQ8

VDD0 VDD1 VDD2

VDD5

VDD3 VDD4

VDD6 VDD7

VDDA0

(2 OF 2)

BI BI BI BI

BI BI BI BI BI

BI

BI BI BI BI

BI

IN IN

BI

IN IN

G

D

S

G

D

S

IN IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

U8500.J12

U8500.J1

U8500.J12

U8500.J1

Connect to designated pin, then GND

NC NCNC

NC

- =PP1V8_S0_FB_VDDQ

- =PP1V8_S0_FB_VDD

(NONE)

Signal aliases required by this page:

BOM options provided by this page:

Power aliases required by this page:

Page Notes

Connect to designated pin, then GND

402

0.1uF

X5R

10% 16V

0.1uF

X5R 402

10% 16V

0.1uF

X5R 402

10% 16V

0.1uF

X5R

10% 16V

402

0.1uF

X5R 402

10% 16V

0.1uF

X5R 402

10% 16V

0.1uF

X5R 402

10% 16V

0.1uF

X5R 402

10% 16V 16V

402

0.1uF

X5R

10%

CRITICAL

OMIT

FBGA

K4J52324QC-BC20

16MX32-GDDR3-500MHZ

K4J52324QC-BC20

FBGA

OMIT

CRITICAL

100

MF-LF 402

5% 1/16W

243

MF-LF

402

1%

1/16W

402

0.1uF

X5R

10% 16V

0.1uF

X5R 402

10% 16V

0.1uF

X5R 402

10% 16V

68 86

68 70 86

68 86

68 70 86

68 86

68 70 86

68 86

68 70 86

68 86

68 70 86

68 86

68 70 86

68 86

68 70 86

68 86

68 70 86

0.1uF

16V

10% 402

X5R

0.1uF

16V

10% 402

X5R

1%

243

MF-LF

402

1/16W

100

5% MF-LF

402

1/16W

FBGA

CRITICAL

OMIT

K4J52324QC-BC20

16MX32-GDDR3-500MHZ

0.1uF

16V X5R 402

10%

0.1uF

X5R 402

10% 16V

0.1uF

16V

10% 402

X5R

16MX32-GDDR3-500MHZ

FBGA

CRITICAL

OMIT

K4J52324QC-BC20

0.1uF

16V

10% 402

X5R

16V

10%

402

X5R

0.1uF

16V

10%

402

X5R

0.1uF

X5R 402

10% 16V

0.1uF

X5R 402

10% 16V

0.1uF

X5R 402

10% 16V

16V

10%

402

X5R

0.1uF

68 86

CERM-X5R

22UF

805

6.3V

20%

22UF

805

6.3V

20%

CERM-X5R

22UF

805

6.3V

20%

CERM-X5R

805

6.3V

20%

22UF

CERM-X5R

MF-LF

1/16W

402

1%

121

1/16W 402

MF-LF

1%

121

402

MF-LF

1%

121

1/16W

121

1/16W

1%

402

MF-LF

1/16W

1%

121

MF-LF

402

1K

1/16W

402

MF-LF

5%

1/16W 402

121

1% MF-LF

1/16W

1%

402

MF-LF

121

1/16W 402

MF-LF

1%

121

1/16W

1%

121

402

MF-LF

1/16W

402

MF-LF

121

1%

1/16W

402

MF-LF

121

1%

121

1% MF-LF

402

1/16W

5%

1K

1/16W

402

MF-LF

CERM

0.01UF

402

10% 16V16V

10%

402

CERM

0.01UF

402

1/16W

1%

MF-LF

5.49K

402

MF-LF

1%

1/16W

2.21K

CERM

25V

0.0047uF

10% 402

0.0047uF

25V CERM

SOT-363

2N7002DW-X-F

1/16W

1%

402

MF-LF

2.37K

5.49K

MF-LF

1%

1/16W

402

1/16W

1%

MF-LF

402

2.21K

2.37K

MF-LF

402

1%

1/16W

CERM

25V

0.0047uF

402

10%

402

10%

0.0047uF

25V CERM

2N7002DW-X-F

SOT-363

68 69 70 72

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

051-7225

A.0.0

8870

GDDR3 Frame Buffer B

=PP1V8_GPU_FB_VDDQ

FB_VREF_UNTERMFB_VREF_UNTERM

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

FB_B0_VREF_UNTERM_L

FB_B_CLK0_TERM

=PP1V8_GPU_FB_VDD =PP1V8_GPU_FB_VDD

FB_B1_MFFB_B0_MF

FB_B_RAS_L

FB_B_DRAM_RST FB_B_RDQS<2>

FB_B_UMA<2>

FB_B_LMA<3>

FB_B_LMA<2>

FB_B_LMA<4> FB_B_LMA<5>

FB_B_RAS_L

FB_B_CAS_L

FB_B_WE_L

FB_B_CS0_L

FB_B_CKE

FB_B_CAS_L

FB_B1_SEN

FB_B_DQ<35>

FB_B_RDQS<5>

FB_B_BA<2>FB_B_BA<2>

FB_B_DQM_L<6>

FB_B_DQM_L<7>

FB_B_BA<1>

FB_B_BA<0>

FB_B_WDQS<7>

FB_B_WDQS<6> FB_B_WDQS<5>

FB_B_DRAM_RST FB_B_RDQS<6>

FB_B_RDQS<7>

FB_B_DQ<57>

FB_B_DQ<62>

FB_B_DQ<59>

FB_B_DQ<61>

FB_B_DQ<33> FB_B_DQ<63>

FB_B_DQ<32>

FB_B_DQ<34>

FB_B_DQ<38>

FB_B_DQ<37>

FB_B_DQ<47>

FB_B_DQ<46>

FB_B_DQ<43>

FB_B_DQ<41>

FB_B_DQ<42>

FB_B_DQ<52>

FB_B_DQ<54>

FB_B_DQ<55>

FB_B_DQ<51>

FB_B_DQ<48>

FB_B_DQ<49> FB_B_DQ<50>

FB_B_MA<8>

FB_B_DQM_L<2> FB_B_DQM_L<1>

FB_B_WDQS<0>

FB_B_WDQS<1> FB_B_WDQS<3>

FB_B_MA<0>

FB_B_MA<6>

FB_B_DQ<3>

FB_B_DQ<7>

FB_B_DQ<0>

FB_B_DQ<6>

FB_B_DQ<1>

FB_B_DQ<26> FB_B_DQ<27> FB_B_DQ<2>

FB_B_DQ<30>

FB_B_DQ<31>

FB_B_DQ<29>

FB_B_DQ<28>

FB_B_DQ<24>

FB_B_DQ<11>

FB_B_DQ<14>

FB_B_DQ<13>

FB_B_DQ<10>

FB_B_DQ<9>

FB_B_DQ<12>

FB_B_DQ<22> FB_B_DQ<8>

FB_B_DQ<21>

FB_B_DQ<20>

FB_B_DQ<23>

FB_B_BA<1>

FB_B_BA<0>

FB_B_DQ<56> FB_B_DQ<60>

FB_B_MA<1>

FB_B_DQ<45>

FB_B_DQ<58>

FB_B1_ZQ

FB_B_DQ<15>

FB_B0_SEN

FB_B0_ZQ

FB_B_RDQS<1> FB_B_RDQS<3> FB_B_RDQS<0>

FB_B_DQM_L<3>

FB_B_DQ<18>

FB_B_DQ<19> FB_B_DQ<16>

FB_B_DQ<25>

FB_B_DQ<4> FB_B_DQ<5>

FB_B_RDQS<4>

FB_B_DQ<17>

FB_B_MA<11>

FB_B_WDQS<2>

FB_B_WE_L

FB_B_CS0_L

FB_B_CLK_N<0>

FB_B_CKE

FB_B_MA<10>

FB_B_MA<9>

FB_B_MA<7>

FB_B_MA<1>

FB_B_DQ<39>

FB_B_DQ<36>

FB_B_DQ<44>

FB_B_DQ<40>

FB_B_CLK_N<1>

FB_B_CLK_P<1>

FB_B_MA<6>

FB_B_UMA<3> FB_B_UMA<4> FB_B_UMA<5>

FB_B_MA<7> FB_B_MA<8> FB_B_MA<9> FB_B_MA<10> FB_B_MA<11>

FB_B_DQ<53>

FB_B_DQM_L<5> FB_B_DQM_L<4>

FB_B_MA<0>

FB_B_CLK_P<0>

FB_B_CLK1_TERM

FB_B_WDQS<4>

FB_B_DQM_L<0>

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm

FB_B1_VREF_UNTERM_L

=PP1V8_GPU_FB_VDDQ

FB_B0_VREF

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm

FB_B1_VREF

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

C8503

1

2

C8502

1

2

C8504

1

2

C8501

1

2

C8522

1

2

C8523

1

2

C8524

1

2

C8525

1

2

C8526

1

2

U8500

K9

H11

K11

L9

K10

M9 K4 H2 K3 L4 K2 M4

G9 G4 H3

F9

J11 J10

H9

F4

E3 E10 N10 N3

B2 B3

C11 C10 E11 F10 F11 G10 M11 L10 N11 M10

C2

R11 R10 T11 T10 M2 L3 N2 M3 R2 R3

C3

T2 T3

E2 F3 F2 G3 B11 B10

A9

H10

D3 D10 P10

P3

V9

J2

J3

V4

D2 D11 P11

P2

H4

A4

U8500

A2

A11

F1

F12

M1

M12

V2

V11

K1

K12

A1

A12

J4 J9 N1 N4 N9

N12

R1 R4 R9

R12

C1

V1

V12

C4 C9

C12

E1 E4 E9

E12

H1

H12

A3 A10 G1 G12 L1 L12 V3 V10

J1 J12

B1 B4

L2 L11 P1 P4 P9 P12 T1 T4 T9 T12

B9 B12 D1 D4 D9 D12 G2 G11

R8549

1

2

R8548

1

2

C8521

1

2

C8515

1

2

C8510

1

2

C8571

1

2

C8572

1

2

R8598

1

2

R8599

1

2

U8550

K9

H11

K11

L9

K10

M9 K4 H2 K3 L4 K2 M4

G9 G4 H3

F9

J11 J10

H9

F4

E3 E10 N10 N3

B2 B3

C11 C10 E11 F10 F11 G10 M11 L10 N11 M10

C2

R11 R10 T11 T10 M2 L3 N2 M3 R2 R3

C3

T2 T3

E2 F3 F2 G3 B11 B10

A9

H10

D3 D10 P10

P3

V9

J2

J3

V4

D2 D11 P11

P2

H4

A4

C8573

1

2

C8574

1

2

C8575

1

2

U8550

A2

A11

F1

F12

M1

M12

V2

V11

K1

K12

A1

A12

J4 J9 N1 N4 N9

N12

R1 R4 R9

R12

C1

V1

V12

C4 C9

C12

E1 E4 E9

E12

H1

H12

A3 A10 G1 G12 L1 L12 V3 V10

J1 J12

B1 B4

L2 L11 P1 P4 P9 P12 T1 T4 T9 T12

B9 B12 D1 D4 D9 D12 G2 G11

C8576

1

2

C8551

1

2

C8552

1

2

C8560

1

2

C8553

1

2

C8565

1

2

C8554

1

2

C8500

1

2

C8520

1

2

C8550

1

2

C8570

1

2

R8546

1

2

R8547

1

2

R8544

1

2

R8545

1

2

R8542

1

2

R8540

1

2

R8543

1

2

R8596

1

2

R8597

1

2

R8595

1

2

R8594

1

2

R8592

1

2

R8593

1

2

R8590

1

2

C8596

1

2

C8546

1

2

R8531

1

2

R8532

1

2

C8531

1

2

C8533

1

2

Q8500

3

5

4

R8530

1

2

R8581

1

2

R8582

1

2

R8580

1

2

C8581

1

2

C8583

1

2

Q8500

6

2

1

70

70 70

70 69

69 69

69

8

8 8

8

VDD33_1 VDD33_2 VDD33_3 VDD33_4 VDD33_5 VDD33_6 VDD33_7 VDD33_8 VDD33_9 VDD33_10 VDD33_11 VDD33_12 VDD33_13

ROM_SCLK ROM_SI ROM_SO

TESTMODE SWAPRDY_A

MIOA_VDDQ_1 MIOA_VDDQ_2 MIOA_VDDQ_3 MIOA_VDDQ_4 MIOA_VDDQ_5 MIOB_VDDQ_1 MIOB_VDDQ_2 MIOB_VDDQ_3 MIOB_VDDQ_4 MIOB_VDDQ_5

MIOA_VREF MIOB_VREF

MIOACAL_PD_VDDQ MIOACAL_PU_GND

MIOBCAL_PD_VDDQ MIOBCAL_PU_GND

PLLVDD PLLGND

H_PLLVDD

VID_PLLVDD

XTALIN XTALOUT

XTALOUTBUFF

XTALSSIN

GPIO0 GPIO1 GPIO2 GPIO3

GPIO9

GPIO11

SPDIF

STEREO

JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS

MIOA_CLKOUT

MIOA_CTL3

MIOA_DE

MIOAD0 MIOAD1 MIOAD2 MIOAD3 MIOAD4 MIOAD5 MIOAD6 MIOAD7 MIOAD8

MIOAD9 MIOAD10 MIOAD11

MIOA_HSYNC MIOA_VSYNC

MIOB_CLKIN

MIOB_CLKOUT

MIOB_CTL3

MIOB_DE

MIOBD0

MIOBD1

MIOBD2

MIOBD3

MIOBD4

MIOBD5

MIOBD6

MIOBD7

MIOBD8

MIOBD9 MIOBD10 MIOBD11

MIOB_HSYNC MIOB_VSYNC

THERMDP THERMDN

GPIO4 GPIO5 GPIO6 GPIO7 GPIO8

GPIO10

GPIO12

GPIO13

GPIO14

BUFRST_L

JTAG_TRST_L

MIOA_CLKOUT_L

MIOB_CLKOUT_L

ROMCS_L

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Typically <??mA

40mA

Power aliases required by this page:

- =PP3V3_GPU_VDD33

- =PP3V3_GPI_MIO

- =PP1V2_GPU_PLLVDD

- =PP1V2_GPU_H_PLLVDD

- =PP1V2_GPU_VID_PLLVDD

(NONE)

(IPD)

40mA

Signal aliases required by this page: (NONE)

BOM options provided by this page:

Page Notes

BGA

(6 OF 8)

OMIT

NB8P-GS-W-A2

10K

1/16W MF-LF

5%

402

100K

402

1/16W

5%

MF-LF

402

0.47UF

10%

6.3V CERM-X5R

402

0.47UF

10%

6.3V CERM-X5R

0.1uF

X5R

16V 402

10%

4.7UF

603

CERM

6.3V

20%

FERR-220-OHM

0402

FERR-220-OHM

0.1uF

10% 16V X5R 402

MF-LF

5%

1/16W

402

10K

5%

MF-LF

402

1/16W

10K

49.9

1% 1/16W MF-LF

402

1/16W MF-LF

49.9

1%

402

49.9

1% 1/16W MF-LF 402

402

X5R

16V

10%

0.1uF

402

MF-LF

1/16W

5%

10K

1/16W MF-LF 402

5%

10K

6.3V

10%

1UF

CERM

402

6.3V 402

10%

1UF

CERM

49.9

402

MF-LF

1/16W

1%

10%

402

16V X5R

0.1uF

20%

6.3V CERM

603

4.7UF

FERR-220-OHM

0402

20%

6.3V CERM

603

4.7UF

0.1uF

X5R

16V 402

10%

4.7UF

603

CERM

6.3V

20%20%

6.3V CERM

603

4.7UF

603

CERM

6.3V

20%

402

0.47UF

10%

6.3V CERM-X5R

SYNC_MASTER=(MASTER)

051-7225

A.0.0

8871

SYNC_DATE=(MASTER)

NV G84M GPIO/MIO/Misc

=PP1V2_GPU_PLLVDD

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

PP1V2_GPU_H_PLLVDD_F

VOLTAGE=1.2V

GPU_ROM_CS_L

GPU_GPIO_13

GPU_MIOB_D<1>

GPU_MIOB_D<0>

GPU_MIOB_CLKIN

GPU_THERMD_P

GPU_MIOB_HSYNC

TP_GPU_JTAG_TRST_L

GPU_GPIO_12

GPU_GPIO_10

GPU_GPIO_8

GPU_GPIO_5

GPU_GPIO_4

GPU_THERMD_N

TP_GPU_JTAG_TMS

TP_GPU_JTAG_TDO

TP_GPU_JTAG_TDI

TP_GPU_JTAG_TCK

GPU_SPDIF

GPU_GPIO_9

GPU_GPIO_3

GPU_GPIO_2

GPU_GPIO_0

GPU_STEREO TP_GPU_BUFRST_L

GPU_TESTMODE_PD

GPU_ROM_SO

GPU_ROM_SCLK

GPU_GPIO_14

GPU_GPIO_11

GPU_GPIO_1

GPU_GPIO_7

GPU_GPIO_6

GPU_MIOA_CLKOUT_P GPU_MIOA_CLKOUT_N GPU_MIOA_CTL3 GPU_MIOA_DE GPU_MIOA_D<0> GPU_MIOA_D<1> GPU_MIOA_D<2> GPU_MIOA_D<3> GPU_MIOA_D<4> GPU_MIOA_D<5>

GPU_MIOA_D<9> GPU_MIOA_D<10> GPU_MIOA_D<11> GPU_MIOA_HSYNC

GPU_MIOB_VSYNC

GPU_MIOB_D<11>

GPU_MIOB_D<9>

GPU_MIOB_D<8>

GPU_MIOB_D<7>

GPU_MIOB_D<6>

GPU_MIOB_D<5>

GPU_MIOB_D<4>

GPU_MIOB_D<3>

GPU_MIOB_D<2>

GPU_MIOB_DE

GPU_MIOB_CTL3

GPU_MIOB_CLKOUT_N

GPU_MIOB_CLKOUT_P

GPU_MIOB_D<10>

GPU_XTALSSIN

GPU_ROM_SI

GPU_MIOA_PD_VDDQ GPU_MIOA_PU_GND

GPU_MIOB_PD_VDDQ GPU_MIOB_PU_GND

GPU_MIOA_PD_VDDQ GPU_MIOB_PD_VDDQ

GPU_MIOB_PU_GND

GPU_MIOA_PU_GND

GPU_MIOA_D<8>

GPU_MIOA_D<7>

GPU_XTALIN GPU_XTALOUT

GPU_XTALOUTBUFF

GPU_MIOA_D<6>

GPU_MIOA_VSYNC

GPU_MIOB_VREF

GPU_MIOA_VREF

=PP3V3_GPU_MIO

PP1V2_GPU_PLLVDD_F

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.2V

=PP1V2_GPU_H_PLLVDD

VOLTAGE=1.2V

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

PP1V2_GPU_VID_PLLVDD_F

=PP1V2_GPU_VID_PLLVDD

=PP3V3_GPU_MIO

GPU_SWAPRDY_A

=PP3V3_GPU_VDD33

U8000

F3

K3 H1

H5 F4 E3 U3 U4

K5 G5 E2 J5 G6 K6 E1 D2

G23

AJ11 AK12 AL12 AK11 AL13

R4 P4 P3 P1

R3

M7 M8 R8 T8 U9

L2

R1

L1 L3

P2 N2

L4 L5

N1 N3 M1 M3 P5 N6 N5 M4

AE4 AD4 AD5 AD3 AD1

AF3

AA8 AB7 AB8 AC6 AC7

Y2

AE3

Y1 Y3

AC3 AC1

AB4 AA5

AC2 AB2 AB1 AA1 AB3 AA3 AC5 AB5

U10

T9

AA7

W2

AA6

AA4

J6 T3

M6

H2

J1

K1

AC11

L10

L7 L8

M10

AC12 AC24 AD24 AE11 AE12

H7 J7 K7

T10

U1 U2

T2

T1

R8696

1 2

R8695

1

2

C8601

1

2

C8602

1

2

C8636

1

2

C8635

1

2

L8635

1 2

L8640

1 2

C8617

1

2

R8616

1

2

R8617

1

2

R8620

1

2

R8622

1

2

R8621

1

2

C8619

1

2

R8618

1

2

R8619

1

2

C8611

1

2

C8610

1

2

R8623

1

2

C8631

1

2

C8630

1

2

L8630

1 2

C8633

1

2

C8641

1

2

C8640

1

2

C8643

1

2

C8637

1

2

C8600

1

2

72

71

8

72

71

72

8

IN

DB

DC

DD

EN_L

IN

S2D

S1D

S2C

S1C

S2B

S1B

S2A

S1A

DA

VCC

GND

THRML

PAD

OUT

IN

G

D S

G

D

S

OUT

BI

GND

VCC

NC

SDA

SCL

NC

OUT

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_5_ITEM

TABLE_ALT_ITEM

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

MIOB_CTL3, MIOB_D<11>

PCI_DEVID<4..3>

MIOB_VSYNC, MIOB_D<10>

ROMTYPE<1..0>

BAR2_SIZE

PCI_IOBAR

SLOT_CLOCK_CFG

USER<3..0>

MIOB_DE

Analog Video Mux

PCI_DEVID0

PCI_DEVID1

PCI_DEVID2

3GIO_PADCFG1

3GIO_PADCFG0

RAMCFG3

RAMCFG2

RAMCFG1

Place Rs near GPU

Unused Clocks

RAMCFG0

VID1

NC

MEM_VID

MEM_VREF SLI_SYNC

AC_DET

PWR_CTL0

GPIOs

HPD1

VID0

FAN_PWM

THERM

Native Func

Place Rs

Renamed signals

Unused signals

Unused I2C Buses

Config Straps

LCD0_BL_PWM

I2CS ties into SMBus connection page

(I2CS requires pullups even if not used)

HPD0

HDCP Support

NC

IS

TMDS Backdrive Protection

LCD0_BL_EN

LCD0_VDD

PWR_CTL1

Supported straps:

near GPU

Straps not supported:

MIOB_D<7>

MIOA_HSYNC

MIOA_D<5..2>

3GIO_PADCFG3

3GIO_PADCFG2

PEX_PLL_EN_TERM SUBVENDOR

PCI_DEVID<2..0>

(BIOS ROM PRESENT)

76

1/16W

NO STUFF

1K

402

MF-LF

5%

10K

MF-LF

1/16W

5%

402

NO STUFF

10K

402

MF-LF

1/16W

5%

VRAM_128

10K

1/16W

5%

402

MF-LF

402

MF-LF

1/16W

5%

10K

VRAM_SAMSUNG

402

5%

MF-LF

10K

1/16W

10K

402

MF-LF

1/16W

5%

VRAM_256

MF-LF

1/16W

5%

402

10K

NO STUFF

VRAM_HYNIX

402

MF-LF

5%

10K

1/16W

NO STUFF

1K

402

MF-LF

1/16W

5%

1K

5% 1/16W MF-LF

402

NO STUFF

1K

5%

NO STUFF

1/16W MF-LF

402

1K

402

MF-LF

5%

1/16W

NO STUFF

402

5%

1K

1/16W MF-LF

402

5% 1/16W MF-LF

10K

GPU_SS_INT

10K

402

5% 1/16W MF-LF

1/16W MF-LF

402

150

1%

402

1/16W MF-LF

150

1%

150

1% 1/16W MF-LF

402

73 86

1/16W MF-LF

402

150

1%

402

1/16W MF-LF

150

1%

MF-LF

402

150

1% 1/16W

OMIT

QFN

TS3V330

CRITICAL

76 86

0.1UF

CERM

402

20% 10V

10K

5%

402

MF-LF

1/16W

74

65 74

100K

1/16W

402

MF-LF

5%

SI2305DS

SOT-23

CRITICAL

2N7002DW-X-F

SOT-363

10K

1/16W

5%

402

MF-LF

74

HDCP

CERM

402

20%

0.1UF

10V

10K

402

MF-LF

5%

1/16W

HDCP

1/16W

5%

MF-LF

402

10K

73

HDCP

AT88SC080C

SOI

CRITICAL

68 69 70

1/16W

5%

MF-LF

402

1K1K

1/16W

5%

402

MF-LF MF-LF

402

5%

1/16W

1K

77

GPU Straps

72 88

A.0.0

051-7225

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

TS3V330 alt to TS3V340

ALL (U8700)

353S1718353S1579

IC,TS3V340,QUAD VIDEO SW,QFN16

CRITICAL

U8700

1

353S1718

=PP3V3_GPU_MIO

GPU_GPIO_1

GPU_MIOB_D<9>

GPU_GPIO_11

GPU_GPIO_9

GPU_GPIO_7

GPU_GPIO_6

GPU_GPIO_3

MAKE_BASE=TRUE

TP_GPU_GSTATE<0>

=PP3V3_GPU_TMDS

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_I2CA_SDA

GPU_I2CA_SDA

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_I2CA_SCL

GPU_I2CA_SCL

TP_FB_A_MA13

TP_FB_B_MA12

TP_FB_B_MA13

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_FB_A_MA13

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_FB_B_MA12

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_FB_B_MA13GPU_I2CC_SDA

GPU_I2CC_SCL

GPU_I2CB_SDA

GPU_XTALOUT

GPU_SPDIF

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_SPDIF

GPU_STEREO

GPU_XTALSSIN

MAKE_BASE=TRUE

GPU_CLK27M_SS_GATED

GPU_THERMD_P

MAKE_BASE=TRUE

GPU_TDIODE_P

GPU_XTALIN

MAKE_BASE=TRUE

GPU_CLK27M_GATED

MAKE_BASE=TRUE

GPU_PANEL_DDC_CLK

MAKE_BASE=TRUE

GPU_DVI_DDC_CLK

MAKE_BASE=TRUE

GPU_DVI_DDC_DATA

MAKE_BASE=TRUE

GPU_PANEL_DDC_DATA

GPU_TV_Y_VGA_G

GPU_TV_COMP_VGA_B

GPU_TV_C_VGA_R

GPU_HPD

MAKE_BASE=TRUE

NC_GPU_GPIO_1

NO_TEST=TRUE

MAKE_BASE=TRUE

GPU_BL_PWM

MAKE_BASE=TRUE

GPU_BKLT_EN

MAKE_BASE=TRUE

GPU_PANEL_EN

GPU_VGA_EN_L

MAKE_BASE=TRUE

NC_GPU_GPIO_8

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_GPU_GSTATE<1>

MAKE_BASE=TRUE

GPU_VCORE_VID0

GPU_GPIO_14

GPU_GPIO_10

GPU_VCORE_VID2

MAKE_BASE=TRUE

=GPUVCORE_EN

=PP3V3_GPU_TMDS_FET

GPU_TMDS_PWREN_L

GPU_VCORE_PWRCTL0

MAKE_BASE=TRUE

GPU_VCORE_PWRCTL1

TP_FB_A_MA12

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_FB_A_MA12

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_STEREO

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_XTALOUT

GPU_I2CB_SCL

GPU_THERMD_N

MAKE_BASE=TRUE

GPU_TDIODE_N

LVDS_U_DATA_N<3>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_U_DATAN<3>

LVDS_L_DATA_P<3>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_L_DATAP<3>

GPU_CSYNC

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_CSYNC

LVDS_L_DATA_N<3>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_L_DATAN<3>

GPU_MIOA_CLKOUT_P

MAKE_BASE=TRUE

TP_GPU_MIOA_CLKOUT_P

GPU_MIOA_D<7>

MAKE_BASE=TRUE

TP_GPU_MIOA_D<7>

GPU_MIOA_D<5..2>

MAKE_BASE=TRUE

TP_GPU_MIOA_D<5..2>

GPU_MIOA_D<11..10>

MAKE_BASE=TRUE

TP_GPU_MIOA_D<11..10>

GPU_G2

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_G2

GPU_B2

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_B2

GPU_R2

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_R2

GPU_H2SYNC

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_H2SYNC

GPU_MIOA_CLKOUT_N

MAKE_BASE=TRUE

TP_GPU_MIOA_CLKOUT_N

GPU_MIOA_CTL3

MAKE_BASE=TRUE

TP_GPU_MIOA_CTL3

GPU_MIOA_DE

MAKE_BASE=TRUE

TP_GPU_MIOA_DE

GPU_MIOA_HSYNC

MAKE_BASE=TRUE

TP_GPU_MIOA_HSYNC

GPU_V2SYNC

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_V2SYNC

GPU_MIOA_VSYNC

MAKE_BASE=TRUE

TP_GPU_MIOA_VSYNC

GPU_MIOB_CLKOUT_P

MAKE_BASE=TRUE

TP_GPU_MIOB_CLKOUT_P

GPU_MIOB_CLKOUT_N

MAKE_BASE=TRUE

TP_GPU_MIOB_CLKOUT_N

GPU_MIOB_CLKIN

MAKE_BASE=TRUE

TP_GPU_MIOB_CLKIN

LVDS_U_DATA_P<3>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_U_DATAP<3>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_FBA_CMD27

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_FBC_CMD27 TP_FBC_CMD27

TP_FBA_CMD27

TP_FBA_CMD28

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_FBA_CMD28

TP_FBC_CMD28

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_FBC_CMD28

GPU_ROM_SO

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_ROM_SO

GPU_ROM_SI

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_ROM_SI

GPU_ROM_SCLK

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_ROM_SCLK

GPU_ROM_CS_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_ROM_CS_L

GPU_GPIO_13

GPU_I2CH_SDA

=PP3V3_GPU_HDCP

GPU_I2CH_SCL

GPU_VCORE_VID1

MAKE_BASE=TRUE

FB_VREF_UNTERM

MAKE_BASE=TRUE

GPU_VGA_G

GPU_GPIO_8

GPU_VGA_EN_L

GPU_TV_COMP

GPU_TV_Y

GPU_TV_C

GPU_XTALOUTBUFF

GPU_XTALSSIN

GPU_MIOA_D<8>

GPU_MIOB_D<8>

=PP3V3_GPU_MIO

GPU_GPIO_12

GPU_GPIO_2

GPU_GPIO_0

GPU_MIOA_D<1>

GPU_MIOA_D<0>

GPU_MIOB_HSYNC

GPU_VGA_B

GPU_VGA_R

GPU_GPIO_5

GPU_GPIO_4

GPU_MIOB_D<5> GPU_MIOB_D<4>

GPU_MIOB_D<3>

GPU_MIOB_DE

MAKE_BASE=TRUE

TP_GPU_MIOB_DE

GPU_MIOA_D<6>

GPU_MIOB_D<1>

GPU_MIOB_D<0>

=PP3V3_GPU_VIDEOMUX

GPU_MIOA_D<9>

GPU_IFPD_CLK_P

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_IFPD_CLK_P

GPU_IFPD_CLK_N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_IFPD_CLK_N

GPU_MIOB_D<7..6>

MAKE_BASE=TRUE

TP_GPU_MIOB_D<7..6>

GPU_MIOB_D<11..10>

MAKE_BASE=TRUE

TP_GPU_MIOB_D<11..10>

GPU_MIOB_VSYNC

MAKE_BASE=TRUE

TP_GPU_MIOB_VSYNC

GPU_MIOB_D<2>

GPU_MIOB_CTL3

MAKE_BASE=TRUE

TP_GPU_MIOB_CTL3

MAKE_BASE=TRUE

TP_GPU_MIOB_D<2>

R8728

1

2

R8726

1

2

R8724

1

2

R8722

1

2

R8720

1

2

R8727

1

2

R8725

1

2

R8723

1

2

R8721

1

2

R8729

1

2

R8730

1

2

R8731

1

2

R8732

1

2

R8733

1

2

R8781

1

2

R8780

1

2

R8745

1

2

R8744

1

2

R8743

1

2

R8742

1

2

R8741

1

2

R8740

1

2

U8700

4

7

9

12

15

8

1

2

5

11

14

3

6

10

13

17

16

C8700

1 2

R8700

1

2

R8791

1

2

Q8790

3

1

2

Q8925

3

5

4

R8790

1

2

C8770

1 2

R8770

1

2

R8771

1

2

U8770

4

12

3

76

5

8

R8737

1

2

R8735

1

2

R8736

1

2

72

71

72

86

87

86

72

71

8

71

8

73

68

68 73

73

71

30

71 51

71 30

77

76

77

72

71

8

68 73

71

51

73

71

73

71

73

71

73

68

71

8

71

72

71

8

71

8

71

73

71

OUT OUT OUT

OUT OUT

OUT

OUT OUT OUT

OUT

OUT OUT

OUT OUT OUT OUT OUT OUT

BI BI

OUT

IFPA_TXD0

I2CB_SDA

I2CB_SCL

I2CA_SDA

I2CA_SCL

DACC_VSYNC

DACC_HSYNC

DACC_BLUE

DACC_GREEN

DACC_RED

DACB_CSYNC

DACB_BLUE

DACB_GREEN

DACB_RED

DACA_VSYNC

DACA_HSYNC

DACA_BLUE

DACA_GREEN

DACA_RED

IFPD_TXD6

IFPD_TXD5

IFPD_TXD4

IFPD_TXC

IFPC_TXD2

IFPC_TXD1

IFPC_TXD0

IFPC_TXC

IFPB_TXD7

IFPB_TXD6

IFPB_TXD5

IFPB_TXD4

IFPB_TXC

IFPA_TXD3

IFPA_TXD2

IFPA_TXD1

IFPA_TXC

I2CS_SDA

I2CS_SCL

I2CH_SDA

I2CH_SCL

I2CC_SDA

I2CC_SCL

DACC_RSET

DACC_VREF

DACC_IDUMP

DACC_VDD

DACB_RSET

DACB_VREF

DACB_IDUMP

DACB_VDD

DACA_RSET

DACA_VREF

DACA_IDUMP

DACA_VDD

IFPCD_RSET

IFPCD_VPROBE

IFPCD_PLLGND

IFPCD_PLLVDD

IFPD_IOVDD

IFPC_IOVDD

IFPAB_RSET

IFPAB_VPROBE

IFPAB_PLLGND

IFPB_IOVDD

IFPA_IOVDD

IFPAB_PLLVDD

IFPA_TXC_L

IFPA_TXD0_L

IFPA_TXD1_L

IFPA_TXD2_L

IFPA_TXD3_L

IFPB_TXC_L

IFPB_TXD4_L

IFPB_TXD5_L

IFPB_TXD6_L

IFPB_TXD7_L

IFPC_TXC_L

IFPC_TXD0_L

IFPC_TXD1_L

IFPC_TXD2_L

IFPD_TXC_L

IFPD_TXD4_L

IFPD_TXD5_L

IFPD_TXD6_L

OUT OUT

OUT

BI BI BI BI BI BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Page Notes

Power aliases required by this page:

Signal aliases required by this page:

Sum of peak currents: 240mA

20mA peak per diff pair 160mA peak for all pairs

200mA peak for all pairs

20mA peak per diff pair

Place at AD6

BOM options provided by this page:

- =PP3V3_GPU_IFPCD_IOVDD

Sum of peak currents: 390mA

120mA peak

150mA peak

120mA peak

40mA peak

Place at AE7

40mA peak

Place at AF9 Place at AF8

Composite/S-Video VGA Component

Comp B Pb

Y G Y

C R Pr

(NONE)

- =PP1V8_GPU_IFPX

- =PP3V3_GPU_DAC

I2CS must be pulled up if not used I2CS addr fixed at 0x9E,0x9F

NO STUFF

1K

1/16W

1%

402

MF-LF

FERR-220-OHM

0402

CERM

402

10V

0.1UF

20%

0402

FERR-220-OHM

0402

FERR-220-OHM

0402

FERR-220-OHM

NO STUFF

0402

FERR-220-OHM

72 86

77 86

72 86

77 86

7

77 86

7

77 86

7

77 86

72 86

76 86

72

603

6.3V CERM

20%

4.7UF

20%

6.3V CERM 603

4.7UF

72

72 86

OMIT

(5 OF 8)

BGA

NB8P-GS-W-A2

72

1%

124

MF-LF 402

1/16W

1%

124

MF-LF 402

1/16W

1%

124

402

MF-LF

1/16W

72

10V

20%

402

CERM

0.1UF

402

CERM

20% 10V

0.1UF

402

CERM

20% 10V

0.1UF

72

48

CERM 402

10V

0.1UF

20%

402

CERM

10V

0.1UF

20%

4.7UF

603

CERM

6.3V

20%

0.1UF

402

CERM

10V

20%

NO STUFF

20%

6.3V CERM 603

4.7UF4.7UF

603

CERM

6.3V

20%

6.3V 603

CERM

4.7UF

CERM

402

10V

0.1UF

20%

603

6.3V

CERM

20%

4.7UF

FERR-220-OHM

0402

20%

0.1UF

10V

CERM

402

NO STUFF

20% 16V

0.01UF

402

CERM

NO STUFF

20% 16V

0.01UF

402

CERM

20%

0.1UF

10V

CERM

402

CERM

402

10V

0.1UF

20%

4.7UF

CERM

603

6.3V

20%

FERR-220-OHM

0402

CERM

402

10V

0.1UF

20%

NO STUFF

1K

1/16W

1%

402

MF-LF

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

NV G84M Video Interfaces

73 88

A.0.0

051-7225

GPU_VGA_G

GPU_G2 GPU_B2

GPU_I2CC_SDA

GPU_I2CC_SCL

GPU_DACC_RSET

GPU_DACC_VREF

=PP1V8_GPU_IFPX

GPU_IFPAB_VPROBE GPU_IFPCD_VPROBE

GPU_DACB_VREF GPU_DACC_VREF

GPU_DACA_RSET GPU_DACA_VREF

GPU_IFPAB_RSET GPU_IFPCD_RSET

GPU_DACC_RSET

GPU_DACB_RSET

=PP3V3_GPU_IFPCD_IOVDD

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 mm

PP1V8_GPU_IFPAB_IOVDD_F

MIN_LINE_WIDTH=0.4 mm

VOLTAGE=1.8V

PP1V8_GPU_IFPAB_PLLVDD_F

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

PP3V3_GPU_IFPCD_IOVDD_F

MIN_LINE_WIDTH=0.4 mm

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.35 mm

PP3V3_GPU_DACA_VDD_F

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.35 mm

PP3V3_GPU_DACB_VDD_F

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.35 mm

PP3V3_GPU_DACC_VDD_F

=PP3V3_GPU_DAC

LVDS_L_DATA_P<0>

GPU_I2CB_SDA

GPU_I2CB_SCL

GPU_I2CA_SDA

GPU_I2CA_SCL

GPU_V2SYNC

GPU_H2SYNC

GPU_R2

GPU_CSYNC

GPU_TV_COMP

GPU_TV_Y

GPU_TV_C

GPU_VGA_VSYNC

GPU_VGA_HSYNC

GPU_VGA_B

GPU_VGA_R

TMDS_DATA_P<5>

TMDS_DATA_P<4>

TMDS_DATA_P<3>

GPU_IFPD_CLK_P

TMDS_DATA_P<2>

TMDS_DATA_P<1>

TMDS_DATA_P<0>

TMDS_CLK_P

LVDS_U_DATA_P<3>

LVDS_U_DATA_P<2>

LVDS_U_DATA_P<1>

LVDS_U_DATA_P<0>

LVDS_U_CLK_P

LVDS_L_DATA_P<3>

LVDS_L_DATA_P<2>

LVDS_L_DATA_P<1>

LVDS_L_CLK_P

GPU_DACB_RSET

GPU_DACB_VREF

GPU_DACA_RSET

GPU_DACA_VREF

GPU_IFPCD_RSET

GPU_IFPCD_VPROBE

GPU_IFPAB_RSET

GPU_IFPAB_VPROBE

LVDS_L_CLK_N

LVDS_L_DATA_N<0>

LVDS_L_DATA_N<1>

LVDS_L_DATA_N<2>

LVDS_L_DATA_N<3>

LVDS_U_CLK_N

LVDS_U_DATA_N<0>

LVDS_U_DATA_N<1>

LVDS_U_DATA_N<2>

LVDS_U_DATA_N<3>

TMDS_CLK_N

TMDS_DATA_N<0>

TMDS_DATA_N<1>

TMDS_DATA_N<2>

GPU_IFPD_CLK_N

TMDS_DATA_N<3>

TMDS_DATA_N<4>

TMDS_DATA_N<5>

MIN_LINE_WIDTH=0.3 mm VOLTAGE=1.8V

PP1V8_GPU_IFPCD_PLLVDD_F

MIN_NECK_WIDTH=0.2 mm

=GPU_I2CS_SDA

=GPU_I2CS_SCL

GPU_I2CH_SDA

GPU_I2CH_SCL

R8851

1

2

R8850

1

2

L8805

1 2

C8806

1

2

L8815

1 2

L8830

1 2

L8820

1 2

L8840

1 2

C8805

1

2

C8820

1

2

U8000

AH12

AJ12

AF10

AG9

AH11

AH9

AD10

AH10

AK10

T6

U5

T5V7

R6

R7

V8

R5

AE5

AG6

AG7

AG4

AF6

AF5

AD7

AH4

AG5

K2 J3

H4 J4

G2 G1 G3 H3 C1 B1

AF9 AK9

AJ9

AH6 AJ6 AH8 AH7 AJ8 AK8 AJ5 AH5

AD9

AC9

AL5

AM4

AF8

AK4 AL4

AM6 AM5 AM7 AL7 AK6 AK5 AK7 AL8

AD6 AM2

AM3

AE2 AE1 AF1 AF2 AG1 AH1

AB10

AA10

AH3

AK3

AE7

AG3 AH2

AK1 AJ1 AL2 AL1 AJ2 AJ3

R8852

1

2

R8853

1

2

R8854

1

2

C8852

1

2

C8853

1

2

C8854

1

2

C8821

1

2

C8831

1

2

C8830

1

2

C8841

1

2

C8840

1

2

C8845

1

2

C8815

1

2

C8801

1

2

C8800

1

2

L8800

1 2

C8803

1

2

C8856

1

2

C8855

1

2

C8813

1

2

C8811

1

2

C8810

1

2

L8810

1 2

C8816

1

2

73

8

73

73 73

73

8

73

OUT

V-

V+

+

-

THRM_PAD

VFB

TRIP

VOUT

EN_PSV

GND

PGND

V5DRV

V5FILT

DRVL

DRVH

LL

TON

VBST

PGOOD

SYM (2 OF 2)

IN

OUT

G

D

S

G

D

S

G

D

S

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

GPU VCore Current Sense

Req = Rb || Rc || Rd || Re

(=PPVCORE_GPU_REG)

(GPUVCORE_TON)

(GND)

18A max output (L8920 limit)

(GPUVCORE_VFB)

Vout(min) = 0.75V * (1 + Ra / Rb)

(=PPVCORE_GPU_REG)

Vout = 1.25V - 0.96V

Vout = 0.75V * (1 + Ra / Req)

Place near C8940

Y Y Y

1

0

11

1

0

10 0 1

0

VID2

StateC D E

Y - Y Y -

All other states not defined

1.125V (max perf)

1.050V (balanced)

1.050V (rsvd state)

1.050V (max batt)

- - -

VID0VID1

GPU VCore Setpoints

(GPUVCORE_VFB)

<Ra>

GPU VCore Regulator

<Rb>

402

1%

MF-LF

1/16W

2.87K

1/16W MF-LF

1%

402

7.15K

6.3V

20%

10UF

X5R 603

10%

1000pF

X7R

25V 402

NO STUFF

61.9K

402

MF-LF

1/16W

1%

NO STUFF

50V 402

CERM

470pF

10%

49

402

50V

470pF

CERM

10%

402

MF-LF

1M

1%

1/16W

402

1M

1%

MF-LF

1/16W

1uF

CERM 402

10%

6.3V

1%

1/16W

402

MF-LF

20.0K

1/16W

1%

20.0K

402

MF-LF

649

1%

402

MF-LF

1/16W

PLACEMENT_NOTE=Place R8990 close to L8920

1/16W MF-LF

402

1K

1%

NO STUFF

PLACEMENT_NOTE=Place R8994 close to L8920

10%

CERM-X5R

0.47UF

6.3V 402

PLACEMENT_NOTE=Place C8990 close to L8920

0603-LF

10KOHM-5%

CRITICAL

PLACEMENT_NOTE=Place R8997 close to L8920

402

1%

1K

1/16W MF-LF

NO STUFF

CERM

50V 402

100PF

5%

CRITICAL

POLY

20% 25V

22UF

CASE-D2-LF

LFPAK

RJK0305DPB

CRITICAL

RJK0301DPB

LFPAK

RJK0301DPB

LFPAK

CRITICAL

1.0UH-20A

IHLP4040DZ11-SM

CRITICAL

CERM-X5R

0.22UF

6.3V 402

10%

PLACEMENT_NOTE=Place C8991 close to L8920

CRITICAL

SC70-5

HPA00141AIDCKR

200K

1% 1/16W MF-LF 402

20%

402

CERM

0.1UF

10V

0

5%

1/16W

402

MF-LF

1uF

16V X5R 603

10%

QFN

TPS51117RGY_QFN14

CRITICAL

16V

10% X5R

603

2.2UF

SM

65 72

65

1/16W 402

1%

10.5K

MF-LF

1% 1/16W MF-LF

402

200

MF-LF

7.5K

402

5%

1/16W

SOT-363

2N7002DW-X-F

SOT-363

7.5K

1/16W

5%

MF-LF

402

SOT-363

2N7002DW-X-F

1/16W

5%

MF-LF

402

7.5K

72

402

1/16W MF-LF

5%

100K

5%

402

MF-LF

1/16W

100K

72

30.1K

1% 1/16W MF-LF 402

NO STUFF

1% 1/16W MF-LF 402

28K

0.1UF

402

CERM

10V

20%

0.1UF

402

CERM

10V

20%

0.1UF

402

CERM

10V

20%

100K

1/16W MF-LF

402

5%

72

603

10%

1UF

25V X5R

22UF

CASE-D2-LF

25V

20%

POLY

CRITICAL

2.0V

330UF

10%

D2T

TANT

TANT D2T

10%

330UF

2.0V

CRITICAL

SM

72

5%

402

MF-LF

1/16W

1.5K

NO STUFF

402

1/16W MF-LF

5%

1K

NO STUFF

402

MF-LF

4.99K

1/16W

1%

NO STUFF

1/16W MF-LF

402

4.99K

1%

NO STUFF

16V

10%

0.01UF

CERM

402

NO STUFF

402

0.01UF

10%

CERM

16V

NO STUFF

1K

5% 1/16W MF-LF

402

NO STUFF

402

1/16W MF-LF

5%

1K

NO STUFF

1.5K

5% MF-LF

1/16W 402

NO STUFF

1K

MF-LF

5%

402

1/16W

NO STUFF

10K

1/16W

5%

MF-LF

402

NO STUFF

402

MF-LF

5%

1/16W

10K

NO STUFF

MMDT3904XF

SOT-363-LF

NO STUFF

SOT-363-LF

MMDT3904XF

NO STUFF

1% 1/16W MF-LF 402

53.6K

NO STUFF

1% 1/16W MF-LF 402

53.6K

SM

A.0.0

051-7225

8874

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

GPU (G84M) Core Supply

GPUVCORE_VFB

GPUVCORE_VFB_D

=PPVCORE_GPU_REG

GPUVCORE_VFB_C

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUE

GPUVCORE_DRVL

VOLTAGE=1.25V

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.20 mm

PPVCORE_GPU_XW

MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V

MIN_LINE_WIDTH=0.6 mm

GND_GPUVCORE_SGND

GPU_VCORE_VID0_RC

GPU_VCORE_VID2

GPUVCORE_VFB_PC0

GND_GPUVCORE_SGND

GPUVCORE_VFB_PC1

MIN_NECK_WIDTH=0.2 mm

GPUVCORE_LL

MIN_LINE_WIDTH=0.6 mm

SWITCH_NODE=TRUE

PP5V_S5_GPUVCORE_V5FILT

VOLTAGE=5V

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

PC1_DIV

PC1_BIAS

PC0_DIV

PC0_BIAS

=PP1V2_GPU_VCOREPWRCTL

GPU_VCORE_PWRCTL1

PC1_BIAS_B

PC0_BIAS_B

=PP5V_S5_GPUVCORE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.25 mm

GPUVCORE_VBST

GND_GPUVCORE_SGND

GPU_VCORE_VID1

GND_GPUVCORE_SGND

GPUVCORE_VFB_PC1

GPUVCORE_VFB_PC0

GPU_VCORE_VID0

GPUVCORE_TRIP

=PPVIN_GPU_GPUVCORE

MIN_LINE_WIDTH=0.6 mm

GPUVCORE_DRVH

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

GPUVCORE_VFB_E

=GPUVCORE_PGOOD

GND_GPUVCORE_SGND

=GPUVCORE_EN

GPUVCORE_BOOT_R

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

GPUISENS_RC

GPUISENS_POS

GPUISENS_NEG

GPUVCORE_IOUT

=PP3V3R5V_GPU_GPUISENS

GPUISENS_NTC

GND_GPUVCORE_SGND

GPU_VCORE_VID1_RC

GPU_VCORE_VID2_RC

=PP3V3_GPU_VCORELOGIC

GPUVCORE_TON

PVCORE_GPU_NTC

GPU_VCORE_PWRCTL0

R8921

1

2

R8922

1

2

C8940

1

2

C8921

1

2

R8923

1

2

C8998

12

C8992

12

R8998

1 2

R8992

1 2

C8995

1

2

R8993

1 2

R8991

1 2

R8990

1

2

R8994

1 2

C8990

12

R8997

1

2

R8996

1

2

C8920

1

2

C8930

1

2

Q8920

5

4

1 2 3

Q8922

5

4

1 2 3

Q8921

5

4

1 2 3

L8920

1 2

C8991

12

U8995

1

3

4

2

5

R8919

1

2

C8915

1

2

R8915

1

2

C8900

1

2

U8900

13

9

1

7

12

8

6

15

2

11

10

4

14

5

3

C8901

1

2

XW8900

1 2

R8905

1

2

R8901

1

2

R8973

1 2

Q8923

3

5

4

Q8923

6

2

1

R8974

1 2

Q8925

6

2

1

R8975

1 2

R8970

1

2

R8971

1

2

R8924

1

2

R8925

1

2

C8973

1

2

C8974

1

2

C8975

1

2

R8972

1

2

C8932

1

2

C8931

1

2

C8942

1

2 3

C8943

1

23

XW8920

1

2

R8967

1

2

R8962

1

2

R8960

1 2

R8965

1 2

C8961

1 2

C8966

1 2

R8966

1

2

R8961

1

2

R8963

1

2

R8968

1

2

R8964

1 2

R8969

1 2

Q8927

5

3

4

Q8927

2

6

1

R8927

1

2

R8926

1

2

XW8901

1

2

49

8 7

74

8

74

8

74

8

74

8

D

S

G

D

S

IN

SYM_VER-1

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

518S0289

Panel has 2K pull-ups

no-panel case (development).

100K pull-ups are for

LCD (LVDS) INTERFACE

0.001uF

CERM

402

20% 50V

20%

0.001uF

50V

CERM

402

CRITICAL

SM

FERR-250-OHM

0.0022uF

CERM

402

10% 50V

100K

MF-LF

402

5%

1/16W

100K

MF-LF

402

5%

1/16W

SI3443DV

TSOP-LF

2N7002

SOT23-LF

MF-LF

100K

402

5%

1/16W

100K

MF-LF 402

5% 1/16W

402

100K

MF-LF

5%

1/16W

77

MSC-RB30-5-FA

F-RT-SM

CRITICAL

PLACEMENT_NOTE=Place close to connector.

90-OHM-100MA

1210-4SM1

CRITICAL

1210-4SM1

90-OHM-100MA

PLACEMENT_NOTE=Place close to connector.

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

LVDS Display Connector

051-7225

A.0.0

8875

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PP3V3_SW_LCD

VOLTAGE=3.3V

LVDS_L_CLK_CONN_F_N LVDS_L_CLK_CONN_F_P

LVDS_U_CLK_CONN_F_N LVDS_U_CLK_CONN_F_P

=PP3V3_S0_DDC_LCD

LVDS_CONN_DDC_CLK LVDS_CONN_DDC_DATA

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

PP3V3_SW_LCD_UF

LCD_PWREN_L_RC

LCD_PWREN_L

LVDS_L_DATA_CONN_P<0>

LVDS_L_DATA_CONN_N<0>

LVDS_U_DATA_CONN_N<0>

LVDS_L_DATA_CONN_P<2>

LVDS_L_DATA_CONN_N<2>

LVDS_L_DATA_CONN_P<1>

LVDS_L_DATA_CONN_N<1>

LVDS_U_DATA_CONN_P<0>

LVDS_U_DATA_CONN_N<1> LVDS_U_DATA_CONN_P<1>

LVDS_U_DATA_CONN_N<2> LVDS_U_DATA_CONN_P<2>

LVDS_L_CLK_CONN_N

LVDS_L_CLK_CONN_P

LVDS_PANEL_EN

LVDS_U_CLK_CONN_N

LVDS_U_CLK_CONN_P

=PP3V3_S0_LCD

C9010

1

2

C9001

1

2

L9000

C9000

1 2

R9001

R9000

1

2

Q9000

1

2

5

63

4

Q9001

3

1

2

R9094

1

2

R9011

1

2

R9010

1

2

J9000

33

34

1

10 11 12 13 14 15 16 17 18 19

2

20 21 22 23 24 25 26 27 28 29

3

30

4 5 6 7 8 9

L9010

1

2 3

4

L9011

1

2 3

4

87

8

77

8

G

SD

G

SD

SYM_VER-1

G

SD

SYM_VER-1

OUT

IN

OUT

G

S

D

G

S

D

IN

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(Place close to GPU)

TMDS Filtering

(DACB TV Y)

(DACB TV COMP)

(DACB TV C)

(Place close to connector)

ANALOG FILTERING

PLACE CLOSE TO CONNECTOR

VGA SYNC Buffers

(PP5V_S0_DDC)

GPU Isolation / Level-Shift

Isolation required for DVI->ADC Adapter

DVI DDC Current Limit

DVI INTERFACE

(55mA requirement per DVI spec)

514-0278

10K

MF-LF 402

5% 1/16W

10K

MF-LF 402

5% 1/16W

2N7002DW-X-F

SOT-363

2N7002DW-X-F

SOT-363

270K

MF-LF 402

5% 1/16W

50V

5% 402

CERM

100pF

1/16W

5%

402

MF-LF

4.7K

1/16W

5%

402

MF-LF

4.7K

100pF

CERM 402

5% 50V

50V

20%

603

CERM

0.01uF

400-OHM-EMI

SM-1

CRITICALCRITICAL

0.5AMP-13.2V

SM-LF

SOD-123

B0530WXF

50V

5%

402

CERM

100pF

1/16W

5%

402

MF-LF

100

1/16W

5%

402

MF-LF

100

MF-LF

402

5%

1/16W

50V

0.25% 402

CERM

3.3pF

VGA_TERM_FILTER

402

MF-LF

150

1/16W

1%

VGA_TERM_FILTER

1/16W

1%

402

MF-LF

150

VGA_TERM_FILTER

MF-LF

402

1%

1/16W

150

50V

0.25%

402

CERM

3.3pF

CERM 402

0.25% 50V

33

MF-LF

402

5%

1/16W

33

MF-LF

402

5%

1/16W

F-RT-TH-DVI

QH11121-RIG02-4F

CRITICAL

20K

MF-LF 402

5% 1/16W

1/16W

1%

49.9

SIGNAL_MODEL=EMPTY

402

MF-LF

NO STUFF

SIGNAL_MODEL=EMPTY

MF-LF

402

1%

1/16W

NO STUFF

49.9

SIGNAL_MODEL=EMPTY

MF-LF

402

1%

1/16W

NO STUFF

49.9

1/16W

5%

402

MF-LF

0

MF-LF

402

5%

1/16W

SIGNAL_MODEL=EMPTY

1/16W

1%

402

MF-LF

NO STUFF

49.9

1/16W

SIGNAL_MODEL=EMPTY

1%

402

MF-LF

NO STUFF

SM

PLACEMENT_NOTE=Place close to connector.

CRITICAL

370-OHM

0.1uF

CERM

402

20% 10V

0.1uF

CERM

402

20% 10V

PLACEMENT_NOTE=Place close to connector.

MC74VHC1G08

SC70

MC74VHC1G08

SC70

PLACEMENT_NOTE=Place close to connector.

SIGNAL_MODEL=EMPTY

NO STUFF

49.9

MF-LF

402

1/16W

1%

2N7002DW-X-F

SOT-363

270K

MF-LF 402

5% 1/16W

90-OHM-100MA

1210-4SM1

CRITICAL

PLACEMENT_NOTE=Place close to connector.

CRITICAL

1210-4SM1

90-OHM-100MA

PLACEMENT_NOTE=Place close to connector.

CRITICAL

90-OHM-100MA

1210-4SM1

90-OHM-100MA

1210-4SM1

PLACEMENT_NOTE=Place close to connector.

CRITICAL

PLACEMENT_NOTE=Place close to connector.

90-OHM-100MA

1210-4SM1

CRITICAL

90-OHM-100MA

PLACEMENT_NOTE=Place close to connector.

1210-4SM1

24

73 86

72 86

72

2N7002DW-X-F

SOT-363

2N7002DW-X-F

SOT-363

28

72

16V

CERM

402

10%

0.01UF

NO STUFF

16V

0.01UF

10%

402

CERM

10%

402

CERM

NO STUFF

0.01UF

16V

0.01UF

10%

402

CERM

NO STUFF

16V

0.01UF

10%

402

CERM

NO STUFF

CERM

402

10%

0.01UF

16V

NO STUFF

CERM

402

10%

0.01UF

16V

SIGNAL_MODEL=EMPTY

1/16W

1%

402

MF-LF

NO STUFF

49.9

CRITICAL

210MHZ

MEA2010P-SM

OMIT

402

NONE

SHORT

NONE NONE

OMIT

NONE 402

NONE

SHORT

NONE

OMIT

NONE

SHORT

NONE 402

NONE

SHORT

NONE 402

OMIT

402

NONE

SHORT

NONE

OMITOMIT

NONE

SHORT

NONE NONE

402

OMIT

SHORT

NONE

NONE NONE

402

OMIT

NONE

SHORT

NONE NONE

402

1/16W

NO STUFF

49.9

1%

MF-LF

402

MF-LF1/16W

1%

49.9

NO STUFF

402

MF-LF1/16W

1%

49.9

NO STUFF

49.9

1%

1/16W MF-LF

402

NO STUFF

402

MF-LF1/16W

1%

49.9

NO STUFF

402

MF-LF1/16W

1%

49.9

NO STUFF

402

MF-LF

1%

49.9

NO STUFF

1/16W

VGA_TERM_CONN

402

MF-LF

150

1/16W

1%

VGA_TERM_CONN

1/16W MF-LF

1%

150

402

VGA_TERM_CONN

1%

1/16W

150

MF-LF

402

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

DVI Display Connector

76 88

A.0.0

051-7225

TMDS_DATA_N<0>

TMDS_DATA_R0

TMDS_DATA_N<1>

TMDS_DATA_R1

TMDS_DATA_N<2>

VGA_B

VGA_G

VGA_R

=GND_CHASSIS_DVI_BOT

=GND_CHASSIS_DVI_TOP

TMDS_DATA_R2

TMDS_DATA_F_P<2>

GPU_TV_C_VGA_R

TMDS_DATA_N<4>

TMDS_DATA_N<5>

TMDS_CLK_F_N

GPU_TV_Y_VGA_G

TMDS_DATA_F_N<5>

TMDS_DATA_F_P<5>

TMDS_DATA_F_N<0>

=GPU_HPD_ENABLE

GPU_HPD

GPU_DVI_DDC_DATA

GPU_HPD_BILAT

=PP3V3_GPU_DVI

DVI_HOTPLUG_DET

=PP5V_S0_SB_HPD

GPU_DVI_DDC_CLK

DVI_DDC_DATA_R

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

PP5V_S0_DDC_F

VOLTAGE=5V

DVI_DDC_DATA

DVI_DDC_CLK

PP5V_S0_DDC_PULLUPS

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V

=PP5V_S0_DVI_DDC

DVI_HPD_R

VGA_VSYNC

TMDS_CLK_F_P

TMDS_CLK_F_N

TMDS_DATA_F_N<2> TMDS_DATA_F_N<1>

TMDS_DATA_F_N<0>

TMDS_DATA_F_P<2>TMDS_DATA_F_P<0> TMDS_DATA_F_P<1>

TMDS_DATA_F_N<4>

TMDS_DATA_F_P<4>

TMDS_DATA_F_N<5>

TMDS_DATA_F_P<5>

=PP3V3_GPU_VGASYNC

VGA_VSYNC

VGA_VSYNC_R

VGA_HSYNC

VGA_HSYNC_R

TMDS_DATA_F_P<4>

TMDS_DATA_F_N<4>

TMDS_DATA_N<3>

TMDS_DATA_F_P<3>

TMDS_DATA_F_N<3>

TMDS_DATA_F_P<1>

TMDS_DATA_F_N<1>

TMDS_DATA_F_N<2>

TMDS_CLK_F_P

VGA_B

VGA_R

GPU_TV_COMP_VGA_B

VGA_G

=PP3V3_GPU_VGASYNC

TMDS_DATA_F_P<0>

GPU_VGA_HSYNC

GPU_VGA_VSYNC

=PP3V3_GPU_TMDSBIAS

VGA_HSYNC

DVI_HPD

MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V

PP5V_S0_DDC

DVI_DDC_CLK_R

TMDS_DATA_F_P<3>

TMDS_DATA_F_N<3>

=GND_CHASSIS_DVI_BOT

TMDS_CLK_R_N

=PP3V3_GPU_TMDSBIAS

TMDS_DATA_P<0>

TMDS_CLK_P

TMDS_CLK_CMF

TMDS_DATA_P<2>

TMDS_DATA_P<1>

TMDS_DATA_P<3>

TMDS_DATA_R3

TMDS_DATA_R4

TMDS_DATA_R5

TMDS_CLK_N

TMDS_DATA_P<5>

TMDS_DATA_P<4>

TMDS_CLK_R_P

R9421

1

2

R9420

1

2

Q9411

6

2

1

Q9411

3

5

4

R9422

1

2

C9413

1

2

R9412

1

2

R9410

1

2

C9411

1

2

C9410

1

2

L9410

1 2

F9410

1 2

D9410

1 2

C9414

1

2

R9411

1 2

R9413

1 2

R9414

1 2

C9441

1

2

R9442

1

2

R9440

1

2

R9441

1

2

C9442

1

2

C9440

1

2

R9450

1 2

R9451

1 2

J9400

C1

C2

C3

C4

C5AC5B

31

32

33

34

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

3

4

5

6

7

8

9

R9415

1

2

R9486

1

2

R9482

1

2

R9478

1

2

R9473

1 2

R9472

1 2

R9470

1

2

R9466

1

2

L9472

1

2 3

4

C9451

1

2

C9450

1

2

U9450

3

2

1

4

5

U9451

3

2

1

4

5

R9462

1

2

Q9415

6

2

1

R9423

1

2

L9460

1

2 3

4

L9464

1

2 3

4

L9468

1

2 3

4

L9480

1

2 3

4

L9476

1

2 3

4

L9484

1

2 3

4

Q9414

6

2

1

Q9414

3

5

4

C9462

1

2

C9466

1

2

C9470

1

2

C9478

1

2

C9482

1

2

C9486

1

2

C9474

1

2

R9474

1

2

FL9440

27

36

45

18

CX9491

1

2

CX9490

1

2

CX9492

1

2

CX9493

1

2

CX9403

1

2

CX9402

1

2

CX9401

1

2

CX9400

1

2

R9463

12

R9467

12

R9471

12

R9475

12

R9479

12

R9483

12

R9487

12

R9443

1

2

R9445

1

2

R9444

1

2

87

76

87

87 87

87

76

87

76

87

76

87

76

9

76

8

76

76 76

76

8

76

87

76

87

76

8

76

8

76

9

87

8

87

SYM_VER-3

GND

SEL

DB19*

DB18*

DB17*

DB16*

DB15*

DB14*

DB13*

DB12*

DB11*

DB10*

DB9* DH19

DH14

DH13

DH12

DH11

DH10

DH9

DH15 DH16 DH17 DH18

DB4* DB5* DB6* DB7* DB8*

DB0* DB1* DB2* DB3*

DH4

DH3

DH2

DH1

DH0

DH8

DH7

DH6

DH5

DA15 DA16 DA17 DA18 DA19

DA13 DA14

DA12

DA11

DA10

DA5 DA6 DA7 DA8 DA9

DA0 DA1 DA2 DA3 DA4

VDD

G

S D

G

S D

IN

OUT

BIBI

BI

OUT OUT OUT

OUT

OUT OUT OUT OUT OUT OUT

OUT

OUT OUT OUT

IN IN IN IN IN IN IN IN

IN IN IN

IN IN

IN IN IN IN IN IN

IN IN

IN IN IN IN IN IN

IN IN

IN IN IN

IN

OUT

VPG

V2

V4

V3

VREF RST*

CRT

THRM_PAD

GND

PBR*

V1

OUT

G

D

S

G

D

S

IN

V+

V-

1B1

4B2

2B1 2B2 3B1 3B2 4B1

1B2

1A

2A

3A

4A

OE*

S

THRML

PAD

GND

VCC

SYM_VER-2

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Trst = 1.5ms

LTC2900 typical threshold is 93.5% (3.055V, 2.325V, 1.685V, 1.120V)

Mux Select Conditioning

GPU DDC Pass FETs

PGOOD delays are provided.

(Ext. GFX)

(Int. GFX)

NC

(Int. GFX)

Trst = 4.6ms/nF

LO=xB1

HI=xB2

be eliminated if GPIO moved to resume well.

should be before platform reset deasserts). Could

GPU power rails have come up and are valid (which

rails until GPIO switches back to default state and

is on SB core well. Keeps PGOOD looking at non-GPU

NOTE: NAND-gate required if EXTGPU_LVDS_EN GPIO

Alias to 3.3V if not used->

Panel/Backlight Control Mux

NOTE: New H/W and S/W challenge since NB gfx might be powered off if using external GPU. S/W will have to guarantee that the "other" device is ready before a switch can occur. If mux select GPIO is still on a core well, this could mean powering up IG supply will be necessary before going to sleep to keep PGOODs valid.

transitions and ICHx will honor whatever

observed PGOOD will not change during S3

timer. If mux select on resume well, then

for PGOODs to be valid at end of 99 ms SMC

or <99ms PGOOD assertion time is required

and AND-gate is implemented, glitch filter

(32 us). If mux select is on core well

can create an S3 duration of 1 RTC clock

Fast wake condition is worst case. ICHx

NOTE: SEL = LOW selects port B

NC

LVDS I/F Mux

NB LVDS I/F

NC

GPU LVDS I/F

LVDS Data Mux Power Supply

LTC2900 provides programmable reset delay which is required to play nice with ICHx PGOOD circuit

PGOOD Monitor for GPU Rails

470K

1/16W

5% MF-LF

402

CBTV4020

CRITICAL

BGA-LF

2N7002DW-X-F

SOT-363

2N7002DW-X-F

402

CERM

0.1UF

10V

20%

CERM

0.1UF

10V

20%

402

5%

402

MF-LF

1/16W

1K

72

15

75

75 72

15

75 87

72

15

72

15

72

15

28 30 77

9

15 80

73 86

7

73 86

7

73 86

7

73 86

15 80

73 86

34

75

LTC2900

DFN

CRITICAL

1%

124K

402

MF-LF

1/16W

MF-LF

1% 1/16W

402

100K

CERM

402

50V

10%

330PF

402

CERM

10V

20%

0.1UF

28 30 77

1/16W

5%

402

MF-LF

10K

5%

10K

1/16W

402

MF-LF

1/16W

402

MF-LF

10K

5%

2N7002DW-X-F

SOT-363

2N7002DW-X-F

SOT-363

5%

1/16W

0

MF-LF

LVDS_SEL_RESUME

402

LVDS_SEL_CORE

MF-LF

0

1/16W

5%

402

20% 10V

CERM

402

LVDS_SEL_CORE

0.1UF

7

24 28

25

13 24

0

402

5% 1/16W MF-LF

LVDS_SEL_RESUME

LVDS_SEL_CORE

402

5% 1/16W

0

MF-LF

SC70-5

LVDS_SEL_CORE

MC74VHC1G00

402

MF-LF

1/16W

1%

10K

SOT23-6-LF

MAX4236EUTT

CRITICAL

402

10V

0.1UF

20%

CERM

1% 1/16W MF-LF

402

31.6K

20% 10V CERM 402

0.1UF

CERM 402

20% 10V

10V

20%

402

CERM

0.1UF

1/16W

1%

402

MF-LF

15.8K

1/16W

402

MF-LF

1%

15.8K

74CBTLV3257

QFN

CRITICAL

10K

MF-LF 402

5% 1/16W1/16W

5%

402

MF-LF

100K

0.1uF

402

CERM

20% 10V

28K

1/16W 402

MF-LF

1%

MF-LF

71.5K

402

1/16W

1%

LVDS Interface Mux

8877

051-7225

A.0.0

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

GPU_BKLT_EN LVDS_BKLT_EN GPU_BL_PWM

=PP2V5_GPU_LTC2900 PP1V8_GPU

=PP3V3_S0_LVDS_MUX

P2V5_S0_VREF

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.10 mm

PP2V5_S0_LVDS_MUX

VOLTAGE=2.5V

LVDS_U_DATA_P<2>

LVDS_U_CLK_P

LVDS_U_CLK_N

LVDS_U_DATA_N<1>

LVDS_U_DATA_P<1>

LVDS_A_CLK_P

LVDS_B_DATA_P<0>

LVDS_B_DATA_N<2> LVDS_B_DATA_N<0>

LVDS_A_DATA_P<2>

LVDS_A_DATA_P<0>

LVDS_A_DATA_N<0>

LVDS_A_CLK_N

LVDS_A_DATA_P<1>

LVDS_A_DATA_N<1>

LVDS_A_DATA_N<2>

LVDS_B_DATA_P<1>

LVDS_B_DATA_P<2>

LVDS_B_CLK_P

LVDS_B_CLK_N

LVDS_B_DATA_N<1>

LVDS_U_DATA_P<0>

LVDS_U_DATA_N<0>

LVDS_U_DATA_N<2>

LVDS_L_CLK_P LVDS_L_CLK_N

LVDS_L_DATA_N<0> LVDS_L_DATA_P<0> LVDS_L_DATA_P<2>

LVDS_L_DATA_P<1>

LVDS_L_DATA_N<1>

LVDS_L_DATA_N<2>

LVDS_U_DATA_CONN_P<0>

LVDS_U_DATA_CONN_N<2> LVDS_U_DATA_CONN_N<0>

LVDS_L_DATA_CONN_P<0>

LVDS_L_DATA_CONN_N<0>

LVDS_L_CLK_CONN_N

LVDS_L_CLK_CONN_P

LVDS_L_DATA_CONN_P<1>

LVDS_L_DATA_CONN_N<1>

LVDS_L_DATA_CONN_N<2>

LVDS_L_DATA_CONN_P<2>

LVDS_U_DATA_CONN_P<1> LVDS_U_DATA_CONN_N<1>

LVDS_U_CLK_CONN_N LVDS_U_CLK_CONN_P LVDS_U_DATA_CONN_P<2>

LVDSDATAMUX_SEL_GPU_L

PP2V5_S0_LVDS_MUX

LVDSDATAMUX_SEL_GPU_L

LVDSCTRLMUX_SEL_GPU_L

GPU_PGOOD_P1V2_DIV

EXTGPU_LVDS_SEL

EXTGPU_LVDS_EN_QUAL

EXTGPU_LVDS_EN

GPU_PGOOD_VREF

GPU_PGOOD_VPG

PM_ALL_GPU_PGOOD

GPU_PGOOD_CRT

PM_ALL_GPU_PGOOD

LVDS_BKLT_CTL

LVDS_VDD_EN

TP_PM_ALL_GFX_PGOOD

LCDBKLT_PWREN

GPU_PANEL_EN

LCDBKLT_PWM_UNBUF

LVDS_PANEL_EN

LVDSCTRLMUX_SEL_GPU_L

PM_ALL_NBGFX_PGOOD

=PP3V3_S0_LVDS_MUX

PLT_RST_L

=PP3V3_S0_LVDS_MUX

LVDS_DDC_DATA

=GPU_DDC_ENABLE

GPU_PANEL_DDC_CLK

LVDS_CONN_DDC_DATA

MAKE_BASE=TRUE

LVDS_CONN_DDC_CLK

MAKE_BASE=TRUE

=PP3V3_GPU_LVDS_DDC

PP1V25_GPU

PP2V5_S0_LVDS_MUX

EXTGPU_LVDS_EN33_L

GPU_PANEL_DDC_DATA

LVDS_DDC_CLK

PP3V3_GPU

=PP3V3_S0_LVDS_MUX

RSVD_EXTGPU_LVDS_EN

C9550

1

2

C9560

1

2

R9570

1

2

R9571

1

2

U9560

42

3

75

6

911

10

1214

13

15

8117

16

R9560

1

2

R9561

1

2

C9590

1

2

R9590

1

2

R9591

1

2

R9596

1

2

U9550

F1 H1 K1 K3 K4 K6 J7

K9 J10 G10 E10 C10 A10

A8

A7

A5

B4

A2

B1

D1

G1

J1

K2

J4

K5

K7

K8 K10 H10 F10 D10 B10

A9

B7

A6

A4

A3

A1

C1

E1

F2 H2 J2 J3 J5 J6 J8 J9 H9 F9 E9 C9 B9 B8 B6 B5 B3 B2 C2 E2

C5C6D2

D9G2G9H5H6

E3

E8F3F8

Q9570

6

2

1

Q9570

3

5

4

C9593

1

2

C9591

1

2

R9595

1

2

U9590

3

6

5

4

11

2

10

1

9

7

8

R9593

1

2

R9594

1

2

C9595

1

2

C9592

12

R9562

1

2

R9545

1

2

R9544

1

2

Q9540

6

2

1

Q9540

3

5

4

R9541

1 2

R9542

1 2

C9561

12

R9543

1 2

R9563

1 2

U9561

3

2

1

4

5

R9555

1

2

U9555

3

4

1

5

6

2

C9555

12

R9556

1

2

C9556

1

2

77

8

77

8

28

8

77

8

IN

OUT

IN

OUT

SYM_VER-1

OUT

BI BI

OUT

BI

OUT

BI BI

BI

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

516S0412

NC NC

SATA HDD & IR & SIL Flex Connector

Left ALS Connector

are to remove this noise from SATA signals.

NOTE: SATA _UF_ nets cross DDR2 signals and pick up significant noise. Common-mode chokes

White colored version of 518S0369

518S0469

Top-Case Connector

7

45 53

7

53

23 82

25V

10%

402

CERM

0.0047uF

PLACEMENT_NOTE=Place C9660 close to southbridge

25V

10%

402

CERM

0.0047uF

PLACEMENT_NOTE=Place C9661 next to C9660

23 82

25V

10%

402

CERM

0.0047uF

PLACEMENT_NOTE=Place C9665 close to J9660

25V

10%

402

CERM

0.0047uF

PLACEMENT_NOTE=Place C9666 next to C9665

1210-4SM1

90-OHM-100MA

CRITICAL

PLACEMENT_NOTE=Place FL9660 close to J9660

90-OHM-100MA

1210-4SM1

CRITICAL

PLACEMENT_NOTE=Place FL9665 close to southbridge

7

45 46

24 82

48

45 46

53

24 82

53

24 82

CRITICAL

QT500206-L020

M-ST-SM

SC-75

RCLAMP0502B

CRITICAL

24 82

M-RT-SM

BM04B-ACH

CRITICAL

24 82

46

CRITICAL

QT500206-L020

M-ST-SM

Project Specific Connectors

SYNC_MASTER=(M59_SYNC)

SYNC_DATE=08/24/2006

78 88

A.0.0

051-7225

LTALS_OUT

ALS_GAIN

=PP3V3_S3_LTALS

SATA_A_R2D_C_P

SATA_A_R2D_UF_P

SATA_A_R2D_UF_N

SATA_A_D2R_UF_N

SATA_A_D2R_UF_P

SATA_A_D2R_N

SATA_A_D2R_P

SATA_A_R2D_C_N

USB_TPAD_N

=I2C_TOPCASE_SCL

USB_TPAD_P

=I2C_TOPCASE_SDA

=PP3V3_S3_TOPCASE

=PP5V_S3_TOPCASE

SMC_ONOFF_L

USB_BT_N USB_BT_P

KBDLED_ANODE

KBDLED_RETURN

SMC_LID

=PP3V42_G3H_LIDSWITCH

=PP5V_S3_IR

SYS_LED_ANODE

USB_IR_P

SATA_A_D2R_C_N

USB_IR_N

SATA_A_D2R_C_P

SATA_A_R2D_N SATA_A_R2D_P

=PP5V_S0_HDD

J9660

1

10 11 12 13 14 15 16 17 18 19

2

20

3 4 5 6 7 8 9

C9660

1 2

C9661

1 2

C9665

2 1

C9666

2 1

FL9660

1

2 3

4

FL9665

1

2 3

4

J9600

1

10 11 12 13 14 15 16 17 18 19

2

20

3 4 5 6 7 8 9

D9600

3

1

2

J9630

5

6

1 2 3 4

8 7

87

8

82

8

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

(FSB_CPURST_L)

(See above)

specifying a target differential impedance.

Intel says to route with 7 mil spacing without

NOTE: 7 mil gap is for VCCSense pair, which

(See above)

ELECTRICAL_CONSTRAINT_SET

SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.2 & 4.3

All FSB signals with impedance requirements are 55-ohm single-ended.

NOTE: Design Guide allows closer spacing if signal lengths can be shortened.

Design Guide recommends FSB signals be routed only on internal layers.

Worst-case spacing is 2:1 within Data bus, with 3:1 spacing to the DSTBs.

DG recommends at least 25 mils, >50 mils preferred

SPACING

NET_TYPE

PHYSICAL

CPU / FSB Net Properties

(See above)

Worst-case spacing is 2:1 within Addr bus, with 3:1 spacing to the ADSTBs.

DSTB complementary pairs are spaced 1:1 and routed as differential pairs.

NOTE: Design Guide does not indicate FSB spacing to other signals, assumed 3:1.

SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4

Some signals require 27.4-ohm single-ended impedance.

Most CPU signals with impedance requirements are 55-ohm single-ended.

CPU Signal Constraints

Design Guide recommends each strobe/signal group is routed on the same layer.

FSB (Front-Side Bus) Constraints

*

CPU_2TO1

?

=2:1_SPACING

?

*

FSB_DATA

=3:1_SPACING

CPU_ITP

*

?

=2:1_SPACING

=STANDARD=STANDARDY

=55_OHM_SE

*

=55_OHM_SE =55_OHM_SE

CPU_55S

FSB_DATA2DSTB

*

FSB_DATA FSB_DSTB

FSB_ADDRFSB_ADDR

*

FSB_ADDR2ADDR

FSB_DATA

*

FSB_DATA

FSB_DATA2DATA

*

FSB_ADSTB

FSB_ADDR

FSB_ADDR2ADSTB

FSB_COMMON

*

=2:1_SPACING

?

*

=3:1_SPACING

FSB_ADDR

?

FSB_DSTB

*

=3:1_SPACING =3:1_SPACING

?

FSB_DATA2DSTB

*

051-7225

A.0.0

8879

SYNC_MASTER=T9_NOME

CPU/FSB Constraints

SYNC_DATE=01/17/2007

=STANDARD

=55_OHM_SE=55_OHM_SE

*

=55_OHM_SE

=STANDARD

FSB_55S

=55_OHM_SE

*

FSB_ADDR2ADDR

=2:1_SPACING

?

*

FSB_ADSTB

=3:1_SPACING

?

FSB_ADDR2ADSTB

*

=3:1_SPACING

?

25 MIL

*

CPU_VCCSENSE

?

*

CPU_COMP

?

25 MIL 25 MIL

CPU_GTLREF

*

?

=55_OHM_SE=55_OHM_SE

*

=55_OHM_SE

=1:1_DIFFPAIR =1:1_DIFFPAIR

FSB_DSTB_55S

=1:1_DIFFPAIR

7 MIL7 MIL

CPU_27P4S

=27P4_OHM_SE=27P4_OHM_SE=27P4_OHM_SE

Y*

=2:1_SPACING

?

FSB_DATA2DATA

*

CPU_55S

CPU_VID<6..0>

CPU_2TO1

XDP_TDI

CPU_ITPCPU_55S

XDP_TDO

CPU_ITPCPU_55S

XDP_TMS

CPU_ITPCPU_55S

XDP_TCK

CPU_ITPCPU_55S

XDP_TRST_L

CPU_ITPCPU_55S

CPU_55S CPU_ITP

XDP_BPM_L

XDP_BPM_L<4..0>

CPU_27P4S

CPU_VCCSENSE

IMVP6_VSEN_P

CPU_VCCSENSE

IMVP6_VSEN_N

CPU_27P4S

CPU_VCCSENSE

CPU_VCCSENSE_P

CPU_VCCSENSE

CPU_27P4S

CPU_VCCSENSE

CPU_VCCSENSE_N

CPU_VCCSENSE

CPU_55S

CPU_2TO1

IMVP6_VID<6..0>

XDP_CPURST_L

CPU_55S CPU_ITP

CLK_FSB

CLK_FSB_100D

XDP_CLK_P XDP_CLK_N

CLK_FSB_100D

CLK_FSB

XDP_BPM_L<5>

XDP_BPM_L5

CPU_ITPCPU_55S

CPU_2TO1

NB_BSEL<2>

CPU_55S

CPU_COMP

CPU_55S

CPU_COMP

CPU_COMP<3>

CPU_55S

CPU_2TO1

NB_BSEL<0>

CPU_GTLREF

CPU_55S

IMVP_DPRSLPVR

CPU_55S

CPU_2TO1

CPU_55S

PM_DPRSLPVR

CPU_2TO1

PM_DPRSLPVR

FSB_CPUSLP_L

CPU_55S

FSB_CPUSLP_L

PM_THRMTRIP_L

CPU_55S

CPU_2TO1

PM_THRMTRIP_L

CPU_55S

CPU_IGNNE_L

CPU_FROM_SB

CPU_IERR_L

CPU_55S

CPU_IERR_L

CPU_BSEL<2>

CPU_2TO1

CPU_BSEL2

CPU_55S

CPU_BSEL1

CPU_BSEL<1>

CPU_2TO1

FSB_55S

FSB_D_L<47..32>

FSB_DATA_GROUP2

FSB_DATA

FSB_55S

FSB_D_L<31..16>

FSB_DATA

FSB_DATA_GROUP1

FSB_55S

FSB_COMMON

FSB_TRDY_L

FSB_COMMON

FSB_BPRI_L

FSB_55S

FSB_COMMON

FSB_55S

FSB_COMMON

FSB_ADS_L

FSB_COMMON

FSB_DBSY_L

FSB_55S

FSB_COMMON

FSB_BREQ0_L

FSB_55S

FSB_COMMON

FSB_DINV_L<0>

FSB_DATA

FSB_55S

FSB_DATA_GROUP0

FSB_55S

FSB_COMMON

FSB_RS_L<2..0>

FSB_COMMON

FSB_55S

FSB_COMMON

FSB_LOCK_L

FSB_COMMON

FSB_55S

FSB_COMMON

FSB_DRDY_L

FSB_COMMON

FSB_55S

FSB_COMMON

FSB_DPWR_L

FSB_COMMON

FSB_55S

FSB_COMMON

FSB_HITM_L

FSB_COMMON

FSB_55S

FSB_COMMON

FSB_CPURST_L

FSB_55S

FSB_COMMON

FSB_DEFER_L

FSB_COMMON

FSB_REQ_L<4..0>

FSB_55S

FSB_ADDR_GROUP0

FSB_ADDR

FSB_DSTB_55S

FSB_DSTB3

FSB_DSTB

FSB_DSTB_L_P<3>

FSB_DATA

FSB_55S

FSB_DATA_GROUP3

FSB_D_L<63..48>

FSB_DSTB_55S

FSB_DSTB_L_N<0>

FSB_DSTB

FSB_DSTB_55S

FSB_DSTB_L_P<0>

FSB_DSTB

FSB_DSTB0

FSB_55S

FSB_COMMON

FSB_BNR_L

FSB_COMMON

FSB_DATA

FSB_55S

FSB_DATA_GROUP3

FSB_DINV_L<3>

FSB_DSTB_55S FSB_DSTB

FSB_DSTB_L_N<1>

FSB_D_L<15..0>

FSB_DATA

FSB_DATA_GROUP0

FSB_55S

FSB_DSTB_55S

FSB_DSTB_L_P<1>

FSB_DSTB

FSB_DSTB1

FSB_DINV_L<1>

FSB_55S

FSB_DATA

FSB_DATA_GROUP1

FSB_COMMON

FSB_55S

FSB_HIT_L

FSB_COMMON

FSB_55S

FSB_DATA

FSB_DATA_GROUP2

FSB_DINV_L<2>

FSB_DSTB_55S

FSB_DSTB2

FSB_DSTB

FSB_DSTB_L_P<2>

FSB_DSTBFSB_DSTB_55S

FSB_DSTB_L_N<2>

FSB_DSTB_55S FSB_DSTB

FSB_DSTB_L_N<3>

FSB_ADDR

FSB_A_L<16..3>

FSB_55S

FSB_ADDR_GROUP0

FSB_55S

FSB_ADSTB_L<1>

FSB_ADSTB1

FSB_ADSTB

FSB_ADDR

FSB_55S

FSB_ADDR_GROUP1

FSB_A_L<35..17>

FSB_ADSTB0

FSB_ADSTB_L<0>

FSB_ADSTB

FSB_55S

CPU_55S

CPU_FERR_L

CPU_55S

CPU_2TO1

CPU_PROCHOT_L

CPU_PROCHOT_L CPU_PWRGD

CPU_55S

CPU_PWRGD

CPU_FROM_SB

CPU_INTR

CPU_55S

CPU_FROM_SB

CPU_55S

CPU_NMI

CPU_55S

CPU_A20M_L

CPU_FROM_SB

CPU_INIT_L

CPU_55S CPU_55S

CPU_SMI_L

CPU_FROM_SB

CPU_COMP

CPU_COMP<0>

CPU_27P4S

CPU_COMP

CPU_FROM_SB

CPU_STPCLK_L

CPU_55S

CPU_2TO1

CPU_BSEL<0>

CPU_BSEL0

CPU_55S

CPU_DPSLP_L

CPU_FROM_SB

CPU_55S

CPU_COMP<1>

CPU_COMP CPU_COMP

CPU_27P4S

CPU_COMPCPU_COMP

CPU_COMP<2>

CPU_DPRSTP_L

CPU_2TO1

CPU_55S

CPU_DPRSTP_L

CPU_2TO1

CPU_55S

NB_BSEL<1>

58

46

14

23

58

84

30

25

14

23

14

13

14

58

13

47

23

16

30

12

13

58

12

30

13

16

58

16

10

16

23

30

10

14

10

14

10

14

10

23

46

10

23

10

30

10

16

11

10

58

11

7

13

10

13

10

13

10

7

10

7

10

7

10

7

10

7

10

7

10

7

10

7

10

7

13

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

DG Says 30 mil spacing minimum

DG Says 40 mil spacing minimum

Video Signal Constraints

PCI-Express / DMI Bus Constraints

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

SPACING

NET_TYPE

DG Says 40 mil spacing minimum

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 7.2, 9.2 & 10.5

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 8.1 - 8.3.

CRT & TVDAC signal single-ended impedence varies by location:

CRT_HSYNC/CRT_VSYNC signals are 55-ohm +/- 15% single-ended impedence.

- 55-ohm +/- 15% from second termination resistor to connector.

- 50-ohm +/- 15% from first to second termination resistor.

- 37.5-ohm +/- 15% from GMCH to first termination resistor.

LVDS signals are 100-ohm +/- 20% differential impedence.

CRT_SYNC

25 MIL

*

?

*

TVDAC TVDAC

TVDAC_2TVDAC

CRT_SYNC2SYNC

CRT_SYNCCRT_SYNC

*

CRT_50S

=50_OHM_SE

=STANDARD* =STANDARD

=50_OHM_SE =50_OHM_SE=50_OHM_SE

=100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF

DMI_100D

=100_OHM_DIFF

*

=100_OHM_DIFF

*

=100_OHM_DIFF=100_OHM_DIFF

=100_OHM_DIFF

PCIE_100D

=100_OHM_DIFF

SYNC_MASTER=T9_NOME

051-7225

A.0.0

8880

SYNC_DATE=01/17/2007

NB Constraints

=STANDARD* =STANDARD

=55_OHM_SE

CRT_55S

=55_OHM_SE =55_OHM_SE=55_OHM_SE

?

*

PCIE

20 MIL

?

*

TVDAC_2TVDAC

20 MIL

CRT_SYNC2SYNC

?

*

?

*

25 MILCRT

=100_OHM_DIFF

LVDS_100D

*

=100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF

=100_OHM_DIFF

?

*

25 MIL

TVDAC

20 MIL

?

*

CRT_2CRT

?

*

LVDS

20 MIL

*

?

20 MILDMI

*

CRT CRT

CRT_2CRT

TV_A_DAC

CRT_50S

TVDAC

CRT_VSYNC_R

CRT_SYNC

CRT_55S

CRT_SYNC

TV_C_DAC

TVDAC

TV_C_DAC

CRT_50S

TV_B_DAC

TVDAC

TV_B_DAC

CRT_50S

CRT_RED

CRT_50S

CRT

CRT_RED

CRT_GREEN

CRT_50S

CRT

CRT_GREEN

CRT_BLUE

CRT_50S

CRT

CRT_BLUE

CRT_TVO_IREF

CRT

DMI_N2S_N<3..0>

DMI

DMI_100D

DMI_S2N

DMI_S2N_P<3..0>

DMI_100D

DMI

DMI_S2N_N<3..0>

DMI_100D

DMI

LVDS

LVDS_IBG

LVDS_B_DATA_N<3>

LVDS_100D

LVDSLVDS_B_DATA3

PEG_D2R_N<15..0>

PCIE_100D

PCIE

PEG_D2R_C_N<15..0>

PCIE_100D

PEG_R2D_C_N<15..0>

PCIE_100D

PCIE

PEG_R2D_C_P<15..0>

PCIE_100D

PCIE

LVDS_100D

LVDS_A_CLK_N

LVDS_A_CLK

LVDS LVDS

LVDS_100D

LVDS_A_DATA_P<2..0>

LVDS_A_DATA

LVDS

LVDS_100D

LVDS_A_DATA_N<2..0>

LVDS_A_DATA

LVDS_100D

LVDS

LVDS_A_CLK_P

LVDS_A_CLK

PEG_D2R_P<15..0>

PEG_D2R

PCIE_100D

PCIE

PEG_R2D_N<15..0>

PCIE_100D

PCIE

PEG_R2D_P<15..0>

PEG_R2D

PCIE_100D

PCIE

LVDS_100D

LVDS

LVDS_A_DATA_N<3>

LVDS_A_DATA3

LVDS_100D

LVDS

LVDS_A_DATA_P<3>

LVDS_A_DATA3

LVDS

LVDS_B_CLK_P

LVDS_B_CLK

LVDS_100D

LVDS

LVDS_100D

LVDS_B_DATA_P<3>

LVDS_B_DATA3

DMI_N2S_P<3..0>

DMI

DMI_N2S

DMI_100D

PEG_D2R_C_P<15..0>

PCIE_100D

PCIE

CRT_HSYNC_R

CRT_SYNC

CRT_55S

CRT_SYNC

LVDS_100D

LVDS

LVDS_B_CLK_N

LVDS_B_CLK

LVDS

LVDS_B_DATA_P<2..0>

LVDS_B_DATA

LVDS_100D LVDS_100D

LVDS

LVDS_B_DATA_N<2..0>

LVDS_B_DATA

24

22

66

77

66

77

24

77

16

15

66

15

66

15

16

66

15

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEMTABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

DDR2 Memory Bus Constraints

Need to support MEM_*-style wildcards!

PHYSICAL

ELECTRICAL_CONSTRAINT_SET

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2

SPACING

NET_TYPE

Memory Net Properties

MEM_CLK

MEM_DATA

MEM_DATA2MEM

*

?

*

MEM_DATA2DATA

=1.5:1_SPACING

?

=3:1_SPACING

*

MEM_DQS2MEM

*

MEM_CLK

MEM_CTRL2MEM

MEM_CTRL

MEM_DQS

*

MEM_CMD

MEM_CMD2MEM

MEM_CMD2CMD

MEM_CMDMEM_CMD

*

?

=3:1_SPACING

*

MEM_CMD2MEM

?

*

=2:1_SPACING

MEM_CTRL2CTRL

?

*

=3:1_SPACINGMEM_DATA2MEM

MEM_DATA

MEM_CMD2MEM

MEM_CMD

*

SYNC_DATE=01/17/2007

SYNC_MASTER=T9_NOME

Memory Constraints

051-7225

A.0.0

8881

* =STANDARD

=45_OHM_SE

=STANDARD

MEM_45S

=45_OHM_SE=45_OHM_SE=45_OHM_SE

=55_OHM_SE

=STANDARD=STANDARD

MEM_55S

*

=55_OHM_SE=55_OHM_SE=55_OHM_SE

MEM_70D

=70_OHM_DIFF=70_OHM_DIFF*

=70_OHM_DIFF=70_OHM_DIFF =70_OHM_DIFF

=70_OHM_DIFF

MEM_CLK

MEM_CMD2MEM

*

MEM_CMD

MEM_CTRL

*

MEM_CTRL

MEM_CTRL2CTRL

MEM_CTRL

*

MEM_CTRL2MEM

MEM_DATA

MEM_CTRL2MEM

*

MEM_CTRL

MEM_DQS

?

=3:1_SPACING

*

MEM_CTRL2MEM

MEM_CTRL

MEM_DATA2MEM

MEM_DATA

*

MEM_CTRL

MEM_CTRL2MEM

*

MEM_CMD

*

MEM_DATA MEM_DATA

MEM_DATA2DATA

MEM_DQS

*

MEM_DATA

MEM_DATA2MEM

MEM_CMD

*

MEM_DATA

MEM_DATA2MEM

?

MEM_CLK2MEM

=4:1_SPACING

*

MEM_CLK MEM_CLK

MEM_CLK2MEM

*

MEM_DATA

*

MEM_CLK

MEM_CLK2MEM

=85_OHM_DIFF

* =85_OHM_DIFF

=85_OHM_DIFF

MEM_85D

=85_OHM_DIFF

?

*

MEM_2OTHER

25 MIL

* *

MEM_CLK

MEM_2OTHER

MEM_CLK

MEM_CTRL

MEM_CLK2MEM

*

?

=1.5:1_SPACING

*

MEM_CMD2CMD

MEM_DQS

MEM_CLK2MEM

MEM_CLK

*

MEM_CMD

MEM_CLK2MEM

MEM_CLK

*

MEM_CTRL

MEM_CMD2MEM

MEM_CMD

*

MEM_CLK

*

MEM_DQS2MEM

MEM_DQS

MEM_CTRL

*

MEM_DQS2MEM

MEM_DQS

MEM_CMDMEM_DQS

MEM_DQS2MEM

*

MEM_DATA

*

MEM_DQS2MEM

MEM_DQS

MEM_DQSMEM_DQS

MEM_DQS2MEM

** *

MEM_DQS

MEM_2OTHER

**

MEM_DATA

MEM_2OTHER

* *

MEM_CMD

MEM_2OTHER

**

MEM_CTRL

MEM_2OTHER

MEM_CKE<1..0>

MEM_CTRL

MEM_45S

MEM_A_CNTL

MEM_CMDMEM_55S

MEM_A_CAS_L

MEM_A_CMD

MEM_55S

MEM_A_WE_L

MEM_A_CMD

MEM_CMD

MEM_A_DQ<7..0>

MEM_A_DQ_BYTE0 MEM_55S

MEM_DATA

MEM_A_DQ<23..16>

MEM_A_DQ_BYTE2

MEM_DATA

MEM_55S

MEM_A_DQ<15..8>

MEM_A_DQ_BYTE1 MEM_55S

MEM_DATA

MEM_A_DQ<55..48>

MEM_A_DQ_BYTE6

MEM_DATA

MEM_55S

MEM_DATA

MEM_55S

MEM_A_DQ<63..56>

MEM_A_DQ_BYTE7

MEM_A_DM<1>

MEM_DATA

MEM_A_DM1

MEM_55S

MEM_A_DM<0>

MEM_A_DM0

MEM_55S

MEM_DATA

MEM_A_DM<2>

MEM_A_DM2

MEM_DATA

MEM_55S

MEM_A_DM4

MEM_DATA

MEM_55S

MEM_A_DM<4>

MEM_A_DM<3>

MEM_A_DM3

MEM_DATA

MEM_55S

MEM_A_DM6

MEM_DATA

MEM_55S

MEM_A_DM<6>

MEM_85D MEM_DQS

MEM_A_DQS0

MEM_A_DQS_P<0>

MEM_85D MEM_DQS

MEM_A_DQS_N<0>

MEM_85D MEM_DQS

MEM_A_DQS_N<1>

MEM_85D MEM_DQS

MEM_A_DQS1

MEM_A_DQS_P<1>

MEM_85D MEM_DQS

MEM_A_DQS_P<3>

MEM_A_DQS3

MEM_85D MEM_DQS

MEM_A_DQS_P<2>

MEM_A_DQS2

MEM_85D MEM_DQS

MEM_A_DQS_N<2>

MEM_85D MEM_DQS

MEM_A_DQS_P<4>

MEM_A_DQS4

MEM_85D MEM_DQS

MEM_A_DQS_N<3>

MEM_85D MEM_DQS

MEM_A_DQS_N<5>

MEM_85D MEM_DQS

MEM_A_DQS_N<4>

MEM_85D MEM_DQS

MEM_A_DQS_P<5>

MEM_A_DQS5

MEM_85D MEM_DQS

MEM_A_DQS_P<6>

MEM_A_DQS6

MEM_CLK_N<5..3>

MEM_CLKMEM_70D

MEM_B_CNTL

MEM_45S

MEM_CTRL

MEM_CKE<4..3>

MEM_B_CNTL

MEM_CS_L<3..2>

MEM_45S

MEM_CTRL

MEM_B_CMD

MEM_B_A<14..0>

MEM_55S MEM_CMD

MEM_B_CMD

MEM_B_WE_L

MEM_55S MEM_CMD

MEM_B_DQ<15..8>

MEM_B_DQ_BYTE1

MEM_DATA

MEM_55S

MEM_B_DQ<7..0>

MEM_B_DQ_BYTE0 MEM_55S

MEM_DATA

MEM_B_DQ<31..24>

MEM_B_DQ_BYTE3

MEM_DATA

MEM_55S

MEM_B_DQ<23..16>

MEM_B_DQ_BYTE2

MEM_DATA

MEM_55S

MEM_B_DQ<39..32>

MEM_B_DQ_BYTE4

MEM_DATA

MEM_55S

MEM_B_DQ<55..48>

MEM_B_DQ_BYTE6

MEM_DATA

MEM_55S

MEM_B_DQ<47..40>

MEM_B_DQ_BYTE5

MEM_DATA

MEM_55S

MEM_B_DM<0>

MEM_B_DM0

MEM_55S

MEM_DATA

MEM_B_DQ<63..56>

MEM_B_DQ_BYTE7

MEM_DATA

MEM_55S

MEM_B_DM<2>

MEM_B_DM2

MEM_DATA

MEM_55S

MEM_B_DM<1>

MEM_B_DM1

MEM_DATA

MEM_55S

MEM_B_DM<3>

MEM_B_DM3

MEM_DATA

MEM_55S

MEM_B_DM<5>

MEM_B_DM5

MEM_DATA

MEM_55S

MEM_B_DM<4>

MEM_B_DM4

MEM_DATA

MEM_55S

MEM_B_DM<6>

MEM_B_DM6

MEM_DATA

MEM_55S

MEM_B_DM<7>

MEM_B_DM7

MEM_DATA

MEM_55S

MEM_B_DQS_P<0>

MEM_B_DQS0

MEM_85D MEM_DQS

MEM_B_DQS_P<1>

MEM_B_DQS1

MEM_85D MEM_DQS

MEM_B_DQS_N<0>

MEM_85D MEM_DQS

MEM_B_DQS_P<2>

MEM_B_DQS2

MEM_85D MEM_DQS

MEM_B_DQS_N<1>

MEM_85D MEM_DQS

MEM_B_DQS_N<2>

MEM_85D MEM_DQS

MEM_B_DQS_N<3>

MEM_85D MEM_DQS

MEM_B_DQS_P<3>

MEM_B_DQS3

MEM_85D MEM_DQS

MEM_B_DQS_N<4>

MEM_85D MEM_DQS

MEM_B_DQS_P<4>

MEM_B_DQS4

MEM_85D MEM_DQS

MEM_B_DQS_P<5>

MEM_B_DQS5

MEM_85D MEM_DQS

MEM_B_DQS_P<6>

MEM_B_DQS6

MEM_85D MEM_DQS

MEM_B_DQS_N<5>

MEM_85D MEM_DQS

MEM_B_DQS_P<7>

MEM_B_DQS7

MEM_85D MEM_DQS

MEM_B_DQS_N<6>

MEM_85D MEM_DQS

MEM_B_DQS_N<7>

MEM_85D MEM_DQS

MEM_70D MEM_CLK

MEM_CLK_N<2..0>

MEM_CTRL

MEM_45S

MEM_CS_L<1..0>

MEM_A_CNTL

MEM_45S

MEM_CTRL

MEM_ODT<1..0>

MEM_A_CNTL

MEM_CMD

MEM_A_A<14..0>

MEM_A_CMD

MEM_55S

MEM_CMD

MEM_A_BS<2..0>

MEM_A_CMD

MEM_55S

MEM_CMDMEM_55S

MEM_A_RAS_L

MEM_A_CMD

MEM_A_DQ<31..24>

MEM_A_DQ_BYTE3

MEM_DATA

MEM_55S

MEM_A_DQ_BYTE4

MEM_DATA

MEM_55S

MEM_A_DQ<39..32>

MEM_A_DQ_BYTE5

MEM_DATA

MEM_55S

MEM_A_DQ<47..40>

MEM_DATA

MEM_55S

MEM_A_DM7

MEM_A_DM<7>

MEM_A_DM5

MEM_DATA

MEM_55S

MEM_A_DM<5>

MEM_CLKMEM_70D

MEM_A_CLK

MEM_CLK_P<2..0>

MEM_DQSMEM_85D

MEM_A_DQS_N<7> MEM_CLK_P<5..3>

MEM_B_CLK

MEM_CLKMEM_70D

MEM_85D MEM_DQS

MEM_A_DQS_P<7>

MEM_A_DQS7

MEM_85D MEM_DQS

MEM_A_DQS_N<6>

MEM_B_CMD

MEM_B_CAS_L

MEM_55S MEM_CMD

MEM_B_CMD

MEM_B_RAS_L

MEM_55S MEM_CMD

MEM_B_BS<2..0>

MEM_B_CMD

MEM_55S MEM_CMD

MEM_B_CNTL

MEM_ODT<3..2>

MEM_45S

MEM_CTRL

33

32

33

31

33

31

32

17

32

31

17

31

32

31

32

16

17

16

17

16

17

16

17

16

17

16

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.7 & 10.9

HD Audio Interface Constraints

Disk Interface Constraints

USB 2.0 Interface Constraints

DG says minimum spacing 50 mils to clocks

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

SPACING

PHYSICAL

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 10.13.2

Internal Interface Constraints

SOURCE: Napa Platform DG, Rev 0.9 (#17978), Section 10.9.1

SOURCE: Santa Platform DG, Rev 1.0 (#21112), Section 10.17

=STANDARD=STANDARD

=55_OHM_SE=55_OHM_SE

*

=55_OHM_SE

HDA_55S

=55_OHM_SE

=STANDARD=STANDARD

=55_OHM_SE =55_OHM_SE

*

SMB_55S

=55_OHM_SE=55_OHM_SE

* =STANDARD

=55_OHM_SE=55_OHM_SE

=STANDARD

=55_OHM_SE

SATA_55S

=55_OHM_SE

=STANDARD=STANDARD*

SPI_55S

=55_OHM_SE=55_OHM_SE =55_OHM_SE=55_OHM_SE

=55_OHM_SE =55_OHM_SE

=STANDARD =STANDARD

IDE_55S

*

=55_OHM_SE=55_OHM_SE

SYNC_MASTER=T9_NOME

SYNC_DATE=01/17/2007

82 88

A.0.0

051-7225

SB Constraints (1 of 2)

?

*

25 MIL

USB_2CLK

?

20 MIL

*

SATA

USB_90D

*

=90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF

=90_OHM_DIFF =90_OHM_DIFF=90_OHM_DIFF

* =STANDARD =STANDARD

=55_OHM_SE =55_OHM_SE =55_OHM_SE

USB_60S

=55_OHM_SE

?

*

SMB

=3:1_SPACING

?

=1.8:1_SPACING

SPI

*

20 MILUSB

?

*

?

=1.8:1_SPACING

HDA

*

IDE

?

=1.8:1_SPACING

=100_OHM_DIFF

SATA_100D

=100_OHM_DIFF

=100_OHM_DIFF*=100_OHM_DIFF

=100_OHM_DIFF

USB_90D

USB

USB_EXTA_MUXED_P

USB_90D

USB

USB_EXTA_MUXED_N

USB_EXTA

USB_EXTA_P

USB

USB_90D

USB_EXTA_N

USB

USB_90D

SPI_CE_L<1>

SPI

SPI_55S

SPI

SPI_CE_L1

SPI_CE_R_L<1>

SPI_CE_L<0>

SPI

SPI_55S

SPI_CE_R_L<0>

SPI_CE_L0

SPI

SPI_55S

SPI

SPI_55S

SPI_B_SO_R

SPI

SPI_55S

SPI_B_SO

SPI_55S

SPI

SPI_A_SO_R

SPI_SO

SPI_55S

SPI

SPI_B_SI_R

SPI_55S

SPI

SPI_A_SI_R

SPI

SPI_55S

SPI_SI

SPI_55S

SPI

SPI_SI_R

SPI_SI

SPI_55S

SPI

SPI_B_SCLK_R

SPI

SPI_55S

SPI_A_SCLK_R

SPI_55S

SPI

SPI_SCLK

SPI

SPI_55S

SMB_SB_ME_SDA

SMB_ME_DATA

SMB

SMB_55S

SPI_SCLK_R

SPI

SPI_55S

SPI_SCLK

SMB_SB_ME_SCL

SMB_ME_CLK

SMB_55S

SMB

SMB_DATA

SMB_55S

SMB

SMB_SB_SDA

SMB_CLK

SMB_SB_SCL

SMB

SMB_55S

USB_60S

USB_RBIAS

USB

USB_EXTC_N

USB_90D

USB

USB_EXTC

USB_EXTC_P

USB_90D

USB

USB_EXCARD_N

USB_90D

USB

USB_EXCARD

USB_EXCARD_P

USB_90D

USB

USB_EXTB_N

USB_90D

USB

USB_EXTB

USB_EXTB_P

USB

USB_90D

USB_IR_N

USB

USB_90D

USB_IR

USB_IR_P

USB

USB_90D

USB_TPAD_N

USB

USB_90D

USB_TPAD

USB_TPAD_P

USB

USB_90D

USB_BT_N

USB

USB_90D

USB_BT

USB_BT_P

USB

USB_90D

USB_CAMERA_N

USB

USB_90D

USB_CAMERA

USB_CAMERA_P

USB

USB_90D

USB_EXTD_N

USB_EXTD

USB

USB_90D

USB_EXTD_P

USB_90D

USB

USB_MINI_N

USB

USB_90D

USB_MINI

USB_MINI_P

HDA_RST_L

HDA

HDA_RST_L

HDA_55S

HDA_RST_L_R

HDA

HDA_55S

HDA_SDIN0

HDA_55S

HDA

HDA_SDIN0

HDA_55S

HDA_SDIN_CODEC

HDA

SATA_RBIAS

SATA_55S

SATA_RBIAS

SATA_C_D2R_C_P

SATA

SATA_100D

SATA_C_D2R

SATA_100D

SATA_C_D2R_P

SATA

SATA_100D

SATA

SATA_C_R2D_C_N

IDE_PDDACK_L

IDE

IDE_55S

IDE_CNTL

IDE_PDIOR_L

IDE

IDE_55S

HDA

HDA_55S

HDA_BIT_CLK_R

SATA

SATA_100D

SATA_B_R2D_N

SATA_B_D2R

SATA_100D

SATA

SATA_B_D2R_P

SATA_100D

SATA

SATA_A_R2D_C_N

SATA

SATA_100D

SATA_A_R2D

SATA_A_R2D_C_P

SATA_100D

SATA_B_R2D_P

SATA

SATA_B_D2R_N

SATA_100D

IDE

IDE_55S

IDE_PDIORDY

SATA_100D

SATA_A_D2R_C_P

SATA

SATA_100D

SATA_A_D2R_C_N

SATA

IDE

IDE_55S

IDE_RST_L

ODD_RST_5VTOL_L

SATA_100D

SATA

SATA_A_D2R_N

IDE_PDD

IDE

IDE_55S

IDE_PDD<15..0>

SATA_100D

SATA

SATA_B_R2D_C_N

SATA_100D

SATA

SATA_A_R2D_N

SATA

SATA_100D

SATA_A_R2D_P

IDE

IDE_PDA IDE_55S

IDE_PDA<2..0>

SATA

SATA_100D

SATA_A_D2R_P

SATA_A_D2R

IDE

IDE_55S

IDE_IRQ14

IDE_55S

IDE

IDE_CNTL

IDE_PDDREQ

IDE_PDCS

IDE

IDE_55S

IDE_PDCS3_L

IDE_PDCS

IDE

IDE_55S

IDE_PDCS1_L

IDE_CNTL

IDE_55S

IDE

IDE_PDIOW_L

SATA_100D

SATA_B_R2D

SATA_B_R2D_C_P

SATA

HDA_SYNC

HDA

HDA_55S

HDA_SYNC HDA_SYNC_R

HDA

HDA_55S

HDA

HDA_55S

HDA_SDOUT_R

HDA_55S

HDA

HDA_SDOUT

HDA_BIT_CLK

HDA

HDA_55S

HDA_BIT_CLK

SATA_100D

SATA_C_R2D_P

SATA

SATA_100D

SATA

SATA_C_R2D

SATA_C_R2D_C_P

SATA_B_D2R_C_N

SATA_100D

SATA

SATA_B_D2R_C_P

SATA_100D

SATA_C_D2R_C_N

SATA

SATA_100D

SATA

SATA_100D

SATA_C_D2R_N

SATA_100D

SATA_C_R2D_N

SATA

44

43

55

48

55

48

24

34

78

24

44

34

42

78

42

78

42

78

42

34

42

24

55

24

55

24

55

24

55

25

24

25

24

9

24

7

24

23

42

23

78

24

23

78

23

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.18.1 & 10.19

PCI Bus Constraints

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

SPACING

PHYSICAL

Controller Link (AMT) Constraints

SOURCE: Based on Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.27.1.5-7, 10.29 & 10.30

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.27.1.5-7, 10.29 & 10.30

Ethernet (Yukon) Constraints

*

=2:1_SPACING

PCI

?

=55_OHM_SE

=STANDARD

PCI_55S

*

=55_OHM_SE

=STANDARD

=55_OHM_SE=55_OHM_SE

12 MILS

CLINK_VREF

*

?

CLINK_55S

=55_OHM_SE

=STANDARD

=55_OHM_SE

*

=55_OHM_SE=55_OHM_SE

=STANDARD

=1.8:1_SPACING

*

CLINK

?

=100_OHM_DIFF

*

ENET_100D

=100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF

=100_OHM_DIFF

25 MILS

ENET_MDI

*

?

CLINK_12MIL

300 MILS

5 MILS

12 MILS

=STANDARD* =STANDARD

=STANDARD

SB Constraints (2 of 2)

83 88

A.0.0

051-7225

SYNC_MASTER=T9_NOME

SYNC_DATE=01/17/2007

PCIE

PCIE_100D

PCIE_EXCARD_D2R_N

PCIE

PCIE_100D

PCIE_FW_R2D_C_P

PCIE_FW_R2D

PCIE

PCIE_100D

PCIE_EXCARD_D2R_P

PCIE_EXCARD_D2R

PCI

PCI_55S

INT_PIRQC_L

PCI

PCI_55S

INT_PIRQD_L

PCIE_B_R2D

PCIE_100D

PCIE_B_R2D_C_P

PCIE

PCIE_100D

PCIE_EXCARD_R2D_C_P

PCIE_EXCARD_R2D

PCIE_A_D2R_N

PCIE

PCIE_100D

PCIE

PCIE_100D

PCIE_EXCARD_R2D_C_N

PCI_FRAME_L

PCI

PCI_55S

PCI_CNTL

PCI_STOP_L

PCI

PCI_55S

PCI_CNTL

PCI_AD<18..0>

PCI_55S

PCI

PCI_AD

PCI_AD<19>

PCI

PCI_55S

PCI_AD19

PCI_AD<20>

PCI

PCI_55S

PCI_AD20

PCI_PAR

PCI

PCI_55S

PCI_AD

PCI_AD<31..21>

PCI

PCI_55S

PCI_AD

PCI_C_BE_L<3..0>

PCI

PCI_55S

PCI_C_BE_L

PCI_FW_GNT_L

PCI

PCI_55S

PCI_REQ1_L

PCI

PCI_55S

PCI_REQ1_L

PCI_GNT1_L

PCI

PCI_55S

PCI_GNT1_L

PCI

INT_PIRQE_L

PCI_55S

INT_PIRQE_L

PCI

INT_PIRQF_L

PCI_55S

INT_PIRQF_L

PCIE

PCIE_100D

PCIE_A_R2D_C_N

PCI_LOCK_L

PCI

PCI_55S

PCI_LOCK_L

PCI

PCI_55S

PCI_CNTL

PCI_IRDY_L PCI_DEVSEL_L

PCI

PCI_55S

PCI_CNTL

PCI_PERR_L

PCI

PCI_55S

PCI_CNTL

PCI_SERR_L

PCI_55S

PCI

PCI_CNTL

PCI_FW_REQ_L

PCI

PCI_55S

PCI_GNT2_L

PCI

PCI_55S

PCI_GNT2_L

PCI_REQ2_L

PCI

PCI_55S

PCI_REQ2_L

PCIE_100D

PCIE_B_R2D_C_N

PCIE

PCIE_B_D2R_P

PCIE

PCIE_100D

PCIE_B_D2R

PCIE_B_D2R_N

PCIE

PCIE_100D

PCIE

PCIE_FW_R2D_C_N

PCIE

PCIE_100D

PCIE_MINI_D2R_N

PCIE

PCIE_100D

PCIE_MINI_D2R_P

PCIE_MINI_D2R

PCIE_100D

PCIE

PCIE_MINI_R2D_C_N

PCIE_100D

PCIE

PCIE_MINI_R2D_C_P

PCIE_MINI_R2D

PCIE

PCIE_100D

PCIE_FW_D2R_N

PCIE

PCIE_100D

PCIE_FW_D2R_P

PCIE_FW_D2R

PCIE_ENET_R2D_N

PCIE

PCIE_100D

PCIE_ENET_R2D_C_N

PCIE_100D

PCIE

PCIE_ENET_R2D_P

PCIE

PCIE_100D

PCIE_ENET_D2R_N

PCIE

PCIE_100D

PCIE_ENET_D2R_P

PCIE_ENET_D2R

PCIE

PCIE_100D

PCIE_ENET_D2R_C_P

PCIE

PCIE_100D

ENET_MDI

ENET_100D

ENET_MDI

ENET_MDI_P<0>

PCIE

PCIE_100D

PCIE_ENET_D2R_C_N

ENET_MDI ENET_MDI

ENET_MDI_P<1>

ENET_100D

ENET_MDI

ENET_100D

ENET_MDI_N<0>

ENET_MDI_N<2>

ENET_MDI

ENET_100D

ENET_MDI_N<1>

ENET_MDI

ENET_MDI_P<2>

ENET_100D

ENET_MDI

ENET_MDI_N<3>

ENET_MDI

ENET_100D

ENET_MDI

ENET_MDI_P<3>

ENET_MDI

ENET_100D

CLINK_55S

CLINK_NB_CLK

CLINK

CLINK_NB

CLINK_NB_DATA

CLINK_55S

CLINK

CLINK_NB

CLINK

CLINK_WLAN_RESET_L

CLINK_55S

CLINK_VREF

CLINK_12MIL

NB_CLINK_VREF

CLINK_55S

CLINK

CLINK_WLAN

CLINK_WLAN_DATA

CLINK_WLAN_CLK

CLINK_55S

CLINK

CLINK_WLAN

CLINK_NB_RESET_L

CLINK

CLINK_55S

CLINK_NB_RESET_L

GLAN_COMP

PCIE_ENET_R2D_C_P

PCIE

PCIE_100D

PCIE_ENET_R2D

SB_CLINK_VREF1

CLINK_12MIL

CLINK_VREF

SB_CLINK_VREF1

SB_CLINK_VREF0

CLINK_12MIL

CLINK_VREF

SB_CLINK_VREF0

PCI_TRDY_L

PCI

PCI_55S

PCI_CNTL

INT_PIRQA_L

PCI

PCI_55S

INT_PIRQA_L

PCI

PCI_55S

INT_PIRQB_L

PCIE

PCIE_100D

PCIE_A_R2D

PCIE_A_R2D_C_P

PCIE_A_D2R_P

PCIE

PCIE_100D

PCIE_A_D2R

38

34

35

37

25

35

38

34

24

34

24

35

24

35

24

35

16

23

24

25

24

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

(CK505_SRC5)

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

NET_TYPE

SMC SMBus Net Properties

SPACING

(CK505_SRC4) (CK505_SRC4) (CK505_SRC5)

(CK505_SRC8) (CK505_SRC8)

(CK505_SRC3)

(CK505_SRC2)

(CPU_BSEL0)

Clock Net Properties

ELECTRICAL_CONSTRAINT_SET

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 14.1 - 14.6

SPACING

NET_TYPE

(CPU_BSEL2)

(CPU_BSEL0)

PHYSICAL

CK505 PCI5 is project-specific

CK505 PCI4 is project-specific

CK505 SRC7 is project-specific

(CK505_NB)

(CK505_PCIF1)

(CK505_PCIF0)

(CK505_ITP)

(CK505_SRC1) (CK505_SRC1)

(CPU_BSEL2)

(CK505_LVDS) (CK505_LVDS)

(CK505_SRC6)

(CK505_SRC2)

(CK505_PCI3)

(CPU_BSEL2)

(CPU_BSEL0)

(CK505_DOT96)

(CK505_PCI1) (CK505_PCI2)

(CK505_ITP)

(CK505_NB)

(CK505_CPU) (CK505_CPU)

Clock Signal Constraints

SYNC_DATE=01/17/2007

SYNC_MASTER=T9_NOME

84 88

A.0.0

051-7225

Clock & SMC Constraints

CLK_FSB_100D

*

=100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF

?

CLK_MED

*

20 MIL

* =STANDARD

CLK_MED_55S

=55_OHM_SE =55_OHM_SE

=STANDARD

=55_OHM_SE=55_OHM_SE

?

CLK_FSB

*

25 MIL

*

?

CLK_PCIE

20 MIL

=55_OHM_SE

=STANDARD=STANDARD

=55_OHM_SE

*

=55_OHM_SE

CLK_SLOW_55S

=55_OHM_SE

CLK_SLOW

?

*

10 MIL

=100_OHM_DIFF

*

=100_OHM_DIFF=100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFFCLK_PCIE_100D

=100_OHM_DIFF

NB_CLK100M_PCIE_N

CLK_PCIE

CLK_PCIE_100D

CLK_PCIE

CLK_PCIE_100D

PCIE_CLK100M_MINI_N

SMB

SMB_55S

SMBUS_SMC_MGMT_SDA

SMB_55S

SMB

SMBUS_SMC_BSA_SDA

SMB_55S

SMB

SMBUS_SMC_B_S0_SDA

SMB_55S

SMB

SMBUS_SMC_MGMT_SCL

SMB

SMB_55S

SMBUS_SMC_BSA_SCL

SMB_55S

SMB

SMBUS_SMC_0_S0_SDA

SMB

SMB_55S

SMBUS_SMC_0_S0_SCL

SMB

SMB_55S

SMBUS_SMC_B_S0_SCL

SMB_55S

SMB

SMBUS_SMC_A_S3_SCL

SMB_55S

SMB

SMBUS_SMC_A_S3_SDA

SB_CLK100M_SATA_P

CLK_PCIE

CLK_PCIE_100D

SB_CLK100M_SATA_N

CLK_PCIE

CLK_PCIE_100D

NB_CLK100M_PCIE_P

CLK_PCIE

CLK_PCIE_100D

PCIE_CLK100M_MINI_P

CLK_PCIE

CLK_PCIE_100D

PCIE_CLK100M_ENET_P

CLK_PCIE

CLK_PCIE_100D

PCIE_CLK100M_ENET_N

CLK_PCIE

CLK_PCIE_100D

CLK_PCIE

PCIE_CLK100M_EXCARD_N

CLK_PCIE_100D

CLK_MED_55S

CLK_MED

SB_CLK14P3M_TIMER

NB_CLK100M_DPLLSS_P

CLK_PCIE

CLK_PCIE_100D

CK505_FSA

CLK_MED_55S

CLK_MED

FSB_CLK_CPU_P

CLK_FSB

CLK_FSB_100D

CK505_SRC7_P

CLK_PCIE_100D

CLK_PCIE

CK505_SRC7

CLK_FSB_100D

CLK_FSB

CK505_CPU0_P

CK505_CPU

CLK_MED

CLK_MED_55S

CK505_PCIF1_CLK

CK505_PCIF1 CK505_PCI1

CLK_MED

CLK_MED_55S

CK505_PCI1_CLK

CLK_FSB

XDP_CLK_N

CLK_FSB_100D

CK505_SRC3_P

CK505_SRC3

CLK_PCIE

CLK_PCIE_100D

CK505_SRC2_P

CLK_PCIE

CLK_PCIE_100D

CK505_SRC2

CK505_SRC2_N

CLK_PCIE

CLK_PCIE_100D

CK505_DOT96_27M_P

CLK_PCIE

CLK_PCIE_100D

CK505_DOT96

CK505_REF0_FSC

CLK_MED

CLK_MED_55S

CK505_NB CLK_FSB_100D

CK505_CPU1_P

CLK_FSB

CLK_FSB_100D

CK505_CPU0_N

CLK_FSB

CK505_CPU

CLK_FSB_100D

CK505_ITP

CK505_CPU2_ITP_SRC10_N

CLK_FSB

CK505_ITP

CLK_FSB_100D

CLK_FSB

CK505_CPU2_ITP_SRC10_P

CLK_FSB_100D

CK505_CPU1_N

CLK_FSB

CK505_NB

CK505_48M_FSA

CLK_MED

CLK_MED_55S

CLK_PCIE_100D

CLK_PCIE

CK505_DOT96_27M_N

CK505_LVDS_N

CLK_PCIE

CLK_PCIE_100D

CLK_PCIE

CLK_PCIE_100D

CK505_SRC1_N

CK505_PCI5_CLK_FCTSEL

CLK_MED

CK505_PCI5

CLK_MED_55S

CLK_MED

CLK_MED_55S

CK505_PCI4

CK505_PCI4_CLK

CLK_MED

CLK_MED_55S

CK505_PCI3

CK505_PCI3_CLK

CK505_PCI2

CLK_MED

CLK_MED_55S

CK505_PCI2_CLK

CK505_PCIF0_CLK_ITPEN

CLK_MED

CK505_PCIF0 CLK_MED_55S

CK505_SRC1_P

CLK_PCIE

CLK_PCIE_100D

CK505_SRC1

CK505_LVDS_P

CLK_PCIE

CLK_PCIE_100D

CK505_LVDS

CK505_SRC5_P

CLK_PCIE_100D

CK505_SRC5

CLK_PCIE

CK505_SRC3_N

CLK_PCIE

CLK_PCIE_100D

PCI_CLK33M_SB

CLK_MED

CLK_MED_55S

PCI_CLK33M_LPCPLUS

CLK_MED

CLK_MED_55S

PCI_CLK33M_FW

CLK_MED

CLK_MED_55S

PCI_CLK33M_SMC

CLK_MED

CLK_MED_55S

CLK_MED

SB_CLK48M_USBCTLR

CLK_MED_55S

CLK_PCIE_100D

CLK_PCIE

NB_CLK100M_DPLLSS_N

PEG_CLK100M_N

CLK_PCIE

CLK_PCIE_100D

SB_CLK100M_DMI_P

CLK_PCIE

CLK_PCIE_100D

CLK_PCIE

CLK_PCIE_100D

PCIE_CLK100M_EXCARD_P

CLK_PCIE_100D

PEG_CLK100M_P

CLK_PCIE

NB_CLK96M_DOT_N

CLK_PCIE

CLK_PCIE_100D

NB_CLK96M_DOT_P

CLK_PCIE

CLK_PCIE_100D

CLK_PCIE

SB_CLK100M_DMI_N

CK505_FSC

CLK_MED_55S

CLK_MED

PCI_CLK33M_TPM

CLK_MED

CLK_MED_55S

CLK_FSB_100D

CLK_FSB

XDP_CLK_P

FSB_CLK_NB_N

CLK_FSB

CLK_FSB_100D

FSB_CLK_NB_P

CLK_FSB

CLK_FSB_100D

FSB_CLK_CPU_N

CLK_FSB

CLK_FSB_100D

CK505_SRC7_N

CLK_PCIE

CLK_PCIE_100D

CK505_SRC6_N

CLK_PCIE_100D

CLK_PCIE

CLK_PCIE_100D

CK505_SRC5_N

CLK_PCIE

CK505_SRC4_P

CLK_PCIE

CLK_PCIE_100D

CK505_SRC4

CK505_SRC4_N

CLK_PCIE

CLK_PCIE_100D

CK505_SRC6_P

CLK_PCIE_100D

CK505_SRC6

CLK_PCIE

CLK_PCIE_100D

CK505_SRC8_N

CLK_PCIE

CK505_SRC8_P

CLK_PCIE

CK505_SRC8

CLK_PCIE_100D

30

79

47

30

79

30

16

34

30

16

34

35

34

30

22

30

38

45

30

22

30

34

30

14

30

7

30

48

23

7

30

25

7

30

10

29

13

29

24

7

30

25

7

9

24

30

9

7

24

30

13

7

10

29

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

Port 2 Not Used

SPACING

FireWire Net Properties

PHYSICAL

NET_TYPE

ELECTRICAL_CONSTRAINT_SET

FireWire Interface Constraints

SYNC_DATE=01/17/2007

SYNC_MASTER=T9_NOME

85 88

A.0.0

051-7225

FireWire Constraints

*

FW_55S

=55_OHM_SE =55_OHM_SE

=STANDARD =STANDARD

=55_OHM_SE=55_OHM_SE

=110_OHM_DIFF=110_OHM_DIFF

FW_110D

=110_OHM_DIFF=110_OHM_DIFF

=110_OHM_DIFF

*

=110_OHM_DIFF

FW_TP

?

=3:1_SPACING

*

=2:1_SPACING

FW *

?

FW_1_TPA

FW_1_TPA_N

FW_110D

FW_TP

FW_1_TPA

FW_1_TPA_P

FW_110D

FW_TP

CLKFW_PHY_LCLK

CLK_MED_55S

CLK_MED

FW_0_TPB_P

FW_TP

FW_110D

FW_0_TPB

FW_LKON_R

FW

FW_55S

FW_PINT

FW

FW_55S

FW_PINT

FW_0_TPA_P

FW_0_TPA

FW_110D

FW_TP

FW_0_TPB_N

FW_110D

FW_0_TPB

CLK98P304M_FW_XI

CLK_MED_55S

CLK_MED

FW_1_TPB_P

FW_110D

FW_TP

FW_1_TPB

FW_1_TPB_N

FW_110D

FW_TP

FW_1_TPB

FW_0_TPA

FW_TP

FW_110D

FW_0_TPA_N

FW_LKON

FW

FW_55S

FW_D_CTL

FW_CTL<1..0>

FW_55S

FW

CLKFW_LINK_LCLK

CLK_MED_55S

CLK_MEDFW_LCLK

CLKFW_LINK_PCLK

CLK_MED_55S

CLK_MEDFW_PCLK

CLKFW_PHY_PCLK

CLK_MED

CLK_MED_55S

FW_LINK<7..0>

FW

FW_55S

FW_D_CTL

CLK98P304M_FW_XI_R

FWPHY_CLK98P304M_XI

CLK_MED

CLK_MED_55S

FW_LREQ

FW

FW_55S

FW

FW_LPS

41

39

41

39

41

39

38

39

38

39

38

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

GDDR3 Frame Buffer Signal Constraints

G84M Net Properties

PHYSICAL

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

NET_TYPE NET_TYPE

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

GDDR3 FB C/D Net PropertiesGDDR3 FB A/B Net Properties

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

(CK505_DOT96)

SPACING

SPACING SPACING

Video Signal Constraints

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

GPU (G84M) Constraints

86 88

A.0.0

051-7225

=STANDARD=STANDARD

12.7 MM

=50_OHM_SE

*

GDDR3_40R50SE

=40_OHM_SE

=50_OHM_SE

=50_OHM_SE=50_OHM_SE

=STANDARD=STANDARD

=50_OHM_SE

*

GDDR3_50SE

=50_OHM_SE

*

GDDR3_80D

=80_OHM_DIFF =80_OHM_DIFF

=80_OHM_DIFF =80_OHM_DIFF=80_OHM_DIFF

=80_OHM_DIFF

=2.5:1_SPACING

*

GDDR3_DQS

?

TMDS

?

*

20 MIL 20 MILVGA

*

?

VGA_SYNC

?

*

20 MIL

=STANDARD

VGA_55S

* =STANDARD

=55_OHM_SE=55_OHM_SE =55_OHM_SE=55_OHM_SE

=50_OHM_SE

=STANDARD

VGA_50S

=50_OHM_SE

=STANDARD*

=50_OHM_SE=50_OHM_SE

=2.5:1_SPACING

GDDR3_DATA

?

*

?

GDDR3_CMD

=2.5:1_SPACING

*

?

GDDR3_CLK

=100_OHM_DIFF =100_OHM_DIFF

TMDS_100D

=100_OHM_DIFF

*

=100_OHM_DIFF

GPU_CLK27M_GATED

CLK_SLOWCLK_SLOW_55S

GPU_CLK27M_SS_GATED

CLK_SLOWCLK_SLOW_55S

LVDS_L_CLK_P

LVDS_100D

LVDS

FB_B_DQM3

FB_A_DQM_L<7>

GDDR3_50SE GDDR3_DATA

GPU_VGA_HSYNC

VGA_55S

VGA_SYNCVGA_SYNC VGA_SYNC

VGA_55S

GPU_VGA_VSYNC

VGA_SYNC

VGA

VGA_50S

GPU_TV_C

VGA_50S

GPU_TV_Y

VGA

VGA_50S

GPU_TV_COMP

VGA

GPU_VGA_B

VGA

VGA_50S

GPU_VGA_R

VGA

VGA_50S

VGA

GPU_TV_Y_VGA_G

VGA_G_TV_Y

VGA_50S

TMDS_100D

TMDS

TMDS_DATA_P<5..0>

TMDS_DATA

LVDS_L_DATA_P<3..0>

LVDS_100D

LVDS

VGA

GPU_TV_C_VGA_R

VGA_50S

VGA_R_TV_C

TMDS_100D

TMDS_DATA_N<5..0>

TMDS

TMDS_DATA

VGA

GPU_TV_COMP_VGA_B

VGA_B_TV_COMP

VGA_50S

GPU_VGA_G

VGA

VGA_50S

LVDS_U_DATA_N<3..0>

LVDS_100D

LVDS

LVDS_100D

LVDS

LVDS_U_CLK_P

FB_B_DQM1

FB_A_DQM_L<5>

GDDR3_50SE GDDR3_DATA

FB_B_DQ_BYTE2

FB_A_DQ<55..48>

GDDR3_50SE GDDR3_DATA

FB_B_WDQS1

GDDR3_DQS

FB_A_WDQS<5>

GDDR3_50SE

FB_A_DQ<7..0>

FB_A_DQ_BYTE0

GDDR3_50SE GDDR3_DATA

GDDR3_CMD

FB_A_DRAM_RST

GDDR3_40R50SE

FB_AB_CMD_PD

FB_B_WDQS2

GDDR3_DQS

FB_A_WDQS<6>

GDDR3_50SE

FB_B_DQ_BYTE3

FB_A_DQ<63..56>

GDDR3_50SE GDDR3_DATA

FB_B_DQM0

FB_A_DQM_L<4>

GDDR3_50SE GDDR3_DATA

CLK_SLOW_55S

GPU_CLK27M

CLK_SLOW

FB_A_DQM3

FB_A_DQM_L<3>

GDDR3_50SE GDDR3_DATA

FB_AB_CMD GDDR3_CMD

FB_A_MA<1..0>

GDDR3_40R50SE

FB_A_WDQS0

GDDR3_DQS

FB_A_WDQS<0>

GDDR3_50SE

FB_A_UMA<5..2>

GDDR3_CMD

GDDR3_50SE

FB_B_CMD

FB_A_RDQS<3>

FB_A_RDQS3

GDDR3_DQS

GDDR3_50SE

FB_A_DQ<15..8>

FB_A_DQ_BYTE1

GDDR3_50SE GDDR3_DATA

FB_A_DQ<23..16>

FB_A_DQ_BYTE2

GDDR3_50SE GDDR3_DATA

FB_A_DQ<31..24>

FB_A_DQ_BYTE3

GDDR3_50SE GDDR3_DATA

FB_B_DQ<15..8>

FB_C_DQ_BYTE1

GDDR3_50SE GDDR3_DATA

FB_B_DQM_L<1>

FB_C_DQM1

GDDR3_50SE GDDR3_DATA

FB_B_DQM_L<2>

FB_C_DQM2

GDDR3_50SE GDDR3_DATA

FB_D_RDQS0

GDDR3_DQS

FB_B_RDQS<4>

GDDR3_50SE

FB_B_LMA<5..2>

GDDR3_CMD

FB_C_CMD

GDDR3_50SE

FB_B_UMA<5..2>

GDDR3_CMD

FB_D_CMD

GDDR3_50SE

FB_C_RDQS0

GDDR3_DQS

FB_B_RDQS<0>

GDDR3_50SE

FB_A_DQM_L<6>

GDDR3_50SE GDDR3_DATA

FB_B_DQM2

FB_B_DQ_BYTE0

FB_A_DQ<39..32>

GDDR3_50SE GDDR3_DATA

FB_B_DQ_BYTE1

FB_A_DQ<47..40>

GDDR3_50SE GDDR3_DATA

FB_B_RDQS2

GDDR3_DQS

FB_A_RDQS<6>

GDDR3_50SE

FB_B_RDQS3

GDDR3_DQS

FB_A_RDQS<7>

GDDR3_50SE

FB_B_RDQS0

GDDR3_DQS

FB_A_RDQS<4>

GDDR3_50SE

FB_B_RDQS1

GDDR3_DQS

FB_A_RDQS<5>

GDDR3_50SE

FB_B_WDQS3

GDDR3_DQS

FB_A_WDQS<7>

GDDR3_50SE

GDDR3_DQS

FB_B_WDQS0

FB_A_WDQS<4>

GDDR3_50SE

FB_A_DQM1

FB_A_DQM_L<1>

GDDR3_50SE GDDR3_DATA

FB_A_DQM2

FB_A_DQM_L<2>

GDDR3_50SE GDDR3_DATA

FB_A_DQM0

FB_A_DQM_L<0>

GDDR3_50SE GDDR3_DATA

FB_A_RDQS2

GDDR3_DQS

FB_A_RDQS<2>

GDDR3_50SE

FB_A_RDQS0

FB_A_RDQS<0>

GDDR3_DQS

GDDR3_50SE

FB_A_RDQS1

GDDR3_DQS

FB_A_RDQS<1>

GDDR3_50SE

FB_A_WDQS<2>

FB_A_WDQS2

GDDR3_DQS

GDDR3_50SE

FB_A_WDQS3

GDDR3_DQS

FB_A_WDQS<3>

GDDR3_50SE

FB_A_WDQS1

GDDR3_DQS

FB_A_WDQS<1>

GDDR3_50SE

GDDR3_CMD

FB_A_CAS_L

FB_AB_CMD

GDDR3_40R50SE

GDDR3_CMDFB_AB_CMD

FB_A_MA<11..6>

GDDR3_40R50SE

GDDR3_CLK

FB_B_CLK_N<0>

GDDR3_80D

GDDR3_CLK

FB_B_CLK_P<0>

FB_C_CLK_P

GDDR3_80D

GDDR3_CLK

FB_B_CLK_P<1>

FB_D_CLK_P

GDDR3_80D

GDDR3_CLK

FB_B_CLK_N<1>

GDDR3_80D

GDDR3_CMD

FB_B_MA<1..0>

FB_CD_CMD

GDDR3_40R50SE

GDDR3_CMD

FB_B_BA<2..0>

FB_CD_CMD

GDDR3_40R50SE

GDDR3_CMD

FB_B_MA<11..6>

FB_CD_CMD

GDDR3_40R50SE

GDDR3_CMD

FB_B_RAS_L

FB_CD_CMD

GDDR3_40R50SE

GDDR3_CMD

FB_B_WE_L

FB_CD_CMD

GDDR3_40R50SE

GDDR3_CMD

FB_B_CAS_L

FB_CD_CMD

GDDR3_40R50SE

GDDR3_CMD

FB_B_CS0_L

FB_CD_CMD

GDDR3_40R50SE

FB_CD_CMD_PD

GDDR3_CMD

FB_B_CKE

GDDR3_40R50SE

FB_CD_CMD_PD

GDDR3_CMD

FB_B_DRAM_RST

GDDR3_40R50SE

FB_C_WDQS0

GDDR3_DQS

FB_B_WDQS<0>

GDDR3_50SE

FB_C_WDQS1

GDDR3_DQS

FB_B_WDQS<1>

GDDR3_50SE

FB_C_WDQS3

GDDR3_DQS

FB_B_WDQS<3>

GDDR3_50SE

FB_C_WDQS2

GDDR3_DQS

FB_B_WDQS<2>

GDDR3_50SE

FB_C_RDQS1

GDDR3_DQS

FB_B_RDQS<1>

GDDR3_50SE

FB_C_RDQS3

GDDR3_DQS

FB_B_RDQS<3>

GDDR3_50SE

FB_C_RDQS2

GDDR3_DQS

FB_B_RDQS<2>

GDDR3_50SE

FB_C_DQM0

FB_B_DQM_L<0>

GDDR3_50SE GDDR3_DATA

FB_B_DQM_L<3>

FB_C_DQM3

GDDR3_50SE GDDR3_DATA

FB_D_WDQS0

GDDR3_DQS

FB_B_WDQS<4>

GDDR3_50SE

FB_D_WDQS1

GDDR3_DQS

FB_B_WDQS<5>

GDDR3_50SE

FB_D_WDQS3

GDDR3_DQS

FB_B_WDQS<7>

GDDR3_50SE

FB_D_WDQS2

GDDR3_DQS

FB_B_WDQS<6>

GDDR3_50SE

FB_D_RDQS1

FB_B_RDQS<5>

GDDR3_DQS

GDDR3_50SE

FB_D_RDQS3

GDDR3_DQS

FB_B_RDQS<7>

GDDR3_50SE

FB_D_RDQS2

GDDR3_DQS

FB_B_RDQS<6>

GDDR3_50SE

FB_B_DQ<47..40>

FB_D_DQ_BYTE1

GDDR3_50SE GDDR3_DATA

FB_B_DQ<39..32>

FB_D_DQ_BYTE0

GDDR3_50SE GDDR3_DATA

FB_B_DQ<55..48>

FB_D_DQ_BYTE2

GDDR3_50SE GDDR3_DATA

FB_B_DQ<63..56>

FB_D_DQ_BYTE3

GDDR3_50SE GDDR3_DATA

FB_B_DQM_L<4>

FB_D_DQM0

GDDR3_50SE GDDR3_DATA

FB_B_DQM_L<6>

FB_D_DQM2

GDDR3_50SE GDDR3_DATA

FB_B_DQM_L<5>

FB_D_DQM1

GDDR3_50SE GDDR3_DATA

FB_B_DQM_L<7>

FB_D_DQM3

GDDR3_50SE GDDR3_DATA

GDDR3_CLK

FB_A_CLK_N<1>

GDDR3_80D

FB_AB_CMD GDDR3_CMD

FB_A_RAS_L

GDDR3_40R50SE

GDDR3_CMD

FB_AB_CMD_PD

FB_A_CKE

GDDR3_40R50SE

FB_AB_CMD

FB_A_CS0_L

GDDR3_CMD

GDDR3_40R50SE

FB_B_DQ<7..0>

FB_C_DQ_BYTE0

GDDR3_50SE GDDR3_DATA

FB_B_DQ<23..16>

FB_C_DQ_BYTE2

GDDR3_50SE GDDR3_DATA

FB_B_DQ<31..24>

FB_C_DQ_BYTE3

GDDR3_50SE GDDR3_DATA

FB_A_LMA<5..2>

GDDR3_CMD

FB_A_CMD

GDDR3_50SE

GDDR3_CMDFB_AB_CMD

FB_A_WE_L

GDDR3_40R50SE

FB_AB_CMD GDDR3_CMD

FB_A_BA<2..0>

GDDR3_40R50SE

FB_B_CLK_P

FB_A_CLK_P<1>

GDDR3_CLKGDDR3_80D

GDDR3_CLK

FB_A_CLK_N<0>

GDDR3_80D

GDDR3_CLK

FB_A_CLK_P<0>

FB_A_CLK_P

GDDR3_80D

CK505_CLK27MSS

GPU_CLK27M_SS

CLK_SLOWCLK_SLOW_55S

LVDS_L_CLK_N

LVDS_100D

LVDS

LVDS_100D

LVDS_L_DATA_N<3..0>

LVDS

LVDS_100D

LVDS

LVDS_U_CLK_N

LVDS_100D

LVDS

LVDS_U_DATA_P<3..0>

TMDS_100D

TMDS

TMDS_CLK_P

TMDS_CLK

TMDS_100D

TMDS

TMDS_CLK_N

TMDS_CLK

77

73

77

73

77

72

77

69

76

73

76

72

76

73

77

69

70

69

70

69

70

69

77

72

77

73

76

30

73

68

73

72

73

7

72

73

72

73

68

30

68

30

73

7

73

72

73

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Allow 0.127 mm necks for >0.127 mm lines for GMCH fanout.

Memory Constraint Relaxations

Allow 0.1 mm necks for >0.1 mm lines between thru-hole SO-DIMM pins.

(VGA_SYNC) (VGA_SYNC)

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

SPACING

NET_TYPE

M75 Specific Net Properties

(PCIE_MINI)

(PCIE_EXCARD)

(SATA_A_D2R)

(SATA_A_R2D)

(USB_CAMERA) (USB_CAMERA)

(USB_EXTD)

(USB_EXTA)

(VGA_B_TV_COMP)

(VGA_G_TV_C)

(VGA_R_TV_Y)

(VGA_SYNC)

Graphics Constraint Relaxations

Alternate diffpair width/gap through BGA fanout areas (95-ohm diff)

SIM Card Constraints

I118

I119

=50_OHM_SE

=50_OHM_SE=50_OHM_SE=50_OHM_SE

WWAN_SIM

*

=50_OHM_SE

ISL4,ISL10

0.100 MM

2.54 MMMEM_85D

LVDS_100D

100_DIFF_BGA

BGA

2.54 MM

ISL10

0.100 MM

MEM_70D

6.35 MMMEM_70D

0.127 MM

BOTTOM

MEM_45S

0.100 MM

2.54 MM

*

GND_P2MM

LVDS

GND

*

SB_POWER PWR_P2MM

*

USB

SATA

SB_POWER

*

PWR_P2MM

GND_P2MM

*

USB GND

PWR_P2MM

*

DMI

SB_POWER

PWR_P2MMCLK_PCIE SB_POWER

*

SATA

*

GND

GND_P2MM

*

GND

PCIE

GND_P2MM

DMI

*

GND

GND_P2MM

*

GND

CLK_PCIE

GND

*

CLK_MED

GND_P2MM

CLINK_VREF

GND

*

GND_P2MM

*

MEM_DQS

PP1V8_MEM

PWR_P2MM

*

MEM_DATA

PP1V8_MEM

*

PP1V8_MEM

MEM_CTRL PWR_P2MM

PWR_P2MM

MEM_CLK

*

PP1V8_MEM PP1V8_MEM

PWR_P2MM

MEM_CMD

*

GND

*

MEM_DQS

GND_P2MM

*

GND

MEM_DATA GND_P2MM

*

GND

GND_P2MMMEM_CTRL

MEM_CMD

GND_P2MM

GND

*

MEM_CLK

*

GND

GND_P2MM

PP1V8_MEM

*

=STANDARD

?

0.20 MM

1000

*

GND_P2MM

1000

*

PWR_P2MM

0.20 MM

?

=STANDARD

GND

*

GND_P2MM

*

FW_POWER

CLK_MED

GND_P2MM

*

GND

ENET_MDI ENET_MDI

*

ENET_POWER

PWR_P2MM

FSB_DSTB

GND

*

GND_P2MM

CPU_VCCSENSE

GND_P2MM

GND

*

CPU_GTLREF

*

GND

GND_P2MM

CLK_FSB

GND

*

GND_P2MM

CPU_COMP

GND

*

GND_P2MM

?

*

SENSE

=2:1_SPACING

?

*

=2:1_SPACING

THERM

=1:1_DIFFPAIR

=55_OHM_SE

=1:1_DIFFPAIR=1:1_DIFFPAIR

=55_OHM_SE

*

=55_OHM_SE

SENSE_1TO1_55S

=1:1_DIFFPAIR

=1:1_DIFFPAIR=1:1_DIFFPAIR

=55_OHM_SE

*

=55_OHM_SE=55_OHM_SE

THERM_1TO1_55S

?

*

25 MILS

ENETCONN

?

*

WWAN_SIM

=2:1_SPACING

TMDS_100D

100_DIFF_BGA

BGA

051-7225

A.0.0

8887

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

Project Specific Constraints

VGA_SYNC

VGA_55S

VGA_HSYNC

SB_POWER

PP3V3_S0

WWAN_SIM_CLOCK

WWAN_SIM WWAN_SIM

WWAN_SIM_DATA

WWAN_SIM WWAN_SIM

PCIE

PCIE_EXCARD_R2D_P

PCIE_100D PCIE_100D

PCIE

PCIE_EXCARD_R2D_N

PCIE

PCIE_100D

PCIE_MINI_R2D_N

PCIE_100D

PCIE_MINI_R2D_P

PCIE

ENET_MDI

ENET_100D

ENET_MDI_R_P<3..0>

ENETCONN

ENET_100D

ENETCONN_P<3..0>

ENET_MDI

ENET_100D

ENET_MDI_R_N<3..0>

FW_110D

FW_PORT0_TPA_FL_P

FW_TP

ENET_100D

ENETCONN

ENETCONN_N<3..0>

FW_110D

FW_TP

FW_PORT0_TPA_FL_N

FW_110D

FW_TP

FW_PORT0_TPB_FL_P

FW_110D

FW_TP

FW_PORT0_TPB_FL_N

SATA

SATA_100D

SATA_A_R2D_UF_P

SATA

SATA_100D

SATA_A_R2D_UF_N

SATA

SATA_100D

SATA_A_D2R_UF_P

SATA

SATA_100D

SATA_A_D2R_UF_N

USB_90D

USB

USB2_EXTA_MUXED_P

USB

USB_90D

USB2_EXTA_MUXED_N

USB

USB_90D

USB2_RT_P

USB

USB_90D

USB2_RT_N

USB_90D

USB

USB_WWAN_F_P

USB_90D

USB

USB_WWAN_F_N

USB

USB_90D

USB_CAMERA_F_P

SENSE_1TO1_55S

GFXIMVP6_VSEN_P

SENSE_DIFFPAIR

SENSE

USB_CAMERA_F_N

USB

USB_90D

SENSE_1TO1_55S

NBCOREISNS_P

SENSE

SENSE_DIFFPAIR

SENSE_1TO1_55S

P1V8ISNS_P

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_55S

P1V25ISNS_P

SENSE

SENSE_DIFFPAIR

THERM_1TO1_55S

CPUTHMSNS_D2_P

THERM

THERM_DIFFPAIR

THERM_1TO1_55S

CPU_THERMD_P

THERM_DIFFPAIR

THERM

THERM_1TO1_55S

GPU_TDIODE_P

THERM_DIFFPAIR

THERM

THERM_1TO1_55S

GPUTHMSNS_D_P

THERM_DIFFPAIR

THERM

THERM_1TO1_55S

REMTHMSNS_DX_P

THERM

THERM_DIFFPAIR

THERM_1TO1_55S

HSTHMSNS_D_P

THERM_DIFFPAIR

THERM

THERM_1TO1_55S

RSFSTHMSNS_D_P

THERM_DIFFPAIR

THERM

LVDS_L_CLK_CONN_F_P

LVDS

LVDS_100D

LVDS_L_CLK_CONN_F_N

LVDS

LVDS_100D

LVDS_L_CLK_CONN_N

LVDS_100D

LVDS

LVDS_L_CLK_CONN_P

LVDS_100D

LVDS

LVDS_L_DATA_CONN_N<3..0>

LVDS_100D

LVDS

LVDS_100D

LVDS_L_DATA_CONN_P<3..0>

LVDS_U_CLK_CONN_P

LVDS

LVDS_100D

LVDS_U_DATA_CONN_P<3..0>

LVDS

LVDS_U_CLK_CONN_N

LVDS_100D

LVDS

LVDS_100D

LVDS_U_DATA_CONN_N<3..0>

TMDS_100D

TMDS

TMDS_CLK_R_P

TMDS

TMDS_100D

TMDS_CLK_R_N

TMDS

TMDS_100D

TMDS_CLK_F_P

TMDS_100D

TMDS

TMDS_CLK_F_N

TMDS_DATA_F_N<5..0>

TMDS

TMDS_100D

TMDS_DATA_F_P<5..0>

TMDS

TMDS_100D

VGA_50S

VGA

VGA_G

VGA_50S

VGA

VGA_R

VGA_50S

VGA

VGA_B

VGA_55S

VGA_SYNC

VGA_HSYNC_R

VGA_SYNC

VGA_55S

VGA_VSYNC_R

VGA_SYNC

VGA_55S

VGA_VSYNC

=PP1V8_S3M_MEM_A

PP1V8_MEM

=PP1V8_S3M_MEM_B

PP1V8_MEM

PP3V3_S5

SB_POWER

PP1V5_S0

GND

65

51

72

51

77

31

32

76

8

44

34

37

41

37

41

78

43

44

59

44

50

7

10

51

7

75

76

8

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_BOARD_INFO

VERSION

ALLEGRO

(MIL or MM)

BOARD UNITS

BOARD LAYERS

BOARD AREAS

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

M75 Board-Specific Spacing & Physical Constraints

NOTE: 100_DIFF_BGA is 100-ohms differential impedance on outer layers and 95-ohms on inner layers.

BGA

BGA_P2MM

CLK_MED

*

BGA

BGA_P2MM

*

CLK_FSB

BGA

*

BGA_P2MM

MEM_CLK

BGA

BGA_P1MM

* *

BGA

CLK_PCIE

*

BGA_P2MM

?

*

3:1_SPACING

0.3 MM

2.5:1_SPACING

?

*

0.25 MM

?

*

0.15 MM

1.5:1_SPACING

0.18 MM

?

*

1.8:1_SPACING

BGA

FSB_DSTB BGA_P3MMFSB_DSTB

BGA

BGA_P2MM

*

CLK_SLOW

15.5.1

MM

NO_TYPE,BGA

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

STANDARD

*

=DEFAULT

?

=DEFAULT

?

BGA_P1MM

*

=DEFAULT

?

BGA_P3MM

=DEFAULTBGA_P2MM

?

*

0.1 MM

*

DEFAULT

?

TOP,BOTTOM

110_OHM_DIFF

Y

0.330 MM 0.330 MM

0.089 MM 0.089 MM

=STANDARD=STANDARD =STANDARD

*

110_OHM_DIFF

=STANDARD=STANDARDN

Y

0.330 MM 0.330 MM

110_OHM_DIFF

ISL2,ISL11

0.089 MM 0.089 MM

110_OHM_DIFF

0.330 MM0.330 MM

0.077 MM0.077 MM

Y

ISL3,ISL4

110_OHM_DIFF

0.330 MM0.330 MM

0.077 MM0.077 MM

Y

ISL9,ISL10

0.220 MM0.220 MM

0.130 MM0.130 MM

Y

ISL2,ISL11

90_OHM_DIFF

Y

ISL2,ISL11

80_OHM_DIFF

0.125 MM0.125 MM

0.140 MM0.140 MM

0.125 MM

0.101 MM0.101 MM

ISL3,ISL4

85_OHM_DIFF

Y

0.125 MM

=STANDARD=STANDARD

*

=STANDARD

N

80_OHM_DIFF

=STANDARD =STANDARD

0.125 MM

0.185 MM0.185 MM

70_OHM_DIFF

Y

0.125 MM

TOP,BOTTOM

=STANDARD

N =STANDARD =STANDARD

=STANDARD

70_OHM_DIFF

*

=STANDARD

0.240 MM0.240 MM

=STANDARD

27P4_OHM_SE

=STANDARDY*

Y

TOP,BOTTOM

40_OHM_SE

0.185 MM 0.185 MM

0.335 MM0.335 MM

27P4_OHM_SEYTOP,BOTTOM

0.125 MM0.125 MM

50_OHM_SEYTOP,BOTTOM

55_OHM_SE

Y =STANDARD*

0.076 MM

=STANDARD

0.076 MM

=STANDARD

Y

30 MM

*

0 MM 0 MM

=55_OHM_SE

DEFAULT

=55_OHM_SE

STANDARD

* Y

=DEFAULT =DEFAULT

12.7 MM

=DEFAULT =DEFAULT

0.105 MM0.105 MM

=STANDARD

=STANDARD=STANDARDY*

45_OHM_SE

Y

ISL2,ISL11

0.250 MM

55_OHM_SE

0.076 MM

0.100 MM0.100 MM

Y

55_OHM_SE

TOP,BOTTOM

0.150 MM0.150 MM

45_OHM_SE

TOP,BOTTOM

Y

50_OHM_SE

0.090 MM0.090 MM

=STANDARD=STANDARDY*

=STANDARD

?

*

0.4 MM

4:1_SPACING

* Y =STANDARD =STANDARD

=STANDARD40_OHM_SE

0.131 MM 0.131 MM

0.1 MM0.1 MM

=STANDARD=STANDARD

1:1_DIFFPAIR

* Y

=STANDARD

0.125 MM0.125 MM

0.149 MM0.149 MM

ISL3,ISL4

70_OHM_DIFF

Y

0.149 MM

ISL9,ISL10

0.125 MM

0.149 MM

70_OHM_DIFF

Y

0.125 MM

ISL2,ISL11

0.125 MM0.125 MM

0.185 MM0.185 MM

70_OHM_DIFF

Y

ISL3,ISL4 Y

80_OHM_DIFF

0.125 MM0.125 MM

0.115 MM 0.115 MM

ISL9,ISL10

Y

80_OHM_DIFF

0.125 MM 0.125 MM

0.115 MM0.115 MM

Y

TOP,BOTTOM

80_OHM_DIFF

0.125 MM0.125 MM

0.140 MM0.140 MM

90_OHM_DIFF

=STANDARD =STANDARD

*

=STANDARD

=STANDARD=STANDARDN

N =STANDARD =STANDARD

=STANDARD

100_OHM_DIFF

=STANDARD

*

=STANDARD

0.125 MM0.125 MM

Y

85_OHM_DIFF

TOP,BOTTOM

0.125 MM 0.125 MM

0.125 MM

0.125 MM0.125 MM

Y

85_OHM_DIFF

ISL2,ISL11

0.125 MM

ISL9,ISL10

0.125 MM

0.101 MM0.101 MM

85_OHM_DIFF

Y

0.125 MM

N =STANDARD=STANDARD

=STANDARD

*

85_OHM_DIFF

=STANDARD=STANDARD

100_DIFF_BGA

=100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF

*

Y

100_OHM_DIFF

TOP,BOTTOM

0.099 MM 0.099 MM

0.200 MM 0.200 MM

ISL2,ISL11

100_OHM_DIFF

0.099 MM

Y

0.200 MM 0.200 MM

0.099 MM

ISL9,ISL10

0.200 MM0.200 MM

0.080 MM

100_OHM_DIFF

Y

0.080 MM

100_DIFF_BGA

0.125 MM0.125 MM

0.075 MM0.075 MM

ISL9,ISL10

Y

0.080 MM

0.200 MM 0.200 MM

100_OHM_DIFF

ISL3,ISL4

0.080 MM

100_DIFF_BGA

0.125 MM0.125 MM

0.075 MM0.075 MM

YISL3,ISL4

Y

0.130 MM 0.130 MM

0.220 MM 0.220 MM

TOP,BOTTOM

90_OHM_DIFF

2:1_SPACING

?

0.2 MM

*

Y

90_OHM_DIFF

0.102 MM 0.102 MM

0.220 MM 0.220 MM

ISL9,ISL10

Y

90_OHM_DIFF

0.102 MM 0.102 MM

0.220 MM 0.220 MM

ISL3,ISL4

88 88

A.0.0

051-7225

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

PCB Rule Definitions

Apple A1226 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual