Analog Devices AD5552BR, AD5551BR Datasheet

5 V, Serial-Input

SERIAL INPUT REGISTER

V

REF

CS

DIN

SCLK

AGND

V

OUT

V

DD

DGND

AD5551

14-BIT DAC

14-BIT DATA LATCH

CONTROL

LOGIC

a

FEATURES
Full 14-Bit Performance
5 V Single Supply Operation
Low Power
Fast Settling Time
Unbuffered Voltage Output Capable of Driving 60 k⍀

Loads Directly

SPI™/QSPI™/MICROWIRE™-Compatible Interface

Standards

Power-On Reset Clears DAC Output to 0 V (Unipolar

Mode)

Schmitt Trigger Inputs for Direct Optocoupler Interface

APPLICATIONS
Digital Gain and Offset Adjustment
Automatic Test Equipment
Data Acquisition Systems
Industrial Process Control

GENERAL DESCRIPTION

The AD5551 and AD5552 are single, 14-bit, serial input, voltage
output DACs that operate from a single 5 V ± 10% supply.

The AD5551 and AD5552 utilize a versatile 3-wire interface that
is compatible with SPI, QSPI, MICROWIRE, and DSP inter­face standards.

These DACs provide 14-bit performance without any adjust­ments. The DAC output is unbuffered, which reduces power
consumption and offset errors contributed by an output buffer.

With an external op amp the AD5552 can be operated in bipo­lar mode generating a ±V
includes Kelvin sense connections for the reference and analog
ground pins to reduce layout sensitivity. For higher precision
applications, please refer to 16-bit DACs AD5541, AD5542,
and AD5544.

The AD5551 and AD5552 are available in an SO package.

output swing. The AD5552 also

REF

Voltage-Output, 14-Bit DACs

AD5551/AD5552

FUNCTIONAL BLOCK DIAGRAMS

V

DD

R

FB

RFB

INV

V

OUT

AGNDF

AGNDS

V

REFF

V

REFS

LDAC

SCLK

DIN

AD5552

CS

R

CONTROL

LOGIC

INV

14-BIT DAC

14-BIT DATA LATCH

SERIAL INPUT REGISTER

DGND

PRODUCT HIGHLIGHTS

1. Single Supply Operation.
The AD5551 and AD5552 are fully specified and guaranteed
for a single 5 V ± 10% supply.

2. Low Power Consumption.
Typically 1.5 mW with a 5 V supply.

3. 3-Wire Serial Interface.

4. Unbuffered output capable of driving 60 kΩ loads, which
reduces power consumption as there is no internal buffer
to drive.

5. Power-On Reset Circuitry.

SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.

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Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

AD5551/AD5552–SPECIFICATIONS

(VDD = 5 V ⴞ 10%, V
TA = T

to T

MIN

MAX,

= 2.5 V, AGND = DGND = 0 V. All specifications

REF

unless otherwise noted.)

Parameter Min Typ Max Unit Test Condition

STATIC PERFORMANCE

Resolution 14 Bits
Relative Accuracy, INL ± 0.15 ± 1.0 LSB B Grade
Differential Nonlinearity ± 0.15 ± 0.8 LSB Guaranteed Monotonic
Gain Error –1.75 –0.3 0 LSB
Gain Error Temperature Coefficient ± 0.1 ppm/°C
Zero Code Error 0 0.1 0.5 LSB
Zero Code Temperature Coefficient ± 0.05 ppm/°C

AD5552

Bipolar Resistor Matching 1.000 Ω/Ω R

, Typically RFB = R

FB/RINV

= 28 kΩ

INV

± 0.0015 ± 0.0152 % Ratio Error
Bipolar Zero Offset Error ±0.25 ±2.5 LSB
Bipolar Zero Temperature Coefficient ±0.2 ppm/°C

OUTPUT CHARACTERISTICS

Output Voltage Range 0 V

–V

REF

Output Voltage Settling Time 1 µs to 1/2 LSB of FS, C
Slew Rate 25 V/µsC

– 1 LSB V Unipolar Operation

REF

V

– 1 LSB V AD5552 Bipolar Operation

REF

= 10 pF, Measured from 0% to 63%

L

= 10 pF

L

Digital-to-Analog Glitch Impulse 10 nV-s 1 LSB Change Around the Major Carry
Digital Feedthrough 10 nV-s All 1s Loaded to DAC, V

= 2.5 V

REF

DAC Output Impedance 6.25 kΩ Tolerance Typically 20%
Power Supply Rejection Ratio ± 1.0 LSB ∆VDD ± 10%

DAC REFERENCE INPUT

Reference Input Range 2.0 V
Reference Input Resistance

2

9kΩ Unipolar Operation

DD

V

7.5 kΩ AD5552, Bipolar Operation

LOGIC INPUTS

Input Current ± 1 µA
V

, Input Low Voltage 0.8 V

INL

, Input High Voltage 2.4 V

V

INH

Input Capacitance
Hysteresis Voltage

3

3

0.4 V

10 pF

REFERENCE

Reference –3 dB Bandwidth 1.3 MHz All 1s Loaded
Reference Feedthrough 1 mV p-p All 0s Loaded, V

= 1 V p-p at 100 kHz

REF

Signal-to-Noise Ratio 92 dB
Reference Input Capacitance 75 pF Code 0000

120 pF Code 3FFF

H

H

POWER REQUIREMENTS

V

DD

I

DD

4.50 5.50 V

0.3 1.1 mA

Power Dissipation 1.5 6.05 mW

NOTES

1

Temperature range is as follows: B Version: –40°C to +85°C.

2

Reference input resistance is code-dependent, minimum at 2555H.

3

Guaranteed by design, not subject to production test.

Specifications subject to change without notice.

–2–

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AD5551/AD5552

TIMING CHARACTERISTICS1,

Limit at T

MIN

, T

(VDD = 5 V ⴞ 5%, V

2

otherwise noted.)

MAX

= 2.5 V, AGND = DGND = 0 V. All specifications TA = T

REF

MIN

to T

MAX,

unless

Parameter All Versions Unit Description

f

SCLK

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

t

10

t

11

t

12

NOTES

1

Guaranteed by design. Not production tested.

2

Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 5 ns (10% to
90% of +3 V and timed from a voltage level of +1.6 V).

Specifications subject to change without notice.

25 MHz max SCLK Cycle Frequency
40 ns min SCLK Cycle Time
20 ns min SCLK High Time
20 ns min SCLK Low Time
15 ns min CS Low to SCLK High Setup
15 ns min CS High to SCLK High Setup
35 ns min SCLK High to CS Low Hold Time
20 ns min SCLK High to CS High Hold Time
15 ns min Data Setup Time
0 ns min Data Hold Time
30 ns min LDAC Pulsewidth
30 ns min CS High to LDAC Low Setup
30 ns min CS High Time Between Active Periods

t

1

SCLK

t

6

t

4

LDAC

CS

DIN

*

t

12

t

8

t

9

DB13

*

AD5552 ONLY. MAY BE TIED PERMANENTLY LOW IF REQUIRED.

t

2

t

3

DB0

t

5

t

7

t

11

t

10

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Figure 1. Timing Diagram

–3–

AD5551/AD5552

WARNING!

ESD SENSITIVE DEVICE

TOP VIEW

(Not to Scale)

14

13

12

11

10

9

8

1

2

3

4

5

6

7

NC = NO CONNECT

RFB

V

OUT

AGNDF

AGNDS

V

REFS

V

REFF

CS

V

DD

INV

DGND

LDAC

DIN

NC

SCLK

AD5552

ABSOLUTE MAXIMUM RATINGS*

(TA = 25°C unless otherwise noted)

VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V

Digital Input Voltage to DGND . . . . . –0.3 V to V

V

to AGND . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V

OUT

+ 0.3 V

DD

AGND, AGNDF, AGNDS to DGND . . . . . –0.3 V to +0.3 V

Input Current to Any Pin Except Supplies . . . . . . . . ±10 mA

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Maximum Junction Temperature, (T

max) . . . . . . . . . 150°C

J

Package Power Dissipation . . . . . . . . . . . . . (TJ max – TA)/θ

Thermal Impedance θ

JA

JA

SOIC (SO-8) . . . . . . . . . . . . . . . . . . . . . . . . . . 149.5°C/W

SOIC (R-14) . . . . . . . . . . . . . . . . . . . . . . . . . . 104.5°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

ORDERING GUIDE

Model INL DNL Temperature Range Package Description Package Option

AD5551BR ± 1 LSB ± 0.8 LSB –40°C to +85°C 8-Lead Small Outline IC SO-8
AD5552BR ± 1 LSB ± 0.8 LSB –40°C to +85°C 14-Lead Small Outline IC R-14

Die Size = 80 ⫻ 139 = 11,120 sq mil; Number of Transistors = 1230.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5551/AD5552 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.

AD5551 PIN FUNCTION DESCRIPTIONS

Mnemonic Pin No. Description

V

OUT

1 Analog Output Voltage from the DAC.
AGND 2 Ground Reference Point for Analog Circuitry.
V

REF

3 This is the voltage reference input for the DAC. Connect to external reference ranges from

2 V to V

DD

.

CS 4 This is an active low-logic input signal. The chip select signal is used to frame the serial

data input.

SCLK 5 Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle

must be between 40% and 60%.

DIN 6 Serial Data Input. This device accepts 14-bit words. Data is clocked into the input register on

the rising edge of SCLK.
DGND 7 Digital Ground. Ground reference for digital circuitry.
V

DD

8 Analog Supply Voltage, 5 V ± 10%.

AD5551 PIN CONFIGURATION

SOIC

1

V

OUT

2

AGND

V

REF

AD5551

TOP VIEW

3

(Not to Scale)

4

8

7

6

5

V

DD

DGND

DIN

SCLKCS

–4–

AD5552 PIN CONFIGURATION

SOIC

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