Xilinx RocketIO XC2VP2, RocketIO XC2VP20, RocketIO XC2VP4, RocketIO XC2VP7, RocketIO XC2VP30 User Manual
...
R
RocketIO™
Transceiver
User Guide
UG024 (v2.3.2) June 24, 2004
RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v2.3.2) June 24, 2004
1-800-255-7778
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UG024 (v2.3.2) June 24, 2004 www.xilinx.com RocketIO™ Transceiver User Guide
1-800-255-7778
RocketIO™ Transceiver User Guide
UG024 (v2.3.2) June 24, 2004
The following table shows the revision history for this document.
Date Version Revision
11/20/01 1.0 • Initial Xilinx release.
01/23/02 1.1 • Updated for typographical and other errors found during review.
02/25/02 1.2 • Part of Virtex-II Pro™ Developer’s Kit (March 2002 Release)
07/11/02 1.3 • Updated “PCB Design Requirements”. Added Appendix A, “RocketIO Transceiver Timing
Model.” Changed Cell Models to Appendix B.
09/27/02 1.4 • Added additional IMPORTANT NOTE regarding ISE revisions at the beginning of Chapter 1
• Added material in section “CRC (Cyclic Redundancy Check).”
• Added section “Other Important Design Notes.”
• New pre-emphasis eye diagrams in section “Pre-emphasis Techniques.”
• Numerous parameter additions previously shown as “TBD” in “MGT Package Pins.”
10/16/02 1.5 • Corrected pinouts for FF1152 package, device column 2VP20/30, LOC Constraints rows
GT_X0_Y0 and GT_X0_Y1.
• Corrected section “CRC Latency” and Table 2-20 to express latency in terms of TXUSRCLK
and RXUSRCLK cycles.
• Corrected sequence of packet elements in Figure 2-30.
11/20/02 1.6 • Tabl e 1-2: Added support for XAUI Fibre Channel.
• Corrected max PCB drive distance to 40 inches.
• Reorganized content sequence in Chapter 2, “Digital Design Considerations.”
• Table 1 -5: Additional information in RXCOMMADET definition.
• Code corrections in VHDL Clock templates.
• “Data Path Latency” section expanded and reformatted.
• Corrections in clocking scheme drawings. Addition of drawings showing clocking schemes
without using DCM.
• Table B -1: Corrections in Valid Data Characters.
• Table 3 -4: Data added.
• Corrections made to power regulator schematic, Figure 3-7.
• Table 2 -23: Data added/corrected.
12/12/02 1.6.1 • Added clarifying text regarding trace length vs. width.
03/25/03 2.0 • Reorganized existing content
• Added new content
• Added Appendix C, “Related Online Documents”
• Added “Index”
RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v2.3.2) June 24, 2004
1-800-255-7778
06/12/03 2.1 • Table 1-2: Added qualifying footnote to XAUI 10GFC.
• Table 1 -5: Corrected definition of RXRECCLK.
• Section “RocketIO Transceiver Instantiations” in Chapter 1: added text briefly explaining what
the Instantiation Wizard does.
• Table 2 -14: Changed numerics from exact values to rounded-off approximations (nearest
5,000), and added footnote calling attention to this.
• Section “Clocking” in Chapter 2: added text recommending use of an IBUFGDS for reference
clock input to FPGA fabric.
• Section “RXRECCLK” in Chapter 2: Deleted references to SERDES_10B attribute and to
divide-by-10. (RXRECCLK is always 1/20th the data rate.).
• Section “CRC_FORMAT” in Chapter 2: Corrected minimum data length for USER_MODE to
“greater than 20”.
• Table 3 -5: Clarified the significance of the V
TTX/VTRX
voltages shown in this table.
• Section “AC and DC Coupling” in Chapter 3: Explanatory material added regarding
V
TRX/VTTX
settings when AC or DC coupling is used.
• Table 4 -1: Corrected pinouts for FG256 and FG456.
• Table 4 -3: Corrected pinouts for FF1517 (XC2VP70).
11/07/03 2.2 • Section “Clock Signals” in Chapter 2: Added material that states:
♦ the reference clock must be provided at all times.
♦ any added jitter on the reference clock will be reflected on the RX/TX I/O.
• Figure 2-3: Added a BUFG after the IBUFGDS reference clock buffer.
• Section “RX_BUFFER_USE” in Chapter 2: Corrected erroneous “USRCLK2” to
“RXUSRCLK/RXUSRCLK2”.
• Table 2 -20: Added footnotes qualifying the maximum receive-side latency parameters given
in the table.
• Section “FIBRE_CHAN” in Chapter 2: Added specification for minimum data length (24
bytes not including CRC placeholder).
• Section “ETHERNET” in Chapter 2: Added note indicating that Gigabit Ethernet 802.3 frame
specifications must be adhered to.
• Table 2 -23: Corrected “External” to “Internal” loopback. Improved explanation of Parallel
Mode loopback.
• Added Figure 2-28, “Serial and Parallel Loopback Logic.”
• Section “Clock and Data Recovery” in Chapter 3: Corrected text to make clear that
RXRECCLK is always 1/20th the incoming data rate, and that CDR requires a minimum
number of transitions to achieve and maintain a lock on the received data.
• Section “Voltage Regulation” in Chapter 3: Added material defining voltage regulator
requirements when a device other than the LT1963 is used.
• Section “AC and DC Coupling” in Chapter 3: Added footnote to Table 3-7 clarifying
V
TRX/VTTX
voltage compliance.
• Figure 3-17 and section “Epson EG-2121CA 2.5V (LVPECL Outputs)” in Chapter 3: Added
material specifying the optional use of an LVPECL buffer as an alternative to the LVDS buffer
previously specified.
• Table 4 -2: Added pinouts for FG676 package, XC2VP20 and XC2VP30.
• Table A -5: Added BREFCLK parameters T
BREFPWH
and T
BREFPWL
.
• Section “Application Notes” in Appendix C: Included new Xilinx Application Notes
XAPP648, XAPP669, and XAPP670.
• Various non-technical edits and corrections.
Date Version Revision
UG024 (v2.3.2) June 24, 2004 www.xilinx.com RocketIO™ Transceiver User Guide
1-800-255-7778
02/24/04 2.3 • Table 2-3, page 41: Added FG676 row to BREFCLK Pin Numbers.
• Figure 2-4, page 47: Added note above Figure 2-4 stating, “These local MGT clock input
inverters, shown and noted in Figure 2-4, are not included in the FOUR_BYTE_CLK
templates.
• Section“RXRECCLK” in Chapter 2: Added paragraph to section explaining how RXRECCLK
changes monotonically and how the recovered bit clock is derived.
• Section “Data Path Latency” in Chapter 2: Revised first sentence to read: “With the many
configurations of the MGT, both the transmit and receive data path latencies vary.”
• Section “RXBUFSTATUS” in Chapter 2: Revised the description of RXBUFSTATUS.
• Figure 3-1, page 101: Replaced old Figure 3-1, page 101, with new Figure 3-1 showing
“Differential Amplifier.”
• Figure 3-6, page 105: Added new Figure 3-6, page 105, showing “MGT Receiver.”
• Table 3-4, page 106: Added text to CDR Parameters (TLOCK parameter in Conditions
column) and edited Note 3.
• Section “Voltage Regulation” in Chapter 3: Added Linear Technology part numbers
(LT1963A, LT1964).
• Section “Passive Filtering” in Chapter 3: Added new cap rules for RocketIO transceiver.
• Figure 3-8, page 109: Replaced old Figure 3-8 with new figure showing “Power Filtering
Network on Devices with Internal and External Capacitors.”
• Table 3-6, page 110: Added Device and Package combinations table.
• Figure 3-9, page 110: Added new Figure 3-10, page 110, showing “Example Power Filtering
PCB Layout for Four MGTs, in Device with Internal Capacitors, Bottom Layer.” Modified the
text describing Figure 3-9, page 110.
• Figure 3-10, page 111: Replaced old Figure 3-10 with new figure showing “Example Power
Filtering PCB Layout for Four MGTs, in Device with External Capacitors, Top Layer.”
Removed the text describing old Figure 3-10.
• Figure 3-11, page 112: Replaced old Figure 3-11 with new figure showing “Example Power
Filtering PCB Layout for Four MGTs, in Device with External Capacitors, Bottom Layer.”
Removed the text describing old Figure 3-11.
• Table 3-7, page 115: Added V
TRX
and V
TTX
voltages for different coupling environments.
05/20/04 2.3.1 • Changed the value of TRCLK/RFCLK in Table 3-4.
06/24/04 2.3.2 • Modified Figure 2-3.
Date Version Revision
RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v2.3.2) June 24, 2004
1-800-255-7778
RocketIO™ Transceiver User Guide www.xilinx.com 7
UG024 (v2.3.2) June 24, 2004 1-800-255-7778
Schedule of Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Schedule of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Preface: About This Guide
RocketIO Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
For More Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Port and Attribute Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Typographical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Chapter 1: RocketIO Transceiver Overview
Basic Architecture and Capabilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
RocketIO Transceiver Instantiations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
HDL Code Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
List of Available Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Primitive Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Modifiable Primitives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Byte Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Chapter 2: Digital Design Considerations
Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
BREFCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Clock Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Digital Clock Manager (DCM) Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Example 1a: Two-Byte Clock with DCM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Example 1b: Two-Byte Clock without DCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Example 2: Four-Byte Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Example 3: One-Byte Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Half-Rate Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Multiplexed Clocking Scheme with DCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Multiplexed Clocking Scheme without DCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
RXRECCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Clock Dependency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Data Path Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Reset/Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
8B/10B Encoding/Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
8B/10B Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table of Contents
8 www.xilinx.com RocketIO™ Transceiver User Guide
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8B/10B Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
TXBYPASS8B10B,
RX_DECODE_USE
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
TXCHARDISPVAL,
TXCHARDISPMODE
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
TXCHARISK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
TXRUNDISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
TXKERR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
RXCHARISK,
RXRUNDISP
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
RXDISPERR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
RXNOTINTABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Vitesse Disparity Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Transmitting Vitesse Channel Bonding Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Receiving Vitesse Channel Bonding Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
8B/10B Bypass Serial Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
8B/10B Serial Output Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
HDL Code Examples: Transceiver Bypassing of 8B/10B Encoding . . . . . . . . . . . . . . . . . . . 67
SERDES Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Serializer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Deserializer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
ALIGN_COMMA_MSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
ENPCOMMAALIGN,
ENMCOMMAALIGN
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
PCOMMA_DETECT,
MCOMMA_DETECT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
COMMA_10B_MASK,
PCOMMA_10B_VALUE,
MCOMMA_10B_VALUE
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
DEC_PCOMMA_DETECT,
DEC_MCOMMA_DETECT,
DEC_VALID_COMMA_ONLY
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
RXREALIGN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
RXCHARISCOMMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
RXCOMMADET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Clock Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Clock and Data Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Clock Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
CLK_CORRECT_USE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
RX_BUFFER_USE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
CLK_COR_SEQ_*_* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
CLK_COR_SEQ_LEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
CLK_COR_INSERT_IDLE_FLAG,
CLK_COR_KEEP_IDLE,
CLK_COR_REPEAT_WAIT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Synchronization Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
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Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
RXCLKCORCNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
RX_LOS_INVALID_INCR,
RX_LOS_THRESHOLD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
RX_LOSS_OF_SYNC_FSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
RXLOSSOFSYNC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Channel Bonding (Channel Alignment) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Channel Bonding (Alignment) Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
CHAN_BOND_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
ENCHANSYNC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
CHAN_BOND_ONE_SHOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
CHAN_BOND_SEQ_*_*,
CHAN_BOND__SEQ_LEN,
CHAN_BOND_SEQ_2_USE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
CHAN_BOND_WAIT,
CHAN_BOND_OFFSET,
CHAN_BOND_LIMIT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
CHBONDDONE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
CHBONDI,
CHBONDO
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
RXCLKCORCNT,
RXLOSSOFSYNC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
CRC (Cyclic Redundancy Check). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
CRC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
CRC Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
CRC Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
TX_CRC_USE,
RX_CRC_USE
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
CRC_FORMAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
CRC_START_OF_PACKET,
CRC_END_OF_PACKET
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
RXCHECKINGCRC,
RXCRCERR
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
TXFORCECRCERR,
TX_CRC_FORCE_VALUE
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
RocketIO CRC Support Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Fabric Interface (Buffers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Overview: Transmitter and Elastic (Receiver) Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Transmitter Buffer (FIFO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Receiver Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
TXBUFERR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
TX_BUFFER_USE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
RXBUFSTATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
RX_BUFFER_USE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Miscellaneous Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
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RX_DATA_WIDTH,
TX_DATA_WIDTH
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
SERDES_10B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
TERMINATION_IMP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
TXPOLARITY,
RXPOLARITY,
TXINHIBIT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
TX_DIFF_CTRL,
PRE_EMPHASIS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
LOOPBACK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Other Important Design Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Receive Data Path 32-bit Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
32-bit Alignment Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Chapter 3: Analog Design Considerations
Serial I/O Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Pre-emphasis Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Differential Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Clock and Data Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
PCB Design Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Power Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Voltage Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Passive Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
High-Speed Serial Trace Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Routing Serial Traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Differential Trace Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
AC and DC Coupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Epson EG-2121CA 2.5V (LVPECL Outputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Pletronics LV1145B (LVDS Outputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Other Important Design Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Powering the RocketIO Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
The POWERDOWN Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Chapter 4: Simulation and Implementation
Simulation Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
SmartModels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
HSPICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Implementation Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Par . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
MGT Package Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Appendix A: RocketIO Transceiver Timing Model
Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Setup/Hold Times of Inputs Relative to Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Clock to Output Delays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
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Clock Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Timing Parameter Tables and Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Appendix B: 8B/10B Valid Characters
Valid Data Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Valid Control Characters (K-Characters) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Appendix C: Related Online Documents
Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
XAPP648: Serial Backplane Interface to a Shared Memory . . . . . . . . . . . . . . . . . . . . . . . . 143
XAPP649: SONET Rate Conversion in Virtex-II Pro Devices . . . . . . . . . . . . . . . . . . . . . . 143
XAPP651: SONET and OTN Scramblers/Descramblers . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
XAPP652: Word Alignment and SONET/SDH Deframing . . . . . . . . . . . . . . . . . . . . . . . . . 144
XAPP660: Partial Reconfiguration of RocketIO Pre-emphasis
and Differential Swing Control Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
XAPP661: RocketIO Transceiver Bit-Error Rate Tester . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
XAPP662: In-Circuit Partial Reconfiguration of RocketIO Attributes . . . . . . . . . . . . . . . . 144
XAPP669: PPC405 PPE Reference System Using Virtex-II Pro
RocketIO Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
XAPP670: Minimizing Receiver Elastic Buffer Delay in the Virtex-II Pro
RocketIO Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
XAPP680: HD-SDI Transmitter Using Virtex-II Pro RocketIO Multi-Gigabit Transceivers145
XAPP681: HD-SDI Receiver Using Virtex-II Pro RocketIO Multi-Gigabit Transceivers . 145
XAPP687: 64B/66B Encoder/Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Characterization Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Virtex-II Pro RocketIO Multi-Gigabit Transceiver
Characterization Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Virtex-II Pro RocketIO MGT HSSDC2 Cable Characterization . . . . . . . . . . . . . . . . . . . . . 146
White Papers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
WP157: Usage Models for Multi-Gigabit Serial Transceivers . . . . . . . . . . . . . . . . . . . . . . . 147
WP160: Emulating External SERDES Devices with
Embedded RocketIO Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
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Chapter 1: RocketIO Transceiver Overview
Figure 1-1: RocketIO Transceiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Chapter 2: Digital Design Considerations
Figure 2-1: REFCLK/BREFCLK Selection Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 2-2: Two-Byte Clock with DCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 2-3: Two-Byte Clock without DCM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 2-4: Four-Byte Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 2-5: One-Byte Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 2-6: One-Byte Data Path Clocks, SERDES_10B = TRUE. . . . . . . . . . . . . . . . . . . . . . . 55
Figure 2-7: Two-Byte Data Path Clocks, SERDES_10B = TRUE . . . . . . . . . . . . . . . . . . . . . . 55
Figure 2-8: Four-Byte Data Path Clocks, SERDES_10B = TRUE . . . . . . . . . . . . . . . . . . . . . . 55
Figure 2-9: Multiplexed REFCLK with DCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 2-10: Multiplexed REFCLK without DCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 2-11: Using RXRECCLK to Generate RXUSRCLK and RXUSRCLK2 . . . . . . . . . . 57
Figure 2-12: 8B/10B Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 2-13: 10-Bit TX Data Map with 8B/10B Bypassed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 2-14: 10-Bit RX Data Map with 8B/10B Bypassed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 2-15: 8B/10B Parallel to Serial Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 2-16: 4-Byte Serial Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 2-17: Synchronizing Comma Align Signals to RXRECCLK . . . . . . . . . . . . . . . . . . . . 69
Figure 2-18: Top MGT Comma Control Flip-Flop Ideal Locations . . . . . . . . . . . . . . . . . . . . 70
Figure 2-19: Bottom MGT Comma Control Flip-Flop Ideal Locations. . . . . . . . . . . . . . . . . . 70
Figure 2-20: Clock Correction in Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 2-21: RXLOSSOFSYNC FSM States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 2-22: Channel Bonding (Alignment) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 2-23: CRC Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 2-24: USER_MODE / FIBRE_CHAN Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 2-25: Ethernet Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 2-26:
Infiniband Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 2-27: Local Route Header. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 2-28: Serial and Parallel Loopback Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 2-29: RXDATA Aligned Correctly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 2-30: Realignment of RXDATA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Chapter 3: Analog Design Considerations
Figure 3-1: Differential Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 3-2: Alternating K28.5+ with No Pre-Emphasis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Schedule of Figures
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Figure 3-3: K28.5+ with Pre-Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 3-4: Eye Diagram, 10% Pre-Emphasis, 20" FR4, Worst-Case Conditions . . . . . . . . 104
Figure 3-5: Eye Diagram, 33% Pre-Emphasis, 20" FR4, Worst-Case Conditions . . . . . . . . 104
Figure 3-6: MGT Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 3-7: Power Supply Circuit Using LT1963 (LT1963A) Regulator . . . . . . . . . . . . . . . . 108
Figure 3-8: Power Filtering Network on Devices with Internal and External Capacitors . . 109
Figure 3-9: Example Power Filtering PCB Layout for Four MGTs, in Device with Internal Capacitors,
Bottom Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 3-10: Example Power Filtering PCB Layout for Four MGTs, In Device with External
Capacitors, Top Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 3-11: Example Power Filtering PCB Layout for Four MGTs, in Device with External Capacitors,
Bottom Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 3-12: Single-Ended Trace Geometry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 3-13: Microstrip Edge-Coupled Differential Pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 3-14: Stripline Edge-Coupled Differential Pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 3-15: AC-Coupled Serial Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 3-16: DC-Coupled Serial Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 3-17: LVPECL Reference Clock Oscillator Interface . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 3-18: LVPECL Reference Clock Oscillator Interface (On-Chip Termination) . . . . 116
Figure 3-19: LVDS Reference Clock Oscillator Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 3-20: LVDS Reference Clock Oscillator Interface (On-Chip Termination) . . . . . . . 116
Chapter 4: Simulation and Implementation
Figure 4-1: 2VP2 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 4-2: 2VP50 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Appendix A: RocketIO Transceiver Timing Model
Figure A-1: RocketIO Transceiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure A-2: RocketIO Transceiver Timing Relative to Clock Edge. . . . . . . . . . . . . . . . . . . . 131
Appendix B: 8B/10B Valid Characters
Appendix C: Related Online Documents
RocketIO™ Transceiver User Guide www.xilinx.com 15
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Chapter 1: RocketIO Transceiver Overview
Table 1-1: Number of RocketIO Cores per Device Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 1-2: Communications Standards Supported by RocketIO Transceiver . . . . . . . . . . . . 21
Table 1-3: Serial Baud Rates and the SERDES_10B Attribute . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 1-4: Supported RocketIO Transceiver Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 1-5: GT_CUSTOM
(1)
, GT_AURORA, GT_FIBRE_CHAN
(2)
, GT_ETHERNET
(2)
,
GT_INFINIBAND, and GT_XAUI Primitive Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 1-6: RocketIO Transceiver Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 1-7: Default Attribute Values: GT_AURORA, GT_CUSTOM, GT_ETHERNET . . . 33
Table 1-8: Default Attribute Values: GT_FIBRE_CHAN, GT_INFINIBAND,
and GT_XAUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 1-9: Control/Status Bus Association to Data Bus Byte Paths . . . . . . . . . . . . . . . . . . . . . 37
Chapter 2: Digital Design Considerations
Table 2-1: Clock Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 2-2: Reference Clock Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 2-3: BREFCLK Pin Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 2-4: Data Width Clock Ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 2-5: DCM Outputs for Different DATA_WIDTHs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 2-6: Latency through Various Transmitter Components/Processes . . . . . . . . . . . . . . . 57
Table 2-7: Latency through Various Receiver Components/Processes . . . . . . . . . . . . . . . . . . 58
Table 2-8: Reset and Power Control Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 2-9: Power Control Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 2-10: 8B/10B Bypassed Signal Significance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 2-11: Running Disparity Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 2-12: Possible Locations of Comma Character . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 2-13: Effects of Comma-Related Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 2-14: Data Bytes Allowed Between Clock Corrections as a Function of
REFCLK Stability and IDLE Sequences Removed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 2-15: Clock Correction Sequence / Data Correlation for 16-Bit Data Port. . . . . . . . . . 75
Table 2-16: Applicable Clock Correction Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 2-17: RXCLKCORCNT Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 2-18: Bonded Channel Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 2-19: Master/Slave Channel Bonding Attribute Settings . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 2-20: Effects of CRC on Transceiver Latency
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 2-21: Global and Local Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 2-22: Serial Speed Ranges as a Function of SERDES_10B. . . . . . . . . . . . . . . . . . . . . . . 90
Table 2-23: LOOPBACK Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 2-24: 32-bit RXDATA, Aligned versus Misaligned . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Schedule of Tables
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Chapter 3: Analog Design Considerations
Table 3-1: Differential Transmitter Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 3-2: Pre-emphasis Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 3-3: Differential Receiver Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 3-4: CDR Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 3-5: Transceiver Power Supplies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 3-6: Device and Package Combinations showing Devices with RocketIO Power Filtering Capaci-
tors Internal to the Package and Externally Mounted on the PCB . . . . . . . . . . . . . . . . . . 110
Table 3-7: V
TRX
and V
TTX
for AC- and DC-Coupled Environments . . . . . . . . . . . . . . . . . . 115
Chapter 4: Simulation and Implementation
Table 4-1: LOC Grid & Package Pins Correlation for FG256/456 & FF672 . . . . . . . . . . . . . . . . . . 121
Table 4-2:
LOC Grid & Package Pins Correlation for FG676, FF896, and FF1152 . . . . . . . . . . . . 122
Table 4-3:
LOC Grid & Package Pins Correlation for FF1517 and FF1704 . . . . . . . . . . . . . . . . . . 123
Appendix A: RocketIO Transceiver Timing Model
Table A-1: RocketIO Clock Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table A-2: Parameters Relative to the RX User Clock (RXUSRCLK) . . . . . . . . . . . . . . . . . 128
Table A-3: Parameters Relative to the RX User Clock2 (RXUSRCLK2) . . . . . . . . . . . . . . . 129
Table A-4: Parameters Relative to the TX User Clock2 (TXUSRCLK2). . . . . . . . . . . . . . . . 129
Table A-5: Miscellaneous Clock Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Appendix B: 8B/10B Valid Characters
Table B-1: Valid Data Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table B-2: Valid Control Characters (K-Characters) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Appendix C: Related Online Documents
RocketIO™ Transceiver User Guide www.xilinx.com 17
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Preface
About This Guide
The RocketIO Transceiver User Guide provides the product designer with the detailed technical
information needed to successfully implement the RocketIO™ multi-gigabit transceiver in
Virtex-II Pro Platform FPGA designs.
RocketIO Features
The RocketIO transceiver’s flexible, programmable features allow a multi-gigabit serial transceiver
to be easily integrated into any Virtex-II Pro design:
• Variable-speed, full-duplex transceiver, allowing 600 Mb/s to 3.125 Gb/s baud transfer rates
• Monolithic clock synthesis and clock recovery system, eliminating the need for external
components
• Automatic lock-to-reference function
• Five levels of programmable serial output differential swing (800 mV to 1600 mV peak-peak),
allowing compatibility with other serial system voltage levels
• Four levels of programmable pre-emphasis
• AC and DC coupling
• Programmable 50Ω/75Ω on-chip termination, eliminating the need for external termination
resistors
• Serial and parallel TX-to-RX internal loopback modes for testing operability
• Programmable comma detection to allow for any protocol and detection of any 10-bit
character.
Guide Contents
The RocketIO Transceiver User Guide contains these sections:
• Preface, “About This Guide” — This section.
• Chapter 1, “RocketIO Transceiver Overview” — An overview of the transceiver’s capabilities
and how it works.
• Chapter 2, “Digital Design Considerations” — Ports and attributes for the six provided
communications protocol primitives; VHDL/Verilog code examples for clocking and reset
schemes; transceiver instantiation; 8B/10B encoding; CRC; channel bonding.
• Chapter 3, “Analog Design Considerations” — RocketIO serial overview; pre-emphasis; jitter;
clock/data recovery; PCB design requirements.
• Chapter 4, “Simulation and Implementation” — Simulation models; implementation tools;
debugging and diagnostics.
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Preface: About This Guide
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• Appendix A, “RocketIO Transceiver Timing Model” — Timing parameters associated with the
RocketIO transceiver core.
• Appendix B, “8B/10B Valid Characters” — Valid data and K-characters.
• Appendix C, “Related Online Documents” — Bibliography of online Application Notes,
Characterization Reports, and White Papers.
For More Information
For a complete menu of online information resources available on the Xilinx website, visit
http://www.xilinx.com/virtex2pro/
or refer to Appendix C, “Related Online Documents.”
For a comprehensive listing of available tutorials and resources on network technologies and
communications protocols, visit http://www.iol.unh.edu/training/
.
Additional Resources
For additional information, go to http://support.xilinx.com. The following table lists some of the
resources you can access from this website. You can also directly access these resources using the
provided URLs.
Resource Description/URL
Tutorials Tutorials covering Xilinx design flows, from design entry to verification
and debugging
http://support.xilinx.com/support/techsup/tutorials/index.htm
Answer Browser Database of Xilinx solution records
http://support.xilinx.com/xlnx/xil_ans_browser.jsp
Application Notes Descriptions of device-specific design techniques and approaches
http://support.xilinx.com/apps/appsweb.htm
Data Sheets Device-specific information on Xilinx device characteristics, including
readback, boundary scan, configuration, length count, and debugging
http://support.xilinx.com/xlnx/xweb/xil_publications_index.jsp
Problem Solvers Interactive tools that allow you to troubleshoot your design issues
http://support.xilinx.com/support/troubleshoot/psolvers.htm
Tech Tips Latest news, design tips, and patch information for the Xilinx design
environment
http://www.support.xilinx.com/xlnx/xil_tt_home.jsp
RocketIO™ Transceiver User Guide www.xilinx.com 19
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Conventions
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Conventions
This document uses the following conventions. An example illustrates each typographical and
online convention.
Port and Attribute Names
Input and output ports of the RocketIO transceiver primitives are denoted in upper-case letters.
Attributes of the RocketIO transceiver are denoted in upper-case letters with underscores. Trailing
numbers in primitive names denote the byte width of the data path. These values are preset and not
modifiable. When assumed to be the same frequency, RXUSRCLK and TXUSRCLK are referred to
as USRCLK and can be used interchangeably. This also holds true for RXUSRCLK2,
TXUSRCLK2, and USRCLK2.
Comma Definition
A comma is a “K-character” used by the transceiver to align the serial data on a byte/half-word
boundary (depending on the protocol used), so that the serial data is correctly decoded into parallel
data.
Typographical
The following typographical conventions are used in this document:
Convention Meaning or Use Example
Courier font
Messages, prompts, and program
files that the system displays
speed grade: - 100
Courier bold
Literal commands that you enter
in a syntactical statement
ngdbuild design_name
Helvetica bold
Commands that you select from a
menu
File → Open
Keyboard shortcuts Ctrl+C
Italic font
Variables in a syntax statement
for which you must supply values
ngdbuild design_name
References to other manuals
See the Development System
Reference Guide for more
information.
Emphasis in text
If a wire is drawn so that it
overlaps the pin of a symbol, the
two nets are not connected.
Square brackets [ ]
An optional entry or parameter.
However, in bus specifications,
such as bus[7:0], they are
required.
ngdbuild [ option_name]
design_name
Braces { }
A list of items from which you
must choose one or more
lowpwr ={on|off}
Vertical bar | Separates items in a list of choices lowpwr ={on|off}
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Preface: About This Guide
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Online Document
The following conventions are used in this document:
Vertical ellipsis
.
.
.
Repetitive material that has been
omitted
IOB #1: Name = QOUT’
IOB #2: Name = CLKIN’
.
.
.
Horizontal ellipsis . . .
Repetitive material that has been
omitted
allow block block_name
loc1 loc2 ... locn;
Convention Meaning or Use Example
Convention Meaning or Use Example
Blue text
Cross-reference link to a location
in the current document
See the section “Additional
Resources” for details.
Refer to “Title Formats” in
Chapter 1 for details.
Red text
Cross-reference link to a location
in another document
See Figure 2-5 in the Virtex-II
Handbook.
Blue, underlined text
Hyperlink to a website (URL)
Go to http://www.xilinx.com
for
the latest speed files.
RocketIO™ Transceiver User Guide www.xilinx.com 21
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Chapter 1
RocketIO Transceiver Overview
Basic Architecture and Capabilities
The RocketIO transceiver is based on Mindspeed’s SkyRail™ technology. Figure 1-1, page 23,
depicts an overall block diagram of the transceiver. Up to 20 transceiver modules are available on a
single Virtex-II Pro FPGA, depending on the part being used. Table 1-1 shows the RocketIO cores
available by device.
The transceiver module is designed to operate at any serial bit rate in the range of 600 Mb/s to
3.125 Gb/s per channel, including the specific bit rates used by the communications standards listed
in Table 1-2. The serial bit rate need not be configured in the transceiver, as the operating frequency
is implied by the received data, the reference clock applied, and the SERDES_10B attribute (see
Tabl e 1-3).
Table 1-1: Number of RocketIO Cores per Device Type
Device RocketIO Cores Device RocketIO Cores
XC2VP2 4 XC2VP40 0 or 12
XC2VP4 4 XC2VP50 0 or 16
XC2VP7 8 XC2VP70 16 or 20
XC2VP20 8 XC2VP100 0 or 20
XC2VP30 8
Table 1-2: Communications Standards Supported by RocketIO Transceiver
Mode
Channels
(Lanes)
(1)
I/O Bit Rate
(Gb/s)
Fibre Channel 1
1.06
2.12
Gbit Ethernet 1 1.25
XAUI (10-Gbit Ethernet) 4 3.125
XAUI (10-Gbit Fibre Channel)
(2)
4 3.1875
(3)
Infiniband 1, 4, 12 2.5
Aurora (Xilinx protocol) 1, 2, 3, 4, ... 0.600 – 3.125
Custom Mode 1, 2, 3, 4, ... 0.600 – 3.125
Notes:
1. One channel is considered to be one transceiver.
2. Supported with the GT_CUSTOM primitive. Certain attributes must be modified to comply with the XAUI
10GFC specifications, including but not limited to CLK_COR_SEQ and CHAN_BOND_SEQ.
3. Bit rate is possible with the following topology specification: maximum 6" FR4 and one Molex 74441 connector.
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Chapter 1: RocketIO Transceiver Overview
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Table 1-3: Serial Baud Rates and the SERDES_10B Attribute
SERDES_10B Serial Baud Rate
FALSE 1.0 Gb/s – 3.125 Gb/s
TRUE 600 Mb/s – 1.0 Gb/s
Figure 1-1: RocketIO Transceiver Block Diagram
FPGA FABRIC
MULTI-GIGABIT TRANSCEIVER CORE
Serializer
RXP
TXP
Clock
Manager
Power Down
PACKAGE
PINS
Deserializer
Comma
Detect
Realign
8B/10B
Decoder
TX
FIFO
CRC
Check
CRC
Channel Bonding
and
Clock Correction
CHBONDI[3:0]
CHBONDO[3:0]
8B/10B
Encoder
RX
Elastic
Buffer
Output
Polarity
RXN
GNDA
TXN
DS083-2_04_090402
POWERDOWN
RXRECCLK
RXPOLARITY
RXREALIGN
RXCOMMADET
RXRESET
RXCLKCORCNT
RXLOSSOFSYNC
RXDATA[15:0]
RXDATA[31:16]
RXCHECKINGCRC
RXCRCERR
RXNOTINTABLE[3:0]
RXDISPERR[3:0]
RXCHARISK[3:0]
RXCHARISCOMMA[3:0]
RXRUNDISP[3:0]
RXBUFSTATUS[1:0]
ENCHANSYNC
RXUSRCLK
RXUSRCLK2
CHBONDDONE
TXBUFERR
TXDATA[15:0]
TXDATA[31:16]
TXBYPASS8B10B[3:0]
TXCHARISK[3:0]
TXCHARDISPMODE[3:0]
TXCHARDISPVAL[3:0]
TXKERR[3:0]
TXRUNDISP[3:0]
TXPOLARITY
TXFORCECRCERR
TXINHIBIT
LOOPBACK[1:0]
TXRESET
REFCLK
REFCLK2
REFCLKSEL
ENPCOMMAALIGN
ENMCOMMAALIGN
TXUSRCLK
TXUSRCLK2
VTRX
AVCCAUXRX
VTTX
AVCCAUXTX
2.5V RX
TX/RX GND
Termination Supply RX
2.5V TX
Termination Supply TX
Serial Loopback Path
Parallel Loopback Path
BREFCLK
BREFCLK2
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RocketIO Transceiver Instantiations
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Tabl e 1-4 lists the sixteen gigabit transceiver primitives provided. These primitives carry attributes
set to default values for the communications protocols listed in Ta ble 1-2. Data widths of one, two,
and four bytes are selectable for each protocol.
There are two ways to modify the RocketIO transceiver:
• Static properties can be set through attributes in the HDL code. Use of attributes are covered in
detail in “Primitive Attributes,” page 29.
• Dynamic changes can be made by the ports of the primitives
The RocketIO transceiver consists of the Physical Media Attachment (PMA) and Physical Coding
Sublayer (PCS). The PMA contains the serializer/deserializer (SERDES), TX and RX buffers, clock
generator, and clock recovery circuitry. The PCS contains the 8B/10B encoder/decoder and the
elastic buffer supporting channel bonding and clock correction. The PCS also handles Cyclic
Redundancy Check (CRC). Refer again to Figure 1-1, showing the RocketIO transceiver top-level
block diagram and FPGA interface signals.
RocketIO Transceiver Instantiations
For the different clocking schemes, several things must change, including the clock frequency for
USRCLK and USRCLK2 discussed in “Digital Clock Manager (DCM) Examples” in Chapter 2.
The data and control ports for GT_CUSTOM must also reflect this change in data width by
concatenating zeros onto inputs and wires for outputs for Verilog designs, and by setting outputs to
open and concatenating zeros on unused input bits for VHDL designs.
HDL Code Examples
Please use the Architecture Wizard to create instantiation templates. This wizard creates code and
instantiation templates that define the attributes for a specific application.
Table 1-4: Supported RocketIO Transceiver Primitives
Primitives Description Primitive Description
GT_C US TO M
Fully customizable
by user
GT_X AU I_ 2
10-Gb Ethernet,
2-byte data path
GT_FIBRE_CHAN_1
Fibre Channel,
1-byte data path
GT_X AU I_ 4
10-Gb Ethernet,
4-byte data path
GT_FIBRE_CHAN_2
Fibre Channel,
2-byte data path
GT_INFINIBAND_1
Infiniband, 1-byte
data path
GT_FIBRE_CHAN_4
Fibre Channel,
4-byte data path
GT_INFINIBAND_2
Infiniband, 2-byte
data path
GT_ETHERNET_1
Gigabit Ethernet,
1-byte data path
GT_INFINIBAND_4
Infiniband, 4-byte
data path
GT_ETHERNET_2
Gigabit Ethernet,
2-byte data path
GT_AURORA_1
Xilinx protocol,
1-byte data path
GT_ETHERNET_4
Gigabit Ethernet,
4-byte data path
GT_AURORA_2
Xilinx protocol,
2-byte data path
GT_XAUI_1
10-Gb Ethernet,
1-byte data path
GT_AURORA_4
Xilinx protocol,
4-byte data path
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List of Available Ports
The RocketIO transceiver primitives contain 50 ports, with the exception of the 46-port
GT_ETHERNET and GT_FIBRE_CHAN primitives. The differential serial data ports (RXN, RXP,
TXN, and TXP) are connected directly to external pads; the remaining 46 ports are all accessible
from the FPGA logic (42 ports for GT_ETHERNET and GT_FIBRE_CHAN).
Tabl e 1-5 contains the port descriptions of all primitives.
Table 1-5: GT_CUSTOM
(1)
, GT_AURORA, GT_FIBRE_CHAN
(2)
, GT_ETHERNET
(2)
,
GT_INFINIBAND, and GT_XAUI Primitive Ports
Port I/O
Port
Size
Definition
BREFCLK I 1 This high-quality reference clock uses dedicated routing to improve jitter for
serial speeds of 2.5 Gb/s or greater. See Table 2-2, page 40 for usage cases.
BREFCLK2 I 1 Alternative to BREFCLK. Can be selected by REFCLKSEL.
CHBONDDONE
(2)
O 1 Indicates a receiver has successfully completed channel bonding when asserted
High.
CHBONDI
(2)
I 4 The channel bonding control that is used only by “slaves” which is driven by a
transceiver's CHBONDO port.
CHBONDO
(2)
O 4 Channel bonding control that passes channel bonding and clock correction
control to other transceivers.
CONFIGENABLE I 1 Reconfiguration enable input (unused)
CONFIGIN I 1 Data input for reconfiguring transceiver (unused)
CONFIGOUT O 1 Data output for configuration readback (unused)
ENCHANSYNC
(2)
I 1 Comes from the core to the transceiver and enables the transceiver to perform
channel bonding
ENMCOMMAALIGN I 1 Selects realignment of incoming serial bitstream on minus-comma. High
realigns serial bitstream byte boundary when minus-comma is detected.
ENPCOMMAALIGN I 1 Selects realignment of incoming serial bitstream on plus-comma. High realigns
serial bitstream byte boundary when plus-comma is detected.
LOOPBACK I 2 Selects the two loopback test modes. Bit 1 is for serial loopback and bit 0 is for
internal parallel loopback.
POWERDOWN I 1 Shuts down both the receiver and transmitter sides of the transceiver when
asserted High. This decreases the power consumption while the transceiver is
shut down. This input is asynchronous.
REFCLK I 1 High-quality reference clock driving transmission (reading TX FIFO, and
multiplied for parallel/serial conversion) and clock recovery. REFCLK
frequency is accurate to ±100 ppm. This clock originates off the device, is
routed through fabric interconnect, and is selected by REFCLKSEL.
REFCLK2 I 1 An alternative to REFCLK. Can be selected by REFCLKSEL.
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REFCLKSEL I 1 Selects the reference clock to use:
Low = selects REFCLK if REF_CLK_V_SEL = 0
selects BREFCLK if REF_CLK_V_SEL = 1
High = selects REFCLK2 if REF_CLK_V_SEL = 0
selects BREFCLK2 if REF_CLK_V_SEL = 1
See “REF_CLK_V_SEL,” page 32.
RXBUFSTATUS O 2 Receiver elastic buffer status. Bit 1 indicates if an overflow/underflow error
has occurred when asserted High. Bit 0 indicates that the buffer is at least halffull when asserted High.
RXCHARISCOMMA
(3)
O 1, 2, 4 Similar to RXCHARISK except that the data is a comma.
RXCHARISK
(3)
O 1, 2, 4 If 8B/10B decoding is enabled, it indicates that the received data is a
K-character when asserted High. Included in Byte-mapping. If 8B/10B
decoding is bypassed, it remains as the first bit received (Bit “a”) of the 10-bit
encoded data (see Figure 2-14, page 66).
RXCHECKINGCRC O 1 CRC status for the receiver. Asserts High to indicate that the receiver has
recognized the end of a data packet. Only meaningful if RX_CRC_USE =
TRUE.
RXCLKCORCNT O 3 Status that denotes occurrence of clock correction or channel bonding. This
status is synchronized on the incoming RXDATA. See “RXCLKCORCNT,”
page 77.
RXCOMMADET O 1 Signals that a comma has been detected in the data stream.
To assure signal is reliably brought out to the fabric for different data paths, this
signal may remain High for more than one USRCLK/USRCLK2 cycle.
RXCRCERR O 1 Indicates if the CRC code is incorrect when asserted High. Only meaningful if
RX_CRC_USE = TRUE.
RXDATA
(3)
O 8, 16, 32 Up to four bytes of decoded (8B/10B encoding) or encoded (8B/10B bypassed)
receive data.
RXDISPERR
(3)
O 1, 2, 4 If 8B/10B encoding is enabled it indicates whether a disparity error has
occurred on the serial line. Included in Byte-mapping scheme.
RXLOSSOFSYNC O 2 Status related to byte-stream synchronization (RX_LOSS_OF_SYNC_FSM)
If RX_LOSS_OF_SYNC_FSM = TRUE, RXLOSSOFSYNC indicates the
state of the FSM:
Bit 1 = Loss of sync (High)
Bit 0 = Resync state (High)
If RX_LOSS_OF_SYNC_FSM = FALSE, RXLOSSOFSYNC indicates:
Bit 1 = Received data invalid (High)
Bit 0 = Channel bonding sequence recognized (High)
RXN
(4)
I 1 Serial differential port (FPGA external)
Table 1-5: GT_CUSTOM
(1)
, GT_AURORA, GT_FIBRE_CHAN
(2)
, GT_ETHERNET
(2)
,
GT_INFINIBAND, and GT_XAUI Primitive Ports (Continued)
Port I/O
Port
Size
Definition
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RXNOTINTABLE
(3)
O 1, 2, 4 Status of encoded data when the data is not a valid character when asserted
High. Applies to the byte-mapping scheme.
RXP
(4)
I 1 Serial differential port (FPGA external)
RXPOLARITY I 1 Similar to TXPOLARITY, but for RXN and RXP. When de-asserted, assumes
regular polarity. When asserted, reverses polarity.
RXREALIGN O 1 Signal from the PMA denoting that the byte alignment with the serial data
stream changed due to a comma detection. Asserted High when alignment
occurs.
RXRECCLK O 1 Clock recovered from the data stream by dividing its speed by 20.
RXRESET I 1 Synchronous RX system reset that “recenters” the receive elastic buffer. It also
resets 8B/10B decoder, comma detect, channel bonding, clock correction logic,
and other internal receive registers. It does not reset the receiver PLL.
RXRUNDISP
(3)
O 1, 2, 4 Signals the running disparity (0 = negative, 1 = positive) in the received serial
data. If 8B/10B encoding is bypassed, it remains as the second bit received (Bit
“b”) of the 10-bit encoded data (see Figure 2-14, page 66).
RXUSRCLK I 1 Clock from a DCM or a BUFG that is used for reading the RX elastic buffer. It
also clocks CHBONDI and CHBONDO in and out of the transceiver.
Typically, the same as TXUSRCLK.
RXUSRCLK2 I 1 Clock output from a DCM that clocks the receiver data and status between the
transceiver and the FPGA core. Typically the same as TXUSRCLK2. The
relationship between RXUSRCLK and RXUSRCLK2 depends on the width of
RXDATA.
TXBUFERR O 1 Provides status of the transmission FIFO. If asserted High, an
overflow/underflow has occurred. When this bit becomes set, it can only be
reset by asserting TXRESET.
TXBYPASS8B10B
(3)
I 1, 2, 4 This control signal determines whether the 8B/10B encoding is enabled or
bypassed. If the signal is asserted High, the encoding is bypassed. This creates
a 10-bit interface to the FPGA core. See the 8B/10B section for more details.
TXCHARDISPMODE
(3)
I 1, 2, 4 If 8B/10B encoding is enabled, this bus determines what mode of disparity is
to be sent. When 8B/10B is bypassed, this becomes the first bit transmitted (Bit
“a”) of the 10-bit encoded TXDATA bus section (see Figure 2-13, page 66) for
each byte specified by the byte-mapping.
TXCHARDISPVAL
(3)
I 1, 2, 4 If 8B/10B encoding is enabled, this bus determines what type of disparity is to
be sent. When 8B/10B is bypassed, this becomes the second bit transmitted
(Bit “b”) of the 10-bit encoded TXDATA bus section (see Figure 2-13,
page 66) for each byte specified by the byte-mapping section.
TXCHARISK
(3)
I 1, 2, 4 If 8B/10B encoding is enabled, this control bus determines if the transmitted
data is a K-character or a Data character. A logic High indicates a K-character.
Table 1-5: GT_CUSTOM
(1)
, GT_AURORA, GT_FIBRE_CHAN
(2)
, GT_ETHERNET
(2)
,
GT_INFINIBAND, and GT_XAUI Primitive Ports (Continued)
Port I/O
Port
Size
Definition
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TXDATA
(3)
I 8, 16, 32 Transmit data that can be 1, 2, or 4 bytes wide, depending on the primitive
used. TXDATA [7:0] is always the last byte transmitted. The position of the
first byte depends on selected TX data path width.
TXFORCECRCERR I 1 Specifies whether to insert error in computed CRC.
When TXFORCECRCERR = TRUE, the transmitter corrupts the correctly
computed CRC value by XORing with the bits specified in attribute
TX_CRC_FORCE_VALUE. This input can be used to test detection of CRC
errors at the receiver.
TXINHIBIT I 1 If a logic High, the TX differential pairs are forced to be a constant 1/0.
TXN = 1, TXP = 0
TXKERR
(3)
O 1, 2, 4 If 8B/10B encoding is enabled, this signal indicates (High) when the
K-character to be transmitted is not a valid K-character. Bits correspond to the
byte-mapping scheme.
TXN
(4)
O 1 Transmit differential port (FPGA external)
TXP
(4)
O 1 Transmit differential port (FPGA external)
TXPOLARITY I 1 Specifies whether or not to invert the final transmitter output. Able to reverse
the polarity on the TXN and TXP lines. Deasserted sets regular polarity.
Asserted reverses polarity.
TXRESET I 1 Synchronous TX system reset that “recenters” the transmit elastic buffer. It
also resets 8B/10B encoder and other internal transmission registers. It does
not reset the transmission PLL.
TXRUNDISP
(3)
O 1, 2, 4 Signals the running disparity after this byte is encoded. Low indicates negative
disparity, High indicates positive disparity.
TXUSRCLK I 1 Clock output from a DCM or a BUFG that is clocked with a reference clock.
This clock is used for writing the TX buffer and is frequency-locked to the
reference clock.
TXUSRCLK2 I 1 Clock output from a DCM that clocks transmission data and status and
reconfiguration data between the transceiver an the FPGA core. The ratio
between TXUSRCLK and TXUSRCLK2 depends on the width of TXDATA.
Notes:
1. The GT_CUSTOM ports are always the maximum port size.
2. GT_FIBRE_CHAN and GT_ETHERNET ports do not have the three CHBOND** or ENCHANSYNC ports.
3. The port size changes with relation to the primitive selected, and also correlates to the byte mapping.
4. External ports only accessible from package pins.
Table 1-5: GT_CUSTOM
(1)
, GT_AURORA, GT_FIBRE_CHAN
(2)
, GT_ETHERNET
(2)
,
GT_INFINIBAND, and GT_XAUI Primitive Ports (Continued)
Port I/O
Port
Size
Definition
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Primitive Attributes
The primitives also contain attributes set by default to specific values controlling each specific
primitive’s protocol parameters. Included are channel-bonding settings (for primitives supporting
channel bonding), clock correction sequences, and CRC. Tab le 1-6 shows a brief description of each
attribute. Table 1- 7 and Table 1-8 have the default values of each primitive.
Table 1-6: RocketIO Transceiver Attributes
Attribute Description
ALIGN_COMMA_MSB TRUE/FALSE controls the alignment of detected commas within the transceiver’s
2-byte-wide data path.
FALSE: Align commas within a 10-bit alignment range. As a result the comma
is aligned to either RXDATA[15:8} byte or RXDATA [7:0] byte in the
transceivers internal data path.
TRUE: Aligns comma with 20-bit alignment range.
As a result aligns on the RXDATA[15:8] byte.
Notes:
1. If protocols (like Gigabit Ethernet) are oriented in byte pairs with commas always in even
(first) byte formation, this can be set to TRUE. Otherwise, it should be set to FALSE.
2. For 32-bit data path primitives, see “32-bit Alignment Design,” page 95.
3. This attribute is only modifiable in the GT_CUSTOM primitive.
CHAN_BOND_LIMIT Integer 1-31 that defines maximum number of bytes a slave receiver can read
following a channel bonding sequence and still successfully align to that sequence.
CHAN_BOND_MODE STRING
OFF, MASTER, SLAVE_1_HOP, SLAVE_2_HOPS
OFF: No channel bonding involving this transceiver.
MASTER: This transceiver is master for channel bonding. Its CHBONDO port
directly drives CHBONDI ports on one or more SLAVE_1_HOP transceivers.
SLAVE_1_HOP: This transceiver is a slave for channel bonding.
SLAVE_1_HOP’s CHBONDI is directly driven by a MASTER transceiver
CHBONDO port. SLAVE_1_HOP’s CHBONDO port can directly drive
CHBONDI ports on one or more SLAVE_2_HOPS transceivers.
SLAVE_2_HOPS: This transceiver is a slave for channel bonding.
SLAVE_2_HOPS CHBONDI is directly driven by a SLAVE_1_HOP
CHBONDO port.
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Primitive Attributes
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CHAN_BOND_OFFSET Integer 0-15 that defines offset (in bytes) from channel bonding sequence for
realignment. It specifies the first elastic buffer read address that all channel-bonded
transceivers have immediately after channel bonding.
CHAN_BOND_WAIT specifies the number of bytes that the master transceiver
passes to RXDATA, starting with the channel bonding sequence, before the
transceiver executes channel bonding (alignment) across all channel-bonded
transceivers.
CHAN_BOND_OFFSET specifies the first elastic buffer read address that all
channel-bonded transceivers have immediately after channel bonding (alignment),
as a positive offset from the beginning of the matched channel bonding sequence in
each transceiver.
For optimal performance of the elastic buffer, CHAN_BOND_WAIT and
CHAN_BOND_OFFSET should be set to the same value (typically 8).
CHAN_BOND_ONE_SHOT TRUE/FALSE that controls repeated execution of channel bonding.
FALSE: Master transceiver initiates channel bonding whenever possible
(whenever channel-bonding sequence is detected in the input) as long as input
ENCHANSYNC is High and RXRESET is Low.
TRUE: Master transceiver initiates channel bonding only the first time it is
possible (channel bonding sequence is detected in input) following negated
RXRESET and asserted ENCHANSYNC. After channel-bonding alignment is
done, it does not occur again until RXRESET is asserted and negated, or until
ENCHANSYNC is negated and reasserted.
Always set Slave transceivers CHAN_BOND_ONE_SHOT to FALSE.
CHAN_BOND_SEQ_*_* 11-bit vectors that define the channel bonding sequence. The usage of these vectors
also depends on CHAN_BOND_SEQ_LEN and CHAN_BOND_SEQ_2_USE. See
“Receiving Vitesse Channel Bonding Sequence,” page 66, for format.
CHAN_BOND_SEQ_2_USE Controls use of second channel bonding sequence.
FALSE: Channel bonding uses only one channel bonding sequence defined by
CHAN_BOND_SEQ_1_1...4.
TRUE: Channel bonding uses two channel bonding sequences defined by:
CHAN_BOND_SEQ_1_1...4 and
CHAN_BOND_SEQ_2_1...4
as further constrained by CHAN_BOND_SEQ_LEN.
CHAN_BOND_SEQ_LEN Integer 1-4 defines length in bytes of channel bonding sequence. This defines the
length of the sequence the transceiver matches to detect opportunities for channel
bonding.
CHAN_BOND_WAIT Integer 1-15 that defines the length of wait (in bytes) after seeing channel bonding
sequence before executing channel bonding.
Table 1-6: RocketIO Transceiver Attributes (Continued)
Attribute Description
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CLK_COR_INSERT_IDLE_FLAG TRUE/FALSE controls whether RXRUNDISP input status denotes running
disparity or inserted-idle flag.
FALSE: RXRUNDISP denotes running disparity when RXDATA is decoded
data.
TRUE: RXRUNDISP is raised for the first byte of each inserted (repeated) clock
correction (“Idle”) sequence (when RXDATA is decoded data).
CLK_COR_KEEP_IDLE TRUE/FALSE controls whether or not the final byte stream must retain at least one
clock correction sequence.
FALSE: Transceiver can remove all clock correction sequences to further
recenter the elastic buffer during clock correction.
TRUE: In the final RXDATA stream, the transceiver must leave at least one
clock correction sequence per continuous stream of clock correction
sequences.
CLK_COR_REPEAT_WAIT Integer 0 - 31 controls frequency of repetition of clock correction operations.
This attribute specifies the minimum number of RXUSRCLK cycles without clock
correction that must occur between successive clock corrections. If this attribute is
zero, no limit is placed on how frequently clock correction can occur.
CLK_COR_SEQ_*_* 11-bit vectors that define the sequence for clock correction. The attribute used
depends on the CLK_COR_SEQ_LEN and CLK_COR_SEQ_2_USE.
CLK_COR_SEQ_2_USE TRUE/FALSE controls use of second clock correction sequence.
FALSE: Clock correction uses only one clock correction sequence defined by
CLK_COR_SEQ_1_1...4.
TRUE: Clock correction uses two clock correction sequences defined by:
CLK_COR_SEQ_1_1...4 and
CLK_COR_SEQ_2_1...4
as further constrained by CLK_COR_SEQ_LEN.
CLK_COR_SEQ_LEN Integer that defines the length of the sequence the transceiver matches to detect
opportunities for clock correction. It also defines the size of the correction, since the
transceiver executes clock correction by repeating or skipping entire clock
correction sequences.
CLK_CORRECT_USE TRUE/FALSE controls the use of clock correction logic.
FALSE: Permanently disable execution of clock correction (rate matching).
Clock RXUSRCLK must be frequency-locked with RXRECCLK in this case.
TRUE: Enable clock correction (normal mode).
COMMA_10B_MASK This 10-bit vector defines the mask that is ANDed with the incoming serial bit
stream before comparison against PCOMMA_10B_VALUE and
MCOMMA_10B_VALUE.
CRC_END_OF_PKT NOTE: This attribute is only valid when CRC_FORMAT = USER_MODE.
K28_0, K28_1, K28_2, K28_3, K28_4, K28_5, K28_6, K28_7, K23_7, K27_7,
K29_7, K30_7. End-of-packet (EOP) K-character for USER_MODE CRC. Must be
one of the 12 legal K-character values.
Table 1-6: RocketIO Transceiver Attributes (Continued)
Attribute Description
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Primitive Attributes
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CRC_FORMAT ETHERNET, INFINIBAND, FIBRE_CHAN, USER_MODE CRC algorithm
selection. Modifiable only for GT_AURORA_n, GT_XAUI_n, and GT_CUSTOM.
USER_MODE allows user definition of Start of Packet (SOP) and End of Packet
(EOP) K-characters.
CRC_START_OF_PKT NOTE: This attribute is only valid when CRC_FORMAT = USER_MODE.
K28_0, K28_1, K28_2, K28_3, K28_4, K28_5, K28_6, K28_7, K23_7, K27_7,
K29_7, K30_7. Start-of-packet (SOP) K-character for USER_MODE CRC. Must
be one of the twelve legal K-character values.
DEC_MCOMMA_DETECT TRUE/FALSE controls the raising of per-byte flag RXCHARISCOMMA on minus-
comma.
DEC_PCOMMA_DETECT TRUE/FALSE controls the raising of per-byte flag RXCHARISCOMMA on plus-
comma.
DEC_VALID_COMMA_ONLY TRUE/FALSE controls the raising of RXCHARISCOMMA on an invalid comma.
FALSE: Raise RXCHARISCOMMA on:
0011111xxx
(if DEC_PCOMMA_DETECT is TRUE)
and/or on:
1100000xxx
(if DEC_MCOMMA_DETECT is TRUE)
regardless of the settings of the xxx bits.
TRUE: Raise RXCHARISCOMMA only on valid characters that are in the
8B/10B translation.
MCOMMA_10B_VALUE This 10-bit vector defines minus-comma for the purpose of raising
RXCOMMADET and realigning the serial bit stream byte boundary. This definition
does not affect 8B/10B encoding or decoding. Also see COMMA_10B_MASK.
MCOMMA_DETECT TRUE/FALSE indicates whether to raise or not raise RXCOMMADET when
minus-comma is detected.
PCOMMA_10B_VALUE This 10-bit vector defines plus-comma for the purpose of raising RXCOMMADET
and realigning the serial bit stream byte boundary. This definition does not affect
8B/10B encoding or decoding. Also see COMMA_10B_MASK.
PCOMMA_DETECT TRUE/FALSE indicates whether to raise or not raise RXCOMMADET when plus-
comma is detected.
REF_CLK_V_SEL 1/0:
1: Selects BREFCLK/BREFCLK2 for 2.5 Gb/s or greater serial speeds.
0: Selects REFCLK/REFCLK2 for serial speeds under 2.5 Gb/s.
RX_BUFFER_USE Always set to TRUE.
RX_CRC_USE,
TX_CRC_USE
TRUE/FALSE determines if CRC is used or not.
RX_DATA_WIDTH,
TX_DATA_WIDTH
Integer (1, 2, or 4). Relates to the data width of the FPGA fabric interface.
Table 1-6: RocketIO Transceiver Attributes (Continued)
Attribute Description
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RX_DECODE_USE This determines if the 8B/10B decoding is bypassed. FALSE denotes that it is
bypassed.
RX_LOS_INVALID_INCR Power of two in a range of 1 to 128 that denotes the number of valid characters
required to “cancel out” appearance of one invalid character for loss of sync
determination.
RX_LOS_THRESHOLD Power of two in a range of 4 to 512. When divided by RX_LOS_INVALID_INCR,
denotes the number of invalid characters required to cause FSM transition to “sync
lost” state.
RX_LOSS_OF_SYNC_FSM TRUE/FALSE denotes the nature of RXLOSSOFSYNC output.
TRUE: RXLOSSOFSYNC outputs the state of the FSM bits.
See “RXLOSSOFSYNC,” page 26, for details.
SERDES_10B Denotes whether the reference clock is 1/10 or 1/20 the serial bit rate.
TRUE: 1/10
FALSE: 1/20
FALSE supports a serial bitstream range of 1.0 Gb/s to 3.125 Gb/s.
TRUE supports a range of 600 Mb/s to 1.0 Gb/s.
See “Half-Rate Clocking Scheme,” page 55.
TERMINATION_IMP Integer (50 or 75). Termination impedance of either 50Ω or 75Ω. Refers to both the
RX and TX.
TX_BUFFER_USE Always set to TRUE.
TX_CRC_FORCE_VALUE 8-bit vector. Value to corrupt TX CRC computation when input
TXFORCECRCERR is High. This value is XORed with the correctly computed
CRC value, corrupting the CRC if TX_CRC_FORCE_VALUE is nonzero. This can
be used to test CRC error detection in the receiver downstream.
TX_DIFF_CTRL An integer value (400, 500, 600, 700, or 800) representing 400 mV, 500 mV,
600 mV, 700 mV, or 800 mV of voltage difference between the differential lines.
Twice this value is the peak-peak voltage.
TX_PREEMPHASIS An integer value (0-3) that sets the output driver pre-emphasis to improve output
waveform shaping for various load conditions. Larger value denotes stronger preemphasis. See pre-emphasis values in Table 3-2, page 102.
Table 1-6: RocketIO Transceiver Attributes (Continued)
Attribute Description
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Modifiable Primitives
As shown in Table 1-7 and Table 1-8 , only certain attributes are modifiable for any primitive. These
attributes help to define the protocol used by the primitive. Only the GT_CUSTOM primitive allows
the user to modify all of the attributes to a protocol not supported by another transceiver primitive.
This allows for complete flexibility. The other primitives allow modification of the analog attributes
of the serial data lines and several channel-bonding values.
Table 1-7: Default Attribute Values: GT_AURORA, GT_CUSTOM, GT_ETHERNET
Attribute
Default
GT_AURORA
Default
GT_CUSTOM
(1)
Default
GT_ETHERNET
ALIGN_COMMA_MSB FALSE FALSE FALSE
CHAN_BOND_LIMIT 16 16 1
CHAN_BOND_MODE OFF
(2)
OFF OFF
CHAN_BOND_OFFSET 8 8 0
CHAN_BOND_ONE_SHOT FALSE
(2)
FALSE TRU E
CHAN_BOND_SEQ_1_1 00101111100 00000000000 00000000000
CHAN_BOND_SEQ_1_2 00000000000 00000000000 00000000000
CHAN_BOND_SEQ_1_3 00000000000 00000000000 00000000000
CHAN_BOND_SEQ_1_4 00000000000 00000000000 00000000000
CHAN_BOND_SEQ_2_1 00000000000 00000000000 00000000000
CHAN_BOND_SEQ_2_2 00000000000 00000000000 00000000000
CHAN_BOND_SEQ_2_3 00000000000 00000000000 00000000000
CHAN_BOND_SEQ_2_4 00000000000 00000000000 00000000000
CHAN_BOND_SEQ_2_USE FALSE FALSE FALSE
CHAN_BOND_SEQ_LEN 1 1 1
CHAN_BOND_WAIT 8 8 7
CLK_COR_INSERT_IDLE_FLAG FALSE
(2)
FALSE FALSE
(2)
CLK_COR_KEEP_IDLE FALSE
(2)
FALSE FALSE
(2)
CLK_COR_REPEAT_WAIT 1
(2)
11
(2)
CLK_COR_SEQ_1_1 00111110111 00000000000 00110111100
CLK_COR_SEQ_1_2 00111110111 00000000000 00001010000
CLK_COR_SEQ_1_3 00111110111
(5)
00000000000 00000000000
CLK_COR_SEQ_1_4 00111110111
(5)
00000000000 00000000000
CLK_COR_SEQ_2_1 00000000000 00000000000 00000000000
CLK_COR_SEQ_2_2 00000000000 00000000000 00000000000
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CLK_COR_SEQ_2_3 00000000000 00000000000 00000000000
CLK_COR_SEQ_2_4 00000000000 00000000000 00000000000
CLK_COR_SEQ_2_USE FALSE FALSE FALSE
CLK_COR_SEQ_LEN 4
(4)
12
CLK_CORRECT_USE TRUE TRUE TRUE
COMMA_10B_MASK 1111111111 1111111000 1111111000
CRC_END_OF_PKT K29_7 K29_7
Note (6)
CRC_FORMAT USER_MODE USER_MODE ETHERNET
CRC_START_OF_PKT K27_7 K27_7
Note (6)
DEC_MCOMMA_DETECT TRUE TRUE TRUE
DEC_PCOMMA_DETECT TRUE TRUE TRUE
DEC_VALID_COMMA_ONLY TRUE TRUE TRUE
MCOMMA_10B_VALUE 1100000101 1100000000 1100000000
MCOMMA_DETECT TRUE TRUE TRUE
PCOMMA_10B_VALUE 0011111010 0011111000 0011111000
PCOMMA_DETECT TRUE TRUE TRUE
REF_CLK_V_SEL 0 0 0
RX_BUFFER_USE TRUE TRUE TRUE
RX_CRC_USE FALSE
(2)
FALSE FALSE
(2)
RX_DATA_WIDTH N
(3)
2N
(3)
RX_DECODE_USE TRUE TRUE TRUE
RX_LOS_INVALID_INCR 1
(2)
11
(2)
RX_LOS_THRESHOLD 4
(2)
44
(2)
RX_LOSS_OF_SYNC_FSM TRUE
(2)
TRUE TRUE
(2)
SERDES_10B FALSE
(2)
FALSE FALSE
(2)
TERMINATION_IMP 50
(2)
50 50
(2)
TX_BUFFER_USE TRUE TRUE TRUE
TX_CRC_FORCE_VALUE 11010110
(2)
11010110 11010110
(2)
TX_CRC_USE FALSE
(2)
FALSE FALSE
(2)
TX_DATA_WIDTH N
(3)
2N
(3)
Table 1-7: Default Attribute Values: GT_AURORA, GT_CUSTOM, GT_ETHERNET (Continued)
Attribute
Default
GT_AURORA
Default
GT_CUSTOM
(1)
Default
GT_ETHERNET
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Modifiable Primitives
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TX_DIFF_CTRL 500
(2)
500 500
(2)
TX_PREEMPHASIS 0
(2)
00
(2)
Notes:
1. All GT_CUSTOM attributes are modifiable.
2. Modifiable attribute for specific primitives.
3. Depends on primitive used: either 1, 2, or 4.
4. Attribute value only when RX_DATA_WIDTH is 4. When RX_DATA_WIDTH is 1 or 2, attribute value is 2.
5. Attribute value only when RX_DATA_WIDTH is 4. When RX_DATA_WIDTH is 1 or 2, attribute value is 0.
6. CRC_EOP and CRC_SOP are not applicable for this primitive.
Table 1-7: Default Attribute Values: GT_AURORA, GT_CUSTOM, GT_ETHERNET (Continued)
Attribute
Default
GT_AURORA
Default
GT_CUSTOM
(1)
Default
GT_ETHERNET
Table 1-8: Default Attribute Values: GT_FIBRE_CHAN, GT_INFINIBAND,
and GT_XAUI
Attribute
Default
GT_FIBRE_CHAN
Default
GT_INFINIBAND
Default
GT_XAUI
ALIGN_COMMA_MSB FALSE FALSE FALSE
CHAN_BOND_LIMIT 1 16 16
CHAN_BOND_MODE OFF OFF
(1)
OFF
(1)
CHAN_BOND_OFFSET 0 8 8
CHAN_BOND_ONE_SHOT TRUE FALSE
(1)
FALSE
(1)
CHAN_BOND_SEQ_1_1 00000000000 00110111100 00101111100
CHAN_BOND_SEQ_1_2 00000000000 Lane ID (Modify with
Lane ID)
00000000000
CHAN_BOND_SEQ_1_3 00000000000 00001001010 00000000000
CHAN_BOND_SEQ_1_4 00000000000 00001001010 00000000000
CHAN_BOND_SEQ_2_1 00000000000 00110111100 00000000000
CHAN_BOND_SEQ_2_2 00000000000 Lane ID (Modify with
Lane ID)
00000000000
CHAN_BOND_SEQ_2_3 00000000000 00001000101 00000000000
CHAN_BOND_SEQ_2_4 00000000000 00001000101 00000000000
CHAN_BOND_SEQ_2_USE FALSE TRUE FALSE
CHAN_BOND_SEQ_LEN 1 4 1
CHAN_BOND_WAIT 7 8 8
CLK_COR_INSERT_IDLE_FLAG FALSE
(1)
FAL SE
(1)
FALSE
(1)
CLK_COR_KEEP_IDLE FALSE
(1)
FAL SE
(1)
FALSE
(1)
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CLK_COR_REPEAT_WAIT 2
(1)
1
(1)
1
(1)
CLK_COR_SEQ_1_1 00110111100 00100011100 00100011100
CLK_COR_SEQ_1_2 00010010101 00000000000 00000000000
CLK_COR_SEQ_1_3 00010110101 00000000000 00000000000
CLK_COR_SEQ_1_4 00010110101 00000000000 00000000000
CLK_COR_SEQ_2_1 00000000000 00000000000 00000000000
CLK_COR_SEQ_2_2 00000000000 00000000000 00000000000
CLK_COR_SEQ_2_3 00000000000 00000000000 00000000000
CLK_COR_SEQ_2_4 00000000000 00000000000 00000000000
CLK_COR_SEQ_2_USE FALSE FALSE FALSE
CLK_COR_SEQ_LEN 4 1 1
CLK_CORRECT_USE TRUE TRUE TRUE
COMMA_10B_MASK 1111111000 1111111000 1111111000
CRC_END_OF_PKT
Note (3) Note (3)
K29_7
(1)
CRC_FORMAT FIBRE_CHAN INFINIBAND USER_MODE
(1)
CRC_START_OF_PKT
Note (3) Note (3)
K27_7
(1)
DEC_MCOMMA_DETECT TRUE TRUE TRUE
DEC_PCOMMA_DETECT TRUE TRUE TRUE
DEC_VALID_COMMA_ONLY TRUE TRUE TRUE
Lane ID(INFINBAND ONLY) NA 00000000000
(1)
NA
MCOMMA_10B_VALUE 1100000000 1100000000 1100000000
MCOMMA_DETECT TRUE TRUE TRUE
PCOMMA_10B_VALUE 0011111000 0011111000 0011111000
PCOMMA_DETECT TRUE TRUE TRUE
REF_CLK_V_SEL 0 0 0
RX_BUFFER_USE TRUE TRUE TRUE
RX_CRC_USE FALSE
(1)
FAL SE
(1)
FALSE
(1)
RX_DATA_WIDTH N
(2)
N
(2)
N
(2)
RX_DECODE_USE TRUE TRUE TRUE
Table 1-8: Default Attribute Values: GT_FIBRE_CHAN, GT_INFINIBAND,
and GT_XAUI (Continued)
Attribute
Default
GT_FIBRE_CHAN
Default
GT_INFINIBAND
Default
GT_XAUI
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Byte Mapping
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Byte Mapping
Most of the 4-bit wide status and control buses correlate to a specific byte of TXDATA or RXDATA.
This scheme is shown in Table 1-9. This creates a way to tie all the signals together regardless of the
data path width needed for the GT_CUSTOM. All other primitives with specific data width paths
and all byte-mapped ports are affected by this situation. For example, a 1-byte wide data path has
only 1-bit control and status bits (TXKERR[0]) correlating to the data bits TXDATA[7:0]. Footnote
3 in Table 1- 5 shows the ports that use byte mapping.
RX_LOS_INVALID_INCR 1
(1)
1
(1)
1
(1)
RX_LOS_THRESHOLD 4
(1)
4
(1)
4
(1)
RX_LOSS_OF_SYNC_FSM TRUE
(1)
TRUE
(1)
TRUE
(1)
SERDES_10B FALSE
(1)
FAL SE
(1)
FALSE
(1)
TERMINATION_IMP 50
(1)
50
(1)
50
(1)
TX_BUFFER_USE TRUE TRUE TRUE
TX_CRC_FORCE_VALUE 11010110
(1)
11010110
(1)
11010110
(1)
TX_CRC_USE FALSE
(1)
FAL SE
(1)
FALSE
(1)
TX_DATA_WIDTH N
(2)
N
(2)
N
(2)
TX_DIFF_CTRL 500
(1)
500
(1)
500
(1)
TX_PREEMPHASIS 0
(1)
0
(1)
0
(1)
Notes:
1. Modifiable attribute for specific primitives.
2. Depends on primitive used: either 1, 2, or 4.
3. CRC_EOP and CRC_SOP are not applicable for this primitive.
Table 1-8: Default Attribute Values: GT_FIBRE_CHAN, GT_INFINIBAND,
and GT_XAUI (Continued)
Attribute
Default
GT_FIBRE_CHAN
Default
GT_INFINIBAND
Default
GT_XAUI
Table 1-9: Control/Status Bus Association to Data Bus Byte Paths
Control/Status Bit Data Bits
[0] [7:0]
[1] [15:8]
[2] [23:16]
[3] [31:24]
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Chapter 2
Digital Design Considerations
Clocking
Clock Signals
There are eight clock inputs into each RocketIO transceiver instantiation (Tab le 2-1). REFCLK and
BREFCLK are reference clocks generated from an external source and presented to the FPGA as
differential inputs. The reference clocks connect to the REFCLK or BREFCLK ports of the
RocketIO multi-gigabit transceiver (MGT). While only one of these reference clocks is needed to
drive the MGT, BREFCLK or BREFCLK2 must be used for serial speeds of 2.5 Gb/s or greater.
(See “BREFCLK,” page 41.)
To clock the serial data, the PLL architecture for the transceiver uses the reference clock as the
interpolation source. Removing the reference clock stops the RX and TX PLLs from working.
Therefore, a reference clock must be provided at all times. This is especially important at the end of
configuration when the PMA portion of the MGT requires a reference clock in order to properly
initialize. If a reference clock is not available at this point, the user should toggle the
POWERDOWN pin when the reference clock becomes available to ensure the PMA is properly
initialized.
The reference clock also clocks a Digital Clock Manager (DCM) or a BUFG to generate all of the
other clocks for the MGT. Never run a reference clock through a DCM, since unwanted jitter will be
introduced. Any additional jitter on the reference clock will be transferred to the transceiver’s RX
and TX serial I/O.
It is recommended that all reference clock sources into the FPGA be LVDS or LVPECL IBUFGDS.
The DCI or DT attributes of LVDS are optional. Refer to the Virtex-II Pro Platform FPGA User
Guide (Chapter 3, “Design Considerations”) for a complete listing and discussion of IBUFGDS and
other available I/O primitives. Also see section “Reference Clock” in Chapter 3 of this Guide.
Typically, TXUSRCLK = RXUSRCLK and TXUSRCLK2 = RXUSRCLK2. The transceiver uses
one or two clocks generated by the DCM. As an example, USRCLK and USRCLK2 clocks run at
the same speed if the 2-byte data path is used. The USRCLK must always be frequency-locked to
the reference clock of the RocketIO transceiver when SERDES_10B = FALSE (full-rate operation).
Note:
The reference clock must be at least 50 MHz (for full-rate operation only; 60 MHz for half-
rate operation) with a duty cycle between 45% and 55%, and should have a frequency stability of
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±100 ppm or better, with jitter as low as possible. Module 3 of the Virtex-II Pro data sheet gives
further details.
Table 2-1: Clock Ports
Clock I/Os Description
BREFCLK Input Reference clock used to read the TX FIFO and multiplied by 20 for
parallel-to-serial conversion (20X)
BREFCLK2 Input Alternative to BREFCLK
RXRECCLK Output Recovered clock (from serial data stream) divided by 20. Clocks
data into the elastic buffer.
REFCLK Input Reference clock used to read the TX FIFO and multiplied by 20 for
parallel-to-serial conversion (20X)
REFCLK2 Input Alternative to REFCLK.
REFCLKSEL Input Selects which reference clock is used. 0 selects REFCLK; 1 selects
REFCLK2.
RXUSRCLK Input Clock from FPGA used for reading the RX Elastic Buffer. Clock
signals CHBONDI and CHBONDO into and out of the transceiver.
This clock is typically the same as TXUSRCLK.
TXUSRCLK
(1)
Input Clock from FPGA used for writing the TX Buffer. This clock must
be frequency locked to REFCLK for proper operation.
RXUSRCLK2 Input Clock from FPGA used to clock RX data and status between the
transceiver and FPGA fabric. The relationship between
RXUSRCLK2 and RXUSRCLK depends on the width of the
receiver data path. RXUSRCLK2 is typically the same as
TXUSRCLK2.
TXUSRCLK2
(1)
Input Clock from FPGA used to clock TX data and status between the
transceiver and FPGA fabric. The relationship between
TXUSRCLK2 and TXUSRCLK depends on the width of the
transmission data path.
Notes:
1. TXUSRCLK and TXUSRCLK2 must be driven by clock sources, even if only the receiver of the MGT is being
used.
Table 2-2: Reference Clock Usage
Data Rate Routing
600 Mb/s –
2.499 Gb/s
2.500 Gb/s –
3.125 Gb/s
Can Route
Across Chip?
Can Route
Through BUFG?
REFCLK √√√
BREFCLK √√
Note (1) Note (1)
Notes:
1. Because of dedicated routing to reduce jitter, BREFCLK cannot be routed through the fabric.
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BREFCLK
At speeds of 2.5 Gb/s or greater, REFCLK configuration introduces more than the maximum
allowable jitter to the RocketIO transceiver. For these higher speeds, BREFCLK configuration is
required. The BREFCLK configuration uses dedicated routing resources that reduce jitter.
BREFCLK must enter the FPGA through dedicated clock I/O. BREFCLK can connect to the
BREFCLK inputs of the transceiver and the CLKIN input of the DCM for creation of USRCLKs. If
all the transceivers on a Virtex-II Pro FPGA are to be used, two BREFCLKs must be created, one for
the top of the chip and one for the bottom. These dedicated clocks use the same clock inputs for all
packages:
An attribute (REF_CLK_V_SEL) and a port (REFCLKSEL) determine which reference clock is
used for the MGT PMA block. Figure 2-1 shows how REFCLK and BREFCLK are selected through
use of REFCLKSEL and REF_CLK_V_SEL.
Table 2-3 shows the BREFCLK pin numbers for all packages. Note that these pads must be used for
BREFCLK operations.
Top
BREFCLK
PGCLK4S
Bottom
BREFCLK
PGCLK6P
N GCLK5P N GCLK7S
BREFCLK2
PGCLK2S
BREFCLK2
PGCLK0P
N GCLK3P N GCLK1S
Figure 2-1: REFCLK/BREFCLK Selection Logic
Table 2-3: BREFCLK Pin Numbers
Package
Top Bott o m
BREFCLK
Pin Number
BREFCLK2
Pin Number
BREFCLK
Pin Number
BREFCLK2
Pin Number
FG256 A8/B8 B9/A9 R8/T8 T9/R9
FG456 C11/D11 D12/C12 W11/Y11 Y12/W12
FG676 B13/C13 C14/B14 AD13/AE13 AE14/AD14
FF672 B14/C14 C13/B13 AD14/AE14 AE13/AD13
0
0
0
1
1
1
1.5V
2.5V
REF_CLK_V_SEL
REFCLKSEL refclk_out
to PCS and PMA
refclk
refclk2
brefclk
brefclk2
ug024_35_091802
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FF896 F16/G16 G15/F15 AH16/AJ16 AJ15/AH15
FF1152 H18/J18 J17/H17 AK18/AL18 AL17/AK17
FF1148 N/A N/A N/A N/A
FF1517 E20/D20 J20/K20 AR20/AT20 AL20/AK20
FF1704 G22/F22 F21/G21 AU22/AT22 AT21/AU21
FF1696 N/A N/A N/A N/A
Table 2-3: BREFCLK Pin Numbers
Package
Top Bott o m
BREFCLK
Pin Number
BREFCLK2
Pin Number
BREFCLK
Pin Number
BREFCLK2
Pin Number
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Clocking
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Clock Ratio
USRCLK2 clocks the data buffers. The ability to send/receive parallel data to/from the transceiver
at three different widths requires the user to change the frequency of USRCLK2. This creates a
frequency ratio between USRCLK and USRCLK2. The falling edges of the clocks must align.
Tabl e 2-4 shows the ratios for each of the three data widths.
Digital Clock Manager (DCM) Examples
With at least three different clocking schemes possible on the transceiver, a DCM is the best way to
create these schemes.
Tabl e 2-5 shows typical DCM connections for several transceiver clocks. REFCLK is the input
reference clock for the DCM. The other clocks are generated by the DCM. The DCM establishes a
desired phase relationship between TXUSRCLK, TXUSRCLK2, etc. in the FPGA core and
REFCLK at the pad.
NOTE: The reference clock may be any of the four MGT clocks, including the BREFCLKs.
Table 2-4: Data Width Clock Ratios
Data Width Frequency Ratio of USRCLK\USRCLK2
1 byte 1:2
(1)
2 byte 1:1
4 byte 2:1
(1)
Notes:
1. Each edge of the slower clock must align with the falling edge of the faster clock.
Table 2-5: DCM Outputs for Different DATA_WIDTHs
SERDES_10B
TX_DATA_WIDTH
RX_DATA_WIDTH
REFCLK
TXUSRCLK
RXUSRCLK
TXUSRCLK2
RXUSRCLK2
FALSE 1 CLKIN CLK0 CLK2X180
FALSE 2 CLKIN CLK0 CLK0
FALSE 4 CLKIN CLK180
(1)
CLKDV (divide by 2)
TRUE 1 CLKIN CLKDV (divide by 2) CLK180
(1)
TRUE 2 CLKIN CLKDV (divide by 2) CLKDV (divide by 2)
TRUE 4 CLKIN CLKFX180 (divide by 2) CLKDV (divide by 4)
Notes:
1. Since CLK0 is needed for feedback, it can be used instead of CLK180 to clock USRCLK or USRCLK2 of the transceiver with the use of the
transceiver ’s local inverter, saving a global buffer (BUFG).
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Example 1a: Two-Byte Clock with DCM
The following HDL codes are examples of a simple clock scheme using 2-byte data with both
USRCLK and USRCLK2 at the same frequency. USRCLK_M is the input for both USRCLK and
USRCLK2.
VHDL Template
-- Module: TWO_BYTE_CLK
-- Description: VHDL submodule
-- DCM for 2-byte GT
--
-- Device: Virtex-II Pro Family
--------------------------------------------------------------------library IEEE;
use IEEE.std_logic_1164.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
-entity TWO_BYTE_CLK is
port (
REFCLKIN : in std_logic;
RST : in std_logic;
USRCLK_M : out std_logic;
REFCLK : out std_logic;
LOCK : out std_logic
);
end TWO_BYTE_CLK;
-architecture TWO_BYTE_CLK_arch of TWO_BYTE_CLK is
--
-- Components Declarations:
component BUFG
port (
I : in std_logic;
O : out std_logic
);
end component;
-component IBUFG
port (
I : in std_logic;
Figure 2-2: Two-Byte Clock with DCM
MGT + DCM for 2-Byte Data Path
GT_std_2
REFCLKSEL
REFCLK
TXUSRCLK2
RXUSRCLK2
TXUSRCLK
RXUSRCLK
CLKIN
CLKFB
RST
DCM
CLK0
0
REFCLK_P
BUFG
IBUFGDS
Clocks for 2-Byte Data Path
TXUSRCLK
RXUSRCLK
TXUSRCLK2
RXUSRCLK2
REFCLK
REFCLK_N
ug024_02a_112202
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Clocking
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O : out std_logic
);
end component;
-component DCM
port (
CLKIN : in std_logic;
CLKFB : in std_logic;
DSSEN : in std_logic;
PSINCDEC : in std_logic;
PSEN : in std_logic;
PSCLK : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector ( 7 downto 0 )
);
end component;
--
-- Signal Declarations:
-signal GND : std_logic;
signal CLK0_W : std_logic;
begin
GND <= '0';
--
-- DCM Instantiation
U_DCM: DCM
port map (
CLKIN => REFCLK,
CLKFB => USRCLK_M,
DSSEN => GND,
PSINCDEC => GND,
PSEN => GND,
PSCLK => GND,
RST => RST,
CLK0 => CLK0_W,
LOCKED => LOCK
);
--
-- BUFG Instantiation
U_BUFG: IBUFG
port map (
I => REFCLKIN,
O => REFCLK
);
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U2_BUFG: BUFG
port map (
I => CLK0_W,
O => USRCLK_M
);
end TWO_BYTE_CLK_arch;
Verilog Template
//Module: TWO_BYTE_CLK
//Description: Verilog Submodule
// DCM for 2-byte GT
//
// Device: Virtex-II Pro Family
module TWO_BYTE_CLK (
REFCLKIN,
REFCLK,
USRCLK_M,
DCM_LOCKED
);
input REFCLKIN;
output REFCLK;
output USRCLK_M;
output DCM_LOCKED;
wire REFCLKIN;
wire REFCLK;
wire USRCLK_M;
wire DCM_LOCKED;
wire REFCLKINBUF;
wire clk_i;
DCM dcm1 (
.CLKFB ( USRCLK_M ),
.CLKIN ( REFCLKINBUF ),
.DSSEN ( 1'b0 ),
.PSCLK ( 1'b0 ),
.PSEN ( 1'b0 ),
.PSINCDEC ( 1'b0 ),
.RST ( 1'b0 ),
.CLK0 ( clk_i ),
.CLK90 ( ),
.CLK180 ( ),
.CLK270 ( ),
.CLK2X ( ),
.CLK2X180 ( ),
.CLKDV ( ),
.CLKFX ( ),
.CLKFX180 ( ),
.LOCKED ( DCM_LOCKED ),
.PSDONE ( ),
.STATUS ( )
);
BUFG buf1 (
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Clocking
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.I ( clk_i ),
.O ( USRCLK_M )
);
IBUFG buf2(
.I ( REFCLKIN ),
.O ( REFCLKINBUF )
);
endmodule
Example 1b: Two-Byte Clock without DCM
If TXDATA and RXDATA are not clocked off the FPGA using the respective USRCLK2s, then the
DCM may be removed from the two-byte clocking scheme, as shown in Figure 2-3:
Example 2: Four-Byte Clock
If a 4-byte or 1-byte data path is chosen, the ratio between USRCLK and USRCLK2 changes. The
time it take for the SERDES to serialize the parallel data requires the change in ratios.
The DCM example (Figure 2-4) is detailed for a 4-byte data path. If 3.125 Gb/s is required,
REFCLK is 156 MHz and USRCLK2_M runs at only 78 MHz, including the clocking for any
interface logic. Both USRCLK and USRCLK2 are aligned on the falling edge, since USRCLK_M
is 180° out of phase when using local inverters with the transceiver.
Note:
These local MGT clock input inverters, shown and noted in Figure 2-4, are not included
in the FOUR_BYTE_CLK templates.
VHDL Template
-- Module: FOUR_BYTE_CLK
-- Description: VHDL submodule
Figure 2-3: Two-Byte Clock without DCM
MGT for 2-Byte Data Path (no DCM)
GT_std_2
REFCLKSEL
REFCLK
TXUSRCLK2
RXUSRCLK2
TXUSRCLK
RXUSRCLK
0
REFCLK_P
IBUFGDS BUFG
REFCLK_N
ug024_02b_062404
Note: Implementation tools automatically
instantiate the BUFG. There is no need to
explicitly instantiate in HDL code.
Figure 2-4: Four-Byte Clock
CLKDV
CLKDV_DIVIDE = 2
MGT clock input inverters (acceptable skew)
MGT + DCM for 4-Byte Data Path
GT_std_4
REFCLKSEL
REFCLK
TXUSRCLK2
RXUSRCLK2
TXUSRCLK
RXUSRCLK
CLKIN
CLKFB
RST
DCM
CLK0
0
BUFG
BUFG
Clocks for 4-Byte Data Path
TXUSRCLK
RXUSRCLK
TXUSRCLK2
RXUSRCLK2
REFCLK
UG024_03_112202
REFCLK_P
IBUFGDS
REFCLK_N
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-- DCM for 4-byte GT
--
-- Device: Virtex-II Pro Family
--------------------------------------------------------------------library IEEE;
use IEEE.std_logic_1164.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
-entity FOUR_BYTE_CLK is
port (
REFCLKIN : in std_logic;
RST : in std_logic;
USRCLK_M : out std_logic;
USRCLK2_M : out std_logic;
REFCLK : out std_logic;
LOCK : out std_logic
);
end FOUR_BYTE_CLK;
-architecture FOUR_BYTE_CLK_arch of FOUR_BYTE_CLK is
--
-- Components Declarations:
component BUFG
port (
I : in std_logic;
O : out std_logic
);
end component;
-component IBUFG
port (
I : in std_logic;
O : out std_logic
);
end component;
-component DCM
port (
CLKIN : in std_logic;
CLKFB : in std_logic;
DSSEN : in std_logic;
PSINCDEC : in std_logic;
PSEN : in std_logic;
PSCLK : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
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Clocking
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PSDONE : out std_logic;
STATUS : out std_logic_vector ( 7 downto 0 )
);
end component;
--
-- Signal Declarations:
-signal GND : std_logic;
signal CLK0_W : std_logic;
signal CLKDV_W : std_logic;
signal USRCLK2_M_W: std_logic;
begin
USRCLK2_M <= USRCLK2_M_W;
GND <= '0';
-- DCM Instantiation
U_DCM: DCM
port map (
CLKIN => REFCLK,
CLKFB => USRCLK2_M_W,
DSSEN => GND,
PSINCDEC => GND,
PSEN => GND,
PSCLK => GND,
RST => RST,
CLK0 => CLK0_W,
CLKDV => CLKDV_W,
LOCKED => LOCK
);
-- BUFG Instantiation
U_BUFG: IBUFG
port map (
I => REFCLKIN,
O => REFCLK
);
U2_BUFG: BUFG
port map (
I => CLK0_W,
O => USRCLK_M
);
U3_BUFG: BUFG
port map (
I => CLKDV_W,
O => USRCLK2_M_W
);
end FOUR_BYTE_CLK_arch;
Verilog Template
// Module: FOUR_BYTE_CLK
// Description: Verilog Submodule
// DCM for 4-byte GT
//
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// Device: Virtex-II Pro Family
module FOUR_BYTE_CLK(
REFCLKIN,
REFCLK,
USRCLK_M,
USRCLK2_M,
DCM_LOCKED
);
input REFCLKIN;
output REFCLK;
output USRCLK_M;
output USRCLK2_M;
output DCM_LOCKED;
wire REFCLKIN;
wire REFCLK;
wire USRCLK_M;
wire USRCLK2_M;
wire DCM_LOCKED;
wire REFCLKINBUF;
wire clkdv2;
wire clk_i;
DCM dcm1 (
.CLKFB ( USRCLK_M ),
.CLKIN ( REFCLKINBUF ) ,
.DSSEN ( 1'b0 ),
.PSCLK ( 1'b0 ),
.PSEN ( 1'b0 ),
.PSINCDEC ( 1'b0 ),
.RST ( 1'b0 ),
.CLK0 ( clk_i ),
.CLK90 ( ),
.CLK180 ( ),
.CLK270 ( ),
.CLK2X ( ),
.CLK2X180 ( ),
.CLKDV ( clkdv2 ),
.CLKFX ( ),
.CLKFX180 ( ),
.LOCKED ( DCM_LOCKED ),
.PSDONE ( ),
.STATUS ( )
);
BUFG buf1 (
.I ( clkdv2 ),
.O ( USRCLK2_M )
);
BUFG buf2 (
.I ( clk_i ),
.O ( USRCLK_M )
);
IBUFG buf3(
.I ( REFCLKIN ),
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Clocking
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.O ( REFCLKINBUF )
);
endmodule
Example 3: One-Byte Clock
This is the 1-byte data path width clocking scheme example. USRCLK2_M is twice as fast as
USRCLK_M. It is also phase-shifted 180° for falling edge alignment.
VHDL Template
-- Module: ONE_BYTE_CLK
-- Description: VHDL submodule
-- DCM for 1-byte GT
--
-- Device: Virtex-II Pro Family
--------------------------------------------------------------------library IEEE;
use IEEE.std_logic_1164.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
-entity ONE_BYTE_CLK is
port (
REFCLKIN : in std_logic;
RST : in std_logic;
USRCLK_M : out std_logic;
USRCLK2_M : out std_logic;
REFCLK : out std_logic;
LOCK : out std_logic
);
end ONE_BYTE_CLK;
-architecture ONE_BYTE_CLK_arch of ONE_BYTE_CLK is
--
-- Components Declarations:
component BUFG
port (
I : in std_logic;
O : out std_logic
Figure 2-5: One-Byte Clock
MGT + DCM for 1-Byte Data Path
GT_std_1
REFCLKSEL
REFCLK
TXUSRCLK2
RXUSRCLK2
TXUSRCLK
RXUSRCLK
CLKIN
CLKFB
RST
DCM
CLK2X180
CLK0
0
BUFG
BUFG
Clocks for 1-Byte Data Path
TXUSRCLK
RXUSRCLK
TXUSRCLK2
RXUSRCLK2
REFCLK
UG024_04_112202
REFCLK_P
IBUFGDS
REFCLK_N
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);
end component;
-component IBUFG
port (
I : in std_logic;
O : out std_logic
);
end component;
-component DCM
port (
CLKIN : in std_logic;
CLKFB : in std_logic;
DSSEN : in std_logic;
PSINCDEC : in std_logic;
PSEN : in std_logic;
PSCLK : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector ( 7 downto 0 )
);
end component;
--
-- Signal Declarations:
-signal GND : std_logic;
signal CLK0_W : std_logic;
signal CLK2X180_W : std_logic;
signal USRCLK2_M_W : std_logic;
signal USRCLK_M_W : std_logic;
begin
GND <= '0';
USRCLK2_M <= USRCLK2_M_W;
USRCLK_M <= USRCLK_M_W;
--
-- DCM Instantiation
U_DCM: DCM
port map (
CLKIN => REFCLK,
CLKFB => USRCLK_M,
DSSEN => GND,
PSINCDEC => GND,
PSEN => GND,
PSCLK => GND,
RST => RST,
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Clocking
R
CLK0 => CLK0_W,
CLK2X180 => CLK2X180_W,
LOCKED => LOCK
);
-- BUFG Instantiation
U_BUFG: IBUFG
port map (
I => REFCLKIN,
O => REFCLK
);
U2_BUFG: BUFG
port map (
I => CLK0_W,
O => USRCLK_M_W
);
U4_BUFG: BUFG
port map (
I => CLK2X180_W,
O => USRCLK2_M_W
);
end ONE_BYTE_CLK_arch;
Verilog Template
// Module: ONE_BYTE_CLK
// Description: Verilog Submodule
// DCM for 1-byte GT
// Device: Virtex-II Pro Family
module ONE_BYTE_CLK (
REFCLKIN,
REFCLK,
USRCLK_M,
USRCLK2_M,
DCM_LOCKED
);
input REFCLKIN;
output REFCLK;
output USRCLK_M;
output USRCLK2_M;
output DCM_LOCKED;
wire REFCLKIN;
wire REFCLK;
wire USRCLK_M;
wire USRCLK2_M;
wire DCM_LOCKED;
wire REFCLKINBUF;
wire clk_i;
wire clk_2x_180;
DCM dcm1 (
.CLKFB ( USRCLK_M ),
.CLKIN ( REFCLKINBUF),
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.DSSEN ( 1'b0 ),
.PSCLK ( 1'b0 ),
.PSEN ( 1'b0 ),
.PSINCDEC ( 1'b0 ),
.RST ( 1'b0 ),
.CLK0 ( clk_i ),
.CLK90 ( ),
.CLK180 ( ),
.CLK270 ( ),
.CLK2X ( ),
.CLK2X180 ( clk2x_180 ),
.CLKDV ( ),
.CLKFX ( ),
.CLKFX180 ( ),
.LOCKED ( DCM_LOCKED ),
.PSDONE ( ),
.STATUS ( )
);
BUFG buf1 (
.I ( clk2x_180 ),
.O ( USRCLK2_M )
);
BUFG buf2 (
.I ( clk_i ),
.O ( USRCLK_M )
);
IBUFGbuf3 (
.I ( REFCLKIN ),
.O ( REFCLKINBUF )
);
endmodule
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Clocking
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Half-Rate Clocking Scheme
Some applications require serial speeds between 600 Mb/s and 1 Gb/s. The transceiver attribute
SERDES_10B, which sets the REFCLK multiplier to 10 instead of 20, enables the half-rate speed
range when set to TRUE. With this configuration, the clocking scheme also changes. The figures
below illustrate the three clocking scheme waveforms when SERDES_10B = TRUE.
Figure 2-6: One-Byte Data Path Clocks, SERDES_10B = TRUE
Clocks for 1-Byte Data Path
(SERDES_10B = TRUE)
TXUSRCLK
RXUSRCLK
TXUSRCLK2
RXUSRCLK2
REFCLK
UG024_29_013103
CLKDV
CLKDV = divide by 2
MGT clock input inverters (acceptable skew)
GT_std_1
REFCLKSEL
REFCLK
TXUSRCLK
RXUSRCLK
TXUSRCLK2
RXUSRCLK2
CLKIN
CLKFB
RST
DCM
CLK0
0
BUFG
BUFG
REFCLK_P
IBUFGDS
REFCLK_N
Figure 2-7: Two-Byte Data Path Clocks, SERDES_10B = TRUE
Clocks for 2-Byte Data Path
(SERDES_10B = TRUE)
TXUSRCLK
RXUSRCLK
TXUSRCLK2
RXUSRCLK2
REFCLK
UG024_30_013103
GT_std_2
REFCLKSEL
REFCLK
TXUSRCLK
RXUSRCLK
TXUSRCLK2
RXUSRCLK2
CLKIN
CLKFB
DCM
CLK0
CLKDV
0
BUFG
BUFG
REFCLK_P
IBUFGDS
REFCLK_N
CLKDV = divide by 2
Figure 2-8: Four-Byte Data Path Clocks, SERDES_10B = TRUE
Clocks for 4-Byte Data Path
(SERDES_10B = TRUE)
TXUSRCLK
RXUSRCLK
TXUSRCLK2
RXUSRCLK2
REFCLK
UG024_31_013103
GT_std_4
REFCLKSEL
REFCLK
TXUSRCLK
RXUSRCLK
TXUSRCLK2
RXUSRCLK2
CLKIN
CLKFB
DCM
CLK_FX180
CLK0
CLKDV
0
BUFG
BUFG
BUFG
REFCLK_P
IBUFGDS
REFCLK_N
CLKDV = divide by 4
CLK_FX = divide by 2
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Multiplexed Clocking Scheme with DCM
Following configuration of the FPGA, some applications might need to change the frequency of its
REFCLK depending on the protocol used. Figure 2-9 shows how the design can use two different
reference clocks connected to two different DCMs. The clocks are then multiplexed before input
into the RocketIO transceiver.
User logic can be designed to determine during auto negotiation if the reference clock used for the
transceiver is incorrect. If so, the transceiver must then be reset and another reference clock selected.
Multiplexed Clocking Scheme without DCM
As with “Example 1b: Two-Byte Clock without DCM”, the DCMs shown in Figure 2-9 may be
removed if TXDATA and RXDATA are not clocked off the FPGA. (See Figure 2-10.) However, the
transceiver must still be reset when clocks are switched.
Figure 2-9: Multiplexed REFCLK with DCM
REFCLKSEL
GT_std_2
REFCLK
REFCLK2
REFCLKSEL
TXUSRCLK2
RXUSRCLK2
TXUSRCLK
RXUSRCLK
CLKIN
CLKFB
RST
DCM
CLK0
CLK0
BUFGMUX
CLKIN
CLKFB
RST
DCM
0
1
Use of 2 DCMs is required
to maintain correct
IBUFG/DCM/BUFGMUX topology
for clock skew compensation
UG024_05a_112202
REFCLK_P
IBUFGDS
REFCLK_N
REFCLK2_P
REFCLK2_N
Figure 2-10: Multiplexed REFCLK without DCM
REFCLKSEL
GT_std_2
REFCLK
REFCLK2
REFCLKSEL
TXUSRCLK2
RXUSRCLK2
TXUSRCLK
RXUSRCLK
0
1
UG024_05b_021503
REFCLK_P
IBUFGDS
BUFGMUX
REFCLK_N
REFCLK2_P
REFCLK2_N
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Clocking
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RXRECCLK
RXRECCLK is a recovered clock derived by dividing by 20 the received data stream bit rate
(whether full-rate or half-rate). If clock correction is bypassed, it is not possible to compensate for
differences in the clock embedded in the received data and the REFCLK-created USRCLKs. In this
case, RXRECCLK is used to generate the RXUSRCLKs, as shown in Figure 2-11.
RXRECCLK changes monotonically when it changes from being locked to the reference clock to
being locked to data and vice versa. The recovered bit clock jumps by a maximum of 1/16th of a bit
period every eight RXRECCLK cycles (20 ps for a data rate of 3.125 Gb/s with a 320-ps bit period)
in the interpolator. RXRECCLK is derived from this bit clock through a divide-by-20 process.
When the data input is kept static, however, the recovered clock does not frequency-lock to the
reference clock exactly, but can deviate from it by up to 400 ppm.
Note:
Bypassing the RX elastic buffer is not recommended, as the skew created by the DCM
and routing to global clock resources is uncertain and may cause unreliable performance.
Clock Dependency
All signals used by the FPGA fabric to interact between user logic and the transceiver depend on an
edge of USRCLK2. These signals all have setup and hold times with respect to this clock. For
specific timing values, see Module 3 of the Virtex-II Pro data sheet. The timing relationships are
further discussed and illustrated in Appendix A, “RocketIO Transceiver Timing Model.”
Data Path Latency
With the many configurations of the MGT, the both transmit and receive data path latencies vary.
Below are several tables that provide approximate latencies for common configurations.
Figure 2-11: Using RXRECCLK to Generate RXUSRCLK and RXUSRCLK2
REFCLKSEL
REFCLK
TXUSRCLK2
RXUSRCLK2
TXUSRCLK
RXUSRCLK
RXRECCLK
CLKIN
CLKFB
RST
DCM
CLK0
0
BUFG
UG024_38_112202
REFCLK_P
IBUFGDS
REFCLK_N
BUFG
Table 2-6: Latency through Various Transmitter Components/Processes
Component/Process Latency
TX Fabric/GT Interface
1 Byte Data Path:
2.5 TXUSRCLK2 cycles
1.25 TXUSRCLK cycles
2 Byte Data Path:
1 TXUSRCLK2 cycle
1 TXUSRCLK cycle
4 Byte Data Path:
1.25 TXUSRCLK2 cycles
2.5 TXUSRCLK cycles
TX CRC
included 7 TXUSRCLK cycles
bypassed 1 TXUSRCLK cycle
8B/10B Encoder
included 1 TXUSRCLK cycle
bypassed 1 TXUSRCLK cycle
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Reset/Power Down
The receiver and transmitter have their own synchronous reset inputs. The transmitter reset recenters
the transmission FIFO, and resets all transmitter registers and the 8B/10B encoder. The receiver
reset recenters the receiver elastic buffer, and resets all receiver registers and the 8B/10B decoder.
Neither reset signal has any effect on the PLLs.
After the DCM-locked signal is asserted, the resets can be asserted. The resets must be asserted for
two USRCLK2 cycles to ensure correct initialization of the FIFOs. Although both the transmit and
receive resets can be attached to the same signal, separate signals are preferred. This allows the
elastic buffer to be cleared in case of an over/underflow without affecting the ongoing TX
transmission. The following example is an implementation that resets all three data-width
transceivers.
Additional reset and power control descriptions are given in Table 2-8 and Table 2- 9.
TX FIFO 4 TXUSRCLK cycles (
±0.5)
TX SERDES
SERDES_10B = FALSE:
1.5 TXUSRCLK cycles
SERDES_10B = TRUE:
0.5 TXUSRCLK cycles (approx.)
Table 2-6: Latency through Various Transmitter Components/Processes (Continued)
Component/Process Latency
Table 2-7: Latency through Various Receiver Components/Processes
Component/Process Latency
RX SERDES 1.5 recovered clock (RXRECCLK) cycles
Comma Detect/Realignment
2.5 or 3.5 recovered clock cycles
(some bits bypass one register, depending on comma alignment)
8B/10B Decoder
included 1 recovered clock cycle
bypassed 1 recovered clock cycle
RX FIFO 18 RXUSRCLK cycles (
±0.5)
RX GT/Fabric Interface
1 Byte Data Path:
2.5 RXUSRCLK2 cycles
1.25 RXUSRCLK cycles
2 Byte Data Path:
1 RXUSRCLK2 cycle
1 RXUSRCLK cycle
4 Byte Data Path:
1.25 RXUSRCLK2 cycles
2.5 RXUSRCLK cycles
Table 2-8: Reset and Power Control Descriptions
Ports Description
RXRESET Synchronous receive system reset recenters the receiver elastic buffer, and resets the
8B/10B decoder, comma detect, channel bonding, clock correction logic, and other
receiver registers. The PLL is unaffected.
TXRESET Synchronous transmit system reset recenters the transmission FIFO, and resets the
8B/10B encoder and other transmission registers. The PLL is unaffected.
POWERDOWN Shuts down the transceiver (both RX and TX sides).
In POWERDOWN mode, transmit output pins TXP/TXN are not driven, but biased by
the state of transmit termination supply VTTX. If VTTX is not powered, TXP/TXN
float to a high-impedance state. Receive input pins RXP/RXN respond similarly to the
state of receive termination supply VTRX.
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Reset/Power Down
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VHDL Template
-- Module: gt_reset
-- Description: VHDL submodule
-- reset for GT
--
-- Device: Virtex-II Pro Family
--------------------------------------------------------------------LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.Numeric_STD.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
-entity gt_reset is
port (
USRCLK2_M : in std_logic;
LOCK : in std_logic;
REFCLK : out std_logic;
DCM_LOCKED: in std_logic;
RST : out std_logic);
end gt_reset;
-architecture RTL of gt_reset is
- signal startup_count : std_logic_vector (7 downto 0);
begin
process (USRCLK2_M, DCM_LOCKED)
begin
if (USRCLK2_M' event and USRCLK2_M = '1') then
if(DCM_LOCKED = '0') then
startup_count <= "00000000";
elsif (DCM_LOCKED = '1') then
startup_count <= startup_count + "00000001";
end if;
end if;
if (USRCLK2_M' event and USRCLK2_M = '1') then
if(DCM_LOCKED = '0') then
RST <= '1';
elsif (startup_count = "00000010") then
RST <= '0';
end if;
Table 2-9: Power Control Descriptions
POWERDOWN Transceiver Status
0 Transceiver in operation
1 Transceiver temporarily powered down
Notes:
1. Unused transceivers are automatically configured as powered-down by the implementation tools.
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end if;
end process;
end RTL;
Verilog Template
// Module: gt_reset
// Description: Verilog Submodule
// reset for4-byte GT
//
// Device: Virtex-II Pro Family
module gt_reset(
USRCLK2_M,
DCM_LOCKED,
RST
);
input USRCLK2_M;
input DCM_LOCKED;
output RST;
wire USRCLK2_M;
wire DCM_LOCKED;
reg RST;
reg [7:0] startup_counter;
always @ ( posedge USRCLK2_M )
if ( !DCM_LOCKED )
startup_counter <= 8'h0;
else if ( startup_counter != 8'h02 )
startup_counter <= startup_counter + 1;
always @ ( posedge USRCLK2_M or negedge DCM_LOCKED )
if ( !DCM_LOCKED )
RST <= 1'b1;
else
RST <= ( startup_counter != 8'h02 );
endmodule
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8B/10B Encoding/Decoding
R
8B/10B Encoding/Decoding
Overview
The RocketIO transceiver has the ability to encode eight bits into a 10-bit serial stream using
standard 8B/10B encoding. This guarantees a DC-balanced, edge-rich serial stream, facilitating DCor AC-coupling and clock recovery. Table 2-10, page 63, shows the significance of 8B/10B ports
that change purpose, depending on whether 8B/10B is bypassed or enabled.
8B/10B Encoder
A bypassable 8B/10B encoder is included in the transmitter. The encoder uses the same 256 data
characters and 12 control characters (shown in Appendix B, “8B/10B Valid Characters”) that are
used for Gigabit Ethernet, XAUI, Fibre Channel, and InfiniBand.
The encoder accepts 8 bits of data along with a K-character signal for a total of 9 bits per character
applied. If the K-character signal is High, the data is encoded into one of the twelve possible
K-characters available in the 8B/10B code. (See Table B-2, page 141.) If the K-character input is
Low, the 8 bits are encoded as standard data. If the K-character input is High and a user applies other
than one of the twelve possible combinations, TXKERR indicates the error.
8B/10B Decoder
An optional 8B/10B decoder is included in the receiver. A programmable option allows the decoder
to be bypassed. When it is bypassed, the 10-bit character order is as shown in Figure 2-14, page 66.
The decoder uses the same table that is used for Gigabit Ethernet, Fibre Channel, and InfiniBand.
The decoder separately detects both “disparity errors” and “out-of-band” errors. A disparity error
occurs when a 10-bit character is received that exists within the 8B/10B table (Table B-1, page 133),
but has an incorrect disparity. An out-of-band error occurs when a 10-bit character is received that
does not exist within the 8B/10B table. It is possible to obtain an out-of-band error without having
a disparity error. The proper disparity is always computed for both legal and illegal characters. The
current running disparity is available at the RXRUNDISP signal.
The 8B/10B decoder performs a unique operation if out-of-band data is detected. Should this occur,
the decoder signals the error, passes the illegal 10 bits through, and places them on the outputs. This
can be used for debugging purposes if desired.
The decoder also signals reception of one of the twelve valid K-characters (Table B-2, page 141) by
way of the RXCHARISK port.
In addition, a programmable comma detect is included. The comma detect signal RXCOMMADET
registers a comma on the receipt of any plus-comma, minus-comma, or both. Since the comma is
defined as a 7-bit character, this includes several out-of-band characters. RXCHARISCOMMA
allows the decoder to detect only the three defined commas (K28.1, K28.5, and K28.7) as pluscomma, minus-comma, or both. In total, there are six possible options, three for valid commas and
three for “any comma.”
Note that all bytes (1, 2, or 4) at the RX FPGA interface each have their own individual 8B/10B
indicators (K-character, disparity error, out-of-band error, current running disparity, and comma
detect).
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Ports and Attributes
TXBYPASS8B10B,
RX_DECODE_USE
One port and one attribute enable 8B/10B encoding/decoding in the transceiver.
TXBYPASS8B10B is a byte-mapped port that is 1, 2, or 4 bits wide, depending on the data width of
the transceiver primitive being used. These bits correlate to each byte of the data path. To enable
8B/10B encoding in the transmitter, these bits must be set Low. In this mode, the transmit data input
to the TXDATA port is non-encoded data of either 8, 16, or 32 bits wide. However, if other encoding
schemes are preferred, the encoder capabilities can be bypassed by setting all bits High. In this
mode, the data input to TXDATA is either 10, 20, or 40 bits wide. The extra bits are fed through the
TXCHARDISPMODE and TXCHARDISPVAL buses (shown in Ta ble 2-10).
The decoder is controlled by the attribute RX_DECODE_USE. When this attribute is set to TRUE,
the decoder is enabled and should coincide with TXBYPASS8B10B being set Low. In this mode, the
received data output from the RXDATA port is decoded data, either 8, 16, or 32 bits wide. However,
when the attribute is set to FALSE, the decoder is disabled. In this mode, the received data is 10, 20,
or 40 bits wide, and the extra bits are provided by RXCHARISK and RXRUNDISP (shown in
Tabl e 2-10).
If this pair is not matched, the data is not received correctly. Figure 2-12 shows the
encoding/decoding blocks of the transceiver and how the data passes through these blocks.
Tabl e 2-10 shows the significance of 8B/10B ports that change purpose depending on whether
8B/10B is bypassed or enabled.
Figure 2-12: 8B/10B Data Flow
UG024_09_031203
TX+
TX−
RX+
RX−
Channel Bonding
and
Clock Correction
TX Clock Generator
RX Clock Recovery
REFCLK
Deserializer
Comma Detect
Serializer
Transmit
Buffer
Transmitter
Receiver
Transceiver Module
32/16/8 bits
32/16/8 bits
50 – 156.3 MHz
8B/10B
Encode
Elastic
Buffer
Receive
Buffer
20X Multiplier
Physical Coding Sublayer Physical Media Attachment
Mindspeed IP
CRC
C
R
C
F
I
F
O
8B/10B
Decode
RXDATA
Loop-back
Loop-back (parallel)
TXDATA
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TXCHARDISPVAL,
TXCHARDISPMODE
TXCHARDISPVAL and TXCHARDISPMODE are dual-purpose ports for the transmitter
depending upon whether 8B/10B encoding is enabled. Tab le 2-10 shows this dual functionality.
When encoding is enabled, these ports function as byte-mapped control ports controlling the
running disparity of the transmitted serial data.
In the encoding configuration, the disparity of the serial transmission can be controlled with the
TXCHARDISPVAL and TXCHARDISPMODE ports. When TXCHARDISPMODE is set High,
the running disparity is set before encoding the specific byte. TXCHARDISPVAL determines if the
disparity is negative (set Low) or positive (set High). Tabl e 2-11 illustrates this.
Table 2-10: 8B/10B Bypassed Signal Significance
Function
TXBYPASS8B10B
0
8B/10B encoding is enabled (not bypassed). 1, 2, or 4 bits, mapped to number of bytes of
data path width.
1
8B/10B encoding bypassed (disabled). 1, 2, or 4 bits, mapped to number of bytes of data
path width.
Function, 8B/10B Enabled Function, 8B/10B Bypassed
TXCHARDISPMODE,
TXCHARDISPVAL
00 Maintain running disparity normally
Part of 10-bit encoded byte
(see Figure 2-13):
TXCHARDISPMODE[0]
(or: [1] / [2] / [3])
TXCHARDISPVAL[0]
(or: [1] / [2] / [3])
TXDATA[7:0]
(or: [15:8] / [23:16] / [31:24])
01
Invert the normally generated running
disparity before encoding this byte.
10
Set negative running disparity before
encoding this byte.
11
Set positive running disparity before
encoding this byte.
RXCHARISK Received byte is a K-character Part of 10-bit encoded byte
(see Figure 2-14):
RXCHARISK[0]
(or: [1] / [2] / [3])
RXRUNDISP[0]
(or: [1] / [2] / [3])
RXDATA[7:0]
(or: [15:8] / [23:16] / [31:24])
RXRUNDISP
0 Indicates running disparity is NEGATIVE
1 Indicates running disparity is POSITIVE
RXDISPERR Disparity error occurred on current byte Unused
TXCHARISK Transmitted byte is a K-character Unused
RXCHARISCOMMA Received byte is a comma Unused
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When TXCHARDISPMODE is set Low, the running disparity is maintained if TXCHARDISPVAL
is also set Low, but the disparity is inverted before encoding the byte when TXCAHRDISPVAL is
set High.
Most applications will use the mode where both TXCHARDISPMODE and TXCHARDISPVAL
are set Low. Some applications may use other settings if special running disparity configurations are
required, such as in the “Vitesse Disparity Example” below.
In the bypassed configuration, TXCHARDISPMODE [0] becomes bit 9 of the 10 bits of encoded
data. TXCHARDISPMODE [1:3] are bits 19, 29, and 39 in the 20- and 40-bit wide buses.
TXCHARDISPVAL becomes bits 8, 18, 28, and 38 of the transmit data. See Figure 2-13.
TXCHARISK
TXCHARISK is a byte-mapped control port that is used only when the 8B/10B encoder is
implemented. This port controls whether the byte of TXDATA is to be encoded as a control (K)
character (when asserted High) or as a data character (when de-asserted). When 8B/10B encoding is
bypassed, this port is undefined.
TXRUNDISP
TXRUNDISP is a status port that is byte-mapped to TXDATA. This port indicates the running
disparity after the byte of TXDATA is encoded. When High, the disparity is positive. When Low, the
disparity is negative.
TXKERR
TXKERR is a status port that is byte-mapped to TXDATA. This port is defined only if 8B/10B
encoding is enabled. If a bit is asserted High, it means that TXDATA and TXCHARISK have
combined to create an invalid control (K) character. The transmission, reception, and decode of this
invalid character will create unexpected RXDATA results in the RocketIO receiver, or in other
transceivers.
RXCHARISK,
RXRUNDISP
RXCHARISK and RXRUNDISP are dual-purpose ports for the receiver depending whether
8B/10B decoding is enabled. Table 2-10 shows this dual functionality. When decoding is enabled,
the ports function as byte-mapped status ports for the received data.
In the 8B/10B decoding configuration, RXCHARISK asserted High indicates the received byte of
data is a control (K) character. Otherwise, the received byte of data is a data character. See Appendix
B, “8B/10B Valid Characters”.
Table 2-11: Running Disparity Control
{TXCHARDISPMODE,
TXCHARDISPVAL}
Function
00 Maintain running disparity normally
01
Invert normally generated running disparity before encoding
this byte
10 Set negative running disparity before encoding this byte
11 Set positive running disparity before encoding this byte
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The RXRUNDISP port indicates the disparity of the received byte is either negative or positive.
RXRUNDISP asserted High indicates positive disparity. This is used in cases like the “Vitesse
Disparity Example” below. When CLK_COR_INSERT_IDLE_FLAG = TRUE, RXRUNDISP is
asserted to flag the presence of an inserted clock correction sequence.
In the bypassed configuration, RXCHARISK and RXRUNDISP are additional data bits for the 10, 20-, or 40-bit buses, similar to the configuration on the transmit side. RXCHARISK [0:3] relates to
bits 9, 19, 29, and 39, while RXRUNDISP pertains to bits 8, 18, 28, and 38 of the data bus. See
Figure 2-14.
RXDISPERR
RXDISPERR is a status port for the receiver that is byte-mapped to RXDATA. When a bit in
RXDISPERR is asserted High, it means that a disparity error has occurred in the received data. This
usually indicates data corruption (bit errors) or transmission of an invalid control character. It can
also occur in cases where normal disparity is not required, such as in the “Vitesse Disparity
Example”.
RXNOTINTABLE
RXNOTINTABLE is a status port for the receiver that is byte-mapped to RXDATA. When it is
asserted High, it means that the received data is not in the 8B/10B tables. This port is only used
when the 8B/10B decoder is enabled.
Vitesse Disparity Example
To support other protocols, the transceiver can affect the disparity mode of the serial data
transmitted. For example, Vitesse channel-to-channel alignment protocol sends out:
K28.5+ K28.5+ K28.5- K28.5- or K28.5- K28.5- K28.5+ K28.5+
instead of:
K28.5+ K28.5- K28.5+ K28.5- or K28.5- K28.5+ K28.5- K28.5+
The logic must assert TXCHARDISPVAL to cause the serial data to send out two negative running
disparity characters.
Note:
If bypassing 8B/10B encoding/decoding, the remaining 10 bits will be the 10-bit-encoded
version of the channel bonding sequence. This is the same as the clock correction sequence
shown in Table 2-15, page 75.
Transmitting Vitesse Channel Bonding Sequence
TXBYPASS8B10B
| TXCHARISK
| | TXCHARDISPMODE
| | | TXCHARDISPVAL
| | | | TXDATA
| | | | |
0 1 0 0 10111100 K28.5+ (or K28.5-)
0 1 0 1 10111100 K28.5+ (or K28.5-)
0 1 0 0 10111100 K28.5- (or K28.5+)
0 1 0 1 10111100 K28.5- (or K28.5+)
The RocketIO core receives this data, but for cases where TXCHARDISPVAL is set High during
data transmission, the disp_err bit in CHAN_BOND_SEQ must also be set High.
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Receiving Vitesse Channel Bonding Sequence
On the RX side, the definition of the channel bonding sequence uses the disp_err bit to specify
the flipped disparity.
10-bit literal value
| disp_err
| | char_is_k
| | | 8-bit_byte_value
| | | |
CHAN_BOND_SEQ_1_1 = 0 0 1 10111100 matches K28.5+ (or K28.5-)
CHAN_BOND_SEQ_1_2 = 0 1 1 10111100 matches K28.5+ (or K28.5-)
CHAN_BOND_SEQ_1_3 = 0 0 1 10111100 matches K28.5- (or K28.5+)
CHAN_BOND_SEQ_1_4 = 0 1 1 10111100 matches K28.5- (or K28.5+)
CHAN_BOND_SEQ_LEN = 4
CHAN_BOND_SEQ_2_USE = FALSE
8B/10B Bypass Serial Output
When 8B/10B encoding is bypassed, the TXCHARDISPVAL and TXCHARDISPMODE bits
become bits “b” and “a”, respectively, of the 10-bit encoded data that the transceiver must transmit
to the receiving terminal. Figure 2-13 illustrates the TX data map during 8B/10B bypass.
During receive when 8B/10B decoding is enabled, the running disparity of the serial transmission
can be read by the transceiver from the RXRUNDISP port, while the RXCHARISK port indicates
presence of a K-character. When 8B/10B decoding is bypassed, these bits remain as Bits “b” and
“a”, respectively, of the 10-bit encoded data that the transceiver passes on to the user logic.
Figure 2-14 illustrates the RX data map during 8B/10B bypass.
Figure 2-13: 10-Bit TX Data Map with 8B/10B Bypassed
Figure 2-14: 10-Bit RX Data Map with 8B/10B Bypassed
UG024_10a_051602
7896543201
First transmitted Last transmitted
TXCHARDISPMODE[0]
TXCHARDISPVAL[0]
TXDATA[7] . . . . . . TXDATA[0]
ghjfiedcab
UG024_10b_051602
7896543201
First received Last received
RXCHARISK[0]
RXRUNDISP[0]
RXDATA[7] . . . . . . RXDATA[0]
ghjfiedcab
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8B/10B Serial Output Format
The 8B/10B encoding translates a 8-bit parallel data byte to be transmitted into a 10-bit serial data
stream. This conversion and data alignment are shown in Figure 2-15. The serial port transmits the
least significant bit of the 10-bit data “a” first and proceeds to “j”. This allows data to be read and
matched to the form shown in Appendix B, “8B/10B Valid Characters.”
The serial data bit sequence is dependent on the width of the parallel data. The most significant byte
is always sent first, regardless of the whether 1-byte, 2-byte, or 4-byte paths are used. The least
significant byte is always last. Figure 2-16 shows a case when the serial data corresponds to each
byte of the parallel data. TXDATA [31:24] is serialized and sent out first, followed by TXDATA
[23:16], TXDATA [15:8], and finally TXDATA [7:0]. The 2-byte path transmits TXDATA [15:8]
and then TXDATA [7:0].
HDL Code Examples: Transceiver Bypassing of 8B/10B Encoding
8B/10B encoding can be bypassed by the transceiver. The TXBYPASS8B10B is set to 1111; the
RXDECODE attribute is set to FALSE to create the extra two bits needed for a 10-bit data bus; and
TXCHARDISPMODE, TXCHARDISPVAL, RXCHARISK, and RXRUNDISP are added to the 8bit data bus.
Please use the Architecture Wizard to create instantiation templates. This wizard creates code and
instantiation templates that define the attributes for a specific application.
Figure 2-15: 8B/10B Parallel to Serial Conversion
Figure 2-16: 4-Byte Serial Structure
UG024_10_021102
01234576
ABCDEFHG
Parallel
7896543201
ghjfiedcab
Serial
8B/10B
First transmitted Last transmitted
U024_11_020802
TXDATA 31:24 TXDATA 23:16 TXDATA 15:8 TXDATA 7:0
H3 − A
3
H2 − A
2
H1 − A
1
H0 − A
0
a3 − j
3
a2 − j
2
a1 − j
1
a0 − j
0
8B/10B
LSB
3
LSB
2
LSB
1
LSB
0
1
st
Sent
Encoded
2nd Sent
Encoded
3rd Sent
Encoded
4th Sent
Encoded
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SERDES Alignment
Overview
Serializer
The multi-gigabit transceiver multiplies the reference frequency provided on the reference clock
input (REFCLK) by 20, or by 10 if half-rate operation is selected. Data is converted from parallel to
serial format and transmitted on the TXP and TXN differential outputs.
The electrical polarity of TXP and TXN can be interchanged through the TXPOLARITY port. This
option can either be programmed or controlled by an input at the FPGA core TX interface. This
facilitates recovery from situations where printed circuit board traces have been reversed.
Deserializer
The RocketIO transceiver core accepts serial differential data on its RXP and RXN inputs. The
clock/data recovery circuit extracts clock phase and frequency from the incoming data stream and
re-times incoming data to this clock. The recovered clock is presented on output RXRECCLK at
1/20 of the received serial data rate.
The receiver is capable of handling either transition-rich 8B/10B streams or scrambled streams, and
can withstand a string of up to 75 non-transitioning bits without an error.
Word alignment is dependent on the state of comma detect bits. If comma detect is enabled, the
transceiver recognizes up to two 10-bit preprogrammed characters. Upon detection of the character
or characters, RXCOMMADET is driven High and the data is synchronously aligned. If a comma is
detected and the data is aligned, no further alignment alteration takes place. If a comma is received
and realignment is necessary, the data is realigned and RXREALIGN is asserted. The realignment
indicator is a distinct output. The transceiver continuously monitors the data for the presence of the
10-bit character(s). Upon each occurrence of the 10-bit character, the data is checked for word
alignment. If comma detect is disabled, the data is not aligned to any particular pattern. The
programmable option allows a user to align data on plus-comma, minus-comma, both, or a unique
user-defined and programmed sequence.
The electrical polarity of RXP and RXN can be interchanged through the RXPOLARITY port. This
can be useful in the event that printed circuit board traces have been reversed.
Ports and Attributes
Comma definition can be accomplished using the attributes discussed below. This method of
definition makes the MGT extremely flexible in implementing different protocols.
ALIGN_COMMA_MSB
This attribute determines where the commas will reside in the parallel received data. The comma
indicates to the deserializer how to parallelize the data. However, with the multiple data path widths
available, the PCS portion must determine where to place the comma in the parallel data bytes.
When ALIGN_COMMA_MSB is FALSE, the PCS may place the comma in any of the RXDATA
bytes. In the 1-byte mode, of course, there is only one location in which the comma can be placed.
In the 2-byte and 4-byte paths, some uncertainty exists as to which byte will contain the comma, as
shown in Ta ble 2-12 .
When ALIGN_COMMA_MSB is TRUE, the PCS places the comma into the most significant byte
(MSB) of RXDATA in the 2-byte mode. Because the PCS is optimized for the 2-byte mode, some
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uncertainty exists in the 4-byte mode as to which byte will contain the comma, as shown in
Tabl e 2-12. See “Receive Data Path 32-bit Alignment” for more details on this case.
ENPCOMMAALIGN,
ENMCOMMAALIGN
These two alignment ports control how the PMA aligns incoming serial data. It can align on a
minus-comma (negative disparity), a plus-comma (positive disparity), both, or neither if comma
alignment is not desired. These signals are latched inside the transceiver with RXRECCLK.
Care must be taken not to de-assert these signals at the improper time. Comma detection may be
vulnerable to spurious realignment if RXRECCLK occurs at the wrong time. To avoid this problem,
ENPCOMMAALIGN and ENMCOMMAALIGN should be passed through a flip-flop that is
clocked with RXRECCLK. These flip-flops should be located near the MGT, and RXRECCLK
should use local interconnect (not global clock resources) to reduce skew. For both top and bottom
edges, the best slices to use are in the CLB immediately to the left of the transceiver, next to the
bottom of the transceiver. For the top side of the chip, this is the fourth CLB row; for the bottom
side, the bottom CLB row. For example, for the XC2VP7, here are the best slices to use for two of
the transceivers:
• For GT_X0Y1 (top edge), the best slices are SLICE_X15Y72 and SLICE_X15Y73.
• For GT_X0Y0 (bottom edge), the best slices are SLICE_X14Y0 and SLICE_X14Y1.
This must be done for each MGT. Figure 2-17 shows this recommendation.
Table 2-12: Possible Locations of Comma Character
ALIGN_COMMA_MSB:
Data Path Width:
1 byte 2 bytes 4 bytes
[7:0] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0]
TRUE √√ √ √
FAL SE √√√√√√√
Figure 2-17: Synchronizing Comma Align Signals to RXRECCLK
GT_std_
*
ENPCOMMAALIGN
ENMCOMMAALIGN
RXRECCLK
DDQ
Q
PCOMMA_CONTROL
MCOMMA_CONTROL
UG024_39_013103
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Figure 2-18 and Figure 2-19 show floorplanner layouts for the two examples given above.
Figure 2-18: Top MGT Comma Control Flip-Flop Ideal Locations
Figure 2-19: Bottom MGT Comma Control Flip-Flop Ideal Locations
ug024_43_031303
ug024_44_031303
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PCOMMA_DETECT,
MCOMMA_DETECT
These two control attributes define when RXCOMMADET signals that a comma has been received.
When only PCOMMA_DETECT is TRUE, RXCOMMADET signals when a plus-comma is
received, but not a minus-comma. When only MCOMMA_DET is TRUE, RXCOMMADET
signals when a minus-comma is received, but not a plus-comma. If both attributes are TRUE,
RXCOMMADET will signal when either comma character is received.
COMMA_10B_MASK,
PCOMMA_10B_VALUE,
MCOMMA_10B_VALUE
The RocketIO transceiver allows the user to define a comma character using these three attributes.
The COMMA_10B_MASK bits are used in conjunction with PCOMMA_10B_VALUE (to define a
plus-comma) or MCOMMA_10B_VALUE (to define a minus-comma) to define some number of
recognized comma characters. High bits in the mask condition the corresponding bits in
PCOMMA_10B_VALUE or MCOMMA_10B_VALUE to matter, while Low bits in the mask
function as a “don’t care” conditioner.
For example, with COMMA_10B_MASK set to 1111111000 (meaning the three least significant
bits don’t matter) and PCOMMA_10B_VALUE is 0011111000, the comma detection unit will
recognize the following characters as plus-commas:
0011111000 (K28.7)
0011111001 (K28.1)
0011111010 (K28.5)
0011111011 through 0011111111 (not valid comma characters)
Using the same value in PCOMMA_10B_VALUE but setting COMMA_10B_MASK to
1111111111 (meaning all the bits in PCOMMA_10B_VALUE matter), the comma detection unit
will recognize only the 0011111000 (K28.7) sequence, which matches the value of
PCOMMA_10B_VALUE exactly.
DEC_PCOMMA_DETECT,
DEC_MCOMMA_DETECT,
DEC_VALID_COMMA_ONLY
These signals only pertain to the 8B/10B decoder, not the comma alignment circuitry. The
DEC_PCOMMA_DETECT and DEC_MCOMMA_DETECT control the 8B/10B decoder to signal
the RXCHARISCOMMA port if a plus-comma or minus-comma is received. This is described in
the table below.
DEC_VALID_COMMA_ONLY, for most applications, should be set to TRUE. If valid data is being
transmitted and hence received, then an invalid comma would arise only in the case of a bit error, in
which case RXCHARISCOMMA would not be asserted in the presence of bit errors. If set to
FALSE, then RXCHARISCOMMA will be asserted for invalid K-characters.
RXREALIGN
This status signal indicates whenever, the serial data is realigned from a comma character in the data
stream. This signal will not necessarily go High after the transceiver is reset. If
ENPCOMMAALIGN and ENMCOMMAALIGN are both set to zero then this signal should not go
High. See Tab le 2-13.
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RXCHARISCOMMA
This signal is similar to RXCHARISK, except that it signals that a specific byte of RXDATA is a
comma character. However, this definition only holds true for when 8B/10B encoding/decoding is
enabled. This port is controlled by the DEC_* attributes and is shown in Tabl e 2-13. If the 8B/10B
decoder is bypassed, this port is undefined.
RXCOMMADET
This signal indicates if a comma character has been detected in the serial data. The definition of this
port is defined by the PCOMMA_DETECT and MCOMMA_DETECT attributes. This signal is
clocked off RXRECCLK, and to reliably have the signal pulse for all the data width configurations,
this pulse may change with respect to the USRCLKs.
Clock Recovery
Overview
Clock Synthesizer
Synchronous serial data reception is facilitated by a clock/data recovery circuit. This circuit uses a
fully monolithic Phase-Locked Loop (PLL), which does not require any external components. The
clock/data recovery circuit extracts both phase and frequency from the incoming data stream. The
recovered clock is presented on output RXRECCLK at 1/20 of the serial received data rate.
The gigabit transceiver multiplies the reference frequency provided on the reference clock input
(REFCLK) by 20.
No fixed phase relationship is assumed between REFCLK, RXRECCLK, and/or any other clock
that is not tied to either of these clocks. When the 4-byte or 1-byte receiver data path is used,
RXUSRCLK and RXUSRCLK2 have different frequencies (1:2), and each edge of the slower clock
is aligned to a falling edge of the faster clock. The same relationships apply to TXUSRCLK and
TXUSRCLK2. See Table 2-5, page 43, for details.
Clock and Data Recovery
The clock/data recovery (CDR) circuits lock to the reference clock automatically if the data is not
present. For proper operation, TXUSRCLK must have the exact same frequency as REFCLK.
Table 2-13: Effects of Comma-Related Ports and Attributes
Port or Attribute
Affects
RXCHARISCOMMA
Affects
RXCOMMADET
Affects Character
Alignment and
RXREALIGN
DEC_VALID_COMMA_ONLY
DEC_PCOMMA_DETECT
DEC_MCOMMA_DETECT
√
PCOMMA_10B_VALUE
MCOMMA_10B_VALUE
√√
PCOMMA_DETECT
MCOMMA_DETECT
√
ENPCOMMAALIGN
ENMCOMMAALIGN
√
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Clock Recovery
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REFCLK, RXUSRCLK, and the incoming stream (RXRECCLK) must not exceed ±100 ppm of
frequency variation.
It is critical to keep power supply noise low in order to minimize common and differential noise
modes into the clock/data recovery circuitry. See “PCB Design Requirements,” page 107, for more
details.
Clock Correction
Clock RXRECCLK (the recovered clock) reflects the data rate of the incoming data. Clock
RXUSRCLK defines the rate at which the FPGA core consumes the data. Ideally, these rates are
identical. However, since the clocks typically have different sources, one of the clocks is faster than
the other. The receiver buffer accommodates this difference between the clock rates. See
Figure 2-20.
Nominally, the buffer is always half-full. This is shown in the top buffer, where the shaded area
represents buffered data not yet read. Received data is inserted via the write pointer under control of
RXRECCLK. The FPGA core reads data via the read pointer under control of RXUSRCLK. The
half-full/half-empty condition of the buffer gives a cushion for the differing clock rates. This
operation continues indefinitely, regardless of whether or not “meaningful” data is being received.
When there is no meaningful data to be received, the incoming data consists of IDLE characters or
other padding.
If RXUSRCLK is faster than RXRECCLK, the buffer becomes more empty over time. The clock
correction logic corrects for this by decrementing the read pointer to reread a repeatable byte
sequence. This is shown in the middle buffer, Figure 2-20, where the solid read pointer decrements
to the value represented by the dashed pointer. By decrementing the read pointer instead of
incrementing it in the usual fashion, the buffer is partially refilled. The transceiver inserts a single
repeatable byte sequence when necessary to refill a buffer. If the byte sequence length is greater than
one, and if attribute CLK_COR_REPEAT_WAIT is 0, then the transceiver can repeat the same
sequence multiple times until the buffer is refilled to the half-full condition.
Similarly, if RXUSRCLK is slower than RXRECCLK, the buffer fills up over time. The clock
correction logic corrects for this by incrementing the read pointer to skip over a removable byte
sequence that need not appear in the final FPGA core byte stream. This is shown in the bottom
buffer, Figure 2-20, where the solid read pointer increments to the value represented by the dashed
pointer. This accelerates the emptying of the buffer, preventing its overflow. The transceiver design
skips a single byte sequence, when necessary, to partially empty a buffer. If attribute
Figure 2-20: Clock Correction in Receiver
Read
RXUSRCLK
Read
Read
Write
RXRECCLK
Write
Write
"Nominal" condition: buffer half-full
Buffer less than half -full (emptying)
Buffer more than half-full (filling up)
Repeatable sequence
Removable sequence
DS083-2_15_100901
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CLK_COR_REPEAT_WAIT is 0, the transceiver can also skip four consecutive removable byte
sequences in one step, to further empty the buffer when necessary.
These operations require the clock correction logic to recognize a byte sequence that can be freely
repeated or omitted in the incoming data stream. This sequence is generally an IDLE sequence, or
other sequence comprised of special values that occur in the gaps separating packets of meaningful
data. These gaps are required to occur sufficiently often to facilitate the timely execution of clock
correction.
The clock correction logic has the ability to remove up to four IDLE sequences during a clock
correction. How many IDLEs are removed depends on several factors, including how many IDLEs
are received and whether CLK_COR_KEEP_IDLE is TRUE or FALSE. For example, if three
IDLEs are received and CLK_COR_KEEP_IDLE is set to TRUE, at least one IDLE sequence must
remain after clock correction has been completed. This limits the clock correction logic to remove
only two of the three IDLE sequences. If CLK_COR_KEEP_IDLE is FALSE, then all three IDLEs
can be removed.
Tabl e 2-14 illustrates the relationship between the number of IDLE sequences removed, the inherent
stability of REFCLK, and the number of bytes allowed between clock correction sequences.
Ports and Attributes
CLK_CORRECT_USE
This attribute controls whether the PCS will repeat/skip the clock correction sequences (CCS) from
the elastic buffer to compensate for differences between the clock recovered from serial data and the
reference clocks. When this attribute is set to TRUE, the clock correction is enabled. If set to
FALSE, clock correction is disabled. When clock correction is disabled, RXRECCLK must drive
the receive logic in the fabric. Otherwise, the elastic buffer may over/underflow.
Clock correction may be used with other encoding protocols, but they must have a 10-bit alignment
scheme. This is required so the comma detection logic can properly align the data in the elastic
buffer, allowing the clock correction logic to properly read out data to the FPGA fabric.
RX_BUFFER_USE
The RX_BUFFER_USE attribute controls if the elastic buffer is bypassed or not. Most applications
use this buffer for clock correction and channel bonding. (See “Channel Bonding (Channel
Alignment),” page 79.) It is recommended that this attribute always be set to TRUE, since this
Table 2-14: Data Bytes Allowed Between Clock Corrections as a Function of
REFCLK Stability and IDLE Sequences Removed
Bytes Allowed Between Clock Correction Sequences
(1)
REFCLK
Stability
Remove 1 IDLE
(2)
Sequence:
Remove 2 IDLE
Sequences:
Remove 3 IDLE
Sequences:
Remove 4 IDLE
Sequences:
100 ppm 5,000 10,000 15,000 20,000
50 ppm 10,000 20,000 30,000 40,000
20 ppm 25,000 50,000 75,000 100,000
Notes:
1. All numbers are approximate.
2. IDLE = the defined clock correction sequence.
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buffer allows a way to cross the clock domains of RXRECCLK and the fabric
RXUSRCLK/RXUSRCLK2.
CLK_COR_SEQ_*_*
To accommodate many different protocols, the MGT features programmability that allows it to
detect a 1-, 2-, or 4-byte clock correction sequence (CCS), such as may be used in Gigabit Ethernet
(2-byte) or Fibre Channel (4-byte). The attributes CLK_COR_SEQ_*_* and
CLK_COR_SEQ_LEN (below) define the CCS that the PCS recognizes. Both SEQ_1 and SEQ_2
can be used at the same time if multiple CCSs are required. As shown in Tabl e 2-15, the example
CCS has two possible modes, one for when 8B/10B encoding is used, the other for when 8B/10B
encoding is bypassed. The most significant bit of the CCS determines whether it is applicable to an
8-bit (encoded) or a 10-bit (unencoded) sequence.
These sequences require that the encoding scheme allows the comma detection and alignment
circuitry to properly align data in the elastic buffer. (See “CLK_CORRECT_USE”, above). The bit
definitions are the same as shown earlier in the Vitesse channel-bonding example. (See “Receiving
Vitesse Channel Bonding Sequence.”)
CLK_COR_SEQ_LEN
To define the CCS length, this attribute takes the integer value 1, 2, 3, or 4. Table 2- 16 shows which
sequences are used for the four possible settings of CLK_COR_SEQ_LEN.
CLK_COR_INSERT_IDLE_FLAG,
CLK_COR_KEEP_IDLE,
CLK_COR_REPEAT_WAIT
These attributes help control how clock correction is implemented.
Table 2-15: Clock Correction Sequence / Data Correlation for 16-Bit Data Port
Attribute Settings
Character CHARISK
TXDATA
(hex)
CLK_COR_SEQ 8-Bit Data Mode
10-Bit Data Mode
(8B/10B Bypass)
CLK_COR_SEQ_1_1 00110111100 10011111010 K28.5 1 ΒΧ
CLK_COR_SEQ_1_2 00010010101 11010100010 D21.4 0 95
CLK_COR_SEQ_1_3 00010110101 11010101010 D21.5 0 Β5
CLK_COR_SEQ_1_4 00010110101 11010101010 D21.5 0 Β5
Table 2-16: Applicable Clock Correction Sequences
CLK_COR_SEQ_LEN
CLK_COR_SEQ_1
That Are Applicable
CLK_COR_SEQ_2
That Are Applicable
(1)
11_12_1
2 1_1, 1_2 2_1, 2_2
3 1_1, 1_2, 1_3 2_1, 2_2, 2_3
4 1_1, 1_2, 1_3. 1_4 2_1, 2_2, 2_3, 2_4
Notes:
1. Applicable only if CLK_COR_SEQ_2_USE is set to TRUE.
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CLK_COR_INSERT_IDLE_FLAG is a TRUE/FALSE attribute that defines the output of the
RXRUNDISP port. When set to TRUE, RXRUNDISP is raised for the first byte of each inserted
(repeated) clock correction sequence (8B/10B decoding enabled). When set to FALSE (default),
RXRUNDISP denotes the running disparity of RXDATA (8B/10B decoding enabled).
CLK_COR_KEEP_IDLE is a TRUE/FALSE attribute that controls whether or not the final byte
stream must retain at least one clock correction sequence. When set to FALSE (default), the clock
correction logic is allowed to remove all clock correction sequences if needed to recenter the elastic
buffer. When set to TRUE, it forces the clock correction logic to retain at least one clock correction
sequence per continuous stream of clock correction sequences.
Example: Elastic buffer is 75% full and clock correction is needed. (IDLE is the defined clock
correction sequence.)
Data stream written into elastic buffer:
Data stream read out of elastic buffer (CLK_COR_KEEP_IDLE = FALSE)
Data stream read out of elastic buffer (CLK_COR_KEEP_IDLE = TRUE)
CLK_COR_REPEAT_WAIT is an integer attribute (0-31) that controls frequency of repetition of
clock correction operations. This attribute specifies the minimum number of RXUSRCLK cycles
without clock correction that must occur between successive clock corrections. For example, if this
attribute is 3, then at least three RXUSRCLK cycles without clock correction must occur before
another clock correction sequence can occur. If this attribute is 0, no limit is placed on how
frequently clock correction can occur.
Example: Elastic buffer is 25% full, clock correction is needed, and one sequence is repeated per
clock correction. (IDLE is the defined clock correction sequence.)
Data stream written into elastic buffer:
Data stream read out of elastic buffer (CLK_COR_REPEAT_WAIT = 0):
Data stream read out of elastic buffer (CLK_COR_REPEAT_WAIT = 1):
The percent that the buffer is full, together with the value of CLK_COR_REPEAT_WAIT,
determines how many times the clock correction sequence is repeated during each clock correction.
Synchronization Logic
Overview
For some applications, it is beneficial to know if incoming data is valid or not, and if the MGT is
synchronized on the data. For applications using the 8B/10B encoding scheme, the
D0
IDLE IDLE IDLE IDLE D1 D2
D0 D1 D2
D0
IDLE D1 D2
D0
IDLE IDLE IDLE D1 D2
D0
IDLE IDLE IDLE IDLE IDLE IDLE D1 D2
D0
IDLE IDLE IDLE IDLE IDLE D1 D2
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RX_LOSS_OF_SYNC FSM does this. It can be programmed to lose sync after a specified number
of invalid data characters are received.
Ports and Attributes
RXCLKCORCNT
Clock correction count (RXCLKCORCNT) is a three-bit signal. It signals if clock correction has
occurred, and whether the elastic buffer realigned the data by skipping or repeating data in the
buffer. It also signals if channel bonding has occurred. Table 2-17 defines the eight binary states of
RXCLKCORCNT.
RX_LOS_INVALID_INCR,
RX_LOS_THRESHOLD
These two signals determine how fast an invalid character advances the RXLOSSOFSYNC FSM
counter before loss of sync is considered to have occurred. RX_LOS_INVALID_INCR determines
how quickly the occurrence of invalid characters is “forgotten” in the presence of subsequent valid
characters. For example, RX_LOS_INVALID_INCR = 4 means that four consecutive valid
characters after an invalid character will reset the counter.
RX_LOS_THRESHOLD determines when the counter has reached the point where the link is
considered to be “out of sync.”
RX_LOSS_OF_SYNC_FSM
The transceiver’s FSM is driven by RXRECCLK and uses status from the data stream prior to the
elastic buffer. This is intended to give early warning of possible problems well before corrupt data
appears on RXDATA. RX_LOSS_OF_SYNC_FSM, a TRUE/FALSE attribute, indicates what the
output of the RXLOSSOFSYNC port (see below) means.
Table 2-17: RXCLKCORCNT Definition
RXCLKCORCNT[2:0] Significance
000
No channel bonding or clock correction occurred for current
RXDATA
001
Elastic buffer skipped one clock correction sequence for current
RXDATA
010
Elastic buffer skipped two clock correction sequence for current
RXDATA
011
Elastic buffer skipped three clock correction sequence for current
RXDATA
100
Elastic buffer skipped four clock correction sequence for current
RXDATA
101 Elastic buffer executed channel bonding for current RXDATA
110
Elastic buffer repeated two clock correction sequences for current
RXDATA
111
Elastic buffer repeated one clock correction sequences for current
RXDATA
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RXLOSSOFSYNC
If RX_LOSS_OF_SYNC_FSM = FALSE, then RXLOSSOFSYNC[1] High indicates that the
transceiver has received an invalid character, and RXLOSSOFSYNC[0] High indicates that a
channel-bonding sequence has been recognized.
If RX_LOSS_OF_SYNC_FSM = TRUE, then the two bits of RXLOSSOFSYNC reflect the state of
the RXLOSSOFSYNC FSM. The state machine diagram in Figure 2-21 and the three subsections
following describe the three states of the RXLOSSOFSYNC FSM.
SYNC_ACQUIRED (RXLOSSOFSYNC = 00)
In this state, a counter is decremented by 1 (but not past 0) for a valid received symbol and
incremented by RX_LOS_INVALID_INCR for an invalid symbol. If the count reaches or exceeds
RX_LOS_THRESHOLD, the FSM moves to state LOSS_OF_SYNC. Otherwise, if a channel
bonding (alignment) sequence has just been written into the elastic buffer, or if a comma
realignment has just occurred, the FSM moves to state RESYNC. Otherwise, the FSM remains in
state SYNC_ACQUIRED.
RESYNC (RXLOSSOFSYNC = 01)
The FSM waits in this state for four RXRECCLK cycles and then goes to state SYNC_ACQUIRED,
unless an invalid symbol is received, in which case the FSM goes to state LOSS_OF_SYNC.
LOSS_OF_SYNC (RXLOSSOFSYNC = 10)
The FSM remains in this state until a comma is received, at which time it goes to state RESYNC.
Figure 2-21: RXLOSSOFSYNC FSM States
00
01 10
SYNC_ACQUIRED
RESYNC LOSS_OF_SYNC
count < RX_LOS_THRESHOLD
count = RX_LOS_THRESHOLD
no comma received
comma received
invalid data
valid data + < 4 RXRECCLK cycles
valid data + 4 RXRECCLK cycles
UG024_40_031803
channel alignment
or
comma realignment
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Channel Bonding (Channel Alignment)
Overview
Some gigabit I/O standards such as XAUI specify the use of multiple transceivers in parallel for
even higher data rates. Words of data are split into bytes, with each byte sent over a separate channel
(transceiver). See Figure 2-22.
The top half of the figure shows the transmission of words split across four transceivers (channels or
lanes). PPPP, QQQQ, RRRR, SSSS, and TTTT represent words sent over the four channels.
The bottom-left portion of the figure shows the initial situation in the FPGA’s receivers at the other
end of the four channels. Due to variations in transmission delay—especially if the channels are
routed through repeaters—the FPGA core might not correctly assemble the bytes into complete
words. The bottom-left illustration shows the incorrect assembly of data words PQPP, QRQQ,
RSRR, etc.
To support correction of this misalignment, the data stream includes special byte sequences that
define corresponding points in the several channels. In the bottom half of Figure 2-22, the shaded
“P” bytes represent these special characters. Each receiver recognizes the “P” channel bonding
character, and remembers its location in the buffer. At some point, one transceiver designated as the
Master instructs all the transceivers to align to the channel bonding character “P” (or to some
location relative to the channel bonding character). After this operation, the words transmitted to the
FPGA core are properly aligned: RRRR, SSSS, TTTT, etc., as shown in the bottom-right portion of
Figure 2-22. To ensure that the channels remain properly aligned following the channel bonding
operation, the Master transceiver must also control the clock correction operations described in the
previous section for all channel-bonded transceivers.
Figure 2-22: Channel Bonding (Alignment)
PQRS T
PQRS T
PQRS T
PQRS T
PQRS T
PQRS T
PQRS T
PQRS T
PQRS T
PQRS T
PQRS T
PQRS T
Before channel bonding After channel bonding
Read
RXUSRCLK
Read
RXUSRCLK
Full word SSSS sent over four channels, one byte per channel
Channel (lane) 0
Channel (lane) 1
Channel (lane) 2
Channel (lane) 3
DS083-2_16_010202
In Transmitters:
In Receivers:
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Channel Bonding (Alignment) Operation
Channel bonding is the technique of tying several serial channels together to create one aggregate
channel. Several channels are fed on the transmit side by one parallel bus and reproduced on the
receive side as the identical parallel bus. The maximum number of serial differential pairs that can
be bonded is 24. For implementation guidelines, see “Implementation Tools,” page 119.
Channel bonding allows those primitives that support it to send data over multiple “channels.”
Among these primitives are GT_CUSTOM, GT_INFINIBAND, GT_XAUI, and GT_AURORA. To
“bond” channels together, there is always one “Master.” The other channels can either be a
SLAVE_1_HOP or SLAVE_2_HOPS. SLAVE_1_HOP is a Slave to a Master that can also be daisy
chained to a SLAVE_2_HOPS. A SLAVE_2_HOPS can only be a Slave to a SLAVE_1_HOP and its
CHBONDO does not connect to another transceiver. To designate a transceiver as a Master or a
Slave, the attribute CHAN_BOND_MODE must be set to one of three designations: Master,
SLAVE_1_HOP, or SLAVE_2_HOPS. To shut off channel bonding, set the transceiver attribute to
“off.” The possible values that can be used are shown in Table 2-18.
Note:
All standards that use both clock correction and channel bonding require a gap greater
than or equal to 4 bytes between clock correction and channel bonding sequences. If a user
creates his/’her own protocol that uses clock correction and channel bonding, the user must
ensure that there is at least a 4 byte gap between the sequences.
The channel bonding sequence is similar in format to the clock correction sequence. This sequence
is set to the appropriate sequence for the primitives supporting channel bonding. The GT_CUSTOM
is the only primitive allowing modification to the sequence. These sequences are comprised of one
or two sequences of length up to 4 bytes each, as set by CHAN_BOND_SEQ_LEN and
CHAN_BOND_SEQ_2_USE. Other control signals include the attributes:
• CHAN_BOND_WAIT
• CHAN_BOND_OFFSET
• CHAN_BOND_LIMIT
• CHAN_BOND_ONE_SHOT
Typical values for these attributes are:
CHAN_BOND_WAIT = 8
CHAN_BOND_OFFSET = CHAN_BOND_WAIT
CHAN_BOND_LIMIT = 2 x CHAN_BOND_WAIT
Lower values are not recommended. Use higher values only if channel bonding sequences are
farther apart than 17 bytes.
Table 2-18: Bonded Channel Connections
Mode CHBONDI CHBONDO
OFF NA NA
MASTER NA Slave 1 CHBONDI
SLAVE_1_HOP Master CHBONDO Slave 2 CHBONDI
SLAVE_2_HOPS Slave 1 CHBONDO NA
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Tabl e 2-19 shows different settings for CHAN_BOND_ONE_SHOT and ENCHANSYNC in
Master and Slave applications.
Ports and Attributes
CHAN_BOND_MODE
An MGT can be designated as one of three types when used in a channel-bonding scheme. The type
is designated by CHAN_BOND_MODE, the three values of which are MASTER, SLAVE_1_HOP,
and SLAVE_2_HOPS. (A fourth mode, OFF, is used when channel bonding is not being performed.)
The Master always controls, for itself and for Slaves of either type, when channel bonding and clock
correction will occur.
Masters are always connected directly to a SLAVE_1_HOP, and indirectly to a SLAVE_2_HOPS
via daisy-chain through a SLAVE_1_HOP. This topology improves the timing characteristics of the
CHBONDO and CHBONDI buses.
ENCHANSYNC
ENCHANSYNC controls when channel bonding is enabled. Table 2-19 shows the recommended
settings for Master and Slaves. To counter the possibility of a bit error causing a false channel
bonding sequence to occur, this port is usually de-asserted once a group of channels have been
successfully aligned.
CHAN_BOND_ONE_SHOT
As with ENCHANSYNC, many applications will require that the channels be aligned only once.
CHAN_BOND_ONE_SHOT = TRUE allows the Master to initiate a channel bonding only once.
This remains true even if more channel bonding sequences are received. (The channels may be
aligned again if RXRESET is asserted and then deasserted, and ENCHANSYNC is deasserted and
then reasserted.)
CHAN_BOND_ONE_SHOT may be set to FALSE when very few channel bonding sequences
appear in the data stream. (For Slave instantiations, this attribute should always be set to FALSE.
See Table 2- 19.) When the channel bonding sequence appears frequently in the data stream,
however, it is recommended that this attribute be set to TRUE in order to prevent the RX buffer from
over- or underflowing.
CHAN_BOND_SEQ_*_*,
CHAN_BOND__SEQ_LEN,
CHAN_BOND_SEQ_2_USE
The channel bonding sequence (CBS) is similar in format to the clock correction sequence. The
CBS is set to the appropriate sequence for the primitives supporting channel bonding.
GT_CUSTOM is the only primitive allowing modification to the sequence. These sequences are
comprised of one or two sequences of length up to 4 bytes each, as set by
CHAN_BOND_SEQ_LEN and CHAN_BOND_SEQ_2_USE.
Table 2-19: Master/Slave Channel Bonding Attribute Settings
Master Slave
CHAN_BOND_ONE_SHOT TRUE or FALSE as desired FALSE
ENCHANSYNC Dynamic control as desired Tie High
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These CBSs should be unique from other delimiters in the data stream, including Clock Correction
Sequence, IDLE, Start of Frame, and End of Frame. As with clock correction, there are multiple
sequences that can be defined (GT_CUSTOM only). The primary CBS is defined by
CHAN_BOND_SEQ_1_*, where * = a number from 1 to 4.
If a second CBS is required, CHAN_BOND_SEQ_2_USE must be set to TRUE, and
CHAN_BOND_SEQ_2_* used to define the second CBS; otherwise, CHAN_BOND_SEQ_2_USE
should be left at its default value, FALSE. See “Receiving Vitesse Channel Bonding Sequence,”
page 66, for the bit breakdown of the sequence definition.
Finally, CHAN_BOND_SEQ_LEN defines the CBS length as 1 to 4 bytes. When set to anything
other than 4, only those sequences are defined. For example, if CHAN_BOND_SEQ_LEN is set to
2, only CHAN_BOND_SEQ_1_1 and CHAN_BOND_SEQ_1_2 need to be defined.
CHAN_BOND_WAIT,
CHAN_BOND_OFFSET,
CHAN_BOND_LIMIT
These three attributes define how the Master performs channel alignment of the RX buffer. The
typical values of these attributes are:
CHAN_BOND_WAIT = 8
CHAN_BOND_WAIT roughly defines the maximum number of bytes by which the Slave can lag
the Master. Due to internal pipelining, the equation should be (CHAN_BOND_WAIT - 3.5) bytes =
# of bytes Slave may lag Master. For example, if CHAN_BOND_WAIT = 8, the Slave may lag the
Master by 4.5 bytes. While this type of lag is equivalent to approximately 14 ns at 3.125 Gb/s, it is
recommended that channel links be matched as closely as possible.
The equation that produces this maximum lag time result is
lag time [ns] = (1 / serial speed [Gb/s] )
• number of lag bytes • 10 bits/byte
or, for schemes that do not use 8B/10B encoding,
(1 / serial speed [Gb/s] )
• number of 10-bit lag characters • 10 bits/character
In the example above, 1/3.125 Gb/s
• 4.5 bytes • 10 bits/byte = 14.4 ns.
The recommended setting of 8 is set for protocols such as Infiniband and XAUI, which can repeat
the CBS every 16 and 17 bytes respectively. However, CHAN_BOND_WAIT can grow accordingly
if CBSs are spaced farther apart.
CHAN_BOND_OFFSET = CHAN_BOND_WAIT
CHAN_BOND_OFFSET measures the number of bytes past the beginning of the channel bonding
sequence. However, this value must always equal CHAN_BOND_WAIT.
CHAN_BOND_LIMIT = 2X CHAN_BOND_WAIT
CHAN_BOND_LIMIT defines the expiration time after which the Slave will invalidate the most
recently seen CBS location in the RX buffer. For proper alignment, this value must always be set to
two times CHAN_BOND_WAIT.
CHBONDDONE
This port indicates when a channel alignment has occurred in the MGT. When it is asserted,
RXDATA is valid after RXCLKCORCNT goes to a 101.
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CRC (Cyclic Redundancy Check)
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Note: The Slave's RXCLKCORCNT will go to 101 regardless of whether the channel bonding
was successful or not. To determine if channel bonding was successful, check both this signal
and RXCLKCORCNT.
CHBONDI,
CHBONDO
These two 4-bit ports are used by the Master MGT to control its clock correction and channel
bonding, as well as those of any Slaves bonded to it. CHBONDO of the Master is connected to
CHBONDI of a SLAVE_1_HOP. The signal is then daisy-chained from SLAVE_1_HOP
CHBONDO to a SLAVE_2_HOPS CHBONDI. See Figure 4-1 and Figure 4-2, page 120, and
Table 2-18, page 80, for examples. The three least significant bits correlate to the value of the
RXCLKCORCNT port. These four bits allow the Master to control when the Slaves perform clock
correction. This keeps channels from going out of sync if, for instance, one Slave repeated a CCS
while another skipped.
RXCLKCORCNT,
RXLOSSOFSYNC
These signals are mainly used for clock correction. However, they can convey some information
relevant to channel bonding as well. Refer to “RXCLKCORCNT” and “RXLOSSOFSYNC,”
page 78.
Troubleshooting
Factors that influence channel bonding include:
• Skew between Master and Slave CBS arrival time, both Master-lags-Slave and Slave-lags-
Master cases. The larger the separation, the larger CHAN_BOND_WAIT needs to be.
• Arrival time between consecutive CBSs. The smaller the separation is between consecutive
CBSs, the smaller CHAN_BOND_WAIT needs to be set to ensure that the Master aligns to the
intended sequence instead of the one after or the one before.
There are several possibilities that could cause unsuccessful channel bonding:
• Slave’s CBS lagging the master by too much. Essentially, the Slave does not see a CBS when
CHBONDO is asserted.
• Master CBS lags the slave by too much. In this case, the slave’s CBS sequence has exceeded
CHAN_BOND_LIMIT and has expired.
• CBS sequences appear more frequently than CHAN_BOND_LIMIT allows, causing the Slave
to align to a CBS before or after the expected one.
CRC (Cyclic Redundancy Check)
Overview
Cyclic Redundancy Check (CRC) is a procedure to detect errors in the received data. The RocketIO
transceiver CRC logic supports the 32-bit invariant CRC calculation used by Infiniband, Fibre
Channel, and Gigabit Ethernet.
CRC Operation
On the transmitter side, the CRC logic recognizes where the CRC bytes should be inserted and
replaces four placeholder bytes at the tail of a data packet with the computed CRC. For Gigabit
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Ethernet and Fibre Channel, transmitter CRC can adjust certain trailing bytes to generate the
required running disparity at the end of the packet. This is discussed further in the “FIBRE_CHAN”
and “ETHERNET” sections under “CRC_FORMAT,” page 85.
On the receiver side, the CRC logic verifies the received CRC value, supporting the same standards
as above.
CRC Generation
RocketIO transceivers support a 32-bit invariant CRC (fixed 32-bit polynomial shown below) for
Gigabit Ethernet, Fibre Channel, Infiniband, and user-defined modes.
The CRC recognizes the SOP (Start of Packet), EOP (End of Packet), and other packet features to
identify the beginning and end of data. These SOP and EOP are defined by CRC_FORMAT for
ETHERNET, INFINIBAND, and FIBRE_CHAN, and in these cases the user does not need to set
CRC_START_OF_PKT and CRC_END_OF_PKT. Where CRC_FORMAT is USER_MODE
(user-defined), CRC_START_OF_PKT and CRC_END_OF_PKT are used to define SOP and EOP.
The transmitter computes 4-byte CRC on the packet data between the SOP and EOP (excluding the
CRC placeholder bytes). The transmitter inserts the computed CRC just before the EOP. The
transmitter modifies trailing Idles or EOP if necessary to generate correct running disparity for
Gigabit Ethernet and Fibre Channel. The receiver recomputes CRC and verifies it against the
inserted CRC. Figure 2-23 shows the packet format for CRC generation. The empty boxes are only
used in certain protocols (Ethernet). The user logic must create a four-byte placeholder for the CRC
by placing it in TXDATA. Otherwise, data is overwritten.
CRC Latency
Enabling CRC increases the transmission latency from TXDATA to TXP and TXN. The enabling of
CRC does not affect the latency from RXP and RXN to RXDATA. The typical and maximum
latencies, expressed in TXUSRCLK/RXUSRCLK cycles, are shown in Table 2-20. For timing
diagrams expressing these relationships, please see Module 3 of the Virtex-II Pro Data Sheet
.
x
32x26x23x22x16x12x11x10x8x7x5x4x2x1
1+ + + + + + + +++++++
Figure 2-23: CRC Packet Format
SOP
…
IdleEOPData CRC
4 Bytes
……
UG024_07_021102
Table 2-20: Effects of CRC on Transceiver Latency
(1)
TXDATA to TXP and TXN
in TXUSRCLK Cycles
RXP and RXN to RXDATA
in RXUSRCLK Cycles
(3)
Typical Maximum Typical Maximum
CRC Disabled 8 11 25 42
(2)
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Ports and Attributes
TX_CRC_USE,
RX_CRC_USE
These two attributes control whether the MGT CRC circuitry is enabled or bypassed. When set to
TRUE, CRC is enabled. When set to FALSE, CRC is bypassed and must be implemented in the
FPGA fabric.
CRC_FORMAT
There are four possible CRC modes: USER_MODE, FIBRE_CHAN, ETHERNET, and
INFINIBAND. This attribute is modifiable only for the GT_XAUI and GT_CUSTOM primitives.
Each mode has a Start of Packet (SOP) and End of Packet (EOP) setting to determine where to start
and end the CRC monitoring. USER_MODE allows the user to define the SOP and EOP by setting
the CRC_START_OF_PKT and CRC_END_OF_PKT to one of the valid K-characters (Tabl e B-2,
page 141). The CRC is controlled by RX_CRC_USE and TX_CRC_USE. Whenever these
attributes are set to TRUE, CRC is used.
The four modes are defined in the subsections following.
USER_MODE
USER_MODE is the simplest CRC methodology. The CRC checks for the SOP and EOP, calculates
CRC on the data, and leaves the four remainders directly before the EOP. The CRC form for the
user-defined mode is shown in Figure 2-24, along with the timing for when RXCHECKINGCRC
and RXCRCERR are asserted High with respect to the incoming data.
To check the CRC error detection logic in a testing mode such as serial loopback, a CRC error can
be forced by setting TXFORCECRCERR to High, which incorporates an error into the transmitted
data. When that data is received, it appears “corrupted,” and the receiver signals an error by
asserting RXCRCERR High at the same time RXCHECKINGCRC goes High. User logic
determines the procedure that is invoked when a CRC error occurs.
Note:
Data length must be greater than 20 bytes for USER_MODE CRC generation. For CRC
to operate correctly, at least four gap bytes are required between EOP of one packet and SOP of
the next packet. The gap may contain clock correction sequences, provided that at least 4 bytes
of gap remain after all clock corrections.
FIBRE_CHAN
The FIBRE_CHAN CRC is similar to USER_MODE CRC (Figure 2-24), with one exception: In
FIBRE_CHAN, SOP and EOP are predefined protocol delimiters. Unlike USER_MODE,
CRC Enabled 14 17 25 42
(2)
Notes:
1. See Table 2- 6 and Tab le 2- 7 for all MGT block latency parameters.
2. This maximum may occur when certain conditions are present, and clock correction and channel bonding are
enabled. If these functions are both disabled, the maximum will be near the typical values.
3. To further reduce receive-side latency, refer to Appendix C, “Related Online Documents.”
Table 2-20: Effects of CRC on Transceiver Latency
(1)
TXDATA to TXP and TXN
in TXUSRCLK Cycles
RXP and RXN to RXDATA
in RXUSRCLK Cycles
(3)
Typical Maximum Typical Maximum
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FIBRE_CHAN does not need to define the attributes CRC_START_OF_PKT and
CRC_END_OF_PKT. Both USER_MODE and FIBRE_CHAN, however, disregard SOP and EOP
in CRC computation.
Designs should generate only the EOP frame delimiter for a beginning running disparity (RD) that
is negative. (These are the frame delimiters that begin with /K28.5/D21.4/ or /K28.5/D10.4/.) Never
generate the EOP frame delimiter for a beginning RD that is positive. (These are the frame
delimiters that begin with /K28.5/D21.5/ or /K28.5/D10.5/.) When the RocketIO CRC determines
that the running disparity must be inverted to satisfy Fibre Channel requirements, it will convert the
second byte of the EOP frame delimiter (D21.4 or D10.4) to the value required to invert the running
disparity (D21.5 or D10.5).
Note that CRC generation for EOP requires that the transmitted K28.5 be left-justified in the MGT’s
internal two-byte data path. Observing the following restrictions assures correct alignment of the
packet delimiters:
• 4-byte data path: K28.5 must appear in TXDATA[31:24] or TXDATA[15:8].
• 2-byte data path: K28.5 must appear in TXDATA[15:8].
• 1-byte data path: K28.5 must be strobed into the MGT on rising TXUSRCLK2 only when
TXUSRCLK is High.
Note:
Minimum data length for this mode is 24 bytes, not including the CRC placeholder.
Note: For correct operation of the Gigabit Ethernet CRC function, the frames that are
transmitted and received must comply with the IEEE 802.3 specifications regarding Gigabit
Ethernet, including the preamble maximum length.
ETHERNET
The Ethernet CRC is more complex (Figure 2-25). The SOP, EOP, and Preamble are neglected by
the CRC. The extension bytes are special “K” characters in special cases. The extension bytes are
untouched by the CRC as are the Trail bits, which are added to maintain packet length.
Designs should generate only the /K28.5/D16.2/ IDLE sequence for transmission, never
/K28.5/D5.6/. When the RocketIO CRC determines that the running disparity must be inverted to
satisfy Gigabit Ethernet requirements, it will convert the first /K28.5/D16.2/ IDLE following a
packet to /K28.5/D5.6/, performing the necessary conversion.
Figure 2-24: USER_MODE / FIBRE_CHAN Mode
UG024_12_022803
SOP DATA R
0
R
1
R
2
R
3
EOP
RXCHECKINGCRC
RXCRCERR
Figure 2-25: Ethernet Mode
UG024_13_101602
Preamble
n Bytes
SOP SOF DATA R0R1R2R
3
Pad Bits EOP Trail Bits
2 to 3 Bytes
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Note: As noted in Figure 2-25, pad bits are used to assure that the header, data, and CRC total
to the 64-byte minimum packet length. For packets that are already 64 bytes or longer, pad bits
are not used.
Note that CRC generation for IDLE requires that the transmitted K28.5 be left-justified in the
MGT’s internal two-byte data path. Observing the following restrictions assures correct alignment
of the packet delimiters:
• 4-byte data path: K28.5 must appear in TXDATA[31:24] or TXDATA[15:8].
• 2-byte data path: K28.5 must appear in TXDATA[15:8].
• 1-byte data path: K28.5 must be strobed into the MGT on rising TXUSRCLK2 only when
TXUSRCLK is High.
Note:
Minimum data length for this mode is defined by the protocol requirements.
Note: For correct operation of the Gigabit Ethernet CRC function, transmitted and received
frames must comply with the 802.3 specification regarding Gigabit Ethernet. This includes the
preamble maximum length.
INFINIBAND
The Infiniband CRC is the most complex mode, and is not supported in the CRC generator.
Infiniband CRC contains two computation types: an invariant 32-bit CRC, the same as in Ethernet
protocol; and a variant 16-bit CRC, which is not supported in the hard core. Infiniband CRC must be
implemented entirely in the FPGA fabric.
There are also two Infiniband Architecture (IBA) packets, a local and a global. Both of these IBA
packets are shown in Figure 2-26.
The CRC is calculated with certain bits masked in LRH and GRH, depending on whether the packet
is local or global. The size of these headers is shown in Table 2-21.
Figure 2-26: Infiniband Mode
Table 2-21: Global and Local Headers
Packet Description Size
LRH Local Routing Header 8 Bytes
GRH Global Routing Header 40 Bytes
BTH IBA Transport Header 12 Bytes
UG024_14_020802
GRHLRHSOP
Global IBA
BTH
Packet
Payload
R
0
R
1
R
2
R
3
Variant CRC EOP
LRHSOP
Local IBA
BTH
Packet
Payload
R
0
R
1
R
2
R
3
Variant CRC EOP
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The CRC checks the LNH (Link Next Header) of the LRH. LRH is shown in Figure 2-27, along
with the bits the CRC uses to evaluate the next packet.
Note:
Minimum data length for this mode is defined by the protocol requirements.
Because of the complexity of the CRC algorithms and implementations, especially with Infiniband,
a more in-depth discussion is beyond the scope of this manual.
CRC_START_OF_PACKET,
CRC_END_OF_PACKET
When implementing USER_MODE CRC, Start of Packet (SOP) and End of Packet (EOP) must be
defined for the CRC logic. These delimiters must be one of the defined K-characters (see Table B-2,
page 141). These must be different than a clock correction sequence (CCS) or IDLE sequence;
otherwise, the CRC will mistake the CCS or IDLE for SOP/EOP.
Note:
These attribute are not applicable to the other CRC formats.
RXCHECKINGCRC,
RXCRCERR
These two signals are status ports for the CRC circuitry.
RXCHECKINGCRC is asserted within several USRCLKs of the EOF being received from
RXDATA. This signals that the CRC circuitry has identified the SOF and the EOF.
If a CRC error occurred, RXCRCERR will be asserted at the same time that RXCHECKINGCRC
goes High.
TXFORCECRCERR,
TX_CRC_FORCE_VALUE
To test the CRC logic in either the MGT or the FPGA fabric, TXFORCECRCERR and
TX_CRC_FORCE_VALUE may be used to invoke a CRC error. When TXFORCECRCERR is
asserted High for at least one USRCLK2 cycle during data transmission (between SOP and EOP),
the CRC circuitry is forced to XOR TXDATA with TX_CRC_FORCE_VALUE, creating a bit error.
This should cause the receiver to register that a CRC error has occurred.
RocketIO CRC Support Limitations
There are limitations to the CRC support provided by the RocketIO transceiver core:
• RocketIO CRC support is implementable for single-channel use only. Computation and byte-
striping of CRC across multiple bonded channels is not supported. For that usage, the CRC
logic can be implemented in the FPGA fabric.
Figure 2-27: Local Route Header
UG024_15_020802
B
0
B17 − B10B
2
B11, B1
0
B
3
B
4
B
5
B
6
B
7
1 1 IBA Global Packet
1 0 IBA Local Packet
0 1 Raw Packet (CRC does not insert remainder)
0 0 Raw Packet (CRC does not insert remainder)
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• The RocketIO transceiver does not compute the 16-bit variant CRC used for Infiniband, and
thus does not fulfill the Infiniband CRC requirement. Infiniband CRC can be computed in the
FPGA fabric.
• All CRC formats have minimum allowable packet sizes. These limits are larger than those set
by the user mode, and are defined by the specific protocol.
Fabric Interface (Buffers)
Overview: Transmitter and Elastic (Receiver) Buffers
Both the transmitter and the receiver include buffers (FIFOs) in the data path. This section gives the
reasons for including the buffers and outlines their operation.
Transmitter Buffer (FIFO)
The transmitter buffer’s write pointer (TXUSRCLK) is frequency-locked to its read pointer
(REFCLK). Therefore, clock correction and channel bonding are not required. The purpose of the
transmitter's buffer is to accommodate a phase difference between TXUSRCLK and REFCLK.
Proper operation of the circuit is only possible if the FPGA clock (TXUSRCLK) is frequencylocked to the reference clock (REFCLK). Phase variations of up to one clock cycle are allowable. A
simple FIFO suffices for this purpose. A FIFO depth of four permits reliable operation with simple
detection of overflow or underflow, which might occur if the clocks are not frequency-locked.
Overflow or underflow conditions are detected and signaled at the interface.
Receiver Buffer
The receiver buffer is required for two reasons:
• To accommodate the slight difference in frequency between the recovered clock RXRECCLK
and the internal FPGA core clock RXUSRCLK (clock correction)
• To allow realignment of the input stream to ensure proper alignment of data being read through
multiple transceivers (channel bonding)
The receiver uses an elastic buffer, where “elastic” refers to the ability to modify the read pointer for
clock correction and channel bonding.
Ports and Attributes
TXBUFERR
When High, this port indicates that a transmit buffer underflow or overflow has occurred. Once set
High, TXRESET must be asserted to clear this bit.
TX_BUFFER_USE
This attribute allows the user to bypass the transmit buffer. A value of FALSE bypasses the buffer,
while a TRUE keeps the buffer in the data path. This attribute should always be set to TRUE.
RXBUFSTATUS
This 2-bit port indicates the status of the receiver elastic buffer. RXBUFSTATUS[1] High indicates
if an overflow/underflow error has occurred. (Once set High, the assertion of RXRESET or
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RXREALIGN clears this bit.) RXBUFSTATUS[0] High indicates that the elastic buffer is at least
half-full.
RX_BUFFER_USE
When set to FALSE, this attribute causes the receive buffer to be bypassed. It should normally be set
to TRUE, since channel bonding and clock correction use the receive buffer for realignment. When
the buffer is bypassed, the user logic must be clocked with RXRECCLK.
Miscellaneous Signals
Ports and Attributes
Several ports and attributes of the MGT have very unique functionality. The following do not have
large roles in the other functionality discussed so far:
RX_DATA_WIDTH,
TX_DATA_WIDTH
These two attributes define the data width in bytes of RXDATA and TXDATA respectively. The
possible values of each attribute are 1, 2, and 4, which correspond to 8-, 16-, and 32-bit data buses
when 8B/10B encoding/decoding is used. (See “8B/10B Encoding/Decoding,” page 61.) The bus
widths are 10, 20, and 40 bits when 8B/10B encoding/decoding is bypassed.
SERDES_10B
This attribute allows the MGT to expand its serial speed range. The normal operational speed range
of 1.0 Gb/s to 3.125 Gb/s (20 times the reference clock rate) is obtained when this attribute is set to
FALSE. When set to TRUE, the MGT serial data will run at 10 times the reference clock rate,
producing a speed range of 622 Mb/s to 1 Gb/s.
TERMINATION_IMP
Receive Termination
On-chip termination is provided at the receiver, eliminating the need for external termination. The
receiver includes programmable on-chip termination circuitry for 50Ω (default) or 75Ω impedance.
Tra ns m i t Ter m i n at io n
On-chip termination is provided at the transmitter, eliminating the need for external termination.
Programmable options exist for 50Ω (default) and 75Ω termination.
Table 2-22: Serial Speed Ranges as a Function of SERDES_10B
SERDES_10B Reference Clock Range Serial Speed Range
TRUE 60 – 100 MHz 600 Mb/s – 1.0 Gb/s
FALSE 50 – 156.25 MHz 1.0 Gb/s – 3.125 Gb/s
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TXPOLARITY,
RXPOLARITY,
TXINHIBIT
A differential pair has a positive-designated and a negative-designated component. If for some
reason the polarity of these components is switched between two transceivers, the data will not be
passed properly. If this occurs, TXPOLARITY will invert the definition of the TXN and TXP pins.
On the receiver side of the MGT, the RXPOLARITY port can invert the definition of RXN and RXP.
For some protocols, the MGT must turn off the TXN/TXP pins. The TXINHIBT port shuts off the
transmit pins and forces them to a constant value (TXN = 0, TXP = 1). Asserting TXINHIBIT also
disables internal serial loopback.
TX_DIFF_CTRL,
PRE_EMPHASIS
These two attributes control analog functionality of the MGT.
The TX_DIFF_CTRL attribute is used to compensate for signal attenuation in the link between
transceivers. It has five possible values of 400, 500, 600, 700, and 800 mV. These values represent
the peak-to-peak amplitude of one component of the differential pair; the full differential peak-to-
peak amplitude is two times these values.
The PRE_EMPHASIS attribute has four values—10%, 20%, 25%, and 33%—which are designated
by 0, 1, 2, and 3 respectively. Pre-emphasis is discussed in greater detail in Chapter 3, “Analog
Design Considerations.”
LOOPBACK
To facilitate testing without the requirement to apply patterns or measure data at gigahertz rates, two
programmable loopback features are available.
One option, serial loopback, places the gigabit transceiver into a state where transmit data is directly
fed back to the receiver. An important point to note is that the feedback path is at the output pads of
the transmitter. This tests the entirety of the transmitter and receiver.
The second loopback path is a parallel path that checks only the digital circuitry. When the parallel
option is enabled, the serial loopback path is disabled. However, the transmitter outputs remain
active and data is transmitted over the serial link. If TXINHIBIT is asserted, TXN is forced High and
TXP is forced Low until TXINHIBIT is de-asserted.
LOOPBACK allows the user to send the data that is being transmitted directly to the receiver of the
transceiver. Table 2-23 shows the three loopback modes.
Table 2-23: LOOPBACK Modes
Input
Value
Mode Description
00 Normal Mode
Normal Mode is selected during normal operation. The
transmitted data is sent out the differential transmit ports (TXN,
TXP) and are sent to another transceiver without being sent to its
own receiver logic. During normal operation, LOOPBACK
should be set to 00.
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Other Important Design Notes
Receive Data Path 32-bit Alignment
The RocketIO transceiver uses the attribute ALIGN_COMMA_MSB to align protocol delimiters
with the use of comma characters (special K-characters K28.5, K28.1, and K28.7 for most
protocols). Setting ALIGN_COMMA_MSB to TRUE/FALSE determines where the comma
characters appear on the RXDATA bus. When ALIGN_COMMA_MSB is set to FALSE, the comma
can appear in any byte lane of RXDATA in the 2- and 4-byte primitives. When
01
Internal Parallel
Mode
Internal Parallel Mode allows testing the transmit and receive
interface logic PCS without having to go into the PMA section of
the transceiver, or to another transceiver. See Figure 2-28.
10
Internal Serial
Mode
Internal Serial Mode is used to check that the entire transceiver is
working properly, including testing of 8B/10B
encoding/decoding. This emulates what another transceiver would
receive as data from this specific transceiver design.
Since the TXP/TXN pins are still being driven during this
loopback mode, PCB traces on these pins should be terminated to
remove reflections; otherwise, loopback bit errors could result.
Termination can be accomplished by any of a variety of methods.
Two examples:
• Connect SMA terminators on the TXP/TXN SMA connectors
(if applicable), or simply use 50Ω resistors on the transmitter
backplane pins.
• Connect the unterminated TXP/TXN to the RXP/RXN of
another instantiated transceiver, allowing its receiver inputs to
terminate the transmitter outputs.
Figure 2-28: Serial and Parallel Loopback Logic
Table 2-23: LOOPBACK Modes
Input
Value
Mode Description
TXDATA
RXDATA
TXP/TXN
RXP/RXN
TX PCS TX SERIALIZER
RX DESERIALIZER
RX PCS MUX
MUX
PARALLEL
LOOPBACK = 01
SERIAL
LOOPBACK = 10
UG024_25_110503
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ALIGN_COMMA_MSB is set to TRUE, the comma appears in RXDATA[15:8] for the 2-byte
primitives, and in either RXDATA[15:8] or RXDATA[31:24] for the 4-byte primitives. (See
“ALIGN_COMMA_MSB,” page 68.)
In the case of a 4-byte primitive, the transceiver sets comma alignment with respect to its 2-byte
internal data path, but it does not constrain the comma to appear only in RXDATA[31:24]. Logic
must be designed in the FPGA fabric to handle comma alignment for the 32-bit primitives when
implementing certain protocols. (Note that FPGA logic is not required for 1-byte and 2-byte
configurations.)
One such protocol is Fibre Channel. Delimiters such as IDLES, SOF, and EOF are four bytes long,
and are assumed by the protocol logic to be aligned on a 32-bit boundary. The Fibre Channel IDLE
delimiter is four bytes long and is composed of characters K28.5, D21.4, D21.5, and D21.5. The
comma, K28.5, is transmitted in TXDATA[31:24], which the protocol logic expects to be received
in RXDATA[31:24].
Using Table B-1, page 133, and Table B-2, page 141, the IDLE delimiter can be translated into a
hexadecimal value 0xBC95B5B5 that represents the 32-bit RXDATA word. On the 32-bit
RXDATA interface, the received word is either 32-bit aligned or misaligned, as shown in
Tabl e 2-24. In the table, “pp” indicates a byte from a previous word of data.
When RXDATA is 32-bit aligned, the logic should pass RXDATA though to the protocol logic
without modification. A properly aligned data flow is shown in Figure 2-29.
Table 2-24: 32-bit RXDATA, Aligned versus Misaligned
RXDATA
[31:24]
RXDATA
[23:16]
RXDATA
[15:8]
RXDATA
[7:0]
32-bit aligned BC 95 B5 B5
CHARISCOMMA 1000
32-bit misaligned pp pp BC 95
CHARISCOMMA 0010
Figure 2-29: RXDATA Aligned Correctly
BC95B5B5
TXDATA
RXDATA
ALIGNED_DATA
BC95B5B5
BC95B5B5
FDB53737
FDB53737
FDB53737
45674893
45674893
45674893
nnnnnnnn nnnnnnnn
nnnnnnnnnnnnnnnn
pppppppp
nnnnnnnn
ug024_33_091602
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When RXDATA is 32-bit misaligned, the word requiring alignment is split between consecutive
RXDATA words in the data stream, as shown in Figure 2-30. (RXDATA_REG in the figure refers to
the design example code in “32-bit Alignment Design,” page 95.)
This conditional shift/delay operation on RXDATA also must be performed on the status outputs
RXNOTINTABLE, RXDISPERR, RXCHARISK, RXCHARISCOMMA, and RXRUNDISP in
order to keep them properly synchronized with RXDATA.
It is not possible to adjust RXCLKCORCNT appropriately for shifted/delayed RXDATA, because
RXCLKCORCNT is summary data, and the summary for the shifted case cannot be recalculated.
32-bit Alignment Design
The following example code illustrates one way to create the logic to properly align 32-bit wide data
with a comma in bits [31:24] For brevity, most status bits are not included in this example design;
however, these should be shifted in the same manner as RXDATA and RXCHARISK.
Note that when using a 40-bit data path (8B/10B bypassed), a similar realignment scheme may be
used, but it cannot rely on RXCHARISCOMMA for comma detection.
Verilog
/*********************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION “AS IS”
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 Xilinx Inc.
* All rights reserved.
*
*********************************************************************/
Figure 2-30: Realignment of RXDATA
BC95B5B5
TXDATA
RXDATA
ALIGNED_DATA
pppp
BC95
BC95B5B5
FDB53737
B5B5FDB5
FDB53737
45674893
37374567
45674893
nnnnnnnn nnnnnnnn
nnnnnnnn
4893
nnnn
RXDATA_REG[15:0]
BC95
pppp
FDB5 4567
nnnn
pppppppp pppppppp
ug024_34_091602
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// Virtex-II Pro RocketIO comma alignment module
//
// This module reads RXDATA[31:0] from a RocketIO transceiver
// and copies it to
// its output, realigning it if necessary so that commas
// are aligned to the MSB position
// [31:24]. The module assumes ALIGN_COMMA_MSB is TRUE,
// so that the comma
// is already aligned to [31:24] or [15:8].
//
// Outputs
//
// aligned_data[31:0] -- Properly aligned 32-bit ALIGNED_DATA
// sync -- Indicator that aligned_data is properly aligned
// aligned_rxisk[3:0] - properly aligned 4 bit RXCHARISK
// Inputs - These are all RocketIO inputs or outputs
// as indicated:
//
// usrclk2 -- RXUSRCLK2
// rxreset -- RXRESET
// rxisk[3:0] RXCHARISK[3:0]
// rxdata[31:0] RXDATA[31:0] -- (commas aligned to
// [31:24] or [15:8])
// rxrealign -- RXREALIGN
// rxcommadet -- RXCOMMADET
// rxchariscomma3 -- RXCHARISCOMMA[3]
// rxchariscomma1 -- RXCHARISCOMMA[1]
//
module align_comma_32 ( aligned_data, aligned_rxisk, sync,
usrclk2, rxreset,
rxdata, rxisk,
rxrealign, rxcommadet,
rxchariscomma3, rxchariscomma1 );
output [31:0] aligned_data;
output [3:0] aligned_rxisk;
output sync;
reg [31:0] aligned_data;
reg sync;
input usrclk2;
input rxreset;
input [31:0] rxdata;
input [3:0] rxisk;
input rxrealign;
input rxcommadet;
input rxchariscomma3;
input rxchariscomma1;
reg [15:0] rxdata_reg;
reg [1:0] rxisk_reg;
reg [3:0] aligned_rxisk;
reg byte_sync;
reg [3:0] wait_to_sync;
reg count;
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// This process maintains wait_to_sync and count,
// which are used only to
// maintain output sync; this provides some idea
// of when the output is properly
// aligned, with the comma in aligned_data[31:24]. The
// counter is set to a high value
// whenever the elastic buffer is reinitialized;
// that is, upon asserted RXRESET or
// RXREALIGN. Count-down is enabled whenever a
// comma is known to have
// come through the comma detection circuit,
// that is, upon an asserted RXREALIGN
// or RXCOMMADET.
always @ ( posedge usrclk2 )
begin
if ( rxreset )
begin
wait_to_sync <= 4'b1111;
count <= 1'b0;
end
else if ( rxrealign )
begin
wait_to_sync <= 4'b1111;
count <= 1'b1;
end
else
begin
if ( count && ( wait_to_sync != 4'b0000 ) )
wait_to_sync <= wait_to_sync - 4'b0001;
if ( rxcommadet )
count <= 1'b1;
end
end
// This process maintains output sync, which indicates
// when outgoing aligned_data
// should be properly aligned, with the comma in aligned_data[31:24].
// Output aligned_data is
// considered to be in sync when a comma is seen on
// rxdata (as indicated
// by rxchariscomma3 or 1) after the counter wait_to_sync
// has reached 0, indicating
// that commas seen by the comma detection circuit
// have had time to propagate to
// aligned_data after initialization of the elastic buffer.
always @ ( posedge usrclk2 )
begin
if ( rxreset | rxrealign )
sync <= 1'b0;
else if ( ( wait_to_sync == 4'b0000 ) &
( rxchariscomma3 | rxchariscomma1 ) )
sync <= 1'b1;
end
// This process generates aligned_data with commas aligned in [31:24],
// assuming that incoming commas are aligned to [31:24] or [15:8].
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// Here, you could add code to use ENPCOMMAALIGN and
// ENMCOMMAALIGN to enable a move back into the byte_sync=0 state.
always @ ( posedge usrclk2 or posedge rxreset )
begin
if ( rxreset )
begin
rxdata_reg <= 16'h0000;
aligned_data <= 32'h0000_0000;
rxisk_reg <= 2'b00;
aligned_rxisk <= 4'b0000;
byte_sync <= 1'b0;
end
else
begin
rxdata_reg[15:0] <= rxdata[15:0];
rxisk_reg[1:0] <= rxisk[1:0];
if ( rxchariscomma3 )
begin
aligned_data[31:0] <= rxdata[31:0];
aligned_rxisk[3:0] <= rxisk[3:0];
byte_sync <= 1'b0;
end
else
if ( rxchariscomma1 | byte_sync )
begin
aligned_data[31:0] <= { rxdata_reg[15:0], rxdata[31:16]
};
aligned_rxisk[3:0] <= { rxisk_reg[1:0], rxisk[3:2] };
byte_sync <= 1'b1;
end
else
begin
aligned_data[31:0] <= rxdata[31:0];
aligned_rxisk <= rxisk;
end
end
end
endmodule // align_comma_32
VHDL
-- *
-- ***********************************************************
-- ***********************************************************
-- *
-- * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION “AS IS”
-- * AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
-- * SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
-- * OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- * APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
-- * THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
-- * AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
-- * FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
-- * WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
-- * IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- * REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
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-- * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- * FOR A PARTICULAR PURPOSE.
-- *
-- * (c) Copyright 2002 Xilinx Inc.
-- * All rights reserved.
-- *
--************************************************************
-- Virtex-II Pro RocketIO comma alignment module
--
-- This module reads RXDATA[31:0] from a RocketIO transceiver
-- and copies it to
-- its output, realigning it if necessary so that commas
-- are aligned to the MSB position
-- [31:24]. The module assumes ALIGN_COMMA_MSB is TRUE,
-- so that the comma
-- is already aligned to [31:24] or [15:8].
--
-- Outputs
--
-- aligned_data[31:0] -- Properly aligned 32-std_logic ALIGNED_DATA
-- sync -- Indicator that aligned_data is properly aligned
-- aligned_rxisk[3:0] -properly aligned 4-std_logic RXCHARISK
-- Inputs - These are all RocketIO inputs or outputs
-- as indicated:
--
-- usrclk2 -- RXUSRCLK2
-- rxreset -- RXRESET
-- rxdata[31:0] RXDATA[31:0] -- (commas aligned to
-- [31:24] or [15:8])
-- rxisk[3:0] - RXCHARISK[3:0]
-- rxrealign -- RXREALIGN
-- rxcommadet -- RXCOMMADET
-- rxchariscomma3 -- RXCHARISCOMMA[3]
-- rxchariscomma1 -- RXCHARISCOMMA[1]
-LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.Numeric_STD.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY align_comma_32 IS
PORT (
aligned_data : OUT std_logic_vector(31 DOWNTO 0);
aligned_rxisk : OUT std_logic_vector(3 DOWNTO 0);
sync : OUT std_logic;
usrclk2 : IN std_logic;
rxreset : IN std_logic;
rxdata : IN std_logic_vector(31 DOWNTO 0);
rxisk : IN std_logic_vector(3 DOWNTO 0);
rxrealign : IN std_logic;
rxcommadet : IN std_logic;
rxchariscomma3 : IN std_logic;
rxchariscomma1 : IN std_logic);
END ENTITY align_comma_32;
ARCHITECTURE translated OF align_comma_32 IS
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SIGNAL rxdata_reg : std_logic_vector(15 DOWNTO 0);
SIGNAL rxisk_reg : std_logic_vector(1 DOWNTO 0);
SIGNAL byte_sync : std_logic;
SIGNAL wait_to_sync : std_logic_vector(3 DOWNTO 0);
SIGNAL count : std_logic;
SIGNAL rxdata_hold : std_logic_vector(31 DOWNTO 0);
SIGNAL rxisk_hold : std_logic_vector(3 DOWNTO 0);
SIGNAL sync_hold : std_logic;
BEGIN
aligned_data <= rxdata_hold;
aligned_rxisk <= rxisk_hold;
sync <= sync_hold;
-- This process maintains wait_to_sync and count,
-- which are used only to
-- maintain output sync; this provides some idea
-- of when the output is properly
-- aligned, with the comma in aligned_data[31:24].
-- The counter is set to a high value
-- whenever the elastic buffer is reinitialized;
-- that is, upon asserted RXRESET or
-- RXREALIGN. Count-down is enabled whenever a
-- comma is known to have
-- come through the comma detection circuit, that
-- is, upon an asserted RXREALIGN
-- or RXCOMMADET.
PROCESS (usrclk2)
BEGIN
IF (usrclk2'EVENT AND usrclk2 = '1') THEN
IF (rxreset = '1') THEN
wait_to_sync <= “1111”;
count <= '0';
ELSE
IF (rxrealign = '1') THEN
wait_to_sync <= “1111”;
count <= '1';
ELSE
IF (count = '1') THEN
IF (wait_to_sync /= “0000”) THEN
wait_to_sync <= wait_to_sync - “0001”;
END IF;
END IF;
IF (rxcommadet = '1') THEN
count <= '1';
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-- This process maintains output sync, which
-- indicates when outgoing aligned_data
-- should be properly aligned, with the comma
-- in aligned_data[31:24]. Output aligned_data is
-- considered to be in sync when a comma is seen
-- on rxdata (as indicated
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-- by rxchariscomma3 or 1) after the counter
-- wait_to_sync has reached 0, indicating
-- that commas seen by the comma detection circuit
-- have had time to propagate to
-- aligned_data after initialization of the elastic buffer.
PROCESS (usrclk2)
BEGIN
IF (usrclk2'EVENT AND usrclk2 = '1') THEN
IF ((rxreset OR rxrealign) = '1') THEN
sync_hold <= '0';
ELSE
IF (wait_to_sync = “0000”)THEN
IF ((rxchariscomma3 OR rxchariscomma1) = '1') THEN
sync_hold <= '1';
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-- This process generates aligned_data with commas
-- aligned in [31:24],
-- assuming that incoming commas are aligned
-- to [31:24] or [15:8].
-- Here, you could add code to use ENPCOMMAALIGN and
-- ENMCOMMAALIGN to enable a move back into the
-- byte_sync=0 state.
PROCESS (usrclk2, rxreset)
BEGIN
IF (rxreset = '1') THEN
rxdata_reg <= “0000000000000000”;
rxdata_hold <= “00000000000000000000000000000000”;
rxisk_reg <= “00”;
rxisk_hold <= “0000”;
byte_sync <= '0';
ELSIF (usrclk2'EVENT AND usrclk2 = '1') THEN
rxdata_reg(15 DOWNTO 0) <= rxdata(15 DOWNTO 0);
rxisk_reg(1 DOWNTO 0) <= rxisk(1 DOWNTO 0);
IF (rxchariscomma3 = '1') THEN
rxdata_hold(31 DOWNTO 0) <= rxdata(31 DOWNTO 0);
rxisk_hold(3 DOWNTO 0) <= rxisk(3 DOWNTO 0);
byte_sync <= '0';
ELSE
IF ((rxchariscomma1 OR byte_sync) = '1') THEN
rxdata_hold(31 DOWNTO 0) <= rxdata_reg(15 DOWNTO 0) &
rxdata(31 DOWNTO 16);
rxisk_hold(3 DOWNTO 0) <= rxisk_reg(1 DOWNTO 0) &
rxisk(3 DOWNTO 2);
byte_sync <= '1';
ELSE
rxdata_hold(31 DOWNTO 0) <= rxdata(31 DOWNTO 0);
rxisk_hold(3 DOWNTO 0) <= rxisk(3 DOWNTO 0);
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE translated;
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