Xilinx RocketIO XC2VP2, RocketIO XC2VP20, RocketIO XC2VP4, RocketIO XC2VP7, RocketIO XC2VP30 User Manual
...
R
RocketIO™
Transceiver
User Guide
UG024 (v2.3.2) June 24, 2004
RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v2.3.2) June 24, 2004
1-800-255-7778
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UG024 (v2.3.2) June 24, 2004 www.xilinx.com RocketIO™ Transceiver User Guide
1-800-255-7778
RocketIO™ Transceiver User Guide
UG024 (v2.3.2) June 24, 2004
The following table shows the revision history for this document.
Date Version Revision
11/20/01 1.0 • Initial Xilinx release.
01/23/02 1.1 • Updated for typographical and other errors found during review.
02/25/02 1.2 • Part of Virtex-II Pro™ Developer’s Kit (March 2002 Release)
07/11/02 1.3 • Updated “PCB Design Requirements”. Added Appendix A, “RocketIO Transceiver Timing
Model.” Changed Cell Models to Appendix B.
09/27/02 1.4 • Added additional IMPORTANT NOTE regarding ISE revisions at the beginning of Chapter 1
• Added material in section “CRC (Cyclic Redundancy Check).”
• Added section “Other Important Design Notes.”
• New pre-emphasis eye diagrams in section “Pre-emphasis Techniques.”
• Numerous parameter additions previously shown as “TBD” in “MGT Package Pins.”
10/16/02 1.5 • Corrected pinouts for FF1152 package, device column 2VP20/30, LOC Constraints rows
GT_X0_Y0 and GT_X0_Y1.
• Corrected section “CRC Latency” and Table 2-20 to express latency in terms of TXUSRCLK
and RXUSRCLK cycles.
• Corrected sequence of packet elements in Figure 2-30.
11/20/02 1.6 • Tabl e 1-2: Added support for XAUI Fibre Channel.
• Corrected max PCB drive distance to 40 inches.
• Reorganized content sequence in Chapter 2, “Digital Design Considerations.”
• Table 1 -5: Additional information in RXCOMMADET definition.
• Code corrections in VHDL Clock templates.
• “Data Path Latency” section expanded and reformatted.
• Corrections in clocking scheme drawings. Addition of drawings showing clocking schemes
without using DCM.
• Table B -1: Corrections in Valid Data Characters.
• Table 3 -4: Data added.
• Corrections made to power regulator schematic, Figure 3-7.
• Table 2 -23: Data added/corrected.
12/12/02 1.6.1 • Added clarifying text regarding trace length vs. width.
03/25/03 2.0 • Reorganized existing content
• Added new content
• Added Appendix C, “Related Online Documents”
• Added “Index”
RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v2.3.2) June 24, 2004
1-800-255-7778
06/12/03 2.1 • Table 1-2: Added qualifying footnote to XAUI 10GFC.
• Table 1 -5: Corrected definition of RXRECCLK.
• Section “RocketIO Transceiver Instantiations” in Chapter 1: added text briefly explaining what
the Instantiation Wizard does.
• Table 2 -14: Changed numerics from exact values to rounded-off approximations (nearest
5,000), and added footnote calling attention to this.
• Section “Clocking” in Chapter 2: added text recommending use of an IBUFGDS for reference
clock input to FPGA fabric.
• Section “RXRECCLK” in Chapter 2: Deleted references to SERDES_10B attribute and to
divide-by-10. (RXRECCLK is always 1/20th the data rate.).
• Section “CRC_FORMAT” in Chapter 2: Corrected minimum data length for USER_MODE to
“greater than 20”.
• Table 3 -5: Clarified the significance of the V
TTX/VTRX
voltages shown in this table.
• Section “AC and DC Coupling” in Chapter 3: Explanatory material added regarding
V
TRX/VTTX
settings when AC or DC coupling is used.
• Table 4 -1: Corrected pinouts for FG256 and FG456.
• Table 4 -3: Corrected pinouts for FF1517 (XC2VP70).
11/07/03 2.2 • Section “Clock Signals” in Chapter 2: Added material that states:
♦ the reference clock must be provided at all times.
♦ any added jitter on the reference clock will be reflected on the RX/TX I/O.
• Figure 2-3: Added a BUFG after the IBUFGDS reference clock buffer.
• Section “RX_BUFFER_USE” in Chapter 2: Corrected erroneous “USRCLK2” to
“RXUSRCLK/RXUSRCLK2”.
• Table 2 -20: Added footnotes qualifying the maximum receive-side latency parameters given
in the table.
• Section “FIBRE_CHAN” in Chapter 2: Added specification for minimum data length (24
bytes not including CRC placeholder).
• Section “ETHERNET” in Chapter 2: Added note indicating that Gigabit Ethernet 802.3 frame
specifications must be adhered to.
• Table 2 -23: Corrected “External” to “Internal” loopback. Improved explanation of Parallel
Mode loopback.
• Added Figure 2-28, “Serial and Parallel Loopback Logic.”
• Section “Clock and Data Recovery” in Chapter 3: Corrected text to make clear that
RXRECCLK is always 1/20th the incoming data rate, and that CDR requires a minimum
number of transitions to achieve and maintain a lock on the received data.
• Section “Voltage Regulation” in Chapter 3: Added material defining voltage regulator
requirements when a device other than the LT1963 is used.
• Section “AC and DC Coupling” in Chapter 3: Added footnote to Table 3-7 clarifying
V
TRX/VTTX
voltage compliance.
• Figure 3-17 and section “Epson EG-2121CA 2.5V (LVPECL Outputs)” in Chapter 3: Added
material specifying the optional use of an LVPECL buffer as an alternative to the LVDS buffer
previously specified.
• Table 4 -2: Added pinouts for FG676 package, XC2VP20 and XC2VP30.
• Table A -5: Added BREFCLK parameters T
BREFPWH
and T
BREFPWL
.
• Section “Application Notes” in Appendix C: Included new Xilinx Application Notes
XAPP648, XAPP669, and XAPP670.
• Various non-technical edits and corrections.
Date Version Revision
UG024 (v2.3.2) June 24, 2004 www.xilinx.com RocketIO™ Transceiver User Guide
1-800-255-7778
02/24/04 2.3 • Table 2-3, page 41: Added FG676 row to BREFCLK Pin Numbers.
• Figure 2-4, page 47: Added note above Figure 2-4 stating, “These local MGT clock input
inverters, shown and noted in Figure 2-4, are not included in the FOUR_BYTE_CLK
templates.
• Section“RXRECCLK” in Chapter 2: Added paragraph to section explaining how RXRECCLK
changes monotonically and how the recovered bit clock is derived.
• Section “Data Path Latency” in Chapter 2: Revised first sentence to read: “With the many
configurations of the MGT, both the transmit and receive data path latencies vary.”
• Section “RXBUFSTATUS” in Chapter 2: Revised the description of RXBUFSTATUS.
• Figure 3-1, page 101: Replaced old Figure 3-1, page 101, with new Figure 3-1 showing
“Differential Amplifier.”
• Figure 3-6, page 105: Added new Figure 3-6, page 105, showing “MGT Receiver.”
• Table 3-4, page 106: Added text to CDR Parameters (TLOCK parameter in Conditions
column) and edited Note 3.
• Section “Voltage Regulation” in Chapter 3: Added Linear Technology part numbers
(LT1963A, LT1964).
• Section “Passive Filtering” in Chapter 3: Added new cap rules for RocketIO transceiver.
• Figure 3-8, page 109: Replaced old Figure 3-8 with new figure showing “Power Filtering
Network on Devices with Internal and External Capacitors.”
• Table 3-6, page 110: Added Device and Package combinations table.
• Figure 3-9, page 110: Added new Figure 3-10, page 110, showing “Example Power Filtering
PCB Layout for Four MGTs, in Device with Internal Capacitors, Bottom Layer.” Modified the
text describing Figure 3-9, page 110.
• Figure 3-10, page 111: Replaced old Figure 3-10 with new figure showing “Example Power
Filtering PCB Layout for Four MGTs, in Device with External Capacitors, Top Layer.”
Removed the text describing old Figure 3-10.
• Figure 3-11, page 112: Replaced old Figure 3-11 with new figure showing “Example Power
Filtering PCB Layout for Four MGTs, in Device with External Capacitors, Bottom Layer.”
Removed the text describing old Figure 3-11.
• Table 3-7, page 115: Added V
TRX
and V
TTX
voltages for different coupling environments.
05/20/04 2.3.1 • Changed the value of TRCLK/RFCLK in Table 3-4.
06/24/04 2.3.2 • Modified Figure 2-3.
Date Version Revision
RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v2.3.2) June 24, 2004
1-800-255-7778
RocketIO™ Transceiver User Guide www.xilinx.com 7
UG024 (v2.3.2) June 24, 2004 1-800-255-7778
Schedule of Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Schedule of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Preface: About This Guide
RocketIO Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
For More Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Port and Attribute Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Typographical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Chapter 1: RocketIO Transceiver Overview
Basic Architecture and Capabilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
RocketIO Transceiver Instantiations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
HDL Code Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
List of Available Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Primitive Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Modifiable Primitives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Byte Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Chapter 2: Digital Design Considerations
Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
BREFCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Clock Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Digital Clock Manager (DCM) Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Example 1a: Two-Byte Clock with DCM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Example 1b: Two-Byte Clock without DCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Example 2: Four-Byte Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Example 3: One-Byte Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Half-Rate Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Multiplexed Clocking Scheme with DCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Multiplexed Clocking Scheme without DCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
RXRECCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Clock Dependency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Data Path Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Reset/Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
8B/10B Encoding/Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
8B/10B Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table of Contents
8 www.xilinx.com RocketIO™ Transceiver User Guide
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8B/10B Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
TXBYPASS8B10B,
RX_DECODE_USE
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
TXCHARDISPVAL,
TXCHARDISPMODE
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
TXCHARISK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
TXRUNDISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
TXKERR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
RXCHARISK,
RXRUNDISP
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
RXDISPERR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
RXNOTINTABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Vitesse Disparity Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Transmitting Vitesse Channel Bonding Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Receiving Vitesse Channel Bonding Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
8B/10B Bypass Serial Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
8B/10B Serial Output Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
HDL Code Examples: Transceiver Bypassing of 8B/10B Encoding . . . . . . . . . . . . . . . . . . . 67
SERDES Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Serializer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Deserializer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
ALIGN_COMMA_MSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
ENPCOMMAALIGN,
ENMCOMMAALIGN
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
PCOMMA_DETECT,
MCOMMA_DETECT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
COMMA_10B_MASK,
PCOMMA_10B_VALUE,
MCOMMA_10B_VALUE
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
DEC_PCOMMA_DETECT,
DEC_MCOMMA_DETECT,
DEC_VALID_COMMA_ONLY
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
RXREALIGN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
RXCHARISCOMMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
RXCOMMADET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Clock Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Clock and Data Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Clock Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
CLK_CORRECT_USE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
RX_BUFFER_USE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
CLK_COR_SEQ_*_* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
CLK_COR_SEQ_LEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
CLK_COR_INSERT_IDLE_FLAG,
CLK_COR_KEEP_IDLE,
CLK_COR_REPEAT_WAIT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Synchronization Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
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Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
RXCLKCORCNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
RX_LOS_INVALID_INCR,
RX_LOS_THRESHOLD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
RX_LOSS_OF_SYNC_FSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
RXLOSSOFSYNC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Channel Bonding (Channel Alignment) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Channel Bonding (Alignment) Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
CHAN_BOND_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
ENCHANSYNC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
CHAN_BOND_ONE_SHOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
CHAN_BOND_SEQ_*_*,
CHAN_BOND__SEQ_LEN,
CHAN_BOND_SEQ_2_USE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
CHAN_BOND_WAIT,
CHAN_BOND_OFFSET,
CHAN_BOND_LIMIT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
CHBONDDONE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
CHBONDI,
CHBONDO
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
RXCLKCORCNT,
RXLOSSOFSYNC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
CRC (Cyclic Redundancy Check). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
CRC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
CRC Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
CRC Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
TX_CRC_USE,
RX_CRC_USE
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
CRC_FORMAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
CRC_START_OF_PACKET,
CRC_END_OF_PACKET
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
RXCHECKINGCRC,
RXCRCERR
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
TXFORCECRCERR,
TX_CRC_FORCE_VALUE
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
RocketIO CRC Support Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Fabric Interface (Buffers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Overview: Transmitter and Elastic (Receiver) Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Transmitter Buffer (FIFO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Receiver Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
TXBUFERR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
TX_BUFFER_USE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
RXBUFSTATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
RX_BUFFER_USE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Miscellaneous Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
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RX_DATA_WIDTH,
TX_DATA_WIDTH
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
SERDES_10B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
TERMINATION_IMP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
TXPOLARITY,
RXPOLARITY,
TXINHIBIT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
TX_DIFF_CTRL,
PRE_EMPHASIS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
LOOPBACK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Other Important Design Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Receive Data Path 32-bit Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
32-bit Alignment Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Chapter 3: Analog Design Considerations
Serial I/O Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Pre-emphasis Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Differential Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Clock and Data Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
PCB Design Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Power Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Voltage Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Passive Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
High-Speed Serial Trace Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Routing Serial Traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Differential Trace Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
AC and DC Coupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Epson EG-2121CA 2.5V (LVPECL Outputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Pletronics LV1145B (LVDS Outputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Other Important Design Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Powering the RocketIO Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
The POWERDOWN Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Chapter 4: Simulation and Implementation
Simulation Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
SmartModels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
HSPICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Implementation Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Par . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
MGT Package Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Appendix A: RocketIO Transceiver Timing Model
Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Setup/Hold Times of Inputs Relative to Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Clock to Output Delays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
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Clock Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Timing Parameter Tables and Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Appendix B: 8B/10B Valid Characters
Valid Data Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Valid Control Characters (K-Characters) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Appendix C: Related Online Documents
Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
XAPP648: Serial Backplane Interface to a Shared Memory . . . . . . . . . . . . . . . . . . . . . . . . 143
XAPP649: SONET Rate Conversion in Virtex-II Pro Devices . . . . . . . . . . . . . . . . . . . . . . 143
XAPP651: SONET and OTN Scramblers/Descramblers . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
XAPP652: Word Alignment and SONET/SDH Deframing . . . . . . . . . . . . . . . . . . . . . . . . . 144
XAPP660: Partial Reconfiguration of RocketIO Pre-emphasis
and Differential Swing Control Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
XAPP661: RocketIO Transceiver Bit-Error Rate Tester . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
XAPP662: In-Circuit Partial Reconfiguration of RocketIO Attributes . . . . . . . . . . . . . . . . 144
XAPP669: PPC405 PPE Reference System Using Virtex-II Pro
RocketIO Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
XAPP670: Minimizing Receiver Elastic Buffer Delay in the Virtex-II Pro
RocketIO Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
XAPP680: HD-SDI Transmitter Using Virtex-II Pro RocketIO Multi-Gigabit Transceivers145
XAPP681: HD-SDI Receiver Using Virtex-II Pro RocketIO Multi-Gigabit Transceivers . 145
XAPP687: 64B/66B Encoder/Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Characterization Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Virtex-II Pro RocketIO Multi-Gigabit Transceiver
Characterization Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Virtex-II Pro RocketIO MGT HSSDC2 Cable Characterization . . . . . . . . . . . . . . . . . . . . . 146
White Papers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
WP157: Usage Models for Multi-Gigabit Serial Transceivers . . . . . . . . . . . . . . . . . . . . . . . 147
WP160: Emulating External SERDES Devices with
Embedded RocketIO Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
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Chapter 1: RocketIO Transceiver Overview
Figure 1-1: RocketIO Transceiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Chapter 2: Digital Design Considerations
Figure 2-1: REFCLK/BREFCLK Selection Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 2-2: Two-Byte Clock with DCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 2-3: Two-Byte Clock without DCM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 2-4: Four-Byte Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 2-5: One-Byte Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 2-6: One-Byte Data Path Clocks, SERDES_10B = TRUE. . . . . . . . . . . . . . . . . . . . . . . 55
Figure 2-7: Two-Byte Data Path Clocks, SERDES_10B = TRUE . . . . . . . . . . . . . . . . . . . . . . 55
Figure 2-8: Four-Byte Data Path Clocks, SERDES_10B = TRUE . . . . . . . . . . . . . . . . . . . . . . 55
Figure 2-9: Multiplexed REFCLK with DCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 2-10: Multiplexed REFCLK without DCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 2-11: Using RXRECCLK to Generate RXUSRCLK and RXUSRCLK2 . . . . . . . . . . 57
Figure 2-12: 8B/10B Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 2-13: 10-Bit TX Data Map with 8B/10B Bypassed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 2-14: 10-Bit RX Data Map with 8B/10B Bypassed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 2-15: 8B/10B Parallel to Serial Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 2-16: 4-Byte Serial Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 2-17: Synchronizing Comma Align Signals to RXRECCLK . . . . . . . . . . . . . . . . . . . . 69
Figure 2-18: Top MGT Comma Control Flip-Flop Ideal Locations . . . . . . . . . . . . . . . . . . . . 70
Figure 2-19: Bottom MGT Comma Control Flip-Flop Ideal Locations. . . . . . . . . . . . . . . . . . 70
Figure 2-20: Clock Correction in Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 2-21: RXLOSSOFSYNC FSM States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 2-22: Channel Bonding (Alignment) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 2-23: CRC Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 2-24: USER_MODE / FIBRE_CHAN Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 2-25: Ethernet Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 2-26:
Infiniband Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 2-27: Local Route Header. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 2-28: Serial and Parallel Loopback Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 2-29: RXDATA Aligned Correctly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 2-30: Realignment of RXDATA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Chapter 3: Analog Design Considerations
Figure 3-1: Differential Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 3-2: Alternating K28.5+ with No Pre-Emphasis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Schedule of Figures
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Figure 3-3: K28.5+ with Pre-Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 3-4: Eye Diagram, 10% Pre-Emphasis, 20" FR4, Worst-Case Conditions . . . . . . . . 104
Figure 3-5: Eye Diagram, 33% Pre-Emphasis, 20" FR4, Worst-Case Conditions . . . . . . . . 104
Figure 3-6: MGT Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 3-7: Power Supply Circuit Using LT1963 (LT1963A) Regulator . . . . . . . . . . . . . . . . 108
Figure 3-8: Power Filtering Network on Devices with Internal and External Capacitors . . 109
Figure 3-9: Example Power Filtering PCB Layout for Four MGTs, in Device with Internal Capacitors,
Bottom Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 3-10: Example Power Filtering PCB Layout for Four MGTs, In Device with External
Capacitors, Top Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 3-11: Example Power Filtering PCB Layout for Four MGTs, in Device with External Capacitors,
Bottom Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 3-12: Single-Ended Trace Geometry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 3-13: Microstrip Edge-Coupled Differential Pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 3-14: Stripline Edge-Coupled Differential Pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 3-15: AC-Coupled Serial Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 3-16: DC-Coupled Serial Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 3-17: LVPECL Reference Clock Oscillator Interface . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 3-18: LVPECL Reference Clock Oscillator Interface (On-Chip Termination) . . . . 116
Figure 3-19: LVDS Reference Clock Oscillator Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 3-20: LVDS Reference Clock Oscillator Interface (On-Chip Termination) . . . . . . . 116
Chapter 4: Simulation and Implementation
Figure 4-1: 2VP2 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 4-2: 2VP50 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Appendix A: RocketIO Transceiver Timing Model
Figure A-1: RocketIO Transceiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure A-2: RocketIO Transceiver Timing Relative to Clock Edge. . . . . . . . . . . . . . . . . . . . 131
Appendix B: 8B/10B Valid Characters
Appendix C: Related Online Documents
RocketIO™ Transceiver User Guide www.xilinx.com 15
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Chapter 1: RocketIO Transceiver Overview
Table 1-1: Number of RocketIO Cores per Device Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 1-2: Communications Standards Supported by RocketIO Transceiver . . . . . . . . . . . . 21
Table 1-3: Serial Baud Rates and the SERDES_10B Attribute . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 1-4: Supported RocketIO Transceiver Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 1-5: GT_CUSTOM
(1)
, GT_AURORA, GT_FIBRE_CHAN
(2)
, GT_ETHERNET
(2)
,
GT_INFINIBAND, and GT_XAUI Primitive Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 1-6: RocketIO Transceiver Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 1-7: Default Attribute Values: GT_AURORA, GT_CUSTOM, GT_ETHERNET . . . 33
Table 1-8: Default Attribute Values: GT_FIBRE_CHAN, GT_INFINIBAND,
and GT_XAUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 1-9: Control/Status Bus Association to Data Bus Byte Paths . . . . . . . . . . . . . . . . . . . . . 37
Chapter 2: Digital Design Considerations
Table 2-1: Clock Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 2-2: Reference Clock Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 2-3: BREFCLK Pin Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 2-4: Data Width Clock Ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 2-5: DCM Outputs for Different DATA_WIDTHs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 2-6: Latency through Various Transmitter Components/Processes . . . . . . . . . . . . . . . 57
Table 2-7: Latency through Various Receiver Components/Processes . . . . . . . . . . . . . . . . . . 58
Table 2-8: Reset and Power Control Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 2-9: Power Control Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 2-10: 8B/10B Bypassed Signal Significance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 2-11: Running Disparity Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 2-12: Possible Locations of Comma Character . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 2-13: Effects of Comma-Related Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 2-14: Data Bytes Allowed Between Clock Corrections as a Function of
REFCLK Stability and IDLE Sequences Removed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 2-15: Clock Correction Sequence / Data Correlation for 16-Bit Data Port. . . . . . . . . . 75
Table 2-16: Applicable Clock Correction Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 2-17: RXCLKCORCNT Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 2-18: Bonded Channel Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 2-19: Master/Slave Channel Bonding Attribute Settings . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 2-20: Effects of CRC on Transceiver Latency
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 2-21: Global and Local Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 2-22: Serial Speed Ranges as a Function of SERDES_10B. . . . . . . . . . . . . . . . . . . . . . . 90
Table 2-23: LOOPBACK Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 2-24: 32-bit RXDATA, Aligned versus Misaligned . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Schedule of Tables
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Chapter 3: Analog Design Considerations
Table 3-1: Differential Transmitter Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 3-2: Pre-emphasis Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 3-3: Differential Receiver Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 3-4: CDR Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 3-5: Transceiver Power Supplies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 3-6: Device and Package Combinations showing Devices with RocketIO Power Filtering Capaci-
tors Internal to the Package and Externally Mounted on the PCB . . . . . . . . . . . . . . . . . . 110
Table 3-7: V
TRX
and V
TTX
for AC- and DC-Coupled Environments . . . . . . . . . . . . . . . . . . 115
Chapter 4: Simulation and Implementation
Table 4-1: LOC Grid & Package Pins Correlation for FG256/456 & FF672 . . . . . . . . . . . . . . . . . . 121
Table 4-2:
LOC Grid & Package Pins Correlation for FG676, FF896, and FF1152 . . . . . . . . . . . . 122
Table 4-3:
LOC Grid & Package Pins Correlation for FF1517 and FF1704 . . . . . . . . . . . . . . . . . . 123
Appendix A: RocketIO Transceiver Timing Model
Table A-1: RocketIO Clock Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table A-2: Parameters Relative to the RX User Clock (RXUSRCLK) . . . . . . . . . . . . . . . . . 128
Table A-3: Parameters Relative to the RX User Clock2 (RXUSRCLK2) . . . . . . . . . . . . . . . 129
Table A-4: Parameters Relative to the TX User Clock2 (TXUSRCLK2). . . . . . . . . . . . . . . . 129
Table A-5: Miscellaneous Clock Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Appendix B: 8B/10B Valid Characters
Table B-1: Valid Data Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table B-2: Valid Control Characters (K-Characters) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Appendix C: Related Online Documents
RocketIO™ Transceiver User Guide www.xilinx.com 17
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Preface
About This Guide
The RocketIO Transceiver User Guide provides the product designer with the detailed technical
information needed to successfully implement the RocketIO™ multi-gigabit transceiver in
Virtex-II Pro Platform FPGA designs.
RocketIO Features
The RocketIO transceiver’s flexible, programmable features allow a multi-gigabit serial transceiver
to be easily integrated into any Virtex-II Pro design:
• Variable-speed, full-duplex transceiver, allowing 600 Mb/s to 3.125 Gb/s baud transfer rates
• Monolithic clock synthesis and clock recovery system, eliminating the need for external
components
• Automatic lock-to-reference function
• Five levels of programmable serial output differential swing (800 mV to 1600 mV peak-peak),
allowing compatibility with other serial system voltage levels
• Four levels of programmable pre-emphasis
• AC and DC coupling
• Programmable 50Ω/75Ω on-chip termination, eliminating the need for external termination
resistors
• Serial and parallel TX-to-RX internal loopback modes for testing operability
• Programmable comma detection to allow for any protocol and detection of any 10-bit
character.
Guide Contents
The RocketIO Transceiver User Guide contains these sections:
• Preface, “About This Guide” — This section.
• Chapter 1, “RocketIO Transceiver Overview” — An overview of the transceiver’s capabilities
and how it works.
• Chapter 2, “Digital Design Considerations” — Ports and attributes for the six provided
communications protocol primitives; VHDL/Verilog code examples for clocking and reset
schemes; transceiver instantiation; 8B/10B encoding; CRC; channel bonding.
• Chapter 3, “Analog Design Considerations” — RocketIO serial overview; pre-emphasis; jitter;
clock/data recovery; PCB design requirements.
• Chapter 4, “Simulation and Implementation” — Simulation models; implementation tools;
debugging and diagnostics.
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Preface: About This Guide
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• Appendix A, “RocketIO Transceiver Timing Model” — Timing parameters associated with the
RocketIO transceiver core.
• Appendix B, “8B/10B Valid Characters” — Valid data and K-characters.
• Appendix C, “Related Online Documents” — Bibliography of online Application Notes,
Characterization Reports, and White Papers.
For More Information
For a complete menu of online information resources available on the Xilinx website, visit
http://www.xilinx.com/virtex2pro/
or refer to Appendix C, “Related Online Documents.”
For a comprehensive listing of available tutorials and resources on network technologies and
communications protocols, visit http://www.iol.unh.edu/training/
.
Additional Resources
For additional information, go to http://support.xilinx.com. The following table lists some of the
resources you can access from this website. You can also directly access these resources using the
provided URLs.
Resource Description/URL
Tutorials Tutorials covering Xilinx design flows, from design entry to verification
and debugging
http://support.xilinx.com/support/techsup/tutorials/index.htm
Answer Browser Database of Xilinx solution records
http://support.xilinx.com/xlnx/xil_ans_browser.jsp
Application Notes Descriptions of device-specific design techniques and approaches
http://support.xilinx.com/apps/appsweb.htm
Data Sheets Device-specific information on Xilinx device characteristics, including
readback, boundary scan, configuration, length count, and debugging
http://support.xilinx.com/xlnx/xweb/xil_publications_index.jsp
Problem Solvers Interactive tools that allow you to troubleshoot your design issues
http://support.xilinx.com/support/troubleshoot/psolvers.htm
Tech Tips Latest news, design tips, and patch information for the Xilinx design
environment
http://www.support.xilinx.com/xlnx/xil_tt_home.jsp
RocketIO™ Transceiver User Guide www.xilinx.com 19
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Conventions
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Conventions
This document uses the following conventions. An example illustrates each typographical and
online convention.
Port and Attribute Names
Input and output ports of the RocketIO transceiver primitives are denoted in upper-case letters.
Attributes of the RocketIO transceiver are denoted in upper-case letters with underscores. Trailing
numbers in primitive names denote the byte width of the data path. These values are preset and not
modifiable. When assumed to be the same frequency, RXUSRCLK and TXUSRCLK are referred to
as USRCLK and can be used interchangeably. This also holds true for RXUSRCLK2,
TXUSRCLK2, and USRCLK2.
Comma Definition
A comma is a “K-character” used by the transceiver to align the serial data on a byte/half-word
boundary (depending on the protocol used), so that the serial data is correctly decoded into parallel
data.
Typographical
The following typographical conventions are used in this document:
Convention Meaning or Use Example
Courier font
Messages, prompts, and program
files that the system displays
speed grade: - 100
Courier bold
Literal commands that you enter
in a syntactical statement
ngdbuild design_name
Helvetica bold
Commands that you select from a
menu
File → Open
Keyboard shortcuts Ctrl+C
Italic font
Variables in a syntax statement
for which you must supply values
ngdbuild design_name
References to other manuals
See the Development System
Reference Guide for more
information.
Emphasis in text
If a wire is drawn so that it
overlaps the pin of a symbol, the
two nets are not connected.
Square brackets [ ]
An optional entry or parameter.
However, in bus specifications,
such as bus[7:0], they are
required.
ngdbuild [ option_name]
design_name
Braces { }
A list of items from which you
must choose one or more
lowpwr ={on|off}
Vertical bar | Separates items in a list of choices lowpwr ={on|off}
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Preface: About This Guide
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Online Document
The following conventions are used in this document:
Vertical ellipsis
.
.
.
Repetitive material that has been
omitted
IOB #1: Name = QOUT’
IOB #2: Name = CLKIN’
.
.
.
Horizontal ellipsis . . .
Repetitive material that has been
omitted
allow block block_name
loc1 loc2 ... locn;
Convention Meaning or Use Example
Convention Meaning or Use Example
Blue text
Cross-reference link to a location
in the current document
See the section “Additional
Resources” for details.
Refer to “Title Formats” in
Chapter 1 for details.
Red text
Cross-reference link to a location
in another document
See Figure 2-5 in the Virtex-II
Handbook.
Blue, underlined text
Hyperlink to a website (URL)
Go to http://www.xilinx.com
for
the latest speed files.
RocketIO™ Transceiver User Guide www.xilinx.com 21
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Chapter 1
RocketIO Transceiver Overview
Basic Architecture and Capabilities
The RocketIO transceiver is based on Mindspeed’s SkyRail™ technology. Figure 1-1, page 23,
depicts an overall block diagram of the transceiver. Up to 20 transceiver modules are available on a
single Virtex-II Pro FPGA, depending on the part being used. Table 1-1 shows the RocketIO cores
available by device.
The transceiver module is designed to operate at any serial bit rate in the range of 600 Mb/s to
3.125 Gb/s per channel, including the specific bit rates used by the communications standards listed
in Table 1-2. The serial bit rate need not be configured in the transceiver, as the operating frequency
is implied by the received data, the reference clock applied, and the SERDES_10B attribute (see
Tabl e 1-3).
Table 1-1: Number of RocketIO Cores per Device Type
Device RocketIO Cores Device RocketIO Cores
XC2VP2 4 XC2VP40 0 or 12
XC2VP4 4 XC2VP50 0 or 16
XC2VP7 8 XC2VP70 16 or 20
XC2VP20 8 XC2VP100 0 or 20
XC2VP30 8
Table 1-2: Communications Standards Supported by RocketIO Transceiver
Mode
Channels
(Lanes)
(1)
I/O Bit Rate
(Gb/s)
Fibre Channel 1
1.06
2.12
Gbit Ethernet 1 1.25
XAUI (10-Gbit Ethernet) 4 3.125
XAUI (10-Gbit Fibre Channel)
(2)
4 3.1875
(3)
Infiniband 1, 4, 12 2.5
Aurora (Xilinx protocol) 1, 2, 3, 4, ... 0.600 – 3.125
Custom Mode 1, 2, 3, 4, ... 0.600 – 3.125
Notes:
1. One channel is considered to be one transceiver.
2. Supported with the GT_CUSTOM primitive. Certain attributes must be modified to comply with the XAUI
10GFC specifications, including but not limited to CLK_COR_SEQ and CHAN_BOND_SEQ.
3. Bit rate is possible with the following topology specification: maximum 6" FR4 and one Molex 74441 connector.
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Chapter 1: RocketIO Transceiver Overview
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Table 1-3: Serial Baud Rates and the SERDES_10B Attribute
SERDES_10B Serial Baud Rate
FALSE 1.0 Gb/s – 3.125 Gb/s
TRUE 600 Mb/s – 1.0 Gb/s
Figure 1-1: RocketIO Transceiver Block Diagram
FPGA FABRIC
MULTI-GIGABIT TRANSCEIVER CORE
Serializer
RXP
TXP
Clock
Manager
Power Down
PACKAGE
PINS
Deserializer
Comma
Detect
Realign
8B/10B
Decoder
TX
FIFO
CRC
Check
CRC
Channel Bonding
and
Clock Correction
CHBONDI[3:0]
CHBONDO[3:0]
8B/10B
Encoder
RX
Elastic
Buffer
Output
Polarity
RXN
GNDA
TXN
DS083-2_04_090402
POWERDOWN
RXRECCLK
RXPOLARITY
RXREALIGN
RXCOMMADET
RXRESET
RXCLKCORCNT
RXLOSSOFSYNC
RXDATA[15:0]
RXDATA[31:16]
RXCHECKINGCRC
RXCRCERR
RXNOTINTABLE[3:0]
RXDISPERR[3:0]
RXCHARISK[3:0]
RXCHARISCOMMA[3:0]
RXRUNDISP[3:0]
RXBUFSTATUS[1:0]
ENCHANSYNC
RXUSRCLK
RXUSRCLK2
CHBONDDONE
TXBUFERR
TXDATA[15:0]
TXDATA[31:16]
TXBYPASS8B10B[3:0]
TXCHARISK[3:0]
TXCHARDISPMODE[3:0]
TXCHARDISPVAL[3:0]
TXKERR[3:0]
TXRUNDISP[3:0]
TXPOLARITY
TXFORCECRCERR
TXINHIBIT
LOOPBACK[1:0]
TXRESET
REFCLK
REFCLK2
REFCLKSEL
ENPCOMMAALIGN
ENMCOMMAALIGN
TXUSRCLK
TXUSRCLK2
VTRX
AVCCAUXRX
VTTX
AVCCAUXTX
2.5V RX
TX/RX GND
Termination Supply RX
2.5V TX
Termination Supply TX
Serial Loopback Path
Parallel Loopback Path
BREFCLK
BREFCLK2
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Tabl e 1-4 lists the sixteen gigabit transceiver primitives provided. These primitives carry attributes
set to default values for the communications protocols listed in Ta ble 1-2. Data widths of one, two,
and four bytes are selectable for each protocol.
There are two ways to modify the RocketIO transceiver:
• Static properties can be set through attributes in the HDL code. Use of attributes are covered in
detail in “Primitive Attributes,” page 29.
• Dynamic changes can be made by the ports of the primitives
The RocketIO transceiver consists of the Physical Media Attachment (PMA) and Physical Coding
Sublayer (PCS). The PMA contains the serializer/deserializer (SERDES), TX and RX buffers, clock
generator, and clock recovery circuitry. The PCS contains the 8B/10B encoder/decoder and the
elastic buffer supporting channel bonding and clock correction. The PCS also handles Cyclic
Redundancy Check (CRC). Refer again to Figure 1-1, showing the RocketIO transceiver top-level
block diagram and FPGA interface signals.
RocketIO Transceiver Instantiations
For the different clocking schemes, several things must change, including the clock frequency for
USRCLK and USRCLK2 discussed in “Digital Clock Manager (DCM) Examples” in Chapter 2.
The data and control ports for GT_CUSTOM must also reflect this change in data width by
concatenating zeros onto inputs and wires for outputs for Verilog designs, and by setting outputs to
open and concatenating zeros on unused input bits for VHDL designs.
HDL Code Examples
Please use the Architecture Wizard to create instantiation templates. This wizard creates code and
instantiation templates that define the attributes for a specific application.
Table 1-4: Supported RocketIO Transceiver Primitives
Primitives Description Primitive Description
GT_C US TO M
Fully customizable
by user
GT_X AU I_ 2
10-Gb Ethernet,
2-byte data path
GT_FIBRE_CHAN_1
Fibre Channel,
1-byte data path
GT_X AU I_ 4
10-Gb Ethernet,
4-byte data path
GT_FIBRE_CHAN_2
Fibre Channel,
2-byte data path
GT_INFINIBAND_1
Infiniband, 1-byte
data path
GT_FIBRE_CHAN_4
Fibre Channel,
4-byte data path
GT_INFINIBAND_2
Infiniband, 2-byte
data path
GT_ETHERNET_1
Gigabit Ethernet,
1-byte data path
GT_INFINIBAND_4
Infiniband, 4-byte
data path
GT_ETHERNET_2
Gigabit Ethernet,
2-byte data path
GT_AURORA_1
Xilinx protocol,
1-byte data path
GT_ETHERNET_4
Gigabit Ethernet,
4-byte data path
GT_AURORA_2
Xilinx protocol,
2-byte data path
GT_XAUI_1
10-Gb Ethernet,
1-byte data path
GT_AURORA_4
Xilinx protocol,
4-byte data path
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List of Available Ports
The RocketIO transceiver primitives contain 50 ports, with the exception of the 46-port
GT_ETHERNET and GT_FIBRE_CHAN primitives. The differential serial data ports (RXN, RXP,
TXN, and TXP) are connected directly to external pads; the remaining 46 ports are all accessible
from the FPGA logic (42 ports for GT_ETHERNET and GT_FIBRE_CHAN).
Tabl e 1-5 contains the port descriptions of all primitives.
Table 1-5: GT_CUSTOM
(1)
, GT_AURORA, GT_FIBRE_CHAN
(2)
, GT_ETHERNET
(2)
,
GT_INFINIBAND, and GT_XAUI Primitive Ports
Port I/O
Port
Size
Definition
BREFCLK I 1 This high-quality reference clock uses dedicated routing to improve jitter for
serial speeds of 2.5 Gb/s or greater. See Table 2-2, page 40 for usage cases.
BREFCLK2 I 1 Alternative to BREFCLK. Can be selected by REFCLKSEL.
CHBONDDONE
(2)
O 1 Indicates a receiver has successfully completed channel bonding when asserted
High.
CHBONDI
(2)
I 4 The channel bonding control that is used only by “slaves” which is driven by a
transceiver's CHBONDO port.
CHBONDO
(2)
O 4 Channel bonding control that passes channel bonding and clock correction
control to other transceivers.
CONFIGENABLE I 1 Reconfiguration enable input (unused)
CONFIGIN I 1 Data input for reconfiguring transceiver (unused)
CONFIGOUT O 1 Data output for configuration readback (unused)
ENCHANSYNC
(2)
I 1 Comes from the core to the transceiver and enables the transceiver to perform
channel bonding
ENMCOMMAALIGN I 1 Selects realignment of incoming serial bitstream on minus-comma. High
realigns serial bitstream byte boundary when minus-comma is detected.
ENPCOMMAALIGN I 1 Selects realignment of incoming serial bitstream on plus-comma. High realigns
serial bitstream byte boundary when plus-comma is detected.
LOOPBACK I 2 Selects the two loopback test modes. Bit 1 is for serial loopback and bit 0 is for
internal parallel loopback.
POWERDOWN I 1 Shuts down both the receiver and transmitter sides of the transceiver when
asserted High. This decreases the power consumption while the transceiver is
shut down. This input is asynchronous.
REFCLK I 1 High-quality reference clock driving transmission (reading TX FIFO, and
multiplied for parallel/serial conversion) and clock recovery. REFCLK
frequency is accurate to ±100 ppm. This clock originates off the device, is
routed through fabric interconnect, and is selected by REFCLKSEL.
REFCLK2 I 1 An alternative to REFCLK. Can be selected by REFCLKSEL.
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REFCLKSEL I 1 Selects the reference clock to use:
Low = selects REFCLK if REF_CLK_V_SEL = 0
selects BREFCLK if REF_CLK_V_SEL = 1
High = selects REFCLK2 if REF_CLK_V_SEL = 0
selects BREFCLK2 if REF_CLK_V_SEL = 1
See “REF_CLK_V_SEL,” page 32.
RXBUFSTATUS O 2 Receiver elastic buffer status. Bit 1 indicates if an overflow/underflow error
has occurred when asserted High. Bit 0 indicates that the buffer is at least halffull when asserted High.
RXCHARISCOMMA
(3)
O 1, 2, 4 Similar to RXCHARISK except that the data is a comma.
RXCHARISK
(3)
O 1, 2, 4 If 8B/10B decoding is enabled, it indicates that the received data is a
K-character when asserted High. Included in Byte-mapping. If 8B/10B
decoding is bypassed, it remains as the first bit received (Bit “a”) of the 10-bit
encoded data (see Figure 2-14, page 66).
RXCHECKINGCRC O 1 CRC status for the receiver. Asserts High to indicate that the receiver has
recognized the end of a data packet. Only meaningful if RX_CRC_USE =
TRUE.
RXCLKCORCNT O 3 Status that denotes occurrence of clock correction or channel bonding. This
status is synchronized on the incoming RXDATA. See “RXCLKCORCNT,”
page 77.
RXCOMMADET O 1 Signals that a comma has been detected in the data stream.
To assure signal is reliably brought out to the fabric for different data paths, this
signal may remain High for more than one USRCLK/USRCLK2 cycle.
RXCRCERR O 1 Indicates if the CRC code is incorrect when asserted High. Only meaningful if
RX_CRC_USE = TRUE.
RXDATA
(3)
O 8, 16, 32 Up to four bytes of decoded (8B/10B encoding) or encoded (8B/10B bypassed)
receive data.
RXDISPERR
(3)
O 1, 2, 4 If 8B/10B encoding is enabled it indicates whether a disparity error has
occurred on the serial line. Included in Byte-mapping scheme.
RXLOSSOFSYNC O 2 Status related to byte-stream synchronization (RX_LOSS_OF_SYNC_FSM)
If RX_LOSS_OF_SYNC_FSM = TRUE, RXLOSSOFSYNC indicates the
state of the FSM:
Bit 1 = Loss of sync (High)
Bit 0 = Resync state (High)
If RX_LOSS_OF_SYNC_FSM = FALSE, RXLOSSOFSYNC indicates:
Bit 1 = Received data invalid (High)
Bit 0 = Channel bonding sequence recognized (High)
RXN
(4)
I 1 Serial differential port (FPGA external)
Table 1-5: GT_CUSTOM
(1)
, GT_AURORA, GT_FIBRE_CHAN
(2)
, GT_ETHERNET
(2)
,
GT_INFINIBAND, and GT_XAUI Primitive Ports (Continued)
Port I/O
Port
Size
Definition
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RXNOTINTABLE
(3)
O 1, 2, 4 Status of encoded data when the data is not a valid character when asserted
High. Applies to the byte-mapping scheme.
RXP
(4)
I 1 Serial differential port (FPGA external)
RXPOLARITY I 1 Similar to TXPOLARITY, but for RXN and RXP. When de-asserted, assumes
regular polarity. When asserted, reverses polarity.
RXREALIGN O 1 Signal from the PMA denoting that the byte alignment with the serial data
stream changed due to a comma detection. Asserted High when alignment
occurs.
RXRECCLK O 1 Clock recovered from the data stream by dividing its speed by 20.
RXRESET I 1 Synchronous RX system reset that “recenters” the receive elastic buffer. It also
resets 8B/10B decoder, comma detect, channel bonding, clock correction logic,
and other internal receive registers. It does not reset the receiver PLL.
RXRUNDISP
(3)
O 1, 2, 4 Signals the running disparity (0 = negative, 1 = positive) in the received serial
data. If 8B/10B encoding is bypassed, it remains as the second bit received (Bit
“b”) of the 10-bit encoded data (see Figure 2-14, page 66).
RXUSRCLK I 1 Clock from a DCM or a BUFG that is used for reading the RX elastic buffer. It
also clocks CHBONDI and CHBONDO in and out of the transceiver.
Typically, the same as TXUSRCLK.
RXUSRCLK2 I 1 Clock output from a DCM that clocks the receiver data and status between the
transceiver and the FPGA core. Typically the same as TXUSRCLK2. The
relationship between RXUSRCLK and RXUSRCLK2 depends on the width of
RXDATA.
TXBUFERR O 1 Provides status of the transmission FIFO. If asserted High, an
overflow/underflow has occurred. When this bit becomes set, it can only be
reset by asserting TXRESET.
TXBYPASS8B10B
(3)
I 1, 2, 4 This control signal determines whether the 8B/10B encoding is enabled or
bypassed. If the signal is asserted High, the encoding is bypassed. This creates
a 10-bit interface to the FPGA core. See the 8B/10B section for more details.
TXCHARDISPMODE
(3)
I 1, 2, 4 If 8B/10B encoding is enabled, this bus determines what mode of disparity is
to be sent. When 8B/10B is bypassed, this becomes the first bit transmitted (Bit
“a”) of the 10-bit encoded TXDATA bus section (see Figure 2-13, page 66) for
each byte specified by the byte-mapping.
TXCHARDISPVAL
(3)
I 1, 2, 4 If 8B/10B encoding is enabled, this bus determines what type of disparity is to
be sent. When 8B/10B is bypassed, this becomes the second bit transmitted
(Bit “b”) of the 10-bit encoded TXDATA bus section (see Figure 2-13,
page 66) for each byte specified by the byte-mapping section.
TXCHARISK
(3)
I 1, 2, 4 If 8B/10B encoding is enabled, this control bus determines if the transmitted
data is a K-character or a Data character. A logic High indicates a K-character.
Table 1-5: GT_CUSTOM
(1)
, GT_AURORA, GT_FIBRE_CHAN
(2)
, GT_ETHERNET
(2)
,
GT_INFINIBAND, and GT_XAUI Primitive Ports (Continued)
Port I/O
Port
Size
Definition
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TXDATA
(3)
I 8, 16, 32 Transmit data that can be 1, 2, or 4 bytes wide, depending on the primitive
used. TXDATA [7:0] is always the last byte transmitted. The position of the
first byte depends on selected TX data path width.
TXFORCECRCERR I 1 Specifies whether to insert error in computed CRC.
When TXFORCECRCERR = TRUE, the transmitter corrupts the correctly
computed CRC value by XORing with the bits specified in attribute
TX_CRC_FORCE_VALUE. This input can be used to test detection of CRC
errors at the receiver.
TXINHIBIT I 1 If a logic High, the TX differential pairs are forced to be a constant 1/0.
TXN = 1, TXP = 0
TXKERR
(3)
O 1, 2, 4 If 8B/10B encoding is enabled, this signal indicates (High) when the
K-character to be transmitted is not a valid K-character. Bits correspond to the
byte-mapping scheme.
TXN
(4)
O 1 Transmit differential port (FPGA external)
TXP
(4)
O 1 Transmit differential port (FPGA external)
TXPOLARITY I 1 Specifies whether or not to invert the final transmitter output. Able to reverse
the polarity on the TXN and TXP lines. Deasserted sets regular polarity.
Asserted reverses polarity.
TXRESET I 1 Synchronous TX system reset that “recenters” the transmit elastic buffer. It
also resets 8B/10B encoder and other internal transmission registers. It does
not reset the transmission PLL.
TXRUNDISP
(3)
O 1, 2, 4 Signals the running disparity after this byte is encoded. Low indicates negative
disparity, High indicates positive disparity.
TXUSRCLK I 1 Clock output from a DCM or a BUFG that is clocked with a reference clock.
This clock is used for writing the TX buffer and is frequency-locked to the
reference clock.
TXUSRCLK2 I 1 Clock output from a DCM that clocks transmission data and status and
reconfiguration data between the transceiver an the FPGA core. The ratio
between TXUSRCLK and TXUSRCLK2 depends on the width of TXDATA.
Notes:
1. The GT_CUSTOM ports are always the maximum port size.
2. GT_FIBRE_CHAN and GT_ETHERNET ports do not have the three CHBOND** or ENCHANSYNC ports.
3. The port size changes with relation to the primitive selected, and also correlates to the byte mapping.
4. External ports only accessible from package pins.
Table 1-5: GT_CUSTOM
(1)
, GT_AURORA, GT_FIBRE_CHAN
(2)
, GT_ETHERNET
(2)
,
GT_INFINIBAND, and GT_XAUI Primitive Ports (Continued)
Port I/O
Port
Size
Definition
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Primitive Attributes
The primitives also contain attributes set by default to specific values controlling each specific
primitive’s protocol parameters. Included are channel-bonding settings (for primitives supporting
channel bonding), clock correction sequences, and CRC. Tab le 1-6 shows a brief description of each
attribute. Table 1- 7 and Table 1-8 have the default values of each primitive.
Table 1-6: RocketIO Transceiver Attributes
Attribute Description
ALIGN_COMMA_MSB TRUE/FALSE controls the alignment of detected commas within the transceiver’s
2-byte-wide data path.
FALSE: Align commas within a 10-bit alignment range. As a result the comma
is aligned to either RXDATA[15:8} byte or RXDATA [7:0] byte in the
transceivers internal data path.
TRUE: Aligns comma with 20-bit alignment range.
As a result aligns on the RXDATA[15:8] byte.
Notes:
1. If protocols (like Gigabit Ethernet) are oriented in byte pairs with commas always in even
(first) byte formation, this can be set to TRUE. Otherwise, it should be set to FALSE.
2. For 32-bit data path primitives, see “32-bit Alignment Design,” page 95.
3. This attribute is only modifiable in the GT_CUSTOM primitive.
CHAN_BOND_LIMIT Integer 1-31 that defines maximum number of bytes a slave receiver can read
following a channel bonding sequence and still successfully align to that sequence.
CHAN_BOND_MODE STRING
OFF, MASTER, SLAVE_1_HOP, SLAVE_2_HOPS
OFF: No channel bonding involving this transceiver.
MASTER: This transceiver is master for channel bonding. Its CHBONDO port
directly drives CHBONDI ports on one or more SLAVE_1_HOP transceivers.
SLAVE_1_HOP: This transceiver is a slave for channel bonding.
SLAVE_1_HOP’s CHBONDI is directly driven by a MASTER transceiver
CHBONDO port. SLAVE_1_HOP’s CHBONDO port can directly drive
CHBONDI ports on one or more SLAVE_2_HOPS transceivers.
SLAVE_2_HOPS: This transceiver is a slave for channel bonding.
SLAVE_2_HOPS CHBONDI is directly driven by a SLAVE_1_HOP
CHBONDO port.
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CHAN_BOND_OFFSET Integer 0-15 that defines offset (in bytes) from channel bonding sequence for
realignment. It specifies the first elastic buffer read address that all channel-bonded
transceivers have immediately after channel bonding.
CHAN_BOND_WAIT specifies the number of bytes that the master transceiver
passes to RXDATA, starting with the channel bonding sequence, before the
transceiver executes channel bonding (alignment) across all channel-bonded
transceivers.
CHAN_BOND_OFFSET specifies the first elastic buffer read address that all
channel-bonded transceivers have immediately after channel bonding (alignment),
as a positive offset from the beginning of the matched channel bonding sequence in
each transceiver.
For optimal performance of the elastic buffer, CHAN_BOND_WAIT and
CHAN_BOND_OFFSET should be set to the same value (typically 8).
CHAN_BOND_ONE_SHOT TRUE/FALSE that controls repeated execution of channel bonding.
FALSE: Master transceiver initiates channel bonding whenever possible
(whenever channel-bonding sequence is detected in the input) as long as input
ENCHANSYNC is High and RXRESET is Low.
TRUE: Master transceiver initiates channel bonding only the first time it is
possible (channel bonding sequence is detected in input) following negated
RXRESET and asserted ENCHANSYNC. After channel-bonding alignment is
done, it does not occur again until RXRESET is asserted and negated, or until
ENCHANSYNC is negated and reasserted.
Always set Slave transceivers CHAN_BOND_ONE_SHOT to FALSE.
CHAN_BOND_SEQ_*_* 11-bit vectors that define the channel bonding sequence. The usage of these vectors
also depends on CHAN_BOND_SEQ_LEN and CHAN_BOND_SEQ_2_USE. See
“Receiving Vitesse Channel Bonding Sequence,” page 66, for format.
CHAN_BOND_SEQ_2_USE Controls use of second channel bonding sequence.
FALSE: Channel bonding uses only one channel bonding sequence defined by
CHAN_BOND_SEQ_1_1...4.
TRUE: Channel bonding uses two channel bonding sequences defined by:
CHAN_BOND_SEQ_1_1...4 and
CHAN_BOND_SEQ_2_1...4
as further constrained by CHAN_BOND_SEQ_LEN.
CHAN_BOND_SEQ_LEN Integer 1-4 defines length in bytes of channel bonding sequence. This defines the
length of the sequence the transceiver matches to detect opportunities for channel
bonding.
CHAN_BOND_WAIT Integer 1-15 that defines the length of wait (in bytes) after seeing channel bonding
sequence before executing channel bonding.
Table 1-6: RocketIO Transceiver Attributes (Continued)
Attribute Description
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CLK_COR_INSERT_IDLE_FLAG TRUE/FALSE controls whether RXRUNDISP input status denotes running
disparity or inserted-idle flag.
FALSE: RXRUNDISP denotes running disparity when RXDATA is decoded
data.
TRUE: RXRUNDISP is raised for the first byte of each inserted (repeated) clock
correction (“Idle”) sequence (when RXDATA is decoded data).
CLK_COR_KEEP_IDLE TRUE/FALSE controls whether or not the final byte stream must retain at least one
clock correction sequence.
FALSE: Transceiver can remove all clock correction sequences to further
recenter the elastic buffer during clock correction.
TRUE: In the final RXDATA stream, the transceiver must leave at least one
clock correction sequence per continuous stream of clock correction
sequences.
CLK_COR_REPEAT_WAIT Integer 0 - 31 controls frequency of repetition of clock correction operations.
This attribute specifies the minimum number of RXUSRCLK cycles without clock
correction that must occur between successive clock corrections. If this attribute is
zero, no limit is placed on how frequently clock correction can occur.
CLK_COR_SEQ_*_* 11-bit vectors that define the sequence for clock correction. The attribute used
depends on the CLK_COR_SEQ_LEN and CLK_COR_SEQ_2_USE.
CLK_COR_SEQ_2_USE TRUE/FALSE controls use of second clock correction sequence.
FALSE: Clock correction uses only one clock correction sequence defined by
CLK_COR_SEQ_1_1...4.
TRUE: Clock correction uses two clock correction sequences defined by:
CLK_COR_SEQ_1_1...4 and
CLK_COR_SEQ_2_1...4
as further constrained by CLK_COR_SEQ_LEN.
CLK_COR_SEQ_LEN Integer that defines the length of the sequence the transceiver matches to detect
opportunities for clock correction. It also defines the size of the correction, since the
transceiver executes clock correction by repeating or skipping entire clock
correction sequences.
CLK_CORRECT_USE TRUE/FALSE controls the use of clock correction logic.
FALSE: Permanently disable execution of clock correction (rate matching).
Clock RXUSRCLK must be frequency-locked with RXRECCLK in this case.
TRUE: Enable clock correction (normal mode).
COMMA_10B_MASK This 10-bit vector defines the mask that is ANDed with the incoming serial bit
stream before comparison against PCOMMA_10B_VALUE and
MCOMMA_10B_VALUE.
CRC_END_OF_PKT NOTE: This attribute is only valid when CRC_FORMAT = USER_MODE.
K28_0, K28_1, K28_2, K28_3, K28_4, K28_5, K28_6, K28_7, K23_7, K27_7,
K29_7, K30_7. End-of-packet (EOP) K-character for USER_MODE CRC. Must be
one of the 12 legal K-character values.
Table 1-6: RocketIO Transceiver Attributes (Continued)
Attribute Description
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