Xilinx ML403 User Manual

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Application Note: Embedded Processing

 

 

 

 

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Reference System: OPB IIC Using the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ML403 Evaluation Platform

 

 

 

 

 

XAPP979 (v1.0) February 26, 2007

Author: Paul Glover, Ed Meinelt, Lester Sanders

 

 

 

 

 

 

Summary

This application note describes how to build a reference system for the On-Chip Peripheral Bus Inter IC (OPB IIC) core using the IBM PowerPC™ 405 Processor (PPC405) based embedded system in the ML403 Embedded Development Platform. The reference system is Base System Builder (BSB) based.

An IIC primer is given and an OPB IIC register reference is provided. The Xilinx Microprocessor Debugger (XMD) commands are used for verifying that the OPB IIC core operates correctly. Several software projects illustrate how to configure the OPB IIC core, set up interrupts, and do read and write operations. Some of the software projects interface the OPB IIC to the MicroChip 24LC04B serial EEPROM with an IIC interface, while others interface to the TotalPhase Aardvark Adapter, which provides IIC master and slave functionality. The procedure for using ChipScope™ to analyze OPB IIC functionality is provided. The steps used to build a Linux kernel using MontaVista are listed. Simulation output files for analyzing basic IIC transactions are provided.

Included

Systems

Required

Hardware/Tools

This application note includes one reference system:

www.xilinx.com/bvdocs/appnotes/xapp979.zip

The project name used in xapp979.zip is ml403_ppc_opb_iic.

Users must have the following tools, cables, peripherals, and licenses available and installed:

Xilinx EDK 8.2.02i

Xilinx ISE 8.2.03

Xilinx Download Cable (Platform Cable USB or Parallel Cable IV)

Monta Vista Linux v2.4 Development Kit

Modeltech ModelSim v6.1d

ChipScope v8.2

© 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. PowerPC is a trademark of IBM Inc. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.

XAPP979 (v1.0) February 26, 2007

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Introduction

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Introduction

This application note accompanies a reference system built on the ML403 development board. Figure 1 is a block diagram of the reference system.

OPB

 

OPB UART

 

OPB

INTC

 

16550

 

IIC

PowerPC™

405 Processor

OPB

PLB

PLB

PLB

DDR

BRAM

X979_01_022307

Figure 1: OPB IIC Reference System Block Diagram

The system uses the embedded PowerPC (PPC) as the microprocessor and the OPB IIC core.

IIC Primer

Figure 2 shows components on an IIC bus.Two IIC masters and three IIC slaves are shown. The master is responsible for setting up transactions. This includes generating the clock on SCL and defining which slave is involved in the communication, with an address field, and which component is transmitting and which component is receiving. Some components are slave only, while others can transition between master and slave operation.

M1

M2

SCL SDA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

S1

 

S2

 

 

S3

 

 

 

 

 

 

 

 

 

 

X979_02_022307

Figure 2: IIC Bus

Figure 3 shows the START and STOP conditions. A START condition is a falling edge on SDA when SCL is high. A STOP condition is a rising edge on SDA when SCL is high. During data transfer, the data line is stable on SDA when SCL is high. Data transitions on SDA when SCL is low. Note that the START and STOP conditions are special conditions, violating the rule that data cannot transition while SCL is high.

SDA

SCL

Start

Stop

X979_03_022307

Figure 3: Start and Stop Conditions

XAPP979 (v1.0) February 26, 2007

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Introduction

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Figure 4 shows the format of the data transfer of two bytes on the IIC bus, beginning with the START (S) condition and ending with the STOP (P) condition, bounded by an idle IIC (F) bus. After a START condition, an eight bit field is transmitted containing a 7 bit address and a single Read/Write (R/W) bit. This 8 bit address/direction field is followed by an Acknowledge bit. After the address/data field, an eight bit data field is followed by an acknowledge bit (A). The last 8- bit data field is followed by a not acknowledge bit (A). This is followed by the STOP condition

(P).

A single message can contain multiple start conditions, or a repeated start, without intervening STOP conditions.

In this data transfer, there are two acknowledge bits and one Not Acknowledge on the IIC bus. The distinction between a Not Acknowledge and a No Acknowledge is that Not Acknowledge occurs after a master has read a byte from a slave and a No Acknowledge occurs after a master has written a byte to a slave.

A synchronized SCL is generated with its LOW period determined by the device with the longest low period and its HIGH period determined by the device with the shortest HIGH period.

F

S

Slave

R/W

A

Data

A

Data

 

 

 

P

F

 

A

Address

 

 

 

 

 

 

 

 

 

 

 

 

 

SDA

SCL

X979_04_012907

Figure 4: Data Transfer on the IIC Bus

Figure 5 shows the data transfer on the IIC bus, beginning with the START condition and ending with the STOP condition.

SDA

 

 

 

 

 

 

 

MSB

 

 

Acknowledgment

 

 

 

 

 

 

 

 

 

 

signal from slave

 

 

 

 

 

Byte complete;

 

 

 

 

interrupt within slave

SCL S

1

2

7

8

9

 

or

 

 

 

 

ACK

SR

START or repeated START condition

P

Acknowledgment Sr signal from receiver

Clock lines held low while interrupts are serviced

1

2

3 - 8

9

Sr

 

 

 

ACK

or

 

 

 

 

P

STOP or repeated START condition

X979_05_022307

Figure 5: Generic Data Transer on the IIC Bus

XAPP979 (v1.0) February 26, 2007

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Reference System Specifics

Figure 6 shows the acknowledge bit on the IIC bus.

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Data output

 

 

 

 

 

by transmitter

 

 

 

 

 

Data output

 

 

 

Not acknowledge

 

 

 

 

 

 

by receiver

 

 

 

 

 

SCL from

 

 

 

Acknowledge

 

 

 

 

 

 

master

S

1

2

8

9

 

 

 

 

 

 

 

START

 

 

Clock pulse for

 

 

condition

 

 

acknowledgment

 

X979_06_012907

Figure 6: Acknowledge on the IIC Bus

Reference

System

Specifics

Figure 7 shows bus arbitration of two masters. The IIC bus is a multi-master bus. Masters monitor the IIC bus to determine if the bus is active. The bus is inactive when SCL and SDA are high for a bus free period tBUF of 1.3 us (FAST) or 4.7 us (STD). If two or more masters monitoring the IIC bus determine that the bus is free and begin a bus transaction simultaneously, the IIC bus is arbitrated to determine which master owns the bus. The IIC is a wired AND bus. This means that the bus is HIGH unless any component is driving it LOW.

Masters monitor the bus even after they have started a transaction as the master. If a master is not driving the IIC bus low and the bus is low, the master knows that another master is driving the IIC bus. If a master cannot get the SDA or SCL to go high it loses arbitration. When a master loses arbitration, it stops transmission. The master driving the bus with the last low when the other master(s) drives high becomes the master of the bus.

Master 1

Master 2

SDA

SCL

S

X979_07_012907

 

Figure 7: Arbitration of two Masters

In addition to the PowerPC405 processor and OPB IIC, this system includes DDR and BRAM memory on the PLB, and a UART and interrupt controller on the OPB. Figure 1 provides the block diagram. Table 1 provides the address map of the ML403 XC4VFX12. This is in the system.mhs.

XAPP979 (v1.0) February 26, 2007

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Reference System Specifics

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ML403 XC4VFX12 Address Map

Table 1: ML403 XC4VSX12 System Address Map

Peripheral

Instance

Base Address

High Address

 

 

 

 

PLB_DDR

DDR_SDRAM_32Mx64

0x00000000

0x03FFFFFF

 

 

 

 

OPB UART16550

RS232_Uart_1

0x40400000

0x4040FFFF

 

 

 

 

OPB INTC

opb_intc_0

0x41200000

0x4120FFFF

 

 

 

 

PLB BRAM

plb_bram_if_cntlr_0

0xFFFF8000

0xFFFFFFFF

 

 

 

 

OPB IIC

IIC_EEPROM

0x40800000

0x4080FFFF

 

 

 

 

OPB IIC Registers

Table 2 provides the register map for the OPB IIC core.

Table 2: OPB IIC Registers

Register

Address

 

 

Device Global Interrupt Enable

C_BASEADDR + 0x01C

 

 

Interrupt Status Register

C_BASEADDR + 0x020

 

 

Interrupt Enable Register

C_BASEADDR + 0x028

 

 

Software Reset Register

C_BASEADDR + 0x040

 

 

Control Register

C_BASEADDR + 0x100

 

 

Status Register

C_BASEADDR + 0x104

 

 

Transmit FIFO

C_BASEADDR + 0x108

 

 

Receive FIFO

C_BASEADDR + 0x10C

 

 

Slave Address Register

C_BASEADDR + 0x110

 

 

Transmit FIFO Occupancy

C_BASEADDR + 0x114

 

 

Receive FIFO Occupancy

C_BASEADDR + 0x118

 

 

Ten Bit Slave Address Register

C_BASEADDR + 0x11C

 

 

Receive FIFO Programmable Depth Interrupt Register

C_BASEADDR + 0x120

 

 

General Purpose Output

C_BASEADDR + 0x124

 

 

Table 3 provides a description of the OPB IIC control register.

Table 3: OPB IIC Control Register

Bit(s)

Name

Description

 

 

 

0- 24

Reserved

Reserved.

 

 

 

25

GC_EN

General Call Enable. Setting this bit High allows the OPB IIC to respond to a

general call address.

 

 

 

 

 

 

 

Repeated Start. Writing a “1” to this bit generates a repeated START condition

 

 

on the bus if the OPB IIC Bus Interface is the current bus Master. Attempting a

26

RSTA

repeated START at the wrong time, if the bus is owned by another Master, results

 

 

in a loss of arbitration. This bit is reset when the repeated start occurs. This bit

 

 

must be set prior to writing the new address to the Tx FIFO or DTR.

 

 

 

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Reference System Specifics

Table 3: OPB IIC Control Register (Contd)

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Bit(s)

Name

Description

 

 

 

 

 

Transmit Acknowledge Enable. This bit specifies the value driven onto the SDA

 

 

line during acknowledge cycles for both Master and Slave receivers.

27

TXAK

Because Master receivers indicate the end of data reception by not

acknowledging the last byte of the transfer, this bit is used to end a Master

 

 

 

 

receiver transfer. As a slave, this bit must be set prior to receiving the byte to no

 

 

acknowledge.

 

 

 

 

 

Transmit/Receive Mode Select. This bit selects the direction of Master/Slave

28

TX

transfers. This bit does not control the Read/Write bit that is sent on the bus with

the address. The Read/Write bit that is sent with an address must be the LSB of

 

 

 

 

the address written into the transmit FIFO.

 

 

 

 

 

Master/Slave Mode Select. When this bit is changed from 0 to 1, the OPB IIC

 

 

Bus Interface generates a START condition in Master mode. When this bit is

29

MSMS

cleared, a STOP condition is generated and the OPB IIC Bus Interface switches

 

 

to Slave mode. When this bit is cleared by the hardware, because arbitration for

 

 

the bus has been lost, a STOP condition is not generated.

 

 

 

30

Tx FIFO

Transmit FIFO Reset. This bit must be set if arbitration is lost or if a transmit error

Reset

occurs to flush the FIFO.

 

 

 

 

31

EN

OPB IIC Enable. This bit must be set before any other CR bits have any effect.

 

 

 

Status Register (SR)

This register contains the status of the OPB IIC Bus Interface. All bits are cleared upon reset. Table 4 provides a definition of the status register.

Table 4: Status Register Bit Definitions

Bit(s)

Name

Description

 

 

 

0 - 23

N/A

Reserved.

 

 

 

24

Tx_FIFO_

Transmit FIFO empty. This bit is set High when the transmit FIFO is

 

Empty

empty.

 

 

 

25

Rc_FIFO_

Receive FIFO empty. This is set High when the receive FIFO is empty.

 

Empty

 

 

 

 

26

Rc_FIFO_

Receive FIFO full. This bit is set High when the receive FIFO is full.

 

Full

This bit is set only when all sixteen locations in the FIFO are full,

 

 

regardless of the value written into Rc_FIFO_PIRQ.

 

 

 

27

Tx_FIFO_F

Transmit FIFO full. This bit is set High when the transmit FIFO is full.

 

ull

 

 

 

 

28

SRW

Slave Read/Write. When the IIC Bus Interface has been addressed as

 

 

a Slave (AAS is set), this bit indicates the value of the read/write bit

 

 

sent by the Master. This bit is only valid when a complete transfer has

 

 

occurred and no other transfers have been initiated. A “1” indicates

 

 

Master reading from Slave. A “0” indicates Master writing to Slave.

 

 

 

29

BB

Bus Busy. This bit indicates the status of the IIC bus. This bit is set

 

 

when a START condition is detected and cleared when a STOP

 

 

condition is detected.

 

 

 

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Reference System Specifics

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Table 4:

Status Register Bit Definitions (Contd)

 

 

 

 

Bit(s)

 

Name

Description

 

 

 

 

30

 

AAS

Addressed as Slave. When the address on the IIC bus matches the

 

 

 

Slave address in the Address Register (ADR), the IIC Bus Interface is

 

 

 

being addressed as a Slave and switches to Slave mode. If 10-bit

 

 

 

addressing is selected this device will only respond to a 10-bit address

 

 

 

or general call if enabled. This bit is cleared when a stop condition is

 

 

 

detected or a repeated start occurs.

 

 

 

 

31

 

ABGC

Addressed By a General Call. This bit is set high when another

 

 

 

master has issued a general call and the general call enable bit is set

 

 

 

high, CR(1) = ’1’.

 

 

 

 

Table 5 provides a register description of the Interrupt Status register.

Table

5: Interrupt Status Register

 

 

 

 

 

 

 

Bit

Name

 

Description

 

 

 

 

 

24

 

TFHE

 

Transmit FIFO Half Empty

 

 

 

 

 

25

 

NAAS

 

Not Addressed as Slave

 

 

 

 

 

26

 

AAS

 

Addressed as Slave

 

 

 

 

 

27

 

BNB

 

Bus is not Busy

 

 

 

 

 

28

 

RFF

 

Receive FiFO Full

 

 

 

 

 

29

 

TFE

 

Transmit FIFO Empty

 

 

 

 

 

30

 

TE/STC

 

Transmit Error/Slave Transmit Complete

 

 

 

 

 

31

 

AL

 

Arbitration Lost

 

 

 

 

 

XAPP979 (v1.0) February 26, 2007

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Reference System Specifics

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Configuring the OPB IIC Core

Figure 8 shows how to specify the values of IIC generics in EDK. To access the dialog box in the figure, double click on the OPB IIC core in the EDK System Assembly View..

X979_08_012907

Figure 8: Specifying the Values of OPB IIC Generics in EDK

Microchip 24LC04

The Microchip Technology 24LC04B-I/ST with 4-KB EEPROM is provided on the ML403 board to store non-volatile data. The EEPROM write protect is tied off on the board to disable its hardware write protect. The IIC bus is extended to the expansion connector to allow additional devices to be added to the IIC bus.

Figure 9 shows IIC Bus Devices on the ML403.

 

 

 

 

 

 

 

 

 

XC4VSX12

 

 

SCL

 

 

 

 

Microchip

 

 

 

 

 

 

 

 

 

 

 

 

FPGA

 

 

SDA

 

 

 

24LC04B

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/O

 

 

 

 

 

 

 

 

Expansion

 

 

 

 

 

 

 

 

Header

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X979_09_022307

Figure 9: ML403 IIC Bus

The 24LC04 is organized as two blocks of 256 bytes. It has a page write buffer of up to 16 bytes. The 24LC04 operates as an IIC slave. The 24LC04 accepts a control byte which contains control code, block select, and Read/Write fields shown in Figure 10. The control code

XAPP979 (v1.0) February 26, 2007

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ML403 Board Information

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ML403 Board

Information

is ‘1010 for read and write operations. The A2, A1 bits are dont cares. The A0 bit is used by the master device to select which of the two 256-word blocks of memory are accessed. The 24LC04 write transactions are either a byte write or a page write. The page write begins the same as the byte write but instead of generating a stop condition the master transmits up to 16 data bytes to the 24LC04B. The 24LC04 supports current address, random, and sequential read operations.

Slave

Address

S

 

 

 

 

 

 

 

R/W

A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

0

1

0

A2

A1

A0

 

 

 

 

 

 

 

 

 

 

 

 

X979_10_012907

Figure 10: 24LC04 Control Byte Allocation

According to the MicroChip 24L024B data sheet, the ML403 board has a low-level output current (IOL) of 3.0 mA at a VCC of 2.5v. The ML403 boards are shipped in the configuration shown in Figure 11. The board must be modified for this design to work correctly. Replace the 10K Ohm R70 and R71resistors with 833 or 1K Ohm resistors. See Answer Record 24049 for additional information.

 

 

C280

VCC2V5

 

 

 

 

 

0.1 µF

 

 

2

2

 

 

 

24LC04B - I / ST

 

 

 

1

8

 

R70

 

R71

 

A0

VCC

 

 

 

 

10k

 

10k

 

2

A1

WP

7

1

1

IIC_SCL

 

3

A2

SCL

6

 

 

 

 

 

 

 

IIC_SDA

 

4

A3

SDA

5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

U9

TSSOPS

 

 

 

 

 

 

X979_11_022307

Figure 11: ML40x Schematic for IIC Connections

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Xilinx ML403 User Manual

ML403 Board Information

The resistors are located on the board as shown in Figure 12.

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X979_12_022307

Figure 12: ML40x Resistors

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