Xilinx UG154 User Manual

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LogiCORE™ IP

SPI-4.2 Core v8.5

Getting Started Guide

UG154 March 24, 2008

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Xilinx UG154 User Manual

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"Xilinx" and the Xilinx logo shown above are registered trademarks of Xilinx, Inc. Any rights not expressly granted herein are reserved.

CoolRunner, RocketChips, Rocket IP, Spartan, StateBENCH, StateCAD, Virtex, XACT, XC2064, XC3090, XC4005, and XC5210 are registered trademarks of Xilinx, Inc.

The shadow X shown above is a trademark of Xilinx, Inc.

ACE Controller, ACE Flash, A.K.A. Speed, Alliance Series, AllianceCORE, Bencher, ChipScope, Configurable Logic Cell, CORE Generator, CoreLINX, Dual Block, EZTag, Fast CLK, Fast CONNECT, Fast FLASH, FastMap, Fast Zero Power, Foundation, Gigabit Speeds...and Beyond!, HardWire, HDL Bencher, IRL, J Drive, JBits, LCA, LogiBLOX, Logic Cell, LogiCORE, LogicProfessor, MicroBlaze, MicroVia, MultiLINX, NanoBlaze, PicoBlaze, PLUSASM, PowerGuide, PowerMaze, QPro, Real-PCI, RocketIO, SelectIO, SelectRAM, SelectRAM+, Silicon Xpresso, Smartguide, Smart-IP, SmartSearch, SMARTswitch, System ACE, Testbench In A Minute, TrueMap, UIM, VectorMaze, VersaBlock, VersaRing, Virtex-II Pro, Virtex-II EasyPath, Virtex-4, Wave Table, WebFITTER, WebPACK, WebPOWERED, XABEL, XACTFloorplanner, XACT-Performance, XACTstep Advanced, XACTstep Foundry, XAM, XAPP, X-BLOX +, XC designated products, XChecker, XDM, XEPLD, Xilinx Foundation Series, Xilinx XDTV, Xinfo, XSI, XtremeDSP and ZERO+ are trademarks of Xilinx, Inc.

The Programmable Logic Company is a service mark of Xilinx, Inc.

All other trademarks are the property of their respective owners.

Xilinx, Inc. does not assume any liability arising out of the application or use of any product described or shown herein; nor does it convey any license under its patents, copyrights, or maskwork rights or any rights of others. Xilinx, Inc. reserves the right to make changes, at any time, in order to improve reliability, function or design and to supply the best product possible. Xilinx, Inc. will not assume responsibility for the use of any circuitry described herein other than circuitry entirely embodied in its products. Xilinx provides any design, code, or information shown or described herein "as is." By providing the design, code, or information as one possible implementation of a feature, application, or standard, Xilinx makes no representation that such implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of any such implementation, including but not limited to any warranties or representations that the implementation is free from claims of infringement, as well as any implied warranties of merchantability or fitness for a particular purpose. Xilinx, Inc. devices and products are protected under U.S. Patents. Other U.S. and foreign patents pending. Xilinx, Inc. does not represent that devices shown or products described herein are free from patent infringement or from any other third party right. Xilinx, Inc. assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made. Xilinx, Inc. will not assume any liability for the accuracy or correctness of any engineering or software support or assistance provided to a user.

Xilinx products are not intended for use in life support appliances, devices, or systems. Use of a Xilinx product in such applications without the written consent of the appropriate Xilinx officer is prohibited.

The contents of this manual are owned and copyrighted by Xilinx. Copyright 2004-2008 Xilinx, Inc. All Rights Reserved. Except as stated herein, none of the material may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of any material contained in this manual may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes.

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UG154 March 24, 2008

Revision History

The following table shows the revision history for this document.

Date

Version

Revision

 

 

 

09/30/04

1.0

Initial Xilinx release.

 

 

 

11/11/04

1.1

Document updated to support SPI-4.2 core v7.1.

 

 

 

04/28/05

1.2

Document updated to support SPI-4.2 core v7.2 and Xilinx ISE v7.1i.

 

 

 

08/31/05

2.0

Updated ISE service pack information.

 

 

 

1/18/06

3.0

Updated ISE to v8.1i, release date

 

 

 

7/13/06

4.0

Added support for Virtex-5, ISE to v8.2i, advanced version number and release date.

 

 

 

9/21/06

4.1

Updted for IP2i minor release. Removed Simulating the Dynamic Alignment Sink

 

 

core section from the example design chapter.

 

 

 

2/15/07

4.2

Updated system requirements, ISE version, and applied new directory structure

 

 

template to Chapter 4.

 

 

 

8/08/07

4.3

Updated for IP1 Jade Minor release. ISE version to 9.2i.

 

 

 

3/24/08

4.4

Updated core to v8.5, updated supported tool versions, and release date.

 

 

 

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Table of Contents

Schedule of Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Schedule of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Preface: About This Guide

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Typographical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Chapter 1: Introduction

System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

About the Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Recommended Design Experience. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Additional Core Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Technical Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Feedback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Chapter 2: Licensing the Core

Before you Begin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 License Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Simulation-Only Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Full System Hardware Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Full . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Obtaining Your License . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Installing Your License File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Chapter 3: Quick Start Example Design

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Generating the Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Implementing the Example Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Running the Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Setting up for Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Functional Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Timing Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Chapter 4: Detailed Example Design

Directory and File Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

<project directory> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

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<project directory>/<component name> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 <component name>/doc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 <component name>/example design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 <component name>/implement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 implement/results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 <component name>/simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 simulation/functional . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 simulation/timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Implementation and Simulation Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Simulation Script Details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Example Design Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Loopback Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Basic Loopback Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Demonstration Test Bench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Startup Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Stimulus Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Procedures Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Data Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Status Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Customizing the Demonstration Test Bench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Test Case Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Testcase Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Calendar Sequence Files (Sink and Source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Appendix A: VHDL Details

Procedures Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Appendix B: Verilog Details

Procedures Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Random Testcase Sample Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Appendix C: Data and Status Monitor Warnings

Appendix D: Timing Simulation Warning and Error Messages

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Schedule of Figures

Chapter 3: Quick Start Example Design

Figure 3-1: Core Customization GUI Main Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Chapter 4: Detailed Example Design

Figure 4-1: Example Design Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 4-2: Demonstration Test Bench Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 4-3: Test Bench Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 4-4: Startup State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

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Schedule of Tables

Chapter 4: Detailed Example Design

Table 4-1: Project Directory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 4-2: Component Name Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 4-3: Doc Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 4-4: Example Design Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 4-5: Implement Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 4-6: Results Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 4-7: Simulation Directory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 4-8: Functional Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 4-9: Timing Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 4-10: Testcase Package User-Defined Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 4-11: Useful Testcase Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 4-12: Testcase Module Request Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Appendix A: VHDL Details

Table A-1: send_packet (PBr, addr, bytes) Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table A-2: send_user_data (PBr, SOP, EOP, Err, Addr, bytes) Inputs . . . . . . . . . . . . . . . . 46

Table A-3: send_idles (PBr, cycles) Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table A-4: send_training (PBr, patterns) Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table A-5: sop_spacing (PBr, Bytes1, Err1, Addr1, EOP2, Err2, Addr2,

Bytes2, num_cycles) Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table A-6: send_status (PBt, channel, value) Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table A-7: get_status (PBt, channel) Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Appendix B: Verilog Details

Table B-1: send_packet (Addr, bytes) Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table B-2: send_user_data (SOP, EOP, Err, Addr, bytes) Inputs. . . . . . . . . . . . . . . . . . . . . 50

Table B-3: send_idles (cycles) Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table B-4: send_training (patterns) Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table B-5: sop_spacing (Bytes1, Err1, Addr1, EOP2, Err2, Addr2,

Bytes2, num_cycles) Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table B-6: send_status (channel, value) Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table B-7: get_status (channel) Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

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Preface

About This Guide

This guide provides information about generating the Xilinx LogiCORE™ IP SPI-4.2 core, customizing and simulating the core using the provided example design, and running the design files through implementation using the Xilinx tools.

Contents

This guide contains the following chapters:

Preface, “About this Guide” introduces the organization and purpose of the Getting Started Guide, and the conventions used in this document.

Chapter 1, “Introduction” describes the core and related information, including recommended design experience, additional resources, technical support, and submitting feedback to Xilinx.

Chapter 2, “Licensing the Core” provides information about installing and licensing the core.

Chapter 3, “Quick Start Example Design” provides instructions to quickly generate the core and run the example design through implementation and simulation using the default settings.

Chapter 4, “Detailed Example Design” describes the files and directories created by the CORE Generator. It also contains detailed information about the demonstration test bench and directions for customizing it for use in a user application.

Appendix A, “VHDL Details” provides details about the VHDL demonstration test bench and how to customize it.

Appendix B, “Verilog Details” provides details about the Verilog demonstration test bench and how to customize it.

Appendix C, “Data and Status Monitor Warnings” describes the common demonstration test bench warnings.

Conventions

This document uses the following conventions. An example illustrates each convention.

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Preface: About This Guide

Typographical

The following typographical conventions are used in this document:

Convention

Meaning or Use

Example

 

 

 

 

Messages, prompts, and

 

Courier font

program files that the system

speed grade: - 100

 

displays

 

 

 

 

Courier bold

Literal commands that you

ngdbuild design_name

enter in a syntactical statement

 

 

 

 

 

See the Development System

 

References to other manuals

Reference Guide for more

Italic font

 

information.

 

 

 

If a wire is drawn so that it

 

 

 

Emphasis in text

overlaps the pin of a symbol,

 

 

the two nets are not connected.

 

 

 

 

An optional entry or

 

Square brackets [ ]

parameter. However, in bus

ngdbuild [option_name]

specifications, such as

design_name

 

 

bus[7:0], they are required.

 

 

 

 

Braces { }

A list of items from which you

lowpwr ={on|off}

must choose one or more

 

 

 

 

 

Vertical bar |

Separates items in a list of

lowpwr ={on|off}

choices

 

 

 

 

 

Vertical ellipsis

 

IOB #1: Name = QOUT’

 

IOB #2: Name = CLKIN’

.

Repetitive material that has

.

.

been omitted

.

.

 

 

.

 

 

 

 

 

Horizontal ellipsis . . .

Repetitive material that has

allow block block_name

 

been omitted

loc1 loc2 ... locn;

 

 

 

Online Document

The following conventions are used in this document:

Convention

Meaning or Use

Example

 

 

 

 

Cross-reference link to a

See the section “Additional

 

Resources” for details.

Blue text

location in the current

Refer to “Title Formats” in

 

document

 

Chapter 1 for details.

 

 

 

 

 

Blue, underlined text

Hyperlink to a website (URL)

Go to www.xilinx.com for the

latest speed files.

 

 

 

 

 

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Chapter 1

Introduction

The LogiCORE IP SPI-4.2 (PL4) core is a fully verified design solution that supports Verilog and VHDL. The example design in this guide is provided in both Verilog and VHDL.

This chapter introduces the SPI-4.2 core and provides related information, including recommended design experience, additional resources, technical support, and how to submit feedback to Xilinx.

System Requirements

Windows

Windows XP® Professional 32-bit/64-bit

Windows Vista® Business 32-bit/64-bit

Linux

Red Hat® Enterprise Linux WS v4.0 32-bit/64-bit

Red Hat® Enterprise Desktop v5.0 32-bit/64-bit (with Workstation Option)

SUSE Linux Enterprise (SLE) v10.1 32-bit/64-bit

Software

ISE™ 10.1 with applicable service pack

Check the release notes for the required service pack; ISE Service Packs can be downloaded from www.xilinx.com/xlnx/xil_sw_updates_home.jsp?update=sp.

About the Core

The SPI-4.2 core is a Xilinx CORE Generator™ IP core, included in the latest IP update on the Xilinx IP Center. For detailed information about the core, see the SPI-4.2 product page. For information about system requirements, installation, and licensing options, see Chapter 2, “Licensing the Core.”

Recommended Design Experience

Although the SPI-4.2 core is a fully verified solution, the challenge associated with implementing a complete design varies, depending on desired configuration and functionality. For best results, previous experience building high-performance, pipelined FPGA designs using Xilinx implementation software and user constraints files (UCF) is recommended.

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Contact your local Xilinx representative for a closer review and estimate of the effort required to meet your specific design requirements.

Additional Core Resources

For detailed information and updates about the SPI-4.2 core, see the following additional documents located on the SPI-4.2 product page.

LogiCORE SPI-4.2 Data Sheet

LogiCORE SPI-4.2 Release Notes

LogiCORE SPI-4.2 User Guide

For updates to this document, see the LogiCORE SPI-4.2 Getting Started Guide, also located on the Xilinx SPI-4.2 product page.

Technical Support

To obtain technical support specific to the SPI-4.2 core, visit http://support.xilinx.com/. Questions are routed to a team of engineers with expertise using the SPI-4.2 core.

Xilinx will provide technical support for use of this product as described in the SPI-4.2 User Guide and the SPI-4.2 Getting Started Guide. Xilinx cannot guarantee timing, functionality, or support of this product for designs outside the guidelines presented in this document.

Feedback

Xilinx welcomes comments and suggestions about the SPI-4.2 core and the documentation provided with the core.

Core

For comments or suggestions about the SPI-4.2 core, please submit a WebCase from

http://support.xilinx.com/. Be sure to include the following information:

Product name

Core version number

Explanation of your comments

Document

For comments or suggestions about this document, please submit a WebCase from

http://support.xilinx.com/. Be sure to include the following information:

Document title

Document number

Page number(s) to which your comments refer

Explanation of your comments

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Chapter 2

Licensing the Core

This chapter provides instructions for obtaining a license for the core so that you can use the core in a design. The SPI-4.2 core is provided under the terms of the Xilinx LogiCORE Site License Agreement. This license agreement conforms to the terms of the SignOnce IP License standard defined by the Common License Consortium. Purchase of the core entitles you to technical support and access to updates for a period of one year.

Before you Begin

This chapter assumes that you have installed the core using either the CORE GeneratorTM IP Update installer or by performing a manual installation after downloading the core from the web. For information about installing the core, see the SPI-4.2 product page.

Before installing the core, you must have a Xilinx.com account and the ISE 10.1 software installed on your system.

To set up an account and install the ISE software:

1.Click Sign in to Access Account at the top of the Xilinx home page; then follow the instructions to create a support account.

2.Install the ISE 10.1 software with the applicable service pack.

License Options

The SPI-4.2 core provides three licensing options, described below.

Simulation-Only Evaluation

The Simulation-Only Evaluation license is provided with the Xilinx CORE Generator system. This license lets you evaluate core functionality using a provided example design. You can also use your own design and simulate the various interfaces on the core. Functional simulation is supported by a dynamically generated gate-level netlist.

Full System Hardware Evaluation

The Full System Hardware Evaluation license is available at no cost and lets you fully integrate the core into an FPGA design, place and route the design, evaluate timing, and perform back-annotated gate-level simulation using the demonstration test bench provided.

In addition, the license lets you generate a bitstream from the placed and routed design, which can then be downloaded to a supported device and tested in hardware. The core can

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be tested in the target device for a limited time before timing out. The core can be reactivated by reconfiguring the device after a time out.

You can obtain the Full System Evaluation License in one of the following ways, depending on the core:

By registering on the Xilinx IP Evaluation page and filling out a form to request an automatically-generated evaluation license

By contacting your local Xilinx FAE to request a Full System Hardware Evaluation license key

Click Evaluate on the SPI-4.2 core product page for information about obtaining a Full System Hardware Evaluation License.

Full

The Full license is provided when you purchase the core. This option provides full access to all core functionality both in simulation and in hardware, including:

Gate-level functional simulation support

Back annotated gate-level simulation support

Full implementation support including place and route and bitstream generation

Full functionality in the programmed device with no time-outs

Obtaining Your License

Obtaining a Simulation-Only or Full System Hardware Evaluation License

To obtain a Simulation-Only or Full System Hardware Evaluation license, do the following:

Navigate to the SPI-4.2 product page.

Click Evaluate.

Select one of the following:

Simulation-Only Evaluation

Full System Hardware Evaluation

For both types of licenses, follow the onscreen instructions to both download the CORE Generator files (delivered as an IP update) and satisfy any additional requirements associated with the license type.

Obtaining a Full License

To obtain a Full license, you must purchase the core. After purchase, you will receive a letter containing a serial number. This serial number is used to register for access to the lounge, a secured area of the SPI-4.2 product page.

From the product page, click Register to request access to the lounge.

Xilinx will review your access request. Requests for access are typically granted within 48 hours. Contact Xilinx Customer Service if you need faster turnaround.

After you receive confirmation of lounge access, click Access Lounge on the SPI-4.2 product page and log in.

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Installing Your License File

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Follow the instructions in the lounge to fill out the license request form; then click Submit to automatically generate the license. An email containing the license and installation instructions will be sent to you immediately.

Installing Your License File

After selecting a license option, an email is sent to your login account that includes instructions for installing your license file. In addition, information about advanced licensing options and technical support is provided.

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