Xilinx LogiCore PLB PCI Full Bridge User Manual

Loading...

 

PLB PCI Full Bridge (v1.00a)

 

 

 

 

 

 

 

 

DS508 March 21, 2006

 

 

 

 

Product Specification

 

 

 

 

 

 

 

 

Introduction

 

 

 

 

 

 

 

 

 

LogiCORE™ Facts

 

 

The PLB PCI Full Bridge design provides full bridge

 

 

 

 

 

 

 

 

 

Core Specifics

 

 

functionality between the Xilinx 64-bit PLB and a 32-bit

 

 

 

 

 

 

 

 

Supported Device

 

 

Virtex™-II Pro, Virtex-4

Revision 2.2 compliant Peripheral Component

 

 

Family

 

 

 

 

 

 

 

 

 

 

Interconnect (PCI) bus. The bridge is referred to as the

 

 

 

 

 

 

 

 

Version of Core

 

 

plb pci

 

v1.00a

PLB PCI Bridge in this document.

 

 

 

 

 

 

 

 

 

 

 

The Xilinx PLB is a 64-bit bus subset of the IBM PLB

 

 

Resources Used

 

 

 

 

 

 

 

 

 

 

described in the 64-Bit Processor Local Bus Architecture

Virtex-IIP

 

 

 

Min

 

Max

Specification v3.5. Details on the Xilinx PLB and the PLB

 

 

 

 

 

 

 

 

I/O (PCI)

 

 

 

49

 

50

 

IPIF are found in the Processor IP Reference Guide. This

 

 

 

 

 

 

 

 

I/O (PLB-related)

 

 

397

 

433

 

guide is accessed via EDK help or the Xilinx website at:

 

 

 

 

 

 

 

 

 

 

 

 

LUTs

 

 

 

3350

 

3870

 

http://www.xilinx.com/ise/embedded/proc_ip_ref_

 

 

 

 

 

guide.pdf.

 

 

 

 

 

 

 

 

FFs

 

 

 

2570

 

2970

 

The LogiCORE PCI v3.0 core provides an interface with

 

 

 

ESS

 

 

 

Block RAMs

 

 

8

 

8

 

the PCI bus. Details of the LogiCORE PCI 32 v3.0 core

 

 

 

 

 

 

 

 

 

 

Provided with Core

 

 

 

 

 

 

 

operation is found in the Xilinx LogiCORE PCI Interface

 

C

 

 

 

 

 

Documentation

 

 

Product Specification

v3.0 Product Specification and the Xilinx The Real-PCI

 

 

 

 

 

 

 

 

 

 

Design Guide v3.0.

Design File Formats

 

VHDL

 

 

 

 

 

 

 

Host bridge functionality (often called North bridge

Constraints File

 

 

example UCF-file

functionality) is an optional functionality.

 

 

 

 

 

 

 

 

Verification

 

 

N/A

 

 

Configuration Read and Write PCI commands can beAC

 

 

N/A

 

 

performed from the PLB-side of the bridge. The PLB

Instantiation Template

 

 

 

 

 

 

 

 

 

 

 

PCI Bridge supports a 32-bit/33 MHz PCI bus only.

Reference Designs

 

None

 

 

 

 

 

 

 

 

 

Exceptions to the support of PCI commands supported

 

Design Tool Requirements

 

 

by the v3.0 core are outlined in the Features section.

 

 

 

 

 

 

Xilinx Implementation

 

8.1.1i or later

 

Tools

 

 

 

The PLB PCI Bridge design has parameters that allow

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

customers to configure the bridge to suit their

Verification

 

 

N/A

 

 

application. The parameterizableRLYfeatures of the design

 

 

 

 

 

Simulation

 

 

 

ModelSim SE/EE 5.8d or later

are discussed in the Bus Interface Parameters section.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

E

Synthesis

 

 

 

XST

 

 

 

 

 

 

 

Support

 

 

 

Support provided by Xilinx, Inc.

 

 

 

 

 

 

 

 

 

 

 

© 2005 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.

DS508 March 21, 2006

www.xilinx.com

1

Product Specification

PLB PCI Full Bridge (v1.00a)

Features

Independent PLB and PCI clocks

33 MHz, 32-bit PCI bus support

Utilizes two pairs of FIFOs to exploit the separate master and slave PLB IPIF modules.

Includes a master IP module for remote PCI initiator transactions, which follows the protocol for interfacing with the master IPIF module utilizing Xilinx LocalLink protocol. The PLB PCI Bridge translates the PCI initiator request to PLB IPIF master transactions.

Includes a slave IP module for remote PLB master transactions, which follows the protocol for interfacing with the slave IPIF module utilizingACCESSXilinx IPIC protocol. The PLB PCI Bridge translates the PLB master request to PCI initiator transactions. The SRAM-like interface is utilized at the IPIC

interface for data transfers.

The PLB IPIF slave attachment has a timer that limits the time for both read and write dataphase operations to complete. When the timer expires, Sl MErr signal is asserted. See PLB IPIF Product Specification for details.

Full bridge functionality

-PLB Master read and write of a remote PCI target (both single and burst)

-PCI Initiator read and write to a remote PLB slave (both single and multiple).

-I/O read and I/O write commands are supported only for PLB master read and writes of PCI I/O space as designated by its associated memory designator parameter. All memory space on the PLB-side is designated as memory space in the PCI sense, therefore, I/O commands cannot be used to access memory on the PLB-side.

-Configuration read and writes are supported (including self-configuration transactions) only whenEARLYupper word address lines are utilized for IDSEL lines. The Configuration Read and Write commands are automatically executed by writing to the Configuration Data Port Register. Data

in the Configuration Address Port Register and the Configuration Bus Number/Subordinate Bus Number Register are used in execution of the configuration transaction per PCI 2.2 specification.

PCI Memory Read Line (MRL) command is supported in which the v3.0 core is a target. MRL is aliased to a Memory Read command which has a single data phase on the PCI.

PCI Memory Write Invalidate (MWI) command is supported in which the v3.0 core is a target. The v3.0 core does not support this command when it is an initiator. MWI is aliased to a Memory Write command which has a single data phase on the PCI.

Supports up to 6 PLB devices, in the sense defined by independent parameters and unique PLB memory space for each device

-Each device has the following parameters: PLB BAR, high (upper) address, memory designator, and translation for mapping PLB address space to PCI address space. Byte addressing integrity is maintained by default in all transfers. Address translation is performed by high-order bit substitution. High-order bit definition can be done with parameters or dynamically via registers.

Supports up to 3 PCI devices (or BARs in PCI context) with unique memory PCI memory space. The v3.0 core supports up to 3 PCI BAR.

-Each device has the following parameters: PCI BAR, length, memory designator, and translation for mapping PCI address space to PLB address space. Byte addressing integrity is maintained by

2

www.xilinx.com

DS508 March 21, 2006

 

 

Product Specification

PLB PCI Full Bridge (v1.00a)

default in all transfers. Address translation is performed by high-order bit substitution. High-order bit definition is defined only by parameters

Registers include

-Interrupt and interrupt enable registers at different hierarchal levels

-Reset

-Configuration Address Port, Configuration Data Port and Bus Number/Subordinate Bus Number

-High-order bits for PLB to PCI address translation

-Bridge Device number on PCI bus

PLB-side Interrupts include

-PLB Master Read SERR and PERR ACCESS

-PLB Master Read Target Abort

-PLB Master Write SERR and PERR

-PLB Master Write Target Abort

-PLB Master Write Master Abort

-PLB Master Burst Write Retry and Retry Disconnect

-PLB Master Burst Write Retry Timeout

-PCI Initiator Read and Write SERR

Asynchronous FIFOs with backup capability

Synchronization circuits for signals that cross time-domain boundaries

Responds to the PCI latency timer

Completes posted write operations prior to initiating new operations

Signal set required for integratingYa PCI bus arbiter in the FPGA with the PLB PCI bridge is available at the top-level of the PLB PCI bridge module. The signal set includes PCLK, RST_N, FRAME_I, REQ_N_toArb andLIRDY I

Supports PCI clock generated in FPGA

ParameterizedARcontrol of IO-buffer insertion of INTR_A and REQ_N IO-buffers

All address translations performed by high-order bit substitution. The number of bits substituted depends on the address range

-Parameterized selection of IPIF BAR high-order bits defined by programmable registers for dynamicEtranslation operation or by parameters for reduced resource utilization

Parameterized selection of device ID number (when configuration functionality is included) defined by a programmable register for dynamic device number definition or by parameter to reduce resource utilization

The PLB PCI bridge does not have an integral DMA

Input signal to provide the means to asynchronous asset INTR_A from a user supplied register (i.e., a PLB GPIO). The signal is Bus2PCI_INTR is an active high signal

PCI Monitor output port to monitor PCI bus activity

DS508 March 21, 2006

www.xilinx.com

3

Product Specification

PLB PCI Full Bridge (v1.00a)

System Reset

When the bridge is reset, both RST_N and PLB_reset must be simultaneously held at reset for at least twenty clock periods of the slowest clock.

Evaluation Version

The PLB PCI Bridge is delivered with a hardware evaluation license. When programmed into a Xilinx device, the core will function in hardware for about 8 hours at the typical frequency of operation. To use the PLB PCI Bridge without this timeout limitation, a full license must be purchased.

Functional Description

The PLB PCI Bridge design is shown in Figure 1 and described in the following sections. As shown, PLB IPIF PCI Bridge is comprised of three main modules:

• The PLB IPIF (Processor Local Bus Intellectual Property InterFace). It interfaces to the PLB bus.

• The IPIF v3.0 Bridge. It interfaces between the PLB IPIF and the v3.0 core.

• The LogiCORE PCI32 Interface v3.0 core. It interfaces to the PCI bus.

 

 

 

 

 

 

 

PLB IPIF

 

 

 

 

 

 

 

 

 

 

 

IPIF/V3 Bridge

 

 

 

 

 

 

 

 

Xilinx

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

v3.0 PCI Core

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Interrupt

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bridge

 

 

 

 

 

 

 

 

 

 

 

 

 

Bus

 

 

Module

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Registers

 

 

 

 

 

 

 

 

 

 

 

Bus

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PLB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ator

 

 

 

 

 

 

PCI

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI2IPIF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FIFO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Slave

 

 

 

 

 

 

 

 

 

 

 

 

aveMS

ACCESS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Attachment

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IPIF2PCI

Initi

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Sl

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FIFO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI2IPIF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Master

 

 

FIFO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Attachment

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IPIF2PCI

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FIFO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

rgetTa

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Master SM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EARLY

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ds508_01_112205

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 1: PLB PCI Full Bridge Block Diagram

LogiCore Version 3.0 32-bit PCI Core Requirements

The PLB PCI bridge uses the 32-bit Xilinx LogiCore Version 3 IP core. Before the bridge can perform transactions on the PCI bus, the v3.0 core must be configured via configuration transactions from either the PCI-side or if configuration functionality is included in the bridge configuration, from the PLB-side. Both a design guide and an implementation guide are available for the Xilinx LogiCore v3.0 PCI IP

4

www.xilinx.com

DS508 March 21, 2006

 

 

Product Specification

PLB PCI Full Bridge (v1.00a)

core. These documents detail the v3.0 core operation, including configuration cycles, and are available from Xilinx.

As required by the LogiCORE v3.0 core, GNT_N must be asserted for two clock cycles to initiate a PCI transaction by the PLB PCI Bridge.

Bus Interface Parameters

Because many features in the IPIF v3.0 Bridge design can be parameterized, the user can realize a PLB PCI Full Bridge uniquely tailored while using only the resources required for the desired functionality. This approach also achieves the best possible performance with the lowest resource usage. Table 1 shown the features that can be parameterized in the PLB PCI Bridge design.

Address Translation

High-order address bits are substituted for theACCESSaddress vector before crossing to the other bus domain. The number of high-order bits substituted in the PLB address presented to the bridge is

given by the number of bits that are the same between the C IPIFBAR N and C IPIF_HIGHADDR_N parameters. The number of high-order bits substituted in the PCI address presented to the bridge for a translation from PCI to PLB domains is given by the bus width minus the parameter C_PCIBAR_LEN_N.Y

The low-order bits are transferred directly between bus domains. The bits substituted in a translation from PLB to PCILdomains can be selected via a parameter (C_INCLUDE_BAROFFSET REG) as either a parameter (C_IPIFBAR2PCIBAR_N) or a

programmable register for each BAR. The bits that are substituted for in a translation from PCI to PLB domainsARis defined by a parameter (C_PCIBAR2IPIFBAR_M) for each BAR. setsandPCImaximumorcontiguousE

Example 1, shown in Figure 2, outlines the use of the two sets of BAR parameters.

Example 2 outlines the use of the IPIFBAR parameters sets for the specific address translations of PLB addresses within the range of a given IPIFBAR to a remote PCI address space.

DS508 March 21, 2006

www.xilinx.com

5

Product Specification

Xilinx LogiCore PLB PCI Full Bridge User Manual

PLB PCI Full Bridge (v1.00a)

Example 3 outlines the use of the PCIBAR parameter sets for the address translation of PCI addresses within the range of a given PCIBAR to a remote PLB address space.

BAR_10

BAR_11

PLB Bus

 

PLB PCI Full Bridge

 

IPIF

 

C_IPIFBAR_NUM = 3

 

 

IPIFBAR_0 IPIFBAR_1

 

ACCESS

 

IPIFBAR 2

IPIFBAR 3

IPIFBAR 4

IPIFBAR 5

Note 1

(high-order

(high-order

(high-order

IPIF to v3.0 LogiCORE Bridge

 

bit sub)

bit sub)

 

bit sub)

 

 

 

 

Addr to PCI

Addr to PCI

Addr to PCI

 

 

 

 

 

 

 

 

Addr to PLB

Addr to PLB

 

 

 

 

 

 

(high-order

(high-order

Note 2

 

 

 

 

 

 

 

 

 

 

 

bit sub)

bit sub)

 

 

v3.0 LogiCORE

 

 

PCIBAR 0

PCIBAR 1

PCIBAR 2

 

C_PCIBAR_NUM = 2

 

 

 

 

 

 

 

 

EARLY

 

 

 

 

PCI Bus

 

 

 

 

 

 

 

 

PBAR 20 PBAR 21 PBAR_22

 

ds508_02_112205

Figure 2: Translation of Addresses Bus-to-Bus with High-Order Bit Substitution

Example 1

Because address translations are performed only when the PLB PCI Bridge is configured with FIFOs, the example shown in Figure 2 is for an PLB PCI Bridge configuration with FIFOs only. In this example, it is assumed that C INCLUDE BAROFFSET REG=0, therefore, the parameters C_IPIFBAR2PCIBAR_N define the high-order bits for substitution in translating the address on the PLB bus to the PCI bus.

The PLB parameters are C IPIFBAR N, C IPIF_HIGHADDR_N, and C_IPIFBAR2PCIBAR_N for N=0 to 5.

The PCI parameters are C_PCIBAR_LEN_M and C_PCIBAR2IPIFBAR_M for M=0 to 2.

Example 2

Example 2 shows of the settings of the two independent sets of base address register (BAR) parameters for specifics of address translation of PLB addresses within the range of a given IPIFBAR to a remote PCI address space. Note that this setting does not depend on the PCIBARs of the PLB PCI Bridge.

6

www.xilinx.com

DS508 March 21, 2006

Product Specification

PLB PCI Full Bridge (v1.00a)

As in example 1, it is assumed that the parameter C_INCLUDE_BAROFFSET_REG=0, therefore the C_IPIFBAR2PCIBAR_N parameters define the address translation.

In this example, where C_IPIFBAR_NUM=4, the following assignments for each range are made:

C_IPIFBAR_0=0x12340000

C_IPIF_HIGHADDR_0=0x1234FFFF

C_IPIFBAR2PCIBAR_0=0x5671XXXX (Bits 16-31 are don’t cares)

C_IPIFBAR_1=0xABCDE000

C_IPIF_HIGHADDR_1=0xABCDFFFF

C_IPIFBAR2PCIBAR_1=0xFEDC0xXX (Bits 19-31 are don’t cares)

C_IPIFBAR_2=0xFE000000

C_IPIF_HIGHADDR_2=0xFFFFFFFF

C_IPIFBAR2PCIBAR_2=0x40xXXXXX (Bits 7-31 are don’t cares)

C_IPIFBAR_3=0x00000000

C_IPIF_HIGHADDR_3=0x0000007F

C_IPIFBAR2PCIBAR_3=8765438X (Bits 25-31 are don’t cares)

Accessing the PLB PCI Bridge IPIFBAR_0 with address 0x12340ABC on the PLB bus yields 0x56710ABC on the PCI bus.

Accessing the PLB PCI Bridge IPIFBAR_1 with address 0xABCDF123 on the PLB bus yields 0xFEDC1123 on the PCI bus.

Accessing the PLB PCI Bridge IPIFBAR_2 with address 0xFFFEDCBA on the PLB bus yields 0x41FEDCBA on the PCI bus.

Accessing the PLB PCI Bridge IPIFBAR_3 with address 0x00000071 on the PLB bus yields Ox876543F1 on the PCI bus.

Example 3

Example 3 outlines address translation of PCI addresses within the range of a given PCIBAR to PLB

 

 

 

ACCESS

address space. Note that this translation is independent of the PLB PCI Bridge IPIF BARs.

The parameters C_PCIBAR2IPIFBAR M parameters define the address translation for all

C_PCIBAR_NUM.

 

Y

 

 

 

 

In this example, where C PCIBAR NUM=2, the following range assignments are made:

 

L

 

AR

 

 

BAR 0 is set to 0xABCDE800 by host

C_PCIBAR_LEN 0=11

C_PCIBAR2IPIFBAR 0=0x123450XX (Bits 21-31 are don’t cares)

BAR 1Eis set to 0x12000000 by host

C_PCIBAR LEN 1=25

C_PCIBAR2IPIFBAR_1=0xFEXXXXXX (Bits 7-31 are don’t cares)

Accessing the PLB PCI Bridge PCIBAR_0 with address 0xABCDEFF4 on the PCI bus yields 0x123457F4 on the PLB bus.

DS508 March 21, 2006

www.xilinx.com

7

Product Specification

PLB PCI Full Bridge (v1.00a)

Accessing the PLB PCI Bridge PCIBAR_1 with address 0x1235FEDC on the PCI bus yields 0xFE35FEDC on the PLB bus.

Table 1: PLB PCI Bridge Interface Design Parameters

Generic

Feature /

Parameter

 

Allowable Values

Default

VHDL

Description

Name

 

Value

Type

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bridge Features Parameter Group

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1-6; Parameters listed

 

 

 

 

 

 

 

below corresponding to

 

 

 

 

 

 

 

unused BARs are

 

std_logic_

 

 

 

 

 

ACCESS

 

 

 

C_IPIFBAR

 

ignored, but must be

 

 

G1

 

Number of IPIF devices

_NUM

 

valid values. BAR label

6

integer

 

 

 

 

 

0 is the required bar for

 

 

 

 

 

 

 

all values 1-6 and the

 

 

 

 

 

 

 

index increments from 0

 

 

 

 

 

 

 

as BARs are added

 

 

G2

 

IPIF device 0 BAR

C_IPIFBAR_0

 

Valid PLB address (1)

0xFFFFFFFF

std_logic_

 

 

 

 

 

 

 

vector

G3

 

IPIF BAR high address

C_IPIFBAR_

 

Valid PLB address (1)

0x00000000

std_logic_

 

 

0

HIGHADDR_0

 

 

vector

 

 

PCI BAR to which IPIF

 

 

 

 

 

 

 

BAR 0 is mapped

C_IPIFBAR2

 

Vector of length

 

std_logic_

G4

 

unless

 

0xFFFFFFFF

 

 

C_INCLUDE_BAROFF

PCIBAR_0 1

 

C PLB AWIDTH

 

vector

 

 

 

 

 

 

 

 

 

SET_REG = 1

 

 

 

 

 

 

 

 

 

 

 

 

G5

 

IPIF BAR 0 memory

C_IPIF_SPACE

0 = I/O space

1

integer

 

designator

TYPE 0

 

1 = Memory space

 

 

 

 

 

 

 

 

 

 

 

 

 

G6

 

EARLY

 

Valid PLB address (1)

0xFFFFFFFF

 

 

IPIF device 1 BAR

C IPIFBAR_1

 

vector

G7

 

IPIF BAR high address

C IPIFBAR_

 

Valid PLB address (1)

0x00000000

std_logic_

 

 

1

HIGHADDR_1

 

 

vector

 

 

PCI BAR to which IPIF

 

 

 

 

 

 

 

BAR 1 is mapped

C IPIFBAR2

 

Vector of length

 

std_logic_

G8

 

unless

 

0xFFFFFFFF

 

 

C INCLUDE BAROFF

PCIBAR 1

 

C_PLB_AWIDTH

 

vector

 

 

SET REG = 1

 

 

 

 

 

 

 

 

 

 

 

 

G9

 

IPIF BAR 1 memory

C IPIF SPACE

0 = I/O space

1

integer

 

designator

TYPE 1

 

1 = Memory space

 

 

 

 

 

 

 

 

 

 

 

 

 

G10

 

IPIF device 2 BAR

C IPIFBAR_2

 

Valid PLB address (1)

0xFFFFFFFF

std_logic_

 

 

 

 

 

 

 

vector

 

 

 

 

 

 

 

 

G11

 

IPIF BAR high address

C IPIFBAR_

 

Valid PLB address (1)

0x00000000

std_logic_

 

 

2

HIGHADDR_2

 

 

vector

 

 

 

 

 

 

 

 

 

 

PCI BAR to which IPIF

 

 

 

 

 

 

 

BAR 2 is mapped

 

 

 

 

 

G12

 

unless

C_IPIFBAR2

 

Vector of length

0xFFFFFFFF

std_logic_

 

 

C_INCLUDE_BAROFF

PCIBAR_2

 

C_PLB_AWIDTH

 

vector

 

 

SET_

 

 

 

 

 

 

 

REG = 1

 

 

 

 

 

 

 

 

 

 

 

 

 

8

www.xilinx.com

DS508 March 21, 2006

 

 

Product Specification

PLB PCI Full Bridge (v1.00a)

Table 1: PLB PCI Bridge Interface Design Parameters (Contd)

Generic

Feature /

Parameter

Allowable Values

Default

 

VHDL

Description

Name

 

Value

 

Type

 

 

 

 

 

 

 

 

 

 

 

G13

IPIF BAR 2 memory

C_IPIF_SPACE

0 = I/O space

1

 

integer

designator

TYPE_2

 

1 = Memory space

 

 

 

 

 

 

 

 

 

 

 

 

G14

IPIF device 3 BAR

C_IPIFBAR_3

Valid PLB address (1), (2)

0xFFFFFFFF

std_logic_

 

 

 

 

 

 

 

vector

 

 

 

 

 

 

 

G15

IPIF BAR high

C_IPIFBAR_

 

Valid PLB address (1), (2)

0x00000000

std_logic_

 

address 3

HIGHADDR_3

 

 

 

vector

 

 

 

 

 

 

 

 

 

PCI BAR to which IPIF

 

 

 

 

 

 

 

BAR 3 is mapped

C_IPIFBAR2

 

Vector of length

 

std_logic_

G16

unless

 

0xFFFFFFFF

 

C_INCLUDE_BAROFF

PCIBAR_3

 

C_PLB_AWIDTH

 

 

vector

 

 

 

ACCESS

 

 

 

SET_REG = 1.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

G17

IPIF BAR 3 memory

C_IPIF_SPACE

0 = I/O space

1

 

integer

designator

TYPE_3

 

1 = Memory space

 

 

 

 

 

 

 

 

 

 

 

 

G18

IPIF device 4 BAR

C_IPIFBAR_4

Valid PLB address (1), (2)

0xFFFFFFFF

std_logic_

 

 

 

 

 

 

 

vector

 

 

 

 

 

 

 

G19

IPIF BAR high

C_IPIFBAR_

 

Valid PLB address (1), (2)

0x00000000

std_logic_

 

address 4

HIGHADDR_4

 

 

 

vector

 

 

 

 

 

 

 

 

 

PCI BAR to which IPIF

 

 

 

 

 

 

 

BAR 4 is mapped

C_IPIFBAR2

 

Vector of length

 

std_logic_

G20

unless

 

0xFFFFFFFF

 

C_INCLUDE_BAROFF

PCIBAR_4

 

C PLB AWIDTH

 

 

vector

 

 

 

 

 

 

 

 

SET_REG = 1

 

 

 

 

 

 

 

 

 

 

 

 

 

G21

IPIF BAR 4 memory

C_IPIF_SPACE

0 = I/O space

1

 

integer

designator

TYPE_4

 

1 = Memory space

 

 

 

 

 

 

 

 

 

 

 

 

G22

IPIF device 5 BAR

C IPIFBAR_5

Valid PLB address (1), (2)

0xFFFFFFFF

std_logic_

 

 

Y

 

 

 

 

vector

 

 

 

 

 

 

 

 

 

 

 

 

 

 

G23

IPIF BAR high

C IPIFBAR_

 

Valid PLB address (1), (2)

0x00000000

std_logic_

 

address 5

HIGHADDR_5

 

 

 

vector

 

 

 

 

 

 

 

 

 

PCI BAR to which IPIF

 

 

 

 

 

 

 

AR

 

 

 

 

 

 

 

BAR 5 is mapped

 

 

 

 

 

 

G24

unless

C IPIFBAR2

 

Vector of length

0xFFFFFFFF

std_logic_

 

C_INCLUDE BAROFFLPCIBAR_5

 

C_PLB_AWIDTH

 

 

vector

 

SET

 

 

 

 

 

 

 

REG = 1

 

 

 

 

 

 

 

IPIF BAR 5 memory

C_IPIF_SPACE

0 = I/O space

1

 

integer

E

 

 

 

 

G25

designator

TYPE_5

 

1 = Memory space

 

 

 

 

 

1-3; Parameters listed

 

 

 

 

 

 

 

below corresponding to

 

 

 

 

 

 

 

unused BARs are

 

 

 

 

 

C_PCIBAR_

 

ignored, but must be

 

 

 

G26

Number of PCI devices

 

valid values. BAR label

3

 

integer

NUM

 

 

 

 

 

0 is the required bar for

 

 

 

 

 

 

 

 

 

 

 

 

 

 

all values 1-3 and the

 

 

 

 

 

 

 

index increments from 0

 

 

 

 

 

 

 

as BARs are added

 

 

 

 

 

 

 

 

 

 

 

DS508 March 21, 2006

www.xilinx.com

9

Product Specification

PLB PCI Full Bridge (v1.00a)

Table 1: PLB PCI Bridge Interface Design Parameters (Contd)

Generic

Feature /

Parameter

 

Allowable Values

Default

VHDL

Description

Name

 

Value

Type

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IPIF BAR to which PCI

C_PCIBAR2

 

Vector of length

 

std_logic_

G27

 

BAR 0

 

0x00000000

 

 

is mapped

IPIFBAR_0

 

C_PLB_AWIDTH

 

vector

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Power of 2 in the size in

C_PCIBAR_

 

 

 

 

G28

 

bytes of PCI BAR 0

 

5 to 29

16

integer

 

LEN_0

 

 

 

space

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ACCESS

 

G29

 

IPIF BAR to which PCI

C_PCIBAR2IPI

Vector of length

0x00000000

std_logic_

 

 

BAR 1 is mapped

FBAR_1

 

C PLB AWIDTH

 

vector

 

 

Power of 2 in the size in

C_PCIBAR_

 

 

 

 

G30

 

bytes of PCI BAR 1

LEN_1

 

5 to 29

16

integer

 

 

space

 

 

 

 

 

G31

 

IPIF BAR to which PCI

C_PCIBAR2

 

Vector of length

0x00000000

std_logic_

 

 

BAR 2 is mapped

IPIFBAR_2

 

C PLB AWIDTH

 

vector

 

 

Power of 2 in the size in

C_PCIBAR_

 

 

 

 

G32

 

bytes of PCI BAR 2

LEN_2

 

5 to 29

16

integer

 

 

space

 

 

 

 

 

 

 

 

 

 

 

G33

 

PCI address bus width

C_PCI_ABUS_

32

32

integer

 

WIDTH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

G34

 

PCI data bus width

C_PCI_DBUS_

32

32

integer

 

WIDTH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Both PCI2IPIF FIFO

 

 

 

 

 

 

 

address bus widths.

C PCI2IPIF_

 

 

 

 

G35

 

EARLY

 

4-14

9

integer

 

Usable depth is

FIFO ABUS_

 

 

 

2^C PCI2IPIF FIFO A

WIDTH

 

 

 

 

 

 

BUS WIDTH - 3

 

 

 

 

 

 

 

Both IPIF2PCI FIFO

 

 

 

 

 

 

 

address bus widths.

C IPIF2PCI_

 

 

 

 

G36

 

Usable depth is

FIFO ABUS_

 

4-14

9

integer

 

 

2^C IPIF2PCI FIFO A

WIDTH

 

 

 

 

 

 

BUS WIDTH - 3

 

 

 

 

 

 

 

Include explicit

 

 

 

 

 

G37

 

instantiation of INTR A

C INCLUDE_

 

0 = not included

1

integer

 

io-buffer (must be 1 to

INTR A BUF

 

1 = included

 

 

 

 

 

 

 

include io-buffer)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Include explicit

 

 

 

 

 

G38

 

instantiation of REQ N

C INCLUDE_

 

0 = not included

1

integer

 

io-buffer (must be 1 to

REQ N BUF

 

1 = included

 

 

 

 

 

 

 

include io-buffer)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Minimum PCI2IPIF

 

 

5 to the lesser of 24 or

 

 

 

 

FIFO occupancy level

C_TRIG_PCI_

the PCI2IPIF FIFO

 

 

 

 

that triggers the bridge

DEPTH-3. PCI2IPIF

 

 

G39

 

READ_OCC_

 

32

integer

 

to initiate a prefetch PCI

 

FIFO DEPTH given by

 

 

LEVEL

 

 

 

 

 

read of a remote PCI

 

2^C_PCI2IPIF_FIFO_

 

 

 

 

 

 

 

 

 

 

agent

 

 

ABUS_WIDTH

 

 

 

 

 

 

 

 

 

 

10

www.xilinx.com

DS508 March 21, 2006

 

 

Product Specification

PLB PCI Full Bridge (v1.00a)

Table 1: PLB PCI Bridge Interface Design Parameters (Contd)

Generic

Feature /

 

Parameter

Allowable Values

Default

 

VHDL

Description

 

Name

 

Value

 

Type

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI2IPIF FIFO

 

 

 

2 to the lesser of 24 or

 

 

 

 

occupancy level in

 

 

 

 

 

 

 

 

 

 

the PCI2IPIF FIFO

 

 

 

 

double words that

 

C_TRIG_IPIF_

 

 

 

 

 

DEPTH-3. PCI2IPIF

 

 

 

G40

triggers the bridge to

WRBURST_

 

8

 

integer

 

FIFO DEPTH given by

 

 

initiate an IPIF burst

 

OCC_LEVEL

 

 

 

 

 

 

 

2^C_PCI2IPIF_FIFO_A

 

 

 

 

write to remote PLB

 

 

 

 

 

 

 

 

 

 

BUS_WIDTH

 

 

 

 

device

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IPIF2PCI FIFO

 

 

 

 

 

 

 

 

occupancy level that

 

 

 

2 to the lesser of 24 or

 

 

 

 

starts data transfer

 

 

 

 

 

 

 

 

 

 

the IPIF2PCI FIFO

 

 

 

 

(Both as initiator and

C_TRIG_PCI_

 

 

 

 

ACCESS

 

 

G41

target on PCI) to PCI

DATA_XFER_

DEPTH-3. IPIF2PCI

8

 

integer

FIFO DEPH given by

 

 

agent with multiple data

OCC_LEVEL

 

 

 

 

 

 

2^C IPIF2PCI FIFO

 

 

 

 

phases per transfer

 

 

 

 

 

 

 

 

 

 

ABUS WIDTH

 

 

 

 

(must meet 16 PCI

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

period maximum).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Minimum IPIF2PCI

 

 

 

2 to the lesser of 24 or

 

 

 

 

FIFO occupancy level

C_TRIG_IPIF

the IPIF2PCI FIFO

 

 

 

 

that triggers bridge to

DEPTH-3. IPIF2PCI

 

 

 

G42

READ_OCC_

16

 

integer

initiate a prefetch IPIF

FIFO DEPH given by

 

 

LEVEL

 

 

 

 

 

read of a remote PLB

 

2^C IPIF2PCI FIFO

 

 

 

 

 

 

 

 

 

 

slave

 

 

 

ABUS WIDTH

 

 

 

 

 

 

 

 

 

 

 

 

Number of PCI retry

 

C_NUM_PCI R

 

 

 

 

G43

attempts in IPIF

 

ETRIES_IN_

 

Any integer

3

 

integer

 

posted-write operations

WRITES

 

 

 

 

 

 

 

 

 

 

 

 

 

Number of PCI clock

C_NUM_PCI P

 

 

 

 

G44

periods between retries

RDS_BETWN

Any integer

6

 

integer

in postedwrite

 

RETRIES_IN

 

 

 

 

 

 

 

 

 

 

operations

 

Y

 

 

 

 

 

 

 

WRITES

 

 

 

 

 

 

Number of IPIF retry

 

 

 

 

 

 

 

 

L

 

 

 

 

 

 

attempts in

 

C NUM IPIF_

 

 

 

 

G45

posted-write PCI

 

RETRIES_IN_

Any integer

6

 

integer

 

initiator operations

 

WRITES

 

 

 

 

 

 

 

 

 

 

 

 

 

G46

Device base address

C BASE

 

Valid PLB address (1), (2)

0xFFFFFFFF

std_logic_

 

 

 

ADDR

 

 

 

 

vector

 

 

 

 

 

 

G47

Device absolute high

C_HIGHADDR

Valid PLB address (1), (2)

0x00000000

std_logic_

 

address

 

 

 

 

 

 

vector

 

 

 

 

 

 

 

 

 

E

 

 

 

 

 

 

 

 

Include the registers for

C_INCLUDE_

 

 

 

 

G48

high-order bits to be

 

BAROFFSET_

1 = include

0

 

integer

 

substituted in

 

REG

 

0 = exclude

 

 

 

 

translationAR

 

 

 

 

 

 

 

 

 

 

 

 

 

Include the register for

 

 

 

 

 

 

 

local bridge device

 

 

 

 

 

 

 

 

number when

 

C_INCLUDE_D

1 = include

 

 

 

G49

configuration

 

0

 

integer

 

EVNUM_REG

0 = exclude

 

 

functionality

 

 

 

 

 

 

 

 

 

 

 

 

 

(C_INCLUDE_PCI_CO

 

 

 

 

 

 

 

NFIG =1) is included

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DS508 March 21, 2006

www.xilinx.com

11

Product Specification

PLB PCI Full Bridge (v1.00a)

Table 1: PLB PCI Bridge Interface Design Parameters (Contd)

Generic

Feature /

Parameter

 

Allowable Values

Default

VHDL

Description

Name

 

Value

Type

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Number of IDELAY

C_NUM_

 

2-6

 

 

G50

 

controllers instantiated.

 

2

integer

 

IDELAYCTRL

 

(Virtex-4 only)

 

 

Ignored it not Virtex-4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Includes IDELAY

 

 

1=Include IDELAY

 

 

 

 

 

 

primitive

 

 

G51

 

primitive on GNT_N.

C_INCLUDE_

 

0

integer

 

 

 

 

Set by tcl-scripts and

GNT_DELAY

 

(Virtex-4 only)

 

 

 

 

 

 

 

ignored if not Virtex-4.

 

 

ACCESS

 

 

 

ID

 

 

 

 

 

 

 

 

0=No IDELAY primitive

 

 

 

 

Provides a means for

 

 

 

 

 

 

 

BSB to pass LOC

 

 

 

 

 

 

 

coordinates for

 

 

 

 

 

 

 

IDELAYCTRLs for a

 

 

See Device

 

 

 

 

given board to

C_IDELAY

 

Implementation section,

 

 

G52

 

EDK and is optional for

CTRL_LOC

 

subsection Virtex-4

NOT SET

string

 

 

user to set LOC

 

 

Support for allowed

 

 

 

 

constraints. This

 

 

values

 

 

 

 

parameter has no

 

 

 

 

 

 

 

impact on bridge

 

 

 

 

 

 

 

functionality.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

v3.0 Core Parameters Group

 

 

 

 

 

 

 

 

 

 

 

 

PCI Configuration

 

 

 

 

std_logic_

G53

 

Space Header Device

C_DEVICE_ID

16-bit vector

0x0000

 

vector

 

 

ID

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

G59

 

PCI Configuration

 

 

8-bit vector

0x0F

std_logic_

 

EARLYSpace Header C MAX LAT

 

G54

 

Space Header Vendor

C VENDOR_

 

16-bit vector

0x0000

 

 

 

ID

 

 

 

vector

 

 

PCI Configuration

C CLASS

 

 

 

std_logic_

G55

 

Space Header Class

CODE

 

24-bit vector

0x000000

vector

 

 

Code

 

 

 

 

 

G56

 

PCI Configuration

C REV ID

 

8-bit vector

0x00

std_logic_

 

 

Space Header Rev ID

 

 

 

 

vector

 

 

PCI Configuration

C SUB

 

 

 

std_logic_

G57

 

Space Header

 

16-bit vector

0x0000

 

SYSTEM ID

 

vector

 

 

Subsystem ID

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI Configuration

C SUBSYSTE

 

 

std_logic_

G58

 

Space Header

M VENDOR_

 

16-bit vector

0x0000

 

 

vector

 

 

Subsystem Vendor ID

ID

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI Configuration

 

 

 

 

std_logic_

 

 

 

 

 

 

 

 

 

Maximum Latency

 

 

 

 

vector

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI Configuration

 

 

 

 

std_logic_

G60

 

Space Header

C_MIN_GNT

 

8-bit vector

0x04

 

 

vector

 

 

Minimum Grant

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Configuration

 

 

 

 

 

 

 

 

 

 

12

www.xilinx.com

DS508 March 21, 2006

 

 

Product Specification

PLB PCI Full Bridge (v1.00a)

Table 1: PLB PCI Bridge Interface Design Parameters (Contd)

Generic

Feature /

Parameter

Allowable Values

Default

VHDL

Description

Name

Value

Type

 

 

 

 

 

 

 

 

 

Include configuration

C_INCLUDE_

0 = Not included

 

 

G61

functionality via IPIF

1

integer

PCI_CONFIG

1 = Included

 

transactions

 

 

 

 

 

 

 

 

 

 

 

 

 

G62

Number of IDSEL

C_NUM_

1 to 16

8

integer

signals supported

IDSEL

 

 

 

 

 

 

 

 

 

 

 

 

 

31 down to 16

 

 

 

PCI address bit that PCI

C_BRIDGE_

Must be <= 15 +

 

 

G63

v3.0 core IDSEL is

IDSEL_ADDR_

C_NUM_IDSEL.

16

integer

 

connected to

BIT

AD(31 down to 0) index

 

 

 

 

 

labeling

 

 

 

 

 

 

 

 

2. The minimum address range specified by C BASEADDRACCESSand C HIGHADDR must be at least 0x1FF.

 

 

IPIF Parameters Group

 

 

 

PLB master ID bus

C_PLB_MID_

log2(C PLB NUM MA

 

 

G64

width (set automatically

3

integer

 

by XPS)

WIDTH

STERS)

 

 

 

Number of masters on

C_PLB_NUM

 

 

 

G65

PLB bus (set

MASTERS

1-16

8

integer

 

automatically by XPS)

 

 

 

 

G66

PLB Address width

C_PLB_

32 (only allowed value

32

integer

 

 

AWIDTH

 

 

 

G67

PLB Data width

C_PLB_

64 (only allowed value

64

integer

DWIDTH

 

 

 

 

 

 

 

 

 

 

 

G68

Specifies the target

C_FAMILY

See PLB IPIF data

virtex2

string

technology

sheet

 

 

 

 

 

 

 

 

 

 

Notes:

1. The range specified must comprise a complete, contiguous power of two range, such that the range = 2n and

 

Y

the n least significant bits of the Base Address are zero.

C_BASEADDR must be a multiple of the range, where the range is C_HIGHADDR - C_BASEADDR + 1.

L

AR

 

E

 

DS508 March 21, 2006

www.xilinx.com

13

Product Specification

PLB PCI Full Bridge (v1.00a)

PLB PCI Bus Interface I/O Signals

The I/O signals for the PLB PCI Bridge are listed in Table 2. The interfaces referenced in this table are shown in Figure 1 in the PLB PCI Bridge block diagram.

Table 2:

PLB PCI Bridge I/O Signals

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Port

 

Signal Name

Interface

 

I/O

Description

 

 

 

 

 

 

 

 

 

 

 

 

System Signals

 

 

 

 

 

 

 

 

 

 

P1

 

IP2INTC_Irpt

Internal

 

O

Interrupt from IP to the Interrupt Controller

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ACCESS

 

 

 

 

 

PLB Signals

 

P2

 

PLB_Clk

PLB Bus

 

I

 

PLB main bus clock. See table note 1.

 

P3

 

PLB_Rst

PLB Bus

 

I

 

PLB main bus reset. See table note 1.

 

P4

 

PLB_ABus(0:C_PLB_

PLB Bus

 

I

 

Note 1 applies from P4 to P53.

 

 

 

AWIDTH-1)

 

 

 

 

 

 

 

P5

 

PLB_PAValid

PLB Bus

 

I

 

 

 

 

P6

 

PLB_masterID(0:C_PLB

PLB Bus

 

I

 

 

 

 

 

 

_MID_WIDTH-1)

 

 

 

 

 

 

 

P7

 

PLB_abort

PLB Bus

 

I

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P8

 

PLB_RNW

PLB Bus

 

I

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P9

 

PLB_BE(0:[C_PLB_DWI

PLB Bus

 

I

 

 

 

 

 

DTH/8]-1)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P10

 

PLB_MSize(0:1)

PLB Bus

 

I

 

 

 

 

 

 

 

 

 

 

 

 

 

P21

 

SlEARLYwrComp PLB Bus

 

O

 

 

 

P11

 

PLB size(0:3)

PLB Bus

 

I

 

 

 

 

P12

 

PLB type(0:2)

PLB Bus

 

I

 

 

 

 

P13

 

PLB wrDBus(0:C PLB

PLB Bus

 

I

 

 

 

 

 

 

DWIDTH-1)

 

 

 

 

 

 

 

P14

 

PLB wrBurst

PLB Bus

 

I

 

 

 

 

P15

 

PLB rdBurst

PLB Bus

 

I

 

 

 

 

P16

 

Sl addAck

PLB Bus

 

O

 

 

 

P17

 

Sl SSize(0:1)

PLB Bus

 

O

 

 

 

 

 

 

 

 

 

 

 

 

P18

 

Sl wait

PLB Bus

 

O

 

 

 

 

 

 

 

 

 

 

 

 

P19

 

Sl rearbitrate

PLB Bus

 

O

 

 

 

 

 

 

 

 

 

 

 

 

P20

 

Sl wrDAck

PLB Bus

 

O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P22

 

Sl_wrBTerm

PLB Bus

 

O

 

 

 

 

 

 

 

 

 

 

 

 

 

P23

 

Sl_rdDBus(0:C_PLB_D

PLB Bus

 

O

 

 

 

 

WIDTH-1)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P24

 

Sl_rdWdAddr(0:3)

PLB Bus

 

O

 

 

 

 

 

 

 

 

 

 

 

 

P25

 

Sl_rdDAck

PLB Bus

 

O

 

 

 

 

 

 

 

 

 

 

 

 

P26

 

Sl_rdComp

PLB Bus

 

O

 

 

 

 

 

 

 

 

 

 

 

 

14

www.xilinx.com

DS508 March 21, 2006

 

 

Product Specification

 

 

 

 

 

 

 

 

 

PLB PCI Full Bridge (v1.00a)

 

 

 

 

 

 

 

 

 

 

 

 

Table 2: PLB PCI Bridge I/O Signals (Contd)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Port

Signal Name

 

Interface

 

I/O

Description

 

 

 

 

 

 

 

 

 

 

 

 

 

P27

Sl_rdBTerm

 

PLB Bus

 

O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P28

Sl_MBusy(0:C_PLB_NU

 

PLB Bus

 

O

 

 

 

 

M_MASTERS-1)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P29

Sl_MErr(0:C_PLB_NUM

 

PLB Bus

 

O

 

 

 

 

_MASTERS-1)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P30

PLB_MAddrAck

 

PLB Bus

 

I

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P31

PLB_MSSize(0:1)

 

PLB Bus

 

I

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P32

PLB_MRearbitrate

 

PLB Bus

 

I

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P33

PLB_MBusy

 

PLB Bus

 

I

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P34

PLB_MErr

 

PLB Bus

 

I

ACCESS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P35

PLB_MWrDAck

 

PLB Bus

 

I

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P36

PLB_MRdDBus(0:C_PL

 

PLB Bus

 

I

 

 

 

 

B_DWIDTH-1)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P37

PLB_MRdWdAddr(0:3)

 

PLB Bus

 

I

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P38

PLB_MRdDAck

 

PLB Bus

 

I

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P39

PLB_MRdBTerm

 

PLB Bus

 

I

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P40

PLB_MWrBTerm

 

PLB Bus

 

I

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P41

M_request

 

PLB Bus

 

O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P42

M_priority

 

PLB Bus

 

O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P43

M_buslock

 

PLB Bus

 

O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P44

M_RNW

 

PLB Bus

 

O

 

 

 

 

 

 

 

 

 

 

 

 

 

P45

M_BE(0:[C_PLB_DWIDT

PLB Bus

 

O

 

 

 

 

H/8]-1)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P46

M_MSize(0:1)

 

L

 

O

 

 

 

 

 

PLB Bus

 

 

 

 

 

 

AR

PLBYBus

 

 

 

 

 

 

P47

M_size(0:3)

 

 

O

 

 

 

 

P48

M_type(0:2)

 

PLB Bus

 

O

 

 

 

 

P49

M_abort

 

PLB Bus

 

O

 

 

 

 

P50

M_ABus(0:C PLB AWI

 

PLB Bus

 

O

 

 

 

 

DTH-1)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P51

M wrDBus(0:C PLB D

 

PLB Bus

 

O

 

 

 

 

WIDTH-1)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P52

M wrBurst

 

PLB Bus

 

O

 

 

 

 

 

E

 

 

 

 

 

 

 

 

P53

M rdBurst

 

PLB Bus

 

O

Table note 1 applies from P53 to P4.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI Address and Data Path Signals

 

 

 

 

 

 

 

 

 

 

 

 

P54

AD[C_PCI_DBUS_WIDT

PCI Bus

 

I/O

Time-multiplexed address and data bus

 

 

 

H-1:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DS508 March 21, 2006

www.xilinx.com

15

Product Specification

PLB PCI Full Bridge (v1.00a)

Table 2:

PLB PCI Bridge I/O Signals (Contd)

 

 

 

 

 

 

 

 

 

 

 

 

Port

 

Signal Name

Interface

 

I/O

Description

 

 

 

 

 

 

 

 

 

 

P55

 

CBE[(C_PCI_DBUS_WI

PCI Bus

 

I/O

Time-multiplexed bus command and byte enable bus

 

 

DTH/8)-1:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P56

 

PAR

PCI Bus

 

I/O

Generates and checks even parity across AD and

 

 

 

CBE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI Transaction Control Signals

 

 

 

 

 

 

 

 

 

P57

 

FRAME_N

PCI Bus

 

I/O

Driven by an initiator to indicate a bus transaction

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ACCESSIndicates that a parity error was detected while the

 

 

 

 

 

 

 

 

Indicates that a target has decoded the address

 

P58

 

DEVSEL_N

PCI Bus

 

I/O

presented during the address phase and is claiming

 

 

 

 

 

 

 

 

the transaction

 

P59

 

TRDY_N

PCI Bus

 

I/O

Indicates that the target is ready to complete the

 

 

 

 

 

 

 

 

current data phase

 

P60

 

IRDY_N

PCI Bus

 

I/O

Indicates that the initiator is ready to complete the

 

 

 

 

 

 

 

 

current data phase

 

P61

 

STOP_N

PCI Bus

 

I/O

Indicates that the target has requested to stop the

 

 

 

 

 

 

 

 

current transaction

 

P62

 

IDSEL

PCI Bus

 

I

 

Indicates that the interface is the target of a

 

 

 

 

configuration cycle

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI Interrupt Signals

 

 

 

 

 

 

 

 

 

 

P63

 

INTR_A

PCI Bus

 

O

Indicates that LogiCORE PCI interface requests an

 

 

 

interrupt

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI Error Signals

 

 

 

 

 

 

 

 

 

 

P64

 

EARLY

 

I/O

LogiCORE PCI interface was the target of a write

 

 

PERR N

PCI Bus

 

 

 

 

 

 

 

 

 

transfer or the initiator of a read transfer

 

P65

 

SERR N

PCI Bus

 

I/O

Indicates that a parity error was detected during an

 

 

 

 

 

 

 

 

address cycle, except during special cycles

 

 

 

 

PCI Arbitration Signals

 

P66

 

REQ N

PCI Bus

 

O

Indicates to the arbiter that the LogiCORE PCI

 

 

 

 

 

 

 

 

initiator requests access to the bus

 

P67

 

GNT N

PCI Bus

 

I

 

Indicates that the arbiter has granted the bus to the

 

 

 

 

LogiCORE PCI initiator

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI System Signals

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI bus reset signal is used to bring PCI-specific

 

P68

 

RST N

PCI Bus

 

I

 

registers, sequences, and signals to a consistent

 

 

 

 

 

 

 

 

state

 

 

 

 

 

 

 

 

 

 

P69

 

PCLK

PCI Bus

 

I

 

PCI bus clock signal

 

 

 

 

 

 

 

 

 

 

 

PCI Bus Internal Arbiter Signals

 

 

 

 

 

 

 

 

 

 

P70

 

REQ_N_toArb

Internal

 

O

Input from PCI Bus REQ_N available at top-level as

 

 

 

output from bridge

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P71

 

FRAME_I

Internal

 

O

Input from PCI Bus FRAME_N availalble at top-level

 

 

 

as output from bridge

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16

www.xilinx.com

DS508 March 21, 2006

 

 

Product Specification

 

 

 

 

 

 

 

 

PLB PCI Full Bridge (v1.00a)

 

 

 

 

 

 

 

 

 

 

 

Table 2: PLB PCI Bridge I/O Signals (Contd)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Port

Signal Name

 

Interface

I/O

Description

 

 

 

 

 

 

 

 

 

 

 

 

P72

IRDY_I

 

Internal

O

Input from PCI Bus IRDY_N availalble at top-level as

 

 

 

 

output from bridge

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI 64-bit Extensions (reserved for future support of 64-bit PCI)

 

 

 

 

 

 

 

 

 

 

 

 

P73

PAR64

 

PCI Bus

I/O

Generates and checks even parity across AD[63:32]

 

 

 

 

and CBE[7:4]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Indicates that a target has decoded the address

 

 

 

P74

ACK64_N

 

PCI Bus

I/O

presented during the address phase and is claiming

 

 

 

 

 

 

 

 

the transaction as a 64-bit target

 

 

 

 

 

 

 

 

 

 

 

 

P75

REQ64_N

 

PCI Bus

I/O

Driven by the initiator to indicate a 64-bit bus

 

 

 

 

transaction

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ACCESS

 

 

 

 

 

 

User Asserted PCI Interrupt Signal

 

 

 

 

 

 

 

 

Active high signal to asynchronously assert INTR_A.

 

 

 

P76

Bus2PCI_INTR

 

Internal

I

Inverted signal drives INTR N user application input

 

 

 

 

 

 

 

 

of v3.0 core. See v3.0 core documents for details on

 

 

 

 

 

 

 

 

INTR N functionality.

 

 

 

 

 

 

Virtex-4 Only, IDELAY Clock

 

 

 

P77

RCLK

 

Internal

I

200 MHz clock input to IDELAY elements of Virtex-4

 

 

 

 

 

 

 

 

buffers. Ignored if not Virtex-4 architecture.

 

 

 

 

 

PCI Bus Monitoring Debug Vector Signal

 

 

 

P78

PCI_monitor(0:47)

 

Internal

O

Output vector to monitor PCI Bus.

 

 

 

 

 

 

 

 

 

Notes:

1. This signal’s function and timing are defined in the IBM 64-Bit Processor Local Bus Architecture Specification Version 3.5.

The REQ_N_toArb facilitates an interface to an internal (i.e., in the FPGA) pci arbiter. The v3.0 input buffer for GNT_N is removed. This allowsYan internal connection to GNT N when using an internal arbiter. When an external arbiter is used, GNT_N_fromArb is not needed.

REQ_N is a 3-stated I/O. The REQLN toArb port is available to maintain a v3.0 core-like interface. The REQ_N_toArb port allows the use of the same port list for PCI bus interface and the ucf-file for the v3.0 core is the standardARfile.

The v3.0 core requires that GNT N be asserted for two clock cycles to initiate a transaction upon receiving grants.

Bus2PCI_INTR is an active High signal. It allows asynchronous assertion of INTR_A on the PCI bus. The signalEis driven by user supplied circuitry (i.e., a PLB GPIO IP core). If it is not connected in the mhs-file, then EDK 8.1 tools will tie the signal Low. The signal is inverted in the PLB PCI Bridge and AND’d with the bridge interrupt signal (active Low) to drive the INTR_N input of the v3.0 core. This signal then asynchronously drives INTR_A on the PCI bus. See the v3.0 core specifications on INTR_A behavior relative to v3.0 input INTR_N. The v3.0 core command register interrupt disable bit controls the INTR_A operation and v3.0 core status register Interrupt status bit flags if v3.0 core INTR_A is asserted.

DS508 March 21, 2006

www.xilinx.com

17

Product Specification

PLB PCI Full Bridge (v1.00a)

Port and Parameter Dependencies

The dependencies between the IPI v3.0 Bridge design port (i.e., I/O signals) and parameters are shown in Table 1.

Table 3: PLB PCI Bridge Parameters-Port Dependencies

Generic

Parameter

Affects

 

Depends

Description

 

 

 

 

 

 

 

 

Bridge Features Parameter Group

 

 

 

 

 

 

 

 

 

 

 

 

 

The set of PLB/IPIF BAR-parameters of

 

 

 

 

 

 

N = 0 to C_IPIFBAR_NUM-1 are

 

 

 

 

 

ACCESSMeaningful only if G1>1, then G6 to G7

 

 

 

 

 

 

meaningful. When C IPIFBAR NUM <

 

 

 

 

 

 

6, the parameters of N =

G1

 

C_IPIFBAR_NUM

G5-G25

 

 

C IPIFBAR NUM up to and including 5

 

 

 

 

 

 

have no effect. If C IPIFBAR NUM = 6,

 

 

 

 

 

 

the set of PLB/IPIF BAR-parameters of N

 

 

 

 

 

 

= 0 to 5 are all meaningful (i.e., G2-G25

 

 

 

 

 

 

are meaningful).

 

 

 

 

 

 

G2 to G3 define range in PLB-memory

G2

 

C_IPIFBAR_0

G3

 

G3

space that is responded to by this device

 

 

 

 

 

 

(IPIF BAR)

 

 

 

 

 

 

G2 to G3 define range in PLB-memory

G3

 

C_IPIFBAR_HIGHADDR_0

G2

 

G2

space that is responded to by this device

 

 

 

 

 

 

(IPIF BAR)

 

 

 

 

 

 

 

 

 

 

 

 

G2, G3 and

Meaningful only if G48 = 0 and in this

G4

 

C_IPIFBAR2PCIBAR_0

 

 

case only high-order bits that are the

 

 

 

G48

 

 

 

 

 

same in G2 and G3 are meaningful.

 

 

 

 

 

 

 

 

 

 

 

 

 

G5

 

C_IPIF_SPACETYPE_0

 

 

 

 

 

 

 

 

 

 

 

 

 

EARLY

 

 

 

define the range in PLB-memory space

G6

 

C IPIFBAR 1

G7

 

G1 and G7

that is responded to by this device (IPIF

 

 

 

 

 

 

BAR)

 

 

 

 

 

 

Meaningful only if G1>1, then G6 to G7

G7

 

C IPIFBAR HIGHADDR 1

G6

 

G1 and G6

define the range in PLB-memory space

 

 

 

 

 

 

that is responded to by this device (IPIF

 

 

 

 

 

 

BAR)

 

 

 

 

 

G1, G6, G7

Meaningful only if G48 = 0 and G1>1. In

G8

 

C IPIFBAR2PCIBAR 1

 

 

this case only high-order bits that are the

 

 

 

and G48

 

 

 

 

 

same in G6 and G7 are meaningful.

 

 

 

 

 

 

 

 

 

 

 

 

 

G9

 

C IPIF SPACETYPE 1

 

 

G1

Meaningful only if G1>1

 

 

 

 

 

 

 

 

 

 

 

 

 

Meaningful only if G1>2, then G10 to

G10

 

C IPIFBAR 2

G11

 

G1 and

G11 define the range in PLB-memory

 

 

G11

space that is responded to by this device

 

 

 

 

 

 

 

 

 

 

 

(IPIF BAR)

 

 

 

 

 

 

 

 

 

 

 

 

 

Meaningful only if G1>2, then G10 to

G11

 

C_IPIFBAR_HIGHADDR_2

G10

 

G1 and

G11 define the range in PLB-memory

 

 

G10

space that is responded to by this device

 

 

 

 

 

 

 

 

 

 

 

(IPIF BAR)

 

 

 

 

 

 

 

18

www.xilinx.com

DS508 March 21, 2006

 

 

Product Specification

+ 40 hidden pages