Xilinx UG078 User Manual

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Virtex-4 LX/SX

Prototype Platform

User Guide

UG078 (v1.2) May 24, 2006

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P/N 0402226-06

Xilinx UG078 User Manual

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Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes.

Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents, copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design. Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design.

THE DESIGN IS PROVIDED “AS IS” WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE, WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DESIGN, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRD-PARTY RIGHTS.

IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOST DATA AND LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN, EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH YOUR USE OF THE DESIGN, WHETHER IN CONTRACT OR TORT OR OTHERWISE, WILL IN NO EVENT EXCEED THE AMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN. YOU ACKNOWLEDGE THAT THE FEES, IF ANY, REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY.

The Design is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring failsafe controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or weapons systems (“High-Risk Applications”). Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk Applications. You represent that use of the Design in such High-Risk Applications is fully at your risk.

© 2004-2006 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners.

Revision History

The following table shows the revision history for this document.

Date

Version

Revision

 

 

 

08/30/04

1.0

Initial Xilinx release.

 

 

 

10/20/04

1.0.1

Minor corrections to text and figures.

 

 

 

06/09/05

1.0.2

Modified title from Virtex-4 Prototype Platform to Virtex-4 LX/SX Prototype Platform.

 

 

Updated figure titles and Table 8, Table 9, and Table 10.

 

 

 

06/27/05

1.0.3

Corrected clock names in Table 6 (pin W9) and Table 7 (pins H17, AJ17, and AK19).

 

 

 

05/05/06

1.1

Corrected title of Table 7.

 

 

 

05/24/06

1.2

Updated title of Table 5 and Table 7.

 

 

Added revision number to P/N on title page.

 

 

 

Virtex-4 LX/SX Prototype Platform

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UG078 (v1.2) May 24, 2006

Table of Contents

Preface: About This Guide

Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Typographical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Virtex-4 LX/SX Prototype Platform

Package Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

CD-ROM Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1. Power Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2. Power Supply Jacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3. Configuration Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4. JTAG Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5. JTAG Termination Jumper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6a. Upstream System ACE Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6b. Downstream System ACE Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6c. Upstream Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6d. Downstream Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7. Prototyping Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

8. VCCO-Enable Supply Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

9. VBATT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

10. Oscillator Sockets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

11. Differential Clock Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

12. DUT Socket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

13. Pin Breakout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

14. User LEDs (Active-High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

15. PROGRAM Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

16. RESET Switch (Active-Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

17. DONE LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

18. INIT LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

19. Platform Flash ISPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Virtex-4 LX/SX Prototype Platform

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Preface

About This Guide

This user guide describes the features and operation of the Virtex™-4 prototype platform and describes how to configure chains of FPGAs and serial PROMs.

Guide Contents

This manual contains one chapter:

“Virtex-4 LX/SX Prototype Platform”

Additional Resources

To find additional documentation, see the Xilinx website at:

http://www.xilinx.com/literature/index.htm.

To search the Answer Database of silicon, software, and IP questions and answers, or to create a technical support WebCase, see the Xilinx website at:

http://www.xilinx.com/support.

Conventions

This document uses the following conventions. An example illustrates each convention.

Typographical

The following typographical conventions are used in this document:

Convention

Meaning or Use

Example

 

 

 

 

Messages, prompts, and

 

Courier font

program files that the system

speed grade: - 100

 

displays

 

 

 

 

Courier bold

Literal commands that you enter

ngdbuild design_name

 

in a syntactical statement

 

 

 

 

 

Commands that you select from

File Open

Helvetica bold

a menu

 

 

 

 

 

 

 

Keyboard shortcuts

Ctrl+C

 

 

 

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Preface: About This Guide

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Convention

 

Meaning or Use

Example

 

 

 

 

 

 

Variables in a syntax statement

 

 

 

for which you must supply

ngdbuild design_name

 

 

values

 

 

 

 

 

 

 

 

See the Development System

Italic font

 

References to other manuals

Reference Guide for more

 

 

 

information.

 

 

 

 

 

 

 

If a wire is drawn so that it

 

 

Emphasis in text

overlaps the pin of a symbol, the

 

 

 

two nets are not connected.

 

 

 

 

 

 

An optional entry or parameter.

 

Square brackets

[ ]

However, in bus specifications,

ngdbuild [option_name]

such as bus[7:0], they are

design_name

 

 

 

 

required.

 

 

 

 

 

Braces { }

 

A list of items from which you

lowpwr ={on|off}

 

must choose one or more

 

 

 

 

 

 

 

Vertical bar |

 

Separates items in a list of

lowpwr ={on|off}

 

choices

 

 

 

 

 

 

 

Vertical ellipsis

 

 

IOB #1: Name = QOUT’

 

 

IOB #2: Name = CLKIN’

.

 

Repetitive material that has

 

.

.

 

been omitted

 

.

.

 

 

 

 

.

 

 

 

 

 

 

 

Horizontal ellipsis . . .

Repetitive material that has

allow block block_name

been omitted

loc1 loc2 ... locn;

 

 

 

 

 

 

Online Document

The following conventions are used in this document:

Convention

Meaning or Use

Example

 

 

 

 

 

See the section “Additional

Blue text

Cross-reference link to a location

Resources” for details.

in the current document

Refer to “Title Formats” in

 

 

 

Chapter 1 for details.

 

 

 

Red text

Cross-reference link to a location

See Figure 2-5 in the Virtex-II

in another document

Handbook.

 

 

 

 

Blue, underlined text

Hyperlink to a website (URL)

Go to http://www.xilinx.com

for the latest speed files.

 

 

 

 

 

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UG078 (v1.2) May 24, 2006

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Virtex-4 LX/SX Prototype Platform

Package Contents

Xilinx Virtex™-4 prototype platform board

User guide

Device vacuum tool

Headers for test points

CD-ROM

One low-voltage, 14-pin, dual-inline package (DIP) crystal oscillator

CD-ROM Contents

User guide in PDF format

Example designs

These designs include the Verilog source code, user constraints files (*.ucf), documentation in PDF, and a readme.txt file

Bitstream files (*.bit) for each part type supported by the board (Bitstream synthesized using Xilinx tools)

Full schematics of the board in both PDF format and ViewDraw schematic format

PC board layout in Pads PCB format

Gerber files in *.pho and *.pdf for the PC board (There are many free or shareware Gerber file viewers available on the Web for viewing and printing these files)

Introduction

The Virtex-4 prototype platform and demonstration boards allow designers to investigate and experiment with the features of Virtex-4 series FPGAs. This user guide describes the features and operation of the Virtex-4 prototype platform, including how to configure chains of FPGAs and serial PROMs.

Note: Prototype platforms are intended strictly for evaluating the functionality of Virtex-4 features and are not intended for A/C characterization or high-speed I/O evaluation.

Virtex-4 LX/SX Prototype Platform

www.xilinx.com

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