Xilinx ML310 User Manual

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ML310 User

Guide

Virtex-II Pro Embedded

Development Platform

UG068 (v1.01) August 25, 2004

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"Xilinx" and the Xilinx logo shown above are registered trademarks of Xilinx, Inc. Any rights not expressly granted herein are reserved.

CoolRunner, RocketChips, Rocket IP, Spartan, StateBENCH, StateCAD, Virtex, XACT, XC2064, XC3090, XC4005, and XC5210 are registered trademarks of Xilinx, Inc.

The shadow X shown above is a trademark of Xilinx, Inc.

ACE Controller, ACE Flash, A.K.A. Speed, Alliance Series, AllianceCORE, Bencher, ChipScope, Configurable Logic Cell, CORE Generator, CoreLINX, Dual Block, EZTag, Fast CLK, Fast CONNECT, Fast FLASH, FastMap, Fast Zero Power, Foundation, Gigabit Speeds...and Beyond!, HardWire, HDL Bencher, IRL, J Drive, JBits, LCA, LogiBLOX, Logic Cell, LogiCORE, LogicProfessor, MicroBlaze, MicroVia, MultiLINX, NanoBlaze, PicoBlaze, PLUSASM, PowerGuide, PowerMaze, QPro, Real-PCI, RocketIO, SelectIO, SelectRAM, SelectRAM+, Silicon Xpresso, Smartguide, Smart-IP, SmartSearch, SMARTswitch, System ACE, Testbench In A Minute, TrueMap, UIM, VectorMaze, VersaBlock, VersaRing, Virtex-II Pro, Virtex-II EasyPath, Wave Table, WebFITTER, WebPACK, WebPOWERED, XABEL, XACTFloorplanner, XACT-Performance, XACTstep Advanced, XACTstep Foundry, XAM, XAPP, X-BLOX +, XC designated products, XChecker, XDM, XEPLD, Xilinx Foundation Series, Xilinx XDTV, Xinfo, XSI, XtremeDSP and ZERO+ are trademarks of Xilinx, Inc.

The Programmable Logic Company is a service mark of Xilinx, Inc.

All other trademarks are the property of their respective owners.

Xilinx, Inc. does not assume any liability arising out of the application or use of any product described or shown herein; nor does it convey any license under its patents, copyrights, or maskwork rights or any rights of others. Xilinx, Inc. reserves the right to make changes, at any time, in order to improve reliability, function or design and to supply the best product possible. Xilinx, Inc. will not assume responsibility for the use of any circuitry described herein other than circuitry entirely embodied in its products. Xilinx provides any design, code, or information shown or described herein "as is." By providing the design, code, or information as one possible implementation of a feature, application, or standard, Xilinx makes no representation that such implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of any such implementation, including but not limited to any warranties or representations that the implementation is free from claims of infringement, as well as any implied warranties of merchantability or fitness for a particular purpose. Xilinx, Inc. devices and products are protected under U.S. Patents. Other U.S. and foreign patents pending. Xilinx, Inc. does not represent that devices shown or products described herein are free from patent infringement or from any other third party right. Xilinx, Inc. assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made. Xilinx, Inc. will not assume any liability for the accuracy or correctness of any engineering or software support or assistance provided to a user.

Xilinx products are not intended for use in life support appliances, devices, or systems. Use of a Xilinx product in such applications without the written consent of the appropriate Xilinx officer is prohibited.

The contents of this manual are owned and copyrighted by Xilinx. Copyright 1994-2004 Xilinx, Inc. All Rights Reserved. Except as stated herein, none of the material may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of any material contained in this manual may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes.

ML310 User Guide

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ML310 User Guide

UG068 (v1.01) August 25, 2004

The following table shows the revision history for this document..

 

Version

Revision

 

 

 

08/15/04

1.0

Initial Xilinx release.

 

 

 

08/25/04

1.01

Added SysACE CFGADDR details.

 

 

 

 

 

 

 

 

 

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ML310 User Guide

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Table of Contents

Preface: About This Manual

Chapter 1: Introduction to Virtex-II Pro, ISE, and EDK

Virtex-II Pro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Summary of Virtex-II Pro Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

PowerPC™ 405 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

RocketIO 3.125 Gb/s Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Virtex-II FPGA Fabric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Foundation ISE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Foundation Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Design Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Implementation and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Board Level Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Embedded Development Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Chapter 2: ML310 Embedded Development Platform

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Board Hardware. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 DDR Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DDR DIMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DDR Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DDR Memory Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Serial Port FPGA UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Introduction to Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Signaling Standards of RS-232 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 RS-232 on the ML310 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 System ACE CF Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Board Bring-Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Non-Volatile Storage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 XC2VP30 Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 JTAG Connection to XC2VP30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Parallel Cable IV Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 System ACE JTAG Configuration Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 GPIO LEDs and LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 GPIO LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 GPIO LCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 CPU Debug and CPU Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 CPU Debug Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 CPU Debug Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 CPU Debug Connection to XC2VP30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

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PCI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 ALi South Bridge Interface, M1535D+, U15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Parallel Port Interface, connector assembly P1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Serial Port Interface, connector assembly P1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

USB, connector assembly J3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 IDE, connectors J15 and J16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 GPIO, connector J5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 System Management Bus (SMBus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 AC97 Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

PS/2 Keyboard/Mouse Interface, connector P2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Flash ROM, U4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Intel GD82559, U11, 10/100 Ethernet Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Intel GD82559 Ethernet Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 IIC/SMBus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Introduction to IIC/SMBus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 IIC/SMBus Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 IIC/SMBus on ML310 Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 SPI Signaling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 SPI Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Push Buttons, Switches, Front Panel Interface and Jumpers . . . . . . . . . . . . . . . . . . . . . 53 Push Buttons. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

System ACE Configuration Dipswitch, SW3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Front Panel Interface Connector, J23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Jumpers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 ATX Power Distribution and Voltage Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

High-Speed I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 ML310 PM Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 PM1 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 PM2 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Adapter Board PM Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 ML310 PM Utility Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Contact Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 PM1 Power and Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 PM2 Power and Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 ML310 PM User I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 PM1 User I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 ML310 PM2 User I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

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Preface

About This Manual

This manual accompanies the ML310 Embedded Development System and contains information about the ML310 Hardware Platform and software tools.

Manual Contents

This manual contains the following chapters:

Chapter 1, “Introduction to Virtex-II Pro, ISE, and EDK,” provides an overview of the hardware and software features.

Chapter 2, “ML310 Embedded Development Platform,” provides an overview of the embedded development platform and details the components and features of the ML310 board.

Additional Resources

For additional information, go to http://support.xilinx.com. The following table lists some of the resources you can access from this website. You can also directly access these resources using the provided URLs.

Resource

Description/URL

 

 

Tutorials

Tutorials covering Xilinx design flows, from design entry to

 

verification and debugging

 

http://support.xilinx.com/support/techsup/tutorials/index.htm

 

 

Answer Browser

Database of Xilinx solution records

 

http://support.xilinx.com/xlnx/xil_ans_browser.jsp

 

 

Application Notes

Descriptions of device-specific design techniques and approaches

 

http://support.xilinx.com/apps/appsweb.htm

 

 

Data Sheets

Device-specific information on Xilinx device characteristics,

 

including readback, boundary scan, configuration, length count,

 

and debugging

 

http://support.xilinx.com/xlnx/xweb/xil_publications_index.jsp

 

 

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Chapter :

Resource

Description/URL

 

 

Problem Solvers

Interactive tools that allow you to troubleshoot your design issues

 

http://support.xilinx.com/support/troubleshoot/psolvers.htm

 

 

Tech Tips

Latest news, design tips, and patch information for the Xilinx

 

design environment

 

http://www.support.xilinx.com/xlnx/xil_tt_home.jsp

 

 

Conventions

This document uses the following conventions. An example illustrates each convention.

Typographical

The following typographical conventions are used in this document:

Convention

 

Meaning or Use

Example

 

 

 

 

 

 

Messages, prompts, and

 

Courier font

 

program files that the system

speed grade: - 100

 

 

displays

 

 

 

 

 

Courier bold

 

Literal commands that you

ngdbuild design_name

 

enter in a syntactical statement

 

 

 

 

 

 

Commands that you select

File Open

Helvetica bold

 

from a menu

 

 

 

 

 

 

 

 

Keyboard shortcuts

Ctrl+C

 

 

 

 

 

 

Variables in a syntax

 

 

 

statement for which you must

ngdbuild design_name

 

 

supply values

 

 

 

 

 

 

 

 

See the Development System

Italic font

 

References to other manuals

Reference Guide for more

 

 

 

information.

 

 

 

 

 

 

 

If a wire is drawn so that it

 

 

Emphasis in text

overlaps the pin of a symbol,

 

 

 

the two nets are not connected.

 

 

 

 

 

 

An optional entry or

 

Square brackets

[ ]

parameter. However, in bus

ngdbuild [option_name]

specifications, such as

design_name

 

 

 

 

bus[7:0], they are required.

 

 

 

 

 

Braces { }

 

A list of items from which you

lowpwr ={on|off}

 

must choose one or more

 

 

 

 

 

 

 

Vertical bar |

 

Separates items in a list of

lowpwr ={on|off}

 

choices

 

 

 

 

 

 

 

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Convention

Meaning or Use

Example

 

 

 

Vertical ellipsis

 

IOB #1: Name = QOUT’

 

IOB #2: Name = CLKIN’

.

Repetitive material that has

.

.

been omitted

.

.

 

 

.

 

 

 

 

 

Horizontal ellipsis . . .

Repetitive material that has

allow block block_name

been omitted

loc1 loc2 ... locn;

 

 

 

 

Online Document

The following conventions are used in this document:

Convention

Meaning or Use

Example

 

 

 

 

Cross-reference link to a

See the section “Additional

Blue text

location in the current file or

Resources” for details.

in another file in the current

Refer to “Title Formats” in

 

 

document

Chapter 1 for details.

 

 

 

Red text

Cross-reference link to a

See Figure 2-5 in the Virtex-II

location in another document

Handbook.

 

 

 

 

Blue, underlined text

Hyperlink to a website (URL)

Go to http://www.xilinx.com

for the latest speed files.

 

 

 

 

 

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Chapter :

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Chapter 1

Introduction to Virtex-II Pro, ISE, and EDK

Virtex-II Pro

The Virtex-II Pro Platform FPGA solution is the most technically sophisticated silicon and software product development in the history of the programmable logic industry. The goal was to revolutionize system architecture “from the ground up.” To achieve that objective, the best circuit engineers and system architects from IBM, Mindspeed, and Xilinx codeveloped the world's most advanced Platform FPGA silicon product. Leading teams from top embedded systems companies worked together with Xilinx software teams to develop the systems software and IP solutions that enabled new system architecture paradigm.

The result is the first Platform FPGA solution capable of implementing high performance system-on-a-chip designs previously the exclusive domain of custom ASICs, yet with the flexibility and low development cost of programmable logic. The Virtex-II Pro family marks the first paradigm change from programmable logic to programmable systems, with profound implications for leading-edge system architectures in networking applications, deeply embedded systems, and digital signal processing systems. It allows custom user-defined system architectures to be synthesized, next-generation connectivity standards to be seamlessly bridged, and complex hardware and software systems to be codeveloped rapidly with in-system debug at system speeds. Together, these capabilities usher in the next programmable logic revolution.

Summary of Virtex-II Pro Features

The Virtex-II Pro has an impressive collection of both programmable logic and hard IP that has historically been the domain of the ASICs.

High-performance Platform FPGA solution including

Up to twenty-four RocketIO™ embedded multi-gigabit transceiver blocks (based on Mindspeed's SkyRail™ technology)

Up to four IBM® PowerPC™ RISC processor blocks

Based on Virtex™-II Platform FPGA technology

Flexible logic resources, up to 125,136 Logic Cells

SRAM-based in-system configuration

Active Interconnect™ technology

SelectRAM™ memory hierarchy

Up to 556 Dedicated 18-bit x 18-bit multiplier blocks

High-performance clock management circuitry

SelectIO™-Ultra technology

Digitally Controlled Impedance (DCI) I/O

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Chapter 1: Introduction to Virtex-II Pro, ISE, and EDK

Table 1-1: Virtex-II Pro Family Members

Device

2VP2

2VP4

2VP7

2VP20

2VP30

2VP40

2VP50

2VP70

2VP100

2VP125

 

 

 

 

 

 

 

 

 

 

 

Logic Cells

3,168

6,768

11,088

20,880

30,816

43,632

53,136

74,448

99,216

125,136

 

 

 

 

 

 

 

 

 

 

 

PPC405

0

1

1

2

2

2

2

2

2

4

 

 

 

 

 

 

 

 

 

 

 

MGTs

4

4

8

8

8

12

16

20

20

24

 

 

 

 

 

 

 

 

 

 

 

BRAM

216

504

792

1,584

2,448

3,456

4,176

5,904

7,992

10,008

(Kbits)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Xtreme

12

28

44

88

136

192

232

328

444

556

Multipliers

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PowerPC™ 405 Core

Embedded 300+ MHz Harvard architecture core

Low power consumption: 0.9 mW/MHz

Five-stage data path pipeline

Hardware multiply/divide unit

Thirty-two 32-bit general purpose registers

16 KB two-way set-associative instruction cache

16 KB two-way set-associative data cache

Memory Management Unit (MMU)

64-entry unified Translation Look-aside Buffers (TLB)

Variable page sizes (1 KB to 16 MB)

Dedicated on-chip memory (OCM) interface

Supports IBM CoreConnect™ bus architecture

Debug and trace support

Timer facilities

RocketIO 3.125 Gb/s Transceivers

Full-duplex serial transceiver (SERDES) capable of baud rates from 622 Mb/s to 3.125 Gb/s

80 Gb/s duplex data rate (16 channels)

Monolithic clock synthesis and clock recovery (CDR)

Fibre Channel, Gigabit Ethernet, 10 Gb Attachment Unit Interface (XAUI), and Infiniband-compliant transceivers

8-, 16-, or 32-bit selectable internal FPGA interface

8B /10B encoder and decoder

50/75on-chip selectable transmit and receive terminations

Programmable comma detection

Channel bonding support (two to sixteen channels)

Rate matching via insertion/deletion characters

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Virtex-II Pro

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Four levels of selectable pre-emphasis

Five levels of output differential voltage

Per-channel internal loopback modes

2.5V transceiver supply voltage

Virtex-II FPGA Fabric

Description of the Virtex-II Family fabric follows:

SelectRAM memory hierarchy

Up to 10 Mb of True Dual-Port RAM in 18 Kb block SelectRAM resources

Up to 1.7 Mb of distributed SelectRAM resources

High-performance interfaces to external memory

Arithmetic functions

Dedicated 18-bit x 18-bit multiplier blocks

Fast look-ahead carry logic chains

Flexible logic resources

Up to 111,232 internal registers/latches with Clock Enable

Up to 111,232 look-up tables (LUTs) or cascadable variable (1 to 16 bits) shift registers

Wide multiplexers and wide-input function support

Horizontal cascade chain and Sum-of-Products support

Internal 3-state busing

High-performance clock management circuitry

Up to eight Digital Clock Manager (DCM) modules

-Precise clock de-skew

-Flexible frequency synthesis

-High-resolution phase shifting

16 global clock multiplexer buffers in all parts

Active Interconnect technology

Fourth-generation segmented routing structure

Fast, predictable routing delay, independent of fanout

Deep sub-micron noise immunity benefits

Select I/O-Ultra technology

Up to 852 user I/Os

Twenty two single-ended standards and five differential standards

Programmable LVTTL and LVCMOS sink/source current (2 mA to 24 mA) per I/O

Digitally Controlled Impedance (DCI) I/O: on-chip termination resistors for single-ended I/O standards

PCI support(1)

Differential signaling

ML310 User Guide

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Chapter 1: Introduction to Virtex-II Pro, ISE, and EDK

-840 Mb/s Low-Voltage Differential Signaling I/O (LVDS) with current mode drivers

-Bus LVDS I/O

-HyperTransport™ (LDT) I/O with current driver buffers

-Built-in DDR input and output registers

Proprietary high-performance SelectLink technology for communications between Xilinx devices

-High-bandwidth data path

-Double Data Rate (DDR) link

-Web-based HDL generation methodology

SRAM-based in-system configuration

Fast SelectMAP™ configuration

Triple Data Encryption Standard (DES) security option (bitstream encryption)

IEEE1532 support

Partial reconfiguration

Unlimited reprogrammability

Readback capability

Supported by Xilinx Foundation™ and Alliance™ series development systems

Integrated VHDL and Verilog design flows

ChipScope™ Pro Integrated Logic Analyzer

0.13-µm, nine-layer copper process with 90 nm high-speed transistors

1.5V (VCCINT) core power supply, dedicated 2.5V VCCAUX auxiliary and VCCO I/O power supplies

IEEE 1149.1 compatible boundary-scan logic support

Flip-Chip and Wire-Bond Ball Grid Array (BGA) packages in standard 1.00 mm pitch

Each device 100% factory tested

Foundation ISE

ISE Foundation is the industry's most complete programmable logic design environment. ISE Foundation includes the industry's most advanced timing driven implementation tools available for programmable logic design, along with design entry, synthesis and verification capabilities. With its ultra-fast runtimes, ProActive Timing Closure technologies, and seamless integration with the industry's most advanced verification products, ISE Foundation offers a great design environment for anyone looking for a complete programmable logic design solution.

Foundation Features

Design Entry

ISE greatly improves your “Time-to-Market”, productivity, and design quality with robust design entry features.

ISE provides support for today's most popular methods for design capture including HDL and schematic entry, integration of IP cores as well as robust support for reuse of your own

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IP. ISE even includes technology called IP Builder, which allows you to capture your own IP and reuse it in other designs.

ISE’s Architecture Wizards allow easy access to device features like the Digital Clock

Manager and Multi-Gigabit I/O technology.

ISE also includes a tool called PACE (Pinout Area Constraint Editor) which includes a front-end pin assignment editor, a design hierarchy browser, and an area constraint editor. By using PACE, designers are able to observe and describe information regarding the connectivity and resource requirements of a design, resource layout of a target FPGA, and the mapping of the design onto the FPGA via location/area.

This rich mixture of design entry capabilities provides the easiest to use design environment available today for your logic design.

Synthesis

Synthesis is one of the most essential steps in your design methodology. It takes your conceptual Hardware Description Language (HDL) design definition and generates the logical or physical representation for the targeted silicon device.

A state of the art synthesis engine is required to produce highly optimized results with a fast compile and turnaround time. To meet this requirement, the synthesis engine needs to be tightly integrated with the physical implementation tool and have the ability to proactively meet the design timing requirements by driving the placement in the physical device. In addition, cross probing between the physical design report and the HDL design code will further enhance the turnaround time.

Xilinx ISE provides the seamless integration with the leading synthesis engines from Mentor Graphics, Synopsys, and Synplicity. You can use the synthesis engine of our choice. In addition, ISE includes Xilinx proprietary synthesis technology, XST. You have options to use multiple synthesis engines to obtain the best-optimized result of your programmable logic design.

Implementation and Configuration

Programmable logic design implementation assigns the logic created during design entry and synthesis into specific physical resources of the target device.

The term “place and route” has historically been used to describe the implementation process for FPGA devices and “fitting” has been used for CPLDs. Implementation is followed by device configuration, where a bitstream is generated from the physical place and route information and downloaded into the target programmable logic device.

To ensure designers get their product to market quickly, Xilinx ISE software provides several key technologies required for design implementation:

Ultra-fast runtimes enable multiple “turns” per day

ProActive™ Timing Closure drives high-performance results

Timing-driven place and route combined with “push-button” ease

Incremental Design

Macro Builder

ML310 User Guide

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Chapter 1: Introduction to Virtex-II Pro, ISE, and EDK

Board Level Integration

Xilinx understands the critical issues such as complex board layout, signal integrity, highspeed bus interface, high-performance I/O bandwidth, and electromagnetic interference for system level designers.

To ease the system level designers’ challenge, ISE provides support to all Xilinx leading FPGA technologies:

System IO

XCITE

Digital clock management for system timing

EMI control management for electromagnetic interference

To really help you ensure your programmable logic design works in context of your entire system, Xilinx provides complete pin configurations, packaging information, tips on signal integration, and various simulation models for your board level verification including:

IBIS models

HSPICE models

STAMP models

Embedded Development Kit

The Embedded Development Kit (EDK) is Xilinx’s solution for embedded programmable systems design and supports designs using the Virtex-II Pro. EDK hardware and software development tools, combined with the advanced features of Virtex-II Pro FPGA provide you with a new level of system design.

The system design process can be loosely divided into the following tasks:

Build the software application

Simulate the hardware description

Simulate the hardware with the software application

Simulate the hardware into the FPGA using the software application in on-chip memory

Run timing simulation

Configure the bitstream for the FPGA

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Chapter 2

ML310 Embedded Development

Platform

Overview

The ML310 Embedded Development Platform offers designers a versatile Virtex-II Pro XC2VP30-FF896 based platform for rapid prototyping and system verification. In addition to the more than 30,000 logic cells, over 2,400 Kb of BRAM, dual PowerPC405 processors and RocketIO transceivers available in the FPGA, the ML310 provides an onboard Ethernet MAC/PHY, DDR memory, multiple PCI bus slots, and standard PC I/O ports within an ATX form factor board. An integrated System ACE CF controller is deployed to perform board bring-up and to load applications from the included 512 MB CompactFlash card.

The ML310 CDROM contains documentation and tutorials, along with reference designs and data sheets. The most recent ML310 material can be found on the Xilinx web site at http://www.xilinx.com/ml310.

The setup and quickstart documentation highlights the functionality of the ML310 using the applications shipped on the included CompactFlash card. The reference designs were produced using the Xilinx Embedded Development Kit (EDK), ISE and Answer Database solution records. Tutorials in coordination with Xilinx documentation for EDK, ISE, and the Answer Database, describe how the reference designs and applications were produced. These tutorials may be used to re-create the applications provided and also as a basis for the development of new designs. Xilinx EDK provides for the development of basic board specific systems beginning with Base System Builder (BSB) to highly customized systems leveraging the flexibility of Xilinx Platform Studio (XPS) and the EDK IP.

Documentation for Xilinx tools and solutions can be found at:

EDK: http://www.xilinx.com/edk

ISE: http://www.xilinx.com/ise

Answer Database: http://www.xilinx.com/support

An image of the ML310 board and its corresponding block diagram are shown in,

Figure 2-1and Figure 2-2 respectively.

ML310 User Guide

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Xilinx ML310 User Manual

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Chapter 2: ML310 Embedded Development Platform

Figure 2-1: ML310 Board

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Overview

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Figure 2-2 shows a high-level block diagram of the ML310 and its peripherals.

CF System ACE

RS232

SMBus

SPI

GPIO / LEDs

GPIO SPI SMBus UART SysACE

INTC

OPB

Bus

PCI Bridge

PLB BRAM

 

OPB2PLB

 

Bridge

DDR

PLB

Bus

 

PLB2OPB

Bridge

PPC 405

OCM

Bus

OCM BRAM

XC2VP30

FF896

8 RocketIO MGTs 3 LVDS pairs 1 LVDS Clock pair

38 Single-EndedI/O

 

 

 

 

39 LVDS Pairs

1 Clock

256 MB

DDR DIMM

High-Speed

PM1

High-Speed

PM2

3.3V PCI

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AMD

 

 

 

 

 

 

 

 

RS232

 

 

 

 

Intel GD82559

 

 

TI

 

 

 

 

 

 

 

 

 

 

 

 

 

RJ45

 

 

 

 

 

 

 

 

 

 

Flash

 

 

 

 

 

 

 

 

(2)

 

 

 

10/100 Ethernet NIC

 

PCI 2250

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3.3V PCI

GPIO

 

 

 

ALi

 

 

 

PS/2

 

 

 

 

5V PCI

 

 

 

 

 

 

 

Slots

 

 

 

 

 

 

K/M

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

M1535D+

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IDE

 

 

 

 

Parallel

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

South Bridge

 

 

 

 

 

 

 

5V PCI

 

 

 

 

 

 

 

 

(2)

 

 

 

 

 

 

Port

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

USB

 

 

 

 

 

 

 

 

SMBus

 

 

 

 

Slots

 

 

 

 

 

 

 

 

(2)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Audio

Figure 2-2: ML310 High-Level Block Diagram

Features

In addition to the Virtex-II Pro™ FPGA with the embedded PPC405, the ML310 board features the following:

ATX Motherboard formfactor

256 MB DDR DIMM

System ACE™ CF Controller

512 MB CompactFlash card

Onboard 10/100 Ethernet NIC

4 PCI slots (3.3V and 5V)

LCD character display and cable

FPGA serial port connection

RS-232 mini-cable

Personality module interface for RocketIO and LVDS access

Standard JTAG connectivity

ALi Super I/O

1 parallel and 2 serial ports

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Chapter 2: ML310 Embedded Development Platform

2 USB ports

2 IDE connectors

GPIO

SMBus Interface

AC97 Audio CODEC

PS/2 keyboard and mouse ports

ATX power supply

Board Hardware

The ML310 Virtex-II Pro FPGA is connected to several peripherals listed below. The peripherals are either directly connected to the FPGA or in directly accessible via the PCI Bus. The following sections describe the main features of each of the peripherals and how they interface with the Xilinx Virtex-II Pro. The EDK Processor IP Reference Guide should be reviewed as well as each of the data sheets corresponding to the devices listed. All device data sheets are located on the ML310 CDROM.

DDR DIMM Memory, compatible with EDK supported IP and SW drivers

FPGA UART, compatible with EDK supported IP and SW drivers

System ACE, compatible with EDK supported IP and SW drivers

GPIOLEDs / LCD, compatible with EDK supported IP and SW drivers

PCI Bus Interface, compatible with EDK supported IP and SW drivers

ALi M1535D+ PCI Device

Intel Ethernet/NIC PCI Device

SMBus/IIC, multiple devices available, compatible with EDK supported IP and SW drivers

LTC1694 SMBUS accelerator

RTC8566 Real time clock

24LC64 EEPROM 64k bits

LM87 voltage/temp monitor

DDR DIMM SPD EEPROM

SPI EEPROM, compatible with EDK supported IP and SW drivers

High speed IO through RocketIO Transceivers

Clock Generation

The ML310 board employs a Xilinx XC2VP30-FF896 FPGA. Several clocks are distributed throughout the ML310 as can be seen in Figure 2-3. The main system clock is a 100 MHz oscillator, X10. The system clock is typically used to generate multiple clocks with varying frequency and phases within the FPGA fabric by using the Virtex-II Pro DMCs. The FPGA also generates and drives clocks required by the DDR DIMM memory and PCI bus interfaces.

The FPGA requires different banking voltages that are set based on the I/O voltage interface requirements of each device connected directly to the FPGA. All but two of the banks are set to 2.5V while banks 1 and 2 are set to 3.0V as shown in Figure 2-3. The Virtex-

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II Pro FPGA I/O can be configured to use different IO standards such as SSTL2 as required on the DDR DIMM interface. Please review the ML310 Virtex-II Pro data sheet for more information regarding I/O standards.

Figure 2-3 shows the top-level clocking for the ML310 board.

X8

OSC

SYACE_FPGA_CLK

 

 

 

 

33MHz

 

 

SYSACE

 

LCD

 

X7

J20

 

 

 

 

PM_CLK_TOP

OSC

 

 

 

 

 

LVDS_CLK_LOC_P

 

 

 

156.25

LVDS_CLK_LOC_N

 

 

 

MHz

 

 

 

 

 

 

 

J17

USER_SMA_CLK

 

 

 

X9

 

 

 

 

J21

 

 

 

 

 

OSC

 

 

 

 

 

 

 

 

 

 

 

125MHz

 

 

7P

6S

5P

4S

 

 

 

 

PM IO

12

 

BANK 0

 

 

2.5V

 

 

2.5V

 

 

LVDS

(6 LVDS)

 

 

 

 

 

 

 

 

DCM

 

DCM

 

 

 

 

X0Y1

 

X1Y1

 

 

 

BANK 7

 

 

 

 

DDR

Note:

2.5V

 

 

 

 

DIMM

All 3 DDR

 

 

 

 

 

64 bit

Clock nets

 

 

 

 

 

256MB are length

 

 

 

 

 

 

matched

 

 

 

 

DDR_CLK

DDR_CLKB

BANK 6

 

 

 

2.5V

 

 

 

FB

DCM

 

DCM

CLK

 

X0Y0

 

X1Y0

DDR_

BANK 5

 

 

 

2.5V

 

7S

6P

5S

4P

LVDS CLK LOC N

LVDS CLK LOC P

USER CLKSYS

DDR_CLK_FB

(notused)

OSC

X6

SYACE_FPGA_CLK

LEDs

 

IIC

 

 

 

UART

 

PM IO

 

 

 

 

 

 

 

 

 

 

 

 

3V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

26

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SYS_CLK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LVDS_CLK_EXT_N

 

(user_clk_pci)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LVDS_CLK_EXT_P

 

 

 

 

PCI_P_CLK5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

All 5 PCI

3P

2S

 

 

 

1P

 

0S

PCI_P_CLK1

Clock nets

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

thru

are length

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BANK 1

 

 

 

 

 

PCI_P_CLK4 matched

 

 

 

 

 

3.0V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DCM

 

 

 

DCM

 

 

 

 

 

 

 

 

 

 

 

X2Y1

 

 

X03Y1

 

 

 

 

 

 

 

PCI

 

 

 

 

 

 

 

 

 

 

 

 

 

BANK 2

 

BUS

 

 

 

 

 

 

 

 

 

 

 

 

 

3.0V

 

3.0V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BANK 3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2.5V

72

 

PM IO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(36 LVDS)

2.5V

 

 

 

 

 

DCM

 

 

 

 

DCM

 

 

 

 

 

 

 

LVDS

 

 

 

 

 

X2Y0

 

 

 

 

X3Y0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BANK 4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2.5V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3S

 

2P

 

1S

 

0P

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LVDS_CLK_EXT_P

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LVDS_CLK_EXT_N

 

 

 

 

 

 

 

 

PM_CLK_BOT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8

 

 

 

 

 

 

 

 

 

 

 

 

 

6

 

 

 

 

 

MGTs

 

 

 

 

 

 

 

 

 

 

 

 

(3 LVDS)

 

 

(to FPGA)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CPU

 

 

 

 

TRACE

 

 

SPI

 

PM IO

 

 

 

 

 

 

 

 

DEBUG

 

 

 

 

 

 

 

2.5V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X10

OSC 100MHz

PM2

PM1

Figure 2-3: Top-Level Clocking

DDR Memory

DDR DIMM

The ML310 includes a registered 256MB PC3200 Double Data Rate (DDR) Dual Inline Memory Module (DIMM) with an industry standard 184-pin count. The DDR DIMM is commercially available from Wintec Industries as part number W4F232726HA-5Q. The associated datasheet is provided on the ML310 CDROM. The DDR DIMM is manufactured using nine Infineon HYB25D256800BT-5, 32Mx8 DDR SDRAM devices with 13-row address lines, 10-column address lines, and 4 bank select lines. Read and write access to the Infineon devices is programmable in burst lengths of 2, 4, or 8 column locations. The memory module inputs and outputs are compatible with SSTL2 signaling. Serial Presence Detect (SPD) using an SMBus interface to the DDR DIMM is also supported. Please refer to section “IIC/SMBus Interface” for more details on accessing the DIMM module’s SPD EEPROM.

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