Xilinx UG018 User Manual

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PowerPC™ 405 Processor

Block Reference Guide

Embedded Development Kit

UG018 (v2.0) August 20, 2004

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"Xilinx" and the Xilinx logo shown above are registered trademarks of Xilinx, Inc. Any rights not expressly granted herein are reserved.

CoolRunner, RocketChips, Rocket IP, Spartan, StateBENCH, StateCAD, Virtex, XACT, XC2064, XC3090, XC4005, and XC5210 are registered trademarks of Xilinx, Inc.

The shadow X shown above is a trademark of Xilinx, Inc.

ACE Controller, ACE Flash, A.K.A. Speed, Alliance Series, AllianceCORE, Bencher, ChipScope, Configurable Logic Cell, CORE Generator, CoreLINX, Dual Block, EZTag, Fast CLK, Fast CONNECT, Fast FLASH, FastMap, Fast Zero Power, Foundation, Gigabit Speeds...and Beyond!, HardWire, HDL Bencher, IRL, J Drive, JBits, LCA, LogiBLOX, Logic Cell, LogiCORE, LogicProfessor, MicroBlaze, MicroVia, MultiLINX, NanoBlaze, PicoBlaze, PLUSASM, PowerGuide, PowerMaze, QPro, Real-PCI, RocketIO, SelectIO, SelectRAM, SelectRAM+, Silicon Xpresso, Smartguide, Smart-IP, SmartSearch, SMARTswitch, System ACE, Testbench In A Minute, TrueMap, UIM, VectorMaze, VersaBlock, VersaRing, Virtex-II Pro, Virtex-II EasyPath, Virtex-4, Virtex-4-FX, Wave Table, WebFITTER, WebPACK, WebPOWERED, XABEL, XACT-Floorplanner, XACT-Performance, XACTstep Advanced, XACTstep Foundry, XAM, XAPP, X-BLOX +, XC designated products, XChecker, XDM, XEPLD, Xilinx Foundation Series, Xilinx XDTV, Xinfo, XSI, XtremeDSP and ZERO+ are trademarks of Xilinx, Inc.

The Programmable Logic Company is a service mark of Xilinx, Inc.

All other trademarks are the property of their respective owners.

Xilinx, Inc. does not assume any liability arising out of the application or use of any product described or shown herein; nor does it convey any license under its patents, copyrights, or maskwork rights or any rights of others. Xilinx, Inc. reserves the right to make changes, at any time, in order to improve reliability, function or design and to supply the best product possible. Xilinx, Inc. will not assume responsibility for the use of any circuitry described herein other than circuitry entirely embodied in its products. Xilinx provides any design, code, or information shown or described herein "as is." By providing the design, code, or information as one possible implementation of a feature, application, or standard, Xilinx makes no representation that such implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of any such implementation, including but not limited to any warranties or representations that the implementation is free from claims of infringement, as well as any implied warranties of merchantability or fitness for a particular purpose. Xilinx, Inc. devices and products are protected under U.S. Patents. Other U.S. and foreign patents pending. Xilinx, Inc. does not represent that devices shown or products described herein are free from patent infringement or from any other third party right. Xilinx, Inc. assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made. Xilinx, Inc. will not assume any liability for the accuracy or correctness of any engineering or software support or assistance provided to a user.

Xilinx products are not intended for use in life support appliances, devices, or systems. Use of a Xilinx product in such applications without the written consent of the appropriate Xilinx officer is prohibited.

The contents of this manual are owned and copyrighted by Xilinx. Copyright 1994-2004 Xilinx, Inc. All Rights Reserved. Except as stated herein, none of the material may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of any material contained in this manual may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes.

PowerPC™ 405 Processor Block Reference Guide

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UG018 (v2.0) August 20, 2004

 

1-800-255-7778

 

PowerPC™ 405 Processor Block Reference Guide

UG018 (v2.0) August 20, 2004

The following table shows the revision history for this document.

 

Version

Revision

 

 

 

09/16/02

1.0

Initial Embedded Development Kit (EDK) release.

 

 

 

09/02/03

1.1

Updated for EDK 6.1 release

 

 

 

04/26/04

DRAFT

Early Access release (DRAFT).

 

 

 

06/15/04

DRAFT

Second Early Access release (DRAFT).

 

 

 

08/20/04

2.0

Updated to include Virtex-4 functionality.

 

 

 

UG018 (v2.0) August 20, 2004

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PowerPC™ 405 Processor Block Reference Guide

 

1-800-255-7778

 

PowerPC™ 405 Processor Block Reference Guide

www.xilinx.com

UG018 (v2.0) August 20, 2004

1-800-255-7778

Table of Contents

Preface: About This Guide

Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Typographical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

General Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Chapter 1: Introduction to the PowerPC 405 Processor

PowerPC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

PowerPC Embedded-Environment Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

PowerPC 405 Software Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Privilege Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Address Translation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Register Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

PowerPC 405 Hardware Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Central-Processing Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Exception Handling Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Memory Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Instruction and Data Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Timer Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

PowerPC 405 Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

PowerPC 405 Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Chapter 2: Input/Output Interfaces

Signal Naming Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Clock and Power Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 CPM Interface I/O Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 CPM Interface I/O Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 System Design Considerations for Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

CPU Control Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 CPU Control Interface I/O Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 CPU Control Interface I/O Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Reset Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Reset Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Reset Interface I/O Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Reset Interface I/O Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Instruction-Side Processor Local Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

PowerPC™ 405 Processor Block Reference Guide

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Instruction-Side PLB Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Instruction-Side PLB I/O Signal Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Instruction-Side PLB Interface I/O Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . 51 Instruction-Side PLB Interface Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Data-Side Processor Local Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Data-Side PLB Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Data-Side PLB Interface I/O Signal Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Data-Side PLB Interface I/O Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Data-Side PLB Interface Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Device-Control Register Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Internal Device Control Register (DCR) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Virtex-II Pro and Virtex-II ProX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Virtex-4-FX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

External DCR Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 External DCR Bus Interface I/O Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 External DCR Bus Interface I/O Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 105 External DCR Bus Interface Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 External DCR Timing Consideration (Virtex-II Pro/ProX Only) . . . . . . . . . . . . . . . . 109

External Interrupt Controller Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 EIC Interface I/O Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 EIC Interface I/O Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

PPC405 JTAG Debug Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 JTAG Interface I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 JTAG Interface I/O Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 JTAG Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Connecting PPC405 JTAG Logic Directly to Programmable I/O . . . . . . . . . . . . . . . . 115 Connecting PPC405 JTAG Logic in Series with the Dedicated Device JTAG Logic 119 VHDL and Verilog Instantiation Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Debug Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Debug Interface I/O Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Debug Interface I/O Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Trace Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Trace Interface Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Trace Interface I/O Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Processor Version Register (PVR) Interface (Virtex-4-FX Only) . . . . . . . . . . . . . . 134 PVR Interface I/O Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 PVR Interface I/O Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Additional FPGA Specific Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Additional FPGA I/O Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Chapter 3: PowerPC 405 OCM Controller

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Comparison of Virtex-II Pro and Virtex-4 OCM Controllers . . . . . . . . . . . . . . . . . 140

Functional Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Common Features for DSOCM and ISOCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Features for Data-Side OCM (DSOCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Features for Instruction-Side OCM (ISOCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

OCM Controller Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

OCM DCR-Based Control Registers (Accessed Via DCR Instructions) . . . . . . . . . . . 143

DSOCM Controller Load/Store Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

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PowerPC™ 405 Processor Block Reference Guide

 

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ISOCM Controller Instruction Fetch Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 DSOCM Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 ISOCM Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 DCR Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 DSARC/ ISARC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 DSCNTL Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 ISCNTL Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Features Introduced in Virtex-4 and Comparison with Virtex-II Pro . . . . . . . . . . . . 161 DCR Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 DCR Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Timing Specification for Fixed Latency (Virtex-4 and Virtex-II Pro) . . . . . . . . . 169 Single-Cycle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Multi-Cycle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 ISOCM Instruction Fetching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Writing to ISBRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 DSOCM Data Load, Fixed Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 DSOCM Store, Fixed Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Timing Specification for Variable Latency (Virtex-4 DSOCM Controller Only) 177 DSOCM Data Load, Variable Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 DSOCM Data Store, Variable Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Application Notes and Reference Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Chapter 4: PowerPC 405 APU Controller

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

FCM Instruction Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Enabling the APU Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Instruction Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Instruction Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 APU Controller Pre-Defined Instruction Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 APU Controller User-Defined Instruction Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . 189 FCM Pre-Defined Instruction Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 FCM User-Defined Instruction Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 FCM Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 FCM Instruction Flushing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Execution Hazards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

APU Controller Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 General Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 UDI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 DCR Access to the Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Interface Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 APU Controller Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 APU Controller Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 APU Controller Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

FCM Interface Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Autonomous Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Blocking Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Non-Blocking Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 FCM Load Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

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FCM Store Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

FCM Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

FCM Decoding Using Decode Busy Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

Appendix A: RISCWatch and RISCTrace Interfaces

RISCWatch Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

RISCTrace Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Appendix B: Signal Summary

Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Appendix C: Processor Block Timing Model

Timing Parameter Tables and Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

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Preface

About This Guide

This guide serves as a technical reference describing the hardware interface to the PowerPC® 405 processor block. It contains information on input/output signals, timing relationships between signals, and the mechanisms software can use to control the interface operation. The document is intended for use by FPGA and system hardware designers and by system programmers who need to understand how certain operations affect hardware external to the processor.

Guide Contents

This manual contains the following chapters:

xChapter 1, “Introduction to the PowerPC 405 Processor,” provides an overview of the PowerPC embedded-environment architecture and the features supported by the PowerPC 405.

xChapter 2, “Input/Output Interfaces,” describes the interface signals into and out of the PowerPC 405 processor block. Where appropriate, timing diagrams are provided to assist in understanding the functional relationship between multiple signals.

xChapter 3, “PowerPC 405 OCM Controller,” describes the features, interface signals, timing specifications, and programming model for the PowerPC 405 on-chip memory (OCM) controller. The OCM controller serves as a dedicated interface between the block RAMs in the FPGA and OCM signals available on the embedded PowerPC 405 core.

xChapter 4, “PowerPC 405 APU Controller,” describes the Auxiliary Processor Unit controller, which allows the designer to extend the native PowerPC 405 instruction set with custom instructions that are executed by an FPGA Fabric Co-processor Module (FCM). The APU controller is available only for Virtex-4 family devices.

xAppendix A, “RISCWatch and RISCTrace Interfaces,” describes the interface requirements between the PowerPC 405 processor block and the RISCWatch and RISCTrace tools.

xAppendix B, “Signal Summary,” lists all PowerPC 405 interface signals in alphabetical order.

xAppendix C, “Processor Block Timing Model,” explains all of the timing parameters associated with the IBM PPC405 Processor Block.

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Preface: About This Guide

Additional Resources

For additional information, go to http://support.xilinx.com. The following table lists some of the resources you can access from this website. You can also directly access these resources using the provided URLs.

Resource

Description/URL

 

 

Tutorials

Tutorials covering Xilinx design flows, from design entry to

 

verification and debugging

 

http://support.xilinx.com/support/techsup/tutorials/index.htm

 

 

Answer Browser

Database of Xilinx solution records

 

http://support.xilinx.com/xlnx/xil_ans_browser.jsp

 

 

Application Notes

Descriptions of device-specific design techniques and approaches

 

http://support.xilinx.com/apps/appsweb.htm

 

 

Data Sheets

Device-specific information on Xilinx device characteristics,

 

including readback, boundary scan, configuration, length count,

 

and debugging

 

http://support.xilinx.com/xlnx/xweb/xil_publications_index.jsp

 

 

Problem Solvers

Interactive tools that allow you to troubleshoot your design issues

 

http://support.xilinx.com/support/troubleshoot/psolvers.htm

 

 

Tech Tips

Latest news, design tips, and patch information for the Xilinx

 

design environment

 

http://www.support.xilinx.com/xlnx/xil_tt_home.jsp

 

 

The following documents contain additional information of potential interest to readers of this manual:

xXILINX PowerPC Processor Reference Guide

xXILINX Virtex-II Pro Platform FPGA Handbook

Conventions

This document uses the following conventions. An example illustrates each convention.

Typographical

The following typographical conventions are used in this document:

Convention

Meaning or Use

Example

 

 

 

 

Messages, prompts, and

 

Courier font

program files that the system

speed grade: - 100

 

displays

 

 

 

 

Courier bold

Literal commands that you

ngdbuild design_name

enter in a syntactical statement

 

 

 

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Convention

Meaning or Use

Example

 

 

 

 

Commands that you select

File o Open

Helvetica bold

from a menu

 

 

 

 

 

 

 

Keyboard shortcuts

Ctrl+C

 

 

 

 

Variables in a syntax

 

 

statement for which you must

ngdbuild design_name

 

supply values

 

 

 

 

 

 

See the Development System

Italic font

References to other manuals

Reference Guide for more

 

 

information.

 

 

 

 

 

If a wire is drawn so that it

 

Emphasis in text

overlaps the pin of a symbol,

 

 

the two nets are not connected.

 

 

 

 

An optional entry or

 

Square brackets [ ]

parameter. However, in bus

ngdbuild [option_name]

specifications, such as

design_name

 

 

bus[7:0], they are required.

 

 

 

 

Braces { }

A list of items from which you

lowpwr ={on|off}

must choose one or more

 

 

 

 

 

Vertical bar |

Separates items in a list of

lowpwr ={on|off}

choices

 

 

 

 

 

Vertical ellipsis

 

IOB #1: Name = QOUT’

Repetitive material that has

IOB #2: Name = CLKIN’

.

.

.

been omitted

.

.

 

 

.

 

 

 

 

 

Horizontal ellipsis . . .

Repetitive material that has

allow block block_name

 

been omitted

loc1 loc2 ... locn;

 

 

 

Online Document

The following conventions are used in this document:

Convention

Meaning or Use

Example

 

 

 

 

Cross-reference link to a

See the section “Additional

 

Resources” for details.

Blue text

location in the current

Refer to “Title Formats” in

 

document

 

Chapter 1 for details.

 

 

 

 

 

Red text

Reference to a location in

See Figure 2-5 in the Virtex-II

another document

Handbook.

 

 

 

 

Blue, underlined text

Hyperlink to a website (URL)

Go to http://www.xilinx.com

for the latest speed files.

 

 

 

 

 

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Preface: About This Guide

General Conventions

Table 1-1 lists the general notational conventions used throughout this document.

Table 1-1: General Notational Conventions

Convention

Definition

 

 

mnemonic

Instruction mnemonics are shown in lower-case bold.

 

 

variable

Variable items are shown in italic.

 

 

ActiveLow

An overbar indicates an active-low signal.

 

 

n

A decimal number

 

 

0xn

A hexadecimal number

 

 

0bn

A binary number

 

 

OBJECTb

A single bit in any object (a register, an instruction, an

 

address, or a field) is shown as a subscripted number or

 

name

 

 

OBJECTb:b

A range of bits in any object (a register, an instruction,

 

an address, or a field)

 

 

OBJECTb,b, . . .

A list of bits in any object (a register, an instruction, an

 

address, or a field)

 

 

REGISTER[FIELD]

Fields within any register are shown in square brackets

 

 

REGISTER[FIELD, FIELD . . .]

A list of fields in any register

REGISTER[FIELD:FIELD]

A range of fields in any register

 

 

Registers

Table 1-2 lists the PowerPC 405 registers used in this document and their descriptive names.

Table 1-2: PowerPC 405 Registers

Register

Descriptive Name

 

 

CCR0

Core-configuration register 0

 

 

DBCRn

Debug-control register n

 

 

DBSR

Debug-status register

 

 

ESR

Exception-syndrome register

 

 

MSR

Machine-state register

 

 

PIT

Programmable-interval timer

 

 

TBL

Time-base lower

 

 

TBU

Time-base upper

 

 

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Table 1-2: PowerPC 405 Registers (Continued)

Register

Descriptive Name

 

 

TCR

Timer-control register

 

 

TSR

Timer-status register

 

 

Terms

active

As applied to signals, this term indicates a signal is in a state

 

that causes an action to occur in the receiving device, or

 

indicates an action occurred in the sending device. An active-

 

high signal drives a logic 1 when active. An active-low signal

 

drives a logic 0 when active.

assert

As applied to signals, this term indicates a signal is driven to its

 

active state.

atomic access

A memory access that attempts to read from and write to the

 

same address uninterrupted by other accesses to that address.

 

The term refers to the fact that such transactions are indivisible.

big endian

A memory byte ordering where the address of an item

 

corresponds to the most-significant byte.

Book-E

An version of the PowerPC architecture designed specifically

 

for embedded applications.

cache block

Synonym for cache line.

cache line

A portion of a cache array that contains a copy of contiguous

 

system-memory addresses. Cache lines are 32-bytes long and

 

aligned on a 32-byte address.

cache set

Synonym for congruence class.

clear

To write a bit value of 0.

clock

Unless otherwise specified, this term refers to the PowerPC 405

 

processor clock.

congruence class

A collection of cache lines with the same index.

cycle

The time between two successive rising edges of the associated

 

clock.

dead cycle

A cycle in which no useful activity occurs on the associated

 

interface.

deassert

As applied to signals, this term indicates a signal is driven to its

 

inactive state.

dirty

An indication that cache information is more recent than the

 

copy in memory.

doubleword

Eight bytes, or 64 bits.

effective address

The untranslated memory address as seen by a program.

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exception

An abnormal event or condition that requires the processor’s

 

attention. They can be caused by instruction execution or an

 

external device. The processor records the occurrence of an

 

exception and they often cause an interrupt to occur.

fill buffer

A buffer that receives and sends data and instructions between

 

the processor and PLB. It is used when cache misses occur and

 

when access to non-cacheable memory occurs.

flush

A cache operation that involves writing back a modified entry

 

to memory, followed by an invalidation of the entry.

GB

Gigabyte, or one-billion bytes.

halfword

Two bytes, or 16 bits.

hit

An indication that requested information exists in the accessed

 

cache array, the associated fill buffer, or on the corresponding

 

OCM interface.

inactive

As applied to signals, this term indicates a signal is in a state

 

that does not cause an action to occur, nor does it indicate an

 

action occurred. An active-high signal drives a logic 0 when

 

inactive. An active-low signal drives a logic 1 when inactive.

interrupt

The process of stopping the currently executing program so that

 

an exception can be handled.

invalidate

A cache or TLB operation that causes an entry to be marked as

 

invalid. An invalid entry can be subsequently replaced.

KB

Kilobyte, or one-thousand bytes.

line buffer

A buffer located in the cache array that can temporarily hold the

 

contents of an entire cache line. It is loaded with the contents of

 

a cache line when a cache hit occurs.

line fill

A transfer of the contents of the instruction or data line buffer

 

into the appropriate cache.

line transfer

A transfer of an aligned, sequentially addressed 4-word or 8-

 

word quantity (instructions or data) across the PLB interface.

 

The transfer can be from the PLB slave (read) or to the PLB slave

 

(write).

little endian

A memory byte ordering where the address of an item

 

corresponds to the least-significant byte.

logical address

Synonym for effective address.

MB

Megabyte, or one-million bytes.

memory

Collectively, cache memory and system memory.

miss

An indication that requested information does not exist in the

 

accessed cache array, the associated fill buffer, or on the

 

corresponding OCM interface.

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OEA

The PowerPC operating-environment architecture, which

 

defines the memory-management model, supervisor-level

 

registers and instructions, synchronization requirements, the

 

exception model, and the time-base resources as seen by

 

supervisor programs.

on chip

In system-on-chip implementations, this indicates on the same

 

FPGA chip as the processor core, but external to the processor

 

core.

pending

As applied to interrupts, this indicates that an exception

 

occurred, but the interrupt is disabled. The interrupt occurs

 

when it is later enabled.

physical address

The address used to access physically-implemented memory.

 

This address can be translated from the effective address. When

 

address translation is not used, this address is equal to the

 

effective address.

PLB

Processor local bus.

privileged mode

The operating mode typically used by system software.

 

Privileged operations are allowed and software can access all

 

registers and memory.

problem state

Synonym for user mode.

process

A program (or portion of a program) and any data required for

 

the program to run.

real address

Synonym for physical address.

scalar

Individual data objects and instructions. Scalars are of arbitrary

 

size.

set

To write a bit value of 1.

sleep

A state in which the PowerPC 405 processor clock is prevented

 

from toggling. The execution state of the PowerPC 405 does not

 

change when in the sleep state.

sticky

A bit that can be set by software, but cleared only by the

 

processor. Alternatively, a bit that can be cleared by software,

 

but set only by the processor.

string

A sequence of consecutive bytes.

supervisor state

Synonym for privileged mode.

system memory

Physical memory installed in a computer system external to the

 

processor core, such RAM, ROM, and flash.

tag

As applied to caches, a set of address bits used to uniquely

 

identify a specific cache line within a congruence class. As

 

applied to TLBs, a set of address bits used to uniquely identify

 

a specific entry within the TLB.

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UISA

The PowerPC user instruction-set architecture, which defines

 

the base user-level instruction set, registers, data types, the

 

memory model, the programming model, and the exception

 

model as seen by user programs.

user mode

The operating mode typically used by application software.

 

Privileged operations are not allowed in user mode, and

 

software can access a restricted set of registers and memory.

VEA

The PowerPC virtual-environment architecture, which defines

 

a multi-access memory model, the cache model, cache-control

 

instructions, and the time-base resources as seen by user

 

programs.

virtual address

An intermediate address used to translate an effective address

 

into a physical address. It consists of a process ID and the

 

effective address. It is only used when address translation is

 

enabled.

wake up

The transition of the PowerPC 405 out of the sleep state. The

 

PowerPC 405 processor clock begins toggling and the execution

 

state of the PowerPC 405 advances from that of the sleep state.

word

Four bytes, or 32 bits.

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Chapter 1

Introduction to the

PowerPC 405 Processor

The PowerPC 405 is a 32-bit implementation of the PowerPC embedded-environment architecture that is derived from the PowerPC architecture. Specifically, the PowerPC 405 is an embedded PowerPC 405D5 (for Virtex-II Pro) or 405F6 (for Virtex-4) processor core. The term processor block is used throughout this document to refer to the combination of a PPC405D5 or PPC405F6 core, on-chip memory logic (OCM), an APU controller (Virtex-4 only), and the gasket logic and interface.

The PowerPC architecture provides a software model that ensures compatibility between implementations of the PowerPC family of microprocessors. The PowerPC architecture defines parameters that guarantee compatible processor implementations at the application-program level, allowing broad flexibility in the development of derivative PowerPC implementations that meet specific market requirements.

This chapter provides an overview of the PowerPC architecture and an introduction to the features of the PowerPC 405 core. The following topics are included:

x“PowerPC Architecture”

x“PowerPC 405 Software Features”

x“PowerPC 405 Hardware Organization”

x“PowerPC 405 Performance”

PowerPC Architecture

The PowerPC architecture is a 64-bit architecture with a 32-bit subset. The various features of the PowerPC architecture are defined at three levels. This layering provides flexibility by allowing degrees of software compatibility across a wide range of implementations. For example, an implementation such as an embedded controller can support the user instruction set, but not the memory management, exception, and cache models where it might be impractical to do so.

The three levels of the PowerPC architecture are defined in Table 1-1.

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Chapter 1: Introduction to the PowerPC 405 Processor

Table 1-1: Three Levels of PowerPC Architecture

User Instruction-Set Architecture

Virtual Environment Architecture

 

Operating Environment

(UISA)

(VEA)

 

Architecture (OEA)

 

 

 

 

x Defines the architecture level to

x Defines additional user-level

x

Defines supervisor-level

which user-level (sometimes

functionality that falls outside

 

resources typically required by

referred to as problem state)

typical user-level software

 

an operating system

software should conform

requirements

x

Defines the memory-

x Defines the base user-level

x Describes the memory model for

 

management model, supervisor-

instruction set, user-level

an environment in which

 

level registers, synchronization

registers, data types, floating-

multiple devices can access

 

requirements, and the exception

point memory conventions,

memory

 

model

exception model as seen by user

x Defines aspects of the cache

x Defines the time-base resources

programs, memory model, and

model and cache-control

 

from a supervisor-level

the programming model

instructions

 

perspective

 

x Defines the time-base resources

 

 

 

from a user-level perspective

 

 

 

x

 

 

Note: All PowerPC implementations

Note: Implementations that conform to

Note: Implementations that conform to

adhere to the UISA.

the VEA level are guaranteed to conform

the OEA level are guaranteed to conform

 

to the UISA level.

to the UISA and VEA levels.

 

 

 

 

The PowerPC architecture requires that all PowerPC implementations adhere to the UISA, offering compatibility among all PowerPC application programs. However, different versions of the VEA and OEA are permitted.

Embedded applications written for the PowerPC 405 are compatible with other PowerPC implementations. Privileged software generally is not compatible. The migration of privileged software from the PowerPC architecture to the PowerPC 405 is in many cases straightforward because of the simplifications made by the PowerPC embeddedenvironment architecture. Refer to the PowerPC Processor Reference Guide for more information on programming the PowerPC 405.

PowerPC Embedded-Environment Architecture

The PowerPC 405 is an implementation of the PowerPC embedded-environment architecture. This architecture is optimized for embedded controllers and is a forerunner to the PowerPC Book-E architecture. The PowerPC embedded-environment architecture provides an alternative definition for certain features specified by the PowerPC VEA and OEA. Implementations that adhere to the PowerPC embedded-environment architecture also adhere to the PowerPC UISA. PowerPC embedded-environment processors are 32-bit only implementations and thus do not include the special 64-bit extensions to the PowerPC UISA. Also, floating-point support can be provided either in hardware or software by PowerPC embedded-environment processors.

The following are features of the PowerPC embedded-environment architecture:

xMemory management optimized for embedded software environments.

xCache-management instructions for optimizing performance and memory control in complex applications that are graphically and numerically intensive.

xStorage attributes for controlling memory-system behavior.

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xSpecial-purpose registers for controlling the use of debug resources, timer resources, interrupts, real-mode storage attributes, memory-management facilities, and other architected processor resources.

xA device-control-register address space for managing on-chip peripherals such as memory controllers.

xA dual-level interrupt structure and interrupt-control instructions.

xMultiple timer resources.

xDebug resources that enable hardware-debug and software-debug functions such as instruction breakpoints, data breakpoints, and program single-stepping.

Virtual Environment

The virtual environment defines architectural features that enable application programs to create or modify code, to manage storage coherency, and to optimize memory-access performance. It defines the cache and memory models, the timekeeping resources from a user perspective, and resources that are accessible in user mode but are primarily used by system-library routines. The following summarizes the virtual-environment features of the PowerPC embedded-environment architecture:

xStorage model:

i Storage-control instructions as defined in the PowerPC virtual-environment architecture. These instructions are used to manage instruction caches and data caches, and for synchronizing and ordering instruction execution.

iStorage attributes for controlling memory-system behavior. These are: writethrough, cacheability, memory coherence (optional), guarded, and endian.

iOperand-placement requirements and their effect on performance.

x The time-base function as defined by the PowerPC virtual-environment architecture, for user-mode read access to the 64-bit time base.

Operating Environment

The operating environment describes features of the architecture that enable operating systems to allocate and manage storage, to handle errors encountered by application programs, to support I/O devices, and to provide operating-system services. It specifies the resources and mechanisms that require privileged access, including the memoryprotection and address-translation mechanisms, the exception-handling model, and privileged timer resources. Table 1-2 summarizes the operating-environment features of the PowerPC embedded-environment architecture.

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Table 1-2: OEA Features of the PowerPC Embedded-Environment Architecture

Operating

Features

Environment

 

 

 

Register model

x Privileged special-purpose registers (SPRs) and instructions for accessing those

 

registers

 

x Device control registers (DCRs) and instructions for accessing those registers

 

 

Storage model

x Privileged cache-management instructions

 

x Storage-attribute controls

 

x Address translation and memory protection

 

x Privileged TLB-management instructions

 

 

Exception model

x Dual-level interrupt structure supporting various exception types

 

x Specification of interrupt priorities and masking

 

x Privileged SPRs for controlling and handling exceptions

 

x Interrupt-control instructions

 

x Specification of how partially executed instructions are handled when an interrupt

 

occurs

 

 

Debug model

x Privileged SPRs for controlling debug modes and debug events

 

x Specification for seven types of debug events

 

x Specification for allowing a debug event to cause a reset

 

x The ability of the debug mechanism to freeze the timer resources

 

 

Time-keeping model

x 64-bit time base

 

x 32-bit decrementer (the programmable-interval timer)

 

x Three timer-event interrupts:

 

i Programmable-interval timer (PIT)

 

i Fixed-interval timer (FIT)

 

i Watchdog timer (WDT)

 

x Privileged SPRs for controlling the timer resources

 

x The ability to freeze the timer resources using the debug mechanism

 

 

Synchronization

x Requirements for special registers and the TLB

requirements

x Requirements for instruction fetch and for data access

 

x Specifications for context synchronization and execution synchronization

 

 

Reset and initialization

x Specification for two internal mechanisms that can cause a reset:

requirements

i Debug-control register (DBCR)

 

i Timer-control register (TCR)

 

x Contents of processor resources after a reset

 

x The software-initialization requirements, including an initialization code example

 

 

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PowerPC 405 Software Features

The PowerPC 405 processor core is an implementation of the PowerPC embeddedenvironment architecture. The processor provides fixed-point embedded applications with high performance at low power consumption. It is compatible with the PowerPC UISA. Much of the PowerPC 405 VEA and OEA support is also available in implementations of the PowerPC Book-E architecture. Key software features of the PowerPC 405 include:

xA fixed-point execution unit fully compliant with the PowerPC UISA:

i 32-bit architecture, containing thirty-two 32-bit general purpose registers (GPRs).

xPowerPC embedded-environment architecture extensions providing additional support for embedded-systems applications:

i True little-endian operation

i Flexible memory management

i Multiply-accumulate instructions for computationally intensive applications i Enhanced debug capabilities

i 64-bit time base

i 3 timers: programmable interval timer (PIT), fixed interval timer (FIT), and watchdog timer (all are synchronous with the time base)

xPerformance-enhancing features, including: i Static branch prediction

i Five-stage pipeline with single-cycle execution of most instructions, including loads and stores

i Multiply-accumulate instructions

i Hardware multiply/divide for faster integer arithmetic (4-cycle multiply, 35-cycle divide)

i Enhanced string and multiple-word handling

i Support for unaligned loads and unaligned stores to cache arrays, main memory, and on-chip memory (OCM)

i Minimized interrupt latency

xIntegrated instruction-cache:

i 16 KB, 2-way set associative

i Eight words (32 bytes) per cache line i Fetch line buffer

i Instruction-fetch hits are supplied from the fetch line buffer

i Programmable prefetch of next-sequential line into the fetch line buffer

i Programmable prefetch of non-cacheable instructions: full line (eight words) or half line (four words)

i Non-blocking during fetch line fills

xIntegrated data-cache:

i 16 KB, 2-way set associative

i Eight words (32 bytes) per cache line i Read and write line buffers

i Load and store hits are supplied from/to the line buffers

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iWrite-back and write-through support

iProgrammable load and store cache line allocation

iOperand forwarding during cache line fills

iNon-blocking during cache line fills and flushes

x Support for on-chip memory (OCM) that can provide memory-access performance identical to a cache hit

xFlexible memory management:

i Translation of the 4 GB logical-address space into the physical-address space

iIndependent control over instruction translation and protection, and data translation and protection

iPage-level access control using the translation mechanism

iSoftware control over the page-replacement strategy

iWrite-through, cacheability, user-defined 0, guarded, and endian (WIU0GE) storage-attribute control for each virtual-memory region

iWIU0GE storage-attribute control for thirty-two 128 MB regions in real mode

iAdditional protection control using zones

x Enhanced debug support with logical operators:

iFour instruction-address compares

iTwo data-address compares

iTwo data-value compares

iJTAG instruction for writing into the instruction cache

iForward and backward instruction tracing

xAdvanced power management support

The following sections describe the software resources available in the PowerPC 405. Refer to the PowerPC Processor Reference Guide for more information on using these resources.

Privilege Modes

Software running on the PowerPC 405 can do so in one of two privilege modes: privileged and user.

Privileged Mode

Privileged mode allows programs to access all registers and execute all instructions supported by the processor. Normally, the operating system and low-level device drivers operate in this mode.

User Mode

User mode restricts access to some registers and instructions. Normally, application programs operate in this mode.

Address Translation Modes

The PowerPC 405 also supports two modes of address translation: real and virtual.

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Real Mode

In real mode, programs address physical memory directly.

Virtual Mode

In virtual mode, programs address virtual memory and virtual-memory addresses are translated by the processor into physical-memory addresses. This allows programs to access much larger address spaces than might be implemented in the system.

Addressing Modes

Whether the PowerPC 405 is running in real mode or virtual mode, data addressing is supported by the load and store instructions using one of the following addressing modes:

xRegister-indirect with immediate index — A base address is stored in a register, and a displacement from the base address is specified as an immediate value in the instruction.

xRegister-indirect with index — A base address is stored in a register, and a displacement from the base address is stored in a second register.

xRegister indirect — The data address is stored in a register.

Instructions that use the two indexed forms of addressing also allow for automatic updates to the base-address register. With these instruction forms, the new data address is calculated, used in the load or store data access, and stored in the base-address register.

With sequential instruction execution, the next-instruction address is calculated by adding four bytes to the current-instruction address. In the case of branch instructions, the nextinstruction address is determined using one of four branch-addressing modes:

xBranch to relative — The next-instruction address is at a location relative to the current-instruction address.

xBranch to absolute — The next-instruction address is at an absolute location in memory.

xBranch to link register — The next-instruction address is stored in the link register.

xBranch to count register — The next-instruction address is stored in the count register.

Data Types

PowerPC 405 instructions support byte, halfword, and word operands. Multiple-word operands are supported by the load/store multiple instructions and byte strings are supported by the load/store string instructions. Integer data are either signed or unsigned, and signed data is represented using two’s-complement format.

The address of a multi-byte operand is determined using the lowest memory address occupied by that operand. For example, if the four bytes in a word operand occupy addresses 4, 5, 6, and 7, the word address is 4. The PowerPC 405 supports both big-endian (an operand’s most significant byte is at the lowest memory address) and little-endian (an operand’s least significant byte is at the lowest memory address) addressing.

Register Set Summary

Figure 1-1 shows the registers contained in the PowerPC 405. Descriptions of the registers are in the following sections.

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Privileged Registers

User Registers

General-Purpose Registers

r0

r1

.

.

.

r31

Condition Register

CR

Fixed-Point Exception Register

XER

Link Register

LR

Count Register

CTR

User-SPR General-Purpose

Registers

USPRG0

SPR General-Purpose

Registers (read only)

SPRG4

SPRG5

SPRG6

SPRG7

Time-Base Registers

(read only)

TBU

TBL

Machine-State Register

MSR

Core-Configuration Register

CCR0

SPR General-Purpose

Registers

SPRG0

SPRG1

SPRG2

SPRG3

SPRG4

SPRG5

SPRG6

SPRG7

Exception-Handling Registers

EVPR

ESR

DEAR

SRR0

SRR1

SRR2

SRR3

Memory-Management

Registers

PID

ZPR

Figure 1-1: PowerPC 405 Registers

General-Purpose Registers

Storage-Attribute Control

Registers

DCCR

DCWR

ICCR

SGR

SLER

SU0R

Debug Registers

DBSR

DBCR0

DBCR1

DAC1

DAC2

DVC1

DVC2

IAC1

IAC2

IAC3

IAC4

ICDBR

Timer Registers

TCR

TSR

PIT

Processor-Version Register

PVR

Time-Base Registers

TBU

TBL

UG018_36_102401

The processor contains thirty-two 32-bit general-purpose registers (GPRs), identified as r0 through r31. The contents of the GPRs are read from memory using load instructions and written to memory using store instructions. Computational instructions often read operands from the GPRs and write their results in GPRs. Other instructions move data between the GPRs and other registers. GPRs can be accessed by all software.

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Special-Purpose Registers

The processor contains a number of 32-bit special-purpose registers (SPRs). SPRs provide access to additional processor resources, such as the count register, the link register, debug resources, timers, interrupt registers, and others. Most SPRs are accessed only by privileged software, but a few, such as the count register and link register, are accessed by all software.

Machine-State Register

The 32-bit machine-state register (MSR) contains fields that control the operating state of the processor. This register can be accessed only by privileged software.

Condition Register

The 32-bit condition register (CR) contains eight 4-bit fields, CR0–CR7. The values in the CR fields can be used to control conditional branching. Arithmetic instructions can set CR0 and compare instructions can set any CR field. Additional instructions are provided to perform logical operations and tests on CR fields and bits within the fields. The CR can be accessed by all software.

Device Control Registers

The 32-bit device control registers (not shown) are used to configure, control, and report status for various external devices that are not part of the PowerPC 405 processor. The OCM controllers are examples of devices that contain DCRs. Although the DCRs are not part of the PowerPC 405 implementation, they are accessed using the mtdcr and mfdcr instructions. The DCRs can be accessed only by privileged software.

PowerPC 405 Hardware Organization

As shown in Figure 1-2, the PowerPC 405 processor contains the following elements:

xA 5-stage pipeline consisting of fetch, decode, execute, write-back, and load writeback stages

xA virtual-memory-management unit that supports multiple page sizes and a variety of storage-protection attributes and access-control options

xSeparate instruction-cache and data-cache units

xDebug support, including a JTAG interface

xThree programmable timers

The following sections provide an overview of each element. Refer to the PowerPC Processor Reference Guide for more information on how software interacts with these elements.

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PLB Master

Instruction

 

 

 

 

 

Read Interface

OCM

 

 

 

 

 

 

 

 

 

MMU

 

CPU

 

 

 

I-Cache I-Cache

 

Fetch

 

 

 

 

Array

Controller

Instruction

and

3-Element

 

 

 

 

 

Shadow-TLB

Decode

Fetch Queue

Timers

Instruction-Cache

 

(4-Entry)

Logic

 

 

 

 

Unit

 

 

 

 

 

 

 

 

 

 

Unified TLB

 

 

 

Timers

Cache Units

 

 

 

 

 

and

 

(64-Entry)

 

 

 

 

 

 

 

 

 

 

Debug

 

 

 

 

 

 

 

Data-Cache

 

 

Execute Unit

 

 

 

Unit

 

Data

 

 

Debug

 

 

 

Shadow-TLB

 

 

 

 

 

 

 

 

 

 

 

Logic

D-Cache

D-Cache

(8-Entry)

32x32

 

 

 

ALU

MAC

 

 

Array

Controller

 

GPR

 

 

 

 

 

 

 

PLB Master

PLB Master

Data

External-Interrupt

 

Instruction

Read Interface

Write Interface

OCM

Controller Interface

JTAG

Trace

 

 

 

 

 

 

 

 

UG018_35_102401

Figure 1-2: PowerPC 405 Organizationa

a. Figure 1-2 is specific to PPC405D5.

Central-Processing Unit

The PowerPC 405 central-processing unit (CPU) implements a 5-stage instruction pipeline consisting of fetch, decode, execute, write-back, and load write-back stages.

The fetch and decode logic sends a steady flow of instructions to the execute unit. All instructions are decoded before they are forwarded to the execute unit. Instructions are queued in the fetch queue if execution stalls. The fetch queue consists of three elements: two prefetch buffers and a decode buffer. If the prefetch buffers are empty instructions flow directly to the decode buffer.

Up to two branches are processed simultaneously by the fetch and decode logic. If a branch cannot be resolved prior to execution, the fetch and decode logic predicts how that branch is resolved, causing the processor to speculatively fetch instructions from the predicted path. Branches with negative-address displacements are predicted as taken, as are branches that do not test the condition register or count register. The default prediction can be overridden by software at assembly or compile time.

The PowerPC 405 has a single-issue execute unit containing the general-purpose register file (GPR), arithmetic-logic unit (ALU), and the multiply-accumulate unit (MAC). The GPRs consist of thirty-two 32-bit registers that are accessed by the execute unit using three

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read ports and two write ports. During the decode stage, data is read out of the GPRs for use by the execute unit. During the write-back stage, results are written to the GPR. The use of five read/write ports on the GPRs allows the processor to execute load/store operations in parallel with ALU and MAC operations.

The execute unit supports all 32-bit PowerPC UISA integer instructions in hardware, and is compliant with the PowerPC embedded-environment architecture specification. Floatingpoint operations are not supported.

The MAC unit supports implementation-specific multiply-accumulate instructions and multiply-halfword instructions. MAC instructions operate on either signed or unsigned 16-bit operands, and they store their results in a 32-bit GPR. These instructions can produce results using either modulo arithmetic or saturating arithmetic. All MAC instructions have a single cycle throughput.

Exception Handling Logic

Exceptions are divided into two classes: critical and noncritical. The PowerPC 405 CPU services exceptions caused by error conditions, the internal timers, debug events, and the external interrupt controller (EIC) interface. Across the two classes, a total of 19 possible exceptions are supported, including the two provided by the EIC interface.

Each exception class has its own pair of save/restore registers. SRR0 and SRR1 are used for noncritical interrupts, and SRR2 and SRR3 are used for critical interrupts. The exceptionreturn address and the machine state are written to these registers when an exception occurs, and they are automatically restored when an interrupt handler exits using the return-from-interrupt (rfi) or return-from critical-interrupt (rfci) instruction. Use of separate save/restore registers allows the PowerPC 405 to handle critical interrupts independently of noncritical interrupts.

Memory Management Unit

The PowerPC 405 supports 4 GB of flat (non-segmented) address space. The memorymanagement unit (MMU) provides address translation, protection functions, and storageattribute control for this address space. The MMU supports demand-paged virtual memory using multiple page sizes of 1 KB, 4 KB, 16 KB, 64 KB, 256 KB, 1 MB, 4 MB and 16 MB. Multiple page sizes can improve memory efficiency and minimize the number of TLB misses. When supported by system software, the MMU provides the following functions:

xTranslation of the 4 GB logical-address space into a physical-address space.

xIndependent enabling of instruction translation and protection from that of data translation and protection.

xPage-level access control using the translation mechanism.

xSoftware control over the page-replacement strategy.

xAdditional protection control using zones.

xStorage attributes for cache policy and speculative memory-access control.

The translation look-aside buffer (TLB) is used to control memory translation and protection. Each one of its 64 entries specifies a page translation. It is fully associative, and can simultaneously hold translations for any combination of page sizes. To prevent TLB contention between data and instruction accesses, a 4-entry instruction and an 8-entry data shadow-TLB are maintained by the processor transparently to software.

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Software manages the initialization and replacement of TLB entries. The PowerPC 405 includes instructions for managing TLB entries by software running in privileged mode. This capability gives significant control to system software over the implementation of a page replacement strategy. For example, software can reduce the potential for TLB thrashing or delays associated with TLB-entry replacement by reserving a subset of TLB entries for globally accessible pages or critical pages.

Storage attributes are provided to control access of memory regions. When memory translation is enabled, storage attributes are maintained on a page basis and read from the TLB when a memory access occurs. When memory translation is disabled, storage attributes are maintained in storage-attribute control registers. A zone-protection register (ZPR) is provided to allow system software to override the TLB access controls without requiring the manipulation of individual TLB entries. For example, the ZPR can provide a simple method for denying read access to certain application programs.

Instruction and Data Caches

The PowerPC 405 accesses memory through the instruction-cache unit (ICU) and datacache unit (DCU). Each cache unit includes a PLB-master interface, cache arrays, and a cache controller. Hits into the instruction cache and data cache appear to the CPU as singlecycle memory accesses. Cache misses are handled as requests over the PLB bus to another PLB device, such as an external-memory controller.

The PowerPC 405 implements separate instruction-cache and data-cache arrays. Each is 16 KB in size, is two-way set-associative, and operates using 8 word (32 byte) cache lines. The caches are non-blocking, allowing the PowerPC 405 to overlap instruction execution with reads over the PLB (when cache misses occur).

The cache controllers replace cache lines according to a least-recently used (LRU) replacement policy. When a cache line fill occurs, the most-recently accessed line in the cache set is retained and the other line is replaced. The cache controller updates the LRU during a cache line fill.

The ICU supplies up to two instructions every cycle to the fetch and decode unit. The ICU can also forward instructions to the fetch and decode unit during a cache line fill, minimizing execution stalls caused by instruction-cache misses. When the ICU is accessed, four instructions are read from the appropriate cache line and placed temporarily in a line buffer. Subsequent ICU accesses check this line buffer for the requested instruction prior to accessing the cache array. This allows the ICU cache array to be accessed as little as once every four instructions, significantly reducing ICU power consumption.

The DCU can independently process load/store operations and cache-control instructions. The DCU can also dynamically reprioritize PLB requests to reduce the length of an execution stall. For example, if the DCU is busy with a low-priority request and a subsequent storage operation requested by the CPU is stalled, the DCU automatically increases the priority of the current (low-priority) request. The current request is thus finished sooner, allowing the DCU to process the stalled request sooner. The DCU can forward data to the execute unit during a cache line fill, further minimizing execution stalls caused by data-cache misses.

Additional features allow programmers to tailor data-cache performance to a specific application. The DCU can function in write-back or write-through mode, as determined by the storage-control attributes. Loads and stores that do not allocate cache lines can also be specified. Inhibiting certain cache line fills can reduce potential pipeline stalls and unwanted external-bus traffic.

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Timer Resources

The PowerPC 405 contains a 64-bit time base and three timers. The time base is incremented synchronously using the CPU clock or an external clock source. The three timers are incremented synchronously with the time base. The three timers supported by the PowerPC 405 are:

xProgrammable Interval Timer

xFixed Interval Timer

xWatchdog Timer

Programmable Interval Timer

The programmable interval timer (PIT) is a 32-bit register that is decremented at the time-base increment frequency. The PIT register is loaded with a delay value. When the PIT count reaches 0, a PIT interrupt occurs. Optionally, the PIT can be programmed to automatically reload the last delay value and begin decrementing again.

Fixed Interval Timer

The fixed interval timer (FIT) causes an interrupt when a selected bit in the time-base register changes from 0 to 1. Programmers can select one of four predefined bits in the time-base for triggering a FIT interrupt.

Watchdog Timer

The watchdog timer causes a hardware reset when a selected bit in the time-base register changes from 0 to 1. Programmers can select one of four predefined bits in the time-base for triggering a reset, and the type of reset can be defined by the programmer.

Debug

The PowerPC 405 debug resources include special debug modes that support the various types of debugging used during hardware and software development. These are:

xInternal-debug mode for use by ROM monitors and software debuggers

xExternal-debug mode for use by JTAG debuggers

xDebug-wait mode, which allows the servicing of interrupts while the processor appears to be stopped

xReal-time trace mode, which supports event triggering for real-time tracing

Debug events are supported that allow developers to manage the debug process. Debug modes and debug events are controlled using debug registers in the processor. The debug registers are accessed either through software running on the processor or through the JTAG port.

The debug modes, events, controls, and interfaces provide a powerful combination of debug resources for hardware and software development tools.

PowerPC 405 Interfaces

The PowerPC 405 provides the following set of interfaces that support the attachment of cores and user logic:

xProcessor local bus interface

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xDevice control register interface

xClock and power management interface

xJTAG port interface

xOn-chip interrupt controller interface

xOn-chip memory controller interface

Processor Local Bus

The processor local bus (PLB) interface provides a 32-bit address and three 64-bit data buses attached to the instruction-cache and data-cache units. Two of the 64-bit buses are attached to the data-cache unit, one supporting read operations and the other supporting write operations. The third 64-bit bus is attached to the instruction-cache unit to support instruction fetching.

Device Control Register

The device control register (DCR) bus interface supports the attachment of on-chip registers for device control. Software can access these registers using the mfdcr and mtdcr instructions.

Clock and Power Management

The clock and power-management interface supports several methods of clock distribution and power management.

JTAG Port

The JTAG port interface supports the attachment of external debug tools. Using the JTAG test-access port, a debug tool can single-step the processor and examine internal-processor state to facilitate software debugging.

On-Chip Interrupt Controller

The on-chip interrupt controller interface is an external interrupt controller that combines asynchronous interrupt inputs from on-chip and off-chip sources and presents them to the core using a pair of interrupt signals (critical and noncritical). Asynchronous interrupt sources can include external signals, the JTAG and debug units, and any other on-chip peripherals.

On-Chip Memory Controller

An on-chip memory (OCM) interface supports the attachment of additional memory to the instruction and data caches that can be accessed at performance levels matching the cache arrays.

PowerPC 405 Performance

The PowerPC 405 executes instructions at sustained speeds approaching one cycle per instruction. Table 1-3 lists the typical execution speed (in processor cycles) of the instruction classes supported by the PowerPC 405.

Instructions that access memory (loads and stores) consider only the “first order” effects of cache misses. The performance penalty associated with a cache miss involves a number of second-order effects. This includes PLB contention between the instruction and data

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caches and the time associated with performing cache-line fills and flushes. Unless stated otherwise, the number of cycles described applies to systems having zero-wait-state memory access.

Table 1-3: PowerPC 405 Cycles per Instruction

Instruction Class

Execution Cycles

 

 

Arithmetic

1

 

 

Trap

2

 

 

Logical

1

 

 

Shift and Rotate

1

 

 

Multiply (32-bit, 48-bit, 64-bit results, respectively)

1, 2, 4

 

 

Multiply Accumulate

1

 

 

Divide

35

 

 

Load

1

 

 

Load Multiple and Load String (cache hit)

1 per data transfer

 

 

Store

1

 

 

Store Multiple and Store String (cache hit or miss)

1 per data transfer

 

 

Move to/from device-control register

3

 

 

Move to/from special-purpose register

1

 

 

Branch known taken

1 or 2

 

 

Branch known not taken

1

 

 

Predicted taken branch

1 or 2

 

 

Predicted not-taken branch

1

 

 

Mispredicted branch

2 or 3

 

 

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Chapter 2

Input/Output Interfaces

This chapter describes all PowerPC 405 input/output signals associated with the following processor block interfaces:

x“Clock and Power Management Interface”

x“CPU Control Interface”

x“Reset Interface”

x“Instruction-Side Processor Local Bus Interface”

x“Data-Side Processor Local Bus Interface”

x“Device-Control Register Interfaces”

x“Internal Device Control Register (DCR) Interface”

x“External DCR Bus Interface”

x“External Interrupt Controller Interface”

x“PPC405 JTAG Debug Port”

x“Debug Interface”

x“Trace Interface”

x“Processor Version Register (PVR) Interface (Virtex-4-FX Only)”

x“Additional FPGA Specific Signals”

The sections within this chapter provide the following information:

xAn overview summarizing the purpose of the interface.

xAn I/O symbol providing a quick view of the signal names and the direction of information flow with respect to the processor block.

xA signal table that summarizes the function of each signal. The I/O column in these tables specifies the direction of information flow with respect to the processor block.

xDetailed descriptions for each signal.

xDetailed timing diagrams (where appropriate) that more clearly describe the operation of the interface. The diagrams typically illustrate best-case performance when the core is attached to the FPGA processor local bus (PLB) core, or to custom bus interface unit (BIU) designs.

The instruction-side and data-side OCM controller interfaces are described separately in Chapter 3, “PowerPC 405 OCM Controller.”

The Fabric Co-Processor Module (FCM) interface associated with the Virtex-4-FX family PowerPC 405 APU controller, is described separately in Chapter 4, “PowerPC 405 APU Controller.”

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Chapter 2: Input/Output Interfaces

Appendix B, “Signal Summary,” alphabetically lists the signals described in this chapter. The l/O designation and a description summary are included for each signal.

Signal Naming Conventions

The following convention is used for signal names throughout this document:

PREFIX1PREFIX2SIGNAME1[SIGNAME2][NEG][(m:n)]

The components of a signal name are as follows:

xPREFIX1 is an uppercase prefix identifying the source of the signal. This prefix specifies either a unit (for example, CPU) or a type of interface (for example, DCR). If PREFIX1 specifies the processor block, the signal is considered an output signal. Otherwise, it is an input signal.

xPREFIX2 is an uppercase prefix identifying the destination of the signal. This prefix specifies either a unit (for example, CPU) or a type of interface (for example, DCR). If PREFIX2 specifies the processor block, the signal is considered an input signal. Otherwise, it is an output signal.

xSIGNAME1 is an uppercase name identifying the primary function of the signal.

xSIGNAME2 is an uppercase name identifying the secondary function of the signal.

x[NEG] is an optional notation that indicates a signal is active low. If this notation is not use, the signal is active high.

x[m:n] is an optional notation that indicates a bussed signal. “m” designates the mostsignificant bit of the bus and “n” designates the least-significant bit of the bus.

Table 2-1 defines the prefixes used in the signal names. The “Location” column in the table identifies whether the functional unit resides inside or outside the processor block.

Table 2-1: Signal Name Prefix Definitions

Prefix1 or Prefix2

Definition

Location

 

 

 

CPM

Clock and power management

Outside

 

 

 

C405

Processor block

Inside

 

 

 

DBG

Debug unit

Inside

 

 

 

DCR

Device control register

Outside

 

 

 

DSOCM

Data-side on-chip memory (DSOCM)

Outsidea

EIC

External interrupt controller

Outside

 

 

 

ISOCM

Instruction-side on-chip memory (ISOCM)

Outsidea

JTG

JTAG

Inside

 

 

 

PLB

Processor local bus

Inside

 

 

 

RST

Reset

Inside

 

 

 

TIE

TIE (signal tied statically to GND or VDD)

Outside

TRC

Trace

Inside

 

 

 

APU

Auxiliary Processor Unit Controller

Inside

 

 

 

FCM

Fabric Co-Processor Module

Outside

 

 

 

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Table 2-1: Signal Name Prefix Definitions (Continued)

Prefix1 or Prefix2

Definition

Location

 

 

 

BRAM

BlockSelect RAM

Outside

 

 

 

XXX

Unspecified FPGA unit

Outside

 

 

 

a. Not to be confused with the OCM controllers, which are located inside the processor block.

Clock and Power Management Interface

The clock and power management (CPM) interface enables power-sensitive applications to control the processor clock using external logic. The OCM controllers are clocked separately from the processor core. In addition to this, the Virtex-4-FX family PowerPC 405 also use separate clocks for the APU and DCR controller. Two types of processor clock control are possible:

xGlobal local enables control a clock zone within the processor. These signals are used to disable the clock splitters within a zone so that the clock signal is prevented from propagating to the latches within the zone. The PowerPC 405 is divided into three clock zones: core, timer, and JTAG. Control over a zone is exercised as follows:

i The core clock zone contains most of the logic comprising the PowerPC 405 core and controllers. It does not contain logic that belongs to the timer or JTAG zones, or other logic within the processor block. The core zone is controlled by the CPMC405CPUCLKEN signal.

iThe timer clock zone contains the PowerPC 405 timer logic. It does not contain logic that belongs to the core or JTAG zones, or other logic within the processor block. This zone is separated from the core zone so that timer events can be used to “wake up” the core logic if a power management application has put it to sleep. The timer zone is controlled by the CPMC405TIMERCLKEN signal.

iThe JTAG clock zone contains the PowerPC 405 JTAG logic. It does not contain logic that belongs to the core or timer zones, or other logic within the processor block. The JTAG zone is controlled by the CPMC405JTAGCLKEN signal.

Although an enable is provided for this zone, the JTAG standard does not allow local gating of the JTAG clock. This enables basic JTAG functions to be maintained when the rest of the chip (including the CPM FPGA macro) is not running.

x Global gating controls the toggling of the PowerPC 405 clock, CPMC405CLOCK. Instead of using the global-local enables to prevent the clock signal from propagating through a zone, CPM logic can stop the PowerPC 405 clock input from toggling. If this method of power management is employed, the clock signal should be held active (logic 1). The CPMC405CLOCK is used by the core and timer zones, but not the JTAG zone.

CPM logic should be designed to wake the PowerPC 405 from sleep mode when any of the following occurs:

iA timer interrupt or timer reset is asserted by the PowerPC 405.

iA chip-reset or system-reset request is asserted (this request comes from a source other than the PowerPC 405).

iAn external interrupt or critical interrupt input is asserted and the corresponding interrupt is enabled by the appropriate machine-state register (MSR) bit.

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iThe DBGC405DEBUGHALT chip-input signal (if provided) is asserted. Assertion of this signal indicates that an external debug tool wants to control the PowerPC 405 processor. See “DBGC405DEBUGHALT (Input)” for more information.

CPM Interface I/O Signal Summary

Figure 2-1 shows the block symbol for the CPM interface. The BRAM clocks associated with the data-side and instruction-side OCM are described in chapter Chapter 3, “PowerPC 405 OCM Controller.” The signals are summarized in Table 2-2.

 

 

 

CPMC405CLOCK

 

 

 

PPC405

 

C405CPMMSREE

 

 

 

 

 

 

 

 

 

 

PLBCLK

 

 

 

 

 

C405CPMMSRCE

 

 

 

 

 

 

 

 

 

CPMC405CPUCLKEN

 

 

 

 

 

C405CPMTIMERIRQ

 

 

 

 

 

 

 

CPMC405TIMERCLKEN

 

 

 

 

 

C405CPMTIMERRESETREQ

 

 

 

 

 

 

 

CPMC405JTAGCLKEN

 

 

 

 

 

C405CPMCORESLEEPREQ

 

 

 

 

 

 

CPMC405CORECLKINACTIVE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CPMC405TIMERTICK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CPMC405SYNCBYPASS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CPMDCRCLK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CPMFCMCLK

 

 

 

 

 

UG018_02_01_051204

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 2-1: CPM Interface Block Symbol

Table 2-2: CPM Interface I/O Signals

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Signal

 

I/O

 

If Unused

 

 

 

 

Function

 

Type

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CPMC405CLOCK

 

I

 

Required

 

 

PowerPC 405 clock input (for all non-JTAG logic,

 

 

 

 

 

 

 

 

including timers).

 

 

 

 

 

 

 

PLBCLK

 

I

 

Required

 

 

PLB clock interface clock (lacks CPM prefix due

 

 

 

 

 

 

 

 

to legacy naming).

 

 

 

 

 

 

 

 

 

CPMC405CPUCLKEN

 

I

 

1

 

 

 

Enables the core clock zone.

 

 

 

 

 

 

 

 

 

CPMC405TIMERCLKEN

 

I

 

1

 

 

 

Enables the timer clock zone.

 

 

 

 

 

 

 

 

 

CPMC405JTAGCLKEN

 

I

 

1

 

 

 

Enables the JTAG clock zone.

 

 

 

 

 

 

 

 

 

CPMC405CORECLKINACTIVE

 

I

 

0

 

 

 

Indicates the CPM logic disabled the clocks to the

 

 

 

 

 

 

 

 

core.

 

 

 

 

 

 

 

 

 

 

CPMC405TIMERTICK

 

I

 

1

 

 

 

Increments or decrements the PowerPC 405

 

 

 

 

 

 

 

 

timers every time it is active with the

 

 

 

 

 

 

 

 

CPMC405CLOCK.

 

 

 

 

 

 

 

 

 

CPMC405SYNCBYPASS

 

I

 

1

 

 

 

Virtex-4-FX only. Bypass PLB re-synchronization

 

 

 

 

 

 

 

 

inside the PowerPC 405 core for Virtex-II Pro

 

 

 

 

 

 

 

 

compatibility.

 

 

 

 

 

 

 

 

 

 

CPMDCRCLK

 

I

 

0

 

 

 

Virtex-4-FX only. DCR bus interface clock for

 

 

 

 

 

 

 

 

PPC405 synchronization.

 

 

 

 

 

 

 

 

 

CPMFCMCLK

 

I

 

0

 

 

 

Virtex-4-FX only. FCM interface clock for the

 

 

 

 

 

 

 

 

APU Controller.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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Table 2-2: CPM Interface I/O Signals (Continued)

Signal

I/O

If Unused

Function

Type

 

 

 

 

 

 

 

C405CPMMSREE

O

No Connect

Indicates the value of MSR[EE].

 

 

 

 

C405CPMMSRCE

O

No Connect

Indicates the value of MSR[CE].

 

 

 

 

C405CPMTIMERIRQ

O

No Connect

Indicates a timer-interrupt request occurred.

 

 

 

 

C405CPMTIMERRESETREQ

O

No Connect

Indicates a watchdog-timer reset request

 

 

 

occurred.

 

 

 

 

C405CPMCORESLEEPREQ

O

No Connect

Indicates the core is requesting to be put into

 

 

 

sleep mode.

 

 

 

 

CPM Interface I/O Signal Descriptions

The following sections describe the operation of the CPM interface I/O signals.

CPMC405CLOCK (Input)

This signal is the source clock for all PowerPC 405 logic (including timers). It is not the source clock for the JTAG logic. External logic can implement a power management mode that stops toggling of this signal. If such a method is employed, the clock signal should be held active (logic 1).

PLBCLK (Input)

This signal is the source clock for all PLB logic.

CPMC405CPUCLKEN (Input)

Enables the core clock zone when asserted and disables the zone when deasserted. If logic is not implemented to control this signal, it must be held active (tied to 1).

CPMC405TIMERCLKEN (Input)

Enables the timer clock zone when asserted and disables the zone when deasserted. If logic is not implemented to control this signal, it must be held active (tied to 1).

CPMC405JTAGCLKEN (Input)

Enables the JTAG clock zone when asserted and disables the zone when deasserted. CPM logic should not control this signal. The JTAG standard requires that it be held active (tied to 1).

CPMC405CORECLKINACTIVE (Input)

This signal is a status indicator that is latched by an internal PowerPC 405 register (JDSR). An external debug tool (such as RISCWatch) can read this register and determine that the PowerPC 405 is in sleep mode. This signal should be asserted by the CPM when it places the PowerPC 405 in sleep mode using either of the following methods:

xDeasserting CPMC405CPUCLKEN to disable the core clock zone.

xStopping CPMC405CLOCK from toggling by holding it active (logic 1).

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CPMC405TIMERTICK (Input)

This signal is used to control the update frequency of the PowerPC 405 time base and PIT (the FIT and WDT are timer events triggered by the time base). The time base is incremented and the PIT is decremented every cycle that CPMC405TIMERTICK and CPMC405CLOCK are both active. CPMC405TIMERTICK should be synchronous with CPMC405CLOCK for the timers to operate predictably. The timers are updated at the PowerPC 405 clock frequency if CPMC405TIMERTICK is held active.

CPMC405SYNCBYPASS (Input, Virtex-4-FX Only)

Allows the user to bypass the PLB synchronization module inside the PowerPC core and instead use a Virtex-II Pro compatible synchronizer in the processor block. When this signal is enabled, integer clock ratios between 1:1 and 16:1 are possible. If disabled, the user can use fractional clock ratios of N/2 and N/3 for any integer N, but must also ensure that PLB and CPU clocks are rising-edge aligned, and accept additional latency for the synchronization.

CPMDCRCLK (Input, Virtex-4-FX Only)

This is the DCR interface clock used by the PPC to synchronize communication between the PowerPC’s internal clock domain (CPMC405CLOCK) and the DCR bus transactions performed using the DCR slave clocks. The PowerPC core to DCR interface clock ratio can be any integer between 1:1 and 16:1. Clocks must be rising-edge aligned.

CPMFCMCLK (Input, Virtex-4-FX Only)

This is the re-synchronization clock for transactions between the APU controller and an FCM. Allows the APU controller internally to run at the CPMC405CLOCK speed, independently of the FCM interface transaction speed. CPMFCMCLK would typically be the same clock that clocks the FCM internally. PowerPC core to FCM interface clock ratio can be any integer between 1:1 and 16:1. Clocks must be rising-edge aligned.

C405CPMMSREE (Output)

This signal indicates the state of the MSR[EE] (external-interrupt enable) bit. When asserted, external interrupts are enabled (MSR[EE]=1). When deasserted, external interrupts are disabled (MSR[EE]=0). The CPM can use this signal to wake the processor from sleep mode when an external noncritical interrupt occurs.

When the processor wakes up, it deasserts the C405CPMMSREE, C405CPMMSRCE, and C405CPMTIMERIRQ signals one processor clock cycle before it deasserts the C405CPMCORESLEEPREQ signal. Consequently, the CPM should latch the C405CPMMSREE, C405CPMMSRCE, and C405CPMTIMERIRQ signals before using them to control the processor clocks.

C405CPMMSRCE (Output)

This signal indicates the state of the MSR[CE] (critical-interrupt enable) bit. When asserted, critical interrupts are enabled (MSR[CE]=1). When deasserted, critical interrupts are disabled (MSR[CE]=0). The CPM can use this signal to wake the processor from sleep mode when an external critical interrupt occurs.

When the processor wakes up, it deasserts the C405CPMMSREE, C405CPMMSRCE, and C405CPMTIMERIRQ signals one processor clock cycle before it deasserts the C405CPMCORESLEEPREQ signal. For this reason, the CPM should latch the

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C405CPMMSREE, C405CPMMSRCE, and C405CPMTIMERIRQ signals before using them to control the processor clocks.

C405CPMTIMERIRQ (Output)

When asserted, this signal indicates a timer exception occurred within the PowerPC 405 and an interrupt request is pending to handle the exception. When deasserted, no timerinterrupt request is pending. This signal is the logical OR of interrupt requests from the programmable-interval timer (PIT), the fixed-interval timer (FIT), and the watchdog timer (WDT). The CPM can use this signal to wake the processor from sleep mode when an internal timer exception occurs.

When the processor wakes up, it deasserts the C405CPMMSREE, C405CPMMSRCE, and C405CPMTIMERIRQ signals one processor clock cycle before it deasserts the C405CPMCORESLEEPREQ signal. Consequently, the CPM should latch the C405CPMMSREE, C405CPMMSRCE, and C405CPMTIMERIRQ signals before using them to control the processor clocks.

C405CPMTIMERRESETREQ (Output)

When asserted, this signal indicates a watchdog time-out occurred and a reset request is pending. When deasserted, no reset request is pending. This signal is the logical OR of the core, chip, and system reset modes that are programmed using the watchdog timer mechanism. The CPM can use this signal to wake the processor from sleep mode when a watchdog time-out occurs.

C405CPMCORESLEEPREQ (Output)

When asserted, this signal indicates the PowerPC 405 has requested to be put into sleep mode. When deasserted, no request exists. This signal is asserted after software enables the wait state by setting the MSR[WE] (wait-state enable) bit to 1. The processor completes execution of all prior instructions and memory accesses before asserting this signal. The CPM can use this signal to place the processor in sleep mode at the request of software.

When the processor gets out of sleep mode at a later time, it deasserts the C405CPMMSREE, C405CPMMSRCE, and C405CPMTIMERIRQ signals one processor clock cycle before it deasserts the C405CPMCORESLEEPREQ signal. Consequently, the CPM should latch the C405CPMMSREE, C405CPMMSRCE, and C405CPMTIMERIRQ signals before using them to control the processor clocks.

System Design Considerations for Clock Domains

The high-level view of an embedded system with the PowerPC 405 processor and

CoreConnect bus architecture includes:

xPowerPC 405 Processor.

xProcessor Local Bus (PLB) peripherals.

xInstruction-side and Data-side On-Chip Memory Controller (OCM).

xDevice Control Register (DCR) peripherals.

xFabric Co-Processor Module (FCM): Virtex-4 only.

These clocks communicate to the processor block the specific clock ratio between the processor block clock and the other system clocks in the design.

xCPMC405CLOCK, main Processor Block clock.

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xPLBCLK, primary PLB I/O Bus clock.

xBRAMISOCMCLK, reference clock for the I-Side OCM controller.

xBRAMDSOCMCLK, reference clock for the D-Side OCM controller.

xCPMFCMCLK, reference clock for the APU controller (Virtex-4 only).

xCPMDCRCLK, reference clock for the external DCR bus (Virtex-4 only).

The PowerPC405 processor block supports multiple clock domains. Using several DCM and BUFG components are recommended to create and drive the clock domains. The clock domains include the PLB, FCM, DCR, and OCM clocks.

PLB

The PLB is used as an interface between the processor block and the higher performance peripherals. The processor block has some internal logic to generate the appropriate enabling signals for controlling the PLB. The PLB clock must be phased-aligned to the processor block. All communication between the processor block and the PLB are based upon the rising edge of the CPMC405CLOCK. The PLB is synchronous with the processor block. The allowed supported integer clock frequency ratios between the processor block and the PLB are 1:1, 2:1, 3:1 . . . up to 16:1. As an example, the processor block can be run at 300 MHz while the PLB bus is run at 100 MHz, in a 3:1 ratio.

DCR

The processor block clock and the DCR clock must come from the same source and be in phase with each other. The DCR clock covers both of the processor block DCR and the memory mapped DCR. The clock ratio between the DCR clock domain and the processor block can run at any integer clock ratio from 1:1 to 16:1 as long as the bus transaction completes in 64 processor block cycles. If the bus transaction does not complete in 64 processor block clock cycles, the processor block will time out and move on to the next instruction.

Virtex-II Pro and ProX Specific

For Virtex-II Pro and Virtex-II ProX devices, there is no CPMDCRCLK input to the processor block. Users can either set appropriate timing constraints (multi-cycle path, false path, etc.), or simply include DCR re-synchronization logic to simply the steps to analyze the timing related to DCR interface.

Virtex-4 Specific

For Virtex-4-FX parts there is a dedicated DCR clock input and re-synchronization registers handling the clock boundary.

FCM (Virtex-4-FX only)

An FCM is used for highest performance integration of custom functionality defined in the FPGA fabric with the execution pipeline of the PowerPC. The FCM clock would typically be the same clock that clocks the FCM internally. PowerPC core to FCM interface clock ratios can range from 1:1 to 16:1. The clocks must be rising-edge aligned.

OCM

For high speed access, the OCM clock domain covers the interface between the processor block and the block RAM surrounding the processor block. There are two independent

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clocks for the OCM controllers in the processor block: BRAMDSOCMCLK (data side controller) and BRAMISOCMCLK (instruction side controllers).

The data side controller and the instruction side controllers can run at different frequencies, based upon the access time of the BRAM. When the processor block, OCM controller, and BRAMs run at the same clock frequency, the processor is in single-cycle mode. Multi-cycle mode occurs when the processor is running at a higher frequency than the BRAMs. In the single-cycle mode and multi-cycle mode, the BRAMISOCMCLK and BRAMDSOCMCLK signals are provided to the OCM controller as inputs.

Through timing analysis, the clock ratio between the processor block clock and the BRAMs clocks is determined by the worst case access time between the OCM controller interface and the BRAMs interface. Based upon the timing analysis, most designs use multi-cycle mode.

The processor block clock and the BRAMDSOCMCLK must be integer multiples. The same is true for the BRAMISOCMCLK with respect to the processor block clock. They need not share the same integer values nor integer clock ratio with respect to the PLB clock. Because the clock ratio between the processor block and the OCM clocks is unknown, the processor block has control registers in the OCM controllers. The control registers are ISCNTL[0:7] and DSCNTL[0:7] for the instruction side and data side, respectively. Refer to Chapter 3, “PowerPC 405 OCM Controller” for more details.

CPU Control Interface

The CPU control interface is used primarily to provide CPU setup information to the PowerPC 405. It is also used to report the detection of a machine check condition within the PowerPC 405.

CPU Control Interface I/O Signal Summary

Figure 2-2 shows the block symbol for the CPU control interface. The signals are summarized in Table 2-3.

TIEC405MMUEN

 

 

PPC405

 

C405XXXMACHINECHECK

 

 

 

 

 

 

TIEC405DETERMINISTICMULT

 

 

 

 

 

 

 

 

 

 

TIEC405DISOPERANDFWD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

UG018_02_102001

 

 

Figure 2-2: CPU Control Interface Block Symbol

Table 2-3: CPU Control Interface I/O Signals

 

 

 

 

 

 

Signal

I/O

 

If Unused

Function

Type

 

 

 

 

 

 

 

 

 

 

TIEC405MMUEN

I

 

Required

Enables the memory-management unit (MMU).

 

 

 

 

 

TIEC405DETERMINISTICMULT

I

 

0

Important: This signal should always be driven low.

 

 

 

 

Specifies whether all multiply operations complete in

 

 

 

 

a fixed number of cycles or have an early-out

 

 

 

 

capability

 

 

 

 

 

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Table 2-3: CPU Control Interface I/O Signals (Continued)

Signal

I/O

If Unused

Function

Type

 

 

 

 

 

 

 

TIEC405DISOPERANDFWD

I

Required

Disables operand forwarding for load instructions.

 

 

 

 

C405XXXMACHINECHECK

O

No Connect

Indicates a machine-check error has been detected by

 

 

 

the PowerPC 405.

 

 

 

 

CPU Control Interface I/O Signal Descriptions

The following sections describe the operation of the CPU control-interface I/O signals.

TIEC405MMUEN (Input)

When held active (tied to logic 1), this signal enables the PowerPC 405 memorymanagement unit (MMU). When held inactive (tied to logic 0), this signal disables the MMU. The MMU is used for virtual to address translation and for memory protection. Its operation is described in the PowerPC Processor Reference Guide.

TIEC405DETERMINISTICMULT (Input)

Note: This signal should always be driven low. Setting it high may produce erroneous results.

When held active (tied to logic 1), this signal disables the hardware multiplier early-out capability. All multiply instructions have a 4-cycle reissue rate and a 5-cycle latency rate. When held inactive (tied to logic 0), this signal enables the hardware multiplier early-out capability. If early out is enabled, multiply instructions are executed in the number of cycles specified in Table 2-4. The performance of multiply instructions is described in the

PowerPC Processor Reference Guide.

Table 2-4: Multiply and MAC Instruction Timing

Operations

Issue-Rate

Latency

Cycles

Cycles

 

 

 

 

MAC and Negative MAC

1

2

 

 

 

Halfword uHalfword (32-bit result)

1

2

 

 

 

Halfword uWord (48-bit result)

2

3

 

 

 

Word uWord (64-bit result)

4

5

 

 

 

Note: In Table 2-4, above, words are treated as halfwords if the upper 16 bits of the operand contain a sign extension of the lower 16 bits. For example, if the upper 16 bits of a word operand are zero, the operand is considered a halfword when calculating the execution time.

TIEC405DISOPERANDFWD (Input)

When held active (tied to logic 1), this signal disables operand forwarding. When held inactive (tied to logic 0), this signal enables operand forwarding. The processor uses operand forwarding to send load-instruction data from the data cache to the execution units as soon as it is available. Operand forwarding often saves a clock cycle when

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instructions following the load require the loaded data. Disabling operand forwarding may improve the performance (clock frequency) of the PowerPC 405.

C405XXXMACHINECHECK (Output)

When asserted, this signal indicates the PowerPC 405 detected an instruction machinecheck error. When deasserted, no error exists. This signal is asserted when the processor attempts to execute an instruction that was transferred to the PowerPC 405 with the PLBC405ICUERR signal asserted. This signal remains asserted until software clears the instruction machine-check bit in the exception-syndrome register (ESR[MCI]).

Reset Interface

A reset causes the processor block to perform a hardware initialization. It always occurs when the processor block is powered up and can occur at any time during normal operation. If it occurs during normal operation, instruction execution is immediately halted and all processor state is lost.

The processor block recognizes three types of reset:

xA processor reset affects only the processor block, including PowerPC 405 execution units, cache units, the device control register controller (DCR), and the on-chip memory controller (OCM). On Virtex-4-FX, it also resets the auxiliary processor unit controller (APU). External devices (on-chip and off-chip) are not affected. This type of reset is also referred to as a core reset.

xA chip reset affects the processor block and all other devices or peripherals located on the same chip as the processor.

xA system reset affects the processor chip and all other devices or peripherals external to the processor chip that are connected to the same system-reset network. The scope of a system reset depends on the system implementation. Power-on reset (POR) is a form of system reset.

Input signals are provided to the processor block for each reset type. The signals are used to reset the processor block and to record the reset type in the debug-status register (DBSR[MRR]). The processor block can produce reset-request output signals for each reset type. External reset logic can process these output signals and generate the appropriate reset input signals to the processor block. Reset activity does not occur when the processor block requests the reset. Reset activity occurs only when external logic asserts the appropriate reset input signal.

Reset Requirements

FPGA logic (external to the processor block) is required to generate the reset input signals to the processor block. The reset input signals can be based on the reset-request output signals from the processor block, system-specific reset-request logic, or a combination of the two. Reset input signals must meet the following minimum requirements:

xThe reset input signals must be synchronized with the PowerPC 405 clock.

xThe reset input signals must be asserted for at least eight (CPMC405CLOCK) clock cycles.

xOnly the combinations of signals shown in Table 2-5 are used to cause a reset.

POR (power-on reset) is handled by logic within the processor block. This logic asserts the RSTC405RESETCORE, RSTC405RESETCHIP, RSTC405RESETSYS, and

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JTGC405TRSTNEG signals for at least sixteen clock cycles. FPGA designers cannot modify the processor block power-on reset mechanism.

The reset logic is not required to support all three types of reset. However, distinguishing resets by type can make it easier to isolate errors during system debug. For example, a system could reset the core to recover from an external error that affects software operation. Following the core reset, a debugger could be used to locate the external error source that is preserved because neither a chip or system reset occurred.

Table 2-5 shows the valid combinations of reset signals and their effect on the DBSR[MRR] field following reset.

Table 2-5: Valid Reset Signal Combinations and Effect on DBSR(MRR)

Reset Input Signal

 

 

Reset Type

 

 

 

 

 

 

 

 

None

Core

 

Chip

System

Power-Ona

 

 

RSTC405RESETCORE

Deassert

Assert

 

Assert

Assert

Assert

 

 

 

 

 

 

 

RSTC405RESETCHIP

Deassert

Deassert

 

Assert

Assert

Assert

 

 

 

 

 

 

 

RSTC405RESETSYS

Deassert

Deassert

 

Deassert

Assert

Assert

 

 

 

 

 

 

 

JTGC405TRSTNEG

Deassert

Deassert

 

Deassert

Deassert

Assert

 

 

 

 

 

 

 

Value of DBSR[MRR]

Previous

0b01

 

0b10

0b11

0b11

following reset

DBSR[MRR]

 

 

 

 

 

 

 

 

 

 

 

 

a. Handled automatically by logic within the processor block.

Reset Interface I/O Signal Summary

Figure 2-3 shows the block symbol for the reset interface. The signals are summarized in Table 2-6.

RSTC405RESETCORE

 

 

PPC405

 

C405RSTCORERESETREQ

 

 

 

 

 

 

RSTC405RESETCHIP

 

 

 

 

C405RSTCHIPRESETREQ

 

 

RSTC405RESETSYS

 

 

 

 

C405RSTSYSRESETREQ

 

 

JTGC405TRSTNEG

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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Figure 2-3: Reset Interface Block Symbol

Table 2-6: Reset Interface I/O Signals

 

 

 

 

 

Signal

I/O

If Unused

Function

Type

 

 

 

 

 

 

 

C405RSTCORERESETREQ

O

Required

Indicates a core-reset request

 

 

 

occurred.

 

 

 

 

C405RSTCHIPRESETREQ

O

Required

Indicates a chip-reset request

 

 

 

occurred.

 

 

 

 

C405RSTSYSRESETREQ

O

Required

Indicates a system-reset request

 

 

 

occurred.

 

 

 

 

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Table 2-6: Reset Interface I/O Signals (Continued)

Signal

I/O

If Unused

Function

Type

 

 

 

 

 

 

 

RSTC405RESETCORE

I

Required

Resets the processor block, including

 

 

 

the PowerPC 405 core logic, data

 

 

 

cache, instruction cache, and interface

 

 

 

controllers.

 

 

 

 

RSTC405RESETCHIP

I

Required

Indicates a chip-reset occurred.

 

 

 

 

RSTC405RESETSYS

I

Required

Indicates a system-reset occurred.

 

 

 

Resets the logic in the PowerPC 405

 

 

 

JTAG unit.

 

 

 

 

JTGC405TRSTNEG

I

Required

Performs a JTAG test reset (TRST).

 

 

 

 

Reset Interface I/O Signal Descriptions

The following sections describe the operation of the reset interface I/O signals.

C405RSTCORERESETREQ (Output)

When asserted, this signal indicates the processor block is requesting a core reset. If asserted, this signal remains active until two clock cycles after external logic asserts the RSTC405RESETCORE input to the processor block. When deasserted, no core-reset request exists.

The processor asserts this signal when one of the following occurs:

xA JTAG debugger sets the reset field in the debug-control register 0 (DBCR0[RST]) to 0b01.

xSoftware sets the reset field in the debug-control register 0 (DBCR0[RST]) to 0b01.

xThe timer-control register watchdog-reset control field (TCR[WRC]) is set to 0b01 and a watchdog time-out causes the watchdog-event state machine to enter the reset state.

C405RSTCHIPRESETREQ (Output)

When asserted, this signal indicates the processor block is requesting a chip reset. If this signal is asserted, it remains active until two clock cycles after external logic asserts the RSTC405RESETCHIP input to the processor block. When deasserted, no chip-reset request exists. Unlike GSR, this output has no associated reset connectivity in the FPGA.

The processor asserts this signal when one of the following occurs:

xA JTAG debugger sets the reset field in the debug-control register 0 (DBCR0[RST]) to 0b10.

xSoftware sets the reset field in the debug-control register 0 (DBCR0[RST]) to 0b10.

xThe timer-control register watchdog-reset control field (TCR[WRC]) is set to 0b10 and a watchdog time-out causes the watchdog-event state machine to enter the reset state.

C405RSTSYSRESETREQ (Output)

When asserted, this signal indicates the processor block is requesting a system reset. If this signal is asserted, it remains active until two clock cycles after external logic asserts the

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RSTC405RESETSYS input to the processor block. When deasserted, no system-reset request exists. Unlike GSR, this output has no associated reset connectivity in the FPGA.

The processor asserts this signal when one of the following occurs:

xA JTAG debugger sets the reset field in the debug-control register 0 (DBCR0[RST]) to 0b11.

xSoftware sets the reset field in the debug-control register 0 (DBCR0[RST]) to 0b11.

xThe timer-control register watchdog-reset control field (TCR[WRC]) is set to 0b11 and a watchdog time-out causes the watchdog-event state machine to enter the reset state.

RSTC405RESETCORE (Input)

External logic asserts this signal to reset the processor block (core). This includes the PowerPC 405 core logic, data cache, instruction cache, and the interface controllers. The PowerPC 405 also uses this signal to record a core reset type in the DBSR[MRR] field. This signal should be asserted for at least eight clock cycles to guarantee that the processor block initiates its reset sequence. No reset occurs and none is recorded in DBSR[MRR] when this signal is deasserted.

Table 2-5, page 44 shows the valid combinations of the RSTC405RESETCORE, RSTC405RESETCHIP, and RSTC405RESETSYS signals and their effect on the DBSR[MRR] field following reset.

RSTC405RESETCHIP (Input)

External logic asserts this signal to reset the chip. A chip reset involves the FPGA logic, onchip peripherals, and the processor block (the PowerPC 405 core logic, data cache, instruction cache, and the interface controllers). The signal does not reset logic in the processor block. The PowerPC 405 uses this signal only to record a chip reset type in the DBSR[MRR] field. The RSTC405RESETCORE signal must be asserted with this signal to cause a core reset. Both signals must be asserted for at least eight clock cycles to guarantee that the processor block recognizes the reset type and initiates the core-reset sequence. The PowerPC 405 does not record a chip reset type in DBSR[MRR] when this signal is deasserted.

Table 2-5, page 44 shows the valid combinations of the RSTC405RESETCORE, RSTC405RESETCHIP, and RSTC405RESETSYS signals and their effect on the DBSR[MRR] field following reset.

RSTC405RESETSYS (Input)

External logic asserts this signal to reset the system. A system reset involves logic external to the FPGA, the FPGA logic, on-chip peripherals, and the processor block (the PowerPC 405 core logic, data cache, instruction cache, and the interface controllers). This signal resets the logic in the PowerPC 405 JTAG unit, but it does not reset any other processor block logic. The PowerPC 405 uses this signal to record a system reset type in the DBSR[MRR] field. The RSTC405RESETCORE signal must be asserted with this signal to cause a core reset. The RSTC405RESETCORE, RSTC405RESETCHIP, and RSTC405RESETSYS signals must be asserted for at least eight clock cycles to guarantee that the processor block recognizes the reset type and initiates the core-reset sequence. The PowerPC 405 does not record a system reset type in DBSR[MRR] when this signal is deasserted.

This signal must be asserted during a power-on reset to initialize the JTAG unit properly.

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Table 2-5, page 44 shows the valid combinations of the RSTC405RESETCORE, RSTC405RESETCHIP, and RSTC405RESETSYS signals and their effect on the DBSR[MRR] field following reset.

JTGC405TRSTNEG (Input)

This input is the JTAG test reset (TRST) signal. It can be connected to the chip-level TRST signal. Although optional in IEEE Standard 1149.1, this signal is automatically used by the processor block during power-on reset to properly reset all processor block logic, including the JTAG and debug logic. When deasserted, no JTAG test reset exists.

This is a negative active signal.

Instruction-Side Processor Local Bus Interface

The instruction-side processor local bus (ISPLB) interface enables the PowerPC 405 instruction cache unit (ICU) to fetch (read) instructions from any memory device connected to the processor local bus (PLB). The ICU cannot write to memory. This interface has a dedicated 30-bit address bus output and a dedicated 64-bit read-data bus input. The interface is designed to attach as a master to a 64-bit PLB, but it also supports attachment as a master to a 32-bit PLB. The interface is capable of one transfer (64 or 32 bits) every PLB cycle.

At the chip level, the ISPLB can be combined with the data-side read-data bus (also a PLB master) to create a shared read-data bus. This is done if a single PLB arbiter services both PLB masters, and the PLB arbiter implementation only returns data to one PLB master at a time.

Refer to the PowerPC Processor Reference Guide for more information on the operation of the PowerPC 405 ICU.

Instruction-Side PLB Operation

Fetch requests are produced by the ICU and communicated over the PLB interface. Fetch requests occur when an access misses the instruction cache or when the accessed memory location is non-cacheable. A fetch request contains the following information:

xA fetch request is indicated by C405PLBICUREQUEST. See “C405PLBICUREQUEST (Output)”.

xThe target address of the instruction to be fetched is specified by the address bus, C405PLBICUABUS[0:29]. See “C405PLBICUABUS[0:29] (Output)”. Bits 30:31 of the 32-bit instruction-fetch address are always zero and must be tied to zero at the PLB arbiter. The ICU always requests an aligned doubleword of data, so the byte enables are not used.

xThe transfer size is specified as four words (quadword) or eight words (cache line) using C405PLBICUSIZE[2:3]. See “C405PLBICUSIZE[2:3] (Output)”. The remaining bits of the transfer size (0:1) must be tied to zero at the PLB arbiter.

xThe cacheability storage attribute is indicated by C405PLBICUCACHEABLE. See “C405PLBICUCACHEABLE (Output)”. Cacheable transfers are always performed with an eight-word transfer size.

xThe user-defined storage attribute is indicated by C405PLBICUU0ATTR. See “C405PLBICUU0ATTR (Output)”.

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xThe request priority is indicated by C405PLBICUPRIORITY[0:1]. See “C405PLBICUPRIORITY[0:1] (Output)”. The PLB arbiter uses this information to prioritize simultaneous requests from multiple PLB masters.

The processor can abort a PLB fetch request using C405PLBICUABORT. See “C405PLBICUABORT (Output)”. This can occur when a branch instruction is executed or when an interrupt occurs.

Fetched instructions are returned to the ICU by a PLB slave device over the PLB interface. A fetch response contains the following information:

xThe fetch-request address is acknowledged by the PLB slave using PLBC405ICUADDRACK. See “PLBC405ICUADDRACK (Input)”.

xInstructions sent from the PLB slave to the ICU during a line transfer are indicated as valid using PLBC405ICURDDACK. See “PLBC405ICURDDACK (Input)”.

xThe PLB-slave bus width, or size (32-bit or 64-bit), is specified by PLBC405ICUSSIZE1. See “PLBC405ICUSSIZE1 (Input)”. The PLB slave is responsible for packing data bytes from non-word devices so that the information sent to the ICU is presented appropriately, as determined by the transfer size.

xThe instructions returned to the ICU by the PLB slave are sent using four-word or eight-word line transfers, as specified by the transfer size in the fetch request. These instructions are returned over the ICU read-data bus, PLBC405ICURDDBUS[0:63]. See “PLBC405ICURDDBUS[0:63] (Input)”. Line transfers operate as follows:

i A four-word line transfer returns the quadword aligned on the address specified by C405PLBICUABUS[0:27]. This quadword contains the target instruction requested by the ICU. The quadword is returned using two doubleword or four word transfer operations, depending on the PLB slave bus width (64-bit or 32-bit, respectively).

iAn eight-word line transfer returns the eight-word cache line aligned on the address specified by C405PLBICUABUS[0:26]. This cache line contains the target instruction requested by the ICU. The cache line is returned using four doubleword or eight word transfer operations, depending on the PLB slave bus width (64-bit or 32-bit, respectively).

x The words returned during a line transfer can be sent from the PLB slave to the ICU in any order (target-word-first, sequential, other). This transfer order is specified by PLBC405ICURDWDADDR[1:3]. See “PLBC405ICURDWDADDR[1:3] (Input)”.

Interaction with the ICU Fill Buffer

As mentioned above, the PLB slave can transfer instructions to the ICU in any order (target-word-first, sequential, other). When instructions are received by the ICU from the PLB slave, they are placed in the ICU fill buffer. When the ICU receives the target instruction, it forwards it immediately from the fill buffer to the instruction-fetch unit so that pipeline stalls due to instruction-fetch delays are minimized. This operation is referred to as a bypass. The remaining instructions are received from the PLB slave and placed in the fill buffer. Subsequent instruction fetches read from the fill buffer if the instruction is already present in the buffer. For the best possible software performance, the PLB slave should be designed to return the target word first.

Non-cacheable instructions are transferred using a four-word or eight-word line-transfer size. Software controls this transfer size using the non-cacheable request-size bit in the coreconfiguration register (CCR0[NCRS]). This enables non-cacheable transfers to take advantage of the PLB line-transfer protocol to minimize PLB-arbitration delays and bus delays associated with multiple, single-word transfers. The transferred instructions are

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placed in the ICU fill buffer, but not in the instruction cache. Subsequent instruction fetches from the same non-cacheable line are read from the fill buffer instead of requiring a separate arbitration and transfer sequence across the PLB. Instructions in the fill buffer are fetched with the same performance as a cache hit. The non-cacheable line remains in the fill buffer until the fill buffer is needed by another line transfer.

Cacheable instructions are always transferred using an eight-word line-transfer size. The transferred instructions are placed in the ICU fill buffer as they are received from the PLB slave. Subsequent instruction fetches from the same cacheable line are read from the fill buffer during the time the line is transferred from the PLB slave. When the fill buffer is full, its contents are transferred to the instruction cache. Software can prevent this transfer by setting the fetch without allocate bit in the core-configuration register (CCR0[FWOA]). In this case, the cacheable line remains in the fill buffer until the fill buffer is needed by another line transfer. An exception is that the contents of the fill buffer are always transferred if the line was fetched because an icbt instruction was executed.

Prefetch and Address Pipelining

A prefetch is a request for the eight-word cache line that sequentially follows the current eight-word fetch request. Prefetched instructions are fetched before it is known that they are needed by the sequential execution of software.

The ICU can overlap a single prefetch request with the prior fetch request. This process, known as address pipelining, enables a second address to be presented to a PLB slave while the slave is returning data associated with the first address. Address pipelining can occur if a prefetch request is produced before all instructions from the previous fetch request are transferred by the slave. This capability maximizes PLB-transfer throughput by reducing dead cycles between instruction transfers associated with the two requests. The ICU can pipeline the prefetch with any combination of sequential, branch, and interrupt fetch requests. A prefetch request is communicated over the PLB two or more cycles after the prior fetch request is acknowledged by the PLB slave.

Address pipelining of prefetch requests never occurs under any one of the following conditions:

xThe PLB slave does not support address pipelining.

xThe prefetch address falls outside the 1 KB physical page holding the current fetch address. This limitation avoids potential problems due to protection violations or storage-attribute mismatches.

xNon-cacheable transfers are programmed to use a four-word line-transfer size (CCR0[NCRS] 0).

xFor non-cacheable transfers, prefetching is disabled (CCR0[PFNC] 0).

xFor cacheable transfers, prefetching is disabled (CCR0[PFC] 0).

Address pipelining of non-cacheable prefetch requests can occur if all of the following conditions are met:

xAddress pipelining is supported by the PLB slave.

xThe ICU is not already involved in an address-pipelined PLB transfer.

xA branch or interrupt does not modify the sequential execution of the current (first) instruction-fetch request.

xNon-cacheable prefetching is enabled (CCR0[PFNC] 1).

xA non-cacheable instruction-prefetch is requested, and the instruction is not in the fill buffer or being returned over the ISOCM interface.

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xThe prefetch address does not fall outside the current 1 KB physical page.

Address pipelining of cacheable prefetch requests can occur if all of the following conditions are met:

xAddress pipelining is supported by the PLB slave.

xThe ICU is not already involved in an address-pipelined PLB transfer.

xA branch or interrupt does not modify the sequential execution of the current (first) instruction-fetch request.

xCacheable prefetching is enabled (CCR0[PFC] 1).

xA cacheable instruction-prefetch is requested, and the instruction is not in the instruction cache, the fill buffer, or being returned over the ISOCM interface.

xThe prefetch address does not fall outside the current 1 KB physical page.

Guarded Storage

Accesses to guarded storage are not indicated by the ISPLB interface. This is because the PowerPC Architecture allows instruction prefetching when:

xThe processor is in real mode (instruction address translation is disabled).

xThe fetched instruction is located in the same physical page (1 KB) as an instruction that is required by the sequential execution model.

xThe fetched instruction is located in the next physical page (1 KB) as an instruction that is required by the sequential execution model.

Memory should be organized such that real-mode instruction prefetching from the same or next 1 KB page does not affect sensitive addresses, such as memory-mapped I/O devices.

If the processor is in virtual mode, an attempt to prefetch from guarded storage causes an instruction-storage interrupt. In this case, the prefetch never appears on the ISPLB.

Instruction-Side PLB I/O Signal Table

Figure 2-4 shows the block symbol for the instruction-side PLB interface. The signals are summarized in Table 2-7.

PLBC405ICUADDRACK

 

 

 

PPC405

 

 

C405PLBICUREQUEST

 

 

 

 

 

 

PLBC405ICUSSIZE1

 

 

 

 

 

 

C405PLBICUABUS[0:29]

 

 

 

 

 

 

PLBC405ICURDDACK

 

 

 

 

 

 

C405PLBICUSIZE[2:3]

 

 

 

 

 

 

PLBC405ICURDDBUS[0:63]

 

 

 

 

 

 

C405PLBICUCACHEABLE

 

 

 

 

 

 

PLBC405ICURDWDADDR[1:3]

 

 

 

 

 

 

C405PLBICUU0ATTR

PLBC405ICUBUSY

 

 

 

 

 

 

C405PLBICUPRIORITY[0:1]

 

 

 

 

 

 

PLBC405ICUERR

 

 

 

 

 

 

C405PLBICUABORT

 

 

 

 

 

 

 

 

 

 

 

 

 

UG018_04_051204

 

 

 

 

 

 

 

Figure 2-4: Instruction-Side PLB Interface Block Symbol

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