Xilinx SP605 User Manual

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SP605 Hardware

User Guide

[Guide Subtitle] [optional]

UG526 (v1.1.1) February 1, 2010 [optional]

Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information.

THE DOCUMENTATION IS DISCLOSED TO YOU “AS-IS” WITH NO WARRANTY OF ANY KIND. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF THE DOCUMENTATION.

© 2009–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG.

Revision History

The following table shows the revision history for this document.

Date

Version

Revision

 

 

 

10/07/2009

1.0

Initial Xilinx release.

 

 

 

11/09/2009

1.1

Updated Figure 1-17 and Figure 1-23.

 

 

Changed speed grade from -2 to -3.

 

 

Miscellaneous typographical edits.

 

 

 

02/01/2010

1.1.1

Minor typographical edits to Table 1-24 and Table 1-25.

 

 

 

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UG526 (v1.1.1) February 1, 2010

Table of Contents

Preface: About This Guide

Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Additional Support Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Chapter 1: SP605 Evaluation Board

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Related Xilinx Documents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1. Spartan-6 XC6SLX45T-3FGG484 FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 I/O Voltage Rails . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2. 128 MB DDR3 Component Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3. SPI x4 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4. Linear BPI Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

FPGA Design Considerations for the Configuration Flash . . . . . . . . . . . . . . . . . . . . . . . 20 5. System ACE CF and CompactFlash Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6. USB JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7. Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Oscillator (Differential) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Oscillator Socket (Single-Ended, 2.5V or 3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

SMA Connectors (Differential) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8. Multi-Gigabit Transceivers (GTP MGTs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9. PCI Express Endpoint Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10. SFP Module Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 11. 10/100/1000 Tri-Speed Ethernet PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 12. USB-to-UART Bridge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 13. DVI CODEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 14. IIC Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8-Kb NV Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 15. Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Ethernet PHY Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 FPGA INIT and DONE LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 16. User I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 User LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 User Pushbutton Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 User DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 User SIP Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 User SMA GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

17. Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Power On/Off Slide Switch SW2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

FPGA_PROG_B Pushbutton SW3 (Active-Low). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 SYSACE_RESET_B Pushbutton SW9 (Active-Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

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System ACE CF CompactFlash Image Select DIP Switch S1 (Active-High) . . . . . . . . . . 48

Mode DIP Switch SW1 (Active-High). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

18. VITA 57.1 FMC LPC Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

AC Adapter and 12V Input Power Jack/Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Onboard Power Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Appendix A: Default Jumper and Switch Settings

Appendix B: VITA 57.1 FMC LPC Connector Pinout

Appendix C: SP605 Master UCF

Appendix D: References

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UG526 (v1.1.1) February 1, 2010

Preface

About This Guide

This manual accompanies the Spartan®-6 FPGA SP605 Evaluation Board and contains information about the SP605 hardware and software tools.

Guide Contents

This manual contains the following chapters:

Chapter 1, “SP605 Evaluation Board,” provides an overview of the embedded development board and details the components and features of the SP605 board.

Appendix A, “Default Jumper and Switch Settings.”

Appendix B, “VITA 57.1 FMC LPC Connector Pinout.”

Appendix C, “SP605 Master UCF.”

Appendix D, “References.”

Additional Documentation

The following documents are available for download at

http://www.xilinx.com/products/spartan6/.

Spartan-6 Family Overview

This overview outlines the features and product selection of the Spartan-6 family.

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

This data sheet contains the DC and switching characteristic specifications for the Spartan-6 family.

Spartan-6 FPGA Packaging and Pinout Specifications

This specification includes the tables for device/package combinations and maximum I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and thermal specifications.

Spartan-6 FPGA Configuration User Guide

This all-encompassing configuration guide includes chapters on configuration interfaces (serial and parallel), multi-bitstream management, bitstream encryption, boundary-scan and JTAG configuration, and reconfiguration techniques.

Spartan-6 FPGA SelectIO Resources User Guide

This guide describes the SelectIO™ resources available in all Spartan-6 devices.

Spartan-6 FPGA Clocking Resources User Guide

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UG526 (v1.1.1) February 1, 2010

Preface: About This Guide

This guide describes the clocking resources available in all Spartan-6 devices, including the DCMs and PLLs.

Spartan-6 FPGA Block RAM Resources User Guide

This guide describes the Spartan-6 device block RAM capabilities.

Spartan-6 FPGA GTP Transceivers User Guide

This guide describes the GTP transceivers available in the Spartan-6 LXT FPGAs.

Spartan-6 FPGA DSP48A1 Slice User Guide

This guide describes the architecture of the DSP48A1 slice in Spartan-6 FPGAs and provides configuration examples.

Spartan-6 FPGA Memory Controller User Guide

This guide describes the Spartan-6 FPGA memory controller block, a dedicated embedded multi-port memory controller that greatly simplifies interfacing Spartan-6 FPGAs to the most popular memory standards.

Spartan-6 FPGA PCB Designer’s Guide

This guide provides information on PCB design for Spartan-6 devices, with a focus on strategies for making design decisions at the PCB and interface level.

Additional Support Resources

To search the database of silicon and software questions and answers or to create a technical support case in WebCase, see the Xilinx website at:

http://www.xilinx.com/support.

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UG526 (v1.1.1) February 1, 2010

Chapter 1

SP605 Evaluation Board

Overview

The SP605 board enables hardware and software developers to create or evaluate designs targeting the Spartan®-6 XC6SLX45T-3FGG484 FPGA.

The SP605 provides board features common to many embedded processing systems. Some commonly used features include: a DDR3 component memory, a 1-lane PCI Express® interface, a tri-mode Ethernet PHY, general purpose I/O and a UART. Additional user desired features can be added through mezzanine cards attached to the onboard high speed VITA-57 FPGA Mezzanine Connector (FMC) low pin count (LPC) connector.

“Features,” page 8 provides a general listing of the board features with details provided in “Detailed Description,” page 10.

Additional Information

Additional information and support material is located at:

http://www.xilinx.com/sp605 This information includes:

Current version of this user guide in PDF format

Example design files for demonstration of Spartan-6 FPGA features and technology

Demonstration hardware and software configuration files for the System ACE CF controller, Platform Flash configuration storage device, and linear flash chip

Reference Design Files

Schematics in PDF format and DxDesigner schematic format

Bill of materials (BOM)

Printed-circuit board (PCB) layout in Allegro PCB format

Gerber files for the PCB (Many free or shareware Gerber file viewers are available on the Internet for viewing and printing these files.)

Additional documentation, errata, frequently asked questions, and the latest news

For information about the Spartan-6 family of FPGA devices, including product highlights, data sheets, user guides, and application notes, see the Spartan-6 FPGA website at http://www.xilinx.com/support/documentation/spartan-6.htm.

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Chapter 1: SP605 Evaluation Board

Features

The SP605 board provides the following features:

1. Spartan-6 XC6SLX45T-3FGG484 FPGA

2. 128 MB DDR3 Component Memory

3. SPI x4 Flash

4. Linear BPI Flash

5. System ACE CF and CompactFlash Connector

6. USB JTAG

7. Clock Generation

Fixed 200 MHz oscillator (differential)

Socket with a 2.5V 27MHz oscillator (single-ended)

SMA connectors (differential)

SMA connectors for MGT clocking (differential)

8. Multi-Gigabit Transceivers (GTP MGTs)

FMC LPC connector

SMA

PCIe

SFP module connector

9. PCI Express Endpoint Connectivity

Gen1 x1

10. SFP Module Connector

11. 10/100/1000 Tri-Speed Ethernet PHY

12. USB-to-UART Bridge

13. DVI CODEC

14. IIC Bus

IIC EEPROM - 1KB

DVI CODEC

DVI connector

FMC LPC connector

SFP Module connector

15. Status LEDs

Ethernet Status

FPGA INIT

FPGA DONE

16. User I/O

USER LED GPIO

User pushbuttons

CPU Reset pushbutton

User DIP switch - GPIO

User SMA GPIO connectors

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Overview

17. Switches

Power On/Off slide switch

System ACE CF Reset pushbutton

System ACE CF bitstream image select DIP switch

Mode DIP switch

18. VITA 57.1 FMC LPC Connector

Configuration Options

3. SPI x4 Flash (both onboard and off-board)

4. Linear BPI Flash

5. System ACE CF and CompactFlash Connector

6. USB JTAG

Power Management

AC Adapter and 12V Input Power Jack/Switch

Onboard Power Regulation

Block Diagram

Figure 1-1 shows a high-level block diagram of the SP605 and its peripherals.

LED

DIP Switch

User SMA x2

1-Lane I/Fs:

 

PCIe 125 MHz Clk

PCIe Edge Conn.

 

SMA REFCLK

SMA x4 SFP

 

SFPCLK

FMC-LPC

 

FMC GBTCLK

 

 

 

Part of

FMC-LPC

SFP IIC Bus

Expansion

Connector

JTAG

JTAG

 

 

 

 

System ACE

 

 

 

Main IIC Bus

MPU I/F

DED

MGTs

 

 

 

 

 

 

 

 

L/S

Bank 0

 

USB UART and

JTAG

 

2.5V

 

 

 

USB Mini-B

USB JTAG Logic

 

 

 

 

 

 

Connector

and USB Mini-B

 

 

 

 

Spartan-6

 

 

Connector

 

Bank 3

Bank 1

DVI Codec and

 

 

XC6SLX45T-3FGG484

 

 

1.5V

2.5V

DDR3

 

U1

DVI Connector

 

 

 

 

 

 

 

 

Component

 

 

 

 

 

Memory

 

 

 

 

10/100/1000

 

 

 

Bank 2

 

Ethernet PHY,

Pushbuttons

L/S

2.5V

 

Status LEDs,

DIP Switch

 

 

 

 

and Connector

 

 

 

 

 

GPIO Header

 

 

DVI IIC Bus

Parallel Flash

 

 

 

 

 

 

 

 

 

LED,

 

SPI x4,

 

Part of FMC-LPC

 

 

 

 

 

DIP Switch

 

SPI Header

 

Expansion Conn.

 

 

 

 

 

 

 

 

 

 

 

 

L/S

= Level Shifter

 

 

 

 

 

UG526_01_110409

Figure 1-1: SP605 Features and Banking

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UG526 (v1.1.1) February 1, 2010

Xilinx SP605 User Manual

Chapter 1: SP605 Evaluation Board

Related Xilinx Documents

Prior to using the SP605 Evaluation Board, users should be familiar with Xilinx resources. See the following locations for additional documentation on Xilinx tools and solutions:

ISE: www.xilinx.com/ise

Answer Browser: www.xilinx.com/support

Intellectual Property: www.xilinx.com/ipcenter

Detailed Description

Figure 1-2 shows a board photo with numbered features corresponding to Table 1-1 and the section headings in this document.

15e

18

6

12 16c

15d

11

3

13

4

7b

9

3, 14 (on backside)

15b 15a

15h

 

 

 

 

 

16d

 

10

 

5

17a

7a

 

17b

 

 

 

 

 

2

 

15c

 

 

 

17d

 

8

7c

19b

 

 

 

1

 

17c

 

15g

 

 

 

8

 

19

 

16b

16a 15f

UG526_02 _110409

Figure 1-2: SP605 Board Photo

The numbered features in Figure 1-2 correlate to the features and notes listed in Table 1-1.

Table 1-1:

SP605 Features

 

 

 

 

 

 

Number

Feature

Notes

Schematic

Page

 

 

 

 

 

 

 

1

Spartan-6 FPGA

XC6SLX45T-3FGG484 FPGA

2–7

 

 

 

 

2

DDR3 Component Memory

Micron MT41J64M16LA-187E

9

 

 

 

 

3

SPI Header Ext. x4

Winbond W25Q64VSFIG

18

SPI Flash x4 (on backside)

 

 

 

 

 

 

 

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Detailed Description

Table 1-1:

SP605 Features (Cont’d)

 

 

 

 

 

 

Number

Feature

Notes

Schematic

Page

 

 

 

 

 

 

 

4

Linear BPI Flash x16

Numonyx JS28F256P30T95

19

 

 

 

 

5

SystemACE CompactFlash

XCCACE-TQ144I Controller

20

Socket

 

 

 

 

 

 

 

6

USB JTAG Conn. (USB Mini-B)

USB JTAG Download Circuit

32

 

 

 

 

 

Clock Generation

200 MHz OSC, oscillator socket,

13, 14

 

SMA connectors

 

 

 

 

 

 

 

7

a. 200 MHz oscillator

Epson 200 MHz 2.5V LVDS

14

 

 

 

b. Oscillator socket, single-

MMD Components 2.5V 27 MHz

14

 

 

ended, LVCMOS

 

 

 

 

 

 

 

 

c. SMA connectors

SMA pair P(J41) / N(J38)

13

 

 

 

 

8

GTP port SMA x4 and

MGT RX,TX Pairs x4 SMA MGT

13

MGT Clocking SMA (REFCLK)

REFCLK x2 SMA

 

 

 

 

 

 

9

PCIe 1-lane edge conn.(Gen 1)

Card Edge Connector, 1-lane

12

 

 

 

 

10

SFP Module Cage/Connector

AMP 136073-1

12

 

 

 

 

11

Ethernet 10/100/1000

Marvell M88E1111 EPHY

11

 

 

 

 

12

USB UART (USB-to-UART

Silicon Labs CP2103GM

15

Bridge)

 

 

 

 

 

 

 

13

DVI Codec and Video Connector

Chrontel CH7301C-TF

16,17

 

 

 

 

14

IIC EEPROM (on backside)

ST Micro M24C08-WDW6TP

15

 

 

 

 

 

 

 

10, 11, 14,

 

Status LEDs

 

18, 20, 25,

 

 

 

27, 31, 33

 

 

 

 

 

a. FMC Power Good

 

10

 

 

 

 

 

b. System ACE CF Status

 

11

 

 

 

 

 

c. FPGA INIT and DONE

 

14

15

 

 

 

d. Ethernet PHY Status

 

18

 

 

 

 

 

 

 

e. JTAG USB Status

 

20

 

 

 

 

 

f. FPGA Awake

 

27

 

 

 

 

 

g. TI Power Good

 

31

 

 

 

 

 

h. MGT AVCC, DDR3 Term

 

33

 

Pwr Good

 

 

 

 

 

 

 

 

 

a. User LEDs (4)

Red LEDs (active-High)

14

 

 

 

 

16

b. User Pushbuttons (4)

Active-High

14

 

 

 

c. User DIP Switch (4-pole)

4-pole (active-High)

14

 

 

 

 

 

 

d. User SMA (2)

GPIO x2 SMA

13

 

 

 

 

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Chapter 1: SP605 Evaluation Board

Table 1-1:

SP605 Features (Cont’d)

 

 

 

 

 

 

Number

Feature

Notes

Schematic

Page

 

 

 

 

 

 

 

 

Switches

Power, Configuration,

14, 18, 20,

 

Pushbutton Switches

25

 

 

 

 

 

 

 

a. SP605 Power On-Off Slide

 

25

 

Switch

 

 

 

 

 

 

 

 

17

b. FPGA Mode DIP Switch

 

18

 

 

 

 

c. System ACE CF

 

20

 

Configuration DIP Switch

 

 

 

 

 

 

 

 

 

d. FPGA PROG, CPU Reset,

 

 

 

and System ACE CF Reset

 

14, 20

 

Pushbutton Switches

 

 

 

 

 

 

18

FMC LPC Connector

Samtec ASP-134603-01

10

 

 

 

 

 

a. Power Management

2x TI UCD9240PFC

21, 26

 

Controller

19

 

 

 

 

 

b. Mini-Fit Type 6-Pin, ATX

12V input power connectors

25

 

 

Type 4-pin

 

 

 

 

 

 

 

1. Spartan-6 XC6SLX45T-3FGG484 FPGA

A Xilinx Spartan-6 XC6SLX45T-3FGG484 FPGA is installed on the Embedded

Development Board.

References

See the Spartan-6 FPGA Data Sheet. [Ref 1]

Configuration

The SP605 supports configuration in the following modes:

JTAG (using the included USB-A to Mini-B cable)

JTAG (using System ACE CF and CompactFlash card)

Master SPI x4

Master SPI x4 with off-board device

Linear BPI Flash

For details on configuring the FPGA, see “Configuration Options.”

Mode switch SW1 (see Table 1-30, page 55) is set to 10 = Slave SelectMAP to choose the System ACE CF default configuration.

References

See the Spartan-6 FPGA Configuration User Guide for more information. [Ref 2]

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Detailed Description

I/O Voltage Rails

There are four available banks on the XC6SLX45T-3FGG484 device. Banks 0, 1, and 2 are connected for 2.5V I/O. Bank 3 is used for the 1.5V DDR3 component memory interface of Spartan-6 FPGA’s hard memory controller. The voltage applied to the FPGA I/O banks used by the SP605 board is summarized in Table 1-2.

Table 1-2: I/O Voltage Rail of FPGA Banks

FPGA Bank

I/O Voltage Rail

 

 

0

2.5V

 

 

1

2.5V

 

 

2

2.5V

 

 

3

1.5V

 

 

References

See the Xilinx Spartan-6 FPGA documentation for more information at

http://www.xilinx.com/support/documentation/spartan-6.htm.

2. 128 MB DDR3 Component Memory

There are 128 MB of DDR3 memory available on the SP605 board. A 1-Gb Micron MT41J64M16LA-187E (96-ball) DDR3 memory component is accessible through Bank 3 of the LX45T device. The Spartan-6 FPGA hard memory controller is used for data transfer across the DDR3 memory interface's 16-bit data path using SSTL15 signaling. The maximum data rate supported is 800 Mb/s with a memory clock running at 400 MHz. Signal integrity is maintained through DDR3 resistor terminations and memory on-die terminations (ODT), as shown in Table 1-3 and Table 1-4.

Table 1-3: Termination Resistor Requirements

Signal Name

Board Termination

On-Die Termination

 

 

 

MEM1_A[14:0]

49.9 ohms to VTT

MEM1_BA[2:0]

49.9 ohms to VTT

 

 

 

MEM1_RAS_N

49.9 ohms to VTT

 

 

 

MEM1_CAS_N

49.9 ohms to VTT

 

 

 

MEM1_WE_N

49.9 ohms to VTT

 

 

 

MEM1_CS_N

100 ohms to GND

 

 

 

MEM1_CKE

4.7K ohms to GND

 

 

 

MEM1_ODT

4.7K ohms to GND

 

 

 

MEM1_DQ[15:0]

ODT

 

 

 

MEM1_UDQS[P,N], MEM1_LDQS[P,N]

ODT

 

 

 

MEM1_UDM, MEM1_LDM

ODT

 

 

 

MEM1_CK[P,N]

100 ohm differential at

memory component

 

 

 

 

 

Notes:

1. Nominal value of VTT for DDR3 interface is 0.75V.

SP605 Hardware User Guide

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Chapter 1: SP605 Evaluation Board

Table 1-4: FPGA On-Chip (OCT) Termination External Resistor Requirements

U1 FPGA Pin

FPGA Pin Number

Board Connection for OCT

 

 

 

ZIO

P3

No Connect

 

 

 

RZQ

L6

100 ohms to GROUND

 

 

 

Table 1-5 shows the connections and pin numbers for the DDR3 Component Memory.

Table 1-5: DDR3 Component Memory Connections

U1 FPGA

Schematic Net Name

Memory U42

 

 

 

 

Pin

Pin Number

 

Pin Name

 

 

 

 

 

 

 

 

 

 

K2

MEM1_A0

N3

 

A0

 

 

 

 

 

K1

MEM1_A1

P7

 

A1

 

 

 

 

 

K5

MEM1_A2

P3

 

A2

 

 

 

 

 

M6

MEM1_A3

N2

 

A3

 

 

 

 

 

H3

MEM1_A4

P8

 

A4

 

 

 

 

 

M3

MEM1_A5

P2

 

A5

 

 

 

 

 

L4

MEM1_A6

R8

 

A6

 

 

 

 

 

K6

MEM1_A7

R2

 

A7

 

 

 

 

 

G3

MEM1_A8

T8

 

A8

 

 

 

 

 

G1

MEM1_A9

R3

 

A9

 

 

 

 

 

J4

MEM1_A10

L7

 

A10/AP

 

 

 

 

 

E1

MEM1_A11

R7

 

A11

 

 

 

 

 

F1

MEM1_A12

N7

 

A12/BCN

 

 

 

 

 

J6

MEM1_A13

T3

 

NC/A13

 

 

 

 

 

H5

MEM1_A14

T7

 

NC/A14

 

 

 

 

 

J3

MEM1_BA0

M2

 

BA0

 

 

 

 

 

J1

MEM1_BA1

N8

 

BA1

 

 

 

 

 

H1

MEM1_BA2

M3

 

BA2

 

 

 

 

 

 

 

 

 

 

R3

MEM1_DQ0

G2

 

DQ6

 

 

 

 

 

R1

MEM1_DQ1

H3

 

DQ4

 

 

 

 

 

P2

MEM1_DQ2

E3

 

DQ0

 

 

 

 

 

P1

MEM1_DQ3

F2

 

DQ2

 

 

 

 

 

L3

MEM1_DQ4

H7

 

DQ7

 

 

 

 

 

L1

MEM1_DQ5

H8

 

DQ5

 

 

 

 

 

M2

MEM1_DQ6

F7

 

DQ1

 

 

 

 

 

M1

MEM1_DQ7

F8

 

DQ3

 

 

 

 

 

T2

MEM1_DQ8

C2

 

DQ11

 

 

 

 

 

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UG526 (v1.1.1) February 1, 2010

Detailed Description

Table 1-5:

DDR3 Component Memory Connections (Cont’d)

 

 

 

 

 

 

 

U1 FPGA

 

Schematic Net Name

Memory U42

 

 

 

 

 

Pin

 

 

 

 

 

Pin Number

 

Pin Name

 

 

 

 

 

 

 

 

 

 

 

 

 

T1

 

MEM1_DQ9

C3

 

DQ9

 

 

 

 

 

 

U3

 

MEM1_DQ10

A2

 

DQ13

 

 

 

 

 

 

U1

 

MEM1_DQ11

D7

 

DQ8

 

 

 

 

 

 

W3

 

MEM1_DQ12

A3

 

DQ15

 

 

 

 

 

 

W1

 

MEM1_DQ13

C8

 

DQ10

 

 

 

 

 

 

Y2

 

MEM1_DQ14

B8

 

DQ14

 

 

 

 

 

 

Y1

 

MEM1_DQ15

A7

 

DQ12

 

 

 

 

 

 

 

 

 

 

 

 

H2

 

MEM1_WE_B

L3

 

WE_B

 

 

 

 

 

 

M5

 

MEM1_RAS_B

J3

 

RAS_B

 

 

 

 

 

 

M4

 

MEM1_CAS_B

K3

 

CAS_B

 

 

 

 

 

 

L6

 

MEM1_ODT

K1

 

ODT

 

 

 

 

 

 

K4

 

MEM1_CLK_P

J7

 

CLK_P

 

 

 

 

 

 

K3

 

MEM1_CLK_N

K7

 

CLK_N

 

 

 

 

 

 

F2

 

MEM1_CKE

K9

 

CKE

 

 

 

 

 

 

N3

 

MEM1_LDQS_P

F3

 

LDQS_P

 

 

 

 

 

 

N1

 

MEM1_LDQS_N

G3

 

LDQS_N

 

 

 

 

 

 

V2

 

MEM1_UDQS_P

C7

 

UDQS_P

 

 

 

 

 

 

V1

 

MEM1_UDQS_N

B7

 

UDQS_N

 

 

 

 

 

 

N4

 

MEM1_LDM

E7

 

LDM

 

 

 

 

 

 

P3

 

MEM1_UDM

D3

 

UDM

 

 

 

 

 

 

E3

 

MEM1_RESET_B

T2

 

RESET_B

 

 

 

 

 

 

References

See the Micron Technology, Inc. DDR3 SDRAM Specification for more information. [Ref 12]

Also, see the Spartan-6 FPGA Memory Controller User Guide. [Ref 3]

SP605 Hardware User Guide

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15

UG526 (v1.1.1) February 1, 2010

Chapter 1: SP605 Evaluation Board

3. SPI x4 Flash

The Xilinx Spartan-6 FPGA hosts a SPI interface which is visible to the Xilinx iMPACT configuration tool. The SPI memory device operates at 3.0V; the Spartan-6 FPGA I/Os are 3.3V tolerant and provide electrically compatible logic levels to directly access the SPI flash through a 2.5V bank. The XC6SLX45T-3FGG484 is a master device when accessing an external SPI flash memory device.

The SP605 SPI interface has two parallel connected configuration options (Figure 1-3): an SPI X4 (Winbond W25Q64VSFIG) 64-Mb flash memory device (U32) and a flash programming header (J17). J17 supports a user-defined SPI mezzanine board. The SPI configuration source is selected via SPI select jumper J46. For details on configuring the FPGA, see “Configuration Options.”

 

 

SPI Prog

 

 

 

 

 

 

J17

 

 

 

 

 

 

 

1

FPGA_PROG_B

 

 

 

 

 

 

2

FPGA_D2_MISO3

 

 

 

 

 

3

FPGA_D1_MISO2

 

 

 

TMS

 

 

4

SPI_CS_B

 

 

 

TDI

 

 

5

FPGA_MOSI_CSI_B_MISO0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TDO

 

 

6

FPGA_D0_DIN_MISO_MISO1

Silkscreen

 

 

7

FPGA_CCLK

 

 

TCK

 

 

 

 

 

 

 

8

GND

 

 

 

GND

 

 

 

 

 

3V3

 

 

9

VCC3V3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HDR_1X9

UG526_03_092409

 

 

 

 

 

Figure 1-3: J17 SPI Flash Programming Header

U1

FPGA SPI Interface

U32

SPI x4

Flash

Memory

Winbond

W25Q64VSFIG

J17

DIN, DOUT, CCLK

 

 

 

 

 

 

 

 

 

SPIX4_CS_B

 

 

SPI_CS_B

 

 

1

 

 

 

2

 

 

 

ON = SPI X4 U32

 

 

 

J46

 

 

 

 

 

OFF = SPI EXT. J17

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SPI Select

Jumper

SPI Program

Header UG526_04_092409

Figure 1-4: SPI Flash Interface Topology

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UG526 (v1.1.1) February 1, 2010

Detailed Description

Table 1-6: SPI x4 Memory Connections

U1 FPGA

Schematic Net Name

SPI MEM U32

SPI HDR J17

 

 

 

 

Pin

 

 

 

 

Pin #

Pin Name

Pin #

Pin Name

 

 

 

 

 

 

 

 

 

AB2

FPGA_PROG_B

1

 

 

 

 

 

 

T14

FPGA_D2_MISO3

1

IO3_HOLD_B

2

 

 

 

 

 

 

R13

FPGA_D1_MISO2_R

9

IO2_WP_B

3

 

 

 

 

 

 

AA3

SPI_CS_B

4

TMS

 

 

 

 

 

 

AB20

FPGA_MOSI_CSI_B_MISO0

15

DIN

5

TDI

 

 

 

 

 

 

AA20

FPGA_D0_DIN_MISO_MISO1

8

IO1_DOUT

6

TDO

 

 

 

 

 

 

Y20

FPGA_CCLK

16

CLK

7

TCK

 

 

 

 

 

 

8

GND

 

 

 

 

 

 

9

VCC3V3

 

 

 

 

 

 

J46.2(1)

SPIX4_CS_B

7

CS_B

Notes:

1. Not a U1 FPGA pin

References

See the Winbond Serial Flash Memory Data Sheet for more information. [Ref 13]

See the XPS Serial Peripheral Interface Data Sheet for more information. [Ref 4]

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17

UG526 (v1.1.1) February 1, 2010

Chapter 1: SP605 Evaluation Board

4. Linear BPI Flash

A Numonyx JS28F256P30 Linear Flash memory (U25) on the SP605 (Figure 1-5) provides 32 MB of non-volatile storage that can be used for configuration as well as software storage. The Linear Flash is operated in asynchronous mode.

For details on configuring the FPGA, see “Configuration Options.”

U1

U25

 

 

 

FPGA

ADDR, DATA, CTRL

Numonyx Type P30

 

 

 

 

 

 

 

JS28F256P30

 

 

 

 

 

BPI Flash

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Interface

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

UG526_05_092409

 

 

 

 

Figure 1-5: Linear BPI Flash Interface

 

 

Table 1-7: Linear Flash Connections

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

U1 FPGA Pin

Schematic Net Name

 

U25 BPI FLASH

 

 

 

 

 

 

 

 

Pin Number

 

 

Pin Name

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

N22

 

FLASH_A0

 

29

 

 

A1

 

 

 

 

 

 

 

 

 

 

 

N20

 

FLASH_A1

 

25

 

 

A2

 

 

 

 

 

 

 

 

 

 

 

M22

 

FLASH_A2

 

24

 

 

A3

 

 

 

 

 

 

 

 

 

 

 

M21

 

FLASH_A3

 

23

 

 

A4

 

 

 

 

 

 

 

 

 

 

 

L19

 

FLASH_A4

 

22

 

 

A5

 

 

 

 

 

 

 

 

 

 

 

K20

 

FLASH_A5

 

21

 

 

A6

 

 

 

 

 

 

 

 

 

 

 

H22

 

FLASH_A6

 

20

 

 

A7

 

 

 

 

 

 

 

 

 

 

 

H21

 

FLASH_A7

 

19

 

 

A8

 

 

 

 

 

 

 

 

 

 

 

L17

 

FLASH_A8

 

8

 

 

A9

 

 

 

 

 

 

 

 

 

 

 

K17

 

FLASH_A9

 

7

 

 

A10

 

 

 

 

 

 

 

 

 

 

 

G22

 

FLASH_A10

 

6

 

 

A11

 

 

 

 

 

 

 

 

 

 

 

G20

 

FLASH_A11

 

5

 

 

A12

 

 

 

 

 

 

 

 

 

 

 

K18

 

FLASH_A12

 

4

 

 

A13

 

 

 

 

 

 

 

 

 

 

 

K19

 

FLASH_A13

 

3

 

 

A14

 

 

 

 

 

 

 

 

 

 

 

H20

 

FLASH_A14

 

2

 

 

A15

 

 

 

 

 

 

 

 

 

 

 

J19

 

FLASH_A15

 

1

 

 

A16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

18

 

 

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UG526 (v1.1.1) February 1, 2010

Detailed Description

Table 1-7: Linear Flash Connections (Cont’d)

U1 FPGA Pin

Schematic Net Name

U25 BPI FLASH

 

 

Pin Number

Pin Name

 

 

 

 

 

 

E22

FLASH_A16

55

A17

 

 

 

 

E20

FLASH_A17

18

A18

 

 

 

 

F22

FLASH_A18

17

A19

 

 

 

 

F21

FLASH_A19

16

A20

 

 

 

 

H19

FLASH_A20

11

A21

 

 

 

 

H18

FLASH_A21

10

A22

 

 

 

 

F20

FLASH_A22

9

A23

 

 

 

 

G19

FLASH_A23

26

A24

 

 

 

 

 

 

 

 

AA20

FPGA_D0_DIN_MISO_MISO1

34

DQ0

 

 

 

 

R13

FPGA_D1_MISO2

36

DQ1

 

 

 

 

T14

FPGA_D2_MISO3

39

DQ2

 

 

 

 

AA6

FLASH_D3

41

DQ3

 

 

 

 

AB6

FLASH_D4

47

DQ4

 

 

 

 

Y5

FLASH_D5

49

DQ5

 

 

 

 

AB5

FLASH_D6

51

DQ6

 

 

 

 

W9

FLASH_D7

53

DQ7

 

 

 

 

T7

FLASH_D8

35

DQ8

 

 

 

 

U6

FLASH_D9

37

DQ9

 

 

 

 

AB19

FLASH_D10

40

DQ10

 

 

 

 

AA18

FLASH_D11

42

DQ11

 

 

 

 

AB18

FLASH_D12

48

DQ12

 

 

 

 

Y13

FLASH_D13

50

DQ13

 

 

 

 

AA12

FLASH_D14

52

DQ14

 

 

 

 

AB12

FLASH_D15

54

DQ15

 

 

 

 

 

 

 

 

V13

FMC_PWR_GOOD_FLASH_RST_B

44

RST_B

 

 

 

 

R20

FLASH_WE_B

14

WE_B

 

 

 

 

P22

FLASH_OE_B

32

OE_B

 

 

 

 

P21

FLASH_CE_B

30

CE_B

 

 

 

 

T19

FLASH_ADV_B

46

ADV_B

 

 

 

 

T18

FLASH_WAIT

56

WAIT

 

 

 

 

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19

UG526 (v1.1.1) February 1, 2010

Chapter 1: SP605 Evaluation Board

FPGA Design Considerations for the Configuration Flash

The SP605 has the P30 BPI flash connected to the FPGA dual use configuration pins and is not shared. It can be used to configure the FPGA, and then controlled post-configuration via the FPGA fabric. After FPGA configuration, the FPGA design can disable the configuration flash or access the configuration flash to read/write code or data.

When the FPGA design does not use the configuration flash, the FPGA design must drive the FLASH_OE_B pin High in order to disable the configuration flash and put the flash into a quiescent, low-power state. Otherwise, the flash memory can continue to drive its array data onto the data bus causing unnecessary switching noise and power consumption.

For FPGA designs that access the flash for reading/writing stored code or data, connect the FPGA design or EDK embedded memory controller (EMC) peripheral to the flash through the pins defined in Figure 1-7, page 18.

References

See the Numonyx StrataFlash Embedded Memory Data Sheet for more information. [Ref 14]

In addition, see the Spartan-6 FPGA Configuration User Guide for more information. [Ref 2]

5. System ACE CF and CompactFlash Connector

The Xilinx System ACE CompactFlash (CF) configuration controller allows a Type I or Type II CompactFlash card to program the FPGA through the JTAG port. Both hardware and software data can be downloaded through the JTAG port. The System ACE CF controller supports up to eight configuration images on a single CompactFlash card. The configuration address switches allow the user to choose which of the eight configuration images to use.

The CompactFlash (CF) card shipped with the board is correctly formatted to enable the System ACE CF controller to access the data stored in the card. The System ACE CF controller requires a FAT16 file system, with only one reserved sector permitted, and a sector-per-cluster size of more than one (UnitSize greater than 512). The FAT16 file system supports partitions of up to 2 GB. If multiple partitions are used, the System ACE CF directory structure must reside in the first partition on the CompactFlash, with the xilinx.sys file located in the root directory. The xilinx.sys file is used by the System ACE CF controller to define the project directory structure, which consists of one main folder containing eight sub-folders used to store the eight ACE files containing the configuration images. Only one ACE file should exist within each sub-folder. All folder names must be compliant to the DOS 8.3 short file name format. This means that the folder names can be up to eight characters long, and cannot contain the following reserved characters: < > " / \ |. This DOS 8.3 file name restriction does not apply to the actual ACE file names.

Other folders and files may also coexist with the System ACE CF project within the FAT16 partition. However, the root directory must not contain more than a total of 16 folder and/or file entries, including deleted entries. When ejecting or unplugging the CompactFlash device, it is important to safely stop any read or write access to the CompactFlash device to avoid data corruption.

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UG526 (v1.1.1) February 1, 2010

Detailed Description

System ACE CF error and status LEDs indicate the operational state of the System ACE CF controller:

A blinking red error LED indicates that no CompactFlash card is present

A solid red error LED indicates an error condition during configuration

A blinking green status LED indicates a configuration operation is ongoing

A solid green status LED indicates a successful download

The mode SW1 setting is important because the System ACE CF can fail to configure the FPGA when the mode pins are set to the master modes (Table 1-30, page 55). A configuration failure from the master mode can drive INIT_B low, which blocks the System ACE CF from downloading a configuration ACE file. The FPGA mode pins must be set as specified in Table 1-30 for the System ACE CF configuration solution.

With the mode switch SW1 set to 10 (Slave SelectMAP, Table 1-30), if a Compact Flash (CF) card is installed in the CF socket U37, the System ACE CF will attempt to load a bitstream from the CF card image address pointed to by the image select switch S1.

Every time a CompactFlash card is inserted into the System ACE CF socket, a configuration operation is initiated. Pressing the System ACE CF reset button reprograms the FPGA.

Note: System ACE CF configuration is enabled by way of DIP switch S1. See “17. Switches,” page 46 for more details.

The System ACE CF MPU port (Table 1-8) is connected to the FPGA. This connection allows the FPGA to use the System ACE CF controller to reconfigure the system or access the CompactFlash card as a generic FAT file system.

Table 1-8: System ACE CF Connections

 

U1 FPGA Pin

Schematic Net Name(1)

U17 XCCACETQ144I

 

 

 

 

Pin Number

Pin Name

 

 

 

 

 

 

 

 

 

N6

SYSACE_D0

66

MPD00

 

 

 

 

 

 

N7

SYSACE_D1

65

MPD01

 

 

 

 

 

 

U4

SYSACE_D2

63

MPD02

 

 

 

 

 

 

T4

SYSACE_D3

62

MPD03

 

 

 

 

 

 

P6

SYSACE_D4

61

MPD04

 

 

 

 

 

 

P7

SYSACE_D5

60

MPD05

 

 

 

 

 

 

T3

SYSACE_D6

59

MPD06

 

 

 

 

 

 

R4

SYSACE_D7

58

MPD07

 

 

 

 

 

 

V5

SYSACE_MPA00

70

MPA00

 

 

 

 

 

 

V3

SYSACE_MPA01

69

MPA01

 

 

 

 

 

 

P5

SYSACE_MPA02

68

MPA02

 

 

 

 

 

 

P4

SYSACE_MPA03

67

MPA03

 

 

 

 

 

 

H4

SYSACE_MPA04

45

MPA04

 

 

 

 

 

 

G4

SYSACE_MPA05

44

MPA05

 

 

 

 

 

 

D2

SYSACE_MPA06

43

MPA06

 

 

 

 

 

 

 

 

 

 

SP605 Hardware User Guide

www.xilinx.com

 

21

UG526 (v1.1.1) February 1, 2010

 

 

 

+ 46 hidden pages