Xilinx LogiCORE IP CAN 3.2 User Manual

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LogiCORE™ IP CAN v3.2

Getting Started Guide

UG186 April 19, 2010

Xilinx LogiCORE IP CAN 3.2 User Manual

Xilinx is providing this product documentation, hereinafter “Information,” to you “AS IS” with no warranty of any kind, express or implied. Xilinx makes no representation that the Information, or any particular implementation thereof, is free from any claims of infringement. You are responsible for obtaining any rights you may require for any implementation based on the Information. All specifications are subject to change without notice.

XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE INFORMATION OR ANY IMPLEMENTATION BASED THEREON, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF INFRINGEMENT AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.

Except as stated herein, none of the Information may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx.

© 2005-2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.

Revision History

The following table shows the revision history for the CAN Getting Started Guide.

 

Version

Revision

 

 

 

08/31/05

1.1

Initial Xilinx release.

 

 

 

11/10/05

1.2

Minor updates, advanced version number to 1.2, updated release date.

 

 

 

1/18/06

2.0

Minor updates, advanced version number, updated release date.

 

 

 

9/21/06

3.0

Updated core version to 1.4, updated release date.

 

 

 

8/08/07

3.5

Updated tools for IP1 Jade Minor release; migrated directory structure chapter to new

 

 

template.

 

 

 

04/24/09

4.0

Updated architecture and Operating System support for IP1 Lava release. Other minor

 

 

updates.

 

 

 

06/24/09

4.1

Corrected document on page 24.

 

 

 

09/16/09

4.2

Updated core version to 3.1; updated release date.

 

 

 

04/19/10

5.0

Updated core version to 3.2; updated release date.

 

 

 

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UG186 April 19, 2010

Table of Contents

Schedule of Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Preface: About This Guide

Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Typographical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Chapter 1: Introduction

About the Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Linux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Recommended Design Experience. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Additional Core Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Technical Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Feedback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Chapter 2: Licensing the Core

Before you Begin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 License Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Simulation Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Full System Hardware Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Full . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Obtaining Your License Key. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Simulation License . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Full System Hardware Evaluation License . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Obtaining a Full License . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Installing Your License File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Chapter 3: Quick Start Example Design

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Generating the Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Implementing the Example Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Simulating the Example Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Setting up for Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Functional Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Timing Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

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Chapter 4: Detailed Example Design

Directory and File Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

<project directory> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

<project_directory>/<component name> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

<component_name>example design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

<component_name>/doc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

<component_name>/implement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

<component_name>/implement/results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

<component_name>/simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

<component_name>/simulation/functional . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

simulation/timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Implementation Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Simulation Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Functional Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Timing Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Example Design Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Demonstration Test Bench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Test Bench Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Customizing the Demonstration Test Bench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

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UG186 April 19, 2010

Schedule of Figures

Chapter 1: Introduction

Chapter 2: Licensing the Core

Chapter 3: Quick Start Example Design

Figure 3-1: Example Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 3-2: CAN Main Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Chapter 4: Detailed Example Design

Figure 4-1: Example Design Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 4-2: Demonstration Test Bench. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

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CAN Getting Started Guide

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Preface

About This Guide

The CAN v3.2 Getting Started Guide provides information about generating the LogiCORE™ IP CAN core, customizing and simulating the core with the provided example design, and running the design files through implementation using the Xilinx tools.

Guide Contents

The following chapters are included in this guide:

Preface, “About This Guide” introduces the organization and purpose of this Getting Started Guide and the conventions used in this document.

Chapter 1, “Introduction” describes the core and related information, including recommended design experience, additional resources, technical support, and submitting feedback to Xilinx.

Chapter 2, “Licensing the Core” provides information about licensing the core.

Chapter 3, “Quick Start Example Design” provides instructions to quickly generate the core and run the example design through implementation and simulation.

Chapter 4, “Detailed Example Design”describes the demonstration test bench in detail and provides instructions for how to customize the demonstration test bench for use in an application.

Conventions

This document uses the following conventions. An example illustrates each convention.

Typographical

The following typographical conventions are used in this document:

 

Convention

Meaning or Use

Example

 

 

 

 

 

 

Messages, prompts, and

 

 

Courier font

program files that the system

speed grade: - 100

 

 

displays. Signal names also.

 

 

 

 

 

 

Courier bold

Literal commands you enter in a

ngdbuild design_name

 

syntactical statement

 

 

 

 

 

 

Commands that you select from

File Open

 

Helvetica bold

a menu

 

 

 

 

 

 

 

 

 

 

 

Keyboard shortcuts

Ctrl+C

 

 

 

 

 

 

 

 

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Preface: About This Guide

Convention

Meaning or Use

Example

 

 

 

 

Variables in a syntax statement

 

 

for which you must supply

ngdbuild design_name

 

values

 

 

 

 

Italic font

References to other manuals

See the User Guide for details.

 

 

 

 

 

If a wire is drawn so that it

 

Emphasis in text

overlaps the pin of a symbol, the

 

 

two nets are not connected.

 

 

 

Dark Shading

Items that are not supported or

This feature is not supported

reserved

 

 

 

 

 

 

An optional entry or parameter.

 

Square brackets [ ]

However, in bus specifications,

ngdbuild [option_name]

such as bus[7:0], they are

design_name

 

 

required.

 

 

 

 

Braces { }

A list of items from which you

lowpwr ={on|off}

must choose one or more

 

 

 

 

 

Vertical bar |

Separates items in a list of

lowpwr ={on|off}

choices

 

 

 

 

 

Angle brackets < >

User-defined variable or in code

<directory name>

samples

 

 

 

 

 

Vertical ellipsis

 

IOB #1: Name = QOUT’

 

IOB #2: Name = CLKIN’

.

Repetitive material that has

.

.

been omitted

.

.

 

 

.

 

 

 

 

 

Horizontal ellipsis . . .

Omitted repetitive material

allow block block_name loc1

loc2 ... locn;

 

 

 

 

 

 

The prefix ‘0x’ or the suffix ‘h

A read of address 0x00112975

Notations

indicate hexadecimal notation

returned 45524943h.

 

 

An ‘_n’ means the signal is

usr_teof_n is active low.

 

 

active low

 

 

 

 

 

Online Document

The following linking conventions are used in this document:

Convention

Meaning or Use

Example

 

 

 

 

Cross-reference link to a

See the section “Guide

 

Contents” for details.

Blue text

location in the current

See “Title Formats” in Chapter 1

 

document

 

for details.

 

 

 

 

 

Blue, underlined text

Hyperlink to a website (URL)

Go to www.xilinx.com for the

latest speed files.

 

 

 

 

 

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Chapter 1

Introduction

The LogiCORE™ IP CAN v3.2 core is a compact, full-featured targeted design platform that conforms to ISO 11898-1, CAN2.0A and CAN2.0B standards. Bit rates of up to 1 Mbps are supported. The core size can be optimized using parameterized configurations for acceptance filtering and FIFO depth. The example design in this guide is provided in both Verilog and VHDL.

This chapter introduces the CAN core and provides related information, including system requirements, recommended design experience, additional resources, technical support, and submitting feedback to Xilinx.

About the Core

The CAN core is a Xilinx CORE Generator™ IP core, included in the latest IP Update on the Xilinx IP Center. For detailed information about the core, see www.xilinx.com/xlnx/xebiz/designResources/ip_product_details. For information about licensing options, see Chapter 2, “Licensing the Core.”

System Requirements

Windows

Windows XP 2000 Professional 32-bit/64-bit

Windows Vista Business 32-bit/64-bit

Linux

Red Hat Enterprise Linux WS v4.0 32-bit/64-bit

Red Hat Enterprise Desktop v5.0 32-bit/64-bit (with Workstation Option)

SUSE Linux Enterprise (SLE) desktop and server v10.1 32-bit/64-bit

Software

ISE® software v12.1

Mentor Graphics ModelSim v6.5c and above

Cadence Incisive Enterprise Simulator (IES) v9.2 and above

Synopsys VCS and VCS MX 2009.12 and above

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