Xilinx UG015 User Manual

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Xilinx UG015 User Manual

Virtex-II

Prototype

Platform

User Guide

UG015 / PN0401974 (v1.1) January 14, 2003

R

Virtex-II Prototype Platform

www.xilinx.com

UG015 / PN0401974 (v1.1) January 14, 2003

1-800-255-7778

R

"Xilinx" and the Xilinx logo shown above are registered trademarks of Xilinx, Inc. Any rights not expressly granted herein are reserved.

CoolRunner, RocketChips, Rocket IP, Spartan, StateBENCH, StateCAD, Virtex, XACT, XC2064, XC3090, XC4005, and XC5210 are registered trademarks of Xilinx, Inc.

The shadow X shown above is a trademark of Xilinx, Inc.

ACE Controller, ACE Flash, A.K.A. Speed, Alliance Series, AllianceCORE, Bencher, ChipScope, Configurable Logic Cell, CORE Generator, CoreLINX, Dual Block, EZTag, Fast CLK, Fast CONNECT, Fast FLASH, FastMap, Fast Zero Power, Foundation, Gigabit Speeds...and Beyond!, HardWire, HDL Bencher, IRL, J Drive, JBits, LCA, LogiBLOX, Logic Cell, LogiCORE, LogicProfessor, MicroBlaze, MicroVia, MultiLINX, NanoBlaze, PicoBlaze, PLUSASM, PowerGuide, PowerMaze, QPro, Real-PCI, RocketIO, SelectIO, SelectRAM, SelectRAM+, Silicon Xpresso, Smartguide, Smart-IP, SmartSearch, SMARTswitch, System ACE, Testbench In A Minute, TrueMap, UIM, VectorMaze, VersaBlock, VersaRing, Virtex-II Pro, Virtex-II EasyPath, Wave Table, WebFITTER, WebPACK, WebPOWERED, XABEL, XACT-Floorplanner, XACT-Performance, XACTstep Advanced, XACTstep Foundry, XAM, XAPP, X-BLOX +, XC designated products, XChecker, XDM, XEPLD, Xilinx Foundation Series, Xilinx XDTV, Xinfo, XSI, XtremeDSP and ZERO+ are trademarks of Xilinx, Inc.

The Programmable Logic Company is a service mark of Xilinx, Inc.

All other trademarks are the property of their respective owners.

Xilinx, Inc. does not assume any liability arising out of the application or use of any product described or shown herein; nor does it convey any license under its patents, copyrights, or maskwork rights or any rights of others. Xilinx, Inc. reserves the right to make changes, at any time, in order to improve reliability, function or design and to supply the best product possible. Xilinx, Inc. will not assume responsibility for the use of any circuitry described herein other than circuitry entirely embodied in its products. Xilinx provides any design, code, or information shown or described herein "as is." By providing the design, code, or information as one possible implementation of a feature, application, or standard, Xilinx makes no representation that such implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of any such implementation, including but not limited to any warranties or representations that the implementation is free from claims of infringement, as well as any implied warranties of merchantability or fitness for a particular purpose. Xilinx, Inc. devices and products are protected under U.S. Patents. Other U.S. and foreign patents pending. Xilinx, Inc. does not represent that devices shown or products described herein are free from patent infringement or from any other third party right. Xilinx, Inc. assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made. Xilinx, Inc. will not assume any liability for the accuracy or correctness of any engineering or software support or assistance provided to a user.

Xilinx products are not intended for use in life support appliances, devices, or systems. Use of a Xilinx product in such applications without the written consent of the appropriate Xilinx officer is prohibited.

The contents of this manual are owned and copyrighted by Xilinx. Copyright 1994-2003 Xilinx, Inc. All Rights Reserved. Except as stated herein, none of the material may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of any material contained in this manual may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes.

UG015 / PN0401974 (v1.1) January 14, 2003

www.xilinx.com

Virtex-II Prototype Platform

 

1-800-255-7778

 

Virtex-II Prototype Platform

UG015 / PN0401974 (v1.1) January 14, 2003

The following table shows the revision history for this document.

 

Version

Revision

 

 

 

06/29/01

1.0

Initial Xilinx release.

 

 

 

01/14/03

1.1

Trademark updates and correction to VCCO Supply Jumpers section.

Virtex-II Prototype Platform

www.xilinx.com

UG015 / PN0401974 (v1.1) January 14, 2003

 

1-800-255-7778

 

Table of Contents

Preface: About This Manual

Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Typographical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Virtex-II Prototype Platform

Package Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

CD-ROM Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

1. Power Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Upward On Position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Off Position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Downward On Position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2. Power Supply Jacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3. Configuration Port User PROM and FPGA Header . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4. Frequency Select Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5. Configuration Mode Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Master Serial PROM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Master Serial UPSTREAM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Master Select Map PROM Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Master Select Map UPSTREAM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Slave Serial Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

JTAG Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Select Map Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

External Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5a. Upstream System ACE Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5b. Downstream System ACE Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5c. Upstream Configuration Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5d. Downstream Configuration Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6. JTAG Control Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7. Chip Select Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8. User PROM Socket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

9. JTAG Interface, Service PROM, and FPGA Header . . . . . . . . . . . . . . . . . . . . . . . . . . 23

10. PROM Daughter Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

11. Service FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

12. Prototyping Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

13. VCCO Supply Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

14. VBATT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

15. Oscillator Sockets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

16. Function Generator Clock Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

17. Clock Enable Switches 0-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

18. Clock Enable Switches 8-12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

19. DUT Socket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

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20. Pin Breakout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

21. User LEDs (Active-High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

22. Program Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

23. Reset Switch (Active-Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

24. DONE LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

25. INIT LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

User Programmable Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

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Virtex-II Prototype Platform

 

1-800-255-7778

UG015 / PN0401974 (v1.1) January 14, 2003

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Preface

About This Manual

This document describes the features and operation of Virtex-II Prototype Platform prototype and demonstration boards.

Additional Resources

For additional information, go to http://support.xilinx.com. The following table lists some of the resources you can access from this website. You can also directly access these resources using the provided URLs.

Resource

Description/URL

 

 

Tutorials

Tutorials covering Xilinx design flows, from design entry to

 

verification and debugging

 

http://support.xilinx.com/support/techsup/tutorials/index.htm

 

 

Answer Browser

Database of Xilinx solution records

 

http://support.xilinx.com/xlnx/xil_ans_browser.jsp

 

 

Application Notes

Descriptions of device-specific design techniques and approaches

 

http://support.xilinx.com/apps/appsweb.htm

 

 

Data Book

Pages from The Programmable Logic Data Book, which contains

 

device-specific information on Xilinx device characteristics,

 

including readback, boundary scan, configuration, length count,

 

and debugging

 

http://support.xilinx.com/partinfo/databook.htm

 

 

Problem Solvers

Interactive tools that allow you to troubleshoot your design issues

 

http://support.xilinx.com/support/troubleshoot/psolvers.htm

 

 

Tech Tips

Latest news, design tips, and patch information for the Xilinx

 

design environment

 

http://www.support.xilinx.com/xlnx/xil_tt_home.jsp

 

 

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Preface: About This Manual

Conventions

This document uses the following conventions. An example illustrates each convention.

Typographical

The following typographical conventions are used in this document:

Convention

Meaning or Use

Example

 

 

 

 

Messages, prompts, and

 

Courier font

program files that the system

speed grade: - 100

 

displays

 

 

 

 

Courier bold

Literal commands that you

ngdbuild design_name

enter in a syntactical statement

 

 

 

 

Commands that you select

File Open

Helvetica bold

from a menu

 

 

 

 

 

Keyboard shortcuts

Ctrl+C

 

 

 

 

Variables in a syntax

 

 

statement for which you must

ngdbuild design_name

 

supply values

 

 

 

 

 

 

See the Development System

Italic font

References to other manuals

Reference Guide for more

 

 

information.

 

 

 

 

 

If a wire is drawn so that it

 

Emphasis in text

overlaps the pin of a symbol,

 

 

the two nets are not connected.

 

 

 

 

An optional entry or

 

Square brackets [ ]

parameter. However, in bus

ngdbuild [option_name]

specifications, such as

design_name

 

 

bus[7:0], they are required.

 

 

 

 

Braces { }

A list of items from which you

lowpwr ={on|off}

must choose one or more

 

 

 

 

 

Vertical bar |

Separates items in a list of

lowpwr ={on|off}

choices

 

 

 

 

 

Vertical ellipsis

 

IOB #1: Name = QOUT’

Repetitive material that has

IOB #2: Name = CLKIN’

.

.

.

been omitted

.

.

 

 

.

 

 

 

 

 

Horizontal ellipsis . . .

Repetitive material that has

allow block block_name

 

been omitted

loc1 loc2 ... locn;

 

 

 

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Virtex-II Prototype Platform

 

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Conventions

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Online Document

The following conventions are used in this document:

Convention

Meaning or Use

Example

 

 

 

 

Cross-reference link to a

See the section “Additional

Blue text

location in the current file or

Resources” for details.

in another file in the current

Refer to “Title Formats” in

 

 

document

Chapter 1 for details.

 

 

 

Red text

Cross-reference link to a

See Figure 2-5 in the Virtex-II

location in another document

Handbook.

 

 

 

 

Blue, underlined text

Hyperlink to a website (URL)

Go to http://www.xilinx.com

for the latest speed files.

 

 

 

 

 

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