Xilinx RocketIO X User Manual
R
RocketIO™ X
Transceiver
User Guide
UG035 (v1.5) November 22, 2004
RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004
1-800-255-7778
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RocketIO™ X Transceiver User Guide
UG035 (v1.5) November 22, 2004
The following table shows the revision history for this document.
R
Date Version Revision
10/31/03 1.0 Xilinx initial release. (ADVANCE DRAFT)
11/14/03 1.1 Minor updates made throughout.
12/09/03 1.2 Additions to end of Chapter 2 and minor changes Appendix C.
12/16/03 1.2.1 Change made to “Status Indication.”
UG035 (v1.5) November 22, 2004 www.xilinx.com RocketIO™ X Transceiver User Guide
1-800-255-7778
03/09/04 1.3
Chapter 1, “RocketIO X Transceiver Overview”:
• Modified GT10 Primitive in “Definitions:,” page 25.
• Modified Tabl e 1-2 , pa ge 27 and added Note 3.
• Updated definitions in Primitive Ports, Tab l e 1- 4, pag e 2 8 . Made changes to:
BREFCLKNIN, BREFCLKPIN, PMAREGADDR[5:0], PMAREGDATAIN[7:0],
PMAREGRW, RXBUFSTATUS[1:0], RXCHARISCOMMA, RXCHARISK[7:0],
RXCLKCORCNT[2:0], RXCOMMADETUSE, RXDATA[63:0], RXDATAWIDTH[1:0],
RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXINTDATAWIDTH[1:0],
RXLOSSOFSYNC[1:0], RXNOTINTABLE[7:0], RXRUNDISP[7:0], RXUSRCLK,
RXUSRCLK2, TXBYPASS8B10B[7:0], TXCHARDISPMODE[7:0],
TXCHARDISPVAL[7:0], TXCHARISK[7:0], TXDATA[63:0], TXDATAWIDTH[1:0],
TXGEARBOX64B66BUSE, TXINTDATAWIDTH[1:0], TXKERR[7:0], TXRUNDISP[7:0],
TXSCRAM64B66BUSE, TXUSRCLK, and TXUSRCLK2.
• Updated RocketIO X Transceiver Attributes, Tab l e 1-5, pa ge 35. Made changes to:
ALIGN_COMMA_WORD, CHAN_BOND_MODE, CHAN_BOND_SEQ_1_*[10:0],
CLK_COR_8B10B_DE, CLK_COR_MAX_LAT, CLK_COR_MIN_LAT,
CLK_COR_SEQ_2_USE, CLK_COR_SEQ_LEN, and RX_LOSS_OF_SYNC_FSM.
• Updated text under “Modifiable Attributes,” page 39 and created new Appendix F,
“Modifiable Attributes.”
Chapter 2, “Digital Design Considerations”
• Changed last sentence of the last paragraph under 8B/10B Tab l e , pa ge 48 .
• Added sentence to “RXNOTINTABLE,” page 51.
• Modified Tabl e 2-8 , pa ge 54 .
• Added new heading, “Setting MCOMMA_10B_VALUE, PCOMMA_10B_VALUE, and
COMMA_10B_MASK (Special Note),” page 54.
• Corrected column heading in Table 2-9 , page 55.
• Added small table to show byte alignment options under “ALIGN_COMMA_WORD,”
page 56.
• Modified text under 64B/66B Encoder “Bypassing,” page 57 and made changes to
Table 2-10, page 57.
• Added note to section, “Scrambler,” page 59 (Normal Operation).
• Updated “Functions Common to All Protocols” under section,“Clock Correction,”
page 63.
• Added text to “Clock Correction Sequences,” page 64 (relating to 11th bit format).
• Updated Attribute Setting column in Table 2-13, page 65.
• Added Channel Bonding match logic example under section “Channel Bonding,” page
65.
• Added new section, “Applications Without Channel Bonding.”
• Modified text under “Status Indication,” page 68 and changed Table 2-15, page 68.
• Modified text under “Event Indication,” page 69 and changed Table 2-17, page 69.
Chapter 3, “Clocking and Clock Domains”:
• Added note to “Clock Domain Architecture,” page 73.
• Modified Figure 3-1, page 73, Figure 3-2 and Figure 3-3. Minor editing change to Figure
3-4.
• Modified Figure 3-6 through Figure 3-12.
• Added new section, “PMA,” page 85 and Tab l e 3-3, pa g e 85 .
• Added new section, “Data Path Latency,” page 89, and new tables, Tab l e 3-4 , p a ge 89 ,
and Tab l e 3- 5, pag e 8 9 .
Date Version Revision
RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004
1-800-255-7778
03/09/04 1.3
(Continued)
Chapter 4, “Analog Design Considerations”:
• Modified text (at end of section) and added “LT1963A” to “Voltage Regulation,” page
114.
• Replaced Figure 4-23, page 117.
• Modified first paragraph under “Routing Serial Traces,” page 117.
• Modified Figure 4-31, page 122 and Figure 4-32, page 122.
• Deleted Figure 4-33.
• Chapter 5, “Simulation and Implementation”:
• Modified Tabl e 5-3 , pa ge 12 7 (Loopback Modes).
• Modified section, “Parallel Loopback,” page 128.
• Added new section, “Post/Pre-Driver Serial Loopback,” page 128.
Appendix B, “8B/10B Valid Characters:
• Updated Tab le B- 1, p age 1 37. Changed entries in “Current RD+” column for Data Byte
D9.1, D9.2, D9.3, D9.4, D9.5, D9.6, and D9.7.
Appendix C, “PMA Attribute Programming Bus:
• Added table references in “Register Definition” section and changed the order of the
register definitions.
• Modified Table C-1, page 147.
Appendix D, “Virtex-II Pro to Virtex-II Pro X FPGA Design Migration:
• Added note directly above Figure D-2, page 171.
• Added new section, “Migration Differences.”
Added new “Index.”
Date Version Revision
UG035 (v1.5) November 22, 2004 www.xilinx.com RocketIO™ X Transceiver User Guide
1-800-255-7778
06/29/04 1.4 • Changed the PMA_SPEED attribute description in Tab le 1-5 .
• Modified “Clock Correction Sequences” in Chapter 2 and Tabl e 2- 13.
• Removed section, “Applications Without Channel Bonding” in Chapter 2.
• Modified first paragraph after Figure 2-6, page 50.
• Added illustration to section on “ALIGN_COMMA_WORD,” page 56.
• Added note to “Clock Correction Sequences,” page 64.
• Made change to Figure 2-12, page 67.
• Added sample Verilog code after Table 2-17, page 69.
• Added notes to Tab le 3-3, p a ge 85.
• Removed old Figure 3-2 through Figure 3-12 and related text. Replaced with new
Figure 3-2 through Figure 3-15 and related text.
• Added new section, “PMA” in Chapter 3 and modified Table 3- 3 , page 85.
• Chapter 3, “Clocking and Clock Domains” text revised; new Use Model figures and
Ta bl e 3- 2 added.
• Added note to “Simulation Transmitter Emphasis and Receiver Equalization
Settings,” page 112.
• Added “Conditions” to T
LOCK
row of Table 4-7, page 104.
• Updated Figure 4-32 and the paragraph above it.
• Removed sentence from the first paragraph of “Model Considerations” in Chapter 5.
• Added paragraph to “Post/Pre-Driver Serial Loopback” in Chapter 5 and modified
Ta bl e 5- 4.
• Made changes to Tab le A- 3, p age 1 3 4, Ta b le A-4, p a ge 135,and Tab le A-5, pa ge 136.
• Corrected Tab le B -1 .
• Added new Appendix G, “Related Online Documents.”
• Miscellaneous edits throughout.
11/22/04 1.5 • Changed RXCOMMADET definition in Ta bl e 1 -4 .
• Modified graphic illustrating “ALIGN_COMMA_WORD,” page 56.
• Added text to TXKERR[3] in Table 2-10, page 57 and a note to the table.
• Fixed error in Figure 3-10, page 79.
• Edited Mode Number column in Table 3- 3 , page 85 .
• Edited Tab le 4-6, p a ge 103 and added note.
• Changed VCSO number to EV-2101CA in text and in Figure 4-32, page 122.
• Added PMA attributes and updated Table C-2, page 148; added new PMA attribute
definitions.
• Added XAPP762 and XAPP767 to Appendix G, “Related Online Documents.”Also
added RPT007 to “Characterization Reports.”
Date Version Revision
RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004
1-800-255-7778
UG035 (v1.5) November 22, 2004 www.xilinx.com RocketIO™ X Transceiver User Guide
1-800-255-7778
Contents
Preface: About This Guide
RocketIO X Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
User Guide Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Related Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
User Guide Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Port and Attribute Names. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Comma Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Typographical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Chapter 1: RocketIO X Transceiver Overview
Basic Architecture and Capabilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
RocketIO X Transceiver Instantiations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
HDL Code Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Available Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Primitive Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Modifiable Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Byte Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Chapter 2: Digital Design Considerations
Top-Level Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Transmit Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Receive Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Block Level Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Classification of Signals and Overloading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Static Signals (Control Inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Dynamic Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Selecting the External Configuration (Fabric Interface) . . . . . . . . . . . . . . . . . . . . . . . . . 46
Selecting the Internal Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Clock Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8B/10B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Encoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
RXCHARISK and RXRUNDISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
RXDISPERR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
RXNOTINTABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Vitesse Disparity Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Comma Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Bypass. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Symbol Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
UG035 (v1.5) November 22, 2004 www.xilinx.com RocketIO™ X Transceiver User Guide
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Setting MCOMMA_10B_VALUE, PCOMMA_10B_VALUE, and COMMA_10B_MASK
(Special Note)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Alignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
64B/66B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Encoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Gearbox. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Descrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Block Sync. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Functions Common to All Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Clock Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Append/Remove Idle Clock Correction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Clock Correction Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Determining Correct CLK_COR_MIN_LAT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Channel Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Status and Event Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Status Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Event Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Sample Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Chapter 3: Clocking and Clock Domains
Clock Domain Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Clock Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Use Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
1:1 Use models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
2:1 Use Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
1:2 Use Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Supported Use Models for Each PMA Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
PMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Clock Dependency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Data Path Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Resets and Power Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
PCS Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
PCS/PMA Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Chapter 4: Analog Design Considerations
Serial I/O Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Differential Transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Output Swing and Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
DC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Differential Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Total Jitter (DJ + RJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Deterministic Jitter (DJ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Random Jitter (RJ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Clock and Data Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Receiver Lock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
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Receive Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Low Frequency Boosting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Mid Frequency Boosting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
High Frequency Boosting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Simulation Transmitter Emphasis and Receiver Equalization Settings . . . . . . 112
PCB Design Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Power Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Voltage Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Passive Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
High-Speed Serial Trace Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Routing Serial Traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Differential Trace Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
AC and DC Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Other Important Design Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Powering the RocketIO X Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
POWERDOWN Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Chapter 5: Simulation and Implementation
PMA Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Model Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Simulation Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
SmartModels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
HSPICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
MGT Package Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Diagnostic Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Parallel Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Post/Pre-Driver Serial Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Appendix A: RocketIO X Transceiver Timing Model
Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Input Setup/Hold Times Relative to Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Clock to Output Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Clock Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Timing Diagram and Timing Parameter Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Appendix B: 8B/10B Valid Characters
Valid Data and Control Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Appendix C: PMA Attribute Programming Bus
Interface Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Register Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
MASTERBIAS[1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
VCODAC[5:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
TXDIVRATIO[9:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
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TXBUSWID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
TXLOOPFILTERC[1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
TXLOOPFILTERR[1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
IBOOST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
TXCPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
TXVCODAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
TXVCOGAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
TXVSEL[1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
TXREG[1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
TXDOWNLEVEL[3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
PRDRVOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
EMPOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
SLEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
TXEMPHLEVEL[3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
TXDIGSW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
TXANASW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
RXDIVRATIO[13:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
RXLOOPFILTERC[1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
RXLOOPFILTERR[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
RXVCOSW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
RXCPI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
RXVCODAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
RXVCOGAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
RXVSEL[1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
RXREG[1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
RXVSELCP[1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
RXCPGAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
RXFLTCPT[4:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
VSELAFE[1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
RXFEI[1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
RXFER[9:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
RXFLCPI[1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
BIASEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
TXANAEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
TXDIGEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
RXANAEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
TXEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
RXEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
TXDRVEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
PMAINIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
SEL_DAC_TRAN[3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
SEL_DAC_FIX[3:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
ENDCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
AFE_FLAT_ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Data-Density Independent Phase Adjustment for CDR . . . . . . . . . . . . . . . . . . . . . 164
Appendix D: Virtex-II Pro to Virtex-II Pro X FPGA Design Migration
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Primary Differences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
BREFCLK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Power Regulation and Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
High-Speed Serial I/O Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
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Migration Differences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Port Widths and Byte Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Comma Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Reference Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Clocking and Data Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Channel Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Clock Correction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
64B/66B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
8B/10B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
PMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Serialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Appendix E: Serial Backplane System Design
Transmission Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Connector to PCB Launch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Package to PCB Launch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Appendix F: Modifiable Attributes
Appendix G: Related Online Documents
Application Notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
XAPP752: Virtex-II Pro X OC-48 Jitter Compliance Test Results . . . . . . . . . . . . . . . . 199
XAPP762: RocketIO X Bit-Error Rate Tester Reference Design. . . . . . . . . . . . . . . . . . 199
XAPP767: RocketIO X Transceiver Clock Mode Switcher for
Virtex-II Pro X FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Characterization Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
RPT007: RocketIO™ Transceiver Characterization Report for the
Virtex-II Pro X FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
White Papers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
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Figures
Chapter 1: RocketIO X Transceiver Overview
Figure 1-1: RocketIO X Transceiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Chapter 2: Digital Design Considerations
Figure 2-1: Transmit Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 2-2: Receive Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 2-3: 8B/10B Parallel-to-Serial Conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 2-4: 4-Byte Serial Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 2-5: 10-Bit TX Data Map with 8B/10B Bypassed . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 2-6: 10-Bit RX Data Map with 8B/10B Bypassed . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 2-7: 8b/10b Comma Detection Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 2-8: Block Format Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 2-9: Block Sync State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 2-10: Daisy-Chained Transceiver CHBONDI/CHBONDO Buses . . . . . . . . . . . . . 66
Figure 2-11: XC2VPX20 Device Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 2-12: XC2VPX70 Device Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Chapter 3: Clocking and Clock Domains
Figure 3-1: Reference Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 3-2: BREFCLK 0:1:1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 3-3: BREFCLK 1:1:1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 3-4: BREFCLK 2:1:1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 3-5: TXOUTCLK 1:1:1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 3-6: RXRECCLK 1:1:1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 3-7: BREFCLK 1:2:1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 3-8: BREFCLK 2:2:1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 3-9: TXOUTCLK 2:2:1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 3-10: RXRECCLK 2:2:1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 3-11: BREFCLK 0:1:2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 3-12: BREFCLK 1:1:2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 3-13: BREFCLK 2:1:2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 3-14: TXOUTCLK 2:1:2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 3-15: RXRECCLK 2:1:2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Chapter 4: Analog Design Considerations
Figure 4-1: Differential Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 4-2: Alternating K28.5+ Without Pre-Emphasis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 4-3: K28.5+ With Pre-Emphasis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 4-5: Eye Diagram: With Pre-Emphasis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
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Figure 4-4: Eye Diagram: Without Pre-Emphasis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 4-6: Output Swing versus Pre-Emphasis (%) When DC Coupled . . . . . . . . . . . . . 96
Figure 4-7: Output Swing versus Pre-Emphasis (dB) When DC Coupled . . . . . . . . . . . . 96
Figure 4-8: Output Swing versus De-Emphasis (%) When DC Coupled . . . . . . . . . . . . . 98
Figure 4-9: Output Swing versus De-Emphasis (dB) When DC Coupled. . . . . . . . . . . . . 98
Figure 4-10: Output Swing versus Pre-Emphasis (%) When AC Coupled . . . . . . . . . . . 100
Figure 4-11: Output Swing versus Pre-Emphasis (dB) When AC Coupled . . . . . . . . . . 100
Figure 4-12: Output Swing versus De-Emphasis (%) When AC Coupled . . . . . . . . . . . 102
Figure 4-13: Output Swing versus De-Emphasis (dB) When AC Coupled. . . . . . . . . . . 102
Figure 4-14: Magnitude (dB) vs. Frequency (Hz) Plot
for all 1024 states of RXFER[9:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 4-15: Magnitude (dB) vs. Frequency (Hz) Response
for Four Settings of RXFER[3:2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 4-16: Magnitude (dB) vs. Frequency (Hz) Response
for Four Settings of RXFER[1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 4-17: Magnitude (dB) vs. Frequency (Hz) Response
for Eight Settings of RXFER[6:4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 4-18: Magnitude (dB) vs. Frequency (Hz) Response
for Eight Settings of RXFER[9:7]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 4-19: Magnitude (dB) vs. Frequency (Hz) Response
for Eight Settings (out of 64) of RXFER[9:4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 4-20: Magnitude (dB) vs. Frequency (Hz) Response
for RXFER[9:0] = 0001111111, 110110111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 4-21: Power Supply Circuit Using LT1963 (LT1963A) Regulator. . . . . . . . . . . . . 115
Figure 4-22: Power Filtering Network for One Transceiver. . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 4-23: Example Power Filtering PCB Layout for Four MGTs
(In Device With Internal Capacitors), Bottom Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 4-24: Single-Ended Trace Geometry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 4-25: Microstrip Edge-Coupled Differential Pair . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 4-26: Stripline Edge-Coupled Differential Pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 4-27: Transmit Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 4-28:
Receive Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 4-29: AC-Coupled Serial Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 4-30: DC-Coupled Serial Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 4-31: Reference Clock Oscillator Interface up to 400 MHz . . . . . . . . . . . . . . . . . . 122
Figure 4-32: Reference Clock Oscillator Interface above 400 MHz . . . . . . . . . . . . . . . . . 122
Chapter 5: Simulation and Implementation
Figure 5-1: PMA Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Appendix A: RocketIO X Transceiver Timing Model
Figure A-1: RocketIO X Transceiver Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure A-2: RocketIO X Transceiver Timing Relative to Clock Edge . . . . . . . . . . . . . . . 133
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Appendix B: 8B/10B Valid Characters
Appendix C: PMA Attribute Programming Bus
Figure C-1: PMA Attribute Bus Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure C-2: Fine Loop Charge Pump. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure C-3: Sampling Point Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Appendix D: Virtex-II Pro to Virtex-II Pro X FPGA Design Migration
Figure D-1: REFCLK/BREFCLK Selection Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Figure D-2: Power Filtering Network for One Transceiver . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure D-3: Transmit Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure D-4: Receive Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Appendix E: Serial Backplane System Design
Figure E-1: Backdrilling Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Figure E-2: Backdrilled vs Non-Backdrilled Channel Characteristics. . . . . . . . . . . . . . . 178
Appendix F: Modifiable Attributes
Appendix G: Related Online Documents
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Ta ble s
Chapter 1: RocketIO X Transceiver Overview
Table 1-1: Number of RocketIO X Cores per Device Type . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 1-2: Communications Standards Supported by RocketIO X Transceiver . . . . . . . 27
Table 1-3: Supported RocketIO X Transceiver Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 1-4: Primitive Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 1-5: RocketIO X Transceiver Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 1-6: Control/Status Bus Association to Data Bus Byte Paths. . . . . . . . . . . . . . . . . . . 39
Chapter 2: Digital Design Considerations
Table 2-1: PCS Interface Choice. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 2-2: Selecting the External Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 2-3: Selecting the Internal Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 2-4: Data Width Clock Ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 2-5: Running Disparity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 2-6: 8B/10B Bypassed Signal Significance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 2-7: 8B/10B Bypassed Signal Significance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 2-8: Symbol Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 2-9: Data Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 2-10: 64B/66B Bypassing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 2-11: Transmit 64B/66B Encoder Control Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 2-12: Control Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 2-13: Clock Correction Sequence/Data Correlation for 16-Bit Data Port . . . . . . . . 65
Table 2-14: Channel Bond Alignment Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 2-15: Signal Values for a Pointer Difference Status . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 2-16: Signal Values for a Channel Bonding Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 2-17: Signal Values for Event Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Chapter 3: Clocking and Clock Domains
Table 3-1: Clock Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 3-2: Supported Use Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 3-3: Supported Standards, Speeds, Bus Widths, and Frequencies for
Reference Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 3-4: Latency Through Various Transmitter Components/Processes . . . . . . . . . . . . 89
Table 3-5: Latency Through Various Receiver Components/Processes . . . . . . . . . . . . . . . 89
Table 3-6: Power Control Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Chapter 4: Analog Design Considerations
Table 4-1: Differential Transmitter Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 4-2: Output Swing versus Pre-Emphasis (DC Coupled) . . . . . . . . . . . . . . . . . . . . . . 95
Table 4-3: Output Swing versus De-Emphasis (DC Coupled). . . . . . . . . . . . . . . . . . . . . . . 97
Table 4-4: Output Swing versus Pre-Emphasis (AC Coupled) . . . . . . . . . . . . . . . . . . . . . . 99
Table 4-5: Output Swing versus De-Emphasis (AC Coupled). . . . . . . . . . . . . . . . . . . . . . 101
Table 4-6: Differential Receiver Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 4-7: CDR Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
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Table 4-8: PMARXLOCKSEL[1:0] Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 4-9: Example Signal Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 4-10: Settings and Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 4-11: Transceiver Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Chapter 5: Simulation and Implementation
Table 5-1: LOC Grid and Package Pins Correlation for FF896Package . . . . . . . . . . . . . . 126
Table 5-2: LOC Grid and Package Pins Correlation for FF1704 Packages . . . . . . . . . . . . 126
Table 5-3: LOOPBACK Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 5-4: Recommended Settings for Serial Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Appendix A: RocketIO X Transceiver Timing Model
Table A-1: RocketIO X Clock Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table A-2: Parameters Relative to RX User Clock (RXUSRCLK) . . . . . . . . . . . . . . . . . . . 134
Table A-3: Parameters Relative to RX User Clock2 (RXUSRCLK2) . . . . . . . . . . . . . . . . . 134
Table A-4: Parameters Relative to TX User Clock2 (TXUSRCLK2) . . . . . . . . . . . . . . . . . 135
Table A-5: PMA Clock Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table A-6: Miscellaneous Clock Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Appendix B: 8B/10B Valid Characters
Table B-1: Valid Data Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table B-2: Valid Control “K” Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Appendix C: PMA Attribute Programming Bus
Table C-1: PMA Attribute Bus Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table C-2: PMA Attribute Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table C-3: MASTERBIAS[1:0] Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table C-4: TX Clock Multiplier Ratio Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table C-5: TXCLK0 Divider Ratio Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table C-6: TXOUTCLK Divider Ratio Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table C-7: TXBUSWID Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table C-8: TXLOOPFILTERC[1:0] Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table C-9: TXLOOPFILTERR[1:0] Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table C-10: IBOOST Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table C-11: TXCPI Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table C-12: TXVCODAC Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table C-13: TXVCOGAIN Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table C-14: TXVSEL[1:0] Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table C-15: TXREG[1:0] Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table C-16: PRDRVOFF Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table C-17: EMPOFF Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table C-18: SLEW Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table C-19: TXDIGSW Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table C-20: TXANASW Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table C-21: RX Clock Multiplier Ratio Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table C-22: RXCLK0 Divider Ratio Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table C-23: RXRECCLK Divider Ratio Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table C-24: VCO Divider Ratio Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
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Table C-25: BREFCLK Divider Ratio Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table C-26: RXLOOPFILTERC[1:0] Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table C-27: RXLOOPFILTERR[2:0] Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table C-28: RXVCOSW Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table C-29: RXCPI[1:0] Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table C-30: RXVCODAC Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table C-31: RXVCOGAIN Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table C-32: RXVSEL[1:0] Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table C-33: RXREG[1:0] Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table C-34: RXVSELCP[1:0] Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table C-35: RXCPGAIN Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table C-36: VSELAFE[1:0] Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table C-37: RXFEI[1:0] Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table C-38: RXFLCPI[1:0] Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table C-39: BIASEN Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table C-40: TXANAEN Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table C-41: TXDIGEN Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table C-42: RXANAEN Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table C-43: TXEN Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table C-44: RXEN Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table C-45: TXDRVEN Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table C-46: Tail Current Value Vs. Programmability Code. . . . . . . . . . . . . . . . . . . . . . . . 165
Table C-47: Allowed Programmable Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Appendix D: Virtex-II Pro to Virtex-II Pro X FPGA Design Migration
Table D-1: BREFCLK Differences Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table D-2: BREFCLK Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table D-3: Virtex-II Pro X BREFCLK Pin Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table D-4: Voltage Changes for Virtex-II Pro X FPGA Power Regulation . . . . . . . . . . . 171
Appendix E: Serial Backplane System Design
Appendix F: Modifiable Attributes
Table F-1: Default Attribute Values: GT10_CUSTOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Table F-2: Default Attribute Values: GT10_AURORA_1, GT10_AURORA_2,
and GT10_AURORA_4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Table F-3: Default Attribute Values: GT10_AURORAX_4, GT10_AURORAX_8,
and GT10_10GE_4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Table F-4: Default Attribute Values: GT10_10GE_8, GT10_10GFC_4,
and GT10_10GFC_8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Table F-5: Default Attribute Values: GT10_PCI_EXPRESS_1, GT10_PCI_EXPRESS_2,
and GT10_PCI_EXPRESS_4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table F-6: Default Attribute Values: GT10_INFINIBAND_1, GT10_INFINIBAND_2,
and GT10_INFINIBAND_4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Table F-7: Default Attribute Values: GT10_XAUI_1, GT10_XAUI_2,
and GT10_XAUI_4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table F-8: Default Attribute Values: GT10_OC192_4 and GT10_OC192_8. . . . . . . . . . . 195
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Table F-9: Default Attribute Values: GT10_OC48_1, GT10_OC48_2, and
GT10_OC48_4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Appendix G: Related Online Documents
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Preface
About This Guide
RocketIO X Features
RocketIO X transceivers have flexible, programmable features that allow a multi-gigabit
serial transceiver (MGT) to be easily integrated into any Virtex-II Pro X design:
• Variable speed full-duplex transceiver, allowing 2.488 Gb/s to 10.3125 Gb/s baud
transfer rates, including specific baud rates used by various standards (listed in
Tabl e 1-2 , pa ge 27 )
• Depending on the Virtex-II Pro X device, from 8 to 20 transceiver modules on an FPGA
• Monolithic clock synthesis and clock recovery system, eliminating the need for
external components
• Automatic lock-to-reference function
• Serial output differential swing that can be programmed between 200 mV to 1600 mV
(peak-peak), allowing compatibility with other serial system voltage levels
• Levels of programmable emphasis from 0 to 500% (not all emphasis and swing
combinations can be attained)
• Receiver equalization
• AC and DC coupling
• On-chip termination of 50Ω (eliminating the need for external termination resistors)
• Pre and post driver serial and parallel TX to RX internal loopback modes for testing
operability
• Programmable comma detection to allow for any protocol and detection of any 10-bit
character
• 8B/10B and 64B/66B encoding blocks
User Guide Organization
This guide is organized as follows:
• Preface, “About This Guide” – Summary of RocketIO X transceiver features, which allow
a multi-gigabit serial transceiver to be integrated easily into any Virtex-II Pro X design.
• Chapter 1, “RocketIO X Transceiver Overview” – RocketIO X transceiver basic
architecture and capabilities. Includes instantiations, VHDL code examples, available
ports, primitive and modifiable attributes, and byte mapping.
• Chapter 2, “Digital Design Considerations” – Ports and attributes for the provided
communications protocol primitives; transceiver instantiation; 8B/10B encoding;
64B/66B encoding; channel bonding.
• Chapter 3, “Clocking and Clock Domains” – Clock domain architecture; clock ports,
and examples for clocking and reset schemes.
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• Chapter 4, “Analog Design Considerations” – RocketIO X serial overview; pre-
emphasis; jitter; clock/data recovery; PCB design requirements.
• Chapter 5, “Simulation and Implementation” – Simulation models and
considerations; implementation tools; and debugging and diagnostics.
• Appendix A, “RocketIO X Transceiver Timing Model” – Timing parameters
associated with the RocketIO X transceiver core.
• Appendix B, “8B/10B Valid Characters” – Valid data and K characters table.
• Appendix C, “PMA Attribute Programming Bus” – RocketIO X transceiver simple,
parallel programming bus for dynamically configuring the PMA attribute settings.
For Advanced Users Only.
• Appendix D, “Virtex-II Pro to Virtex-II Pro X FPGA Design Migration” – Important
differences regarding migration from Virtex-II Pro™ to the Virtex-II Pro X FPGAs.
Highlights relevant PCB, power supply, and reference clock differences.
• Appendix E, “Serial Backplane System Design” – Additional PCB design guidelines to
meet the demands of the RocketIO X transceiver for operation above 3.125 Gb/s.
Related Information
For a complete menu of online information resources available on the Xilinx website, visit
http://www.xilinx.com/virtex2pro x/
.
For a comprehensive listing of available tutorials and resources on network technologies
and communications protocols, visit http://www.iol.unh.edu/training/
.
Additional Resources
For additional information, go to http://support.xilinx.com. The following table lists
some of the resources available on this website. Use the URLs to access these resources
directly.
Resource Description/URL
Tutorials Tutorials covering Xilinx design flows, from design entry to
verification and debugging
http://support.xilinx.com/support/techsup/tutorials/index.htm
Answer Browser Database of Xilinx solution records
http://support.xilinx.com/xlnx/xil_ans_browser.jsp
Application Notes Descriptions of device-specific design techniques and approaches
http://support.xilinx.com/apps/appsweb.htm
Data Sheets Device-specific information on Xilinx device characteristics,
including readback, boundary scan, configuration, length count,
and debugging
http://support.xilinx.com/xlnx/xweb/xil_publications_index.jsp
Problem Solvers Interactive tools that allow you to troubleshoot your design issues
http://support.xilinx.com/support/troubleshoot/psolvers.htm
Tech Tips Latest news, design tips, and patch information for the Xilinx
design environment
http://www.support.xilinx.com/xlnx/xil_tt_home.jsp
RocketIO™ X Transceiver User Guide www.xilinx.com 23
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User Guide Conventions
This document uses the following conventions. An example illustrates each convention.
Port and Attribute Names
Input and output ports of the RocketIO X transceiver primitives are denoted in upper-case
letters. Attributes of the RocketIO X transceiver are denoted in upper-case letters with
underscores. Trailing numbers in primitive names denote the byte width of the data path.
These values are preset and not modifiable. When assumed to be the same frequency,
RXUSRCLK and TXUSRCLK are referred to as USRCLK and can be used interchangeably.
This also holds true for RXUSRCLK2, TXUSRCLK2, and USRCLK2.
Comma Definition
A comma is a “K” character used by the transceiver to align the serial data on a
byte/half-word boundary (depending on the protocol used), so that the serial data is
correctly decoded into parallel data.
Typographical
The following typographical conventions are used in this document:
Convention Meaning or Use Example
Courier font
Messages and prompts that
the system displays
speed grade: - 100
Courier bold
Literal commands that you
enter in a syntactical statement
ngdbuild
design_name
Helvetica bold
Commands that you select
from a menu
File → Open
Keyboard shortcuts Ctrl+C
Italic font
Variables in syntax statements
for which you must supply
values
ngdbuild
design_name
References to other manuals
See the Virtex-II Pro User Guide
for more information.
Emphasis in text
If a wire is drawn so that it
overlaps the pin of a symbol,
the two nets are not connected.
Square brackets [ ]
Optional entry / parameter;
required in bus specifications,
such as bus[7:0]
ngdbuild [
option_name
]
design_name
Braces { }
A list of items from which you
must choose one or more
lowpwr ={on|off}
Vertical bar |
Separates items in a list of
choices
lowpwr ={on|off}
Ellipsis . . .
Repetitive material that has
been omitted
allow block
block_name
loc1 loc2 ... locn;
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Chapter 1
RocketIO X Transceiver Overview
Basic Architecture and Capabilities
Note: The definitions, descriptions, and recommendations in this user guide reflect Step 1
silicon. For Step 0 silicon, see the Errata for special considerations.
The RocketIO X block diagram is illustrated in Figure 1-1. Depending on the device, a
Virtex-II Pro X FPGA has between 8 and 20 transceiver modules, as shown in Tab le 1 -1.
Definitions:
• Attribute – An attribute is a control parameter to configure the RocketIO X
transceiver. There are both primitive ports (traditional I/O ports for control and
status) and transceiver attributes. Transceiver attributes are also controls to the
transceiver that regulate data widths and encoding rules, but controls that are
configured as a group in “soft” form through the invocation of a primitive.
• GT10 Primitive – A primitive is a pre-designed collection of attribute values that
accomplish a known data rate, encoding type, data width, etc. A single primitive
invocation, for example, OC-192 mode which configures all the dozens of pertinent
attributes to their correct values in a single step.
The transceiver module is designed to operate at any serial bit rate in the range of
2.488 Gb/s to 10.3125 Gb/s per channel, including the specific bit rates used by the
communications standards listed in Tab le 1- 2 , p age 2 7 . Data-rate specific attribute settings
are set appropriately in the GT10 primitives.
Table 1-1: Number of RocketIO X Cores per Device Type
Device RocketIO X Cores
XC2VPX20 8
XC2VPX70 20
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Chapter 1: RocketIO X Transceiver Overview
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Figure 1-1: RocketIO X Transceiver Block Diagram
FPGA FABRIC
MULTI-GIGABIT TRANSCEIVER CORE
Serializer
RXP
TXP
Clock
Manager
Power Down
PACKAGE
PINS
Deserializer
Comma
Detect
Realign
8B/10B
Decoder
TX
FIFO
Channel Bonding
and
Clock Correction
CHBONDI[4:0]
CHBONDO[4:0]
8B/10B
Encoder
RX
Elastic
Buffer
Output
Polarity
RXN
GNDA
TXN
UG035_01_111303
POWERDOWN
RXRECCLK
RXPOLARITY
RXREALIGN
RXCOMMADET
RXRESET
RXCLKCORCNT[2:0]
RXLOSSOFSYNC[1:0]
RXDATA[63:0]
RXNOTINTABLE[7:0]
RXDISPERR[7:0]
RXCHARISK[7:0]
RXCHARISCOMMA[7:0]
RXRUNDISP[7:0]
RXBUFSTATUS[1:0]
ENCHANSYNC
RXUSRCLK
RXUSRCLK2
CHBONDDONE
TXBUFERR
TXDATA[63:0]
TXBYPASS8B10B[7:0]
TXCHARISK[7:0]
TXCHARDISPMODE[7:0]
TXCHARDISPVAL[7:0]
TXKERR[7:0]
TXRUNDISP[7:0]
TXPOLARITY
TXINHIBIT
LOOPBACK[1:0]
TXRESET
REFCLK
REFCLK2
REFCLKSEL
ENPCOMMAALIGN
ENMCOMMAALIGN
TXUSRCLK
TXUSRCLK2
VTRX
AVCCAUXTX
VTTX
AVCCAUXRX
2.5V
TX/RX GND
Termination Supply RX
1.5V
Termination Supply TX
Post Driver Serial Loopback Path
Parallel Loopback Path
BREFCLKP
BREFCLKN
64B/66B
Block Sync
64B/66B
Decoder
Gear
Box
Scrambler
64B/66B
Encoder
PMA
Attribute
Load
PMAREGDATAIN[7:0]
RXCOMMADETUSE
RXDATAWIDTH[1:0]
RXDECC64B66BUSE
PMAINIT
PMAREGADDR[5:0]
PMAREGRW
PMAREGSTROBE
PMARXLOCKSEL[1:0]
PMARXLOCK
RXDEC8B10BUSE
RXDESCRAM64B66BUSE
REFCLKBSEL
RXBLCOKSYNC64B66BUSE
RXSLIDE
TXINTDATAWIDTH[1:0]
TXSCRAM64B66BUSE
TXOUTCLK
RXIGNOREBTF
RXINTDATAWIDTH[1:0]
TXDATAWIDTH[1:0]
TXENC64B66BUSE
TXENC8B10BUSE
TXGEARBOX64B66BUSE
Pre-Driver Loopback Path
64B/66B
Descrambler
Clock /
Reset
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.
Ta bl e 1- 3 lists the transceiver primitives provided. These primitives carry attributes set to
default values for the communications protocols listed in Ta bl e 1 -2 . Data widths of one,
two, and four bytes (lower speeds) or four and eight bytes (higher speeds) are selectable
for the various protocols.
There are three ways to configure the RocketIO X transceiver:
• Static properties can be set through attributes in the HDL code. Use of attributes are
covered in detail in “Primitive Attributes,” page 35.
• Dynamic changes can be made to the attributes via the attribute programming bus.
See Appendix C, “PMA Attribute Programming Bus”for details.
• Dynamic changes can be made through the ports of the primitives.
Table 1-2: Communications Standards Supported by RocketIO X Transceiver
Mode Channels
(1)
(Lanes) I/O Bit Rate (Gb/s)
SONET OC-48 1 2.488
PCI Express 1, 2, 4, 8, 16 2.5
Infiniband 1, 4, 12 2.5
XAUI (10-Gigabit Ethernet) 4 3.125
XAUI (10-Gigabit Fibre Channel) 4 3.1875
SONET OC-192
(2)
1 9.95328
Aurora (Xilinx protocol) 1, 2, 3, 4, ... 2.488 – 10.3125
Custom Mode 1, 2, 3, 4, ... 2.488 – 10.3125
Notes:
1. One channel is considered to be one transceiver.
2. See Solution Record 19020
for implementation recommendations.
Table 1-3: Supported RocketIO X Transceiver Primitives
Primitive Description Primitive Description
GT10_CUSTOM Fully customizable by user GT10_XAUI_4 10GE XAUI, 4-byte data path
GT10_OC48_1 SONET OC-48, 1-byte data path GT10_AURORA_1 Xilinx protocol, 1-byte data path
GT10_OC48_2 SONET OC-48, 2-byte data path GT10_AURORA_2 Xilinx protocol, 2-byte data path
GT10_OC48_4 SONET OC-48, 4-byte data path GT10_AURORA_4 Xilinx protocol, 4-byte data path
GT10_PCI_EXPRESS_1 PCI Express, 1-byte data path GT10_OC192_4 SONET OC-192, 4-byte data path
GT10_PCI_EXPRESS_2 PCI Express, 2-byte data path GT10_OC192_8 SONET OC-192, 8-byte data path
GT10_PCI_EXPRESS_4 PCI Express, 4-byte data path GT10_10GE_4 10Gbit Ethernet, 4-byte data path
GT10_INFINIBAND_1 Infiniband, 1-byte data path GT10_10GE_8 10Gbit Ethernet, 8-byte data path
GT10_INFINIBAND_2 Infiniband, 2-byte data path GT10_10GFC_4 10Gbit Fibre Channel, 4-byte data path
GT10_INFINIBAND_4 Infiniband, 4-byte data path GT10_10GFC_8 10Gbit Fibre Channel, 8-byte data path
GT10_XAUI_1 10GE XAUI, 1-byte data path GT10_AURORAX_4 Xilinx 10G protocol, 4-byte data path
GT10_XAUI_2 10GE XAUI, 2-byte data path GT10_AURORAX_8 Xilinx 10G protocol, 8-byte data path
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The RocketIO X transceiver consists of the Physical Media Attachment (PMA) and
Physical Coding Sublayer (PCS). The PMA contains the serializer/deserializer (SERDES),
TX and RX buffers, clock generator, and clock recovery circuitry. The PCS contains the
8B/10B encoder/decoder, 64B/66B encoder/decoder/scrambler/descrambler, and the
elastic buffer supporting channel bonding and clock correction. Refer again to Figure 1-1,
page 26, showing the RocketIO X transceiver top-level block diagram and FPGA interface
signals.
RocketIO X Transceiver Instantiations
For the different clocking schemes, several things must change, including the clock
frequency for USRCLK and USRCLK2 discussed in Chapter 3, “Clocking and Clock
Domains.” The data and control ports for GT10_CUSTOM always use maximum bus
widths. To implement the designs that do not take full advantage of the bus width,
concatenate zeros onto inputs and the wires for outputs for Verilog designs, and set
outputs to open and concatenate zeros on unused input bits for VHDL designs.
HDL Code Examples
The Architecture Wizard can be used to create instantiation templates. This wizard creates
code and instantiation templates that define the attributes for a specific application.
Available Ports
Ta bl e 1- 4 contains the port descriptions of all primitives. The RocketIO X transceiver
primitives contain 72 ports. The differential serial data ports (RXN, RXP, TXN, and TXP)
are connected directly to external pads; the remaining 68 ports are all accessible from the
FPGA logic.
Table 1-4: Primitive Ports
Port I/O Port Size Definition
BREFCLKNIN I 1 Differential BREFCLK negative input from the BREFCLK
pad. See Figure 4-31 and Figure 4-32 for analog
considerations.
BREFCLKPIN I 1 Differential BREFCLK positive input from the BREFCLK
pad. See Figure 4-31 and Figure 4-32 for analog
considerations.
CHBONDDONE O 1 Indicates a receiver has successfully completed channel
bonding when asserted High.
CHBONDI[4:0] I 5 The channel bonding control that is used only by “slaves”
which is driven by a transceiver's CHBONDO port. See
Figure 2-10.
CHBONDO[4:0] O 5 Channel bonding control that passes channel bonding and
clock correction control to other transceivers. See
Figure 2-10.
ENCHANSYNC I 1 Control from the fabric to the transceiver enables the
transceiver to perform channel bonding.
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ENMCOMMAALIGN I 1 Selects realignment of incoming serial bitstream on minus-
comma. When asserted realigns serial bitstream byte
boundary to where minus-comma is detected.
ENPCOMMAALIGN I 1 Selects realignment of incoming serial bitstream on plus-
comma. When reasserted realigns serial bitstream byte
boundary to where plus-comma is detected.
LOOPBACK[1:0] I 2 Selects the three loopback test modes. These modes are
internal parallel, pre-driver serial, and post-driver serial.
See Table 5-3, page 127 for more information.)
PMAINIT I 1 When asserted High and then deasserted Low, reloads the
PMA coefficients into the PMA from the attribute
PMA_SPEED and then resets the PCS.
PMAREGADDR[5:0] I 6 PMA attribute bus address. This input is asynchronous.
PMAREGDATAIN[7:0] I 8 PMA attribute bus data input. This input is asynchronous.
PMAREGRW I 1 PMA attribute bus read/write control. This input is
asynchronous.
PMAREGSTROBE I 1 PMA attribute bus strobe. Note: This input is asynchronous.
PMARXLOCK O 1 Indicates that the receive PLL has locked in the fine loop.
When RX PLL is set to “Lock to Data,” this signal is always
a logic 1.
PMARXLOCKSEL[1:0] I 2 Selects determination of lock in the receive PLL. See
Tabl e 4-8 , pa ge 10 4.
POWERDOWN I 1 Shuts down both the receiver and transmitter sides of the
transceiver when asserted High. Note: This input is
asynchronous.
REFCLK I 1 The reference clock net that is embedded within the fabric.
REFCLK2 I 1 An alternative to REFCLK. Can be selected by the
REFCLKSEL.
REFCLKBSEL I 1 Selects between BREFCLK and REFCLK/REFCLK2 as
reference clock. Asserted selects BREFCLK. Deasserted
selects REFCLK or REFCLK2, depending on REFCLKSEL.
REFCLKSEL I 1 Selects between REFCLK or REFCLK2 as reference clock.
Deasserted selects REFCLK. Asserted selects REFCLK2.
RXBUFSTATUS[1:0] O 2 Receiver elastic buffer status. Indicates the status of the
receive FIFO pointers, channel bonding skew, and clock
correction events. See “Status and Event Bus,” page 68.
RXBLOCKSYNC64B66BUSE I 1 If asserted, the block sync is used. If deasserted, the block
sync logic is bypassed.
RXCHARISCOMMA[7:0] O 1, 2, 4, 8
(1)
Indicates the reception of K28.0, K28.5, K28.7, and some out
of band commas (depending on the setting of
DEC_VALID_COMMA_ONLY by the 8B/10B decoder.
Table 1-4: Primitive Ports (Continued)
Port I/O Port Size Definition
30 www.xilinx.com RocketIO™ X Transceiver User Guide
1-800-255-7778 UG035 (v1.5) November 22, 2004
Chapter 1: RocketIO X Transceiver Overview
R
RXCHARISK[7:0] O 1, 2, 4, 8
(1)
If 8B/10B decoding is enabled, it indicates that the received
data is a “K” character when asserted. Included in Bytemapping. If 8B/10B decoding is bypassed, it remains as the
first bit received (Bit “a”) of the 10-bit encoded data (see
Figure 2-3).
RXCLKCORCNT[2:0] O 3 Status that denotes occurrence of clock correction, channel
bonding, and receive FIFO pointer status. This status is
synchronized on the incoming RXDATA. See “Clock
Correction,” page 63 and “Status and Event Bus,” page 68.
RXCOMMADET O 1 Indicates that the symbol defined by
PCOMMA_10B_VALUE (IF PCOMMA_DETECT is
asserted) and/or MCOMMA_10B_VALUE (if
MCOMMA_DETECT is asserted) has been received.
RXCOMMADETUSE I 1 If asserted High, the comma detect is used. If deasserted, the
comma detect is bypassed.
RXDATA[63:0] O 8, 16, 32, 64
(2)
Up to eight bytes of decoded (8B/10B encoding) or encoded
(8B/10B bypassed) received data at the user fabric.
RXDATAWIDTH[1:0] I 2 (00, 01, 10, 11) Indicates width of FPGA parallel bus. See
“Bus Interface” in Chapter 2.
RXDEC64B66BUSE I 1 If asserted High, the 64/B66B decoder is used. If deasserted,
the 64/66 decoder is bypassed.
RXDEC8B10BUSE I 1 If asserted High, the 8B/10B decoder is used. If deasserted,
the 8b/10b decoder is bypassed.
CLK_COR_8B10B_DE = RXDEC8B10BUSE
RXDESCRAM64B66BUSE I 1 If asserted High, the scrambler is used. If deasserted, the
scrambler is bypassed.
RXDISPERR[7:0] O 1, 2, 4, 8
(1)
If 8B/10B encoding is enabled it indicates whether a
disparity error has occurred on the serial line. Included in
Byte-mapping scheme.
RXIGNOREBTF I 1 If asserted High, the block type field (BTF) is ignored in the
64/66 decoder. Instead of reporting an error, the block is
passed on as is. If deasserted, unrecognized BTFs are
marked as error blocks.
RXINTDATAWIDTH[1:0] I 2 (00, 01, 10, 11) Sets the internal mode of the receive PCS,
either 16, 20, 32, or 40 bit.
RXLOSSOFSYNC[1:0] O 2 Bit 0 is always zero. Bit 1 indicates there is a 64B/66B Block
Lock when deasserted to logic Low.
RXN I 1 Serial differential port (FPGA external)
RXNOTINTABLE[7:0] O 1, 2, 4, 8
(1)
Status of encoded data when the data is not a valid character
when asserted High. Applies to the byte-mapping scheme.
RXP I 1 Serial differential port (FPGA external)
RXPOLARITY I 1 Similar to TXPOLARITY, but for RXN and RXP. When
deasserted, assumes regular polarity. When asserted,
reverses polarity.
Table 1-4: Primitive Ports (Continued)
Port I/O Port Size Definition
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