DS619 (v1.0) September 17, 2007Product Specification
Introduction
The ChipScope™ PLB IBA core is a specialized Bus
Analyzer core designed to debug embedded systems that
contain the IBM CoreConnect™ Processor Local Bus (PLB)
version 4.6. The ChipScope PLB46 IBA core in EDK is
based on a Tcl script that generates an HDL wrapper to the
PLB IBA and calls the ChipScope Core Generator to
generate the netlist based on user parameters.
Features
The ChipScope PLBv46 IBA is a soft IP core designed for
Xilinx® FPGAs and contains the following features:
•Probes the master, slave, arbiter, and error status
signals of the PLBv46 bus
•Probes the PLBv46 OR'ed slave signals
•Automatically adjusts ports to the PLBv46 bus width
•Separates master, slave, and error status signals into
independent match units which can be enabled or
disabled by a design parameter
•Allows independent enabling or disabling of probed
master, slave, and error status signals for data capture
•Supports trigger port customization by a design
parameter
•Supports match unit type customization for each trigger
port by a design parameter
•Supports sample depths from 1024-131,072 on
Virtex™-5 Devices selectable by a design parameter
•Can probe as few as 1 signals and as many as 1115
signals on a Virtex-5 device
•Provides a separate input bus to allow a user-defined
input debug port
•Supports a trigger output indicator pin that can be sent
off chip or to other cores
PowerPC is a trademark of IBM, Inc. All other trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS619 (v1.0) September 17, 2007www.xilinx.comProduct Specification1
P61MU_10PLB_rdPendReqMaster /Slave IPLB pending bus read request indicator
P62MU_10PLB_wrPendReqMaster /Slave IPLB pending bus write request indicator
P63MU_10PLB_reqPri[0:1]Master /Slave IPLB current request priority
PLB Master Signals
P64MU_11M_lockErr[0:
C_PLBV46_NUM_MASTERS-1]
P65MU_11M_rdBurst[0:
C_PLBV46_NUM_MASTERS-1]
P66MU_11M_wrBurst[0:
C_PLBV46_NUM_MASTERS-1]
P67MU_11M_RNW[0:
C_PLBV46_NUM_MASTERS-1]
P68MU_11PLB_MBusy[0:
C_PLBV46_NUM_MASTERS-1]
P69MU_11PLB_MAddrAck[0:
C_PLBV46_NUM_MASTERS-1]
P70MU_11PLB_MRdBTerm[0:
C_PLBV46_NUM_MASTERS-1]
P71MU_11PLB_MRdDAck[0:
C_PLBV46_NUM_MASTERS-1]
P72MU_11PLB_MRearbitrate[0:
C_PLBV46_NUM_MASTERS-1]
P73MU_11PLB_MWrBTerm[0:
C_PLBV46_NUM_MASTERS-1]
P74MU_11PLB_MWrDAck[0:
C_PLBV46_NUM_MASTERS-1]
P75MU_12M_mSize[0:
C_PLBV46_NUM_MASTERS*2-1]
P76MU_12M_size[0:
C_PLBV46_NUM_MASTERS*4-1]
P77MU_12PLB_MSSize[0:
C_PLBV46_NUM_MASTERS*2-1]
P78MU_12M_type[0:
C_PLBV46_NUM_MASTERS*3-1]
P79MU_13M_BE[0: C_PLBV46_NUM_MASTERS*
C_PLBV46_DWIDTH/8-1]
MasterIMaster abort bus request indicator
MasterIMaster lock error indicator
MasterIMaster read burst indicator
MasterIMaster write burst indicator
MasterIMaster read not write
MasterIPLB Master slave busy indicator
MasterIPLB Master Address acknowledge
MasterIPLB Master terminate read burst indicator
MasterIPLB Master read data acknowledge
MasterIPLB Master bus re-arbitrate indicator
MasterIPLB Master terminate write burst indicator
MasterIPLB Master write data acknowledge
MasterIMaster data bus port width
MasterIMaster transfer size
MasterIPLB Master slave data bus width indicator
MasterIMaster transfer type
MasterIMaster byte enables
The IBA_PLBv46 ports listed in Ta bl e 1 connect to the
PLBv46 bus. The core divides related ports into 13 match
unit groups (MUs) as shown in the second column of the
table. Each match unit group can connect to a trigger port of
the IBA. Certain match unit groups, such as MU_1, are
further subdivided to allow more fine control of the signals
attached to a trigger port. For example, PLB_Rst is part of
MU_1A and PLB_MRdErr is part of MU_1B but both will be
combined into MU_1 when enabled.
DS619 (v1.0) September 17, 2007www.xilinx.comProduct Specification4
Every match unit label has a match type and match counter
width parameter. The match unit type describes the type of
compare operation that can be done with the match unit.
The valid values for this type are defined for each match
unit. For instance C_MU_1_TYPE only supports basic and
basic with edges because multiple signals make up this
match unit bus; whereas for C_MU_3_TYPE, all compare
options are available because this match unit has only one
connected signal bus type. The match counter width allows
R
ChipScope PLBv46 IBA (Bus Analyzer) (v1.00a)
a user to look for multiple occurrences of the match event.
This counter width is controllable through the
C_MU_xx_CNT_W parameter (xx is a place holder for
1-13). When this parameter is set to 0 only 1 occurrence is
counted, otherwise the match event count is limited by the
width of this parameter.
The number of match units to use is defined by the
C_MU_xx_NUM parameter. By default if a match unit does
not have the C_MU_xx_NUM parameter then only one
match unit is used for the match group. If the
C_MU_xx_NUM parameter is defined, then one or two
match units are available for this match group. What this
enables is looking at sequences of this particular match
group. For instance in match group 2 you may want a trigger
sequence to first look at PLB_PAValid=1 followed by a rising
edge on PLB_SaddrAck. For this specific trigger the first
match unit is set to look for PLB_PAValid=1 and the second
is set for PLB_SaddrAck=R.
The first match unit is labeled 1a and 1b. The 1a group of
signals makes up the reset and error flag signals. The 1b
group contains master related error signals. The generator
allows adding 1a, 1b or both of these groups to the core via
the generic parameters C_USE_MU_1A, and
C_USE_MU_1B respectively.
The second match unit has labels 2a, 2b, and 2c. The 2a
signals contain 16 of the primitive ports which provide
essential PLB bus transaction information. The 2b signals
contain buses that identify widths and master information of
the active transaction. The 2c label is used for the
transaction attribute bus. The three subdivided match unit
groups can be all or individually enabled using the
parameters C_USE_MU_2A, C_USE_MU_2B, and
C_USE_MU_2C.
The third, fourth, and fifth match units are used for the
address, data write, and data read buses respectively. Each
bus has a dedicated match unit so it can be individually
enabled and defined with unique C_MU_xx_TYPE pattern
match units.
The 6a and 6b match units are used for the slave side
interface. This match unit holds all the control and status
ports of all the slaves on the PLB. Similarly, match units 11,
12 and 13 have all the control and status of all the masters.
Note:
are enabled. You cannot individually enable a particular master.
When these match units are enabled, all slaves or masters
The match units 7, 8, and 9 are slave side signals for BUSY,
READ, and WRITE error controls going to the master.
These units are broken out individually because this bus
has one signal for each master on each slave.
Consequently, you can have up to 256 signals on each one
of these match units (if PLB goes to a 16 slave, 16 master
solution).
The arbiter status signals can be monitored using match
unit 10. The signals probed by this match unit can help
identify the order of the PLB master transactions that are
being sorted on the bus.
ChipScope PLB46 IBA Parameters
To create a ChipScope PLB46 IBA uniquely tailored for your
system and to optimize performance, specific features can
be parameterized on the PLB IBA. Ta bl e 2 describes the
features that can be parameterized.
The ChipScope PLB IBA peripheral supports multiple
trigger units that connect to the PLB Control bus, Address
bus, Data bus, lumped Slave or Master busses. Each one of
these trigger units can be enabled and parameterized
independently. Ta bl e 2 lists all the parameters used in
selecting the trigger port connections. These parameters
define what signals are connected to the trigger ports, the
match unit type, and if the signals are stored in the sample
buffer.
Ta bl e 2 lists the IBA PLBv46 parameterized features.
These parameters control the ports that are attached to the
IBA trigger and storage units. They also are used to
configure the storage and match unit options available for
the different trigger ports.
The IBA ports are subdivided into logical groups call match
units, as shown in Table 1, page 2. Each one of these match
units have a set of parameters which are used to enable and
define the trigger port configuration for a particular set of
PLBv46 signals.
Every match unit group has a match type and match
counter width parameter. The match unit type describes the
type of compare operation that can be done on a match
unit. The valid values for this type are defined for each
match unit. For example, C_MU_1_TYPE only supports
C_MU_13_CNT_W_MSTR_BE 0,1-320Integer
C_MU_13_EN_STORE_
MSTR_BE
0,11Integer
basic and basic with edges since multiple signals make up
this match unit. Alternately, for C_MU_3_TYPE all compare
options are available since this match unit has the complete
PLB_ABus bus connected to it. The match counter width
allows you to look for multiple occurrences of the match
event. This counter width is controllable through the
C_MU_xx_CNT_W parameter (where xx is a place holder
for the MU signal value, 1-13). When this parameter is set to
0, only one occurrence is counted; otherwise, the maximum
match event count is limited by the width of this parameter.
The number of match units is defined by the
C_MU_xx_NUM parameter. By default, if a match unit does
not have the C_MU_xx_NUM parameter, only one match
unit is used for the match unit group. If the C_MU_xx_NUM
parameter is defined, then one or two match units can be
DS619 (v1.0) September 17, 2007www.xilinx.comProduct Specification9
R
ChipScope PLBv46 IBA (Bus Analyzer) (v1.00a)
assigned for this match group. When multiple match units
are available, sequences of a match unit group can be
detected. For example, in MU_2, a trigger sequence could
be created to look for PLB_PAValid=1 followed by a rising
edge on PLB_SaddrAck. For this specific trigger event the
first match unit of MU_2 would be set to PLB_PAValid=1 and
the second to PLB_SaddrAck=R.
Allowable Parameter Combinations
All parameters are independent of each other. Each
parameter must be in the range or exact value listed in the
allowable values of Ta bl e 2 . Certain combinations will
disable the sub-parameters. As an example consider when
C_USE_MU_3 is set to 0. In this case all the
C_MU_3_<XYZ> parameters are ignored because the
match unit group has been disabled.
Depending on the architecture certain parameters may fail
during a design rule check. For instance, if you specify
C_NUM_DATA_SAMPLES to be 32768 for a non-Virtex-5
device, you will get an error message. Also there you must
have a width of at least one signal going to the data sample
storage buffer.
ChipScope PLB46 IBA Module Register
Descriptions
Not applicable.
ChipScope PLB46 IBA Module Interrupt
Descriptions
Not applicable.
Design Implementation
The ChipScope PLB IBA design is implemented in a Tcl
script. When the EDK Platgen tool is run, this Tcl script is
called and it internally calls the ChipScope Pro Core
generator in command line mode providing a generated
argument (.arg) file to create a customized ILA. This ILA is
customized per the IBA settings and is attached to the
PLB46 bus using a custom HDL wrapper.
XST is the synthesis tool used for synthesizing the wrapper
HDL generated for the ChipScope PLB IBA. The EDIF
netlist output from XST and ChipScope Core Generator are
then input to the Xilinx Foundation tool suite for actual
device implementation.
Target Technology
The intended target technology is all Xilinx FPGAs.
Device Utilization and Performance
Benchmarks
The device utilization varies widely based on the parameter
combinations set by the user.
Restrictions
Maximum number of signals that can be stored for
non-Virtex-5 device families is limited to 256 signals. For
Virtex-5 family devices the limit is 1024 signals.
Reference Documents
ChipScope Pro Software and Cores User Guide
ChipScope PLB46 IBA Module Block
Diagram
Chipscope
ICON
mon_plb
PLB Bus
clk
iba_trig_in
Figure 1: ChipScope PLB46 IBA Block Diagram
DS619 (v1.0) September 17, 2007www.xilinx.comProduct Specification10
Chipscope
PLB46_IBA
DS619_02_041707
Revision History
DateVersionRevision
08/02/071.0Initial release
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