Xilinx PCI-X User Manual
R
LogiCORE™ IP
Initiator/Target
v5.1 for PCI-X™
Getting Started Guide
UG158 March 24, 2008
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The following table shows the revision history for this document.
Version Revision
06/01/00 1.0 Initial Xilinx release.
06/15/00 1.1 Accumulated miscellaneous updates and bug fixes.
07/26/00 1.2 Accumulated miscellaneous updates and bug fixes.
08/28/00 1.3 Fine tuning of text frame and paragraph format spacings.
04/11/01 2.0 Revised formats to take advantage of FrameMaker 6.0 book features.
05/02/01 2.1 Master page changes.
07/11/01 2.2 Accumulated miscellaneous updates and bug fixes.
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Version Revision
04/04/02 2.2.1 Updated trademarks page in ug000_title.fm.
06/24/02 3.0 Initial Xilinx release of corporate-wide common template set, used for User Guides,
Tutorials, Release Notes, Manuals, and other lengthy, multiple-chapter documents
created by both CMP and ITP. See related documents for further information.
Descriptions for revisions prior to v3.0 have been abbreviated. For a full summary of revision
changes prior to v3.0, refer to v2.2.1 template set.
10/30/02 3.1 Updated spelling of RocketIO and SelectIO trademarks in ug000_title.fm per 10/09/02
broadcast email announcement. Also updated file version number and date.
12/06/02 3.2 Fixed all instances of old character formats in header/footer in Master pages.
01/20/03 3.3 Revised copyright date in ug000_title.fm to 2003. Changed all instances of “Manual” in
ug000_preface.fm to “Guide.”
02/06/03 3.4 Added paragraph formats GlossBulleted, GlossNumbered, and GlossNumberedCont.
02/25/03 3.4.1 Minor clean-ups and corrections.
03/25/03 3.5 • Corrected Reference Page identification problem that prevented the IX (index)
Reference page from taking control of Index formatting.
• Modified paragraph tags Level1IX through Level3IX (index entries) to provide a
more uniform appearance and enhance clarity.
• Removed <Italic> attribute from Heading2TOC special string on Reference pages.
• Changed autonumbering properties of FigureTitle and TableTitle to remove chapter
number and hyphen.
04/30/03 3.5.1 Updated Additional Resources table in Preface to give correct URL to data sheets index
page instead of to obsolete Programmable Logic Data Book page.
11/11/04 3.5.2 Added installation and licensing chapter; updated to current template.
12/1/04 3.6 Virtex-4 updates; addition of information to Family Specific Considerations, Chapter 3.
3/7/05 3.7 Updated to system 7.1i and build 5.0.95
5/13/05 4.0 Updated to build 5.0.100 and Xilinx tools 7.1i SP2.
8/31/05 5.0 Updated to build 5.0.101 and Xilinx tools 7.1i SP3.
9/12/05 6.0 Updated to build 5.0.102, Xilinx tools 7.1i to SP4, changed release date, removed
instruction to confirm directory structure from Core Licensing chapter.
1/18/06 7.0 Updated build to 5.0.105, Xilinx tools to 8.1i, release date, licensing chapter.
2/14/06 7.5 Advanced build to 108, added SP2 support to ISE v8.1i, updated release date.
7/13/06 8.0 Advanced build to 160, ISE to v8.21, release date
2/15/07 8.1 Advanced build to 161, release date, minor updates
5/17/07 9.0 Changed title and text references to PCI-X and PCI to comply with PCI-SIG trademark
guidelines. Advanced build to 162, support for IUS to v5.7.
8/08/07 9.1 Updated for IP1 Jade Minor release. Changed capacitor value to 10 uF to match XAPP653
recommendation.
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Version Revision
10/10/07 9.5 Updated for IP2 Jade Minor release. Added section regarding configuration pins to
device family chapter.
3/24/08 10.0 Updated tools for IP0K release.
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Table of Contents
Schedule of Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Preface: About This Guide
Guide Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Typographical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Chapter 1: Getting Started
System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
About the Example Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Additional Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Core Interface for PCI-X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Chapter 2: Licensing the Core
Before you Begin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Licensing Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Full System Hardware Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Full License . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Direct Download . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Installing Your License File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Chapter 3: Family Specific Considerations
Design Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Device Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Configuration Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Bus Width Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Bus Mode Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Bus Clock Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Electrical Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Input Delay Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Generating Bitstreams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Chapter 4: Functional Simulation
Cadence IUS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Mentor Graphics ModelSim. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Chapter 5: Synthesizing a Design
Synplicity Synplify. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Exemplar LeonardoSpectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Xilinx XST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Chapter 6: Implementing a Design
ISE Foundation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Chapter 7: Timing Simulation
Cadence IUS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Mentor Graphics ModelSim. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
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Schedule of Figures
Chapter 1: Getting Started
Chapter 2: Licensing the Core
Chapter 3: Family Specific Considerations
Figure 3-1: PCI/PCI-X Output Driver VCCO Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Chapter 4: Functional Simulation
Chapter 5: Synthesizing a Design
Figure 5-1: Create a New Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 5-2: Main Project Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 5-3: Files to Add (Virtex Library) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 5-4: Files to Add (LogiCORE Files). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 5-5: Files to Add (User Application) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 5-6: Source Files in Main Project Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 5-7: Options for Implementation: Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 5-8: Options for Implementation: Options/Constraints. . . . . . . . . . . . . . . . . . . . . 35
Figure 5-9: Create a New Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 5-10: Main Project Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 5-11: Files to Add (Virtex Library) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 5-12: Files to Add (LogiCORE Files). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 5-13: Files to Add (User Application) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 5-14: Main Project Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 5-15: Options for Implementation: Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Chapter 6: Implementing a Design
Chapter 7: Timing Simulation
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About This Guide
The Initiator/Target v5.1 for PCI-X Getting Started Guide provides information about the
LogiCORE™ IP interface core for Peripheral Component Interconnect Extended (PCI-X),
which provides a fully verified, pre-implemented PCI-X bus interface targeting devices
based on the Virtex™ FPGA architecture.
The guide also includes an example design in both Verilog-HDL and VHDL that lets you
simulate, synthesize, and implement the interface to understand the design flow for PCI-X.
Guide Contents
This manual contains the following chapters:
• Chapter 1, “Getting Started,”describes the Initiator/Target core for PCI-X and
provides information about getting technical support, and providing feedback to
Xilinx about the core and the accompanying documentation.
• Chapter 2, “Licensing the Core,” provides instructions for installing and obtaining a
license for the core interface, which you must do before using it in your designs.
• Chapter 3, “Family Specific Considerations,” discusses design considerations specific
to the core interface targeting Virtex devices.
• Chapter 4, “Functional Simulation,” describes the use of supported functional
simulation tools, including Cadence® IUS and Mentor Graphics® ModelSim®.
• Chapter 5, “Synthesizing a Design,” describes the use of supported synthesis tools,
including Synplicity Synplify, Exemplar LeonardoSpectrum, and Xilinx XST.
• Chapter 6, “Implementing a Design,” describes the use of supported FPGA
implementation tools, included with the Xilinx ISE™ Foundation v10.1 software.
• Chapter 7, “Timing Simulation,” describes the use of supported post-route timing
simulation tools, including Cadence IUS and Mentor Graphics ModelSim.
Preface
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Conventions
Typographical
Preface: About This Guide
The following typographical conventions are used in this document:
Convention Meaning or Use Example
Messages, prompts, and
Courier font
program files that the system
displays
speed grade: - 100
Courier bold
angle brackets < >
Italic font
Square brackets [ ]
Braces { }
Vertical bar |
Vertical ellipsis
.
.
.
Literal commands you enter in
a syntactical statement
Variables in a syntax
statement for which you must
supply values
References to other manuals
Emphasis in text
An optional entry or
parameter. However, in bus
specifications, such as
bus[7:0], they are required.
A list of items from which you
must choose one or more
Separates items in a list of
choices
Repetitive material that has
been omitted
ngdbuild design_name
<design_name>
See the Initiator/Target User
Guide for more information.
If a wire is drawn so that it
overlaps the pin of a symbol,
the two nets are not
connected.
ngdbuild [option_name]
design_name
lowpwr ={on|off}
lowpwr ={on|off}
IOB #1: Name = QOUT’
IOB #2: Name = CLKIN’
.
.
.
Horizontal ellipsis . . . Omitted repetitive material
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allow block block_name
loc1 loc2... locn;
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Conventions
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Online Document
The following conventions are used in this document:
Convention Meaning or Use Example
Blue text
Blue, underlined text
Cross-reference link to a
location in the current
document
Hyperlink to a website (URL)
See “Additional Resources”
for details.
See “Title Formats” in Chapter
1 for details.
Go to http://www.xilinx.com
for the latest speed files.
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Preface: About This Guide
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Getting Started
The Initiator/Target core for PCI-X provides a fully verified, pre-implemented PCI-X bus
interface targeted for devices based on the Virtex architecture. This chapter provides
information about the example design, resources for additional documentation, obtaining
technical support, and providing feedback to Xilinx about the core and its documentation.
System Requirements
Windows
• Windows XP® Professional 32-bit/64-bit
• Windows Vista® Business 32-bit/64-bit
Solaris/Linux
Chapter 1
• Red Hat® Enterprise Linux WS v4.0 32-bit/64-bit
• Red Hat® Enterprise Desktop v5.0 32-bit/64-bit
(with Workstation Option)
• SUSE Linux Enterprise (SLE) v10.1 32-bit/64-bit
Software
• ISE™ software v10.1 with applicable service sack
Check the release notes for the required service pack; I
downloaded from www.xilinx.com/xlnx/xil_sw_updates_home.jsp?update=sp
About the Example Design
The example design is a simple user application. It is provided as a training tool and
design flow test. The example design consists of the user application Userapp, and
supporting files for simulation and implementation.
The Userapp example design includes a test bench capable of generating simple read and
write transactions. This stimulation generation capability is used to set up the
configuration space of the design, and then perform some simple transactions. In addition,
a special configuration file is provided with the Userapp design, and the test bench makes
assumptions about the size and number of base address registers used.
You can change the core options related to implementation—options that relate to the
selected FPGA architecture. However, do not change core options that alter the functional
behavior of the core; such change may cause unpredictable results when you simulate the
example design. For custom designs, you have the flexibility to change the core
configuration as described in the Initiator/Target v5.1 for PCI-X User Guide.
SE software service packs can be
.
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Step-by-step instructions using supported design tools are provided in this guide to
simulate, synthesize, and implement the Userapp example design.
Additional Documentation
For more information about the core interface, see the following documents, provided in
the CORE Generator zip file:
•
Initiator/Target v5.1 for PCI-X User Guide
•
Initiator/Target v5.1 Release Notes
Chapter 1: Getting Started
Further information is available in the Mindshare PCI System Architecture
PCI Local Bus Specification, available from the PCI Special Interest Group
Technical Support
For technical support, visit www.xilinx.com/support. Questions are routed to a team of
engineers with expertise using the Initiator/Target core for PCI-X.
Xilinx provides technical support for use of this product as described in the User and
Getting Started Guides for this core. Xilinx cannot guarantee timing, functionality, or
support of this product for designs outside of these guidelines.
Feedback
Xilinx welcomes comments and suggestions about the core interface for PCI-X and the
documentation supplied with the core.
Core Interface for PCI-X
For comments or suggestions about the core interface for PCI-X, please submit a WebCase
from www.xilinx.com/support/clearexpress/websupport.htmt
following information:
• Product name
• Core version number
• Explanation of your comments
text, and the
site.
. Be sure to include the
Document
For comments or suggestions about this document, please submit a WebCase from
www.xilinx.com/support/clearexpress/websupport.htm
following information:
• Document title and number
• Page number(s) to which your comments refer
• Explanation of your comments
14 www.xilinx.com PCI-X v5.1 165 Getting Started Guide
. Be sure to include the
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Licensing the Core
This chapter provides instructions for installing and obtaining a license for the
Initiator/Target core for PCI-X, which you must do before using it in your designs. The
core is provided under the terms of the Xilinx LogiCORE Site License Agreement
conforms to the terms of the SignOnce
License Consortium. Purchase of the core entitles you to technical support and access to
updates for a period of one year.
This chapter assumes that you have installed the core using either the CORE Generator™
IP Softwa re Update ins taller, or by p erf orming a manual installation after downloading the
core from the web. For information about installing the core, see the product lounge at
PCI/PCI-X.
Before you Begin
Chapter 2
, which
IP License standard defined by the Common
Before installing the core, you must have a Xilinx.com account and the ISE 10.1 software
installed on your system.
To create an account, and download ISE software:
1. Click Login at the top of the Xilinx home page
create a support account.
2. Install ISE software v10.1 and the applicable service pack software. ISE service packs
can be downloaded from www.xilinx.com/support/download.htm
Licensing Options
The PCI-X core provides two licensing options, described in this section.
Full System Hardware Evaluation
The Full System Hardware Evaluation license is available at no cost and lets you fully
integrate the core into an FPGA design, place and route the design, evaluate timing, and
perform back-annotated gate-level simulation of the core using the demonstration test
bench provided.
In addition, the license lets you generate a bitstream from the placed and routed design,
which can then be downloaded to a supported device and tested in hardware. The core can
be tested in the target device for a limited time before timing out (ceasing to function) at
which time it can be reactivated by reconfiguring the device.
; then follow the onscreen instructions to
.
You can obtain a Full System Evaluation license for this core by contacting your local Xilinx
FAE to request a Full System Hardware Evaluation license key.
PCI-X v5.1 165 Getting Started Guide www.xilinx.com 15
UG158 March 24, 2008
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