Xilinx PCI32 User Manual

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PCI32 Interface v3.0

DS206 August 31, 2005

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Features

• Fully PCI 3.0-compliant LogiCORE™, 32-bit, 66/33
MHz interface

• Customizable, programmable, single-chip solution

• Pre-defined implementation for predictable timing

• Incorporates Xilinx Smart-IP™ technology

• 3.3V operation at 0-66 MHz

• 5.0V operation at 0-33 MHz

• Fully verified design tested with Xilinx proprietary
testbench and hardware

• Available through the Xilinx CORE Generator™
v7.1i or higher

• CardBus compliant

• Supported initiator functions:

- Configuration read, configuration write

- Memory read, memory write, MRM, MRL

- Interrupt acknowledge, special cycles

- I/O read, I/O write

• Supported target functions:

- Type 0 configuration space header

- Up to three base address registers (MEM or I/O
with adjustable block size from 16 bytes to 2 GB)

- Medium decode speed

- Parity generation, parity error detection

- Configuration read, configuration write

- Memory read, memory write, MRM, MRL

Product Specification v3.0.151

LogiCORE Facts

PCI32 Resource Utilization

Slice Four Input LUTs 553

Slice Flip-Flops 566

IOB Flip-Flops 97

IOBs 50

TBUFs 288

GCLKs 1

Provided with Core

PCI32 Product Specification

Documentation

Design File Formats

Constraints Files

PCI Getting Started Guide

Verilog/VHDL Simulation Model

User Constraints File (UCF)

Example Design Verilog/VHDL Example Design

Design Tool Requirements

Xilinx Tools v7.1i Service Pack 4

Tested Entry and
Verification Tools

Xilinx provides technical support for this LogiCORE product when
used as described in the PCI Getting Started Guide and PCI User
Guide. Xilinx cannot guarantee timing, functionality, or support of
product if implemented in devices not listed, or if customized
beyond that allowed in the product documentation.

(3)

Model Technology ModelSim

Exemplar LeonardoSpectrum

(1)

(2)

PCI User Guide

NGO Netlist

Guide File (NCD)

Synplicity Synplify

Xilinx XST

(4)

Cadence NC-Verilog

- Interrupt acknowledge

- I/O read, I/O write

- Target abort, target retry, target disconnect

© 2005 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective
owners. Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx
makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly
disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from
claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.

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Product Specification v3.0.151

PCI32 Interface v3.0

Fact Table Notes

1. Resource utilization depends on configuration of the interface and user design. Unused resources are trimmed by the Xilinx
technology mapper. The utilization figures reported in this table are representative of a maximum configuration.

2. Designs running at 66 MHz in devices other than Virtex-II, Virtex-II Pro, Virtex-4, Spartan-3, and Spartan-3E require one
GCLKIOB and two GCLKs. Virtex-4 implementations require additional BUFG for 200 MHz reference clock.

3. See the PCI Getting Started Guide or product release notes for current supported versions.

4. XST is a command line option only. See the PCI Getting Started Guide for details.

5. Universal card implementations require two bitstreams.

6. Virtex and Spartan-II not recommended for CardBus.

7. Commercial devices: 0

Table 1: Core Implementation

Virtex™ XCV200-FG256-6C 3.3V only

Virtex-E XCV200E-FG256-6C 3.3V only

Virtex-E XCV400E-FG676-6C 3.3V only

Virtex-4 XC4VLX25-FF668-11C/I
(regional clock based)

Virtex-4 XC4VSX35-FF668-11C/I
(regional clock based)

Virtex-4 XC4VFX20-FF672-11C/I
(regional clock based)

o

C < Tj < 85oC.

Supported Device Power Supply

PCI32/66

(6,7)

(6,7)

(6,7)

3.3V only

3.3V only

3.3V only

PCI32/33

Virtex XCV300-BG432-5C 3.3V, 5.0V only

Virtex XCV1000-FG680-5C 3.3V, 5.0V only

Virtex-E XCV100E-BG352-6C 3.3V only

Virtex-E XCV300E-BG432-6C 3.3V only

Virtex-E XCV1000E-FG680-6C 3.3V only

Virtex-II XC2V1000-FG456-4C/I/M 3.3V only

Virtex-II Pro XC2VP7-FF672-5C/I 3.3V only

Virtex-4 XC4VLX25-FF668-10C/I
(regional clock based)

Virtex-4 4 XC4VSX35-FF668-10C/I
(regional clock based)

Virtex-4 XC4VFX20-FF672-10C/I
(regional clock based)

Virtex-4 XC4VLX25-FF668-10C/I
(global clock based)

Virtex-4 XC4VSX20-FF668-10C/I
(global clock based)

Virtex-4 XC4VFX20-FF672-10C/I
(global clock based)

(6,7)

3.3V only

(6,7)

3.3V only

(6,7)

3.3V only

(6,7)

3.3V only

(6,7)

3.3V only

(6,7)

3.3V only

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Product Specification v3.0.151

Table 1: Core Implementation (Continued)

Supported Device Power Supply

Spartan™-II XC2S30-PQ208-5C 3.3V, 5.0V only

PCI32 Interface v3.0

Spartan-II XC2S50-PQ208-5C

Spartan-II XC2S100-PQ208-5C

Spartan-II XC2S150-PQ208-5C

Spartan-II XC2S200-PQ208-5C

Spartan-IIE 2S50E-PQ208-6C

Spartan-IIE XC2S100E-PQ208-6C

Spartan-IIE XC2S150E-PQ208-6C

Spartan-IIE XC2S200E-PQ208-6C

Spartan-IIE XC2S300E-PQ208-6C

Spartan-3 XC3S1000-FG456-4C/I

Spartan-3E XC3S1200E-FG400-4C/I

(1)

3.3V, 5.0V only

3.3V, 5.0V only

3.3V, 5.0V only

3.3V, 5.0V only

3.3V only

3.3V only

3.3V only

3.3V only

3.3V only

3.3V only

3.3V only

Notes

1. Spartan-3 and Spartan-3E solution pending production speed files.

2. For additional Part/Package combinations, see the UCF Generator in the PCI Lounge.

3. XC2V1000 is supported over Military Temp. range

4. Spartan-3, Spartan-3E, and Virtex-4 devices do not contain TBUFs. The Xilinx tools automatically translate TBUFs to LUTs,
and they are included in the worst case LUT count listed.

5. Virtex-II Pro, Virtex-4, Spartan-3, and Spartan-3E devices are supported over commercial and industrial temperature ranges.

6. As shipped, the core is verified for timing compliance with speedfile versions 1.56 and later. This applies to all production
devices and most engineering samples. If you are using engineering samples that require the 1.54 speedfile, please contact
Xilinx Customer Applications..

7. Requires 200 MHz reference clock.

Applications

• Embedded applications in networking, industrial, and telecommunication systems

• PCI add-in boards such as frame buffers, network adapters, and data acquisition boards

• Hot swap CompactPCI boards

• CardBus compliant

• Any applications that need a PCI interface

General Description

The Xilinx PCI interface is a pre-implemented and fully tested module for Xilinx FPGAs. The pinout for
each device and the relative placement of the internal logic are predefined. Critical paths are controlled
by constraints and guide files to ensure predictable timing. This significantly reduces engineering time
required to implement the PCI portion of your design. Resources can instead be focused on your
unique user application logic in the FPGA and on the system-level design. As a result, Xilinx PCI prod­ucts minimize your product development time.

The core meets the setup, hold, and clock-to-timing requirements as defined in the PCI specification.
The interface is verified through extensive simulation.

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Product Specification v3.0.151

PCI32 Interface v3.0

Other FPGA resources that can be used in conjunction with the core to enable efficient implementation
of a PCI system include:

• Block SelectRAM™ memory. Blocks of on-chip ultra-fast RAM with synchronous write and
dual-port RAM capabilities. Used in PCI designs to implement FIFOs.

• SelectRAM memory. Distributed on-chip ultra-fast RAM with synchronous write option and
dual-port RAM capabilities. Used in PCI designs to implement FIFOs.

• Internal three-state bus capability for data multiplexing.

The interface is carefully optimized for best possible performance and utilization in Xilinx FPGA
devices.

Smart-IP Technology

Drawing on the architectural advantages of Xilinx FPGAs, Xilinx Smart-IP technology ensures the
highest performance, predictability, repeatability, and flexibility in PCI designs. The Smart-IP technol­ogy is incorporated in every PCI interface.

Xilinx Smart-IP technology leverages the Xilinx architectural advantages, such as look-up tables and
segmented routing, as well as floorplanning information, such as logic mapping and location con­straints. This technology provides the best physical layout, predictability, and performance. In addi­tion, these features allow for significantly reduced compile times over competing architectures.

To guarantee the critical setup, hold, minimum clock-to-out, and maximum clock-to-out timing, the
PCI interface is delivered with Smart-IP constraint files that are unique for a device and package com­bination. These constraint files guide the implementation tools so that the critical paths always are
within specification.

Xilinx provides Smart-IP constraint files for many device and package combinations. Constraint files
for unsupported device and package combinations may be generated using the web-based constraint
file generator.

Functional Description

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Product Specification v3.0.151