Xilinx ChipScope PLB46 IBA v1.00a User Manual

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Xilinx ChipScope PLB46 IBA v1.00a User Manual

I

R

ChipScope PLBv46 IBA (Bus Analyzer) (v1.00a)

DS619 (v1.0) September 17, 2007

Product Specification

 

 

Introduction

The ChipScope™ PLB IBA core is a specialized Bus Analyzer core designed to debug embedded systems that contain the IBM CoreConnect™ Processor Local Bus (PLB) version 4.6. The ChipScope PLB46 IBA core in EDK is based on a Tcl script that generates an HDL wrapper to the PLB IBA and calls the ChipScope Core Generator to generate the netlist based on user parameters.

Features

The ChipScope PLBv46 IBA is a soft IP core designed for Xilinx® FPGAs and contains the following features:

Probes the master, slave, arbiter, and error status signals of the PLBv46 bus

Probes the PLBv46 OR'ed slave signals

Automatically adjusts ports to the PLBv46 bus width

Separates master, slave, and error status signals into independent match units which can be enabled or disabled by a design parameter

Allows independent enabling or disabling of probed master, slave, and error status signals for data capture

Supports trigger port customization by a design parameter

Supports match unit type customization for each trigger port by a design parameter

Supports sample depths from 1024-131,072 on Virtex™-5 Devices selectable by a design parameter

Can probe as few as 1 signals and as many as 1115 signals on a Virtex-5 device

Provides a separate input bus to allow a user-defined input debug port

Supports a trigger output indicator pin that can be sent off chip or to other cores

 

LogiCORE™ Facts

 

 

 

 

 

Core Specifics

 

 

 

 

Supported Device

Virtex-E, Virtex, Spartan™-3A DSP,

Family

Spartan-3AN, Spartan-3A, Spartan-3E,

 

Spartan-3, Spartan-IIE, Spartan-II, Virtex-5

 

LX, Virtex-5 LXT Virtex-5 SXT, Virtex-4 FX,

 

Virtex-4 LX, Virtex-4 SX, Virtex-II Pro,

 

Virtex-II, Virtex-II Pro, Virtex-4

 

 

 

 

 

Version of Core

chipscope_plb46_iba

V1.00a

 

 

 

 

 

 

Resources Used

 

 

 

 

 

 

Min

 

Max

 

 

 

 

Slices

 

 

 

 

 

 

 

LUTs

 

 

 

 

 

 

 

FFs

 

 

 

 

 

 

 

Block RAMs

 

 

 

 

 

 

 

 

Provided with Core

 

 

 

 

 

Documentation

Product Specification

 

 

 

 

Design File

VHDL/EDIF

 

Formats

 

 

 

 

 

 

Constraints File

N/A

 

 

 

 

Verification

N/A

 

 

 

 

Instantiation

N/A

 

Template

 

 

 

 

 

 

Reference Designs

None

 

 

 

 

 

Design Tool Requirements

 

 

 

 

 

Xilinx

ISE™ 9.2i or later

 

Implementation

 

 

 

Tools

 

 

 

 

 

 

Verification

ChipScope Pro 9.2i or later

 

 

 

 

Simulation

Not supported in simulation

 

 

 

 

Synthesis

XST

 

 

 

 

 

 

Support

 

Provided by Xilinx, Inc.

© 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. PowerPC is a trademark of IBM, Inc. All other trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS619 (v1.0) September 17, 2007

www.xilinx.com

Product Specification

1

R

ChipScope PLBv46 IBA (Bus Analyzer) (v1.00a)

ChipScope PLB46 IBA I/O Signals

Table 1: IBA_PLBv46 Pin Descriptions

Port

MU

Signal Name

 

Interface

I/O

Description

 

P1

 

CONTROL

 

ICON

I/O

Icon control bus IO

 

 

 

 

 

 

 

 

 

P2

 

PLB_Clk

 

System

I

System Clock

 

 

 

 

 

 

 

 

 

P3

MU_1C

iba_trigin_in

 

GENERIC

I

Generic Trigger Inputs

 

 

 

 

 

 

 

 

 

P4

 

iba_trig_out

 

GENERIC

O

IBA Trigger Output

 

 

 

 

 

 

 

 

 

 

Reset & Error Status

 

 

 

 

 

 

 

 

 

 

 

P5

MU_1A

PLB_Rst

 

System

I

Registered reset output from arbitration

 

 

 

 

 

 

 

logic

 

 

 

 

 

 

 

 

 

P6

MU_1A

Bus_Error_Det

 

System

I

Bus Error Interrupt

 

 

 

 

 

 

 

 

 

P7

MU_1A

PLB_lockErr

 

Slave

I

PLB lock error indicator

 

 

 

 

 

 

 

 

 

P8

MU_1B

PLB_MRdErr[0:

 

Master

I

PLB Master slave read error indicator

 

 

 

C_PLBV46_NUM_MASTERS-1]

 

 

 

 

 

 

 

 

 

 

 

 

 

P9

MU_1B

PLB_MWrErr[0:

 

Master

I

PLB Master slave write error indicator

 

 

 

C_PLBV46_NUM_MASTERS-1]

 

 

 

 

 

 

 

 

 

 

 

 

 

P10

MU_1B

PLB_MIRQ[0:

 

Master

I

Master interrupt request. For each master,

 

 

 

C_PLBV46_NUM_MASTERS-1]

 

 

 

indicates when a slave has encountered an

 

 

 

 

 

 

 

event that is significant to the master

 

 

 

 

 

 

 

 

 

P11

MU_1B

PLB_MTimeout[0:

 

Master

I

PLB address-phase timeout indicator

 

 

 

C_PLBV46_NUM_MASTERS-1]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Common Signals

 

 

 

 

 

 

 

 

 

 

 

P12

MU_2A

PLB_PAValid

 

Slave

I

PLB primary address valid indicator

 

 

 

 

 

 

 

 

 

P13

MU_2A

PLB_SAValid

 

Slave

I

PLB secondary address

 

 

 

 

 

 

 

 

 

P14

MU_2A

PLB_busLock

 

Slave

I

PLB BusLock

 

 

 

 

 

 

 

 

 

P15

MU_2A

PLB_abort

 

Slave

I

PLB abort bus request indicator

 

 

 

 

 

 

 

 

 

P16

MU_2A

PLB_Swait

 

Simulation

I

Output of Sl_wait OR gate

 

 

 

 

 

 

 

 

 

P17

MU_2A

PLB_SaddrAck

 

Simulation

I

Output of Sl_addrAck OR gate

 

 

 

 

 

 

 

 

 

P18

MU_2A

PLB_Srearbitrate

 

Simulation

I

Output of Sl_rearbitrate OR gate

 

 

 

 

 

 

 

 

 

P19

MU_2A

PLB_RNW

 

Slave

I

PLB read not write

 

 

 

 

 

 

 

 

 

P20

MU_2A

PLB_SwrDAck

 

Simulation

I

Output of Sl_wrDAck OR gate

 

 

 

 

 

 

 

 

 

P21

MU_2A

PLB_SwrComp

 

Simulation

I

Output of Sl_wrComp OR gate

 

 

 

 

 

 

 

 

 

P22

MU_2A

PLB_SwrBTerm

 

Simulation

I

Output of Sl_wrBTerm OR gate

 

 

 

 

 

 

 

 

 

P23

MU_2A

PLB_wrBurst

 

Slave

I

PLB burst write transfer indicator

 

 

 

 

 

 

 

 

 

P24

MU_2A

PLB_SrdDAck

 

Simulation

I

Output of Sl_rdDAck OR gate

 

 

 

 

 

 

 

 

 

P25

MU_2A

PLB_SrdComp

 

Simulation

I

Output of Sl_rdComp OR gate

 

 

 

 

 

 

 

 

 

P26

MU_2A

PLB_SrdBTerm

 

Simulation

I

Output of Sl_rdBTerm OR gate

 

 

 

 

 

 

 

 

 

P27

MU_2A

PLB_rdBurst

 

Slave

I

PLB burst read transfer indicator

 

 

 

 

 

 

 

 

 

P28

MU_2B

PLB_size[0:3]

 

Slave

I

PLB Transfer size

 

 

 

 

 

 

 

 

 

P29

MU_2B

PLB_type[0:2]

 

Slave

I

PLB Transfer type

 

 

 

 

 

 

 

 

 

P30

MU_2B

PLB_MSize[0:1]

 

Slave

I

PLB data bus port width indicator.

 

 

 

 

 

 

 

 

 

P31

MU_2B

PLB_Ssize[0:1]

 

Simulation

I

Output of slave Sl_SSize OR gate

 

 

 

 

 

 

 

 

 

P32

MU_2B

PLB_masterID[0:

 

Slave

I

PLB current master identifier

 

 

 

C_PLBV46_MID_WIDTH-1]

 

 

 

 

 

 

 

 

 

 

 

 

 

P33

MU_2B

PLB_BE[0: C_PLBV46_DWIDTH/8-1]

 

Slave

I

PLB byte enables

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DS619 (v1.0) September 17, 2007

www.xilinx.com

 

 

 

Product Specification

 

 

 

2

R

ChipScope PLBv46 IBA (Bus Analyzer) (v1.00a)

Table 1:

IBA_PLBv46 Pin Descriptions (Continued)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Port

MU

Signal Name

 

Interface

 

I/O

Description

 

 

 

 

 

 

 

 

 

 

P34

MU_2C

PLB_TAttribute[0:15]

 

Slave

 

I

PLB Transfer Attribute

 

 

 

 

 

 

 

 

 

 

 

 

 

Address

 

 

 

 

 

 

 

 

 

 

 

 

P35

MU_3A

PLB_ABus[0:31]

 

Slave

 

I

PLB address bus, lower 32 bits

 

 

 

 

 

 

 

 

 

 

P36

MU_3B

PLB_UABus[0:31]

 

Slave

 

I

PLB address bus, upper 32 bits

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Data

 

 

 

 

 

 

 

 

 

 

 

P37

MU_4

PLB_wrDBus[0: C_PLBV46_DWIDTH-1]

Slave

 

I

PLB write data bus

 

 

 

 

 

 

 

 

 

 

P38

MU_5

PLB_SrdDBus[0:

 

Sim

 

I

Output of SL_rdDBus OR gate

 

 

 

C_PLBV46_DWIDTH-1]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Slave

 

 

 

 

 

 

 

 

 

 

 

 

P39

MU_6A

PLB_rdPrim[0:

 

Slave

 

I

PLB secondary to primary read request

 

 

 

C_PLBV46_NUM_SLAVES-1]

 

 

 

 

indicator

 

 

 

 

 

 

 

 

 

 

P40

MU_6A

PLB_wrPrim[0:

 

Slave

 

I

PLB secondary to primary write request

 

 

 

C_PLBV46_NUM_SLAVES-1]

 

 

 

 

indicator

 

 

 

 

 

 

 

 

 

 

P41

MU_6A

Sl_AddrAck[0:

 

Slave

 

I

Slave Address acknowledge

 

 

 

C_PLBV46_NUM_SLAVES-1]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P42

MU_6A

Sl_Rearbitrate[0:

 

Slave

 

I

Slave bus re-arbitrate indicator

 

 

 

C_PLBV46_NUM_SLAVES-1]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P43

MU_6A

Sl_wait[0: C_PLBV46_NUM_SLAVES-1]

Slave

 

I

Slave wait indicator

 

 

 

 

 

 

 

 

 

 

P44

MU_6A

Sl_rdBTerm[0:

 

Slave

 

I

Slave terminate read burst indicator

 

 

 

C_PLBV46_NUM_SLAVES -1]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P45

MU_6A

Sl_rdComp[0:

 

Slave

 

I

Slave read transfer complete indicator

 

 

 

C_PLBV46_NUM_SLAVES -1]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P46

MU_6A

Sl_rdDAck[0:

 

Slave

 

I

Slave read data acknowledge

 

 

 

C_PLBV46_NUM_SLAVES-1]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P47

MU_6A

Sl_wrBTerm[0:

 

Slave

 

I

Slave terminate write burst indicator

 

 

 

C_PLBV46_NUM_SLAVES -1]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P48

MU_6A

Sl_wrComp[0:

 

Slave

 

I

Slave write transfer complete indicator

 

 

 

C_PLBV46_NUM_SLAVES -1]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P49

MU_6A

Sl_wrDAck[0:

 

Slave

 

I

Slave write data acknowledge

 

 

 

C_PLBV46_NUM_SLAVES-1]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P50

MU_6B

Sl_rdWdAddr[0:

 

Slave

 

I

Slave read word address

 

 

 

C_PLBV46_NUM_SLAVES*4-1]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P51

MU_6B

Sl_SSize[0:

 

Slave

 

I

Slave data bus port size indicator

 

 

 

C_PLBV46_NUM_SLAVES*2-1]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P52

MU_7

Sl_MBusy[0: C_PLBV46_NUM_SLAVES

Slave

 

I

Slave busy indicator

 

 

 

*C_PLBV46_NUM_MASTERS-1]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P53

MU_8

Sl_MRdErr[0:

 

Slave

 

I

Slave read error indicator

 

 

 

C_PLBV46_NUM_SLAVES

 

 

 

 

 

 

 

 

*C_PLBV46_NUM_MASTERS-1]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P54

MU_9

Sl_MWrErr[0:

 

Slave

 

I

Slave write error indicator

 

 

 

C_PLBV46_NUM_SLAVES

 

 

 

 

 

 

 

 

*C_PLBV46_NUM_MASTERS-1]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PLB Arbitration Signals

 

 

 

 

 

 

 

 

 

 

 

 

P55

MU_10

M_request[0:

 

Master

 

I

Master bus request

 

 

 

C_PLBV46_NUM_MASTERS-1]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P56

MU_10

M_priority[0:

 

Master

 

I

Master bus request priority

 

 

 

C_PLBV46_NUM_MASTERS*2-1]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P57

MU_10

M_busLock[0:

 

Master

 

I

Master Bus Lock

 

 

 

C_PLBV46_NUM_MASTERS-1]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DS619 (v1.0) September 17, 2007

www.xilinx.com

 

 

 

Product Specification

 

 

 

 

3

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