TB6600HG
TOSHIBA BiCD Integrated Circuit Silicon Monolithic
TB6600HG
PWM Chopper-Type bipolar
Stepping Motor Driver IC
The TB6600HG is a PWM chopper-type single-chip bipolar sinusoidal |
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TB6600HG |
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micro-step stepping motor driver. |
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Forward and reverse rotation control is available |
with 2-phase, |
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1-2-phase, W1-2-phase, 2W1-2-phase, and 4W1-2-phase excitation |
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modes. |
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2-phase bipolar-type stepping motor can be driven by only clock signal |
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with low vibration and high efficiency. |
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Features |
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Single-chip bipolar sinusoidal micro-step stepping motor driver |
HZIP25-P-1.00F |
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• Ron (upper + lower) = 0.4 Ω (typ.) |
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Weight: |
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Forward and reverse rotation control available |
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HZIP25-P-1.00F: 7.7g (typ.) |
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• Selectable phase drive (1/1, 1/2, 1/4, 1/8, and 1/16 step) |
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• Output withstand voltage: Vcc = 50 V |
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• Output current: IOUT = 5.0 A (absolute maximum ratings, peak) |
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IOUT = 4.5 A (operating range, maximal value) |
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Packages: HZIP25-P-1.00F |
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• Built-in input pull-down resistance: 100 kΩ (typ.), (only TQ terminal: 70Ω(typ.))
•Output monitor pins (ALERT): Maximum of IALERT = 1 mA
•Output monitor pins (MO): Maximum of IMO = 1 mA
•Equipped with reset and enable pins
•Stand by function
•Single power supply
•Built-in thermal shutdown (TSD) circuit
•Built-in under voltage lock out (UVLO) circuit
•Built-in over-current detection (ISD) circuit
1 |
2014-01-30 |
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TB6600HG |
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Pin Functions |
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Pin No. |
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I/O |
Symbol |
Functional Description |
Remark |
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1 |
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Output |
ALERT |
TSD / ISD monitor pin |
Pull-up by external resistance |
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2 |
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SGND |
Signal ground |
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3 |
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Input |
TQ |
Torque (output current) setting input pin |
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4 |
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Input |
Latch/Auto |
Select a return type for TSD. |
L: Latch, H: Automatic return |
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5 |
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Input |
Vref |
Voltage input for 100% current level |
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6 |
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Input |
Vcc |
Power supply |
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7 |
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Input |
M1 |
Excitation mode setting input pin |
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8 |
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Input |
M2 |
Excitation mode setting input pin |
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9 |
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Input |
M3 |
Excitation mode setting input pin |
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10 |
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Output |
OUT2B |
B channel output 2 |
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11 |
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― |
NFB |
B channel output current detection pin |
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12 |
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Output |
OUT1B |
B channel output 1 |
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13 |
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― |
PGNDB |
Power ground |
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14 |
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Output |
OUT2A |
A channel output 2 |
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15 |
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― |
NFA |
A channel output current detection pin |
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16 |
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Output |
OUT1A |
A channel output 1 |
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17 |
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― |
PGNDA |
Power ground |
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18 |
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Input |
ENABLE |
Enable signal input pin |
H: Enable, L: All outputs off |
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19 |
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Input |
RESET |
Reset signal input pin |
L: Initial mode |
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20 |
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Input |
Vcc |
Power supply |
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21 |
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Input |
CLK |
CLK pulse input pin |
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22 |
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Input |
CW/CCW |
Forward/reverse control pin |
L: CW, H:CCW |
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23 |
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― |
OSC |
Resistor connection pin for internal oscillation setting |
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24 |
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Output |
Vreg |
Control side connection pin for power capacitor |
Connecting capacitor to |
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SGND |
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25 |
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Output |
MO |
Electrical angle monitor pin |
Pull-up by external resistance |
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<Terminal circuits>
Input pins |
Input pins |
(M1, M2, M3,CLK, CW/CCW, |
(TQ) |
ENABLE, RESET, Latch/Auto) |
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VDD |
10kΩ |
10kΩ |
100kΩ |
70kΩ |
2 |
2014-01-30 |
TB6600HG
Pin Assignment
Top View
SGND |
Latch/Auto |
Vcc |
M2 |
OUT2B |
OUT1B |
OUT2A |
OUT1A |
ENABLE |
Vcc |
CW/CCW |
Vreg |
2 |
4 |
6 |
8 |
10 |
12 |
14 |
16 |
18 |
20 |
22 |
24 |
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1 |
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5 |
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7 |
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9 |
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11 |
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15 |
17 |
19 |
21 |
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25 |
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ALERT |
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TQ |
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Vref |
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M1 |
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M3 |
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NFB |
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PGNDB |
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NFA |
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PGNDA |
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RESET |
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CLK |
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OSC |
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MO |
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3 |
2014-01-30 |
TB6600HG
Block Diagram
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Vreg |
MO |
ALERT |
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Vcc |
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24 |
25 |
1 |
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6, 20 |
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M1 |
7 |
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Reg(5V) |
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OUT1A |
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16 |
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Pre |
H-Bridge |
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M2 |
8 |
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-drive |
driver A |
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9 |
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14 |
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M3 |
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OUT2A |
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CW/CCW |
22 |
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TSD / ISD / UVLO |
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15 |
NFA |
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Input |
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CLK |
21 |
circuit |
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Current selector |
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circuit A |
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RESET |
19 |
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ENABLE |
18 |
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12 |
OUT1B |
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Pre |
H-Bridge |
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Latch/Auto |
4 |
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-drive |
driver B |
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10 |
OUT2B |
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OSC |
23 |
OSC |
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NFB |
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Current selector |
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11 |
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circuit B |
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1/3 |
100%/30% |
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Vref |
5 |
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3 |
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2 |
17 |
13 |
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TQ |
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SGND |
PGNDA |
PGNDB |
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Setting of Vref
Input |
Voltage ratio |
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TQ |
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L |
30% |
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H |
100% |
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4 |
2014-01-30 |
TB6600HG
Description of Functions
1. Excitation Settings
The excitation mode can be selected from the following eight modes using the M1, M2 and M3 inputs. New excitation mode starts from the initial mode when M1, M2, or M3 inputs are shifted during motor operation. In this case, output current waveform may not continue.
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Mode |
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M1 |
M2 |
M3 |
(Excitation) |
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L |
L |
L |
Standby mode |
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(Operation of the internal circuit is almost turned off.) |
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L |
L |
H |
1/1 (2-phase excitation, full-step) |
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L |
H |
L |
1/2A type (1-2 phase excitation A type) |
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( 0%, 71%, 100% ) |
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L |
H |
H |
1/2B type (1-2 phase excitation B type) |
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( 0%, 100% ) |
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H |
L |
L |
1/4 (W1-2 phase excitation) |
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H |
L |
H |
1/8 (2W1-2 phase excitation) |
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H |
H |
L |
1/16 (4W1-2 phase excitation) |
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H |
H |
H |
Standby mode |
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(Operation of the internal circuit is almost turned off.) |
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Note: To change the exciting mode by changing M1, M2, and M3, make sure not to set M1 = M2 = M3 = L or M1 = M2 = M3 = H.
Standby mode
The operation mode moves to the standby mode under the condition M1 = M2 = M3 = L or M1 = M2 = M3 = H.
The power consumption is minimized by turning off all the operations except protecting operation. In standby mode, output terminal MO is HZ.
Standby mode is released by changing the state of M1=M2=M3=L and M1=M2=M3=H to other state. Input signal is not accepted for about 200 μs after releasing the standby mode.
5 |
2014-01-30 |
TB6600HG
2. Function
(1)To turn on the output, configure the ENABLE pin high. To turn off the output, configure the ENABLE pin low.
(2)The output changes to the Initial mode shown in the table below when the ENABLE signal goes High level and the RESET signal goes Low level. (In this mode, the status of the CLK and CW/CCW pins are irrelevant.)
(3)As shown in the below figure of Example 1, when the ENABLE signal goes Low level, it sets an OFF on the output. In this mode, the output changes to the initial mode when the RESET signal goes Low level. Under this condition, the initial mode is output by setting the ENABLE signal High level. And the motor operates from the initial mode by setting the RESET signal High level.
(Example 1)
1
CLK
RESET
ENABLE
Internal current set
Output current(*)(phase A ) (A )
Z
(*: Output current starts rising at the timing of PWM frequency just after ENABLE pin outputs high.)
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Command of the standby has a higher priority |
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Input |
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Output mode |
than ENABLE. Standby mode can be turned on |
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CLK |
CW/CCW |
RESET |
ENABLE |
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and off regardless of the state of ENABLE. |
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L |
H |
H |
CW |
X: |
Don’t Care |
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H |
H |
H |
CCW |
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X |
X |
L |
H |
Initial mode |
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X |
X |
X |
L |
Z |
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6 |
2014-01-30 |
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TB6600HG |
3. Initial Mode |
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When RESET is used, the phase currents are as follows. |
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Excitation Mode |
Phase A Current |
Phase B Current |
1/1 (2-phase excitation, full-step) |
100% |
-100% |
1/2A type (1-2 phase excitation A type) (0%, 71%, 100%) |
100% |
0% |
1/2B type (1-2 phase excitation B type) (0%, 100%) |
100% |
0% |
1/4 (W1-2 phase excitation) |
100% |
0% |
1/8 (2W1-2 phase excitation) |
100% |
0% |
1/16 (4W1-2 phase excitation) |
100% |
0% |
current direction is defined as follows. OUT1A → OUT2A: Forward direction OUT1B → OUT2B: Forward direction
4. 100% current settings (Current value)
100% current value is determined by Vref inputted from external part and the external resistance for detecting output current. Vref is doubled 1/3 inside IC.
Io (100%) = (1/3 × Vref) ÷ RNF
The average current is lower than the calculated value because this IC has the method of peak current detection.
Pleas use the IC under the conditions as follows; 0.11Ω ≤ RNF ≤ 0.5Ω, 0.3V ≤ Vref ≤ 1.95V
5.OSC
Triangle wave is generated internally by CR oscillation by connecting external resistor to OSC terminal. Rosc should be from 30kΩ to 120kΩ. The relation of Rosc and fchop is shown in below table and figure. The values of fchop of the below table are design guarantee values. They are not tested for pre-shipment.
Rosc(kΩ) |
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fchop(kHz) |
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Min |
Typ. |
Max |
30 |
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60 |
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51 |
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40 |
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120 |
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20 |
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7 |
2014-01-30 |
TB6600HG
6. Decay Mode
It takes approximately five OSCM cycles for charging-discharging a current in PWM mode. The 40% fast decay mode is created by inducing decay during the last two cycles in Fast Decay mode.
The ratio 40% of the fast decay mode is always fixed.
The relation between the master clock frequency (fMCLK), the OSCM frequency (fOSCM) and the PWM frequency (fchop) is shown as follows:
fOSCM = 1/20 ×fMCLK fchop = 1/100 ×fMCLK
When Rosc=51kΩ, the master clock=4MHz, OSCM=200kHz, the frequency of PWM(fchop)=40kHz.
6-1. Current Waveform and Mixed Decay Mode settings
The period of PWM operation is equal to five periods of OSCM. The ratio 40% of the fast decay mode is always fixed.
The “NF” refers to the point at which the output current reaches its predefined current level.
MDT means the point of MDT (MIXED DECAY TIMMING) in the below diagram.
fchop
OSCM
Internal Waveform
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Predefined Current Level |
40% |
NF |
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fast |
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Decay |
MDT |
Mode |
Charge mode → NF: Predefined current level → Slow mode → MDT(Mixed decay timing) → Fast mode → Current monitoring → (When predefined current level Output current) Charge mode
8 |
2014-01-30 |
TB6600HG
6-2. Effect of Decay Mode
•Increasing the current (sine wave)
Predefined |
Slow |
Slow |
Current Level |
Fast |
Fast |
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Charge |
Predefined |
Slow |
Slow |
Charge |
Current Level |
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Fast |
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Fast |
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Charge |
Charge |
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•Decreasing the current (In case the current is decreased to the predefined value in a short time because it decays quickly.)
Predefined |
Slow |
Slow |
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Current Level |
Fast |
Fast |
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Charge |
Charge |
Slow |
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Predefined |
Slow |
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Current Level |
Fast |
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Fast |
|
|
|
Charge |
||
|
|
|
|
|
Charge
Even if the output current rises above the predefined current at the RNF point, the current control mode is briefly switched to Charge mode for current sensing.
•Decreasing the current (In case it takes a long time to decrease the current to the predefined value because the current decays slowly.)
Predefined |
Slow |
Slow |
|
Current Level |
Fast |
Fast |
|
|
Slow |
||
|
Charge |
|
|
|
|
Fast |
|
|
|
|
|
|
|
|
Slow |
|
|
Predefined |
Fast |
|
|
|
|
|
|
Current Level |
|
Charge Charge
Even if the output current rises above the predefined current at the RNF point, the current control mode is briefly switched to Charge mode for current sensing.
During Mixed Decay and Fast Decay modes, if the predefined current level is less than the output current at the RNF (current monitoring point), the Charge mode in the next chopping cycle will disappear (though the current control mode is briefly switched to Charge mode in actual operations for current sensing) and the current is controlled in Slow and Fast Decay modes (mode switching from Slow Decay mode to Fast Decay mode at the MDT point).
Note: The above figures are rough illustration of the output current. In actual current waveforms, transient response curves can be observed.
9 |
2014-01-30 |
TB6600HG
6-3. Current Waveforms in Mixed Decay Mode
|
fchop |
fchop |
OSCM |
|
|
Internal |
|
|
waveform |
|
|
IOUT |
|
Predefined Current Level |
|
NF |
|
|
|
|
Predefined |
|
|
Current Level |
NF |
|
|
|
|
40% |
|
|
Fast |
|
|
DECAY |
|
|
MODE |
|
|
MDT (MIXED DECAY TIMMING) points
• When the NF points come after Mixed Decay Timing points
Switches to Fast mode after Charge mode
|
fchop |
fchop |
|
|
Predefined |
|
|
Current Level |
IOUT |
|
NF |
|
|
MDT (MIXED DECAY TIMMING) points |
Predefined |
NF |
|
|
|
|
Current Level |
|
|
40% |
|
|
Fast |
|
|
DECAY |
|
|
MODE |
|
|
CLK signal input
•When the output current value > predefined current level in Mixed Decay mode
|
fchop |
fchop |
fchop |
Predefined |
|
|
|
Current |
NF |
|
|
Level |
|
|
|
|
|
|
|
IOUT |
|
|
|
|
|
NF |
|
|
|
Predefined Current |
|
|
|
Level |
|
40% |
|
|
|
Fast |
|
|
|
DECAY |
|
MDT (MIXED DECAY TIMMING) points |
|
MODE |
|
|
|
CLK signal input
Even if the output current rises above the predefined current at the RNF point, the current control mode is briefly switched to Charge mode for current sensing.
10 |
2014-01-30 |
TB6600HG
Output Stage Transistor Operation Mode
|
Vcc |
U1 |
|
ON |
Note |
OUT1 |
Load OUT2 |
OFF |
|
L1 |
|
RNF |
|
|
PGND |
Charge Mode |
|
Vcc
U2 |
U1 |
|
U2 |
OFF |
OFF |
Note |
OFF |
|
OUT1 |
Load OUT2 |
|
ON |
ON |
|
L2 |
L2 |
L1 |
|
ON |
|
RNF |
|
|
|
|
PGND |
|
|
|
Slow Mode |
|
|
Vcc |
|
U1 |
|
U2 |
OFF |
Note |
ON |
|
OUT1 Load |
OUT2 |
L1 |
|
L2 |
ON |
|
OFF |
RNF
PGND
Fast Mode
Output Stage Transistor Operation Functions
CLK |
U1 |
U2 |
L1 |
L2 |
|
|
|
|
|
CHARGE |
ON |
OFF |
OFF |
ON |
|
|
|
|
|
SLOW |
OFF |
OFF |
ON |
ON |
|
|
|
|
|
FAST |
OFF |
ON |
ON |
OFF |
|
|
|
|
|
Note: The above chart shows an example of when the current flows as indicated by the arrows in the above figures. If the current flows in the opposite direction, refer to the following chart:
CLK |
U1 |
U2 |
L1 |
L2 |
|
|
|
|
|
CHARGE |
OFF |
ON |
ON |
OFF |
|
|
|
|
|
SLOW |
OFF |
OFF |
ON |
ON |
|
|
|
|
|
FAST |
ON |
OFF |
OFF |
ON |
|
|
|
|
|
Upon transitions of above-mentioned functions, a dead time of about 300 ns (Design guarantee value) is inserted respectively.
11 |
2014-01-30 |
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